diff --git a/VAX/vax630_defs.h b/VAX/vax630_defs.h
index 401d0d42..d95957f6 100644
--- a/VAX/vax630_defs.h
+++ b/VAX/vax630_defs.h
@@ -91,7 +91,7 @@
/* CPU */
-#define CPU_MODEL_MODIFIERS { MTAB_XTD|MTAB_VDV, 0, "MODEL", "MODEL={MicroVAX|VAXStation}", \
+#define CPU_MODEL_MODIFIERS { MTAB_XTD|MTAB_VDV, 0, "MODEL", "MODEL={MicroVAX|VAXStation|VAXStationGPX}", \
&cpu_set_model, &cpu_show_model, NULL, "Set/Show the simulator CPU Model" }, \
{ MTAB_XTD|MTAB_VDV, 0, "DIAG", "DIAG={FULL|MIN}", \
&sysd_set_diag, &sysd_show_diag, NULL, "Set/Show boot rom diagnostic mode" }, \
@@ -136,8 +136,10 @@ extern t_stat cpu_show_memory (FILE* st, UNIT* uptr, int32 val, CONST void* desc
#define ROMSIZE (1u << ROMAWIDTH) /* ROM length */
#define ROMAMASK (ROMSIZE - 1) /* ROM addr mask */
#define ROMBASE 0x20040000 /* ROM base */
-#define ADDR_IS_ROM(x) ((((uint32) (x)) >= ROMBASE) && \
- (((uint32) (x)) < (ROMBASE + ROMSIZE + ROMSIZE)))
+#define ADDR_IS_ROM(x) (((((uint32) (x)) >= ROMBASE) && \
+ (((uint32) (x)) < (ROMBASE + ROMSIZE + ROMSIZE))) || \
+ ((((uint32) (x)) >= QDMBASE) && \
+ (((uint32) (x)) < (QDMBASE + QDMSIZE + QDMSIZE))))
/* KA630 board registers */
@@ -178,6 +180,13 @@ extern t_stat cpu_show_memory (FILE* st, UNIT* uptr, int32 val, CONST void* desc
#define QVMAMASK (QVMSIZE - 1) /* QVSS mem addr mask */
#define QVMBASE 0x303C0000 /* QVSS mem base */
+/* QDSS memory space */
+
+#define QDMAWIDTH 16 /* QDSS mem addr width */
+#define QDMSIZE (1u << QDMAWIDTH) /* QDSS mem length */
+#define QDMAMASK (QDMSIZE - 1) /* QDSS mem addr mask */
+#define QDMBASE 0x303F0000 /* QDSS mem base */
+
/* Other address spaces */
#define ADDR_IS_CDG(x) (0)
diff --git a/VAX/vax630_io.c b/VAX/vax630_io.c
index 879b9b76..2b93aa77 100644
--- a/VAX/vax630_io.c
+++ b/VAX/vax630_io.c
@@ -74,6 +74,7 @@ int32 qb_map[QBNMAPR] = { 0 }; /* map registers */
int32 autcon_enb = 1; /* autoconfig enable */
extern int32 ka_mser; /* KA630 mem sys err */
+extern int32 sys_model;
t_stat dbl_rd (int32 *data, int32 addr, int32 access);
t_stat dbl_wr (int32 data, int32 addr, int32 access);
@@ -90,6 +91,11 @@ t_stat qba_show_virt (FILE *of, UNIT *uptr, int32 val, CONST void *desc);
t_stat qba_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr);
const char *qba_description (DEVICE *dptr);
+extern int32 va_mem_rd (int32 pa);
+extern void va_mem_wr (int32 pa, int32 val, int32 lnt);
+extern int32 vc_mem_rd (int32 pa);
+extern void vc_mem_wr (int32 pa, int32 val, int32 lnt);
+
/* Qbus adapter data structures
qba_dev QBA device descriptor
@@ -460,8 +466,18 @@ int32 qbmem_rd (int32 pa)
int32 qa = pa & QBMAMASK; /* Qbus addr */
uint32 ma;
+#if !defined(VAX_620)
+if (sys_model == 1) { /* VAXstation II? */
+ if ((pa >= QVMBASE) && (pa < QVMBASE+QVMSIZE))
+ return vc_mem_rd (pa); /* read QVSS */
+ }
+else if (sys_model == 2) { /* VAXstation II/GPX? */
+ if ((pa >= QDMBASE) && (pa < QDMBASE+QDMSIZE))
+ return va_mem_rd (pa); /* read QDSS */
+ }
+#endif
if (qba_map_addr (qa, &ma)) { /* map addr */
- return M[ma >> 2];
+ return ReadW (ma);
}
MACH_CHECK (MCHK_READ); /* err? mcheck */
return 0;
@@ -472,6 +488,18 @@ void qbmem_wr (int32 pa, int32 val, int32 lnt)
int32 qa = pa & QBMAMASK; /* Qbus addr */
uint32 ma;
+#if !defined(VAX_620)
+if (sys_model == 1) { /* VAXstation II? */
+ if ((pa >= QVMBASE) && (pa < QVMBASE+QVMSIZE))
+ vc_mem_wr (pa, val, lnt); /* write QVSS */
+ return;
+ }
+else if (sys_model == 2) { /* VAXstation II/GPX? */
+ if ((pa >= QDMBASE) && (pa < QDMBASE+QDMSIZE))
+ va_mem_wr (pa, val, lnt); /* write QDSS */
+ return;
+ }
+#endif
if (qba_map_addr (qa, &ma)) { /* map addr */
if (lnt < L_LONG) {
int32 sc = (pa & 3) << 3;
@@ -479,7 +507,7 @@ if (qba_map_addr (qa, &ma)) { /* map addr */
int32 t = M[ma >> 2];
val = ((val & mask) << sc) | (t & ~(mask << sc));
}
- M[ma >> 2] = val;
+ WriteW (ma, val);
}
else mem_err = 1;
return;
diff --git a/VAX/vax630_sysdev.c b/VAX/vax630_sysdev.c
index 3d16a1ac..ddf72039 100644
--- a/VAX/vax630_sysdev.c
+++ b/VAX/vax630_sysdev.c
@@ -123,7 +123,7 @@ CTAB vax630_cmd[] = {
extern UNIT clk_unit;
extern int32 tmr_poll;
-extern DEVICE vc_dev, lk_dev, vs_dev;
+extern DEVICE va_dev, vc_dev, lk_dev, vs_dev;
uint32 *rom = NULL; /* boot ROM */
uint8 *nvr = NULL; /* non-volatile mem */
@@ -165,8 +165,6 @@ extern int32 qbmap_rd (int32 pa);
extern void qbmap_wr (int32 pa, int32 val, int32 lnt);
extern int32 qbmem_rd (int32 pa);
extern void qbmem_wr (int32 pa, int32 val, int32 lnt);
-extern int32 vc_mem_rd (int32 pa);
-extern void vc_mem_wr (int32 pa, int32 val, int32 lnt);
extern int32 wtc_rd (int32 pa);
extern void wtc_wr (int32 pa, int32 val, int32 lnt);
extern void wtc_set_valid (void);
@@ -696,17 +694,15 @@ struct reglink { /* register linkage */
uint32 high; /* high addr */
int32 (*read)(int32 pa); /* read routine */
void (*write)(int32 pa, int32 val, int32 lnt); /* write routine */
+ int32 width; /* data path width */
};
struct reglink regtable[] = {
- { QBMAPBASE, QBMAPBASE+QBMAPSIZE, &qbmap_rd, &qbmap_wr },
- { ROMBASE, ROMBASE+ROMSIZE+ROMSIZE, &rom_rd, NULL },
- { NVRBASE, NVRBASE+NVRASIZE, &nvr_rd, &nvr_wr },
- { KABASE, KABASE+KASIZE, &ka_rd, &ka_wr },
-#if !defined(VAX_620)
- { QVMBASE, QVMBASE+QVMSIZE, &vc_mem_rd, &vc_mem_wr },
-#endif
- { QBMBASE, QBMBASE+QBMSIZE, &qbmem_rd, &qbmem_wr },
+ { QBMAPBASE, QBMAPBASE+QBMAPSIZE, &qbmap_rd, &qbmap_wr, L_LONG },
+ { ROMBASE, ROMBASE+ROMSIZE+ROMSIZE, &rom_rd, NULL, L_LONG },
+ { NVRBASE, NVRBASE+NVRASIZE, &nvr_rd, &nvr_wr, L_LONG },
+ { KABASE, KABASE+KASIZE, &ka_rd, &ka_wr, L_LONG },
+ { QBMBASE, QBMBASE+QBMSIZE, &qbmem_rd, &qbmem_wr, L_WORD },
{ 0, 0, NULL, NULL }
};
@@ -722,10 +718,18 @@ struct reglink regtable[] = {
int32 ReadReg (uint32 pa, int32 lnt)
{
struct reglink *p;
+int32 val;
for (p = ®table[0]; p->low != 0; p++) {
- if ((pa >= p->low) && (pa < p->high) && p->read)
- return p->read (pa);
+ if ((pa >= p->low) && (pa < p->high) && p->read) {
+ val = p->read (pa);
+ if (p->width < L_LONG) {
+ if (lnt < L_LONG)
+ val = val << ((pa & 2)? 16: 0);
+ else val = (p->read (pa + 2) << 16) | val;
+ }
+ return val;
+ }
}
MACH_CHECK (MCHK_READ);
@@ -742,9 +746,27 @@ MACH_CHECK (MCHK_READ);
int32 ReadRegU (uint32 pa, int32 lnt)
{
-if (lnt == L_BYTE)
- return ReadReg (pa & ~03, L_LONG);
-return (ReadReg (pa & ~03, L_WORD) & WMASK) | (ReadReg ((pa & ~03) + 2, L_WORD) & (WMASK << 16));
+struct reglink *p;
+int32 val;
+
+for (p = ®table[0]; p->low != 0; p++) {
+ if ((pa >= p->low) && (pa < p->high) && p->read) {
+ if (p->width < L_LONG) {
+ val = p->read (pa);
+ if ((lnt + (pa & 1)) <= 2)
+ val = val << ((pa & 2)? 16: 0);
+ else val = (p->read (pa + 2) << 16) | val;
+ }
+ else {
+ if (lnt == L_BYTE)
+ val = p->read (pa & ~03);
+ else val = (p->read (pa & ~03) & WMASK) | (p->read ((pa & ~03) + 2) & (WMASK << 16));
+ }
+ return val;
+ }
+ }
+
+MACH_CHECK (MCHK_READ);
}
/* WriteReg - write register space
@@ -763,7 +785,11 @@ struct reglink *p;
for (p = ®table[0]; p->low != 0; p++) {
if ((pa >= p->low) && (pa < p->high) && p->write) {
- p->write (pa, val, lnt);
+ if (lnt > p->width) {
+ p->write (pa, val & WMASK, L_WORD);
+ p->write (pa + 2, (val >> 16) & WMASK, L_WORD);
+ }
+ else p->write (pa, val, lnt);
return;
}
}
@@ -783,12 +809,48 @@ MACH_CHECK (MCHK_WRITE);
void WriteRegU (uint32 pa, int32 val, int32 lnt)
{
-int32 sc = (pa & 03) << 3;
-int32 dat = ReadReg (pa & ~03, L_LONG);
+struct reglink *p;
-dat = (dat & ~(insert[lnt] << sc)) | ((val & insert[lnt]) << sc);
-WriteReg (pa & ~03, dat, L_LONG);
-return;
+for (p = ®table[0]; p->low != 0; p++) {
+ if ((pa >= p->low) && (pa < p->high) && p->write) {
+ if (p->width < L_LONG) {
+ switch (lnt) {
+ case L_BYTE: /* byte */
+ p->write (pa, val & BMASK, L_BYTE);
+ break;
+
+ case L_WORD: /* word */
+ if (pa & 1) { /* odd addr? */
+ p->write (pa, val & BMASK, L_BYTE);
+ p->write (pa + 1, (val >> 8) & BMASK, L_BYTE);
+ }
+ else p->write (pa, val & WMASK, L_WORD);
+ break;
+
+ case 3: /* tribyte */
+ if (pa & 1) { /* odd addr? */
+ p->write (pa, val & BMASK, L_BYTE); /* byte then word */
+ p->write (pa + 1, (val >> 8) & WMASK, L_WORD);
+ }
+ else { /* even */
+ p->write (pa, val & WMASK, WRITE); /* word then byte */
+ p->write (pa + 2, (val >> 16) & BMASK, L_BYTE);
+ }
+ break;
+ }
+ }
+ else if (p->read) {
+ int32 sc = (pa & 03) << 3;
+ int32 dat = p->read (pa & ~03);
+
+ dat = (dat & ~(insert[lnt] << sc)) | ((val & insert[lnt]) << sc);
+ p->write (pa & ~03, dat, L_LONG);
+ }
+ return;
+ }
+ }
+
+MACH_CHECK (MCHK_WRITE);
}
/* KA630 registers */
@@ -1012,6 +1074,7 @@ if (MATCH_CMD(gbuf, "MICROVAX") == 0) {
sys_model = 0;
#if defined(USE_SIM_VIDEO) && defined(HAVE_LIBSDL)
vc_dev.flags = vc_dev.flags | DEV_DIS; /* disable QVSS */
+ va_dev.flags = va_dev.flags | DEV_DIS; /* disable QDSS */
lk_dev.flags = lk_dev.flags | DEV_DIS; /* disable keyboard */
vs_dev.flags = vs_dev.flags | DEV_DIS; /* disable mouse */
#endif
@@ -1022,6 +1085,7 @@ else if (MATCH_CMD(gbuf, "VAXSTATION") == 0) {
#if defined(USE_SIM_VIDEO) && defined(HAVE_LIBSDL)
sys_model = 1;
vc_dev.flags = vc_dev.flags & ~DEV_DIS; /* enable QVSS */
+ va_dev.flags = va_dev.flags | DEV_DIS; /* disable QDSS */
lk_dev.flags = lk_dev.flags & ~DEV_DIS; /* enable keyboard */
vs_dev.flags = vs_dev.flags & ~DEV_DIS; /* enable mouse */
strcpy (sim_name, "VAXStation II (KA630)");
@@ -1030,6 +1094,19 @@ else if (MATCH_CMD(gbuf, "VAXSTATION") == 0) {
return sim_messagef(SCPE_ARG, "Simulator built without Graphic Device Support\n");
#endif
}
+else if (MATCH_CMD(gbuf, "VAXSTATIONGPX") == 0) {
+#if defined(USE_SIM_VIDEO) && defined(HAVE_LIBSDL)
+ sys_model = 2;
+ vc_dev.flags = vc_dev.flags | DEV_DIS; /* disable QVSS */
+ va_dev.flags = va_dev.flags & ~DEV_DIS; /* enable QDSS */
+ lk_dev.flags = lk_dev.flags & ~DEV_DIS; /* enable keyboard */
+ vs_dev.flags = vs_dev.flags & ~DEV_DIS; /* enable mouse */
+ strcpy (sim_name, "VAXStation II/GPX (KA630)");
+ reset_all (0); /* reset everything */
+#else
+ return sim_messagef(SCPE_ARG, "Simulator built without Graphic Device Support");
+#endif
+ }
else
return SCPE_ARG;
return SCPE_OK;
@@ -1040,7 +1117,17 @@ t_stat cpu_print_model (FILE *st)
#if defined(VAX_620)
fprintf (st, "rtVAX 1000");
#else
-fprintf (st, (sys_model ? "VAXstation II" : "MicroVAX II"));
+switch (sys_model) {
+ case 0:
+ fprintf (st, "MicroVAX II");
+ break;
+ case 1:
+ fprintf (st, "VAXstation II");
+ break;
+ case 2:
+ fprintf (st, "VAXstation II/GPX");
+ break;
+ }
#endif
return SCPE_OK;
}
diff --git a/VAX/vax630_syslist.c b/VAX/vax630_syslist.c
index f7af8eb6..581fc7a8 100644
--- a/VAX/vax630_syslist.c
+++ b/VAX/vax630_syslist.c
@@ -66,6 +66,7 @@ extern DEVICE tq_dev;
extern DEVICE dz_dev;
extern DEVICE xq_dev, xqb_dev;
extern DEVICE vh_dev;
+extern DEVICE va_dev;
extern DEVICE vc_dev;
extern DEVICE lk_dev;
extern DEVICE vs_dev;
@@ -87,6 +88,7 @@ DEVICE *sim_devices[] = {
&cr_dev,
&lpt_dev,
#if defined(USE_SIM_VIDEO) && defined(HAVE_LIBSDL)
+ &va_dev,
&vc_dev,
&lk_dev,
&vs_dev,
diff --git a/VAX/vax_2681.c b/VAX/vax_2681.c
index d0248718..67a8eb88 100644
--- a/VAX/vax_2681.c
+++ b/VAX/vax_2681.c
@@ -100,7 +100,7 @@ switch (rg) {
case 2:
ctx->port[PORT_A].cmd &= ~CMD_ERX;
- ctx->port[PORT_A].sts &= ~STS_RXR;
+ ctx->port[PORT_A].sts &= ~(STS_RXR | STS_FFL);
break;
case 3:
@@ -118,7 +118,7 @@ switch (rg) {
case 3: /* tx/rx buf A */
if (((ctx->port[PORT_A].mode[1] >> MODE_V_CHM) & MODE_M_CHM) == 0x2) { /* Maint */
ctx->port[PORT_A].buf = data & 0xFF;
- ctx->port[PORT_A].sts |= STS_RXR;
+ ctx->port[PORT_A].sts |= (STS_RXR | STS_FFL);
ctx->ists |= ISTS_RAI;
}
else {
@@ -165,7 +165,7 @@ switch (rg) {
case 2:
ctx->port[PORT_B].cmd &= ~CMD_ERX;
- ctx->port[PORT_B].sts &= ~STS_RXR;
+ ctx->port[PORT_B].sts &= ~(STS_RXR | STS_FFL);
break;
case 3:
@@ -183,7 +183,7 @@ switch (rg) {
case 11: /* tx/rx buf B (mouse) */
if (((ctx->port[PORT_B].mode[1] >> MODE_V_CHM) & MODE_M_CHM) == 0x2) { /* Maint */
ctx->port[PORT_B].buf = data & 0xFF;
- ctx->port[PORT_B].sts |= STS_RXR;
+ ctx->port[PORT_B].sts |= (STS_RXR | STS_FFL);
ctx->ists |= ISTS_RBI;
}
else {
@@ -230,7 +230,7 @@ switch (rg) {
case 3: /* tx/rx buf A */
data = ctx->port[PORT_A].buf | (ctx->port[PORT_A].sts << 8);
- ctx->port[PORT_A].sts &= ~STS_RXR;
+ ctx->port[PORT_A].sts &= ~(STS_RXR | STS_FFL);
ctx->ists &= ~ISTS_RAI;
ua2681_update_rxi (ctx);
break;
@@ -258,7 +258,7 @@ switch (rg) {
case 11: /* tx/rx buf B */
data = ctx->port[PORT_B].buf | (ctx->port[PORT_B].sts << 8);
- ctx->port[PORT_B].sts &= ~STS_RXR;
+ ctx->port[PORT_B].sts &= ~(STS_RXR | STS_FFL);
ctx->ists &= ~ISTS_RBI;
ua2681_update_rxi (ctx);
break;
@@ -318,17 +318,17 @@ if (ctx->port[PORT_A].cmd & CMD_ERX) {
r = ctx->port[PORT_A].get_char (&c);
if (r == SCPE_OK) {
ctx->port[PORT_A].buf = c;
- ctx->port[PORT_A].sts |= STS_RXR;
+ ctx->port[PORT_A].sts |= (STS_RXR | STS_FFL);
ctx->ists |= ISTS_RAI;
}
else {
- ctx->port[PORT_A].sts &= ~STS_RXR;
+ ctx->port[PORT_A].sts &= ~(STS_RXR | STS_FFL);
ctx->ists &= ~ISTS_RAI;
}
}
}
else {
- ctx->port[PORT_A].sts &= ~STS_RXR;
+ ctx->port[PORT_A].sts &= ~(STS_RXR | STS_FFL);
ctx->ists &= ~ISTS_RAI;
}
@@ -338,17 +338,17 @@ if (ctx->port[PORT_B].cmd & CMD_ERX) {
r = ctx->port[PORT_B].get_char (&c);
if (r == SCPE_OK) {
ctx->port[PORT_B].buf = c;
- ctx->port[PORT_B].sts |= STS_RXR;
+ ctx->port[PORT_B].sts |= (STS_RXR | STS_FFL);
ctx->ists |= ISTS_RBI;
}
else {
- ctx->port[PORT_B].sts &= ~STS_RXR;
+ ctx->port[PORT_B].sts &= ~(STS_RXR | STS_FFL);
ctx->ists &= ~ISTS_RBI;
}
}
}
else {
- ctx->port[PORT_B].sts &= ~STS_RXR;
+ ctx->port[PORT_B].sts &= ~(STS_RXR | STS_FFL);
ctx->ists &= ~ISTS_RBI;
}
diff --git a/VAX/vax_gpx.c b/VAX/vax_gpx.c
new file mode 100644
index 00000000..4fe16b6a
--- /dev/null
+++ b/VAX/vax_gpx.c
@@ -0,0 +1,1855 @@
+/* vax_gpx.h: GPX video common components
+
+ Copyright (c) 2019, Matt Burke
+
+ Permission is hereby granted, free of charge, to any person obtaining a
+ copy of this software and associated documentation files (the "Software"),
+ to deal in the Software without restriction, including without limitation
+ the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ and/or sell copies of the Software, and to permit persons to whom the
+ Software is furnished to do so, subject to the following conditions:
+
+ The above copyright notice and this permission notice shall be included in
+ all copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ THE AUTHOR BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+
+ Except as contained in this notice, the name of the author shall not be
+ used in advertising or otherwise to promote the sale, use or other dealings
+ in this Software without prior written authorization from the author.
+*/
+
+#include "vax_gpx.h"
+
+#define VA_FIFOSIZE 64
+
+struct vdp_t {
+ uint32 rg[0x18];
+ };
+
+typedef struct vdp_t VDP;
+
+int32 va_adp[ADP_NUMREG]; /* Address processor registers */
+uint32 va_adp_fifo[VA_FIFOSIZE]; /* ADP FIFO */
+uint32 va_adp_fifo_wp; /* write pointer */
+uint32 va_adp_fifo_rp; /* read pointer */
+uint32 va_adp_fifo_sz; /* data size */
+
+VDP va_vdp[8]; /* 8 video processors */
+uint32 va_ucs = 0; /* update chip select */
+uint32 va_scs = 0; /* scroll chip select */
+
+typedef struct {
+ int32 x;
+ int32 y;
+ int32 dx;
+ int32 dy;
+ int32 err;
+ int32 xstep;
+ int32 ystep;
+ int32 pix;
+ int32 spix;
+} VA_LINE;
+
+VA_LINE s1_slow, s1_fast, dst_slow, dst_fast;
+VA_LINE s2_slow, s2_fast;
+int32 dx, dy;
+int32 s2_pixf, s2_pixs;
+uint32 s2_xmask, s2_ymask;
+DEVICE *gpx_dev;
+
+const char *va_adp_rgd[] = { /* address processor registers */
+ "Address Counter",
+ "Request Enable",
+ "Interrupt Enable",
+ "Status",
+ "Reserved - Test Function 1",
+ "Spare",
+ "Reserved - Test Function 2",
+ "I/D Data",
+ "Command",
+ "Mode",
+ "Command",
+ "Reserved - Test Function 3",
+ "I/D Scroll Data",
+ "I/D Scroll Command",
+ "Scroll X Min",
+ "Scroll X Max",
+ "Scroll Y Min",
+ "Scroll Y Max",
+ "Pause",
+ "Y Offset",
+ "Y Scroll Constant",
+ "Pending X Index",
+ "Pending Y Index",
+ "New X Index",
+ "New Y Index",
+ "Old X Index",
+ "Old Y Index",
+ "Clip X Min",
+ "Clip X Max",
+ "Clip Y Min",
+ "Clip Y Max",
+ "Spare",
+ "Fast Source 1 DX",
+ "Slow Source 1 DY",
+ "Source 1 X Origin",
+ "Source 1 Y Origin",
+ "Destination X Origin",
+ "Destination Y Origin",
+ "Fast Destination DX",
+ "Fast Destination DY",
+ "Slow Destination DX",
+ "Slow Destination DY",
+ "Fast Scale",
+ "Slow Scale",
+ "Source 2 X Origin",
+ "Source 2 Y Origin",
+ "Source 2 Height & Width",
+ "Error 1",
+ "Error 2",
+ "Y Scan Count 0",
+ "Y Scan Count 1",
+ "Y Scan Count 2",
+ "Y Scan Count 3",
+ "X Scan Configuration",
+ "X Limit",
+ "Y Limit",
+ "X Scan Count 0",
+ "X Scan Count 1",
+ "X Scan Count 2",
+ "X Scan Count 3",
+ "X Scan Count 4",
+ "X Scan Count 5",
+ "X Scan Count 6",
+ "Sync Phase"
+ };
+
+const char *va_vdp_rgd[] = { /* video processor registers */
+ "Resolution Mode",
+ "Bus Width",
+ "Scroll Constant",
+ "Plane Address",
+ "Logic Function 0",
+ "Logic Function 1",
+ "Logic Function 2",
+ "Logic Function 3",
+ "Mask 1",
+ "Mask 2",
+ "Source",
+ "Fill",
+ "Left Scroll Boundary",
+ "Right Scroll Boundary",
+ "Background Colour",
+ "Foreground Colour",
+ "CSR0",
+ "CSR1",
+ "CSR2",
+ "Reserved",
+ "CSR4",
+ "CSR5",
+ "CSR6",
+ "Reserved"
+ };
+
+const char *va_fnc[] = { /* logic functions */
+ "ZEROs",
+ "NOT (D OR S)",
+ "NOT (D) AND S",
+ "NOT (D)",
+ "D AND NOT (S)",
+ "NOT (S)",
+ "D XOR S",
+ "NOT (D AND S)",
+ "D AND S",
+ "NOT (D XOR S)",
+ "S",
+ "NOT (S) OR S",
+ "D",
+ "D OR NOT (S)",
+ "D OR S",
+ "ONEs"
+ };
+
+void va_adpstat (uint32 set, uint32 clr);
+void va_fifo_clr (void);
+void va_cmd (int32 cmd);
+void va_scmd (int32 cmd);
+void va_fill_setup (void);
+void va_adp_setup (void);
+void va_erase (uint32 x0, uint32 x1, uint32 y0, uint32 y1);
+
+void va_adpstat (uint32 set, uint32 clr)
+{
+uint32 chg = (va_adp[ADP_STAT] ^ set) & set;
+
+if (va_adp[ADP_INT] & set) /* unmasked ints 0->1? */
+ va_setint (INT_ADP);
+va_adp[ADP_STAT] = va_adp[ADP_STAT] | set;
+va_adp[ADP_STAT] = va_adp[ADP_STAT] & ~clr;
+}
+
+void va_fifo_clr (void)
+{
+sim_debug (DBG_FIFO, gpx_dev, "va_fifo_clr\n");
+va_adp_fifo[0] = 0; /* clear top word */
+va_adp_fifo_wp = 0; /* reset pointers */
+va_adp_fifo_rp = 0;
+va_adp_fifo_sz = 0; /* empty */
+va_adpstat (ADPSTAT_ITR, ADPSTAT_IRR);
+}
+
+void va_fifo_wr (uint32 val)
+{
+if (va_adp[ADP_STAT] & ADPSTAT_AC) /* addr output complete? */
+ va_fifo_clr ();
+sim_debug (DBG_FIFO, gpx_dev, "fifo_wr: %d, %X (%d) at %08X\n",
+ va_adp_fifo_wp, val, (va_adp_fifo_sz + 1), fault_PC);
+va_adp_fifo[va_adp_fifo_wp++] = val; /* store value */
+if (va_adp_fifo_wp == VA_FIFOSIZE) /* pointer wrap? */
+ va_adp_fifo_wp = 0;
+va_adp_fifo_sz++;
+
+va_adpstat (ADPSTAT_IRR, 0); /* I/D data rcv rdy */
+
+if (va_adp_fifo_sz < VA_FIFOSIZE) /* space in FIFO? */
+ va_adpstat (ADPSTAT_ITR, 0); /* I/D data xmt rdy */
+else
+ va_adpstat (0, ADPSTAT_ITR); /* I/D data xmt not rdy */
+}
+
+uint32 va_fifo_rd (void)
+{
+uint32 val;
+
+if (va_adp_fifo_sz == 0) /* reading empty fifo */
+ return 0; /* should not get here */
+val = va_adp_fifo[va_adp_fifo_rp++]; /* get value */
+sim_debug (DBG_FIFO, gpx_dev, "fifo_rd: %d, %X (%d) at %08X\n",
+ (va_adp_fifo_rp - 1), val, va_adp_fifo_sz, fault_PC);
+if (va_adp_fifo_rp == VA_FIFOSIZE) /* pointer wrap? */
+ va_adp_fifo_rp = 0;
+va_adp_fifo_sz--;
+
+va_adpstat (ADPSTAT_ITR, 0); /* I/D data xmt rdy */
+
+if (va_adp_fifo_sz > 0) /* data in FIFO? */
+ va_adpstat (ADPSTAT_IRR, 0); /* I/D data rcv rdy */
+else
+ va_adpstat (0, ADPSTAT_IRR); /* I/D data rcv not rdy */
+return val;
+}
+
+/* ADP Register descriptions on page 3-58 */
+
+int32 va_adp_rd (int32 rg)
+{
+int32 data = 0;
+
+switch (rg) {
+
+ case ADP_ADCT:
+ rg = va_adp[ADP_ADCT];
+ data = va_adp[rg];
+ va_adp[ADP_ADCT]++;
+ va_adp[ADP_ADCT] = va_adp[ADP_ADCT] & 0x3F;
+ break;
+
+ case ADP_IDD: /* I/D data */
+ switch (va_unit[1].CMD) {
+
+ case CMD_BTPX:
+ case CMD_BTPZ:
+ if (va_adp_fifo_sz == 0)
+ va_btp (&va_unit[1], (va_unit[1].CMD == CMD_BTPZ));
+ break;
+ }
+ data = va_fifo_rd ();
+ switch (va_unit[1].CMD) {
+
+ case CMD_BTPX:
+ case CMD_BTPZ:
+ if (va_adp_fifo_sz == 0)
+ va_btp (&va_unit[1], (va_unit[1].CMD == CMD_BTPZ));
+ break;
+ }
+ break;
+
+ default:
+ data = va_adp[rg];
+ }
+
+if (rg <= ADP_MAXREG)
+ sim_debug (DBG_ADP, gpx_dev, "adp_rd: %s, %X at %08X\n", va_adp_rgd[rg], data, fault_PC);
+else
+ sim_debug (DBG_ADP, gpx_dev, "adp_rd: %X, %X at %08X\n", rg, data, fault_PC);
+
+return data;
+}
+
+/* ADP Register descriptions on page 3-58 */
+
+void va_adp_wr (int32 rg, int32 val)
+{
+if (rg == ADP_ADCT) { /* special processing for address counter */
+ if (va_adp[ADP_ADCT] == ADP_IDD) { /* write full word to I/D data */
+ rg = ADP_IDD;
+ va_adp[ADP_ADCT]++;
+ }
+ else if (va_adp[ADP_ADCT] == ADP_IDS) { /* write full word to I/D scroll data */
+ rg = ADP_IDS;
+ va_adp[ADP_ADCT]++;
+ }
+ else if (val & 0x8000) /* update address counter */
+ val = val & 0x3F;
+ else { /* write low 13 bits to pointed rg */
+ rg = va_adp[ADP_ADCT];
+ val = val & 0x3FFF;
+ va_adp[ADP_ADCT]++;
+ }
+ va_adp[ADP_ADCT] = va_adp[ADP_ADCT] & 0x3F;
+ }
+
+if (rg <= ADP_MAXREG)
+ sim_debug (DBG_ADP, gpx_dev, "adp_wr: %s, %X at %08X\n", va_adp_rgd[rg], val, fault_PC);
+else
+ sim_debug (DBG_ADP, gpx_dev, "adp_wr: %X, %X at %08X\n", rg, val, fault_PC);
+
+switch (rg) {
+
+ case ADP_STAT:
+ va_adp[ADP_STAT] = va_adp[ADP_STAT] & ~(~val & ADPSTAT_W0C);
+ va_adpstat (ADPSTAT_ISR, 0); /* FIXME: temp */
+ break;
+
+ case ADP_IDD: /* I/D data */
+ va_fifo_wr (val);
+ switch (va_unit[1].CMD) {
+
+ case CMD_PTBX:
+ case CMD_PTBZ:
+ va_ptb (&va_unit[1], (va_unit[1].CMD == CMD_PTBZ));
+ break;
+ }
+ break;
+
+ case ADP_PYSC: /* y scroll constant */
+ if (val & 0x2000) /* erase scroll region */
+ va_erase (va_adp[ADP_PXMN], va_adp[ADP_PXMX], va_adp[ADP_PYMN], va_adp[ADP_PYMX]);
+ else
+ va_adp[rg] = (val | 0x8000); /* set valid flag */
+ break;
+
+ case ADP_CMD1: /* command */
+ case ADP_CMD2:
+ va_adp[ADP_CMD1] = val;
+ va_cmd (val);
+ break;
+
+ case ADP_ICS: /* I/D scroll command */
+ va_adp[ADP_ICS] = val;
+ va_scmd (val);
+ break;
+
+ case ADP_CXMN: /* clip X min */
+ case ADP_CXMX: /* clip X max */
+ case ADP_CYMN: /* clip Y min */
+ case ADP_CYMX: /* clip Y max */
+ case ADP_SXO: /* source 1 X origin */
+ case ADP_SYO: /* source 1 Y origin */
+ case ADP_DXO: /* dest X origin */
+ case ADP_DYO: /* dest Y origin */
+ case ADP_FSDX: /* fast source 1 DX */
+ case ADP_SSDY: /* slow source 1 DY */
+ case ADP_FDX: /* fast dest DX */
+ case ADP_FDY: /* fast dest DY */
+ case ADP_SDX: /* slow dest DX */
+ case ADP_SDY: /* slow dest DY */
+ if (val & 0x2000)
+ val = val | 0xFFFFC000; /* sign extend */
+ va_adp[rg] = val;
+ break;
+
+ default:
+ va_adp[rg] = val;
+ }
+return;
+}
+
+void va_vdp_wr (uint32 cn, uint32 rg, uint32 val)
+{
+VDP *vptr = &va_vdp[cn];
+
+if (rg <= VDP_MAXREG)
+ sim_debug (DBG_VDP, gpx_dev, "vdp_wr: [%d], %s, %X at %08X\n", cn, va_vdp_rgd[rg], val, fault_PC);
+else
+ sim_debug (DBG_VDP, gpx_dev, "vdp_wr: [%d], %X, %X at %08X\n", cn, rg, val, fault_PC);
+vptr->rg[rg] = val;
+if (rg == VDP_MSK1)
+ vptr->rg[VDP_MSK2] = val;
+}
+
+/* Initialise line drawing */
+
+void va_line_init (VA_LINE *ln, int32 dx, int32 dy, int32 pix)
+{
+ln->x = 0;
+ln->y = 0;
+ln->dx = dx;
+ln->dy = dy;
+ln->pix = pix;
+ln->spix = pix;
+ln->xstep = (dx < 0) ? -1 : 1;
+ln->ystep = (dy < 0) ? -1 : 1;
+ln->err = (abs(dx) > abs(dy)) ? (ln->xstep * -dx) : (ln->ystep * -dy);
+}
+
+/* Step to the next point on a line */
+
+t_bool va_line_step (VA_LINE *ln)
+{
+if ((ln->dx == 0) && (ln->dy == 0)) /* null line? */
+ return TRUE; /* done */
+else if (ln->dx == 0) { /* no X component? */
+ ln->y = ln->y + ln->ystep; /* just step Y */
+ ln->pix = ln->pix + (VA_XSIZE * ln->ystep);
+ }
+else if (ln->dy == 0) { /* no Y component? */
+ ln->x = ln->x + ln->xstep; /* just step X */
+ ln->pix = ln->pix + ln->xstep;
+ }
+else {
+ if (abs(ln->dx) > abs(ln->dy)) { /* determine major axis */
+ ln->x = ln->x + ln->xstep;
+ ln->pix = ln->pix + ln->xstep;
+ ln->err = ln->err + (2 * ln->dy * ln->ystep);
+ if (ln->err > 0) {
+ ln->y = ln->y + ln->ystep;
+ ln->pix = ln->pix + (VA_XSIZE * ln->ystep);
+ ln->err = ln->err - (2 * ln->dx * ln->xstep);
+ }
+ }
+ else {
+ ln->y = ln->y + ln->ystep;
+ ln->pix = ln->pix + (VA_XSIZE * ln->ystep);
+ ln->err = ln->err + (2 * ln->dx * ln->xstep);
+ if (ln->err > 0) {
+ ln->x = ln->x + ln->xstep;
+ ln->pix = ln->pix + ln->xstep;
+ ln->err = ln->err - (2 * ln->dy * ln->ystep);
+ }
+ }
+ }
+ln->pix = ln->pix & VA_BUFMASK; /* wrap within video buffer */
+
+if ((ln->x == ln->dx) && (ln->y == ln->dy)) { /* finished? */
+ ln->x = 0;
+ ln->y = 0;
+ ln->pix = ln->spix;
+ return TRUE; /* done */
+ }
+return FALSE; /* more steps to do */
+}
+
+void va_viper_rop (int32 cn, uint32 sc, uint32 *pix)
+{
+uint32 cmd = va_adp[ADP_CMD1];
+uint32 lu = (cmd >> 4) & 0x3;
+uint32 fnc = va_vdp[cn].rg[VDP_FNC0 + lu];
+int32 mask = (1u << va_vdp[cn].rg[VDP_PA]);
+
+uint32 mask1 = (va_vdp[cn].rg[VDP_MSK1] >> sc) & 0x1;
+uint32 mask2 = (va_vdp[cn].rg[VDP_MSK2] >> sc) & 0x1;
+uint32 src = (va_vdp[cn].rg[VDP_SRC] >> sc) & 0x1;
+
+uint32 dest = (*pix >> va_vdp[cn].rg[VDP_PA]) & 0x1;
+
+if (fnc & 0x10)
+ mask1 = ~mask1;
+if (fnc & 0x20)
+ mask2 = ~mask2;
+if ((fnc & 0x40) == 0)
+ src = ~src;
+
+if ((mask1 & mask2 & 0x1) == 0)
+ return;
+
+switch (fnc & 0xF) {
+ case 0x0: /* ZEROs */
+ dest = 0;
+ break;
+
+ case 0x1: /* NOT (D OR S) */
+ dest = ~(dest | src);
+ break;
+
+ case 0x2: /* NOT (D) AND S */
+ dest = ~(dest) & src;
+ break;
+
+ case 0x3: /* NOT (D) */
+ dest = ~(dest);
+ break;
+
+ case 0x4: /* D AND NOT (S) */
+ dest = dest & ~(src);
+ break;
+
+ case 0x5: /* NOT (S) */
+ dest = ~(src);
+ break;
+
+ case 0x6: /* D XOR S */
+ dest = dest ^ src;
+ break;
+
+ case 0x7: /* NOT (D AND S) */
+ dest = ~(dest & src);
+ break;
+
+ case 0x8: /* D AND S */
+ dest = (dest & src);
+ break;
+
+ case 0x9: /* NOT (D XOR S) */
+ dest = ~(dest ^ src);
+ break;
+
+ case 0xA: /* S */
+ dest = src;
+ break;
+
+ case 0xB: /* NOT (S) OR S */
+ dest = ~(src) | src;
+ break;
+
+ case 0xC: /* D */
+ break;
+
+ case 0xD: /* D OR NOT (S) */
+ dest = dest | ~(src);
+ break;
+
+ case 0xE: /* D OR S */
+ dest = (dest | src);
+ break;
+
+ case 0xF: /* ONEs */
+ dest = 0xFFFF;
+ break;
+ }
+
+if (dest & 0x1)
+ dest = (va_vdp[cn].rg[VDP_FG] >> sc) & 0x1;
+else
+ dest = (va_vdp[cn].rg[VDP_BG] >> sc) & 0x1;
+dest = (dest << va_vdp[cn].rg[VDP_PA]);
+*pix = (*pix & ~mask) | (dest & mask);
+}
+
+t_stat va_fill (UNIT *uptr)
+{
+uint32 cmd = va_adp[ADP_CMD1];
+int32 old_y, x0, x1;
+int32 sel, cn;
+int32 bs2 = -1;
+t_bool clip;
+uint32 s2_temp;
+uint32 s2_csr;
+
+if (cmd & 0x4)
+ s2_csr = VDP_CSR5;
+else
+ s2_csr = VDP_CSR1;
+
+for (sel = va_ucs, cn = 0; sel; sel >>=1, cn++) {
+ if (sel & 1) { /* chip selected? */
+ if (cmd & 0x1000) { /* source 2 enabled? */
+ if (va_vdp[cn].rg[s2_csr] & 0x10) { /* broadcast enabled? */
+ bs2 = cn;
+ }
+ }
+ }
+ }
+
+for (;;) {
+ x0 = (dst_slow.x + va_adp[ADP_DXO]);
+ x1 = (s1_slow.x + va_adp[ADP_SXO]);
+ sim_debug (DBG_ROP, gpx_dev, "Fill line %d from %d to %d\n", (dst_slow.y + dy), x0, x1);
+ va_line_init (&dst_fast, (x1 - x0), 0, dst_slow.pix);
+
+ for (;;) {
+ if (cmd & 0x1000) { /* source 2 enabled? */
+ s2_fast.x = (dst_fast.x + va_adp[ADP_DXO]) & s2_xmask;
+ s2_slow.y = (dst_slow.y + va_adp[ADP_DYO]) & s2_ymask;
+ s2_pixf = s2_pixs + (s2_slow.y * VA_XSIZE);
+ s2_pixf = s2_pixf + s2_fast.x;
+ s2_pixf = s2_pixf & VA_BUFMASK;
+ sim_debug (DBG_ROP, gpx_dev, "Source 2 X: %d, Y: %d, pix: %X\n", s2_fast.x, s2_slow.y, va_buf[s2_pixf]);
+ /* get source pixel and put in Viper source register */
+ for (sel = va_ucs, cn = 0; sel; sel >>=1, cn++) { /* internal load */
+ if (sel & 1) { /* chip selected? */
+ if ((va_vdp[cn].rg[s2_csr] & 0xC) == 0)
+ continue;
+ s2_temp = va_buf[s2_pixf]; /* FIXME: implement fast mode */
+ s2_temp >>= va_vdp[cn].rg[VDP_PA];
+ s2_temp <<= (dst_fast.x & 0xF);
+ switch (va_vdp[cn].rg[s2_csr] & 0xC) {
+ case 0x4:
+ va_vdp[cn].rg[VDP_SRC] = s2_temp;
+ break;
+ case 0x8:
+ va_vdp[cn].rg[VDP_MSK1] = s2_temp;
+ va_vdp[cn].rg[VDP_MSK2] = s2_temp;
+ break;
+ case 0xC:
+ va_vdp[cn].rg[VDP_MSK2] = s2_temp;
+ break;
+ }
+ }
+ }
+ if (bs2 >= 0) {
+ s2_temp = va_buf[s2_pixf]; /* FIXME: implement fast mode */
+ s2_temp >>= va_vdp[bs2].rg[VDP_PA];
+ s2_temp <<= (dst_fast.x & 0xF);
+ for (sel = va_ucs, cn = 0; sel; sel >>=1, cn++) { /* external load */
+ if (sel & 1) { /* chip selected? */
+ if ((va_vdp[cn].rg[s2_csr] & 0x3) == 0)
+ continue;
+ switch (va_vdp[cn].rg[s2_csr] & 0x3) {
+ case 0x1:
+ va_vdp[cn].rg[VDP_SRC] = s2_temp;
+ break;
+ case 0x2:
+ va_vdp[cn].rg[VDP_MSK1] = s2_temp;
+ va_vdp[cn].rg[VDP_MSK2] = s2_temp;
+ break;
+ case 0x3:
+ va_vdp[cn].rg[VDP_MSK2] = s2_temp;
+ break;
+ }
+ }
+ }
+ }
+ }
+ clip = FALSE;
+ if ((dst_slow.x + dst_fast.x + dx) < va_adp[ADP_CXMN]) {
+ va_adp[ADP_STAT] |= ADPSTAT_CL;
+ clip = TRUE;
+ }
+ else if ((dst_slow.x + dst_fast.x + dx) > va_adp[ADP_CXMX]) {
+ va_adp[ADP_STAT] |= ADPSTAT_CR;
+ clip = TRUE;
+ }
+ if ((dst_slow.y + dst_fast.y + dy) < va_adp[ADP_CYMN]) {
+ va_adp[ADP_STAT] |= ADPSTAT_CT;
+ clip = TRUE;
+ }
+ else if ((dst_slow.y + dst_fast.y + dy) > va_adp[ADP_CYMX]) {
+ va_adp[ADP_STAT] |= ADPSTAT_CB;
+ clip = TRUE;
+ }
+ if ((cmd & 0x400) && (va_adp[ADP_MDE] & 0x80) && !clip) { /* dest enabled, pen down? */
+ /* Call all enabled Vipers to process the current pixel */
+ for (sel = va_ucs, cn = 0; sel; sel >>=1, cn++) {
+ if (sel & 1) /* chip selected? */
+ va_viper_rop (cn, (dst_fast.x & 0xF), &va_buf[dst_fast.pix]);
+ }
+ sim_debug (DBG_ROP, gpx_dev, "-> Dest X: %d, Y: %d, pix: %X\n", dst_fast.x, dst_slow.y, va_buf[dst_fast.pix]);
+ va_updated[dst_slow.y + dst_fast.y + dy] = TRUE;
+ }
+
+ if (va_line_step (&dst_fast)) /* fast vector exhausted? */
+ break;
+ }
+
+ for (old_y = dst_slow.y; dst_slow.y == old_y;) { /* step vector A */
+ if (va_line_step (&dst_slow)) {
+ if ((va_adp[ADP_STAT] & ADPSTAT_CP) == 0)
+ va_adp[ADP_STAT] |= ADPSTAT_CN;
+ sim_debug (DBG_ROP, gpx_dev, "Fill Complete\n");
+ uptr->CMD = 0;
+ va_adpstat (ADPSTAT_AC | ADPSTAT_RC, 0);
+ return SCPE_OK;
+ }
+ }
+ for (old_y = s1_slow.y; s1_slow.y == old_y;) { /* step vector B */
+ if (va_line_step (&s1_slow)) {
+ if ((va_adp[ADP_STAT] & ADPSTAT_CP) == 0)
+ va_adp[ADP_STAT] |= ADPSTAT_CN;
+ sim_debug (DBG_ROP, gpx_dev, "Fill Complete\n");
+ uptr->CMD = 0;
+ va_adpstat (ADPSTAT_AC | ADPSTAT_RC, 0);
+ return SCPE_OK;
+ }
+ }
+ }
+}
+
+t_stat va_rop (UNIT *uptr)
+{
+uint32 cmd = va_adp[ADP_CMD1];
+int32 sel, cn;
+int32 bs1 = -1;
+int32 bs2 = -1;
+t_bool clip, scale, wrap;
+uint32 s1_temp;
+uint32 s2_temp;
+uint32 s1_csr;
+uint32 s2_csr;
+uint32 acf = 0; /* fast scale accumulator */
+uint32 acs = 0; /* slow scale accumulator */
+
+scale = FALSE;
+if ((va_adp[ADP_FS] & 0x1FFF) != 0x1FFF) /* fast scale != unity? */
+ scale = TRUE; /* enable scaling */
+if ((va_adp[ADP_SS] & 0x1FFF) != 0x1FFF) /* slow scale != unity? */
+ scale = TRUE; /* enable scaling */
+
+if (cmd & 0x4) {
+ s1_csr = VDP_CSR4; /* CSR bank 2 */
+ s2_csr = VDP_CSR5;
+ }
+else {
+ s1_csr = VDP_CSR0; /* CSR bank 1 */
+ s2_csr = VDP_CSR1;
+ }
+
+for (sel = va_ucs, cn = 0; sel; sel >>=1, cn++) {
+ if (sel & 1) { /* chip selected? */
+ if (cmd & 0x800) { /* source 1 enabled? */
+ if (va_vdp[cn].rg[s1_csr] & 0x10) { /* broadcast enabled? */
+ bs1 = cn;
+ }
+ }
+ if (cmd & 0x1000) { /* source 2 enabled? */
+ if (va_vdp[cn].rg[s2_csr] & 0x10) { /* broadcast enabled? */
+ bs2 = cn;
+ }
+ }
+ }
+ }
+
+for (;;) {
+ if (cmd & 0x800) { /* source 1 enabled? */
+ sim_debug (DBG_ROP, gpx_dev, "Source X: %d, Y: %d, pix: %X\n", s1_fast.x, s1_slow.y, va_buf[s1_fast.pix]);
+ /* get source pixel and put in Viper source register */
+ for (sel = va_ucs, cn = 0; sel; sel >>=1, cn++) { /* internal load */
+ if (sel & 1) { /* chip selected? */
+ if ((va_vdp[cn].rg[s1_csr] & 0xC) == 0)
+ continue;
+ s1_temp = va_buf[s1_fast.pix]; /* FIXME: implement fast mode */
+ s1_temp >>= va_vdp[cn].rg[VDP_PA];
+ s1_temp <<= (dst_fast.x & 0xF);
+ switch (va_vdp[cn].rg[s1_csr] & 0xC) {
+ case 0x4:
+ va_vdp[cn].rg[VDP_SRC] = s1_temp;
+ break;
+ case 0x8:
+ va_vdp[cn].rg[VDP_MSK1] = s1_temp;
+ va_vdp[cn].rg[VDP_MSK2] = s1_temp;
+ break;
+ case 0xC:
+ va_vdp[cn].rg[VDP_MSK2] = s1_temp;
+ break;
+ }
+ }
+ }
+ if (bs1 >= 0) {
+ s1_temp = va_buf[s1_fast.pix]; /* FIXME: implement fast mode */
+ s1_temp >>= va_vdp[bs1].rg[VDP_PA];
+ s1_temp <<= (dst_fast.x & 0xF);
+ for (sel = va_ucs, cn = 0; sel; sel >>=1, cn++) { /* external load */
+ if (sel & 1) { /* chip selected? */
+ if ((va_vdp[cn].rg[s1_csr] & 0x3) == 0)
+ continue;
+ switch (va_vdp[cn].rg[s1_csr] & 0x3) {
+ case 0x1:
+ va_vdp[cn].rg[VDP_SRC] = s1_temp;
+ break;
+ case 0x2:
+ va_vdp[cn].rg[VDP_MSK1] = s1_temp;
+ va_vdp[cn].rg[VDP_MSK2] = s1_temp;
+ break;
+ case 0x3:
+ va_vdp[cn].rg[VDP_MSK2] = s1_temp;
+ break;
+ }
+ }
+ }
+ }
+ }
+ if (cmd & 0x1000) { /* source 2 enabled? */
+ s2_fast.x = (dst_fast.x + va_adp[ADP_DXO]) & s2_xmask;
+ s2_slow.y = (dst_slow.y + va_adp[ADP_DYO]) & s2_ymask;
+ s2_pixf = s2_pixs + (s2_slow.y * VA_XSIZE);
+ s2_pixf = s2_pixf + s2_fast.x;
+ s2_pixf = s2_pixf & VA_BUFMASK;
+ sim_debug (DBG_ROP, gpx_dev, "Source 2 X: %d, Y: %d, pix: %X\n", s2_fast.x, s2_slow.y, va_buf[s2_pixf]);
+ /* get source pixel and put in Viper source register */
+ for (sel = va_ucs, cn = 0; sel; sel >>=1, cn++) { /* internal load */
+ if (sel & 1) { /* chip selected? */
+ if ((va_vdp[cn].rg[s2_csr] & 0xC) == 0)
+ continue;
+ s2_temp = va_buf[s2_pixf]; /* FIXME: implement fast mode */
+ s2_temp >>= va_vdp[cn].rg[VDP_PA];
+ s2_temp <<= (dst_fast.x & 0xF);
+ switch (va_vdp[cn].rg[s2_csr] & 0xC) {
+ case 0x4:
+ va_vdp[cn].rg[VDP_SRC] = s2_temp;
+ break;
+ case 0x8:
+ va_vdp[cn].rg[VDP_MSK1] = s2_temp;
+ va_vdp[cn].rg[VDP_MSK2] = s2_temp;
+ break;
+ case 0xC:
+ va_vdp[cn].rg[VDP_MSK2] = s2_temp;
+ break;
+ }
+ }
+ }
+ if (bs2 >= 0) {
+ s2_temp = va_buf[s2_pixf]; /* FIXME: implement fast mode */
+ s2_temp >>= va_vdp[bs2].rg[VDP_PA];
+ s2_temp <<= (dst_fast.x & 0xF);
+ for (sel = va_ucs, cn = 0; sel; sel >>=1, cn++) { /* external load */
+ if (sel & 1) { /* chip selected? */
+ if ((va_vdp[cn].rg[s2_csr] & 0x3) == 0)
+ continue;
+ switch (va_vdp[cn].rg[s2_csr] & 0x3) {
+ case 0x1:
+ va_vdp[cn].rg[VDP_SRC] = s2_temp;
+ break;
+ case 0x2:
+ va_vdp[cn].rg[VDP_MSK1] = s2_temp;
+ va_vdp[cn].rg[VDP_MSK2] = s2_temp;
+ break;
+ case 0x3:
+ va_vdp[cn].rg[VDP_MSK2] = s2_temp;
+ break;
+ }
+ }
+ }
+ }
+ }
+ clip = FALSE;
+ if ((dst_slow.x + dst_fast.x + dx) < va_adp[ADP_CXMN]) {
+ va_adp[ADP_STAT] |= ADPSTAT_CL;
+ clip = TRUE;
+ }
+ else if ((dst_slow.x + dst_fast.x + dx) > va_adp[ADP_CXMX]) {
+ va_adp[ADP_STAT] |= ADPSTAT_CR;
+ clip = TRUE;
+ }
+ if ((dst_slow.y + dst_fast.y + dy) < va_adp[ADP_CYMN]) {
+ va_adp[ADP_STAT] |= ADPSTAT_CT;
+ clip = TRUE;
+ }
+ else if ((dst_slow.y + dst_fast.y + dy) > va_adp[ADP_CYMX]) {
+ va_adp[ADP_STAT] |= ADPSTAT_CB;
+ clip = TRUE;
+ }
+ if ((cmd & 0x400) && (va_adp[ADP_MDE] & 0x80) && !clip) { /* dest enabled, pen down? */
+ /* Call all enabled Vipers to process the current pixel */
+ for (sel = va_ucs, cn = 0; sel; sel >>=1, cn++) {
+ if (sel & 1) /* chip selected? */
+ va_viper_rop (cn, (dst_fast.x & 0xF), &va_buf[dst_fast.pix]);
+ }
+ sim_debug (DBG_ROP, gpx_dev, "-> Dest X: %d, Y: %d, pix: %X\n", dst_fast.x, dst_slow.y, va_buf[dst_fast.pix]);
+ va_updated[dst_slow.y + dst_fast.y + dy] = TRUE;
+ }
+
+ if ((va_adp[ADP_MDE] & 3) == 2) { /* linear pattern mode? */
+ if (cmd & 0x800) /* source 1 enabled? */
+ va_line_step (&s1_fast); /* step fast vector */
+ if (va_line_step (&dst_fast)) { /* fast vector exhausted? */
+ if (va_line_step (&dst_slow)) /* slow vector exhausted? */
+ break; /* finished */
+ if (cmd & 0x800) { /* source 1 enabled? */
+ va_line_step (&s1_slow); /* step slow vector */
+ s1_fast.pix = s1_slow.pix;
+ s1_fast.spix = s1_slow.pix;
+ }
+ dst_fast.pix = dst_slow.pix;
+ }
+ }
+ else {
+ if (cmd & 0x800) { /* source 1 enabled? */
+ if (scale) {
+ acf = acf + (va_adp[ADP_FS] & 0x1FFF) + 1; /* increment fast accumulator */
+ wrap = FALSE;
+ if ((va_adp[ADP_FS] & 0x2000) || (acf & 0x2000)) /* all but upscaling, no overflow */
+ wrap = wrap | va_line_step (&s1_fast); /* fast vector exhausted? */
+ if (((va_adp[ADP_FS] & 0x2000) == 0) || (acf & 0x2000)) /* all but downscaling, no overflow */
+ wrap = wrap | va_line_step (&dst_fast); /* fast vector exhausted? */
+ if (wrap) {
+ acs = acs + (va_adp[ADP_SS] & 0x1FFF) + 1; /* increment slow accumulator */
+ if ((va_adp[ADP_SS] & 0x2000) || (acs & 0x2000)) { /* all but upscaling, no overflow */
+ if (va_line_step (&s1_slow)) /* slow vector exhausted? */
+ break; /* finished */
+ }
+ s1_fast.x = 0;
+ s1_fast.y = 0;
+ s1_fast.pix = s1_slow.pix;
+ if (((va_adp[ADP_FS] & 0x2000) == 0) || (acf & 0x2000)) { /* all but downscaling, no overflow */
+ if (va_line_step (&dst_slow)) /* slow vector exhausted? */
+ break; /* finished */
+ }
+ dst_fast.x = 0;
+ dst_fast.y = 0;
+ dst_fast.pix = dst_slow.pix;
+ acf = 0;
+ }
+ acf = acf & 0x1FFF; /* clear overflow bits */
+ acs = acs & 0x1FFF;
+ }
+ else {
+ if (va_line_step (&s1_fast)) { /* fast vector exhausted? */
+ if (va_line_step (&s1_slow)) /* slow vector exhausted? */
+ break; /* finished */
+ s1_fast.pix = s1_slow.pix;
+ }
+ if (va_line_step (&dst_fast)) { /* fast vector exhausted? */
+ if (va_line_step (&dst_slow)) /* slow vector exhausted? */
+ break; /* finished */
+ dst_fast.pix = dst_slow.pix;
+ }
+ }
+ }
+ else {
+ if (va_line_step (&dst_fast)) { /* fast vector exhausted? */
+ if (va_line_step (&dst_slow)) /* slow vector exhausted? */
+ break; /* finished */
+ dst_fast.pix = dst_slow.pix;
+ }
+ }
+ }
+ }
+if ((va_adp[ADP_STAT] & ADPSTAT_CP) == 0)
+ va_adp[ADP_STAT] |= ADPSTAT_CN;
+sim_debug (DBG_ROP, gpx_dev, "ROP Complete\n");
+uptr->CMD = 0;
+va_adpstat (ADPSTAT_AC | ADPSTAT_RC, 0);
+return SCPE_OK;
+}
+
+void va_cmd (int32 cmd)
+{
+uint32 sel, cn, val, rg;
+uint32 adp_opc = (cmd >> 8) & 0x7;
+uint32 lu;
+
+/* Commands on page 3-74 */
+
+switch (adp_opc) { /* address processor opcode */
+
+ case 0: /* cancel */
+ sim_debug (DBG_ROP, gpx_dev, "Command: Cancel\n");
+ va_adpstat (0, ADPSTAT_ITR);
+ va_unit[1].CMD = CMD_NOP;
+ va_adpstat (ADPSTAT_IC|ADPSTAT_RC|ADPSTAT_AC, 0); /* addr output complete */
+ va_fifo_clr ();
+ return;
+
+ case 1: /* register load */
+ /* Video processor chip registers on page 3-82 */
+ if (cmd & 0x80) {
+ if (cmd & 0x20) { /* I/D Bus Z-Axis Register Load */
+ rg = ((cmd >> 2) & 3);
+ val = va_fifo_rd ();
+ sim_debug (DBG_VDP, gpx_dev, "vdp_wr: z-reg[%X, %X] = %X\n", rg, (cmd & 0x3), val);
+ switch (rg) {
+ case 0:
+ rg = VDP_SRC;
+ break;
+ case 1:
+ rg = VDP_FG;
+ break;
+ case 2:
+ rg = VDP_FILL;
+ break;
+ case 3:
+ rg = VDP_BG;
+ break;
+ }
+ for (sel = va_ucs, cn = 0; sel; sel >>=1, cn++) {
+ if (sel & 1) { /* chip selected? */
+ if (val & (1u << cn))
+ va_vdp_wr (cn, rg, 0xFFFF);
+ else
+ va_vdp_wr (cn, rg, 0);
+ }
+ }
+ }
+ else { /* I/D Bus Video Processor Register Load */
+ rg = (cmd & 0x1F);
+ val = va_fifo_rd ();
+ for (sel = va_ucs, cn = 0; sel; sel >>=1, cn++) {
+ if (sel & 1) /* chip selected? */
+ va_vdp_wr (cn, rg, val);
+ }
+ }
+ }
+ else { /* I/D Bus External Register Load */
+ switch (cmd & 0xff) {
+ case 0x40: /* scroll chip select */
+ va_scs = va_fifo_rd ();
+ va_scs = va_scs & VA_PLANE_MASK;
+ sim_debug (DBG_VDP, gpx_dev, "scs_sel: %X (%X) at %08X\n", va_scs, (cmd & 0x7F), fault_PC);
+ break;
+
+ case 0x60: /* update chip select (green update mask) */
+ va_ucs = va_fifo_rd ();
+ va_ucs = va_ucs & VA_PLANE_MASK;
+ sim_debug (DBG_VDP, gpx_dev, "ucs_sel: %X (%X) at %08X\n", va_ucs, (cmd & 0x7F), fault_PC);
+ break;
+
+ case 0x30: /* red update mask */
+ break;
+
+ case 0x18: /* blue update mask */
+ break;
+ }
+ }
+ return;
+
+ case 3: /* bitmap to processor */
+ sim_debug (DBG_ROP, gpx_dev, "Command: BTP\n");
+ sim_debug (DBG_ROP, gpx_dev, " Mode: %s\n", (cmd & 0x40) ? "X-Mode" : "Z-Mode");
+ sim_debug (DBG_ROP, gpx_dev, " Select: %X\n", va_ucs);
+ sim_debug (DBG_ROP, gpx_dev, " X Index: %d\n", va_adp[ADP_NXI]);
+ sim_debug (DBG_ROP, gpx_dev, " Y Index: %d\n", va_adp[ADP_NYI]);
+ sim_debug (DBG_ROP, gpx_dev, " Source 1 Indexing: %s\n", (va_adp[ADP_MDE]& 0x20) ? "Enabled" : "Disabled");
+ sim_debug (DBG_ROP, gpx_dev, " Source 1 X Origin: %d\n", va_adp[ADP_SXO]);
+ sim_debug (DBG_ROP, gpx_dev, " Source 1 Y Origin: %d\n", va_adp[ADP_SYO]);
+ sim_debug (DBG_ROP, gpx_dev, " Fast Source 1 DX: %d\n", va_adp[ADP_FSDX]);
+ sim_debug (DBG_ROP, gpx_dev, " Slow Source 1 DY: %d\n", va_adp[ADP_SSDY]);
+ sim_debug (DBG_ROP, gpx_dev, " Fast Scale: %d\n", va_adp[ADP_FS]);
+ sim_debug (DBG_ROP, gpx_dev, " Slow Scale: %d\n", va_adp[ADP_SS]);
+
+ va_fifo_clr ();
+ va_adpstat (ADPSTAT_IC, (ADPSTAT_AC | ADPSTAT_RC));
+ if (cmd & 0x40)
+ va_unit[1].CMD = CMD_BTPX; /* X-Mode */
+ else
+ va_unit[1].CMD = CMD_BTPZ; /* Z-Mode */
+ va_adp_setup ();
+ if (va_adp[ADP_STAT] & ADPSTAT_ITR) /* space in FIFO? */
+ va_btp (&va_unit[1], (va_unit[1].CMD == CMD_BTPZ));
+ return;
+
+ case 6: /* rasterop */
+ lu = (cmd >> 4) & 0x3; /* get logic unit */
+ sim_debug (DBG_ROP, gpx_dev, "Command: ROP\n");
+ sim_debug (DBG_ROP, gpx_dev, " Mode: %s\n", (cmd & 0x40) ? "X-Mode" : "Z-Mode");
+ sim_debug (DBG_ROP, gpx_dev, " Select: %X\n", va_ucs);
+ sim_debug (DBG_ROP, gpx_dev, " Source 1: %s\n", (cmd & 0x800) ? "Enabled" : "Disabled");
+ sim_debug (DBG_ROP, gpx_dev, " Source 2: %s\n", (cmd & 0x1000) ? "Enabled" : "Disabled");
+ sim_debug (DBG_ROP, gpx_dev, " Clip: (%d, %d, %d, %d)\n", va_adp[ADP_CXMN], va_adp[ADP_CYMN], va_adp[ADP_CXMX], va_adp[ADP_CYMX]);
+ switch (va_adp[ADP_MDE] & 0x3) {
+ case 0:
+ sim_debug (DBG_ROP, gpx_dev, " Mode: Normal\n");
+ break;
+ case 1:
+ sim_debug (DBG_ROP, gpx_dev, " Mode: Reserved\n");
+ break;
+ case 2:
+ sim_debug (DBG_ROP, gpx_dev, " Mode: Linear Pattern\n");
+ break;
+ case 3:
+ sim_debug (DBG_ROP, gpx_dev, " Mode: Fill (%s, %s)\n", (va_adp[ADP_MDE] & 0x4) ? "Y" : "X",
+ (va_adp[ADP_MDE] & 0x8) ? "Baseline" : "Normal");
+ break;
+ }
+ sim_debug (DBG_ROP, gpx_dev, " Hole Fill: %s\n", (va_adp[ADP_MDE] & 0x10) ? "Enabled" : "Disabled");
+ sim_debug (DBG_ROP, gpx_dev, " Pen: %s\n", (va_adp[ADP_MDE] & 0x80) ? "Down" : "Up");
+ sim_debug (DBG_ROP, gpx_dev, " Logic Unit: %d\n", lu);
+ rg = (cmd & 0x4);
+ for (sel = va_ucs, cn = 0; sel; sel >>=1, cn++) {
+ if (sel & 1) { /* chip selected? */
+ sim_debug (DBG_ROP, gpx_dev, " [%d] Function: %s\n", cn, va_fnc[va_vdp[cn].rg[0x4 + lu] & 0xF]);
+ sim_debug (DBG_ROP, gpx_dev, " [%d] Mask 1: %04X (%s)\n", cn, va_vdp[cn].rg[VDP_MSK1], (va_vdp[cn].rg[0x4 + lu] & 0x10) ? "Complement" : "Enabled");
+ sim_debug (DBG_ROP, gpx_dev, " [%d] Mask 2: %04X (%s)\n", cn, va_vdp[cn].rg[VDP_MSK2], (va_vdp[cn].rg[0x4 + lu] & 0x20) ? "Complement" : "Enabled");
+ sim_debug (DBG_ROP, gpx_dev, " [%d] Source: %04X (%s)\n", cn, va_vdp[cn].rg[VDP_SRC], (va_vdp[cn].rg[0x4 + lu] & 0x40) ? "Enabled" : "Complement");
+ sim_debug (DBG_ROP, gpx_dev, " [%d] Resolution Mode: %s\n", cn, (va_vdp[cn].rg[0x4 + lu] & 0x40) ? "Disabled" : "Enabled");
+ sim_debug (DBG_ROP, gpx_dev, " [%d] Foreground: %04X\n", cn, va_vdp[cn].rg[VDP_FG]);
+ sim_debug (DBG_ROP, gpx_dev, " [%d] Background: %04X\n", cn, va_vdp[cn].rg[VDP_BG]);
+ sim_debug (DBG_ROP, gpx_dev, " [%d] Fill: %04X\n", cn, va_vdp[cn].rg[VDP_FILL]);
+ if (va_vdp[cn].rg[VDP_CSR0 + rg] & 0x10) {
+ sim_debug (DBG_ROP, gpx_dev, " [%d] Broadcast: Enabled\n", cn);
+ }
+ if (va_vdp[cn].rg[VDP_CSR1 + rg] & 0x10) {
+ sim_debug (DBG_ROP, gpx_dev, " [%d] S2 Broadcast: Enabled\n", cn);
+ }
+ if (cmd & 0x800) { /* source 1 enabled? */
+ switch (va_vdp[cn].rg[VDP_CSR0 + rg] & 0xC) {
+ case 0x0:
+ sim_debug (DBG_ROP, gpx_dev, " [%d] Source 1 Internal: None\n", cn);
+ break;
+ case 0x4:
+ sim_debug (DBG_ROP, gpx_dev, " [%d] Source 1 Internal: Source\n", cn);
+ break;
+ case 0x8:
+ sim_debug (DBG_ROP, gpx_dev, " [%d] Source 1 Internal: Mask 1 & 2\n", cn);
+ break;
+ case 0xC:
+ sim_debug (DBG_ROP, gpx_dev, " [%d] Source 1 Internal: Mask 2\n", cn);
+ break;
+ }
+ switch (va_vdp[cn].rg[VDP_CSR0 + rg] & 0x3) {
+ case 0x0:
+ sim_debug (DBG_ROP, gpx_dev, " [%d] Source 1 External: None\n", cn);
+ break;
+ case 0x1:
+ sim_debug (DBG_ROP, gpx_dev, " [%d] Source 1 External: Source\n", cn);
+ break;
+ case 0x2:
+ sim_debug (DBG_ROP, gpx_dev, " [%d] Source 1 External: Mask 1 & 2\n", cn);
+ break;
+ case 0x3:
+ sim_debug (DBG_ROP, gpx_dev, " [%d] Source 1 External: Mask 2\n", cn);
+ break;
+ }
+ }
+ if (cmd & 0x1000) { /* source 2 enabled? */
+ switch (va_vdp[cn].rg[VDP_CSR1 + rg] & 0xC) {
+ case 0x0:
+ sim_debug (DBG_ROP, gpx_dev, " [%d] Source 2 Internal: None\n", cn);
+ break;
+ case 0x4:
+ sim_debug (DBG_ROP, gpx_dev, " [%d] Source 2 Internal: Source\n", cn);
+ break;
+ case 0x8:
+ sim_debug (DBG_ROP, gpx_dev, " [%d] Source 2 Internal: Mask 1 & 2\n", cn);
+ break;
+ case 0xC:
+ sim_debug (DBG_ROP, gpx_dev, " [%d] Source 2 Internal: Mask 2\n", cn);
+ break;
+ }
+ switch (va_vdp[cn].rg[VDP_CSR1 + rg] & 0x3) {
+ case 0x0:
+ sim_debug (DBG_ROP, gpx_dev, " [%d] Source 2 External: None\n", cn);
+ break;
+ case 0x1:
+ sim_debug (DBG_ROP, gpx_dev, " [%d] Source 2 External: Source\n", cn);
+ break;
+ case 0x2:
+ sim_debug (DBG_ROP, gpx_dev, " [%d] Source 2 External: Mask 1 & 2\n", cn);
+ break;
+ case 0x3:
+ sim_debug (DBG_ROP, gpx_dev, " [%d] Source 2 External: Mask 2\n", cn);
+ break;
+ }
+ }
+ }
+ }
+ sim_debug (DBG_ROP, gpx_dev, " X Index: %d\n", va_adp[ADP_NXI]);
+ sim_debug (DBG_ROP, gpx_dev, " Y Index: %d\n", va_adp[ADP_NYI]);
+ if (cmd & 0x800) {
+ sim_debug (DBG_ROP, gpx_dev, " Source 1 Indexing: %s\n", (va_adp[ADP_MDE]& 0x20) ? "Enabled" : "Disabled");
+ sim_debug (DBG_ROP, gpx_dev, " Source 1 X Origin: %d\n", va_adp[ADP_SXO]);
+ sim_debug (DBG_ROP, gpx_dev, " Source 1 Y Origin: %d\n", va_adp[ADP_SYO]);
+ sim_debug (DBG_ROP, gpx_dev, " Fast Source 1 DX: %d\n", va_adp[ADP_FSDX]);
+ sim_debug (DBG_ROP, gpx_dev, " Slow Source 1 DY: %d\n", va_adp[ADP_SSDY]);
+ }
+ if (cmd & 0x1000) {
+ sim_debug (DBG_ROP, gpx_dev, " Source 2 X Origin: %d\n", va_adp[ADP_S2XO]);
+ sim_debug (DBG_ROP, gpx_dev, " Source 2 Y Origin: %d\n", va_adp[ADP_S2YO]);
+ sim_debug (DBG_ROP, gpx_dev, " Source 2 Height/Width: %04X\n", va_adp[ADP_S2HW]);
+ }
+ sim_debug (DBG_ROP, gpx_dev, " Destination Indexing: %s\n", (va_adp[ADP_MDE]& 0x40) ? "Enabled" : "Disabled");
+ sim_debug (DBG_ROP, gpx_dev, " Destination X Origin: %d\n", va_adp[ADP_DXO]);
+ sim_debug (DBG_ROP, gpx_dev, " Destination Y Origin: %d\n", va_adp[ADP_DYO]);
+ sim_debug (DBG_ROP, gpx_dev, " Fast Destination DX: %d\n", va_adp[ADP_FDX]);
+ sim_debug (DBG_ROP, gpx_dev, " Fast Destination DY: %d\n", va_adp[ADP_FDY]);
+ sim_debug (DBG_ROP, gpx_dev, " Slow Destination DX: %d\n", va_adp[ADP_SDX]);
+ sim_debug (DBG_ROP, gpx_dev, " Slow Destination DY: %d\n", va_adp[ADP_SDY]);
+ sim_debug (DBG_ROP, gpx_dev, " Fast Scale: %d\n", va_adp[ADP_FS]);
+ sim_debug (DBG_ROP, gpx_dev, " Slow Scale: %d\n", va_adp[ADP_SS]);
+ switch (va_adp[ADP_MDE] & 0x3) {
+ case 0: /* normal */
+ case 2: /* linear pattern */
+ va_fifo_clr ();
+ va_adpstat (ADPSTAT_IC, (ADPSTAT_AC | ADPSTAT_RC));
+ va_unit[1].CMD = CMD_ROP;
+ va_adp_setup ();
+ va_rop (&va_unit[1]);
+ break;
+ case 3: /* fill */
+ va_fifo_clr ();
+ va_adpstat (ADPSTAT_IC, (ADPSTAT_AC | ADPSTAT_RC));
+ va_unit[1].CMD = CMD_ROP;
+ va_fill_setup ();
+ va_fill (&va_unit[1]);
+ break;
+ }
+ return;
+
+ case 7: /* processor to bitmap */
+ lu = (cmd >> 4) & 0x3; /* get logic unit */
+ sim_debug (DBG_ROP, gpx_dev, "Command: PTB\n");
+ sim_debug (DBG_ROP, gpx_dev, " Mode: %s\n", (cmd & 0x40) ? "X-Mode" : "Z-Mode");
+ sim_debug (DBG_ROP, gpx_dev, " Select: %X\n", va_ucs);
+ sim_debug (DBG_ROP, gpx_dev, " Clip: (%d, %d, %d, %d)\n", va_adp[ADP_CXMN], va_adp[ADP_CYMN], va_adp[ADP_CXMX], va_adp[ADP_CYMX]);
+ sim_debug (DBG_ROP, gpx_dev, " Pen: %s\n", (va_adp[ADP_MDE] & 0x80) ? "Down" : "Up");
+ sim_debug (DBG_ROP, gpx_dev, " Logic Unit: %d\n", lu);
+ if ((cmd & 0x40) == 0) {
+ lu = 2; /* always use logic unit 2 for Z-mode */
+ sim_debug (DBG_ROP, gpx_dev, " Z-Mode: %s\n", (cmd & 0x8) ? "Background" : "Foreground");
+ if (cmd & 0x8)
+ sim_printf ("Warning: PTB-Z with background selected at %08X\n", fault_PC);
+ }
+ rg = (cmd & 0x7);
+ for (sel = va_ucs, cn = 0; sel; sel >>=1, cn++) {
+ if (sel & 1) { /* chip selected? */
+ sim_debug (DBG_ROP, gpx_dev, " [%d] Function: %s\n", cn, va_fnc[va_vdp[cn].rg[0x4 + lu] & 0xF]);
+ sim_debug (DBG_ROP, gpx_dev, " [%d] Mask 1: %04X (%s)\n", cn, va_vdp[cn].rg[VDP_MSK1], (va_vdp[cn].rg[0x4 + lu] & 0x10) ? "Complement" : "Enabled");
+ sim_debug (DBG_ROP, gpx_dev, " [%d] Mask 2: %04X (%s)\n", cn, va_vdp[cn].rg[VDP_MSK2], (va_vdp[cn].rg[0x4 + lu] & 0x20) ? "Complement" : "Enabled");
+ sim_debug (DBG_ROP, gpx_dev, " [%d] Source: %04X (%s)\n", cn, va_vdp[cn].rg[VDP_SRC], (va_vdp[cn].rg[0x4 + lu] & 0x40) ? "Enabled" : "Complement");
+ sim_debug (DBG_ROP, gpx_dev, " [%d] Resolution Mode: %s\n", cn, (va_vdp[cn].rg[0x4 + lu] & 0x40) ? "Disabled" : "Enabled");
+ sim_debug (DBG_ROP, gpx_dev, " [%d] Foreground: %04X\n", cn, va_vdp[cn].rg[VDP_FG]);
+ sim_debug (DBG_ROP, gpx_dev, " [%d] Background: %04X\n", cn, va_vdp[cn].rg[VDP_BG]);
+ sim_debug (DBG_ROP, gpx_dev, " [%d] Fill: %04X\n", cn, va_vdp[cn].rg[VDP_FILL]);
+ if (va_vdp[cn].rg[VDP_CSR0 + rg] & 0x10) {
+ sim_debug (DBG_ROP, gpx_dev, " [%d] Broadcast: Enabled\n", cn);
+ }
+ switch (va_vdp[cn].rg[VDP_CSR0 + rg] & 0xC) {
+ case 0x0:
+ sim_debug (DBG_ROP, gpx_dev, " [%d] Internal: None\n", cn);
+ break;
+ case 0x4:
+ sim_debug (DBG_ROP, gpx_dev, " [%d] Internal: Source\n", cn);
+ break;
+ case 0x8:
+ sim_debug (DBG_ROP, gpx_dev, " [%d] Internal: Mask 1 & 2\n", cn);
+ break;
+ case 0xC:
+ sim_debug (DBG_ROP, gpx_dev, " [%d] Internal: Mask 2\n", cn);
+ break;
+ }
+ switch (va_vdp[cn].rg[VDP_CSR0 + rg] & 0x3) {
+ case 0x0:
+ sim_debug (DBG_ROP, gpx_dev, " [%d] External: None\n", cn);
+ break;
+ case 0x1:
+ sim_debug (DBG_ROP, gpx_dev, " [%d] External: Source\n", cn);
+ break;
+ case 0x2:
+ sim_debug (DBG_ROP, gpx_dev, " [%d] External: Mask 1 & 2\n", cn);
+ break;
+ case 0x3:
+ sim_debug (DBG_ROP, gpx_dev, " [%d] External: Mask 2\n", cn);
+ break;
+ }
+ }
+ }
+ sim_debug (DBG_ROP, gpx_dev, " X Index: %d\n", va_adp[ADP_NXI]);
+ sim_debug (DBG_ROP, gpx_dev, " Y Index: %d\n", va_adp[ADP_NYI]);
+ sim_debug (DBG_ROP, gpx_dev, " Destination Indexing: %s\n", (va_adp[ADP_MDE]& 0x40) ? "Enabled" : "Disabled");
+ sim_debug (DBG_ROP, gpx_dev, " Destination X Origin: %d\n", va_adp[ADP_DXO]);
+ sim_debug (DBG_ROP, gpx_dev, " Destination Y Origin: %d\n", va_adp[ADP_DYO]);
+ sim_debug (DBG_ROP, gpx_dev, " Fast Destination DX: %d\n", va_adp[ADP_FDX]);
+ sim_debug (DBG_ROP, gpx_dev, " Fast Destination DY: %d\n", va_adp[ADP_FDY]);
+ sim_debug (DBG_ROP, gpx_dev, " Slow Destination DX: %d\n", va_adp[ADP_SDX]);
+ sim_debug (DBG_ROP, gpx_dev, " Slow Destination DY: %d\n", va_adp[ADP_SDY]);
+ sim_debug (DBG_ROP, gpx_dev, " Fast Scale: %d\n", va_adp[ADP_FS]);
+ sim_debug (DBG_ROP, gpx_dev, " Slow Scale: %d\n", va_adp[ADP_SS]);
+ va_fifo_clr ();
+ va_adpstat (ADPSTAT_IC, (ADPSTAT_AC | ADPSTAT_RC));
+ if (cmd & 0x40)
+ va_unit[1].CMD = CMD_PTBX; /* X-Mode */
+ else
+ va_unit[1].CMD = CMD_PTBZ; /* Z-Mode */
+ va_adp_setup ();
+ if (va_adp[ADP_STAT] & ADPSTAT_IRR) /* data in FIFO? */
+ va_ptb (&va_unit[1], (va_unit[1].CMD == CMD_PTBZ));
+ return;
+ }
+sim_debug (DBG_ROP, gpx_dev, "Command: Unknown(%02X)\n", cmd);
+}
+
+void va_scmd (int32 cmd)
+{
+uint32 sel, cn, val, rg;
+uint32 adp_opc = (cmd >> 8) & 0x7;
+
+/* Commands on page 3-74 */
+
+switch (adp_opc) { /* address processor opcode */
+
+ case 0: /* cancel */
+ sim_debug (DBG_ROP, gpx_dev, "Scroll Command: Cancel\n");
+ return;
+
+ case 1: /* register load */
+ /* Video processor chip registers on page 3-82 */
+ if (cmd & 0x80) {
+ if (cmd & 0x20) { /* I/D Bus Z-Axis Register Load */
+ rg = ((cmd >> 2) & 3);
+ val = va_adp[ADP_IDS];
+ sim_debug (DBG_VDP, gpx_dev, "vdp_wr: z-reg[%X, %X] = %X\n", rg, (cmd & 0x3), val);
+ switch (rg) {
+ case 0:
+ rg = VDP_SRC;
+ break;
+ case 1:
+ rg = VDP_FG;
+ break;
+ case 2:
+ rg = VDP_FILL;
+ break;
+ case 3:
+ rg = VDP_BG;
+ break;
+ }
+ for (sel = va_scs, cn = 0; sel; sel >>=1, cn++) {
+ if (sel & 1) { /* chip selected? */
+ if (val & (1u << cn))
+ va_vdp_wr (cn, rg, 0xFFFF);
+ else
+ va_vdp_wr (cn, rg, 0);
+ }
+ }
+ }
+ else { /* I/D Bus Video Processor Register Load */
+ rg = (cmd & 0x1F);
+ val = va_adp[ADP_IDS];
+ for (sel = va_scs, cn = 0; sel; sel >>=1, cn++) {
+ if (sel & 1) /* chip selected? */
+ va_vdp_wr (cn, rg, val);
+ }
+ }
+ }
+ else { /* I/D Bus External Register Load */
+ switch (cmd & 0xff) {
+ case 0x40: /* scroll chip select */
+ va_scs = va_adp[ADP_IDS];
+ va_scs = va_scs & VA_PLANE_MASK;
+ sim_debug (DBG_VDP, gpx_dev, "scs_sel: %X (%X) at %08X\n", va_scs, (cmd & 0x7F), fault_PC);
+ break;
+
+ case 0x60: /* update chip select (green update mask) */
+ va_ucs = va_adp[ADP_IDS];
+ va_ucs = va_ucs & VA_PLANE_MASK;
+ sim_debug (DBG_VDP, gpx_dev, "ucs_sel: %X (%X) at %08X\n", va_ucs, (cmd & 0x7F), fault_PC);
+ break;
+
+ case 0x30: /* red update mask */
+ break;
+
+ case 0x18: /* blue update mask */
+ break;
+ }
+ }
+ return;
+
+ case 3: /* bitmap to processor */
+ sim_debug (DBG_ROP, gpx_dev, "Scroll Command: BTP\n");
+ return;
+
+ case 6: /* rasterop */
+ sim_debug (DBG_ROP, gpx_dev, "Scroll Command: ROP\n");
+ return;
+
+ case 7: /* processor to bitmap */
+ sim_debug (DBG_ROP, gpx_dev, "Scroll Command: PTB\n");
+ return;
+ }
+sim_debug (DBG_ROP, gpx_dev, "Scroll Command: Unknown(%02X)\n", cmd);
+}
+
+void va_scroll ()
+{
+uint32 x_min, x_max, y_min, y_max, x_lim;
+uint32 src, dest;
+int32 y_old, y_new;
+uint32 x, y, x_size, y_size;
+uint32 vscroll, hscroll;
+uint32 sel, cn;
+
+va_adpstat (ADPSTAT_SC, 0); /* scroll service */
+
+if ((va_adp[ADP_PYSC] & 0x8000) == 0) /* scroll required? */
+ return;
+
+if (va_adp[ADP_PYSC] & 0x1000) { /* down scrolling? */
+ vscroll = va_adp[ADP_PYSC] & 0xFFF;
+ if (vscroll != 0) { /* scroll required? */
+ sel = 0;
+ for (cn = 0; cn < VA_PLANES; cn++) {
+ if (va_vdp[cn].rg[VDP_SC] & 0x20) /* scrolling enabled? */
+ sel = sel | (1u << va_vdp[cn].rg[VDP_PA]);
+ }
+ if (sel) {
+ sim_debug (DBG_ROP, gpx_dev, "Scrolling planes %X down by %d pixels (%d, %d, %d, %d)\n", sel, vscroll, va_adp[ADP_PXMN], va_adp[ADP_PYMN], va_adp[ADP_PXMX], va_adp[ADP_PYMX]);
+ x_size = va_adp[ADP_PXMX] - va_adp[ADP_PXMN];
+ y_size = va_adp[ADP_PYMX] - va_adp[ADP_PYMN] - vscroll;
+ y_old = va_adp[ADP_PYOF];
+ y_new = va_adp[ADP_PYOF] - vscroll;
+ if (y_new < 0)
+ y_new = y_new + va_adp[ADP_YL];
+ dest = (y_new * VA_XSIZE);
+ src = (y_old * VA_XSIZE);
+ for (y = 0; y < 864; y++) {
+ if ((y_old >= va_adp[ADP_PYMN]) && (y_old < va_adp[ADP_PYMX])) {
+ for (x = 0; x < (uint32)va_adp[ADP_PXMN]; x++) {
+ va_buf[dest] = va_buf[dest] & ~sel;
+ va_buf[dest] |= (va_buf[src++] & sel);
+ sim_debug (DBG_ROP, gpx_dev, "(%d, %d) -> (%d, %d) = %X\n", x, y_old, x, y_new, va_buf[dest]);
+ dest++;
+ }
+ dest = dest + x_size;
+ src = src + x_size;
+ for (x = va_adp[ADP_PXMX]; x < 1024; x++) {
+ va_buf[dest] = va_buf[dest] & ~sel;
+ va_buf[dest] |= (va_buf[src++] & sel);
+ sim_debug (DBG_ROP, gpx_dev, "(%d, %d) -> (%d, %d) = %X\n", x, y_old, x, y_new, va_buf[dest]);
+ dest++;
+ }
+ }
+ else {
+ for (x = 0; x < 1024; x++) {
+ va_buf[dest] = va_buf[dest] & ~sel;
+ va_buf[dest] |= (va_buf[src++] & sel);
+ sim_debug (DBG_ROP, gpx_dev, "(%d, %d) -> (%d, %d) = %X\n", x, y_old, x, y_new, va_buf[dest]);
+ dest++;
+ }
+ }
+ va_updated[y_new] = TRUE;
+ y_new++;
+ if (y_new == va_adp[ADP_YL]) {
+ y_new = 0;
+ dest = 0;
+ }
+ y_old++;
+ if (y_old == va_adp[ADP_YL]) {
+ y_old = 0;
+ src = 0;
+ }
+ }
+ va_erase (va_adp[ADP_PXMN], va_adp[ADP_PXMX], va_adp[ADP_PYMN] - vscroll, va_adp[ADP_PYMN]);
+ }
+ }
+ }
+else { /* up, left or right */
+ vscroll = va_adp[ADP_PYSC] & 0xFFF;
+ if (vscroll != 0) { /* scroll required? */
+ sel = 0;
+ for (cn = 0; cn < VA_PLANES; cn++) {
+ if (va_vdp[cn].rg[VDP_SC] & 0x20) /* scrolling enabled? */
+ sel = sel | (1u << va_vdp[cn].rg[VDP_PA]);
+ }
+ if (sel) {
+ sim_debug (DBG_ROP, gpx_dev, "Scrolling planes %X up by %d pixels (%d, %d, %d, %d)\n", sel, vscroll, va_adp[ADP_PXMN], va_adp[ADP_PYMN], va_adp[ADP_PXMX], va_adp[ADP_PYMX]);
+ x_size = va_adp[ADP_PXMX] - va_adp[ADP_PXMN];
+ y_size = va_adp[ADP_PYMX] - va_adp[ADP_PYMN] - vscroll;
+ y_old = va_adp[ADP_PYMN] + vscroll;
+ y_new = va_adp[ADP_PYMN];
+ dest = (y_new * VA_XSIZE) + va_adp[ADP_PXMN];
+ src = (y_old * VA_XSIZE) + va_adp[ADP_PXMN];
+ for (y = 0; y < y_size; y++) {
+ for (x = 0; x < x_size; x++) {
+ va_buf[dest] = va_buf[dest] & ~sel;
+ va_buf[dest] |= (va_buf[src++] & sel);
+ sim_debug (DBG_ROP, gpx_dev, "(%d, %d) -> (%d, %d) = %X\n", (x + va_adp[ADP_PXMN]), (y_old + y), (x + va_adp[ADP_PXMN]), (y_new + y), va_buf[dest]);
+ dest++;
+ }
+ va_updated[y_new + y] = TRUE;
+ dest = dest + (VA_XSIZE - x_size);
+ src = src + (VA_XSIZE - x_size);
+ }
+ va_erase (va_adp[ADP_PXMN], va_adp[ADP_PXMX], va_adp[ADP_PYMX] - vscroll, va_adp[ADP_PYMX]);
+ }
+ }
+ for (cn = 0; cn < VA_PLANES; cn++) {
+ if (va_vdp[cn].rg[VDP_SC] & 0x20) { /* scrolling enabled? */
+ if (va_vdp[cn].rg[VDP_SC] & 0xF) { /* scroll required? */
+ sim_debug (DBG_ROP, gpx_dev, "Scrolling plane %d %s by %d pixels (%d, %d, %d, %d)\n", cn,
+ (va_vdp[cn].rg[VDP_SC] & 0x10) ? "right" : "left",
+ (va_vdp[cn].rg[VDP_SC] & 0xF),
+ va_adp[ADP_PXMN], va_adp[ADP_PYMN], va_adp[ADP_PXMX], va_adp[ADP_PYMX]);
+ hscroll = va_vdp[cn].rg[VDP_SC] & 0xF;
+ if (va_vdp[cn].rg[VDP_SC] & 0x10) { /* right */
+ hscroll++;
+ y_min = va_adp[ADP_PYMN];
+ y_max = va_adp[ADP_PYMX];
+ if (y_max > VA_YSIZE)
+ y_max = VA_YSIZE;
+ x_min = va_adp[ADP_PXMN];
+ x_max = va_adp[ADP_PXMX] - 1;
+ if (x_max > VA_XSIZE)
+ x_max = VA_XSIZE;
+ x_lim = x_min + hscroll;
+ dest = (va_adp[ADP_PYMN] * VA_XSIZE) + va_adp[ADP_PXMX] - 1;
+ src = (va_adp[ADP_PYMN] * VA_XSIZE) + va_adp[ADP_PXMX] - hscroll - 1;
+ for (y = y_min; y < y_max; y++) {
+ for (x = x_max; x >= x_min; x--) {
+ va_buf[dest] = va_buf[dest] & ~(1u << va_vdp[cn].rg[VDP_PA]);
+ if (x >= x_lim) {
+ sim_debug (DBG_ROP, gpx_dev, "(%d, %d) copy pixel %X (%d = %d), %X (%d = %d) -> ", x, y, va_buf[src], src, (src & 1023), va_buf[dest], dest, (dest & 1023));
+ va_buf[dest] |= (va_buf[src--] & (1u << va_vdp[cn].rg[VDP_PA]));
+ sim_debug (DBG_ROP, gpx_dev, "%X\n", va_buf[dest]);
+ dest--;
+ }
+ else {
+ sim_debug (DBG_ROP, gpx_dev, "(%d, %d) fill pixel %X (%d = %d) -> ", x, y, va_buf[dest], dest, (dest & 1023));
+ va_buf[dest] |= (((va_vdp[cn].rg[VDP_FILL] >> (x & 0xF)) & 0x1) << va_vdp[cn].rg[VDP_PA]);
+ sim_debug (DBG_ROP, gpx_dev, "%X\n", va_buf[dest]);
+ dest--;
+ src--;
+ }
+ }
+ va_updated[y] = TRUE;
+ dest = dest + (VA_XSIZE + (x_max - x_min)) + 1;
+ src = src + (VA_XSIZE + (x_max - x_min)) + 1;
+ }
+ }
+ else { /* left */
+ y_min = va_adp[ADP_PYMN];
+ y_max = va_adp[ADP_PYMX];
+ if (y_max > VA_YSIZE)
+ y_max = VA_YSIZE;
+ x_min = va_adp[ADP_PXMN];
+ x_max = va_adp[ADP_PXMX];
+ if (x_max > VA_XSIZE)
+ x_max = VA_XSIZE;
+ x_lim = x_max - hscroll;
+ dest = (va_adp[ADP_PYMN] * VA_XSIZE) + va_adp[ADP_PXMN];
+ src = (va_adp[ADP_PYMN] * VA_XSIZE) + va_adp[ADP_PXMN] + hscroll;
+ for (y = y_min; y < y_max; y++) {
+ for (x = x_min; x < x_max; x++) {
+ va_buf[dest] = va_buf[dest] & ~(1u << va_vdp[cn].rg[VDP_PA]);
+ if (x < x_lim) {
+ sim_debug (DBG_ROP, gpx_dev, "(%d, %d) copy pixel %X (%d = %d), %X (%d = %d) -> ", x, y, va_buf[src], src, (src & 1023), va_buf[dest], dest, (dest & 1023));
+ va_buf[dest] |= (va_buf[src++] & (1u << va_vdp[cn].rg[VDP_PA]));
+ sim_debug (DBG_ROP, gpx_dev, "%X\n", va_buf[dest]);
+ dest++;
+ }
+ else {
+ sim_debug (DBG_ROP, gpx_dev, "(%d, %d) fill pixel %X (%d = %d) -> ", x, y, va_buf[dest], dest, (dest & 1023));
+ va_buf[dest] |= (((va_vdp[cn].rg[VDP_FILL] >> (x & 0xF)) & 0x1) << va_vdp[cn].rg[VDP_PA]);
+ sim_debug (DBG_ROP, gpx_dev, "%X\n", va_buf[dest]);
+ dest++;
+ src++;
+ }
+ }
+ va_updated[y] = TRUE;
+ dest = dest + (VA_XSIZE - (x_max - x_min));
+ src = src + (VA_XSIZE - (x_max - x_min));
+ }
+ }
+ }
+ }
+ }
+ }
+va_adp[ADP_PYSC] = 0;
+}
+
+void va_adp_setup ()
+{
+int32 sx, sy;
+uint32 pix;
+
+sim_debug (DBG_ROP, gpx_dev, "ROP: ");
+if (va_adp[ADP_CMD1] & 0x800) { /* source 1 enabled? */
+ pix = 0;
+ sx = 0;
+ sy = 0;
+ if (va_adp[ADP_MDE] & 0x20) { /* source indexing enable? */
+ pix = pix + va_adp[ADP_NXI]; /* apply indexing */
+ pix = pix + (va_adp[ADP_NYI] * VA_XSIZE);
+ sx = sx + va_adp[ADP_NXI];
+ sy = sy + va_adp[ADP_NYI];
+ }
+ pix = pix + va_adp[ADP_SXO]; /* apply offset */
+ pix = pix + (va_adp[ADP_SYO] * VA_XSIZE);
+ pix = pix + (va_adp[ADP_PYOF] * VA_XSIZE);
+ pix = pix & VA_BUFMASK;
+ sx = sx + va_adp[ADP_SXO];
+ sy = sy + va_adp[ADP_SYO];
+
+ if ((va_adp[ADP_MDE] & 0x3) == 0) { /* normal mode */
+ if ((va_adp[ADP_FSDX] < 0) && (va_adp[ADP_FDX] > 0))
+ va_line_init (&s1_fast, -va_adp[ADP_FDX], 0, pix);
+ else
+ va_line_init (&s1_fast, va_adp[ADP_FDX], 0, pix);
+
+ if ((va_adp[ADP_SSDY] < 0) && (va_adp[ADP_SDY] > 0))
+ va_line_init (&s1_slow, 0, -va_adp[ADP_SDY], pix);
+ else
+ va_line_init (&s1_slow, 0, va_adp[ADP_SDY], pix);
+ }
+ else { /* linear pattern mode */
+ va_line_init (&s1_fast, va_adp[ADP_FSDX], 0, pix);
+ va_line_init (&s1_slow, 0, va_adp[ADP_SSDY], pix);
+ }
+
+ sim_debug (DBG_ROP, gpx_dev, "Source 1 (%d, %d, %d, %d) ", sx, sy, (sx + va_adp[ADP_FDX]), (sy + va_adp[ADP_SDY]));
+ }
+
+if (va_adp[ADP_CMD1] & 0x1000) { /* source 2 enabled? */
+ s2_xmask = va_adp[ADP_S2HW] & 0x7;
+ s2_xmask = (1u << (s2_xmask + 2)) - 1;
+ s2_ymask = (va_adp[ADP_S2HW] >> 4) & 0x7;
+ s2_ymask = (1u << (s2_ymask + 2)) - 1;
+ s2_pixs = 0;
+ s2_pixs = s2_pixs + va_adp[ADP_S2XO]; /* apply offset */
+ s2_pixs = s2_pixs + (va_adp[ADP_S2YO] * VA_XSIZE);
+ s2_pixs = s2_pixs & VA_BUFMASK;
+ sx = va_adp[ADP_S2XO];
+ sy = va_adp[ADP_S2YO];
+ sim_debug (DBG_ROP, gpx_dev, "Source 2 (%d, %d, %d, %d) ", sx, sy, (sx + s2_xmask + 1), (sy + s2_ymask + 1));
+ }
+
+pix = 0;
+dx = 0;
+dy = 0;
+if (va_adp[ADP_MDE] & 0x40) { /* dest indexing enable? */
+ pix = pix + va_adp[ADP_NXI]; /* apply indexing */
+ pix = pix + (va_adp[ADP_NYI] * VA_XSIZE);
+ dx = dx + va_adp[ADP_NXI];
+ dy = dy + va_adp[ADP_NYI];
+ }
+pix = pix + va_adp[ADP_DXO]; /* apply offset */
+pix = pix + (va_adp[ADP_DYO] * VA_XSIZE);
+pix = pix + (va_adp[ADP_PYOF] * VA_XSIZE);
+pix = pix & VA_BUFMASK;
+dx = dx + va_adp[ADP_DXO];
+dy = dy + va_adp[ADP_DYO];
+
+va_line_init (&dst_fast, va_adp[ADP_FDX], va_adp[ADP_FDY], pix);
+va_line_init (&dst_slow, va_adp[ADP_SDX], va_adp[ADP_SDY], pix);
+
+dst_slow.err = dst_slow.err + va_adp[ADP_ERR1];
+dst_fast.err = dst_fast.err + va_adp[ADP_ERR2];
+
+if ((va_adp[ADP_CMD1] & 0x400) && (va_adp[ADP_MDE] & 0x80)) /* dest enabled, pen down? */
+ sim_debug (DBG_ROP, gpx_dev, "-> Dest (%d, %d, %d, %d)", dx, dy, (dx + va_adp[ADP_FDX]), (dy + va_adp[ADP_SDY]));
+sim_debug (DBG_ROP, gpx_dev, "\n");
+}
+
+void va_fill_setup ()
+{
+int32 sx, sy;
+uint32 pix;
+
+sim_debug (DBG_ROP, gpx_dev, "ROP: Fill ");
+
+pix = 0;
+if (va_adp[ADP_MDE] & 0x40) { /* dest indexing enable? */
+ pix = pix + va_adp[ADP_NXI]; /* apply indexing */
+ pix = pix + (va_adp[ADP_NYI] * VA_XSIZE);
+ }
+pix = pix + va_adp[ADP_SXO]; /* apply offset */
+pix = pix + (va_adp[ADP_SYO] * VA_XSIZE);
+pix = pix + (va_adp[ADP_PYOF] * VA_XSIZE);
+pix = pix & VA_BUFMASK;
+
+va_line_init (&s1_slow, va_adp[ADP_FSDX], va_adp[ADP_SSDY], pix);
+
+if (va_adp[ADP_CMD1] & 0x1000) { /* source 2 enabled? */
+ s2_xmask = va_adp[ADP_S2HW] & 0x7;
+ s2_xmask = (1u << (s2_xmask + 2)) - 1;
+ s2_ymask = (va_adp[ADP_S2HW] >> 4) & 0x7;
+ s2_ymask = (1u << (s2_ymask + 2)) - 1;
+ s2_pixs = 0;
+ s2_pixs = s2_pixs + va_adp[ADP_S2XO]; /* apply offset */
+ s2_pixs = s2_pixs + (va_adp[ADP_S2YO] * VA_XSIZE);
+ s2_pixs = s2_pixs & VA_BUFMASK;
+ sx = va_adp[ADP_S2XO];
+ sy = va_adp[ADP_S2YO];
+ sim_debug (DBG_ROP, gpx_dev, "Source 2 (%d, %d, %d, %d) ", sx, sy, (sx + s2_xmask + 1), (sy + s2_ymask + 1));
+ }
+
+pix = 0;
+dx = 0;
+dy = 0;
+if (va_adp[ADP_MDE] & 0x40) { /* dest indexing enable? */
+ pix = pix + va_adp[ADP_NXI]; /* apply indexing */
+ pix = pix + (va_adp[ADP_NYI] * VA_XSIZE);
+ dx = dx + va_adp[ADP_NXI];
+ dy = dy + va_adp[ADP_NYI];
+ }
+pix = pix + va_adp[ADP_DXO]; /* apply offset */
+pix = pix + (va_adp[ADP_DYO] * VA_XSIZE);
+pix = pix + (va_adp[ADP_PYOF] * VA_XSIZE);
+pix = pix & VA_BUFMASK;
+dx = dx + va_adp[ADP_DXO];
+dy = dy + va_adp[ADP_DYO];
+
+va_line_init (&dst_slow, va_adp[ADP_SDX], va_adp[ADP_SDY], pix);
+
+dst_slow.err = dst_slow.err + va_adp[ADP_ERR1];
+s1_slow.err = s1_slow.err + va_adp[ADP_ERR2];
+
+sim_debug (DBG_ROP, gpx_dev, "\n");
+}
+
+t_stat va_ptb (UNIT *uptr, t_bool zmode)
+{
+uint32 val, sc;
+t_bool clip;
+
+if ((uptr->CMD != CMD_PTBX) && (uptr->CMD != CMD_PTBZ))
+ return SCPE_OK;
+for (;;) {
+ if (zmode) {
+ if ((va_adp[ADP_STAT] & ADPSTAT_IRR) == 0) /* no data in FIFO? */
+ return SCPE_OK;
+ val = va_fifo_rd (); /* read FIFO */
+ }
+ else {
+ sc = (dst_fast.x + dx) & 0xF;
+ if ((sc == 0) || (dst_fast.x == 0)) {
+ if ((va_adp[ADP_STAT] & ADPSTAT_IRR) == 0) /* no data in FIFO? */
+ return SCPE_OK;
+ val = va_fifo_rd (); /* read FIFO */
+ }
+ }
+ clip = FALSE;
+ if ((dst_fast.x + dx) < va_adp[ADP_CXMN]) {
+ va_adp[ADP_STAT] |= ADPSTAT_CL;
+ clip = TRUE;
+ }
+ else if ((dst_fast.x + dx) > va_adp[ADP_CXMX]) {
+ va_adp[ADP_STAT] |= ADPSTAT_CR;
+ clip = TRUE;
+ }
+ if ((dst_fast.y + dy) < va_adp[ADP_CYMN]) {
+ va_adp[ADP_STAT] |= ADPSTAT_CT;
+ clip = TRUE;
+ }
+ else if ((dst_fast.y + dy) > va_adp[ADP_CYMX]) {
+ va_adp[ADP_STAT] |= ADPSTAT_CB;
+ clip = TRUE;
+ }
+ if ((va_adp[ADP_CMD1] & 0x400) && (va_adp[ADP_MDE] & 0x80) && !clip) { /* dest enabled, pen down? */
+ if (zmode)
+ va_buf[dst_fast.pix] = val & VA_PLANE_MASK;
+ else {
+ if (val & (1u << sc))
+ va_buf[dst_fast.pix] = va_buf[dst_fast.pix] | va_ucs; /* set pixel in selected chips */
+ else
+ va_buf[dst_fast.pix] = va_buf[dst_fast.pix] & ~va_ucs; /* clear pixel in selected chips */
+ }
+ sim_debug (DBG_ROP, gpx_dev, "-> Dest X: %d, Y: %d, pix: %X\n", dst_fast.x, dst_slow.y, va_buf[dst_fast.pix]);
+ va_updated[dst_slow.y + dst_fast.y + dy] = TRUE;
+ }
+
+ if (va_line_step (&dst_fast)) { /* fast vector exhausted? */
+ if (va_line_step (&dst_slow)) /* slow vector exhausted? */
+ break; /* finished */
+ dst_fast.pix = dst_slow.pix;
+ }
+ }
+sim_debug (DBG_ROP, gpx_dev, "PTB Complete\n");
+uptr->CMD = 0;
+va_adpstat (ADPSTAT_AC | ADPSTAT_RC, 0);
+return SCPE_OK;
+}
+
+t_stat va_btp (UNIT *uptr, t_bool zmode)
+{
+uint32 val, sc;
+
+if ((uptr->CMD != CMD_BTPX) && (uptr->CMD != CMD_BTPZ))
+ return SCPE_OK;
+if ((va_adp[ADP_STAT] & ADPSTAT_RC) && (va_adp_fifo_sz == 0)) {
+ uptr->CMD = 0;
+ va_adpstat (ADPSTAT_AC, 0);
+ return SCPE_OK;
+ }
+for (val = 0;;) {
+ if (zmode) {
+ if ((va_adp[ADP_STAT] & ADPSTAT_ITR) == 0) /* no space in FIFO? */
+ return SCPE_OK;
+ val = 0;
+ }
+ else {
+ sc = s1_fast.x & 0xF;
+ if (sc == 0) {
+ if ((va_adp[ADP_STAT] & ADPSTAT_ITR) == 0) /* no space in FIFO? */
+ return SCPE_OK;
+ val = 0;
+ }
+ }
+ if (va_adp[ADP_CMD1] & 0x800) { /* source 1 enabled? */
+ sim_debug (DBG_ROP, gpx_dev, "Source X: %d, Y: %d, pix: %X\n", s1_fast.x, s1_slow.y, va_buf[s1_fast.pix]);
+ if (zmode)
+ val = (va_buf[s1_fast.pix] & VA_PLANE_MASK);
+ else {
+ if (va_buf[s1_fast.pix] & va_ucs)
+ val |= (1u << sc);
+ }
+ }
+ if (zmode || (sc == 0xF))
+ va_fifo_wr (val);
+ if (va_line_step (&s1_fast)) { /* fast vector exhausted? */
+ if (!zmode && (sc != 0xF))
+ va_fifo_wr (val);
+ if (va_line_step (&s1_slow)) /* slow vector exhausted? */
+ break; /* finished */
+ s1_fast.pix = s1_slow.pix;
+ }
+ }
+sim_debug (DBG_ROP, gpx_dev, "BTP Complete\n");
+/* FIXME - This is a temporary workaround for the QDSS. Address output complete
+ should not be set until the FIFO is empty */
+uptr->CMD = 0;
+va_adpstat (ADPSTAT_AC | ADPSTAT_RC, 0);
+return SCPE_OK;
+}
+
+void va_erase (uint32 x0, uint32 x1, uint32 y0, uint32 y1)
+{
+uint32 i, j, msk, val, x, y, dest;
+uint8 zfill[16];
+
+for (i = 0; i < 16; i++)
+ zfill[i] = 0;
+for (i = 0, msk = 1; i < 8; i++, msk <<= 1) { /* for each viper */
+ val = va_vdp[i].rg[VDP_FILL]; /* get the fill constant */
+ for (j = 0; j < 16; j++) {
+ if (val & 1)
+ zfill[j] = zfill[j] | msk; /* convert x-mode to z-mode */
+ val >>= 1;
+ }
+ }
+dest = (y0 * VA_XSIZE) + x0;
+for (y = y0; y < y1; y++) {
+ for (x = x0; x < x1; x++)
+ va_buf[dest++] = zfill[x & 0xF];
+ va_updated[y] = TRUE;
+ dest = dest + VA_XSIZE - (x1 - x0);
+ }
+sim_debug (DBG_ROP, gpx_dev, "Erase Complete\n");
+}
+
+t_stat va_adp_reset (DEVICE *dptr)
+{
+gpx_dev = dptr;
+va_fifo_clr ();
+va_adp[ADP_STAT] |= 0x3FFF;
+va_ucs = 0;
+va_scs = 0;
+return SCPE_OK;
+}
+
+t_stat va_adp_svc (UNIT *uptr)
+{
+va_adpstat (ADPSTAT_VB, 0); /* vertical blanking */
+
+va_adp[ADP_OXI] = va_adp[ADP_NXI]; /* load pending index values */
+va_adp[ADP_OYI] = va_adp[ADP_NYI];
+va_adp[ADP_NXI] = va_adp[ADP_PXI];
+va_adp[ADP_NYI] = va_adp[ADP_PYI];
+
+va_scroll ();
+
+return SCPE_OK;
+}
diff --git a/VAX/vax_gpx.h b/VAX/vax_gpx.h
new file mode 100644
index 00000000..3cb6465c
--- /dev/null
+++ b/VAX/vax_gpx.h
@@ -0,0 +1,199 @@
+/* vax_gpx.h: GPX video common components
+
+ Copyright (c) 2019, Matt Burke
+
+ Permission is hereby granted, free of charge, to any person obtaining a
+ copy of this software and associated documentation files (the "Software"),
+ to deal in the Software without restriction, including without limitation
+ the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ and/or sell copies of the Software, and to permit persons to whom the
+ Software is furnished to do so, subject to the following conditions:
+
+ The above copyright notice and this permission notice shall be included in
+ all copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ THE AUTHOR BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+
+ Except as contained in this notice, the name of the author shall not be
+ used in advertising or otherwise to promote the sale, use or other dealings
+ in this Software without prior written authorization from the author.
+*/
+
+#ifndef VAX_GPX_H
+#define VAX_GPX_H 0
+
+#include "vax_defs.h"
+
+/* FIXME - Some or all of these should be dynamic */
+
+#define VA_PLANES 4
+#define VA_BPP (1u << VA_PLANES)
+#define VA_PLANE_MASK (VA_BPP - 1)
+
+#define VA_XSIZE 1024 /* visible width */
+#define VA_YSIZE 864 /* visible height */
+#define VA_BXSIZE 1024 /* video buffer width */
+#define VA_BYSIZE 2048 /* video buffer height */
+#define VA_BUFSIZE (1u << 21) /* video buffer size */
+#define VA_BUFMASK (VA_BUFSIZE - 1)
+
+/* Address processor (Adder) registers */
+
+#define ADP_ADCT 0x0 /* address counter */
+#define ADP_REQ 0x1 /* request enable */
+#define ADP_INT 0x2 /* interrupt enable */
+#define ADP_STAT 0x3 /* status */
+#define ADP_IDD 0x7 /* I/D data */
+#define ADP_CMD1 0x8 /* command */
+#define ADP_MDE 0x9 /* mode */
+#define ADP_CMD2 0xA /* command (alt) */
+#define ADP_IDS 0xC /* I/D scroll data */
+#define ADP_ICS 0xD /* I/D scroll command */
+#define ADP_PXMN 0xE /* scroll x min */
+#define ADP_PXMX 0xF /* scroll x max */
+#define ADP_PYMN 0x10 /* scroll y min */
+#define ADP_PYMX 0x11 /* scroll y max */
+#define ADP_PSE 0x12 /* pause */
+#define ADP_PYOF 0x13 /* y offset */
+#define ADP_PYSC 0x14 /* y scroll constant */
+#define ADP_PXI 0x15 /* pending x index */
+#define ADP_PYI 0x16 /* pending y index */
+#define ADP_NXI 0x17 /* new x index */
+#define ADP_NYI 0x18 /* new y index */
+#define ADP_OXI 0x19 /* old x index */
+#define ADP_OYI 0x1A /* old y index */
+#define ADP_CXMN 0x1B /* clip x min */
+#define ADP_CXMX 0x1C /* clip x max */
+#define ADP_CYMN 0x1D /* clip y min */
+#define ADP_CYMX 0x1E /* clip y max */
+#define ADP_FSDX 0x20 /* fast source 1 DX */
+#define ADP_SSDY 0x21 /* slow source 1 DY */
+#define ADP_SXO 0x22 /* source 1 X origin */
+#define ADP_SYO 0x23 /* source 1 Y origin */
+#define ADP_DXO 0x24 /* dest X origin */
+#define ADP_DYO 0x25 /* dest Y origin */
+#define ADP_FDX 0x26 /* fast dest DX */
+#define ADP_FDY 0x27 /* fast dest DY */
+#define ADP_SDX 0x28 /* slow dest DX */
+#define ADP_SDY 0x29 /* slow dest DY */
+#define ADP_FS 0x2A /* fast scale */
+#define ADP_SS 0x2B /* slow scale */
+#define ADP_S2XO 0x2C /* source 2 X origin */
+#define ADP_S2YO 0x2D /* source 2 Y origin */
+#define ADP_S2HW 0x2E /* source 2 height/width */
+#define ADP_ERR1 0x2F /* error 1 */
+#define ADP_ERR2 0x30 /* error 2 */
+#define ADP_YCT0 0x31 /* y scan count 0 */
+#define ADP_YCT1 0x32 /* y scan count 1 */
+#define ADP_YCT2 0x33 /* y scan count 2 */
+#define ADP_YCT3 0x34 /* y scan count 3 */
+#define ADP_XCON 0x35 /* x scan configuration */
+#define ADP_XL 0x36 /* x limit */
+#define ADP_YL 0x37 /* y limit */
+#define ADP_XCT0 0x38 /* x scan count 0 */
+#define ADP_XCT1 0x39 /* x scan count 1 */
+#define ADP_XCT2 0x3A /* x scan count 2 */
+#define ADP_XCT3 0x3B /* x scan count 3 */
+#define ADP_XCT4 0x3C /* x scan count 4 */
+#define ADP_XCT5 0x3D /* x scan count 5 */
+#define ADP_XCT6 0x3E /* x scan count 6 */
+#define ADP_SYNP 0x3F /* sync phase */
+#define ADP_MAXREG 0x3F
+#define ADP_NUMREG (ADP_MAXREG + 1)
+
+/* Adder status register */
+
+#define ADPSTAT_PC 0x0001 /* pause complete */
+#define ADPSTAT_SC 0x0002 /* scroll service */
+#define ADPSTAT_IC 0x0004 /* rasterop init complete */
+#define ADPSTAT_RC 0x0008 /* rasterop complete */
+#define ADPSTAT_AC 0x0010 /* address output complete */
+#define ADPSTAT_IRR 0x0020 /* I/D data rcv ready */
+#define ADPSTAT_ITR 0x0040 /* I/D data xmt ready */
+#define ADPSTAT_ISR 0x0080 /* I/D scroll data ready */
+#define ADPSTAT_CT 0x0100 /* rasterop clipped top */
+#define ADPSTAT_CB 0x0200 /* rasterop clipped bottom */
+#define ADPSTAT_CL 0x0400 /* rasterop clipped left */
+#define ADPSTAT_CR 0x0800 /* rasterop clipped right */
+#define ADPSTAT_CP (ADPSTAT_CT|ADPSTAT_CB|ADPSTAT_CL|ADPSTAT_CR)
+#define ADPSTAT_CN 0x1000 /* rasterop clipped none */
+#define ADPSTAT_VB 0x2000 /* vertical blanking */
+#define ADPSTAT_W0C 0x3F83
+
+#define INT_ADP 0 /* Adder interrupt */
+
+/* Video processor (Viper) registers */
+
+#define VDP_RES 0x0 /* resolution mode */
+#define VDP_BW 0x1 /* bus width */
+#define VDP_SC 0x2 /* scroll constant */
+#define VDP_PA 0x3 /* plane address */
+#define VDP_FNC0 0x4 /* logic function 0 */
+#define VDP_FNC1 0x5 /* logic function 1 */
+#define VDP_FNC2 0x6 /* logic function 2 */
+#define VDP_FNC3 0x7 /* logic function 3 */
+#define VDP_MSK1 0x8 /* mask 1 */
+#define VDP_MSK2 0x9 /* mask 2 */
+#define VDP_SRC 0xA /* source */
+#define VDP_FILL 0xB /* fill */
+#define VDP_LSB 0xC /* left scroll boundary */
+#define VDP_RSB 0xD /* right scroll boundary */
+#define VDP_BG 0xE /* background colour */
+#define VDP_FG 0xF /* foreground colour */
+#define VDP_CSR0 0x10 /* CSR 0 */
+#define VDP_CSR1 0x11 /* CSR 1 */
+#define VDP_CSR2 0x12 /* CSR 2 */
+#define VDP_CSR4 0x14 /* CSR 4 */
+#define VDP_CSR5 0x15 /* CSR 5 */
+#define VDP_CSR6 0x16 /* CSR 6 */
+#define VDP_MAXREG 0x17
+
+#define CMD u3
+
+#define CMD_NOP 0 /* no operation */
+#define CMD_BTPX 1 /* bitmap to processor (x-mode) */
+#define CMD_BTPZ 2 /* bitmap to processor (z-mode) */
+#define CMD_PTBX 3 /* processor to bitmap (x-mode) */
+#define CMD_PTBZ 4 /* processor to bitmap (z-mode) */
+#define CMD_ROP 5 /* rasterop */
+#define CMD_ERASE 6 /* erase region */
+
+/* Debugging Bitmaps */
+
+#define DBG_REG 0x0100 /* register activity */
+#define DBG_FIFO 0x0200 /* fifo activity */
+#define DBG_ADP 0x0400 /* adder activity */
+#define DBG_VDP 0x0800 /* viper activity */
+#define DBG_ROP 0x1000 /* raster operations */
+
+/* Internal functions/data - implemented by vax_gpx.c */
+
+int32 va_adp_rd (int32 rg);
+void va_adp_wr (int32 rg, int32 val);
+t_stat va_adp_reset (DEVICE *dptr);
+t_stat va_adp_svc (UNIT *uptr);
+t_stat va_vdp_reset (DEVICE *dptr);
+
+t_stat va_btp (UNIT *uptr, t_bool zmode);
+t_stat va_ptb (UNIT *uptr, t_bool zmode);
+void va_fifo_wr (uint32 val);
+uint32 va_fifo_rd (void);
+void va_adpstat (uint32 set, uint32 clr);
+
+extern int32 va_adp[ADP_NUMREG]; /* Address processor registers */
+
+/* External functions/data - implemented by machine specific device */
+
+extern void va_setint (int32 src);
+extern void va_clrint (int32 src);
+
+extern uint32 *va_buf; /* Video memory */
+extern t_bool va_updated[VA_BYSIZE];
+extern UNIT va_unit[];
+
+#endif
diff --git a/VAX/vax_va.c b/VAX/vax_va.c
new file mode 100644
index 00000000..4577c303
--- /dev/null
+++ b/VAX/vax_va.c
@@ -0,0 +1,1226 @@
+/* vax_va.c: QDSS video simulator
+
+ Copyright (c) 2019, Matt Burke
+
+ Permission is hereby granted, free of charge, to any person obtaining a
+ copy of this software and associated documentation files (the "Software"),
+ to deal in the Software without restriction, including without limitation
+ the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ and/or sell copies of the Software, and to permit persons to whom the
+ Software is furnished to do so, subject to the following conditions:
+
+ The above copyright notice and this permission notice shall be included in
+ all copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ THE AUTHOR BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+
+ Except as contained in this notice, the name of the author shall not be
+ used in advertising or otherwise to promote the sale, use or other dealings
+ in this Software without prior written authorization from the author.
+
+ va QDSS (VCB02)
+
+ Related documents:
+
+ EK-104AA-TM - VCB02 Video Subsystem Technical Manual
+ MP02083 - VCB02 Field Maintenance Print Set
+*/
+
+#include "vax_defs.h"
+#include "sim_video.h"
+#include "vax_gpx.h"
+#include "vax_2681.h"
+#include "vax_lk.h"
+#include "vax_vs.h"
+#include "vax_vcb02_bin.h"
+
+/* QBus memory space offsets */
+
+#define VA_RAM_OF 0x4000 /* RAM */
+#define VA_ADP_OF 0x6000 /* address processor */
+#define VA_DGA_OF 0x6100 /* DMA gate array */
+#define VA_COM1_OF 0x6200 /* DUART */
+#define VA_COM2_OF 0x6300 /* memory registers */
+#define VA_CSR_OF 0x6400 /* CSR registers */
+#define VA_RED_OF 0x6500 /* red colour map */
+#define VA_BLU_OF 0x6600 /* blue colour map */
+#define VA_GRN_OF 0x6700 /* green colour map */
+#define VA_RSV_OF 0x6800
+
+#define VA_ROMSIZE (1u << 14)
+
+#define VA_FIFOSIZE 64
+#define VA_DGA_FIFOSIZE 64
+
+/* RAM offsets */
+
+#define VA_FFO_OF 0x000 /* FIFO */
+#define VA_TMP_OF 0x040 /* template RAM */
+#define VA_CUR_OF 0x7E0 /* cursor image */
+
+/* I/O page CSR */
+
+#define CSR_RAM 0x80 /* 1 = 8KW, 0 = 2KW */
+#define CSR_OPT2 0x40 /* option 2 not present */
+#define CSR_OPT1 0x20 /* option 1 not present */
+#define CSR_MBO 0x10 /* must be one */
+#define CSR_FPS 0x04 /* full page system */
+#define CSR_HPS 0x02 /* half page system */
+#define CSR_QPS 0x01 /* quarter page system */
+
+/* DMA gate array registers */
+
+#define DGA_CSR 0x0 /* CSR */
+#define DGA_ADL 0x1 /* DMA address counter 15:00 */
+#define DGA_ADH 0x2 /* DMA address counter 21:16 (write only) */
+#define DGA_BCL 0x3 /* DMA byte counter 15:00 */
+#define DGA_BCH 0x4 /* DMA byte counter 21:16 */
+#define DGA_FFO 0x5 /* FIFO register */
+#define DGA_CX 0x6 /* Cursor X pos (write only) */
+#define DGA_CY 0x7 /* Cursor Y pos (write only) */
+#define DGA_INT 0x8 /* Interrupt register */
+#define DGA_MAXREG 0x8
+
+#define CUR_PLNA VA_CUR_OF /* cursor plane A */
+#define CUR_PLNB (VA_CUR_OF + 16) /* cursor plane B */
+#define CUR_FG 255 /* cursor foreground */
+#define CUR_BG 254 /* cursor background */
+#define CUR_V (va_dga_csr & 0x1) /* cursor visible */
+#define CUR_X (va_dga_curx) /* cursor X */
+#define CUR_Y (va_dga_cury) /* cursor Y */
+#define CUR_X_OF 232 /* cursor X offset */
+#define CUR_Y_OF 15 /* cursor Y offset */
+
+#define RAM_SIZE (1u << 11) /* template RAM size */
+#define RAM_MASK (RAM_SIZE - 1)
+
+#define IOLN_QDSS 002
+
+/* DMA gate array registers */
+
+#define DGACSR_PACK 0x0100 /* byte/word */
+#define DGACSR_DE 0x0080
+#define DGACSR_WR 0x471F /* write mask */
+#define DGACSR_V_MODE 9
+#define DGACSR_M_MODE 0x3
+#define GET_MODE(x) ((x >> DGACSR_V_MODE) & DGACSR_M_MODE)
+
+#define DGAINT_WR 0x01F0
+
+/* DGA modes */
+
+#define MODE_HALT 0 /* halted */
+#define MODE_DL 1 /* display list */
+#define MODE_BTP 2 /* bitmap to processor */
+#define MODE_PTB 3 /* processor to bitmap */
+
+/* interrupt sources */
+
+#define INT_DGA 1 /* DMA gate array */
+#define INT_COM 2 /* UART */
+
+/* Debugging Bitmaps */
+
+#define DBG_DGA 0x0001 /* DMA gate array activity */
+#define DBG_INT 0x0002 /* interrupt activity */
+#define DBG_CURSOR 0x0004 /* Cursor content, function and visibility activity */
+
+extern int32 int_req[IPL_HLVL];
+extern int32 tmxr_poll; /* calibrated delay */
+extern int32 fault_PC;
+extern int32 trpirq;
+
+uint8 va_red_map[256]; /* red colour map */
+uint8 va_blu_map[256]; /* blue colour map */
+uint8 va_grn_map[256]; /* green colour map */
+uint16 va_ram[RAM_SIZE]; /* template RAM */
+
+uint32 va_dga_csr = 0; /* control/status */
+uint32 va_dga_addr = 0; /* DMA address */
+uint32 va_dga_count = 0; /* DMA counter */
+int32 va_dga_curx = 0; /* cursor X */
+int32 va_dga_cury = 0; /* cursor Y */
+uint32 va_dga_int = 0; /* interrupt register */
+uint32 va_dga_fifo[VA_DGA_FIFOSIZE]; /* FIFO */
+uint32 va_dga_fifo_wp = 0; /* write pointer */
+uint32 va_dga_fifo_rp = 0; /* read pointer */
+uint32 va_dga_fifo_sz = 0; /* data size */
+
+uint32 va_rdbk = 0; /* video readback */
+uint32 va_mcsr = 0; /* memory csr */
+
+int32 va_cur_x = 0; /* last cursor X-position */
+int32 va_cur_y = 0; /* last cursor Y-position */
+t_bool va_cur_v = FALSE; /* last cursor visible */
+
+t_bool va_active = FALSE;
+t_bool va_updated[VA_BYSIZE];
+t_bool va_input_captured = FALSE; /* Mouse and Keyboard input captured in video window */
+uint32 *va_buf = NULL; /* Video memory */
+uint32 *va_lines = NULL; /* Video Display Lines */
+uint32 va_palette[256]; /* Colour palette */
+
+uint32 va_dla = 0; /* display list addr */
+uint32 va_rom_poll = 0;
+
+/* debug variables */
+
+int32 va_yoff = 0; /* debug Y offset */
+int32 va_dpln = 0; /* debug plane */
+uint32 va_white = 0; /* white pixel */
+uint32 va_black = 0; /* black pixel */
+
+const char *va_dga_rgd[] = { /* DMA gate array registers */
+ "Control/Status",
+ "DMA Address Counter (15:00)",
+ "DMA Address Counter (21:16)",
+ "DMA Byte Counter (15:00)",
+ "DMA Byte Counter (21:16)",
+ "FIFO",
+ "Cursor X Position",
+ "Cursor Y Position",
+ "Interrupt Register"
+ };
+
+DEVICE va_dev;
+t_stat va_rd (int32 *data, int32 PA, int32 access);
+t_stat va_wr (int32 data, int32 PA, int32 access);
+t_stat va_svc (UNIT *uptr);
+t_stat va_dmasvc (UNIT *uptr);
+t_stat va_intsvc (UNIT *uptr);
+t_stat va_reset (DEVICE *dptr);
+t_stat va_set_enable (UNIT *uptr, int32 val, CONST char *cptr, void *desc);
+t_stat va_set_capture (UNIT *uptr, int32 val, CONST char *cptr, void *desc);
+t_stat va_show_capture (FILE* st, UNIT* uptr, int32 val, CONST void* desc);
+t_stat va_set_yoff (UNIT *uptr, int32 val, CONST char *cptr, void *desc);
+t_stat va_show_yoff (FILE* st, UNIT* uptr, int32 val, CONST void* desc);
+t_stat va_set_dpln (UNIT *uptr, int32 val, CONST char *cptr, void *desc);
+t_stat va_show_dpln (FILE* st, UNIT* uptr, int32 val, CONST void* desc);
+t_stat va_show_cmap (FILE* st, UNIT* uptr, int32 val, CONST void* desc);
+void va_setint (int32 src);
+int32 va_inta (void);
+void va_clrint (int32 src);
+void va_uart_int (uint32 set);
+t_stat va_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr);
+const char *va_description (DEVICE *dptr);
+void va_checkint (void);
+void va_dlist (void);
+
+/* QDSS data structures
+
+ va_dev QDSS device descriptor
+ va_unit QDSS unit list
+ va_reg QDSS register list
+ va_mod QDSS modifier list
+*/
+
+DIB va_dib = {
+ IOBA_AUTO, IOLN_QDSS, &va_rd, &va_wr,
+ 1, IVCL (QDSS), VEC_AUTO, { &va_inta }
+ };
+
+DEBTAB va_debug[] = {
+ { "REG", DBG_REG, "Register activity" },
+ { "FIFO", DBG_FIFO, "FIFO activity" },
+ { "ADP", DBG_ADP, "Address Procesor (Adder) activity" },
+ { "VDP", DBG_VDP, "Video Processor (Viper) activity" },
+ { "ROP", DBG_ROP, "Raster operations" },
+ { "DGA", DBG_DGA, "DMA Gate Array activity" },
+ { "INT", DBG_INT, "Interrupt activity" },
+ { "CURSOR", DBG_CURSOR, "Cursor content, function and visibility activity"},
+ { "VMOUSE", SIM_VID_DBG_MOUSE, "Video Mouse" },
+ { "VCURSOR", SIM_VID_DBG_CURSOR, "Video Cursor" },
+ { "VKEY", SIM_VID_DBG_KEY, "Video Key" },
+ { "VVIDEO", SIM_VID_DBG_VIDEO, "Video Video" },
+ { 0 }
+ };
+
+UNIT va_unit[] = {
+ { UDATA (&va_svc, UNIT_IDLE, 0) },
+ { UDATA (&va_dmasvc, UNIT_IDLE+UNIT_DIS, 0) },
+ { UDATA (&va_intsvc, UNIT_IDLE+UNIT_DIS, 0) },
+ };
+
+REG va_reg[] = {
+ { HRDATAD (AADCT, va_adp[ADP_ADCT], 16, "address counter") },
+ { HRDATAD (AREQ, va_adp[ADP_REQ], 16, "request enable") },
+ { HRDATAD (AINT, va_adp[ADP_INT], 16, "interrupt enable") },
+ { HRDATAD (ASTAT, va_adp[ADP_STAT], 16, "status") },
+ { HRDATAD (AMDE, va_adp[ADP_MDE], 16, "mode") },
+ { NULL }
+ };
+
+MTAB va_mod[] = {
+ { MTAB_XTD|MTAB_VDV, 1, NULL, "ENABLE",
+ &va_set_enable, NULL, NULL, "Enable VCB02 (QDSS)" },
+ { MTAB_XTD|MTAB_VDV, 0, NULL, "DISABLE",
+ &va_set_enable, NULL, NULL, "Disable VCB02 (QDSS)" },
+ { MTAB_XTD|MTAB_VDV, TRUE, NULL, "CAPTURE",
+ &va_set_capture, &va_show_capture, NULL, "Enable Captured Input Mode" },
+ { MTAB_XTD|MTAB_VDV, FALSE, NULL, "NOCAPTURE",
+ &va_set_capture, NULL, NULL, "Disable Captured Input Mode" },
+ { MTAB_XTD|MTAB_VDV, TRUE, "OSCURSOR", NULL,
+ NULL, &va_show_capture, NULL, "Display Input Capture mode" },
+ { MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, "VIDEO", NULL,
+ NULL, &vid_show_video, NULL, "Display the host system video capabilities" },
+ { MTAB_XTD|MTAB_VDV|MTAB_VALR, 004, "ADDRESS", "ADDRESS",
+ &set_addr, &show_addr, NULL, "Bus address" },
+ { MTAB_XTD|MTAB_VDV|MTAB_VALR, 0, "VECTOR", "VECTOR",
+ &set_vec, &show_vec, NULL, "Interrupt vector" },
+ { MTAB_XTD|MTAB_VDV|MTAB_VALR, 0, "OFFSET", "OFFSET=n",
+ &va_set_yoff, &va_show_yoff, NULL, "Display the debug Y offset" },
+ { MTAB_XTD|MTAB_VDV|MTAB_VALR, 0, "DPLANE", "DPLANE=n",
+ &va_set_dpln, &va_show_dpln, NULL, "Display the debug plane" },
+ { MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, "CMAP", NULL,
+ NULL, &va_show_cmap, NULL, "Display the colour map" },
+ { 0 }
+ };
+
+DEVICE va_dev = {
+ "QDSS", va_unit, va_reg, va_mod,
+ 3, DEV_RDX, 20, 1, DEV_RDX, 8,
+ NULL, NULL, &va_reset,
+ NULL, NULL, NULL,
+ &va_dib, DEV_DIS | DEV_QBUS | DEV_DEBUG, 0,
+ va_debug, NULL, NULL, &va_help, NULL, NULL,
+ &va_description
+ };
+
+UART2681 va_uart = {
+ &va_uart_int, NULL,
+ { { &lk_wr, &lk_rd }, { &vs_wr, &vs_rd } }
+ };
+
+/* I/O Register descriptions on page 3-10 */
+
+t_stat va_rd (int32 *data, int32 PA, int32 access)
+{
+int32 rg = (PA >> 1) & 0x1F;
+if (rg == 0) {
+ *data = CSR_MBO | CSR_FPS;
+ if (RAM_SIZE >= 0x4000)
+ *data = *data | CSR_RAM; /* 8KW system */
+ if (VA_PLANES < 8)
+ *data = *data | CSR_OPT2; /* option 2 not present */
+ }
+else *data = 0;
+sim_debug (DBG_REG, &va_dev, "va_rd: %d, %X at %08X\n", rg, *data, fault_PC);
+return SCPE_OK;
+}
+
+t_stat va_wr (int32 data, int32 PA, int32 access)
+{
+int32 rg = (PA >> 1) & 0x1F;
+if (rg == 0) {
+ if (data > 0)
+ sim_activate_abs (&va_unit[0], tmxr_poll);
+ else
+ sim_cancel (&va_unit[0]);
+ }
+sim_debug (DBG_REG, &va_dev, "va_wr: %d, %X at %08X\n", rg, data, fault_PC);
+return SCPE_OK;
+}
+
+void va_dga_fifo_clr (void)
+{
+sim_debug (DBG_DGA, &va_dev, "dga_fifo_clr\n");
+va_ram[VA_FFO_OF] = 0; /* clear top word */
+va_dga_fifo_wp = VA_FFO_OF; /* reset pointers */
+va_dga_fifo_rp = VA_FFO_OF;
+va_dga_fifo_sz = 0; /* empty */
+}
+
+void va_dga_fifo_wr (uint32 val)
+{
+sim_debug (DBG_DGA, &va_dev, "dga_fifo_wr: %d, %X (%d) at %08X\n", va_dga_fifo_wp, val, (va_dga_fifo_sz + 1), fault_PC);
+#if 0
+if (va_dga_fifo_sz == VA_DGA_FIFOSIZE) { /* writing full fifo? */
+ if (va_dga_count > 0) { /* DMA in progress? */
+ switch (GET_MODE (va_dga_csr)) {
+
+ case MODE_BTP:
+ bc = va_dga_count;
+ if (bc > (VA_DGA_FIFOSIZE << 1))
+ bc = (VA_DGA_FIFOSIZE << 1);
+ wc = bc >> 1;
+ r = Map_WriteW (va_dga_addr, bc, &va_ram[VA_FFO_OF]);
+ va_dga_fifo_clr ();
+ va_dga_count -= bc;
+ va_dga_addr += bc;
+ break;
+ }
+ }
+ }
+if (va_dga_fifo_sz == VA_DGA_FIFOSIZE) { /* writing full fifo? */
+ sim_debug (DBG_DGA, &va_dev, "dga fifo overflow\n");
+ return; /* should not get here */
+ }
+#endif
+va_ram[va_dga_fifo_wp++] = val; /* store value */
+if (va_dga_fifo_wp == VA_DGA_FIFOSIZE) /* pointer wrap? */
+ va_dga_fifo_wp = VA_FFO_OF;
+va_dga_fifo_sz++;
+}
+
+uint32 va_dga_fifo_rd (void)
+{
+uint32 val, wc, bc, r;
+
+if (va_dga_fifo_sz == 0) { /* reading empty fifo */
+ if (va_dga_count > 0) { /* DMA in progress? */
+ switch (GET_MODE (va_dga_csr)) {
+
+ case MODE_PTB:
+ case MODE_DL:
+ bc = va_dga_count; /* get remaining DMA size */
+ if (bc > (VA_DGA_FIFOSIZE << 1)) /* limit to size of FIFO */
+ bc = (VA_DGA_FIFOSIZE << 1);
+ wc = bc >> 1; /* bytes -> words */
+ r = Map_ReadW (va_dga_addr, bc, &va_ram[VA_FFO_OF]);
+ /* do the DMA */
+ va_dga_fifo_sz = wc;
+ va_dga_fifo_wp = wc;
+ va_dga_count -= bc; /* decrement DMA size */
+ va_dga_addr += bc; /* increment DMA addr */
+ break;
+ }
+ }
+ }
+if (va_dga_fifo_sz == 0) { /* reading empty fifo? */
+ sim_debug (DBG_DGA, &va_dev, "dga fifo underflow\n");
+ return 0; /* should not get here */
+ }
+val = va_ram[va_dga_fifo_rp++]; /* get value */
+sim_debug (DBG_DGA, &va_dev, "dga_fifo_rd: %d, %X (%d) at %08X\n", (va_dga_fifo_rp - 1), val, va_dga_fifo_sz, fault_PC);
+if (va_dga_fifo_rp == VA_DGA_FIFOSIZE) /* pointer wrap? */
+ va_dga_fifo_rp = VA_FFO_OF;
+va_dga_fifo_sz--;
+if (va_dga_fifo_sz == 0) /* now empty? */
+ va_dga_fifo_clr (); /* reset pointers */
+return val;
+}
+
+/* DGA Register descriptions on page 3-121 */
+
+int32 va_dga_rd (int32 pa)
+{
+int32 rg = (pa >> 1) & 0xFF;
+int32 data = 0;
+
+switch (rg) {
+ case DGA_CSR: /* CSR */
+ data = va_dga_csr;
+ if (va_dga_csr & 0x4000) {
+ if ((va_dga_count == 0) && (va_dga_fifo_sz == 0))
+ data |= 0x8000;
+ }
+ else {
+ if (va_dga_count == 0)
+ data |= 0x8000;
+ }
+ break;
+
+ case DGA_ADL: /* DMA address counter 15:00 */
+ data = va_dga_addr & WMASK;
+ break;
+
+ case DGA_ADH: /* DMA address counter 21:16 (write only) */
+ break;
+
+ case DGA_BCL: /* DMA byte counter 15:00 */
+ data = va_dga_count & WMASK;
+ break;
+
+ case DGA_BCH: /* DMA byte counter 21:16 */
+ data = ((va_dga_count >> 16) & BMASK) | (va_dga_fifo_sz << 8);
+ break;
+
+ case DGA_FFO: /* FIFO register */
+ data = va_dga_fifo_rd ();
+ break;
+
+ case DGA_CX: /* Cursor X pos (write only) */
+ break;
+
+ case DGA_CY: /* Cursor Y pos (write only) */
+ break;
+
+ case DGA_INT: /* Interrupt register */
+ data = va_dga_int;
+ if (data & 0x4000) /* IRQ 2 */
+ data = data | 0x8;
+ else if (data & 0x2000) /* IRQ 1 */
+ data = data | 0x4;
+ else if (data & 0x1000) /* DMA IRQ */
+ data = data | 0x0;
+ if (data & 0x7000) /* pending int? */
+ data = data | 0x8000;
+ break;
+
+ default:
+ data = 0;
+ sim_debug (DBG_DGA, &va_dev, "dga_rd: %X, %X at %08X\n", pa, data, fault_PC);
+ }
+if (rg <= DGA_MAXREG)
+ sim_debug (DBG_DGA, &va_dev, "dga_rd: %s, %X at %08X\n", va_dga_rgd[rg], data, fault_PC);
+
+return data;
+}
+
+/* DGA Register descriptions on page 3-121 */
+
+void va_dga_wr (int32 pa, int32 val, int32 lnt)
+{
+int32 rg = (pa >> 1) & 0xFF;
+uint32 addr = VA_FFO_OF;
+
+if (rg <= DGA_MAXREG)
+ sim_debug (DBG_DGA, &va_dev, "dga_wr: %s, %X at %08X\n", va_dga_rgd[rg], val, fault_PC);
+
+switch (rg) {
+ case DGA_CSR: /* CSR */
+ if (val & DGACSR_DE)
+ va_dga_csr = va_dga_csr & ~0x00E0;
+ if ((val & 0x2) && ((va_dga_csr & 0x2) == 0)) {
+ if (GET_MODE (val) != MODE_HALT)
+ sim_activate (&va_unit[1], 30);
+ }
+ va_dga_csr = val & DGACSR_WR;
+ va_checkint ();
+ break;
+
+ case DGA_ADL: /* DMA address counter 15:00 */
+ va_dga_addr = (va_dga_addr & ~WMASK) | (val & WMASK);
+ break;
+
+ case DGA_ADH: /* DMA address counter 21:16 */
+ va_dga_addr = (va_dga_addr & ~(WMASK << 16)) | ((val & WMASK) << 16);
+ break;
+
+ case DGA_BCL: /* DMA byte counter 15:00 */
+ va_dga_count = (va_dga_count & ~WMASK) | (val & WMASK);
+ break;
+
+ case DGA_BCH: /* DMA byte counter 21:16 */
+ va_dga_count = (va_dga_count & ~(WMASK << 16)) | ((val & WMASK) << 16);
+ if (va_dga_count > 0)
+ sim_activate (&va_unit[1], 30);
+ break;
+
+ case DGA_FFO: /* FIFO register */
+ va_dga_fifo_wr (val);
+ if (GET_MODE (va_dga_csr) == MODE_DL)
+ va_dlist ();
+ break;
+
+ case DGA_CX: /* Cursor X pos */
+ va_dga_curx = val & 0xFFC; /* get 2s complement component */
+ va_dga_curx = va_dga_curx | 0xFFFFF000; /* sign extend */
+ va_dga_curx = -va_dga_curx; /* negate */
+ va_dga_curx = va_dga_curx + (val & 0x3); /* add non-2s complement component */
+ va_dga_curx = va_dga_curx - CUR_X_OF;
+ break;
+
+ case DGA_CY: /* Cursor Y pos */
+ va_dga_cury = val & 0xFFF; /* get 2s complement component */
+ va_dga_cury = va_dga_cury | 0xFFFFF000; /* sign extend */
+ va_dga_cury = -va_dga_cury; /* negate */
+ va_dga_cury = va_dga_cury - CUR_Y_OF;
+ break;
+
+ case DGA_INT: /* Interrupt register */
+ va_dga_int = (va_dga_int & ~DGAINT_WR) | (val & DGAINT_WR);
+ break;
+
+ default:
+ sim_debug (DBG_DGA, &va_dev, "dga_wr: %X, %X at %08X\n", pa, val, fault_PC);
+ break;
+ }
+return;
+}
+
+int32 va_mem_rd (int32 pa)
+{
+int32 rg = (pa >> 1) & 0x7FFF;
+int32 data;
+UNIT *uptr = &va_dev.units[0];
+uint16 *qr = (uint16*) vax_vcb02_bin;
+
+if (rg >= VA_RSV_OF) {
+ return 0;
+ }
+if (rg >= VA_GRN_OF) { /* green colour map */
+ rg = rg - VA_GRN_OF;
+ data = va_grn_map[rg];
+ sim_debug (DBG_REG, &va_dev, "grn_map_rd: %d, %X at %08X\n", rg, data, fault_PC);
+ return data;
+ }
+if (rg >= VA_BLU_OF) { /* blue colour map */
+ rg = rg - VA_BLU_OF;
+ data = va_blu_map[rg];
+ sim_debug (DBG_REG, &va_dev, "blu_map_rd: %d, %X at %08X\n", rg, data, fault_PC);
+ return data;
+ }
+if (rg >= VA_RED_OF) { /* red colour map */
+ rg = rg - VA_RED_OF;
+ data = va_red_map[rg];
+ sim_debug (DBG_REG, &va_dev, "red_map_rd: %d, %X at %08X\n", rg, data, fault_PC);
+ return data;
+ }
+if (rg >= VA_COM2_OF) { /* video readback register */
+ data = va_rdbk;
+ sim_debug (DBG_REG, &va_dev, "com2_rd: %X, %X at %08X\n", pa, data, fault_PC);
+ return data;
+ }
+if (rg >= VA_COM1_OF) { /* DUART */
+ rg = rg & 0xF;
+ data = ua2681_rd (&va_uart, rg);
+ SET_IRQL;
+ sim_debug (DBG_REG, &va_dev, "com1_rd: %X, %X at %08X\n", pa, data, fault_PC);
+ return data;
+ }
+if (rg >= VA_DGA_OF) { /* DMA gate array */
+ data = va_dga_rd (pa);
+ SET_IRQL;
+ return data;
+ }
+if (rg >= VA_ADP_OF) { /* address processor */
+ rg = rg & 0xFF;
+ data = va_adp_rd (rg);
+ SET_IRQL;
+ return data;
+ }
+if (rg >= VA_RAM_OF) { /* RAM */
+ rg = rg & RAM_MASK;
+ data = va_ram[rg];
+ sim_debug (DBG_REG, &va_dev, "ram_rd: %X, %X at %08X\n", pa, data, fault_PC);
+ return data;
+ }
+rg = rg & 0x1FFF; /* ROM */
+data = qr[rg];
+va_rom_poll = sim_grtime ();
+return sim_rom_read_with_delay (data);
+}
+
+void va_mem_wr (int32 pa, int32 val, int32 lnt)
+{
+int32 nval, i;
+int32 rg = (pa >> 1) & 0x7FFF;
+int32 sc;
+
+if (rg >= VA_RSV_OF) {
+ return;
+ }
+
+if (rg >= VA_GRN_OF) { /* green colour map */
+ rg = rg - VA_GRN_OF;
+ va_grn_map[rg] = val & 0xFF;
+ va_palette[rg] = vid_map_rgb (va_red_map[rg], va_grn_map[rg], va_blu_map[rg]);
+ sim_debug (DBG_REG, &va_dev, "grn_map_wr: %d, %X at %08X\n", rg, val, fault_PC);
+ for (i = 0; i < VA_YSIZE; i++)
+ va_updated[i] = TRUE;
+ return;
+ }
+if (rg >= VA_BLU_OF) { /* blue colour map */
+ rg = rg - VA_BLU_OF;
+ va_blu_map[rg] = val & 0xFF;
+ va_palette[rg] = vid_map_rgb (va_red_map[rg], va_grn_map[rg], va_blu_map[rg]);
+ sim_debug (DBG_REG, &va_dev, "blu_map_wr: %d, %X at %08X\n", rg, val, fault_PC);
+ for (i = 0; i < VA_YSIZE; i++)
+ va_updated[i] = TRUE;
+ return;
+ }
+if (rg >= VA_RED_OF) { /* red colour map */
+ rg = rg - VA_RED_OF;
+ va_red_map[rg] = val & 0xFF;
+ va_palette[rg] = vid_map_rgb (va_red_map[rg], va_grn_map[rg], va_blu_map[rg]);
+ sim_debug (DBG_REG, &va_dev, "red_map_wr: %d, %X at %08X\n", rg, val, fault_PC);
+ for (i = 0; i < VA_YSIZE; i++)
+ va_updated[i] = TRUE;
+ return;
+ }
+if (rg >= VA_COM2_OF) { /* memory CSR */
+ va_mcsr = val;
+ sim_debug (DBG_REG, &va_dev, "com2_wr: %X, %X at %08X\n", pa, val, fault_PC);
+ return;
+ }
+if (rg >= VA_COM1_OF) { /* DUART */
+ rg = rg & 0xF;
+ sim_debug (DBG_REG, &va_dev, "com1_wr: %X, %X at %08X\n", pa, val, fault_PC);
+ ua2681_wr (&va_uart, rg, val);
+ SET_IRQL;
+ return;
+ }
+if (rg >= VA_DGA_OF) { /* DMA gate array */
+ va_dga_wr (pa, val, lnt);
+ SET_IRQL;
+ return;
+ }
+if (rg >= VA_ADP_OF) { /* address processor */
+ rg = rg & 0xFF;
+ va_adp_wr (rg, val);
+ SET_IRQL;
+ return;
+ }
+if (rg >= VA_RAM_OF) { /* RAM */
+ rg = rg & RAM_MASK;
+ if (lnt < L_WORD) {
+ int32 t = va_ram[rg];
+ sc = (pa & 1) << 3;
+ nval = ((val & BMASK) << sc) | (t & ~(BMASK << sc));
+ }
+ else nval = val;
+ va_ram[rg] = nval;
+ sim_debug (DBG_REG, &va_dev, "ram_wr: %X, %X at %08X\n", pa, val, fault_PC);
+ return;
+ }
+}
+
+/* Display list processing */
+
+void va_dlist ()
+{
+t_bool nodec = FALSE;
+uint32 inst, saved_inst;
+int32 val;
+
+saved_inst = (va_dla >> 16) & 0xFFFF; /* get saved instruction */
+va_dla = va_dla & 0x0000FFFF; /* get saved address */
+if ((va_dla < VA_TMP_OF) || (saved_inst & 0x2000)) {
+ if (va_dga_fifo_sz == 0)
+ return;
+ inst = va_dga_fifo_rd ();
+ }
+else
+ inst = va_ram[va_dla++];
+if (saved_inst & 0x1000) /* saved decode flag */
+ nodec = TRUE;
+
+sim_debug (DBG_ROP, &va_dev, "Begin display list\n");
+sim_debug (DBG_ROP, &va_dev, "DLIST: %04X = %04X ", (va_dla == 0) ? 0 : (va_dla - 1), inst);
+for (;;) {
+ if (nodec) { /* decode disabled? */
+ sim_debug (DBG_ROP, &va_dev, "(data - full word)\n");
+ va_adp_wr (ADP_ADCT, inst); /* write to adder (full word) */
+ nodec = FALSE; /* enable decode */
+ }
+ else if (inst & 0x8000) { /* command? */
+ sim_debug (DBG_ROP, &va_dev, "(command");
+ if (inst & 0x4000)
+ sim_debug (DBG_ROP, &va_dev, ", write disable");
+ if (inst & 0x2000) /* read fifo? */
+ sim_debug (DBG_ROP, &va_dev, ", read fifo");
+ if (inst & 0x1000) /* decode disable? */
+ sim_debug (DBG_ROP, &va_dev, ", decode disable");
+ sim_debug (DBG_ROP, &va_dev, ")\n");
+ if ((inst & 0x4000) == 0) /* write enabled? */
+ va_adp_wr (ADP_ADCT, (0x8000 | (inst & 0xFFF))); /* update counter */
+ if (inst & 0x1000) /* decode disable? */
+ nodec = TRUE;
+ if (inst & 0x2000) { /* read fifo? */
+ if (va_dga_fifo_sz == 0) {
+ va_dla = va_dla | (inst << 16); /* save current instruction */
+ break;
+ }
+ inst = va_dga_fifo_rd ();
+ sim_debug (DBG_ROP, &va_dev, "DLIST: fifo = %04X\n", inst);
+ continue;
+ }
+ }
+ else if (inst & 0x4000) { /* write disable? */
+ if (inst & 0x2000) { /* read fifo? */
+ val = inst & 0x1FFF;
+ val = 0x2000 - val; /* FIXME: # words is negative? */
+ sim_debug (DBG_ROP, &va_dev, "(PTB %d words)\n", val);
+ for (; val > 0; val--) {
+ inst = va_dga_fifo_rd ();
+ va_adp_wr (ADP_IDD, inst);
+ }
+ va_dla = 0; /* always returns to FIFO */
+ }
+ else {
+ va_dla = inst & 0x1FFF;
+ sim_debug (DBG_ROP, &va_dev, "(JMPT @ %X)\n", va_dla);
+ }
+ }
+ else {
+ sim_debug (DBG_ROP, &va_dev, "(data)\n");
+ va_adp_wr (ADP_ADCT, (inst & 0x3FFF)); /* write to adder */
+ }
+ if (va_dla < VA_TMP_OF) {
+ if (va_dga_fifo_sz == 0)
+ break;
+ inst = va_dga_fifo_rd ();
+ }
+ else
+ inst = va_ram[va_dla++];
+ sim_debug (DBG_ROP, &va_dev, "DLIST: %04X = %04X ", (va_dla == 0) ? 0 : (va_dla - 1), inst);
+ }
+sim_debug (DBG_ROP, &va_dev, "Display list complete\n");
+}
+
+/* Interrupt handling */
+
+void va_setint (int32 src)
+{
+switch (src) {
+ case INT_DGA: /* DMA IRQ */
+ va_dga_int = va_dga_int | 0x1000;
+ break;
+ case INT_ADP: /* IRQ 1 */
+ va_dga_int = va_dga_int | 0x2000;
+ break;
+ case INT_COM: /* IRQ 2 */
+ va_dga_int = va_dga_int | 0x4000;
+ break;
+ }
+va_checkint ();
+}
+
+void va_clrint (int32 src)
+{
+switch (src) {
+ case INT_DGA: /* DMA IRQ */
+ va_dga_int = va_dga_int & ~0x1000;
+ break;
+ case INT_ADP: /* IRQ 1 */
+ va_dga_int = va_dga_int & ~0x2000;
+ break;
+ case INT_COM: /* IRQ 2 */
+ va_dga_int = va_dga_int & ~0x4000;
+ break;
+ }
+va_checkint ();
+}
+
+void va_checkint (void)
+{
+if (va_dga_csr & 0x4) { /* external int en?*/
+ if (va_dga_int & 0x4000) { /* IRQ 2 */
+ sim_debug (DBG_INT, &va_dev, "uart int\n");
+ SET_INT (QDSS);
+ return;
+ }
+ if (va_dga_int & 0x2000) { /* IRQ 1 */
+ sim_debug (DBG_INT, &va_dev, "adp int\n");
+ SET_INT (QDSS);
+ return;
+ }
+ }
+if ((va_dga_int & 0x1000) && (va_dga_csr & 0x2)) { /* dma int & enabled? */
+ sim_debug (DBG_INT, &va_dev, "dga int\n");
+ SET_INT (QDSS);
+ return;
+ }
+CLR_INT (QDSS);
+}
+
+int32 va_inta (void)
+{
+int32 vec = 0;
+
+if (va_dga_int & 0x4000) { /* IRQ 2 */
+ vec = (va_dga_int & 0x1FC) + 0x8;
+ va_dga_int = va_dga_int & ~0x4000;
+ }
+else if (va_dga_int & 0x2000) { /* IRQ 1 */
+ vec = (va_dga_int & 0x1FC) + 0x4;
+ va_dga_int = va_dga_int & ~0x2000;
+ }
+else if (va_dga_int & 0x1000) { /* DMA IRQ */
+ vec = (va_dga_int & 0x1FC) + 0x0;
+ va_dga_int = va_dga_int & ~0x1000;
+ }
+va_checkint ();
+
+sim_debug (DBG_INT, &va_dev, "returning vector: %X\n", vec);
+return vec;
+}
+
+void va_uart_int (uint32 set)
+{
+if (set)
+ va_setint (INT_COM);
+else
+ va_clrint (INT_COM);
+}
+
+t_stat va_intsvc (UNIT *uptr)
+{
+SET_INT (QDSS);
+return SCPE_OK;
+}
+
+static SIM_INLINE void va_invalidate (uint32 y1, uint32 y2)
+{
+uint32 ln;
+
+for (ln = y1; ln < y2; ln++)
+ va_updated[ln] = TRUE; /* flag as updated */
+}
+
+/* Screen update service routine */
+
+t_stat va_svc (UNIT *uptr)
+{
+SIM_MOUSE_EVENT mev;
+SIM_KEY_EVENT kev;
+t_bool updated = FALSE; /* flag for refresh */
+uint32 lines;
+uint32 col, off, pix;
+uint16 *plna, *plnb;
+uint16 bita, bitb;
+uint32 poll_time;
+int32 ln;
+
+va_adp_svc (uptr);
+
+if (va_cur_v != CUR_V) { /* visibility changed? */
+ if (CUR_V) /* visible? */
+ va_invalidate (CUR_Y, (CUR_Y + 16)); /* invalidate new pos */
+ else
+ va_invalidate (va_cur_y, (va_cur_y + 16)); /* invalidate old pos */
+ }
+else if (va_cur_y != CUR_Y) { /* moved (Y)? */
+ va_invalidate (CUR_Y, (CUR_Y + 16)); /* invalidate new pos */
+ va_invalidate (va_cur_y, (va_cur_y + 16)); /* invalidate old pos */
+ }
+else if (va_cur_x != CUR_X) { /* moved (X)? */
+ va_invalidate (CUR_Y, (CUR_Y + 16)); /* invalidate new pos */
+ }
+
+va_cur_x = CUR_X; /* store cursor data */
+va_cur_y = CUR_Y;
+va_cur_v = CUR_V;
+
+if (vid_poll_kb (&kev) == SCPE_OK) /* poll keyboard */
+ lk_event (&kev); /* push event */
+if (vid_poll_mouse (&mev) == SCPE_OK) /* poll mouse */
+ vs_event (&mev); /* push event */
+
+va_rdbk = 0xF;
+if (va_mcsr & 0x8) { /* sync enable? */
+ if (CUR_X < 0) /* in horizontal front porch? */
+ va_rdbk = va_rdbk & ~0x8; /* sync detect */
+ }
+
+lines = 0;
+for (ln = 0; ln < VA_YSIZE; ln++) {
+ if ((va_adp[ADP_PSE] > 0) && (ln >= va_adp[ADP_PSE])) {
+ sim_debug (DBG_ROP, &va_dev, "pausing at line %d\n", ln);
+ va_adpstat (ADPSTAT_PC, 0);
+ va_adp[ADP_PSE] = 0;
+ if ((CUR_X < 0) || (CUR_X >= VA_XSIZE)) /* cursor off screen? */
+ break; /* done */
+ if (va_mcsr & 0x10) { /* video readback? */
+ pix = va_buf[ln*VA_XSIZE + CUR_X] & VA_PLANE_MASK;
+ sim_debug (DBG_ROP, &va_dev, "video readback enabled, pix = %x\n", pix);
+ if (va_blu_map[pix] < va_red_map[pix]) /* test inverted */
+ va_rdbk = va_rdbk & ~0x4; /* blue > red */
+ if (va_grn_map[pix] < va_blu_map[pix]) /* test inverted */
+ va_rdbk = va_rdbk & ~0x2; /* green > blue */
+ if (va_red_map[pix] < va_grn_map[pix]) /* test inverted */
+ va_rdbk = va_rdbk & ~0x1; /* red > green */
+ sim_debug (DBG_ROP, &va_dev, "video readback value = %x\n", va_rdbk);
+ }
+ break;
+ }
+ if (va_updated[ln + va_yoff]) { /* line updated? */
+ off = (ln + va_yoff) * VA_XSIZE; /* get video buf offet */
+ if (va_dpln > 0) { /* debug plane enabled? */
+ for (col = 0; col < VA_XSIZE; col++) /* force monochrome */
+ va_lines[ln*VA_XSIZE + col] = (va_buf[off + col] & va_dpln) ? va_white : va_black;
+ }
+ else { /* normal mode */
+ for (col = 0; col < VA_XSIZE; col++)
+ va_lines[ln*VA_XSIZE + col] = va_palette[va_buf[off + col] & VA_PLANE_MASK];
+ }
+
+ if (CUR_V && /* cursor visible && need to draw cursor? */
+ (va_input_captured || (va_dev.dctrl & DBG_CURSOR))) {
+ if ((ln >= CUR_Y) && (ln < (CUR_Y + 16))) { /* cursor on this line? */
+ plna = &va_ram[(CUR_PLNA + ln - CUR_Y)];/* get plane A base */
+ plnb = &va_ram[(CUR_PLNB + ln - CUR_Y)];/* get plane B base */
+ for (col = 0; col < 16; col++) {
+ if ((CUR_X + col) < 0) /* Part of cursor off screen? */
+ continue; /* Skip */
+ if ((CUR_X + col) >= VA_XSIZE) /* Part of cursor off screen? */
+ continue; /* Skip */
+ bita = (*plna >> col) & 1;
+ bitb = (*plnb >> col) & 1;
+ if (bita & bitb)
+ va_lines[ln*VA_XSIZE + CUR_X + col] = va_palette[CUR_FG];
+ else if (bita ^ bitb)
+ va_lines[ln*VA_XSIZE + CUR_X + col] = va_palette[CUR_BG];
+ }
+ }
+ }
+ va_updated[ln + va_yoff] = FALSE; /* set valid */
+ if ((ln == (VA_YSIZE-1)) || /* if end of window OR */
+ (va_updated[ln+va_yoff+1] == FALSE)) { /* next is already valid? */
+ vid_draw (0, ln-lines, VA_XSIZE, lines+1, va_lines+(ln-lines)*VA_XSIZE); /* update region */
+ lines = 0;
+ }
+ else
+ lines++;
+ updated = TRUE;
+ }
+ }
+
+if (updated) /* video updated? */
+ vid_refresh (); /* put to screen */
+
+ua2681_svc (&va_uart); /* service DUART */
+poll_time = sim_grtime ();
+
+/*
+ * The interval tmxr_poll is too variable for use during the selftest. *
+ * Instead we use a more deterministic value when we detect that we *
+ * are running from the VCB02 ROM. To detect this we have to look if *
+ * the ROM has been read recently. We can't use fault_PC as the VCB02 *
+ * ROM calls subroutines within the main console ROM */
+
+if ((poll_time - va_rom_poll) < 100000) /* executing from ROM? */
+ sim_activate (uptr, 20000); /* yes, use fast poll */
+else
+ sim_activate (uptr, tmxr_poll); /* no, reactivate */
+return SCPE_OK;
+}
+
+/* DMA service routine */
+
+t_stat va_dmasvc (UNIT *uptr)
+{
+uint32 wc, bc, i, r;
+
+if (GET_MODE (va_dga_csr) == MODE_HALT)
+ return SCPE_OK;
+
+while (va_dga_count > 0) {
+ sim_debug (DBG_DGA, &va_dev, "DMA %d bytes left\n", va_dga_count);
+ bc = va_dga_count;
+ if (bc > (VA_DGA_FIFOSIZE << 1))
+ bc = (VA_DGA_FIFOSIZE << 1);
+ wc = bc >> 1;
+ switch (GET_MODE (va_dga_csr)) {
+
+ case MODE_PTB:
+ r = Map_ReadW (va_dga_addr, bc, &va_ram[VA_FFO_OF]);
+ va_dga_count -= bc;
+ va_dga_addr += bc;
+ for (i = 0; i < wc; i++) {
+ if (va_dga_csr & DGACSR_PACK) {
+ if ((va_adp[ADP_STAT] & ADPSTAT_ITR) == 0)
+ va_ptb (&va_unit[1], (va_unit[1].CMD == CMD_PTBZ));
+ va_fifo_wr (va_ram[VA_FFO_OF + i] & BMASK);
+ if ((va_adp[ADP_STAT] & ADPSTAT_ITR) == 0)
+ va_ptb (&va_unit[1], (va_unit[1].CMD == CMD_PTBZ));
+ va_fifo_wr ((va_ram[VA_FFO_OF + i] >> 8) & BMASK);
+ }
+ else {
+ if ((va_adp[ADP_STAT] & ADPSTAT_ITR) == 0)
+ va_ptb (&va_unit[1], (va_unit[1].CMD == CMD_PTBZ));
+ va_fifo_wr (va_ram[VA_FFO_OF + i]);
+ }
+ }
+ va_ptb (&va_unit[1], (va_unit[1].CMD == CMD_PTBZ));
+ break;
+
+ case MODE_BTP:
+ va_btp (&va_unit[1], (va_unit[1].CMD == CMD_BTPZ));
+ for (i = 0; i < wc; i++) {
+ if (va_dga_csr & DGACSR_PACK) {
+ if ((va_adp[ADP_STAT] & ADPSTAT_IRR) == 0)
+ va_btp (&va_unit[1], (va_unit[1].CMD == CMD_BTPZ));
+ va_ram[VA_FFO_OF + i] = (va_fifo_rd () & BMASK);
+ if ((va_adp[ADP_STAT] & ADPSTAT_IRR) == 0)
+ va_btp (&va_unit[1], (va_unit[1].CMD == CMD_BTPZ));
+ va_ram[VA_FFO_OF + i] |= ((va_fifo_rd () & BMASK) << 8);
+ }
+ else {
+ if ((va_adp[ADP_STAT] & ADPSTAT_IRR) == 0)
+ va_btp (&va_unit[1], (va_unit[1].CMD == CMD_BTPZ));
+ va_ram[VA_FFO_OF + i] = va_fifo_rd ();
+ }
+ }
+ r = Map_WriteW (va_dga_addr, bc, &va_ram[VA_FFO_OF]);
+ va_dga_count -= bc;
+ va_dga_addr += bc;
+ break;
+
+ case MODE_DL:
+ r = Map_ReadW (va_dga_addr, bc, &va_ram[VA_FFO_OF]);
+ va_dga_count -= bc;
+ va_dga_addr += bc;
+ for (i = 0; i < wc; i++)
+ va_dga_fifo_wr (va_ram[VA_FFO_OF + i]);
+ va_dlist ();
+ break;
+
+ default:
+ sim_debug (DBG_DGA, &va_dev, "DMA mode %X\n", GET_MODE(va_dga_csr));
+ return SCPE_OK;
+ }
+ }
+va_setint (INT_DGA);
+return SCPE_OK;
+}
+
+t_stat va_reset (DEVICE *dptr)
+{
+int32 i;
+t_stat r;
+
+CLR_INT (QDSS); /* clear int req */
+sim_cancel (&va_unit[0]); /* stop poll */
+sim_cancel (&va_unit[1]);
+ua2681_reset (&va_uart); /* reset DUART */
+va_adp_reset (dptr);
+
+va_dga_fifo_clr ();
+va_mcsr = 0;
+va_rdbk = 0;
+va_dla = 0;
+va_rom_poll = 0;
+
+for (i = 0; i < VA_YSIZE; i++)
+ va_updated[i] = TRUE;
+
+if (dptr->flags & DEV_DIS) {
+ if (va_active) {
+ free (va_buf);
+ va_buf = NULL;
+ free (va_lines);
+ va_lines = NULL;
+ va_active = FALSE;
+ return vid_close ();
+ }
+ else
+ return SCPE_OK;
+ }
+
+if (!vid_active) {
+ r = vid_open (dptr, NULL, VA_XSIZE, VA_YSIZE, va_input_captured ? SIM_VID_INPUTCAPTURED : 0);/* display size & capture mode */
+ if (r != SCPE_OK)
+ return r;
+ va_buf = (uint32 *) calloc (VA_BUFSIZE, sizeof (uint32));
+ if (va_buf == NULL) {
+ vid_close ();
+ return SCPE_MEM;
+ }
+ va_lines = (uint32 *) calloc (VA_XSIZE * VA_YSIZE, sizeof (uint32));
+ if (va_lines == NULL) {
+ free (va_buf);
+ vid_close ();
+ return SCPE_MEM;
+ }
+ va_palette[0] = vid_map_rgb (0x00, 0x00, 0x00); /* black */
+ for (i = 1; i < 256; i++)
+ va_palette[i] = vid_map_rgb (0xFF, 0xFF, 0xFF); /* white */
+ va_black = vid_map_rgb (0x00, 0x00, 0x00); /* black */
+ va_white = vid_map_rgb (0xFF, 0xFF, 0xFF); /* white */
+ sim_printf ("QDSS Display Created. ");
+ va_show_capture (stdout, NULL, 0, NULL);
+ if (sim_log)
+ va_show_capture (sim_log, NULL, 0, NULL);
+ sim_printf ("\n");
+ va_active = TRUE;
+ }
+return auto_config (NULL, 0); /* run autoconfig */
+}
+
+t_stat va_set_yoff (UNIT *uptr, int32 val, CONST char *cptr, void *desc)
+{
+int32 i;
+t_stat r;
+
+if (cptr == NULL)
+ return SCPE_ARG;
+va_yoff = (int32) get_uint (cptr, 10, 2048, &r);
+for (i = 0; i < VA_YSIZE; i++)
+ va_updated[i + va_yoff] = TRUE;
+return r;
+}
+
+t_stat va_show_yoff (FILE* st, UNIT* uptr, int32 val, CONST void* desc)
+{
+fprintf (st, "%d", va_yoff);
+return SCPE_OK;
+}
+
+t_stat va_set_dpln (UNIT *uptr, int32 val, CONST char *cptr, void *desc)
+{
+int32 i;
+t_stat r;
+
+if (cptr == NULL)
+ return SCPE_ARG;
+va_dpln = (int32) get_uint (cptr, 10, VA_PLANES, &r);
+if (va_dpln > 0) {
+ va_dpln = va_dpln - 1;
+ va_dpln = (1u << va_dpln);
+ }
+for (i = 0; i < VA_YSIZE; i++)
+ va_updated[i + va_yoff] = TRUE;
+return r;
+}
+
+t_stat va_show_dpln (FILE* st, UNIT* uptr, int32 val, CONST void* desc)
+{
+fprintf (st, "%d", va_dpln);
+return SCPE_OK;
+}
+
+t_stat va_show_cmap (FILE* st, UNIT* uptr, int32 val, CONST void* desc)
+{
+int32 i;
+for (i = 0; i < VA_BPP; i++)
+ fprintf (st, "%d = (0x%02x, 0x%02x, 0x%02x)\n", i,
+ va_red_map[i], va_grn_map[i], va_blu_map[i]);
+return SCPE_OK;
+}
+
+t_stat va_set_enable (UNIT *uptr, int32 val, CONST char *cptr, void *desc)
+{
+return cpu_set_model (NULL, 0, (val ? "VAXSTATIONGPX" : "MICROVAX"), NULL);
+}
+
+t_stat va_set_capture (UNIT *uptr, int32 val, CONST char *cptr, void *desc)
+{
+if (vid_active)
+ return sim_messagef (SCPE_ALATT, "Capture Mode Can't be changed with device enabled\n");
+va_input_captured = val;
+return SCPE_OK;
+}
+
+t_stat va_show_capture (FILE* st, UNIT* uptr, int32 val, CONST void* desc)
+{
+if (va_input_captured) {
+ fprintf (st, "Captured Input Mode, ");
+ vid_show_release_key (st, uptr, val, desc);
+ }
+else
+ fprintf (st, "Uncaptured Input Mode");
+return SCPE_OK;
+}
+
+t_stat va_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr)
+{
+fprintf (st, "VCB02 8-Bit Colour Video Subsystem (%s)\n\n", dptr->name);
+fprintf (st, "Use the Control-Right-Shift key combination to regain focus from the simulated\n");
+fprintf (st, "video display\n");
+fprint_set_help (st, dptr);
+fprint_show_help (st, dptr);
+fprint_reg_help (st, dptr);
+return SCPE_OK;
+}
+
+const char *va_description (DEVICE *dptr)
+{
+return "VCB02 Colour Graphics Adapter";
+}
diff --git a/VAX/vax_vc.c b/VAX/vax_vc.c
index 4c7ec192..06d2366e 100644
--- a/VAX/vax_vc.c
+++ b/VAX/vax_vc.c
@@ -230,6 +230,8 @@ uint32 *vc_map; /* Scanline map */
uint32 *vc_buf = NULL; /* Video memory */
uint32 *vc_lines = NULL; /* Video Display Lines */
uint8 vc_cur[256]; /* Cursor image */
+uint32 vc_palette[2]; /* Monochrome palette */
+t_bool vc_active = FALSE;
t_stat vc_rd (int32 *data, int32 PA, int32 access);
t_stat vc_wr (int32 data, int32 PA, int32 access);
@@ -673,7 +675,7 @@ uint32 rg = (pa >> 2) & 0xFFFF;
if (!vc_buf) /* QVSS disabled? */
MACH_CHECK (MCHK_READ); /* Invalid memory reference */
-return vc_buf[rg];
+return (pa & 0x2) ? (vc_buf[rg] >> 16) : vc_buf[rg] & 0xFFFF;
}
void vc_mem_wr (int32 pa, int32 val, int32 lnt)
@@ -952,7 +954,7 @@ for (ln = 0; ln < VC_YSIZE; ln++) {
if ((vc_map[ln] & VCMAP_VLD) == 0) { /* line invalid? */
off = vc_map[ln] * 32; /* get video buf offset */
for (col = 0; col < VC_XSIZE; col++)
- vc_lines[ln*VC_XSIZE + col] = vid_mono_palette[(vc_buf[off + (col >> 5)] >> (col & 0x1F)) & 1];
+ vc_lines[ln*VC_XSIZE + col] = vc_palette[(vc_buf[off + (col >> 5)] >> (col & 0x1F)) & 1];
/* 1bpp to 32bpp */
if (CUR_V && /* cursor visible && need to draw cursor? */
(vc_input_captured || (vc_dev.dctrl & DBG_CURSOR))) {
@@ -962,9 +964,9 @@ for (ln = 0; ln < VC_YSIZE; ln++) {
if ((CUR_X + col) >= VC_XSIZE) /* Part of cursor off screen? */
continue; /* Skip */
if (CUR_F) /* mask function */
- vc_lines[ln*VC_XSIZE + CUR_X + col] = vid_mono_palette[(vc_lines[ln*VC_XSIZE + CUR_X + col] == vid_mono_palette[1]) | (cur[col] & 1)];
+ vc_lines[ln*VC_XSIZE + CUR_X + col] = vc_palette[(vc_lines[ln*VC_XSIZE + CUR_X + col] == vc_palette[1]) | (cur[col] & 1)];
else
- vc_lines[ln*VC_XSIZE + CUR_X + col] = vid_mono_palette[(vc_lines[ln*VC_XSIZE + CUR_X + col] == vid_mono_palette[1]) & (~cur[col] & 1)];
+ vc_lines[ln*VC_XSIZE + CUR_X + col] = vc_palette[(vc_lines[ln*VC_XSIZE + CUR_X + col] == vc_palette[1]) & (~cur[col] & 1)];
}
}
}
@@ -1016,13 +1018,18 @@ vc_crtc[CRTC_CSCS] = 0x20; /* hide cursor */
vc_crtc_p = (CRTCP_LPF | CRTCP_VB);
if (dptr->flags & DEV_DIS) {
- free (vc_buf);
- vc_buf = NULL;
- free (vc_lines);
- vc_lines = NULL;
- free (vc_map);
- vc_map = NULL;
- return vid_close ();
+ if (vc_active) {
+ free (vc_buf);
+ vc_buf = NULL;
+ free (vc_lines);
+ vc_lines = NULL;
+ free (vc_map);
+ vc_map = NULL;
+ vc_active = FALSE;
+ return vid_close ();
+ }
+ else
+ return SCPE_OK;
}
if (!vid_active) {
@@ -1048,6 +1055,9 @@ if (!vid_active) {
vid_close ();
return SCPE_MEM;
}
+ vc_palette[0] = vid_map_rgb (0x00, 0x00, 0x00); /* black */
+ vc_palette[1] = vid_map_rgb (0xFF, 0xFF, 0xFF); /* white */
+ vc_active = TRUE;
sim_printf ("QVSS Display Created. ");
vc_show_capture (stdout, NULL, 0, NULL);
if (sim_log)
diff --git a/VAX/vax_vcb02_bin.h b/VAX/vax_vcb02_bin.h
new file mode 100644
index 00000000..b184385f
--- /dev/null
+++ b/VAX/vax_vcb02_bin.h
@@ -0,0 +1,1037 @@
+#ifndef ROM_vax_vcb02_bin_H
+#define ROM_vax_vcb02_bin_H 0
+/*
+ VAX/vax_vcb02_bin.h produced at Thu Sep 6 00:39:45 2018
+ from VAX/vcb02.bin which was last modified at Thu Sep 6 00:33:02 2018
+ file size: 16384 (0x4000) - checksum: 0xFFF1D2AD
+ This file is a generated file and should NOT be edited or changed by hand.
+*/
+#define BOOT_CODE_SIZE 0x4000
+#define BOOT_CODE_FILENAME "vcb02.bin"
+#define BOOT_CODE_ARRAY vax_vcb02_bin
+unsigned char vax_vcb02_bin[] = {
+0x00,0x01,0x00,0x01,0x12,0x04,0x51,0x44,0x41,0x30,0x00,0x40,0x00,0x00,0x00,0x00,
+0x46,0xF5,0x01,0x00,0x44,0x49,0x41,0x47,0x30,0x20,0x20,0x20,0x20,0x20,0x58,0x22,
+0x00,0x00,0x2E,0x00,0x00,0x00,0x6A,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x0E,0x00,
+0x00,0x00,0xFC,0x0C,0x00,0x00,0xE0,0x12,0x00,0x00,0x40,0x13,0x00,0x00,0xDC,0x13,
+0x00,0x00,0x04,0x14,0x00,0x00,0x50,0x15,0x00,0x00,0xF0,0x1A,0x00,0x00,0x2C,0x1D,
+0x00,0x00,0xE8,0x1F,0x00,0x00,0x7C,0x0D,0x00,0x00,0xD4,0x0D,0x00,0x00,0x14,0x10,
+0x00,0x00,0x88,0x11,0x00,0x00,0x54,0x12,0x00,0x00,0xFC,0x0F,0xD5,0x6C,0x13,0x10,
+0xD1,0xAC,0x04,0x01,0x13,0x06,0x7D,0x01,0x50,0x31,0x65,0x01,0xD0,0xAC,0x08,0x5B,
+0xD0,0xAB,0x58,0x5A,0xB0,0x07,0xEA,0x00,0xC8,0x00,0x00,0xD0,0xAB,0x68,0x59,0xD5,
+0x6C,0x12,0x61,0xDB,0x12,0x7E,0x3C,0x9F,0x40,0x1F,0x00,0x20,0x7E,0xDB,0x11,0x7E,
+0xDD,0x9F,0x00,0x80,0x08,0x20,0xD4,0xA9,0x08,0xD0,0x10,0xA9,0x18,0xD0,0x17,0xA9,
+0x14,0xDB,0x11,0x58,0x28,0x8F,0x00,0x04,0x68,0xC9,0x00,0xFC,0x9E,0xC9,0x00,0xFC,
+0x58,0xD0,0x58,0xA9,0x24,0xDA,0x58,0x11,0xD0,0x8F,0xF0,0x01,0x00,0x00,0xA9,0x0C,
+0xD0,0x8F,0x00,0x02,0x00,0x00,0xA9,0x10,0xD4,0x69,0x78,0x8F,0xF7,0x59,0x58,0xC9,
+0x8F,0x00,0x00,0x00,0x80,0x58,0x9F,0x00,0x80,0x08,0x20,0xA8,0x20,0x9F,0x40,0x1F,
+0x00,0x20,0x11,0x3C,0xDB,0x12,0x7E,0xD0,0xAC,0x04,0xA9,0x08,0xD0,0xAC,0x1C,0xA9,
+0x18,0xD0,0xAC,0x20,0xA9,0x14,0xD0,0xAC,0x18,0x69,0xD0,0xAC,0x0C,0x58,0xD0,0x58,
+0xA9,0x24,0xD0,0xAC,0x10,0xA9,0x10,0xD0,0xAC,0x14,0xA9,0x0C,0xDD,0xA8,0x04,0xC0,
+0xA9,0x10,0x58,0xC0,0xA9,0x0C,0x58,0x7D,0x88,0x7E,0x7D,0x88,0x7E,0xD0,0x58,0x7E,
+0xD0,0x5E,0xA9,0x1C,0x9E,0xEF,0xE2,0x0B,0x00,0x00,0x57,0xCA,0x03,0x57,0xD0,0x57,
+0x58,0xD0,0xA9,0x24,0x56,0xD0,0x57,0xA6,0x04,0xC0,0xA9,0x10,0x56,0xC0,0xA9,0x0C,
+0x56,0x7D,0x57,0x86,0x7D,0x57,0x86,0xDA,0xA9,0x18,0x12,0xD0,0x01,0x50,0xD0,0x8F,
+0x00,0x00,0x00,0x2F,0x51,0x7D,0x50,0x52,0x9E,0xEF,0xC0,0xFE,0xFF,0xFF,0x57,0xD0,
+0x01,0x58,0xC1,0x48,0x67,0x57,0x56,0xBB,0x8F,0xFC,0x0F,0x16,0x66,0xBA,0x8F,0xFC,
+0x0F,0xD5,0x50,0x13,0x16,0xD1,0x50,0x01,0x13,0x08,0xD1,0x52,0x02,0x13,0x03,0x7D,
+0x50,0x52,0xF3,0x67,0x58,0xDC,0x7D,0x52,0x50,0x11,0x00,0x78,0x8F,0xE8,0x51,0x52,
+0xB0,0x52,0xEA,0x00,0xC8,0x00,0x00,0xCA,0x8F,0x00,0x00,0xFF,0xFF,0x51,0xD0,0xAB,
+0x68,0x59,0xD0,0xA9,0x1C,0x5E,0xD5,0xA9,0x08,0x12,0x18,0xD0,0x8E,0x9F,0x00,0x80,
+0x08,0x20,0xDA,0x8E,0x11,0xB0,0x6E,0x9F,0x40,0x1F,0x00,0x20,0xD5,0x8E,0xDA,0x8E,
+0x12,0x11,0x0E,0xD0,0x8E,0x58,0x7D,0x8E,0x78,0x7D,0x8E,0x78,0xDA,0x8E,0x12,0x11,
+0x00,0x04,0x04,0x55,0xAA,0x33,0x0F,0x05,0x00,0x55,0x55,0xAA,0xAA,0x33,0x33,0x0F,
+0x0F,0xFF,0x00,0x07,0x00,0x00,0x00,0x55,0x55,0x55,0x55,0xAA,0xAA,0xAA,0xAA,0x33,
+0x33,0x33,0x33,0x0F,0x0F,0x0F,0x0F,0xFF,0x00,0xFF,0x00,0xFF,0xFF,0x00,0x00,0x21,
+0x43,0x65,0x87,0x00,0x1C,0x04,0xD0,0xAB,0x58,0x5A,0x9A,0x01,0x50,0xB4,0xEA,0x06,
+0xC0,0x00,0x00,0xD0,0x8F,0xF4,0x01,0x00,0x00,0x54,0xE0,0xAC,0x04,0xEA,0x06,0xC0,
+0x00,0x00,0x08,0x16,0xBB,0x5C,0xF5,0x54,0xF1,0xD4,0x50,0x04,0x7C,0x04,0xD0,0xAB,
+0x58,0x5A,0xDD,0x04,0xFB,0x01,0xAF,0xCC,0xE8,0x50,0x03,0x31,0x79,0x00,0xB0,0x8F,
+0x80,0x00,0xEA,0x12,0xC0,0x00,0x00,0xB0,0x00,0xEA,0x44,0xC0,0x00,0x00,0xB0,0x00,
+0xEA,0x46,0xC0,0x00,0x00,0x9A,0xAB,0x50,0x55,0xA4,0x08,0x55,0xB0,0x55,0xEA,0x48,
+0xC0,0x00,0x00,0x9A,0xAB,0x4C,0x56,0xA5,0x0F,0x56,0xEA,0x4A,0xC0,0x00,0x00,0xB0,
+0x8F,0xC6,0x07,0xEA,0x14,0xC0,0x00,0x00,0x9A,0xAB,0x4C,0x56,0xD4,0x53,0xD0,0x51,
+0x52,0xE0,0x06,0xEA,0x06,0xC0,0x00,0x00,0x0D,0xDD,0x06,0xFB,0x01,0xCF,0x74,0xFF,
+0xE8,0x50,0x03,0x31,0x21,0x00,0xE1,0x03,0x55,0x11,0x9A,0x43,0x62,0x54,0x78,0x08,
+0x54,0x54,0xB0,0x54,0xEA,0x0E,0xC0,0x00,0x00,0x11,0x08,0x9B,0x43,0x62,0xEA,0x0E,
+0xC0,0x00,0x00,0xF2,0x0F,0x53,0xCA,0x04,0x60,0x04,0xDD,0x0A,0xDD,0x8F,0xFF,0xFF,
+0x00,0x00,0xFB,0x02,0xEF,0x05,0x0A,0x00,0x00,0x11,0x0D,0x60,0x04,0xDD,0x0A,0xDD,
+0x00,0xFB,0x02,0xEF,0xF6,0x09,0x00,0x00,0x91,0xAB,0x50,0xAB,0x51,0x13,0x3C,0xD0,
+0xAB,0x58,0x5A,0xB0,0x8F,0x80,0x00,0xEA,0x12,0xC0,0x00,0x00,0xB0,0x00,0xEA,0x44,
+0xC0,0x00,0x00,0xB0,0x00,0xEA,0x46,0xC0,0x00,0x00,0x9A,0xAB,0x50,0x56,0xA5,0x56,
+0x08,0xEA,0x48,0xC0,0x00,0x00,0x9A,0xAB,0x4C,0x56,0xA5,0x56,0x0F,0xEA,0x4A,0xC0,
+0x00,0x00,0xB0,0x8F,0xC0,0x06,0xEA,0x14,0xC0,0x00,0x00,0x04,0x00,0x04,0xD0,0xAB,
+0x58,0x5A,0xDD,0x01,0xFB,0x01,0xCF,0xDB,0xFE,0xE9,0x50,0x18,0xB0,0x0F,0xEA,0x28,
+0xC0,0x00,0x00,0xDD,0x01,0xFB,0x01,0xCF,0xCA,0xFE,0xE9,0x50,0x07,0xDD,0x01,0xFB,
+0x01,0xCF,0xC0,0xFE,0x04,0x0C,0x00,0xDD,0x04,0xFB,0x01,0xCF,0xB6,0xFE,0xE9,0x50,
+0x44,0x3E,0xEA,0x48,0xC0,0x00,0x00,0x53,0xB4,0x83,0xB0,0xAC,0x04,0x83,0xB0,0x8F,
+0xFF,0x03,0x83,0xB4,0x83,0xB4,0x83,0xB0,0x01,0x83,0xDD,0x8F,0xA4,0x00,0x00,0x00,
+0xDD,0xAC,0x0C,0xFB,0x02,0xEF,0x54,0x09,0x00,0x00,0xE9,0x50,0x18,0xDD,0x0A,0xDD,
+0xAC,0x08,0xFB,0x02,0xEF,0x45,0x09,0x00,0x00,0xE9,0x50,0x09,0xB0,0x8F,0xC0,0x06,
+0xEA,0x14,0xC0,0x00,0x00,0x04,0xBB,0x8F,0x04,0x04,0xD0,0xAB,0x58,0x5A,0xD4,0x50,
+0xE1,0x00,0xEA,0x02,0xC4,0x00,0x00,0x0D,0x9A,0xEA,0x06,0xC4,0x00,0x00,0x52,0x9A,
+0x01,0x50,0x16,0xBB,0x48,0xBA,0x8F,0x04,0x04,0x05,0x3C,0x00,0x9E,0xEF,0x7C,0x00,
+0x00,0x00,0x53,0x3C,0x83,0x52,0x3C,0x83,0x54,0x3C,0x83,0x55,0xC0,0x5A,0x55,0xB0,
+0x83,0x85,0xF5,0x54,0xFA,0xF5,0x52,0xEE,0xDD,0x01,0xFB,0x01,0xCF,0x25,0xFE,0xE9,
+0x50,0x0A,0xDD,0x01,0xFB,0x01,0xCF,0x1B,0xFE,0xE8,0x50,0x51,0xB0,0x01,0xEA,0x62,
+0xC0,0x00,0x00,0xB0,0x01,0xEA,0x64,0xC0,0x00,0x00,0xB0,0x01,0xEA,0x66,0xC0,0x00,
+0x00,0xB0,0x01,0xEA,0x68,0xC0,0x00,0x00,0xDD,0x01,0xFB,0x01,0xCF,0xF5,0xFD,0xE9,
+0x50,0x2B,0xB0,0x8F,0x88,0x03,0xEA,0x68,0xC0,0x00,0x00,0xB0,0x8F,0x66,0x23,0xEA,
+0x66,0xC0,0x00,0x00,0xB0,0x8F,0x63,0x33,0xEA,0x64,0xC0,0x00,0x00,0xB0,0x8F,0x5F,
+0x13,0xEA,0x62,0xC0,0x00,0x00,0xDD,0x01,0xFB,0x01,0xCF,0xC7,0xFD,0x04,0x06,0x00,
+0x04,0x00,0x00,0xC0,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x10,0xC0,
+0x00,0x00,0x80,0x00,0x00,0x00,0x07,0x00,0x18,0xC0,0x00,0x00,0x00,0x00,0x00,0x04,
+0x00,0x00,0x00,0x08,0x00,0x00,0x00,0x00,0x0A,0x00,0x2A,0xC0,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x08,
+0x11,0x00,0x40,0xC0,0x20,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x20,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0xFF,0x1F,0xFF,0x1F,0x00,0x00,0x00,0x00,
+0x22,0x00,0x00,0x00,0x00,0x00,0x0F,0x00,0x62,0xC0,0x5F,0x13,0x63,0x33,0x66,0x23,
+0x88,0x03,0xC8,0x00,0x00,0x04,0x00,0x08,0x00,0x28,0x20,0x10,0x3A,0x00,0xF0,0x38,
+0x28,0x61,0x3A,0x09,0x3C,0x31,0x00,0x01,0x7C,0x04,0xD0,0xAB,0x58,0x5A,0xD0,0x8F,
+0x00,0x00,0xFF,0x00,0x52,0xD0,0x52,0x53,0x3C,0x8F,0xC0,0x00,0x54,0x9E,0xEA,0x00,
+0xCA,0x00,0x00,0x55,0xDD,0x0D,0xFB,0x01,0xCF,0x19,0xFD,0x7D,0x52,0x85,0xF5,0x54,
+0xFA,0x04,0x00,0x07,0xD0,0xAB,0x58,0x5A,0xD4,0x58,0x9E,0xEA,0x00,0xC4,0x00,0x00,
+0x59,0x90,0x3A,0xA9,0x04,0x16,0xBB,0x5C,0x90,0x2A,0xA9,0x04,0x16,0xBB,0x5C,0x90,
+0x1A,0xA9,0x04,0xE0,0x00,0x58,0x05,0x90,0x13,0x69,0x11,0x03,0x90,0x07,0x69,0x90,
+0x07,0x69,0x16,0xBB,0x5C,0x90,0x00,0xEA,0x08,0xC4,0x00,0x00,0x90,0x8F,0x99,0xA9,
+0x02,0x90,0x8F,0x45,0xA9,0x04,0x16,0xBB,0x5C,0x9E,0xEA,0x10,0xC4,0x00,0x00,0x59,
+0xE3,0x00,0x58,0xBD,0x9A,0x01,0x50,0x04,0x80,0x07,0xD0,0xAB,0x58,0x5A,0x9E,0xEF,
+0x35,0x00,0x00,0x00,0x59,0x9A,0x89,0x58,0x90,0x89,0xEA,0x06,0xC4,0x00,0x00,0xD0,
+0x8F,0xE8,0x03,0x00,0x00,0x57,0xE0,0x00,0xEA,0x02,0xC4,0x00,0x00,0x0A,0x16,0xBB,
+0x5C,0xF5,0x57,0xF2,0xD4,0x50,0x11,0x10,0x91,0xEA,0x06,0xC4,0x00,0x00,0x8F,0xBA,
+0x12,0xDD,0xF5,0x58,0xD3,0x9A,0x01,0x50,0x04,0x0E,0x88,0x90,0x98,0xA0,0xA8,0xB6,
+0xB8,0xC0,0xC8,0xD0,0xD8,0xE0,0xE8,0xF0,0x00,0x04,0xD0,0xAB,0x58,0x5A,0xDD,0x01,
+0xFB,0x01,0xEF,0xF4,0x06,0x00,0x00,0xE8,0x50,0x03,0x31,0xB2,0x02,0xDD,0x03,0xDD,
+0x00,0xFB,0x02,0xEF,0x16,0x07,0x00,0x00,0xE8,0x50,0x03,0x31,0xA1,0x02,0xDD,0x02,
+0xFB,0x01,0xEF,0xD4,0x06,0x00,0x00,0xE8,0x50,0x03,0x31,0x92,0x02,0xDD,0x03,0xDD,
+0x01,0xFB,0x02,0xEF,0xF6,0x06,0x00,0x00,0xE8,0x50,0x03,0x31,0x81,0x02,0xDD,0x04,
+0xFB,0x01,0xEF,0xB4,0x06,0x00,0x00,0xE8,0x50,0x03,0x31,0x72,0x02,0xDD,0x03,0xDD,
+0x02,0xFB,0x02,0xEF,0xD6,0x06,0x00,0x00,0xE8,0x50,0x03,0x31,0x61,0x02,0xDD,0x08,
+0xFB,0x01,0xEF,0x94,0x06,0x00,0x00,0xE8,0x50,0x03,0x31,0x52,0x02,0xDD,0x03,0xDD,
+0x03,0xFB,0x02,0xEF,0xB6,0x06,0x00,0x00,0xE8,0x50,0x03,0x31,0x41,0x02,0xE1,0x06,
+0xBB,0x3C,0x03,0x31,0x88,0x00,0xDD,0x10,0xFB,0x01,0xEF,0x6C,0x06,0x00,0x00,0xE8,
+0x50,0x03,0x31,0x2A,0x02,0xDD,0x03,0xDD,0x04,0xFB,0x02,0xEF,0x8E,0x06,0x00,0x00,
+0xE8,0x50,0x03,0x31,0x19,0x02,0xDD,0x20,0xFB,0x01,0xEF,0x4C,0x06,0x00,0x00,0xE8,
+0x50,0x03,0x31,0x0A,0x02,0xDD,0x03,0xDD,0x05,0xFB,0x02,0xEF,0x6E,0x06,0x00,0x00,
+0xE8,0x50,0x03,0x31,0xF9,0x01,0xDD,0x8F,0x40,0x00,0x00,0x00,0xFB,0x01,0xEF,0x28,
+0x06,0x00,0x00,0xE8,0x50,0x03,0x31,0xE6,0x01,0xDD,0x03,0xDD,0x06,0xFB,0x02,0xEF,
+0x4A,0x06,0x00,0x00,0xE8,0x50,0x03,0x31,0xD5,0x01,0xDD,0x8F,0x80,0x00,0x00,0x00,
+0xFB,0x01,0xEF,0x04,0x06,0x00,0x00,0xE8,0x50,0x03,0x31,0xC2,0x01,0xDD,0x03,0xDD,
+0x07,0xFB,0x02,0xEF,0x26,0x06,0x00,0x00,0xE8,0x50,0x03,0x31,0xB1,0x01,0xDD,0x04,
+0xFB,0x01,0xCF,0x4F,0xFB,0xE8,0x50,0x03,0x31,0xA4,0x01,0xDD,0x06,0xFB,0x01,0xCF,
+0x42,0xFB,0xE8,0x50,0x03,0x31,0x97,0x01,0xB0,0x8F,0xFF,0x00,0xEA,0x0E,0xC0,0x00,
+0x00,0xB0,0x8F,0x40,0x01,0xEA,0x14,0xC0,0x00,0x00,0xDD,0x8F,0xFF,0x00,0x00,0x00,
+0xFB,0x01,0xEF,0xB4,0x05,0x00,0x00,0xE8,0x50,0x03,0x31,0x72,0x01,0xDD,0x01,0xDD,
+0x0C,0xFB,0x02,0xEF,0xD6,0x05,0x00,0x00,0xE8,0x50,0x03,0x31,0x61,0x01,0xDD,0x00,
+0xDD,0x00,0xFB,0x02,0xEF,0xC5,0x05,0x00,0x00,0xE8,0x50,0x03,0x31,0x50,0x01,0xDD,
+0x02,0xDD,0x8F,0x60,0x00,0x00,0x00,0xFB,0x02,0xEF,0xB0,0x05,0x00,0x00,0xE8,0x50,
+0x03,0x31,0x3B,0x01,0xDD,0x0B,0xDD,0x00,0xFB,0x02,0xEF,0x9F,0x05,0x00,0x00,0xE8,
+0x50,0x03,0x31,0x2A,0x01,0xDD,0x0C,0xDD,0x00,0xFB,0x02,0xEF,0x8E,0x05,0x00,0x00,
+0xE8,0x50,0x03,0x31,0x19,0x01,0xDD,0x0D,0xDD,0x8F,0xFF,0xFF,0x00,0x00,0xFB,0x02,
+0xEF,0x79,0x05,0x00,0x00,0xE8,0x50,0x03,0x31,0x04,0x01,0xDD,0x08,0xDD,0x8F,0xFF,
+0xFF,0x00,0x00,0xFB,0x02,0xEF,0x64,0x05,0x00,0x00,0xE8,0x50,0x03,0x31,0xEF,0x00,
+0xDD,0x0A,0xDD,0x8F,0xFF,0xFF,0x00,0x00,0xFB,0x02,0xEF,0x4F,0x05,0x00,0x00,0xE8,
+0x50,0x03,0x31,0xDA,0x00,0xDD,0x0E,0xDD,0x00,0xFB,0x02,0xEF,0x3E,0x05,0x00,0x00,
+0xE8,0x50,0x03,0x31,0xC9,0x00,0xDD,0x0F,0xDD,0x8F,0xFF,0xFF,0x00,0x00,0xFB,0x02,
+0xEF,0x29,0x05,0x00,0x00,0xE8,0x50,0x03,0x31,0xB4,0x00,0xDD,0x10,0xDD,0x28,0xFB,
+0x02,0xEF,0x18,0x05,0x00,0x00,0xE8,0x50,0x03,0x31,0xA3,0x00,0xDD,0x11,0xDD,0x04,
+0xFB,0x02,0xEF,0x07,0x05,0x00,0x00,0xE8,0x50,0x03,0x31,0x92,0x00,0xDD,0x12,0xDD,
+0x00,0xFB,0x02,0xEF,0xF6,0x04,0x00,0x00,0xE8,0x50,0x03,0x31,0x81,0x00,0xDD,0x14,
+0xDD,0x24,0xFB,0x02,0xEF,0xE5,0x04,0x00,0x00,0xE8,0x50,0x03,0x31,0x70,0x00,0xDD,
+0x15,0xDD,0x08,0xFB,0x02,0xEF,0xD4,0x04,0x00,0x00,0xE8,0x50,0x03,0x31,0x5F,0x00,
+0xDD,0x16,0xDD,0x00,0xFB,0x02,0xEF,0xC3,0x04,0x00,0x00,0xE8,0x50,0x03,0x31,0x4E,
+0x00,0xDD,0x04,0xDD,0x8F,0xCA,0x00,0x00,0x00,0xFB,0x02,0xEF,0xAE,0x04,0x00,0x00,
+0xE8,0x50,0x03,0x31,0x39,0x00,0xDD,0x05,0xDD,0x8F,0xFA,0x00,0x00,0x00,0xFB,0x02,
+0xEF,0x99,0x04,0x00,0x00,0xE8,0x50,0x03,0x31,0x24,0x00,0xDD,0x06,0xDD,0x8F,0xCA,
+0x00,0x00,0x00,0xFB,0x02,0xEF,0x84,0x04,0x00,0x00,0xE8,0x50,0x03,0x31,0x0F,0x00,
+0xDD,0x07,0xDD,0x8F,0xCF,0x00,0x00,0x00,0xFB,0x02,0xEF,0x6F,0x04,0x00,0x00,0x04,
+0xBB,0x8F,0x04,0x04,0xD0,0xAB,0x58,0x5A,0xD0,0x8F,0xE8,0x03,0x00,0x00,0x52,0xE0,
+0x02,0xEA,0x02,0xC4,0x00,0x00,0x0A,0x16,0xBB,0x5C,0xF5,0x52,0xF2,0xD4,0x50,0x11,
+0x0C,0x90,0x80,0xEA,0x06,0xC4,0x00,0x00,0x12,0xDE,0x9A,0x01,0x50,0xBA,0x8F,0x04,
+0x04,0x05,0xBB,0x8F,0x42,0x04,0xD1,0x51,0x02,0x15,0x03,0x31,0xDE,0x01,0xD5,0xAB,
+0x38,0x13,0x06,0xD0,0x01,0x51,0x16,0xBB,0x38,0xD0,0xAB,0x58,0x5A,0xFB,0x00,0xCF,
+0x40,0xFC,0xE8,0x50,0x03,0x31,0xC4,0x01,0xFB,0x00,0xCF,0x0B,0xFC,0xE8,0x50,0x03,
+0x31,0xB9,0x01,0xFB,0x00,0xCF,0xD0,0xFC,0xE8,0x50,0x03,0x31,0xAE,0x01,0xDD,0x8F,
+0xFF,0x00,0x00,0x00,0xFB,0x01,0xEF,0xC0,0x03,0x00,0x00,0xE8,0x50,0x03,0x31,0x9B,
+0x01,0xDD,0x02,0xDD,0x8F,0x40,0x00,0x00,0x00,0xFB,0x02,0xEF,0xDE,0x03,0x00,0x00,
+0xE8,0x50,0x03,0x31,0x86,0x01,0xDD,0x01,0xFB,0x01,0xEF,0x9C,0x03,0x00,0x00,0xE8,
+0x50,0x03,0x31,0x77,0x01,0xB0,0x08,0xEA,0x4C,0xC0,0x00,0x00,0xB0,0x00,0xEA,0x4E,
+0xC0,0x00,0x00,0xB0,0x00,0xEA,0x50,0xC0,0x00,0x00,0xB0,0x0F,0xEA,0x52,0xC0,0x00,
+0x00,0xB0,0x08,0xEA,0x40,0xC0,0x00,0x00,0xB0,0x0F,0xEA,0x42,0xC0,0x00,0x00,0xB0,
+0x00,0xEA,0x44,0xC0,0x00,0x00,0xB0,0x00,0xEA,0x46,0xC0,0x00,0x00,0x9A,0xAB,0x51,
+0x56,0xA5,0x56,0x08,0x57,0xB0,0x57,0xEA,0x1C,0xC0,0x00,0x00,0xB0,0x57,0xEA,0x36,
+0xC0,0x00,0x00,0x9A,0xAB,0x52,0x56,0xD6,0x56,0xA5,0x56,0x08,0x57,0xB0,0x57,0xEA,
+0x1E,0xC0,0x00,0x00,0xB0,0x57,0xEA,0x38,0xC0,0x00,0x00,0x9A,0xAB,0x4D,0x56,0xA5,
+0x56,0x0F,0x57,0xB0,0x57,0xEA,0x20,0xC0,0x00,0x00,0xB0,0x57,0xEA,0x3A,0xC0,0x00,
+0x00,0x9A,0xAB,0x4E,0x56,0xD6,0x56,0xA5,0x56,0x0F,0x57,0xB0,0x57,0xEA,0x22,0xC0,
+0x00,0x00,0xB0,0x57,0xEA,0x3C,0xC0,0x00,0x00,0xD4,0x56,0xE9,0xAB,0x51,0x04,0x9A,
+0x8F,0xFF,0x56,0xDD,0x0C,0xDD,0x56,0xFB,0x02,0xEF,0x20,0x03,0x00,0x00,0xE8,0x50,
+0x03,0x31,0xC8,0x00,0xB2,0x00,0x56,0xE9,0xAB,0x51,0x05,0x3C,0x8F,0x00,0xFF,0x56,
+0xDD,0x0D,0xDD,0x56,0xFB,0x02,0xEF,0x03,0x03,0x00,0x00,0xE8,0x50,0x03,0x31,0xAB,
+0x00,0xDD,0x0B,0xDD,0x00,0xFB,0x02,0xEF,0xF2,0x02,0x00,0x00,0xE8,0x50,0x03,0x31,
+0x9A,0x00,0xDD,0x08,0xDD,0x8F,0xFF,0xFF,0x00,0x00,0xFB,0x02,0xEF,0xDD,0x02,0x00,
+0x00,0xE8,0x50,0x03,0x31,0x85,0x00,0xDD,0x0E,0xDD,0x00,0xFB,0x02,0xEF,0xCC,0x02,
+0x00,0x00,0xE9,0x50,0x77,0xDD,0x0F,0xDD,0x8F,0xFF,0xFF,0x00,0x00,0xFB,0x02,0xEF,
+0xBA,0x02,0x00,0x00,0xE9,0x50,0x65,0xDD,0x10,0xDD,0x28,0xFB,0x02,0xEF,0xAC,0x02,
+0x00,0x00,0xE9,0x50,0x57,0xDD,0x11,0xDD,0x04,0xFB,0x02,0xEF,0x9E,0x02,0x00,0x00,
+0xE9,0x50,0x49,0xDD,0x12,0xDD,0x00,0xFB,0x02,0xEF,0x90,0x02,0x00,0x00,0xE9,0x50,
+0x3B,0xDD,0x04,0xDD,0x8F,0xCA,0x00,0x00,0x00,0xFB,0x02,0xEF,0x7E,0x02,0x00,0x00,
+0xE9,0x50,0x29,0xDD,0x16,0xDD,0x01,0xFB,0x02,0xEF,0x70,0x02,0x00,0x00,0xE9,0x50,
+0x1B,0xDD,0x02,0xDD,0x8F,0x60,0x00,0x00,0x00,0xFB,0x02,0xEF,0x5E,0x02,0x00,0x00,
+0xD1,0x51,0x02,0x13,0x07,0xB0,0x2F,0xEA,0x00,0xC8,0x00,0x00,0xBA,0x8F,0x42,0x04,
+0x05,0xBB,0x8F,0x0E,0x04,0xD0,0xAB,0x58,0x5A,0x91,0xAB,0x50,0xAB,0x51,0x1F,0x07,
+0x91,0xAB,0x50,0xAB,0x52,0x1B,0x05,0x90,0xAB,0x51,0xAB,0x50,0x91,0xAB,0x4C,0xAB,
+0x4D,0x1F,0x07,0x91,0xAB,0x4C,0xAB,0x4E,0x1B,0x05,0x90,0xAB,0x4D,0xAB,0x4C,0x9A,
+0x51,0x52,0xE4,0x07,0x52,0x12,0xD0,0xAB,0x40,0x53,0xC2,0x20,0x52,0x19,0x42,0x91,
+0x51,0x8F,0x7F,0x12,0x0F,0x31,0x97,0x00,0xD0,0xAB,0x44,0x53,0xC2,0x20,0x52,0x18,
+0x03,0x31,0x8B,0x00,0x91,0xAB,0x50,0xAB,0x52,0x19,0x03,0x31,0x81,0x00,0x91,0xAB,
+0x4C,0xAB,0x4E,0x15,0x05,0x90,0xAB,0x4E,0xAB,0x4C,0xC4,0x0F,0x52,0x9E,0x42,0x63,
+0x51,0xFB,0x00,0xCF,0x36,0xF7,0x96,0xAB,0x50,0xFB,0x00,0xCF,0xBA,0xF7,0x31,0x5E,
+0x00,0x91,0x0D,0x51,0x12,0x0C,0xFB,0x00,0xCF,0xC0,0xF7,0x90,0xAB,0x51,0xAB,0x50,
+0x11,0x4D,0x91,0x0A,0x51,0x12,0x20,0xFB,0x00,0xCF,0xAF,0xF7,0x96,0xAB,0x4C,0x91,
+0xAB,0x4C,0xAB,0x4E,0x15,0x0A,0x90,0xAB,0x4E,0xAB,0x4C,0xFB,0x00,0xCF,0xEC,0xF7,
+0xFB,0x00,0xCF,0x83,0xF7,0x11,0x28,0x91,0x08,0x51,0x12,0x16,0x91,0xAB,0x51,0xAB,
+0x50,0x13,0x1C,0xFB,0x00,0xCF,0x83,0xF7,0x97,0xAB,0x50,0xFB,0x00,0xCF,0x68,0xF7,
+0x11,0x0D,0x91,0x07,0x51,0x12,0x08,0x90,0x8F,0xA7,0xEA,0x06,0xC4,0x00,0x00,0xBA,
+0x8F,0x0E,0x04,0x9A,0x01,0x50,0x05,0x0C,0x04,0xD0,0xAB,0x58,0x5A,0xDD,0x8F,0xFF,
+0x00,0x00,0x00,0xFB,0x01,0xEF,0x21,0x01,0x00,0x00,0xDD,0x02,0xDD,0x00,0xFB,0x02,
+0xEF,0x49,0x01,0x00,0x00,0xE8,0x50,0x03,0x31,0xA5,0x00,0xDD,0xAC,0x04,0xFB,0x01,
+0xEF,0x06,0x01,0x00,0x00,0xDD,0x02,0xDD,0x8F,0x60,0x00,0x00,0x00,0xFB,0x02,0xEF,
+0x2A,0x01,0x00,0x00,0xE8,0x50,0x03,0x31,0x86,0x00,0xDD,0x0B,0xDD,0xAC,0x08,0xFB,
+0x02,0xEF,0x18,0x01,0x00,0x00,0xE8,0x50,0x03,0x31,0x74,0x00,0xDD,0x01,0xFB,0x01,
+0xCF,0x41,0xF6,0xE9,0x50,0x6A,0xB0,0x00,0xEA,0x26,0xC0,0x00,0x00,0xDD,0x01,0xFB,
+0x01,0xCF,0x30,0xF6,0xE9,0x50,0x59,0xB0,0x8F,0x00,0x20,0xEA,0x28,0xC0,0x00,0x00,
+0xB0,0x8F,0x60,0x03,0xEA,0x26,0xC0,0x00,0x00,0xDD,0x01,0xFB,0x01,0xCF,0x14,0xF6,
+0xE9,0x50,0x3D,0xB0,0x8F,0x00,0x20,0xEA,0x28,0xC0,0x00,0x00,0xB0,0x8F,0xC0,0x06,
+0xEA,0x26,0xC0,0x00,0x00,0xDD,0x01,0xFB,0x01,0xCF,0xF8,0xF5,0xE9,0x50,0x21,0xB0,
+0x8F,0x00,0x20,0xEA,0x28,0xC0,0x00,0x00,0xB0,0x00,0xEA,0x26,0xC0,0x00,0x00,0xDD,
+0x01,0xFB,0x01,0xCF,0xDE,0xF5,0xE9,0x50,0x07,0xDD,0x01,0xFB,0x01,0xCF,0xD4,0xF5,
+0x04,0xDD,0x0D,0xFB,0x01,0xCF,0xCC,0xF5,0xE8,0x50,0x03,0x31,0x5C,0x00,0x78,0x8F,
+0xFE,0x52,0x54,0xAE,0x54,0x54,0x78,0x02,0x54,0x54,0xCB,0x8F,0xFC,0xFF,0xFF,0x00,
+0x52,0x51,0xC8,0x51,0x54,0xB0,0x54,0xEA,0x0C,0xC2,0x00,0x00,0xC1,0x10,0x53,0x54,
+0xAE,0x54,0xEA,0x0E,0xC2,0x00,0x00,0x9B,0x01,0xEA,0x00,0xC2,0x00,0x00,0xA1,0x01,
+0x53,0xEA,0x24,0xC0,0x00,0x00,0xB4,0xEA,0x06,0xC0,0x00,0x00,0xB4,0xEA,0x06,0xC0,
+0x00,0x00,0xDD,0x00,0xFB,0x01,0xCF,0x7B,0xF5,0xE8,0x50,0x03,0x31,0x0B,0x00,0xB0,
+0xEA,0x00,0xC8,0x00,0x00,0x54,0x8A,0x8F,0xF0,0x54,0x05,0x00,0x04,0xD0,0xAB,0x58,
+0x5A,0xDD,0x04,0xFB,0x01,0xCF,0x5C,0xF5,0xE9,0x50,0x22,0xDD,0x06,0xFB,0x01,0xCF,
+0x52,0xF5,0xE9,0x50,0x18,0xB0,0xAC,0x04,0xEA,0x0E,0xC0,0x00,0x00,0xB0,0x8F,0x60,
+0x01,0xEA,0x14,0xC0,0x00,0x00,0xDD,0x06,0xFB,0x01,0xCF,0x37,0xF5,0x04,0x00,0x04,
+0xD0,0xAB,0x58,0x5A,0xDD,0x04,0xFB,0x01,0xCF,0x29,0xF5,0xE9,0x50,0x29,0xDD,0x06,
+0xFB,0x01,0xCF,0x1F,0xF5,0xE9,0x50,0x1F,0xB0,0xAC,0x04,0xEA,0x0E,0xC0,0x00,0x00,
+0xC8,0x8F,0x80,0x01,0x00,0x00,0xAC,0x08,0xB0,0xAC,0x08,0xEA,0x14,0xC0,0x00,0x00,
+0xDD,0x06,0xFB,0x01,0xCF,0xFD,0xF4,0x04,0x01,0x01,0x01,0x01,0xD4,0x50,0xD0,0x8F,
+0x01,0x00,0x00,0x0E,0x51,0x31,0x73,0xF4,0x00,0x00,0xB0,0xBB,0x3C,0x52,0xAA,0x8F,
+0x9F,0xFF,0x52,0xB5,0x52,0x13,0x05,0xB1,0x52,0x20,0x13,0x50,0x9E,0xEA,0x00,0x80,
+0x00,0x00,0x52,0xD0,0x8F,0x00,0x30,0x00,0x00,0x53,0xB5,0x82,0xF5,0x53,0xFB,0x9E,
+0xEF,0x41,0x00,0x00,0x00,0x52,0x3C,0x82,0x53,0x3C,0x82,0x54,0xC0,0x5A,0x54,0x9E,
+0xEF,0x82,0xF4,0xFF,0xFF,0x55,0x3C,0x85,0x56,0xAB,0x62,0x85,0x57,0xB0,0x57,0x64,
+0xAB,0x62,0x64,0x58,0xB1,0x57,0x58,0x12,0x13,0xF5,0x56,0xED,0xC0,0x02,0x52,0xF5,
+0x53,0xD7,0xB0,0xA9,0x0C,0xEA,0x10,0xC2,0x00,0x00,0x11,0x09,0xD4,0x50,0xD0,0x8F,
+0x02,0x00,0x00,0x0E,0x51,0x05,0x04,0x00,0x02,0xC2,0x00,0x00,0x06,0xC2,0x00,0x00,
+0x0E,0xC0,0x00,0x00,0x10,0xC2,0x0F,0xFE,0x00,0x00,0xDD,0x00,0xDD,0x8F,0xFF,0x00,
+0x00,0x00,0xFB,0x02,0xEF,0xBE,0xFD,0xFF,0xFF,0xE9,0x50,0x38,0xB0,0x3E,0xEA,0x00,
+0xC8,0x00,0x00,0x9E,0xEA,0xC0,0x8F,0x00,0x00,0x52,0xD4,0x53,0xB4,0x43,0x62,0xF2,
+0x20,0x53,0xF9,0xB0,0x8F,0xFF,0xFF,0xA2,0x20,0x3C,0x8F,0x46,0x00,0x52,0x3C,0x8F,
+0xB0,0x01,0x53,0x30,0x5B,0xFE,0xE8,0x50,0x0B,0xD4,0x50,0xD0,0x8F,0x1C,0x00,0x00,
+0x0E,0x51,0x11,0x0D,0xE1,0x03,0x54,0x09,0xD4,0x50,0xD0,0x8F,0x1D,0x00,0x00,0x0E,
+0x51,0x05,0x30,0x16,0x02,0xE8,0x50,0x0C,0xD4,0x50,0xD0,0x8F,0x1E,0x00,0x00,0x0E,
+0x51,0x31,0xBD,0x00,0x9A,0x04,0x56,0xE0,0x06,0xBB,0x3C,0x03,0x9A,0x08,0x56,0x30,
+0xDE,0x00,0x30,0x62,0x01,0xD0,0x56,0x55,0x3C,0x8F,0xEC,0x02,0x52,0x9A,0x02,0x53,
+0x30,0x0E,0xFE,0xE8,0x50,0x0C,0xD4,0x50,0xD0,0x8F,0x1F,0x00,0x00,0x0E,0x51,0x31,
+0x8F,0x00,0x91,0x0B,0x54,0x13,0x0C,0xD4,0x50,0xD0,0x8F,0x20,0x00,0x00,0x0E,0x51,
+0x31,0x7E,0x00,0xD6,0x53,0xF4,0x55,0xD8,0x30,0xD1,0x00,0x30,0x29,0x01,0xD0,0x56,
+0x55,0x3C,0x8F,0xEC,0x02,0x52,0x9A,0x02,0x53,0x30,0xD5,0xFD,0xE8,0x50,0x0C,0xD4,
+0x50,0xD0,0x8F,0x21,0x00,0x00,0x0E,0x51,0x31,0x56,0x00,0x91,0x0D,0x54,0x13,0x0C,
+0xD4,0x50,0xD0,0x8F,0x22,0x00,0x00,0x0E,0x51,0x31,0x45,0x00,0xD6,0x53,0xF4,0x55,
+0xD8,0x30,0xC4,0x00,0x30,0x3A,0x01,0xD0,0x56,0x55,0x3C,0x8F,0xEC,0x02,0x52,0x9A,
+0x02,0x53,0x30,0x9C,0xFD,0xE8,0x50,0x0C,0xD4,0x50,0xD0,0x8F,0x23,0x00,0x00,0x0E,
+0x51,0x31,0x1D,0x00,0x91,0x0E,0x54,0x13,0x0C,0xD4,0x50,0xD0,0x8F,0x24,0x00,0x00,
+0x0E,0x51,0x31,0x0C,0x00,0xD6,0x53,0xF4,0x55,0xD8,0xB0,0x0E,0xEA,0x00,0xC8,0x00,
+0x00,0x05,0x0F,0x00,0x00,0x00,0x55,0x00,0xAA,0x00,0x33,0x00,0xCC,0x00,0x0F,0x00,
+0xF0,0x00,0xF0,0x00,0x0F,0x00,0xEF,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x02,0x00,
+0x04,0x00,0x08,0x00,0x10,0x00,0x20,0x00,0x40,0x00,0x80,0x00,0x00,0x01,0x00,0x02,
+0x9E,0xAF,0xD3,0x52,0x9E,0xAF,0xE3,0x53,0x3C,0x83,0x54,0xB0,0x62,0x44,0xEA,0x00,
+0xCE,0x00,0x00,0xA1,0xAF,0xBC,0x62,0x44,0xEA,0x00,0xCA,0x00,0x00,0xA3,0xAF,0xB2,
+0x82,0x44,0xEA,0x00,0xCC,0x00,0x00,0xB5,0x62,0x12,0xDD,0x05,0x9E,0xAF,0xA7,0x52,
+0x9E,0xAF,0xB7,0x53,0x3C,0x83,0x54,0xB0,0x62,0x44,0xEA,0x00,0xCA,0x00,0x00,0xA1,
+0xAF,0x90,0x62,0x44,0xEA,0x00,0xCC,0x00,0x00,0xA3,0xAF,0x86,0x82,0x44,0xEA,0x00,
+0xCE,0x00,0x00,0xB5,0x62,0x12,0xDD,0x05,0x9E,0xCF,0x7A,0xFF,0x52,0x9E,0xAF,0x8A,
+0x53,0x3C,0x83,0x54,0xB0,0x62,0x44,0xEA,0x00,0xCC,0x00,0x00,0xA1,0xCF,0x62,0xFF,
+0x62,0x44,0xEA,0x00,0xCE,0x00,0x00,0xA3,0xCF,0x57,0xFF,0x82,0x44,0xEA,0x00,0xCA,
+0x00,0x00,0xB5,0x62,0x12,0xDB,0x05,0x9E,0xCF,0x67,0xFF,0x53,0x9A,0x02,0x54,0x9A,
+0x8F,0xDB,0x52,0x9A,0x01,0x55,0xD6,0x54,0xB0,0x52,0x44,0xEA,0x00,0xCC,0x00,0x00,
+0xA1,0xCF,0x2E,0xFF,0x52,0x44,0xEA,0x00,0xCE,0x00,0x00,0xA3,0xCF,0x23,0xFF,0x52,
+0x44,0xEA,0x00,0xCA,0x00,0x00,0xF5,0x55,0xDD,0xA3,0x63,0xA3,0x02,0x55,0x78,0x8F,
+0xFF,0x55,0x55,0xD7,0x55,0xC0,0x02,0x53,0xF2,0x8F,0x00,0x01,0x00,0x00,0x54,0xC6,
+0x05,0x9E,0xCF,0x1D,0xFF,0x53,0x9A,0x02,0x54,0x9A,0x8F,0xDB,0x52,0x9A,0x01,0x55,
+0xD6,0x54,0xB0,0x52,0x44,0xEA,0x00,0xCE,0x00,0x00,0xA1,0xCF,0xE4,0xFE,0x52,0x44,
+0xEA,0x00,0xCA,0x00,0x00,0xA3,0xCF,0xD9,0xFE,0x52,0x44,0xEA,0x00,0xCC,0x00,0x00,
+0xF5,0x55,0xDD,0xA3,0x63,0xA3,0x02,0x55,0x78,0x8F,0xFF,0x55,0x55,0xD7,0x55,0xC0,
+0x02,0x53,0xF2,0x8F,0x00,0x01,0x00,0x00,0x54,0xC6,0x05,0x9E,0xCF,0xCB,0xFE,0x52,
+0x9A,0x02,0x54,0x3C,0x82,0x53,0xDD,0x53,0xDD,0x8F,0xFF,0xFF,0x00,0x00,0xDD,0x54,
+0xFB,0x03,0xEF,0x1E,0xF3,0xFF,0xFF,0xE9,0x50,0x04,0xF3,0x0A,0x54,0xE5,0x05,0x00,
+0x00,0x00,0xC1,0xA9,0x10,0xA9,0x0C,0x52,0xC0,0x08,0x52,0xBB,0x8F,0x00,0x03,0xD0,
+0xAB,0x68,0x59,0xC1,0xA9,0x24,0x52,0x58,0x9E,0x68,0xA9,0x04,0xD0,0x68,0xA9,0x20,
+0x9E,0xEF,0xC8,0x00,0x00,0x00,0x68,0xCA,0x03,0x68,0xBA,0x8F,0x00,0x03,0x9E,0xEF,
+0xAC,0x00,0x00,0x00,0x52,0x3C,0x82,0x53,0x3C,0xC2,0x00,0x00,0x59,0xC0,0x5A,0x59,
+0x9E,0xEF,0x5C,0xF1,0xFF,0xFF,0x54,0x9A,0x84,0x55,0x7D,0x54,0x56,0x90,0x3A,0xA9,
+0x04,0x16,0xBB,0x5C,0x90,0x2A,0xA9,0x04,0x16,0xBB,0x5C,0x90,0x1A,0xA9,0x04,0x90,
+0x13,0x69,0x90,0x8F,0x87,0x69,0x16,0xBB,0x5C,0x90,0x00,0xEA,0x08,0xC4,0x00,0x00,
+0x90,0x8F,0x99,0xA9,0x02,0x16,0xBB,0x5C,0x89,0xC2,0x03,0x00,0xC2,0x02,0x00,0xEA,
+0x0A,0xC4,0x00,0x00,0xA8,0x04,0xEA,0x00,0xC2,0x00,0x00,0x90,0x8F,0x45,0xA9,0x04,
+0x9A,0x8F,0x08,0x58,0xDD,0x58,0xD5,0x57,0x1B,0x12,0xE9,0x50,0x0F,0x16,0xBB,0x5C,
+0xF5,0x58,0xF3,0xD4,0x50,0xD0,0x8F,0x25,0x00,0x00,0x0E,0x51,0xD0,0x8E,0x58,0x90,
+0x0A,0xA9,0x04,0x94,0xEA,0x0A,0xC4,0x00,0x00,0xAA,0x04,0xEA,0x00,0xC2,0x00,0x00,
+0xE9,0x50,0x0E,0xC0,0x8F,0x04,0x00,0x00,0x00,0x52,0xD7,0x53,0x1B,0x03,0x31,0x67,
+0xFF,0xDD,0x59,0xD0,0xAB,0x68,0x59,0xD0,0xA9,0x20,0xB9,0x04,0xD0,0x8E,0x59,0x05,
+0x02,0x00,0x00,0xC4,0x01,0x02,0x10,0xC4,0x10,0x20,0x01,0x01,0x01,0x01,0xBB,0x8F,
+0x00,0x01,0xAA,0x04,0xEA,0x00,0xC2,0x00,0x00,0x93,0xA2,0x03,0xEA,0x0A,0xC4,0x00,
+0x00,0x13,0x1C,0x93,0x8F,0x70,0xA9,0x02,0x12,0x41,0x91,0xA9,0x06,0x86,0x12,0x3B,
+0xF5,0x57,0x02,0x11,0x3F,0x93,0xA2,0x02,0xEA,0x0A,0xC4,0x00,0x00,0x13,0x48,0x93,
+0xA2,0x02,0xEA,0x0A,0xC4,0x00,0x00,0x13,0x22,0x90,0x84,0xA9,0x06,0xE0,0x03,0xA9,
+0x02,0x10,0x9A,0x0A,0x58,0xE0,0x03,0xA9,0x02,0x08,0x16,0xBB,0x5C,0xF5,0x58,0xF5,
+0x11,0x09,0xF5,0x55,0x22,0x90,0x08,0xA9,0x04,0x11,0x1C,0xD4,0x50,0xD0,0x8F,0x26,
+0x00,0x00,0x0E,0x51,0x90,0x0A,0xA9,0x04,0x94,0xEA,0x0A,0xC4,0x00,0x00,0xAA,0x04,
+0xEA,0x00,0xC2,0x00,0x00,0x11,0x07,0xA8,0x04,0xEA,0x00,0xC2,0x00,0x00,0xBA,0x8F,
+0x00,0x01,0x02,0x00,0x00,0x00,0xD4,0x52,0xFB,0x00,0xEF,0x43,0xF3,0xFF,0xFF,0x90,
+0x8F,0xFD,0xEA,0x06,0xC4,0x00,0x00,0x9A,0x04,0x53,0xD0,0x8F,0xE8,0x03,0x00,0x00,
+0x55,0xE0,0x00,0xEA,0x02,0xC4,0x00,0x00,0x24,0x16,0xBB,0x5C,0xF5,0x55,0xF2,0xD1,
+0x53,0x03,0x12,0x2E,0x91,0x54,0x8F,0xFD,0x12,0x28,0xD6,0x52,0xD1,0x50,0x02,0x13,
+0x0A,0x9A,0x02,0x50,0xD0,0x8F,0x27,0x00,0x00,0x0A,0x51,0x11,0x21,0x78,0x08,0x54,
+0x54,0x90,0xEA,0x06,0xC4,0x00,0x00,0x54,0xF5,0x53,0xC6,0xB3,0x8F,0x00,0xFF,0x54,
+0x13,0x0C,0xD4,0x50,0xD0,0x8F,0x28,0x00,0x00,0x0A,0x51,0x31,0x61,0x00,0x90,0x8F,
+0x54,0xEA,0x16,0xC4,0x00,0x00,0x9A,0x04,0x53,0xD0,0x8F,0xE8,0x03,0x00,0x00,0x55,
+0xE0,0x00,0xEA,0x12,0xC4,0x00,0x00,0x26,0x16,0xBB,0x5C,0xF5,0x55,0xF2,0xE1,0x00,
+0x52,0x3D,0xD1,0x53,0x03,0x12,0x2F,0x91,0x54,0x8F,0x54,0x12,0x29,0xD1,0x50,0x02,
+0x13,0x0A,0x9A,0x02,0x50,0xD0,0x8F,0x29,0x00,0x00,0x09,0x51,0x11,0x21,0x78,0x08,
+0x54,0x54,0x90,0xEA,0x16,0xC4,0x00,0x00,0x54,0xF5,0x53,0xC4,0x78,0x8F,0xF8,0x54,
+0x54,0x91,0x54,0x20,0x19,0x09,0xD4,0x50,0xD0,0x8F,0x2A,0x00,0x00,0x09,0x51,0x05,
+0x00,0x00,0xD1,0x50,0x02,0x12,0x03,0x31,0x83,0x00,0xD4,0xAB,0x38,0x94,0xAB,0x4C,
+0x90,0x00,0xAB,0x4D,0x90,0x38,0xAB,0x4E,0x94,0xAB,0x50,0x90,0x00,0xAB,0x51,0x90,
+0x8F,0x7F,0xAB,0x52,0x9E,0xEF,0xFC,0xF0,0xFF,0xFF,0xAB,0x1C,0x9E,0xEF,0xDF,0xF7,
+0xFF,0xFF,0xAB,0x24,0x9E,0xEF,0xB9,0xF8,0xFF,0xFF,0xAB,0x20,0x9E,0xEF,0xE0,0xF5,
+0xFF,0xFF,0xAB,0x30,0x9E,0xEF,0xA6,0xF5,0xFF,0xFF,0xAB,0x34,0xDD,0x00,0xDD,0x8F,
+0xFF,0x00,0x00,0x00,0xFB,0x02,0xEF,0x9C,0xF8,0xFF,0xFF,0xE9,0x50,0x26,0xDD,0x51,
+0x9A,0x02,0x51,0x30,0xBC,0xF5,0xD0,0x8E,0x51,0xE9,0x50,0x18,0xFB,0x00,0xEF,0x65,
+0xF2,0xFF,0xFF,0xE9,0x50,0x0E,0xDD,0x51,0x9A,0x07,0x51,0x16,0xBB,0x24,0xD0,0x8E,
+0x51,0xE8,0x50,0x09,0xD4,0x50,0xD0,0x8F,0x2B,0x00,0x00,0x0E,0x51,0x05,0x9E,0xEA,
+0x00,0x80,0x00,0x00,0x58,0xD0,0x8F,0x00,0x08,0x00,0x00,0x59,0x9E,0xEF,0xC5,0xEE,
+0xFF,0xFF,0x54,0x3C,0x84,0x55,0xB0,0x64,0x68,0xB1,0x84,0x68,0x12,0x35,0xF5,0x55,
+0xF5,0xD0,0x58,0x52,0xD0,0x59,0x53,0xB0,0x8F,0x55,0x55,0x82,0xF5,0x53,0xF8,0xD0,
+0x58,0x52,0xD0,0x59,0x53,0xB1,0x62,0x8F,0x55,0x55,0x12,0x17,0xB0,0x8F,0xAA,0xAA,
+0x82,0xF5,0x53,0xF1,0xD0,0x59,0x53,0xB1,0x72,0x8F,0xAA,0xAA,0x12,0x05,0xF5,0x53,
+0xF6,0x11,0x09,0xD4,0x50,0xD0,0x8F,0x03,0x00,0x00,0x0E,0x51,0x05,0x00,0xC1,0xA9,
+0x10,0xA9,0x0C,0x52,0xC0,0x04,0x52,0xBB,0x8F,0x00,0x03,0xD0,0xAB,0x68,0x59,0xC1,
+0xA9,0x24,0x52,0x58,0x9E,0x68,0xA9,0x04,0xD0,0x68,0xA9,0x20,0x9E,0xEF,0x55,0x00,
+0x00,0x00,0x68,0xCA,0x03,0x68,0xBA,0x8F,0x00,0x03,0xD0,0x01,0x52,0xB0,0x8F,0x40,
+0x00,0xEA,0x04,0xC0,0x00,0x00,0xB0,0x04,0xEA,0x00,0xC2,0x00,0x00,0xB0,0x00,0xEA,
+0x14,0xC0,0x00,0x00,0x16,0xBB,0x5C,0xB4,0xEA,0x04,0xC0,0x00,0x00,0xAA,0x04,0xEA,
+0x00,0xC2,0x00,0x00,0xE9,0x50,0x0D,0xD5,0x52,0x13,0x09,0xD4,0x50,0xD0,0x8F,0x04,
+0x00,0x00,0x0E,0x51,0xDD,0x59,0xD0,0xAB,0x68,0x59,0xD0,0xA9,0x20,0xB9,0x04,0xD0,
+0x8E,0x59,0x05,0x01,0x01,0x01,0x01,0xE1,0x06,0xEA,0x06,0xC0,0x00,0x00,0x04,0xD7,
+0x52,0x18,0x16,0xB4,0xEA,0x04,0xC0,0x00,0x00,0xAA,0x04,0xEA,0x00,0xC2,0x00,0x00,
+0xD4,0x50,0xD0,0x8F,0x05,0x00,0x00,0x0E,0x51,0x02,0xFB,0x00,0xEF,0xB9,0xEF,0xFF,
+0xFF,0xE9,0x50,0x13,0xFB,0x00,0xEF,0x8D,0xF1,0xFF,0xFF,0xE9,0x50,0x09,0xB0,0x0E,
+0xEA,0x00,0xC8,0x00,0x00,0x11,0x09,0xD4,0x50,0xD0,0x8F,0x06,0x00,0x00,0x0E,0x51,
+0x05,0x00,0x9A,0x08,0x59,0xD2,0x8F,0xFF,0x00,0x00,0x00,0x56,0xE1,0x06,0xBB,0x3C,
+0x06,0x9A,0x04,0x59,0xD2,0x0F,0x56,0xDD,0x04,0xFB,0x01,0xEF,0xC4,0xED,0xFF,0xFF,
+0xE8,0x50,0x03,0x31,0x1B,0x01,0x3E,0xEA,0x40,0xC0,0x00,0x00,0x58,0xB0,0x01,0x88,
+0xB0,0x01,0x88,0x3E,0xEA,0x4C,0xC0,0x00,0x00,0x58,0xB0,0x01,0x88,0xB4,0x88,0xB4,
+0x88,0xB0,0x01,0x88,0xD4,0x54,0xDD,0x8F,0xFF,0x00,0x00,0x00,0xFB,0x01,0xEF,0x28,
+0xF8,0xFF,0xFF,0xE8,0x50,0x03,0x31,0xE8,0x00,0xDD,0x04,0xDD,0x8F,0xCA,0x00,0x00,
+0x00,0xFB,0x02,0xEF,0x46,0xF8,0xFF,0xFF,0xDD,0x16,0xDD,0x01,0xFB,0x02,0xEF,0x3B,
+0xF8,0xFF,0xFF,0xB0,0x00,0xEA,0x48,0xC0,0x00,0x00,0xB0,0x00,0xEA,0x4A,0xC0,0x00,
+0x00,0xB0,0x8F,0xC6,0x07,0xEA,0x14,0xC0,0x00,0x00,0xDD,0x06,0xFB,0x01,0xEF,0x51,
+0xED,0xFF,0xFF,0xE8,0x50,0x03,0x31,0xA8,0x00,0xB0,0x00,0xEA,0x0E,0xC0,0x00,0x00,
+0x78,0x54,0x01,0x55,0xDD,0x55,0xFB,0x01,0xEF,0xCE,0xF7,0xFF,0xFF,0xE8,0x50,0x03,
+0x31,0x8E,0x00,0xB0,0x00,0xEA,0x48,0xC0,0x00,0x00,0xB0,0x00,0xEA,0x4A,0xC0,0x00,
+0x00,0xB0,0x8F,0xC6,0x07,0xEA,0x14,0xC0,0x00,0x00,0xDD,0x06,0xFB,0x01,0xEF,0x11,
+0xED,0xFF,0xFF,0xE8,0x50,0x03,0x31,0x68,0x00,0xB0,0x8F,0xFF,0xFF,0xEA,0x0E,0xC0,
+0x00,0x00,0xDD,0x8F,0xFF,0x00,0x00,0x00,0xFB,0x01,0xEF,0x8C,0xF7,0xFF,0xFF,0xE8,
+0x50,0x03,0x31,0x4C,0x00,0xB0,0x00,0xEA,0x44,0xC0,0x00,0x00,0xB0,0x00,0xEA,0x46,
+0xC0,0x00,0x00,0xB0,0x00,0xEA,0x48,0xC0,0x00,0x00,0xB0,0x00,0xEA,0x4A,0xC0,0x00,
+0x00,0xB0,0x8F,0xB0,0x0B,0xEA,0x14,0xC0,0x00,0x00,0xDD,0x05,0xFB,0x01,0xEF,0xC1,
+0xEC,0xFF,0xFF,0xE8,0x50,0x03,0x31,0x18,0x00,0x3C,0xEA,0x0E,0xC0,0x00,0x00,0x57,
+0x8A,0x56,0x57,0x91,0x55,0x57,0x12,0x09,0xF2,0x59,0x54,0x02,0x11,0x0C,0x31,0x05,
+0xFF,0xD4,0x50,0xD0,0x8F,0x07,0x00,0x00,0x0E,0x51,0x05,0x00,0x00,0x00,0xBB,0x03,
+0x9E,0xEF,0x47,0x04,0x00,0x00,0x56,0x28,0x8F,0x3F,0x00,0x66,0xA9,0x28,0xBA,0x03,
+0x9A,0x04,0x52,0xE0,0x06,0xBB,0x3C,0x03,0x9A,0x08,0x52,0xD4,0x53,0x78,0x53,0x01,
+0x56,0xDD,0x56,0xFB,0x01,0xEF,0x01,0xF7,0xFF,0xFF,0xE8,0x50,0x03,0x31,0x05,0x01,
+0xDD,0x16,0xDD,0x01,0xFB,0x02,0xEF,0x23,0xF7,0xFF,0xFF,0xE8,0x50,0x03,0x31,0xF4,
+0x00,0xDD,0x10,0xDD,0x30,0xFB,0x02,0xEF,0x12,0xF7,0xFF,0xFF,0xE8,0x50,0x03,0x31,
+0xE3,0x00,0x9E,0xEF,0x1B,0xEC,0xFF,0xFF,0x54,0xD0,0x84,0x55,0x9E,0xEA,0x40,0xC0,
+0x00,0x00,0x56,0xB0,0x20,0x86,0xB0,0x01,0x86,0xB4,0x86,0xB4,0x86,0xB4,0x86,0xB4,
+0x86,0xB0,0x20,0x86,0xB4,0x86,0xB4,0x86,0xB0,0x01,0x86,0xB0,0x8F,0xC6,0x07,0xEA,
+0x14,0xC0,0x00,0x00,0xDD,0x06,0xFB,0x01,0xEF,0x07,0xEC,0xFF,0xFF,0xE8,0x50,0x03,
+0x31,0xA2,0x00,0xB0,0x64,0xEA,0x0E,0xC0,0x00,0x00,0xDD,0x06,0xFB,0x01,0xEF,0xF1,
+0xEB,0xFF,0xFF,0xE8,0x50,0x03,0x31,0x8C,0x00,0xB0,0xA4,0x02,0xEA,0x0E,0xC0,0x00,
+0x00,0xDD,0x04,0xFB,0x01,0xEF,0xDA,0xEB,0xFF,0xFF,0xE8,0x50,0x03,0x31,0x75,0x00,
+0x9E,0xEA,0x44,0xC0,0x00,0x00,0x56,0xB4,0x86,0xB4,0x86,0x9E,0xEA,0x48,0xC0,0x00,
+0x00,0x56,0xB4,0x86,0xB4,0x86,0xB0,0x8F,0xC0,0x0B,0xEA,0x14,0xC0,0x00,0x00,0xDD,
+0x05,0xFB,0x01,0xEF,0xAC,0xEB,0xFF,0xFF,0xE9,0x50,0x4A,0xB1,0xEA,0x0E,0xC0,0x00,
+0x00,0x84,0x12,0x41,0xDD,0x05,0xFB,0x01,0xEF,0x97,0xEB,0xFF,0xFF,0xE9,0x50,0x35,
+0xB1,0xEA,0x0E,0xC0,0x00,0x00,0x84,0x12,0x2C,0xD7,0x55,0x15,0x03,0x31,0x4C,0xFF,
+0xDD,0x16,0xDD,0x00,0xFB,0x02,0xEF,0x43,0xF6,0xFF,0xFF,0xE9,0x50,0x17,0xDD,0x10,
+0xDD,0x28,0xFB,0x02,0xEF,0x35,0xF6,0xFF,0xFF,0xE9,0x50,0x09,0xF2,0x52,0x53,0x02,
+0x11,0x1D,0x31,0xE8,0xFE,0xD4,0x50,0xD0,0x8F,0x08,0x00,0x00,0x0D,0x51,0xD1,0x04,
+0x53,0x14,0x09,0xD4,0x50,0xD0,0x8F,0x09,0x00,0x00,0x0C,0x51,0x31,0xFD,0x02,0x3C,
+0x8F,0x55,0x55,0x54,0xDD,0x04,0xFB,0x01,0xEF,0x37,0xEB,0xFF,0xFF,0xE8,0x50,0x03,
+0x31,0xE0,0x02,0xB0,0x00,0xEA,0x1C,0xC0,0x00,0x00,0xB0,0x8F,0x00,0x04,0xEA,0x1E,
+0xC0,0x00,0x00,0xB0,0x00,0xEA,0x20,0xC0,0x00,0x00,0xB0,0x8F,0x00,0x08,0xEA,0x22,
+0xC0,0x00,0x00,0xDD,0x8F,0xFF,0x00,0x00,0x00,0xFB,0x01,0xEF,0x9B,0xF5,0xFF,0xFF,
+0xE8,0x50,0x03,0x31,0xAD,0x02,0xDD,0x54,0xDD,0x8F,0xFF,0x00,0x00,0x00,0xFB,0x02,
+0xEF,0x52,0xF4,0xFF,0xFF,0xE8,0x50,0x03,0x31,0x98,0x02,0xD4,0x53,0x78,0x53,0x01,
+0x56,0xDD,0x56,0xFB,0x01,0xEF,0x71,0xF5,0xFF,0xFF,0xE8,0x50,0x03,0x31,0x7A,0x00,
+0xDD,0x14,0xDD,0x30,0xFB,0x02,0xEF,0x93,0xF5,0xFF,0xFF,0xE8,0x50,0x03,0x31,0x69,
+0x00,0x9E,0xEA,0x40,0xC0,0x00,0x00,0x56,0xB0,0x8F,0x00,0x04,0x86,0xB0,0x8F,0x00,
+0x08,0x86,0xB4,0x86,0xB4,0x86,0xB4,0x86,0xB4,0x86,0xB0,0x8F,0x00,0x04,0x86,0xB4,
+0x86,0xB4,0x86,0xB0,0x8F,0x00,0x08,0x86,0xB0,0x8F,0xC4,0x0B,0xEA,0x14,0xC0,0x00,
+0x00,0xDD,0x8F,0x00,0x00,0x02,0x00,0xDD,0x54,0xFB,0x02,0xA9,0x28,0xE8,0x50,0x03,
+0x31,0x27,0x00,0xDD,0x14,0xDD,0x28,0xFB,0x02,0xEF,0x40,0xF5,0xFF,0xFF,0xE8,0x50,
+0x03,0x31,0x16,0x00,0xF2,0x52,0x53,0x02,0x11,0x03,0x31,0x80,0xFF,0xB2,0x54,0x54,
+0xB1,0x54,0x8F,0x55,0x55,0x13,0x1D,0x31,0x49,0xFF,0xD4,0x50,0xD0,0x8F,0x0A,0x00,
+0x00,0x0D,0x51,0xD1,0x04,0x53,0x14,0x09,0xD4,0x50,0xD0,0x8F,0x0B,0x00,0x00,0x0C,
+0x51,0x31,0xF8,0x01,0x9E,0xEF,0x32,0x02,0x00,0x00,0x54,0x3C,0x84,0x55,0xDD,0x8F,
+0xFF,0x00,0x00,0x00,0xFB,0x01,0xEF,0xC0,0xF4,0xFF,0xFF,0xE8,0x50,0x03,0x31,0xD2,
+0x01,0xDD,0x16,0xDD,0x01,0xFB,0x02,0xEF,0xE2,0xF4,0xFF,0xFF,0xE8,0x50,0x03,0x31,
+0xC1,0x01,0x9E,0xEF,0x88,0xEC,0xFF,0xFF,0x56,0x3C,0x86,0x57,0x3C,0x86,0x58,0xC0,
+0x5A,0x58,0xB0,0x86,0x88,0xF5,0x57,0xFA,0xDD,0x04,0xFB,0x01,0xEF,0xF3,0xE9,0xFF,
+0xFF,0xE8,0x50,0x03,0x31,0x9C,0x01,0xB0,0x84,0xEA,0x48,0xC0,0x00,0x00,0xB0,0x84,
+0xEA,0x4A,0xC0,0x00,0x00,0xB0,0x8F,0xC6,0x07,0xEA,0x14,0xC0,0x00,0x00,0xDD,0x06,
+0xFB,0x01,0xEF,0xCD,0xE9,0xFF,0xFF,0xE8,0x50,0x03,0x31,0x76,0x01,0xB0,0x84,0xEA,
+0x0E,0xC0,0x00,0x00,0xDD,0x06,0xFB,0x01,0xEF,0xB7,0xE9,0xFF,0xFF,0xE8,0x50,0x03,
+0x31,0x60,0x01,0xB0,0x84,0xEA,0x0E,0xC0,0x00,0x00,0xF5,0x55,0xAB,0xDD,0x16,0xDD,
+0x00,0xFB,0x02,0xEF,0x66,0xF4,0xFF,0xFF,0xE8,0x50,0x03,0x31,0x45,0x01,0xDD,0x10,
+0xDD,0x00,0xFB,0x02,0xEF,0x55,0xF4,0xFF,0xFF,0xE8,0x50,0x03,0x31,0x34,0x01,0xDD,
+0x12,0xDD,0x00,0xFB,0x02,0xEF,0x44,0xF4,0xFF,0xFF,0xE8,0x50,0x03,0x31,0x23,0x01,
+0xDD,0x04,0xDD,0x8F,0xC3,0x00,0x00,0x00,0xFB,0x02,0xEF,0x2F,0xF4,0xFF,0xFF,0xE8,
+0x50,0x03,0x31,0x0E,0x01,0x9E,0xEA,0x40,0xC0,0x00,0x00,0x58,0xB0,0x8F,0x00,0x04,
+0x88,0xB0,0x8F,0x00,0x08,0x88,0xB4,0x88,0xB4,0x88,0xB4,0x88,0xB4,0x88,0xB0,0x8F,
+0x00,0x04,0x88,0xB4,0x88,0xB4,0x88,0xB0,0x8F,0x00,0x08,0x88,0xB0,0x8F,0xC0,0x06,
+0xEA,0x14,0xC0,0x00,0x00,0xDD,0x04,0xDD,0x8F,0xCA,0x00,0x00,0x00,0xFB,0x02,0xEF,
+0xEA,0xF3,0xFF,0xFF,0xE8,0x50,0x03,0x31,0xC9,0x00,0xD4,0x53,0x78,0x53,0x01,0x56,
+0xDD,0x56,0xFB,0x01,0xEF,0xA2,0xF3,0xFF,0xFF,0xE8,0x50,0x03,0x31,0x9B,0x00,0x9E,
+0xEF,0xF7,0x00,0x00,0x00,0x54,0x3C,0x84,0x55,0xDD,0x14,0xDD,0x30,0xFB,0x02,0xEF,
+0xBA,0xF3,0xFF,0xFF,0xE8,0x50,0x03,0x31,0x80,0x00,0x9E,0xEF,0x60,0xEB,0xFF,0xFF,
+0x56,0x3C,0x86,0x57,0x3C,0x86,0x58,0xC0,0x5A,0x58,0xB0,0x86,0x88,0xF5,0x57,0xFA,
+0xB0,0x84,0xEA,0x44,0xC0,0x00,0x00,0xB0,0x84,0xEA,0x46,0xC0,0x00,0x00,0xB0,0x8F,
+0xC4,0x0B,0xEA,0x14,0xC0,0x00,0x00,0xDD,0x05,0xFB,0x01,0xEF,0xB4,0xE8,0xFF,0xFF,
+0xE8,0x50,0x03,0x31,0x44,0x00,0xB2,0xEA,0x0E,0xC0,0x00,0x00,0x56,0xB1,0x56,0x84,
+0x12,0x38,0xDD,0x05,0xFB,0x01,0xEF,0x99,0xE8,0xFF,0xFF,0xE8,0x50,0x03,0x31,0x29,
+0x00,0xB2,0xEA,0x0E,0xC0,0x00,0x00,0x56,0xB1,0x56,0x84,0x12,0x1D,0xB4,0xEA,0x14,
+0xC0,0x00,0x00,0xF5,0x55,0xAA,0xDD,0x14,0xDD,0x28,0xFB,0x02,0xEF,0x3D,0xF3,0xFF,
+0xFF,0xF2,0x52,0x53,0x02,0x11,0x25,0x31,0x52,0xFF,0xD4,0x50,0xD0,0x8F,0x0C,0x00,
+0x00,0x0D,0x51,0xD1,0x04,0x53,0x14,0x09,0xD4,0x50,0xD0,0x8F,0x0D,0x00,0x00,0x0C,
+0x51,0x11,0x09,0xD4,0x50,0xD0,0x8F,0x0E,0x00,0x00,0x0E,0x51,0x05,0x3C,0x00,0xD4,
+0x50,0xD0,0xAC,0x08,0x52,0x9E,0xEA,0x0E,0xC0,0x00,0x00,0x53,0x3C,0xAC,0x04,0x54,
+0xE0,0x05,0xEA,0x06,0xC0,0x00,0x00,0x18,0xD0,0x8F,0xF4,0x01,0x00,0x00,0x55,0xE0,
+0x05,0xEA,0x06,0xC0,0x00,0x00,0x09,0x16,0xBB,0x5C,0xF5,0x55,0xF2,0x31,0x0B,0x00,
+0xB1,0x63,0x54,0x12,0x06,0xF5,0x52,0xD8,0x9A,0x01,0x50,0x04,0x22,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x11,0x11,0x11,0x11,0x40,0x00,
+0x00,0x00,0x22,0x22,0x22,0x22,0x80,0x00,0x00,0x00,0x33,0x33,0x33,0x33,0x00,0x01,
+0x00,0x00,0x44,0x44,0x44,0x44,0x00,0x02,0x00,0x00,0x55,0x55,0x55,0x55,0x00,0x00,
+0x01,0x00,0x66,0x66,0x66,0x66,0x00,0x00,0x02,0x00,0x77,0x77,0x77,0x77,0x00,0x00,
+0x04,0x00,0x88,0x88,0x88,0x88,0x00,0x00,0x08,0x00,0x99,0x99,0x99,0x99,0x00,0x00,
+0x10,0x00,0xAA,0xAA,0xAA,0xAA,0x00,0x00,0x20,0x00,0xBB,0xBB,0xBB,0xBB,0x00,0x00,
+0x40,0x00,0xCC,0xCC,0xCC,0xCC,0x00,0x00,0x80,0x00,0xDD,0xDD,0xDD,0xDD,0x00,0x00,
+0x00,0x01,0xEE,0xEE,0xEE,0xEE,0x00,0x00,0x00,0x02,0xFF,0xFF,0xFF,0xFF,0xE0,0x03,
+0xFF,0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x11,0x11,0x11,0x11,0xE0,0x03,
+0xFF,0x05,0x22,0x22,0x22,0x22,0xE0,0x03,0xFF,0x06,0x33,0x33,0x33,0x33,0xE0,0x03,
+0x7F,0x07,0x44,0x44,0x44,0x44,0xE0,0x03,0xBF,0x07,0x55,0x55,0x55,0x55,0xE0,0x03,
+0xDF,0x07,0x66,0x66,0x66,0x66,0xE0,0x03,0xEF,0x07,0x77,0x77,0x77,0x77,0xE0,0x03,
+0xF7,0x07,0x88,0x88,0x88,0x88,0xE0,0x03,0xFB,0x07,0x99,0x99,0x99,0x99,0x00,0x00,
+0x10,0x00,0xAA,0xAA,0xAA,0xAA,0x00,0x00,0x20,0x00,0xBB,0xBB,0xBB,0xBB,0x00,0x00,
+0x40,0x00,0xCC,0xCC,0xCC,0xCC,0x00,0x00,0x80,0x00,0xDD,0xDD,0xDD,0xDD,0x00,0x00,
+0x00,0x01,0xEE,0xEE,0xEE,0xEE,0x00,0x00,0x00,0x02,0xFF,0xFF,0xFF,0xFF,0xC0,0x03,
+0xFF,0x07,0x00,0x00,0x00,0x00,0xE0,0x03,0xFF,0x07,0x11,0x11,0x11,0x11,0x9A,0x08,
+0x57,0xE1,0x06,0xBB,0x3C,0x03,0x9A,0x04,0x57,0x3E,0xEA,0x1C,0xC0,0x00,0x00,0x58,
+0xB4,0x88,0xB0,0x8F,0x00,0x04,0x88,0xB4,0x88,0xB0,0x8F,0x60,0x03,0x88,0xDD,0x00,
+0xDD,0x8F,0xFF,0x00,0x00,0x00,0xFB,0x02,0xEF,0x2A,0xF0,0xFF,0xFF,0xE8,0x50,0x03,
+0x31,0xFA,0x01,0xDD,0x0A,0xDD,0x8F,0x55,0x55,0x00,0x00,0xFB,0x02,0xEF,0x7C,0xF1,
+0xFF,0xFF,0xE8,0x50,0x03,0x31,0xE5,0x01,0x9E,0xEA,0x48,0xC0,0x00,0x00,0x58,0xB0,
+0x04,0x88,0xB4,0x88,0xB0,0x08,0x88,0xB4,0x88,0xB4,0x88,0xB0,0x20,0x88,0xB0,0x8F,
+0xC0,0x06,0xEA,0x14,0xC0,0x00,0x00,0x7C,0x52,0xC0,0x8F,0x11,0x11,0x00,0x00,0x52,
+0x78,0x53,0x01,0x54,0xDD,0x07,0xFB,0x01,0xEF,0x77,0xE6,0xFF,0xFF,0xE8,0x50,0x03,
+0x31,0xAA,0x01,0xB0,0x54,0xEA,0x18,0xC0,0x00,0x00,0xB0,0x8F,0x40,0x01,0xEA,0x1A,
+0xC0,0x00,0x00,0xDD,0x07,0xFB,0x01,0xEF,0x58,0xE6,0xFF,0xFF,0xE8,0x50,0x03,0x31,
+0x8B,0x01,0xB0,0x52,0xEA,0x18,0xC0,0x00,0x00,0xA9,0x8F,0x80,0x01,0x0B,0xEA,0x1A,
+0xC0,0x00,0x00,0xF2,0x57,0x53,0xB2,0xDD,0x0C,0xDD,0x0F,0xFB,0x02,0xEF,0xFC,0xF0,
+0xFF,0xFF,0xE8,0x50,0x03,0x31,0x65,0x01,0xDD,0x0D,0xDD,0x00,0xFB,0x02,0xEF,0xEB,
+0xF0,0xFF,0xFF,0xE8,0x50,0x03,0x31,0x54,0x01,0x3E,0xEA,0x1C,0xC0,0x00,0x00,0x58,
+0xB0,0x04,0x88,0xB0,0x0C,0x88,0xB4,0x88,0xB0,0x20,0x88,0x3C,0x8F,0x73,0x00,0x56,
+0xDD,0x07,0xFB,0x01,0xEF,0xFB,0xE5,0xFF,0xFF,0xE8,0x50,0x03,0x31,0x2E,0x01,0xB0,
+0x8F,0xFF,0x00,0xEA,0x18,0xC0,0x00,0x00,0xB0,0x8F,0x40,0x01,0xEA,0x1A,0xC0,0x00,
+0x00,0xDD,0x07,0xFB,0x01,0xEF,0xDA,0xE5,0xFF,0xFF,0xE8,0x50,0x03,0x31,0x0D,0x01,
+0xB0,0x56,0xEA,0x18,0xC0,0x00,0x00,0xA9,0x8F,0x80,0x01,0x02,0xEA,0x1A,0xC0,0x00,
+0x00,0xB0,0x00,0xEA,0x28,0xC0,0x00,0x00,0xDD,0x01,0xFB,0x01,0xEF,0xB3,0xE5,0xFF,
+0xFF,0xE8,0x50,0x03,0x31,0xE6,0x00,0xDD,0x01,0xFB,0x01,0xEF,0xA4,0xE5,0xFF,0xFF,
+0xE8,0x50,0x03,0x31,0xD7,0x00,0xD4,0x53,0x9A,0x04,0x52,0x7C,0x54,0x80,0x01,0x54,
+0x78,0x55,0x01,0x56,0xDD,0x56,0xFB,0x01,0xEF,0x1E,0xF0,0xFF,0xFF,0xE8,0x50,0x03,
+0x31,0xBA,0x00,0xDD,0x14,0xDD,0x30,0xFB,0x02,0xEF,0x40,0xF0,0xFF,0xFF,0xE8,0x50,
+0x03,0x31,0xA9,0x00,0x3E,0xEA,0x40,0xC0,0x00,0x00,0x58,0xB0,0x04,0x88,0xB0,0x20,
+0x88,0xB0,0x52,0x88,0xB4,0x88,0xB4,0x88,0xB4,0x88,0xB0,0x04,0x88,0xB4,0x88,0xB4,
+0x88,0xB0,0x20,0x88,0xB0,0x8F,0xC4,0x0B,0xEA,0x14,0xC0,0x00,0x00,0xD0,0x20,0x58,
+0xDD,0x05,0xFB,0x01,0xEF,0x3B,0xE5,0xFF,0xFF,0xE8,0x50,0x03,0x31,0x6E,0x00,0xAB,
+0x8F,0xF0,0xFF,0xEA,0x0E,0xC0,0x00,0x00,0x56,0xB1,0x56,0x54,0x12,0x44,0xF5,0x58,
+0xDF,0xF2,0x57,0x55,0x02,0x11,0x0A,0xD5,0x53,0x13,0x03,0x31,0x82,0xFF,0x31,0x7C,
+0xFF,0xD4,0x55,0xD5,0x53,0x14,0x09,0xD6,0x53,0xD4,0x54,0xD4,0x52,0x31,0x70,0xFF,
+0xD1,0x53,0x01,0x14,0x0B,0xD6,0x53,0x9A,0x08,0x52,0x9A,0x05,0x54,0x31,0x60,0xFF,
+0xD1,0x53,0x02,0x14,0x0A,0xD6,0x53,0x9A,0x0C,0x52,0xD4,0x54,0x31,0x51,0xFF,0x31,
+0x24,0x00,0xB1,0x04,0x55,0x14,0x0B,0xD4,0x50,0xD0,0x8F,0x0F,0x00,0x00,0x0D,0x51,
+0x11,0x14,0xD4,0x50,0xD0,0x8F,0x10,0x00,0x00,0x0C,0x51,0x11,0x09,0xD4,0x50,0xD0,
+0x8F,0x11,0x00,0x00,0x0E,0x51,0x05,0x00,0x00,0x00,0x9A,0x08,0x57,0xE1,0x06,0xBB,
+0x3C,0x03,0x9A,0x04,0x57,0x3E,0xEA,0x1C,0xC0,0x00,0x00,0x58,0xB4,0x88,0xB0,0x8F,
+0x00,0x04,0x88,0xB4,0x88,0xB0,0x8F,0x00,0x08,0x88,0xDD,0x00,0xDD,0x8F,0xFF,0x00,
+0x00,0x00,0xFB,0x02,0xEF,0xEE,0xED,0xFF,0xFF,0xE8,0x50,0x03,0x31,0x56,0x02,0xDD,
+0x0C,0xDD,0x8F,0x00,0x00,0x01,0x00,0xFB,0x02,0xEF,0x40,0xEF,0xFF,0xFF,0xE8,0x50,
+0x03,0x31,0x41,0x02,0xDD,0x0D,0xDD,0x8F,0xFF,0xFF,0x00,0x00,0xFB,0x02,0xEF,0x2B,
+0xEF,0xFF,0xFF,0xE8,0x50,0x03,0x31,0x2C,0x02,0xDD,0x0A,0xDD,0x8F,0xAA,0xAA,0x00,
+0x00,0xFB,0x02,0xEF,0x16,0xEF,0xFF,0xFF,0xE8,0x50,0x03,0x31,0x17,0x02,0x3E,0xEA,
+0x48,0xC0,0x00,0x00,0x58,0xB0,0x8F,0x40,0x01,0x88,0xB0,0x8F,0xA6,0x01,0x88,0xB0,
+0x10,0x88,0xB4,0x88,0xB4,0x88,0xB0,0x14,0x88,0xB0,0x8F,0xC0,0x06,0xEA,0x14,0xC0,
+0x00,0x00,0xDD,0x04,0xFB,0x01,0xEF,0x19,0xE4,0xFF,0xFF,0xE8,0x50,0x03,0x31,0xE4,
+0x01,0xDD,0x01,0xFB,0x01,0xEF,0x0A,0xE4,0xFF,0xFF,0xE8,0x50,0x03,0x31,0xD5,0x01,
+0xDD,0x02,0xDD,0x20,0xFB,0x02,0xEF,0xC3,0xEE,0xFF,0xFF,0xE8,0x50,0x03,0x31,0xC4,
+0x01,0x7C,0x52,0xC0,0x8F,0x11,0x11,0x00,0x00,0x53,0x78,0x52,0x01,0x54,0xDD,0x54,
+0xFB,0x01,0xEF,0x74,0xEE,0xFF,0xFF,0xDD,0x0B,0xDD,0x53,0xFB,0x02,0xEF,0x9C,0xEE,
+0xFF,0xFF,0xE8,0x50,0x03,0x31,0x9D,0x01,0xF2,0x57,0x52,0xD7,0xDD,0x04,0xFB,0x01,
+0xEF,0xBF,0xE3,0xFF,0xFF,0xE8,0x50,0x03,0x31,0x8A,0x01,0xDD,0x06,0xFB,0x01,0xEF,
+0xB0,0xE3,0xFF,0xFF,0xE8,0x50,0x03,0x31,0x7B,0x01,0xB0,0x8F,0xFF,0x00,0xEA,0x0E,
+0xC0,0x00,0x00,0xB0,0x8F,0x40,0x01,0xEA,0x14,0xC0,0x00,0x00,0xDD,0x06,0xFB,0x01,
+0xEF,0x8F,0xE3,0xFF,0xFF,0xE8,0x50,0x03,0x31,0x5A,0x01,0xB0,0x8F,0x40,0x01,0xEA,
+0x1C,0xC0,0x00,0x00,0xB0,0x8F,0x50,0x01,0xEA,0x1E,0xC0,0x00,0x00,0xB0,0x8F,0xA6,
+0x01,0xEA,0x20,0xC0,0x00,0x00,0xB0,0x8F,0xBA,0x01,0xEA,0x22,0xC0,0x00,0x00,0xB0,
+0x8F,0x0A,0x10,0xEA,0x28,0xC0,0x00,0x00,0xDD,0x01,0xFB,0x01,0xEF,0x53,0xE3,0xFF,
+0xFF,0xE8,0x50,0x03,0x31,0x1E,0x01,0xDD,0x01,0xFB,0x01,0xEF,0x44,0xE3,0xFF,0xFF,
+0xE8,0x50,0x03,0x31,0x0F,0x01,0x7C,0x52,0x78,0x52,0x01,0x54,0xDD,0x54,0xFB,0x01,
+0xEF,0xC6,0xED,0xFF,0xFF,0xE8,0x50,0x03,0x31,0x89,0x00,0xDD,0x14,0xDD,0x30,0xFB,
+0x02,0xEF,0xE8,0xED,0xFF,0xFF,0xE9,0x50,0x7B,0xC0,0x8F,0x11,0x11,0x00,0x00,0x53,
+0x3C,0x8F,0x40,0x01,0x56,0x30,0xE7,0x00,0xB0,0x8F,0xC4,0x0B,0xEA,0x14,0xC0,0x00,
+0x00,0xDD,0x05,0xFB,0x01,0xEF,0xFA,0xE2,0xFF,0xFF,0xE9,0x50,0x57,0xB5,0xEA,0x0E,
+0xC0,0x00,0x00,0x12,0x4C,0xD4,0x58,0xDD,0x05,0xFB,0x01,0xEF,0xE4,0xE2,0xFF,0xFF,
+0xE9,0x50,0x41,0xB1,0xEA,0x0E,0xC0,0x00,0x00,0x53,0x12,0x35,0xF2,0x0A,0x58,0xE7,
+0xDD,0x05,0xFB,0x01,0xEF,0xCB,0xE2,0xFF,0xFF,0xE9,0x50,0x28,0xB1,0xEA,0x0E,0xC0,
+0x00,0x00,0x8F,0xAA,0xAA,0x12,0x1A,0xF2,0x14,0x58,0xE5,0xDD,0x05,0xFB,0x01,0xEF,
+0xB0,0xE2,0xFF,0xFF,0xE9,0x50,0x0D,0xB5,0xEA,0x0E,0xC0,0x00,0x00,0x12,0x02,0x11,
+0x06,0x31,0x56,0x00,0x31,0x6E,0x00,0x3C,0x8F,0x30,0x01,0x56,0x30,0x70,0x00,0xB0,
+0x8F,0xC4,0x0B,0xEA,0x14,0xC0,0x00,0x00,0xD4,0x58,0xDD,0x05,0xFB,0x01,0xEF,0x81,
+0xE2,0xFF,0xFF,0xE9,0x50,0xDE,0xB5,0xEA,0x0E,0xC0,0x00,0x00,0x12,0xD6,0xF2,0x16,
+0x58,0xE8,0xD1,0x56,0x8F,0x50,0x01,0x00,0x00,0x13,0x08,0x3C,0x8F,0x50,0x01,0x56,
+0x31,0xC9,0xFF,0xDD,0x14,0xDD,0x24,0xFB,0x02,0xEF,0x20,0xED,0xFF,0xFF,0xE9,0x50,
+0x24,0xF2,0x57,0x52,0x02,0x11,0x27,0x31,0x0E,0xFF,0xB1,0x04,0x52,0x14,0x0B,0xD4,
+0x50,0xD0,0x8F,0x12,0x00,0x00,0x0D,0x51,0x11,0x14,0xD4,0x50,0xD0,0x8F,0x13,0x00,
+0x00,0x0C,0x51,0x11,0x09,0xD4,0x50,0xD0,0x8F,0x14,0x00,0x00,0x0E,0x51,0x05,0x3E,
+0xEA,0x40,0xC0,0x00,0x00,0x58,0xB0,0x10,0x88,0xB0,0x16,0x88,0xB0,0x56,0x88,0xB0,
+0x8F,0x9B,0x01,0x88,0xB4,0x88,0xB4,0x88,0xB0,0x10,0x88,0xB4,0x88,0xB4,0x88,0xB0,
+0x16,0x88,0x05,0x00,0x00,0x00,0x9A,0x04,0x52,0xE0,0x06,0xBB,0x3C,0x03,0x9A,0x08,
+0x52,0xC1,0xA9,0x10,0xA9,0x0C,0x53,0xC0,0x00,0x53,0xBB,0x8F,0x00,0x03,0xD0,0xAB,
+0x68,0x59,0xC1,0xA9,0x24,0x53,0x58,0x9E,0x68,0xA9,0x04,0xD0,0x68,0xA9,0x20,0x9E,
+0xEF,0xDE,0x01,0x00,0x00,0x68,0xCA,0x03,0x68,0xBA,0x8F,0x00,0x03,0xD0,0x01,0x53,
+0x3E,0xEA,0x1C,0xC0,0x00,0x00,0x58,0xB4,0x88,0xB0,0x8F,0x00,0x04,0x88,0xB4,0x88,
+0xB0,0x8F,0x00,0x08,0x88,0xDD,0x8F,0xFF,0x00,0x00,0x00,0xFB,0x01,0xEF,0x39,0xEC,
+0xFF,0xFF,0xE8,0x50,0x03,0x31,0x8F,0x01,0xDD,0x04,0xDD,0x8F,0xCA,0x00,0x00,0x00,
+0xFB,0x02,0xEF,0x57,0xEC,0xFF,0xFF,0xE8,0x50,0x03,0x31,0x7A,0x01,0xDD,0x16,0xDD,
+0x01,0xFB,0x02,0xEF,0x46,0xEC,0xFF,0xFF,0xE8,0x50,0x03,0x31,0x69,0x01,0x30,0xA9,
+0x01,0xE8,0x50,0x03,0x31,0x60,0x01,0xB0,0x8F,0x02,0x46,0xEA,0x00,0xC2,0x00,0x00,
+0xBB,0x3F,0x2C,0x1C,0xEF,0x3E,0xE1,0xFF,0xFF,0x8F,0x55,0x8F,0x88,0x00,0xA9,0x28,
+0xBA,0x3F,0xC1,0x69,0x28,0xEA,0x02,0xC2,0x00,0x00,0xB0,0x8F,0x40,0x00,0xEA,0x02,
+0xC0,0x00,0x00,0xB0,0x8F,0xC6,0x07,0xEA,0x14,0xC0,0x00,0x00,0xD0,0x8F,0x88,0x00,
+0x00,0x00,0xEA,0x06,0xC2,0x00,0x00,0xD0,0x8F,0xF4,0x01,0x00,0x00,0x58,0xD5,0x53,
+0x13,0x0F,0x16,0xBB,0x5C,0xF5,0x58,0xF6,0xD4,0x50,0xD0,0x8F,0x15,0x00,0x00,0x0E,
+0x51,0xAA,0x02,0xEA,0x00,0xC2,0x00,0x00,0xB0,0x00,0xEA,0x00,0xC2,0x00,0x00,0xE8,
+0x50,0x03,0x31,0xFB,0x00,0xD4,0x54,0xD0,0x01,0x53,0xBB,0x3F,0x2C,0x00,0xEF,0x0B,
+0xDF,0xFF,0xFF,0x00,0x8F,0x88,0x00,0xC9,0xB0,0x00,0xBA,0x3F,0x78,0x54,0x01,0x55,
+0xDD,0x55,0xFB,0x01,0xEF,0x72,0xEB,0xFF,0xFF,0xE8,0x50,0x03,0x31,0xC8,0x00,0xDD,
+0x10,0xDD,0x30,0xFB,0x02,0xEF,0x94,0xEB,0xFF,0xFF,0xE8,0x50,0x03,0x31,0xB7,0x00,
+0x30,0xF7,0x00,0xE8,0x50,0x03,0x31,0xAE,0x00,0xB0,0x20,0xEA,0x02,0xC0,0x00,0x00,
+0xB0,0x8F,0xC0,0x0B,0xEA,0x14,0xC0,0x00,0x00,0xB0,0x8F,0x02,0x44,0xEA,0x00,0xC2,
+0x00,0x00,0xC1,0x69,0x8F,0xB0,0x00,0x00,0x00,0xEA,0x02,0xC2,0x00,0x00,0xD0,0x8F,
+0x88,0x00,0x00,0x00,0xEA,0x06,0xC2,0x00,0x00,0xD0,0x8F,0xF4,0x01,0x00,0x00,0x58,
+0xD5,0x53,0x13,0x0F,0x16,0xBB,0x5C,0xF5,0x58,0xF6,0xD4,0x50,0xD0,0x8F,0x16,0x00,
+0x00,0x0E,0x51,0xAA,0x02,0xEA,0x00,0xC2,0x00,0x00,0xB0,0x00,0xEA,0x00,0xC2,0x00,
+0x00,0xE8,0x50,0x03,0x31,0x59,0x00,0x9E,0xA9,0x28,0x56,0x9E,0xC9,0xB0,0x00,0x57,
+0xD0,0x22,0x58,0xD1,0x86,0x87,0x13,0x0C,0xD4,0x50,0xD0,0x8F,0x17,0x00,0x00,0x0E,
+0x51,0x31,0x3C,0x00,0xF5,0x58,0xEC,0xDD,0x10,0xDD,0x00,0xFB,0x02,0xEF,0xFC,0xEA,
+0xFF,0xFF,0xE9,0x50,0x22,0xF2,0x52,0x54,0x02,0x11,0x25,0x31,0x29,0xFF,0xD4,0x50,
+0xD0,0x8F,0x18,0x00,0x00,0x0D,0x51,0xD1,0x04,0x54,0x14,0x14,0xD4,0x50,0xD0,0x8F,
+0x19,0x00,0x00,0x0C,0x51,0x11,0x09,0xD4,0x50,0xD0,0x8F,0x1A,0x00,0x00,0x0E,0x51,
+0xDD,0x59,0xD0,0xAB,0x68,0x59,0xD0,0xA9,0x20,0xB9,0x04,0xD0,0x8E,0x59,0x05,0x01,
+0x01,0x01,0x01,0xD7,0x53,0x19,0x0B,0xB3,0x8F,0xE0,0x00,0xEA,0x00,0xC2,0x00,0x00,
+0x13,0x17,0xAA,0x02,0xEA,0x00,0xC2,0x00,0x00,0xB0,0x00,0xEA,0x00,0xC2,0x00,0x00,
+0xD4,0x50,0xD0,0x8F,0x1B,0x00,0x00,0x0E,0x51,0x02,0x3E,0xEA,0x40,0xC0,0x00,0x00,
+0x58,0xB0,0x10,0x88,0xB0,0x8F,0x44,0x00,0x88,0xB4,0x88,0xB4,0x88,0xB4,0x88,0xB4,
+0x88,0xB0,0x10,0x88,0xB4,0x88,0xB4,0x88,0xB0,0x8F,0x44,0x00,0x88,0xB0,0x00,0xEA,
+0x00,0xC2,0x00,0x00,0xD4,0xEA,0x06,0xC2,0x00,0x00,0xB4,0xEA,0x06,0xC2,0x00,0x00,
+0x05,0x00,0x00,0x00,0x23,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x32,0x60,};
+#endif /* ROM_vax_vcb02_bin_H */
diff --git a/VAX/vcb02.bin b/VAX/vcb02.bin
new file mode 100644
index 00000000..eb1e5472
Binary files /dev/null and b/VAX/vcb02.bin differ
diff --git a/Visual Studio Projects/MicroVAX2.vcproj b/Visual Studio Projects/MicroVAX2.vcproj
index 6603b16b..dc0fd6b7 100644
--- a/Visual Studio Projects/MicroVAX2.vcproj
+++ b/Visual Studio Projects/MicroVAX2.vcproj
@@ -348,6 +348,10 @@
RelativePath="..\VAX\vax_fpa.c"
>
+
+
@@ -368,6 +372,10 @@
RelativePath="..\VAX\vax_syscm.c"
>
+
+
@@ -641,6 +649,10 @@
RelativePath="..\VAX\vax_defs.h"
>
+
+
diff --git a/descrip.mms b/descrip.mms
index f8256437..cf05ff4d 100644
--- a/descrip.mms
+++ b/descrip.mms
@@ -777,14 +777,15 @@ VAX630_SOURCE1 = $(VAX630_DIR)VAX_CPU.C,$(VAX630_DIR)VAX_CPU1.C,\
$(VAX630_DIR)VAX630_STDDEV.C,$(VAX630_DIR)VAX630_SYSDEV.C,\
$(VAX630_DIR)VAX630_IO.C,$(VAX630_DIR)VAX630_SYSLIST.C
VAX630_LIB2 = $(LIB_DIR)VAX630L2-$(ARCH).OLB
-VAX630_SOURCE2 = $(PDP11_DIR)PDP11_IO_LIB.C,\
+VAX630_SOURCE2 = $(PDP11_DIR)PDP11_IO_LIB.C,$(PDP11_DIR)PDP11_CR.C,\
$(PDP11_DIR)PDP11_RL.C,$(PDP11_DIR)PDP11_RQ.C,\
$(PDP11_DIR)PDP11_TS.C,$(PDP11_DIR)PDP11_DZ.C,\
- $(PDP11_DIR)PDP11_LP.C,$(PDP11_DIR)PDP11_TD.C,$(PDP11_DIR)PDP11_TQ.C,\
- $(PDP11_DIR)PDP11_XQ.C,$(PDP11_DIR)PDP11_VH.C,\
- $(PDP11_DIR)PDP11_CR.C,$(VAX630_DIR)VAX_VC.C,\
+ $(PDP11_DIR)PDP11_LP.C,$(PDP11_DIR)PDP11_TD.C,\
+ $(PDP11_DIR)PDP11_TQ.C,$(PDP11_DIR)PDP11_XQ.C,\
+ $(PDP11_DIR)PDP11_VH.C,\
+ $(VAX630_DIR)VAX_VA.C,$(VAX630_DIR)VAX_VC.C,\
$(VAX630_DIR)VAX_LK.C,$(VAX630_DIR)VAX_VS.C,\
- $(VAX630_DIR)VAX_2681.C
+ $(VAX630_DIR)VAX_2681.C,$(VAX630_DIR)VAX_GPX.C
.IFDEF ALPHA_OR_IA64
VAX630_OPTIONS = /INCL=($(SIMH_DIR),$(VAX630_DIR),$(PDP11_DIR)$(PCAP_INC))\
/DEF=($(CC_DEFS),"VM_VAX=1","USE_ADDR64=1","USE_INT64=1"$(PCAP_DEFS),"VAX_630=1")
diff --git a/display/sim_ws.c b/display/sim_ws.c
index 0f8cc14f..47a573a0 100644
--- a/display/sim_ws.c
+++ b/display/sim_ws.c
@@ -75,6 +75,7 @@ static const char *window_name;
static uint32 *colors = NULL;
static uint32 ncolors = 0, size_colors = 0;
static uint32 *surface = NULL;
+static uint32 ws_palette[2]; /* Monochrome palette */
typedef struct cursor {
Uint8 *data;
Uint8 *mask;
@@ -394,11 +395,13 @@ ws_init(const char *name, int xp, int yp, int colors, void *dptr)
ypixels = yp;
window_name = name;
surface = (uint32 *)realloc (surface, xpixels*ypixels*sizeof(*surface));
- for (i=0; iwidth, arrow_cursor->height, arrow_cursor->data, arrow_cursor->mask, arrow_cursor->hot_x, arrow_cursor->hot_y);
+ ws_palette[0] = vid_map_rgb (0x00, 0x00, 0x00); /* black */
+ ws_palette[1] = vid_map_rgb (0xFF, 0xFF, 0xFF); /* white */
+ for (i=0; i> 8)) : (0x000000FF | (r & 0xFF00) | ((g & 0xFF00) << 8) | ((b & 0xFF00) << 16));
+ color = vid_map_rgb ((r >> 8) & 0xFF, (g >> 8) & 0xFF, (b >> 8) & 0xFF);
for (i=0; iformat, r, g, b);
+#else
+return SDL_MapRGB (vid_format, r, g, b);
+#endif
+}
+
void vid_draw (int32 x, int32 y, int32 w, int32 h, uint32 *buf)
{
#if SDL_MAJOR_VERSION == 1
@@ -1604,9 +1612,6 @@ if (!initialized) {
sim_debug (SIM_VID_DBG_VIDEO|SIM_VID_DBG_KEY|SIM_VID_DBG_MOUSE, vid_dev, "vid_thread() - Starting\n");
-vid_mono_palette[0] = sim_end ? 0xFF000000 : 0x000000FF; /* Black */
-vid_mono_palette[1] = 0xFFFFFFFF; /* White */
-
memset (&vid_key_state, 0, sizeof(vid_key_state));
#if SDL_MAJOR_VERSION == 1
@@ -1646,6 +1651,8 @@ if (!vid_texture) {
return 0;
}
+vid_format = SDL_AllocFormat (SDL_PIXELFORMAT_ARGB8888);
+
SDL_StopTextInput ();
vid_windowID = SDL_GetWindowID (vid_window);
@@ -2317,8 +2324,6 @@ SDL_Delay (vid_beep_duration + 100);/* Wait for sound to finnish */
#else /* !(defined(USE_SIM_VIDEO) && defined(HAVE_LIBSDL)) */
/* Non-implemented versions */
-uint32 vid_mono_palette[2]; /* Monochrome Color Map */
-
t_stat vid_open (DEVICE *dptr, const char *title, uint32 width, uint32 height, int flags)
{
return SCPE_NOFNC;
@@ -2339,6 +2344,11 @@ t_stat vid_poll_mouse (SIM_MOUSE_EVENT *ev)
return SCPE_EOF;
}
+uint32 vid_map_rgb (uint8 r, uint8 g, uint8 b)
+{
+return 0;
+}
+
void vid_draw (int32 x, int32 y, int32 w, int32 h, uint32 *buf)
{
return;
diff --git a/sim_video.h b/sim_video.h
index 210bcd6a..47bb8bbb 100644
--- a/sim_video.h
+++ b/sim_video.h
@@ -183,6 +183,7 @@ t_stat vid_register_quit_callback (VID_QUIT_CALLBACK callback);
t_stat vid_close (void);
t_stat vid_poll_kb (SIM_KEY_EVENT *ev);
t_stat vid_poll_mouse (SIM_MOUSE_EVENT *ev);
+uint32 vid_map_rgb (uint8 r, uint8 g, uint8 b);
void vid_draw (int32 x, int32 y, int32 w, int32 h, uint32 *buf);
void vid_beep (void);
void vid_refresh (void);
@@ -196,7 +197,6 @@ t_stat vid_show (FILE* st, DEVICE *dptr, UNIT* uptr, int32 val, CONST char* des
t_stat vid_screenshot (const char *filename);
extern t_bool vid_active;
-extern uint32 vid_mono_palette[2];
void vid_set_cursor_position (int32 x, int32 y); /* cursor position (set by calling code) */
/* A device simulator can optionally set the vid_display_kb_event_process