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AltairZ80: Correct spelling, formatting and years

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This commit is contained in:
Peter Schorn 2023-06-30 14:31:06 +02:00
parent 09f67aa06c
commit 4c1aee0887
42 changed files with 286 additions and 288 deletions
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6
AltairZ80/altairz80_cpu.c
View file

@ -1,6 +1,6 @@
/* altairz80_cpu.c: MITS Altair CPU (8080 and Z80) /* altairz80_cpu.c: MITS Altair CPU (8080 and Z80)
Copyright (c) 2002-2014, Peter Schorn Copyright (c) 2002-2023, Peter Schorn
Permission is hereby granted, free of charge, to any person obtaining a Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"), copy of this software and associated documentation files (the "Software"),
@ -451,7 +451,7 @@ REG cpu_reg[] = {
}, /* 65 M68K, PREF_ADDR */ }, /* 65 M68K, PREF_ADDR */
{ HRDATAD (M68K_PREF_DATA, m68k_registers[M68K_REG_PREF_DATA], 32, "M68K Last Prefetch Data register"), { HRDATAD (M68K_PREF_DATA, m68k_registers[M68K_REG_PREF_DATA], 32, "M68K Last Prefetch Data register"),
}, /* 66 M68K, PREF_DATA */ }, /* 66 M68K, PREF_DATA */
{ HRDATAD (M68K_PPC, m68k_registers[M68K_REG_PPC], 32, "M68K Previous Proram Counter register"), { HRDATAD (M68K_PPC, m68k_registers[M68K_REG_PPC], 32, "M68K Previous Program Counter register"),
}, /* 67 M68K, PPC */ }, /* 67 M68K, PPC */
{ HRDATAD (M68K_IR, m68k_registers[M68K_REG_IR], 32, "M68K Instruction Register"), { HRDATAD (M68K_IR, m68k_registers[M68K_REG_IR], 32, "M68K Instruction Register"),
}, /* 68 M68K, IR */ }, /* 68 M68K, IR */
@ -6384,7 +6384,7 @@ static t_stat sim_instr_mmu (void) {
/* /*
* This sequence of instructions is a mix that mimics * This sequence of instructions is a mix that mimics
* a resonable instruction set that is a close estimate * a reasonable instruction set that is a close estimate
* to the calibrated result. * to the calibrated result.
*/ */

2
AltairZ80/altairz80_cpu_nommu.c
View file

@ -1,6 +1,6 @@
/* altairz80_cpu_opt.c: MITS Altair CPU (8080 and Z80) /* altairz80_cpu_opt.c: MITS Altair CPU (8080 and Z80)
Copyright (c) 2002-2014, Peter Schorn Copyright (c) 2002-2023, Peter Schorn
Permission is hereby granted, free of charge, to any person obtaining a Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"), copy of this software and associated documentation files (the "Software"),

2
AltairZ80/altairz80_defs.h
View file

@ -1,6 +1,6 @@
/* altairz80_defs.h: MITS Altair simulator definitions /* altairz80_defs.h: MITS Altair simulator definitions
Copyright (c) 2002-2014, Peter Schorn Copyright (c) 2002-2023, Peter Schorn
Permission is hereby granted, free of charge, to any person obtaining a Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"), copy of this software and associated documentation files (the "Software"),

2
AltairZ80/altairz80_dsk.c
View file

@ -1,6 +1,6 @@
/* altairz80_dsk.c: MITS Altair 88-DISK Simulator /* altairz80_dsk.c: MITS Altair 88-DISK Simulator
Copyright (c) 2002-2014, Peter Schorn Copyright (c) 2002-2023, Peter Schorn
Permission is hereby granted, free of charge, to any person obtaining a Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"), copy of this software and associated documentation files (the "Software"),

6
AltairZ80/altairz80_hdsk.c
View file

@ -1,6 +1,6 @@
/* altairz80_hdsk.c: simulated hard disk device to increase capacity /* altairz80_hdsk.c: simulated hard disk device to increase capacity
Copyright (c) 2002-2014, Peter Schorn Copyright (c) 2002-2023, Peter Schorn
Permission is hereby granted, free of charge, to any person obtaining a Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"), copy of this software and associated documentation files (the "Software"),
@ -419,7 +419,7 @@ static DISK_INFO* hdsk_imd[HDSK_NUMBER];
static REG hdsk_reg[] = { static REG hdsk_reg[] = {
{ DRDATAD (HDCMD, hdskLastCommand, 32, "Last command"), { DRDATAD (HDCMD, hdskLastCommand, 32, "Last command"),
REG_RO }, REG_RO },
{ DRDATAD (HDPOS, hdskCommandPosition, 32, "Commmand position"), { DRDATAD (HDPOS, hdskCommandPosition, 32, "Command position"),
REG_RO }, REG_RO },
{ DRDATAD (HDDSK, selectedDisk, 32, "Selected disk"), { DRDATAD (HDDSK, selectedDisk, 32, "Selected disk"),
REG_RO }, REG_RO },
@ -605,7 +605,7 @@ static t_stat hdsk_attach(UNIT *uptr, CONST char *cptr) {
} }
ASSURE((uptr -> HDSK_SECTORS_PER_TRACK) && (uptr -> HDSK_SECTOR_SIZE) && (uptr -> HDSK_FORMAT_TYPE >= 0)); ASSURE((uptr -> HDSK_SECTORS_PER_TRACK) && (uptr -> HDSK_SECTOR_SIZE) && (uptr -> HDSK_FORMAT_TYPE >= 0));
/* Step 4: Number of tracks is smallest number to accomodate capacity */ /* Step 4: Number of tracks is smallest number to accommodate capacity */
uptr -> HDSK_NUMBER_OF_TRACKS = (uptr -> capac + uptr -> HDSK_SECTORS_PER_TRACK * uptr -> HDSK_NUMBER_OF_TRACKS = (uptr -> capac + uptr -> HDSK_SECTORS_PER_TRACK *
uptr -> HDSK_SECTOR_SIZE - 1) / (uptr -> HDSK_SECTORS_PER_TRACK * uptr -> HDSK_SECTOR_SIZE); uptr -> HDSK_SECTOR_SIZE - 1) / (uptr -> HDSK_SECTORS_PER_TRACK * uptr -> HDSK_SECTOR_SIZE);
ASSURE( ( (t_addr) ((uptr -> HDSK_NUMBER_OF_TRACKS - 1) * uptr -> HDSK_SECTORS_PER_TRACK * ASSURE( ( (t_addr) ((uptr -> HDSK_NUMBER_OF_TRACKS - 1) * uptr -> HDSK_SECTORS_PER_TRACK *

2
AltairZ80/altairz80_mhdsk.c
View file

@ -1,6 +1,6 @@
/* altairz80_mhdsk.c: MITS 88-HDSK Hard Disk simulator /* altairz80_mhdsk.c: MITS 88-HDSK Hard Disk simulator
Copyright (c) 2002-2014, Peter Schorn Copyright (c) 2002-2023, Peter Schorn
Permission is hereby granted, free of charge, to any person obtaining a Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"), copy of this software and associated documentation files (the "Software"),

2
AltairZ80/altairz80_net.c
View file

@ -1,6 +1,6 @@
/* altairz80_net.c: networking capability /* altairz80_net.c: networking capability
Copyright (c) 2002-2014, Peter Schorn Copyright (c) 2002-2023, Peter Schorn
Permission is hereby granted, free of charge, to any person obtaining a Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"), copy of this software and associated documentation files (the "Software"),

2
AltairZ80/altairz80_sio.c
View file

@ -1,6 +1,6 @@
/* altairz80_sio.c: MITS Altair serial I/O card /* altairz80_sio.c: MITS Altair serial I/O card
Copyright (c) 2002-2014, Peter Schorn Copyright (c) 2002-2023, Peter Schorn
Permission is hereby granted, free of charge, to any person obtaining a Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"), copy of this software and associated documentation files (the "Software"),

2
AltairZ80/altairz80_sys.c
View file

@ -1,6 +1,6 @@
/* altairz80_sys.c: MITS Altair system interface /* altairz80_sys.c: MITS Altair system interface
Copyright (c) 2002-2014, Peter Schorn Copyright (c) 2002-2023, Peter Schorn
Permission is hereby granted, free of charge, to any person obtaining a Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"), copy of this software and associated documentation files (the "Software"),

2
AltairZ80/i86.h
View file

@ -196,7 +196,7 @@ struct pc_env
struct i386_general_regs Gn_regs; struct i386_general_regs Gn_regs;
struct i386_special_regs Sp_regs; struct i386_special_regs Sp_regs;
struct i386_segment_regs Sg_regs; struct i386_segment_regs Sg_regs;
/* our flags structrure. This contains information on /* our flags structure. This contains information on
REPE prefix 2 bits repe,repne REPE prefix 2 bits repe,repne
SEGMENT overrides 5 bits normal,DS,SS,CS,ES SEGMENT overrides 5 bits normal,DS,SS,CS,ES
Delayed flag set 3 bits (zero, signed, parity) Delayed flag set 3 bits (zero, signed, parity)

6
AltairZ80/i86_decode.c
View file

@ -77,7 +77,7 @@ void cpu8086_intr(uint8 intrnum);
/* this file includes subroutines which do: /* this file includes subroutines which do:
stuff involving decoding instruction formats. stuff involving decoding instruction formats.
stuff involving accessess of immediate data via IP. stuff involving accesses of immediate data via IP.
etc. etc.
*/ */
@ -675,7 +675,7 @@ uint8 fetch_data_byte(PC_ENV *m, uint16 offset)
refer to addresses relative to the SS. So, at the minimum, refer to addresses relative to the SS. So, at the minimum,
all decodings of addressing modes would have to set/clear all decodings of addressing modes would have to set/clear
a bit describing whether the access is relative to DS or SS. a bit describing whether the access is relative to DS or SS.
That is the function of the cpu-state-varible m->sysmode. That is the function of the cpu-state-variable m->sysmode.
There are several potential states: There are several potential states:
repe prefix seen (handled elsewhere) repe prefix seen (handled elsewhere)
repne prefix seen (ditto) repne prefix seen (ditto)
@ -683,7 +683,7 @@ uint8 fetch_data_byte(PC_ENV *m, uint16 offset)
ds segment override ds segment override
es segment override es segment override
ss segment override ss segment override
ds/ss select (in absense of override) ds/ss select (in absence of override)
Each of the above 7 items are handled with a bit in the sysmode Each of the above 7 items are handled with a bit in the sysmode
field. field.
The latter 5 can be implemented as a simple state machine: The latter 5 can be implemented as a simple state machine:

14
AltairZ80/i86_ops.c
View file

@ -78,7 +78,7 @@ extern uint32 in(const uint32 Port);
to the 256 byte-"opcodes" found on the 8086. The table which to the 256 byte-"opcodes" found on the 8086. The table which
dispatches this is found in the files optab.[ch]. dispatches this is found in the files optab.[ch].
Each opcode proc has a comment preceeding it which gives it's table Each opcode proc has a comment preceding it which gives it's table
address. Several opcodes are missing (undefined) in the table. address. Several opcodes are missing (undefined) in the table.
Each proc includes information for decoding (DECODE_PRINTF and Each proc includes information for decoding (DECODE_PRINTF and
@ -3100,7 +3100,7 @@ static void i86op_movs_byte(PC_ENV *m)
inc = 1; inc = 1;
if (m->sysmode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) if (m->sysmode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE))
{ {
/* dont care whether REPE or REPNE */ /* don't care whether REPE or REPNE */
/* move them until CX is ZERO. */ /* move them until CX is ZERO. */
while (m->R_CX != 0) while (m->R_CX != 0)
{ {
@ -3133,7 +3133,7 @@ static void i86op_movs_word(PC_ENV *m)
inc = 2; inc = 2;
if (m->sysmode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) if (m->sysmode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE))
{ {
/* dont care whether REPE or REPNE */ /* don't care whether REPE or REPNE */
/* move them until CX is ZERO. */ /* move them until CX is ZERO. */
while (m->R_CX != 0) while (m->R_CX != 0)
{ {
@ -3291,7 +3291,7 @@ static void i86op_stos_byte(PC_ENV *m)
inc = 1; inc = 1;
if (m->sysmode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) if (m->sysmode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE))
{ {
/* dont care whether REPE or REPNE */ /* don't care whether REPE or REPNE */
/* move them until CX is ZERO. */ /* move them until CX is ZERO. */
while (m->R_CX != 0) while (m->R_CX != 0)
{ {
@ -3319,7 +3319,7 @@ static void i86op_stos_word(PC_ENV *m)
inc = 2; inc = 2;
if (m->sysmode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) if (m->sysmode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE))
{ {
/* dont care whether REPE or REPNE */ /* don't care whether REPE or REPNE */
/* move them until CX is ZERO. */ /* move them until CX is ZERO. */
while (m->R_CX != 0) while (m->R_CX != 0)
{ {
@ -3347,7 +3347,7 @@ static void i86op_lods_byte(PC_ENV *m)
inc = 1; inc = 1;
if (m->sysmode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) if (m->sysmode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE))
{ {
/* dont care whether REPE or REPNE */ /* don't care whether REPE or REPNE */
/* move them until CX is ZERO. */ /* move them until CX is ZERO. */
while (m->R_CX != 0) while (m->R_CX != 0)
{ {
@ -3375,7 +3375,7 @@ static void i86op_lods_word(PC_ENV *m)
inc = 2; inc = 2;
if (m->sysmode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) if (m->sysmode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE))
{ {
/* dont care whether REPE or REPNE */ /* don't care whether REPE or REPNE */
/* move them until CX is ZERO. */ /* move them until CX is ZERO. */
while (m->R_CX != 0) while (m->R_CX != 0)
{ {

10
AltairZ80/i86_prim_ops.c
View file

@ -498,7 +498,7 @@ uint8 neg_byte(PC_ENV *m, uint8 s)
CONDITIONAL_SET_FLAG(res & 0x80, m, F_SF); CONDITIONAL_SET_FLAG(res & 0x80, m, F_SF);
CONDITIONAL_SET_FLAG(parity_tab[res], m, F_PF); CONDITIONAL_SET_FLAG(parity_tab[res], m, F_PF);
/* calculate the borrow chain --- modified such that d=0. /* calculate the borrow chain --- modified such that d=0.
substitutiing d=0 into bc= res&(~d|s)|(~d&s); substituting d=0 into bc= res&(~d|s)|(~d&s);
(the one used for sub) and simplifying, since ~d=0xff..., (the one used for sub) and simplifying, since ~d=0xff...,
~d|s == 0xffff..., and res&0xfff... == res. Similarly ~d|s == 0xffff..., and res&0xfff... == res. Similarly
~d&s == s. So the simplified result is:*/ ~d&s == s. So the simplified result is:*/
@ -518,7 +518,7 @@ uint16 neg_word(PC_ENV *m, uint16 s)
CONDITIONAL_SET_FLAG(res & 0x8000, m, F_SF); CONDITIONAL_SET_FLAG(res & 0x8000, m, F_SF);
CONDITIONAL_SET_FLAG(parity_tab[res&0xff], m, F_PF); CONDITIONAL_SET_FLAG(parity_tab[res&0xff], m, F_PF);
/* calculate the borrow chain --- modified such that d=0. /* calculate the borrow chain --- modified such that d=0.
substitutiing d=0 into bc= res&(~d|s)|(~d&s); substituting d=0 into bc= res&(~d|s)|(~d&s);
(the one used for sub) and simplifying, since ~d=0xff..., (the one used for sub) and simplifying, since ~d=0xff...,
~d|s == 0xffff..., and res&0xfff... == res. Similarly ~d|s == 0xffff..., and res&0xfff... == res. Similarly
~d&s == s. So the simplified result is:*/ ~d&s == s. So the simplified result is:*/
@ -793,7 +793,7 @@ uint16 rcr_word(PC_ENV *m, uint16 d, uint16 s)
if (cnt==1) if (cnt==1)
{ {
cf = d & 0x1; cf = d & 0x1;
/* see note above on teh byte version */ /* see note above on the byte version */
ocf = ACCESS_FLAG(m,F_CF) != 0; ocf = ACCESS_FLAG(m,F_CF) != 0;
} }
else else
@ -1310,7 +1310,7 @@ void test_byte(PC_ENV *m, uint8 d, uint8 s)
CONDITIONAL_SET_FLAG(res&0x80, m, F_SF); CONDITIONAL_SET_FLAG(res&0x80, m, F_SF);
CONDITIONAL_SET_FLAG(res==0, m, F_ZF); CONDITIONAL_SET_FLAG(res==0, m, F_ZF);
CONDITIONAL_SET_FLAG(parity_tab[res&0xff], m, F_PF); CONDITIONAL_SET_FLAG(parity_tab[res&0xff], m, F_PF);
/* AF == dont care*/ /* AF == don't care*/
CLEAR_FLAG(m, F_CF); CLEAR_FLAG(m, F_CF);
} }
@ -1322,7 +1322,7 @@ void test_word(PC_ENV *m, uint16 d, uint16 s)
CONDITIONAL_SET_FLAG(res&0x8000, m, F_SF); CONDITIONAL_SET_FLAG(res&0x8000, m, F_SF);
CONDITIONAL_SET_FLAG(res==0, m, F_ZF); CONDITIONAL_SET_FLAG(res==0, m, F_ZF);
CONDITIONAL_SET_FLAG(parity_tab[res&0xff], m, F_PF); CONDITIONAL_SET_FLAG(parity_tab[res&0xff], m, F_PF);
/* AF == dont care*/ /* AF == don't care*/
CLEAR_FLAG(m, F_CF); CLEAR_FLAG(m, F_CF);
} }

10
AltairZ80/ibc.c
View file

@ -142,10 +142,10 @@ static const char* ibc_description(DEVICE *dptr);
/* IBC Middi Cadet I/O Ports */ /* IBC Middi Cadet I/O Ports */
#define IBC_SIO 0x04 /* 0x04-0x13: UARTs (using AltairZ80 SIO.) UARTS 0x00-0x03 are using 2sio. */ #define IBC_SIO 0x04 /* 0x04-0x13: UARTs (using AltairZ80 SIO.) UARTS 0x00-0x03 are using 2sio. */
#define IBC_FDC_DATA 0x28 /* FDC Data Regster */ #define IBC_FDC_DATA 0x28 /* FDC Data Register */
#define IBC_PARAM 0x2a /* FDC PARAM register */ #define IBC_PARAM 0x2a /* FDC PARAM Register */
#define IBC_DIPSWE 0x3c /* CPU Board DIP Switch E */ #define IBC_DIPSWE 0x3c /* CPU Board DIP Switch E */
#define IBC_BANKSEL 0x38 /* Bank Select register */ #define IBC_BANKSEL 0x38 /* Bank Select Register */
#define IBC_FIFO_CTRL 0x3e /* FDC FIFO Control */ #define IBC_FIFO_CTRL 0x3e /* FDC FIFO Control */
#define IBC_ROM_CTRL 0x3f /* ROM Control Register */ #define IBC_ROM_CTRL 0x3f /* ROM Control Register */
#define IBC_SCC_BANKSEL 0x58 /* Bank Select register */ #define IBC_SCC_BANKSEL 0x58 /* Bank Select register */
@ -252,7 +252,7 @@ static DEBTAB ibc_dt[] = {
{ "SBD", SBD_MSG, "System Board messages" }, { "SBD", SBD_MSG, "System Board messages" },
{ "UART", UART_MSG, "UART messages" }, { "UART", UART_MSG, "UART messages" },
{ "CACHE", CACHE_MSG, "CACHE messages" }, { "CACHE", CACHE_MSG, "CACHE messages" },
{ "UIO", UNHANDLED_IO_MSG, "Unsuported I/O Ports" }, { "UIO", UNHANDLED_IO_MSG, "Unsupported I/O Ports" },
{ "FIFO", FIFO_MSG, "FDC FIFO messages" }, { "FIFO", FIFO_MSG, "FDC FIFO messages" },
{ "DIPSW", DIPSW_MSG, "DIP Switch messages" }, { "DIPSW", DIPSW_MSG, "DIP Switch messages" },
{ NULL, 0, NULL } { NULL, 0, NULL }
@ -1817,7 +1817,7 @@ static int32 ibc_banksel(const int32 port, const int32 io, const int32 data)
* 0xff: Boot from floppy (All off.) * 0xff: Boot from floppy (All off.)
* Switch 1 - 0xfe: Boot into ROM monitor (Switch 1 on.) * Switch 1 - 0xfe: Boot into ROM monitor (Switch 1 on.)
* Switch 2 - 0xfd: Boot from hard disk (Switch 2 on.) * Switch 2 - 0xfd: Boot from hard disk (Switch 2 on.)
* Switch 7 - 0xbe: OFF = Use FDC Interupts, ON = Poll FDC instead. * Switch 7 - 0xbe: OFF = Use FDC Interrupts, ON = Poll FDC instead.
*/ */
result = ibc_info->dipsw_E; result = ibc_info->dipsw_E;

2
AltairZ80/ibc_mcc_hdc.c
View file

@ -240,7 +240,7 @@ static t_stat ibc_hdc_attach(UNIT *uptr, CONST char *cptr)
/* Defaults for the Quantum 2020 Drive */ /* Defaults for the Quantum 2020 Drive */
pDrive->ready = 0; pDrive->ready = 0;
if (pDrive->ncyls == 0) { if (pDrive->ncyls == 0) {
/* If geometry was not specified, default to Quantun 2020 */ /* If geometry was not specified, default to Quantum 2020 */
pDrive->ncyls = 512; pDrive->ncyls = 512;
pDrive->nheads = 4; pDrive->nheads = 4;
pDrive->nsectors = 32; pDrive->nsectors = 32;

2
AltairZ80/ibc_smd_hdc.c
View file

@ -232,7 +232,7 @@ static t_stat ibc_smd_attach(UNIT *uptr, CONST char *cptr)
/* Defaults for the Quantum 2020 Drive */ /* Defaults for the Quantum 2020 Drive */
pDrive->ready = 0; pDrive->ready = 0;
if (pDrive->ncyls == 0) { if (pDrive->ncyls == 0) {
/* If geometry was not specified, default to Quantun 2020 */ /* If geometry was not specified, default to Quantum 2020 */
pDrive->ncyls = 512; pDrive->ncyls = 512;
pDrive->nheads = 4; pDrive->nheads = 4;
pDrive->nsectors = 16; pDrive->nsectors = 16;

2
AltairZ80/m68k/m68k.h
View file

@ -379,7 +379,7 @@ void m68k_set_reg(m68k_register_t reg, unsigned int value);
/* Check if an instruction is valid for the specified CPU type */ /* Check if an instruction is valid for the specified CPU type */
unsigned int m68k_is_valid_instruction(unsigned int instruction, unsigned int cpu_type); unsigned int m68k_is_valid_instruction(unsigned int instruction, unsigned int cpu_type);
/* Disassemble 1 instruction using the epecified CPU type at pc. Stores /* Disassemble 1 instruction using the specified CPU type at pc. Stores
* disassembly in str_buff and returns the size of the instruction in bytes. * disassembly in str_buff and returns the size of the instruction in bytes.
*/ */
unsigned int m68k_disassemble(char* str_buff, unsigned int pc, unsigned int cpu_type); unsigned int m68k_disassemble(char* str_buff, unsigned int pc, unsigned int cpu_type);

4
AltairZ80/m68k/m68kconf.h
View file

@ -140,7 +140,7 @@
* the exception occurs normally. * the exception occurs normally.
* The callback looks like int callback(int opcode) * The callback looks like int callback(int opcode)
* You should put OPT_SPECIFY_HANDLER here if you cant to use it, otherwise it will * You should put OPT_SPECIFY_HANDLER here if you cant to use it, otherwise it will
* use a dummy default handler and you'll have to call m68k_set_illg_instr_callback explicitely * use a dummy default handler and you'll have to call m68k_set_illg_instr_callback explicitly
*/ */
#define M68K_ILLG_HAS_CALLBACK OPT_OFF #define M68K_ILLG_HAS_CALLBACK OPT_OFF
#define M68K_ILLG_CALLBACK(opcode) op_illg(opcode) #define M68K_ILLG_CALLBACK(opcode) op_illg(opcode)
@ -199,7 +199,7 @@
*/ */
/* If ON, the enulation core will use 64-bit integers to speed up some /* If ON, the emulation core will use 64-bit integers to speed up some
* operations. * operations.
*/ */
#define M68K_USE_64_BIT OPT_ON #define M68K_USE_64_BIT OPT_ON

4
AltairZ80/m68k/m68kcpu.c
View file

@ -973,7 +973,7 @@ int m68k_execute(int num_cycles)
do do
{ {
int i; int i;
/* Set tracing accodring to T1. (T0 is done inside instruction) */ /* Set tracing according to T1. (T0 is done inside instruction) */
m68ki_trace_t1(); /* auto-disable (see m68kcpu.h) */ m68ki_trace_t1(); /* auto-disable (see m68kcpu.h) */
/* Set the address space for reads */ /* Set the address space for reads */
@ -1037,7 +1037,7 @@ void m68k_end_timeslice(void)
/* ASG: rewrote so that the int_level is a mask of the IPL0/IPL1/IPL2 bits */ /* ASG: rewrote so that the int_level is a mask of the IPL0/IPL1/IPL2 bits */
/* KS: Modified so that IPL* bits match with mask positions in the SR /* KS: Modified so that IPL* bits match with mask positions in the SR
* and cleaned out remenants of the interrupt controller. * and cleaned out remnants of the interrupt controller.
*/ */
void m68k_set_irq(unsigned int int_level) void m68k_set_irq(unsigned int int_level)
{ {

6
AltairZ80/m68k/m68kcpu.h
View file

@ -398,7 +398,7 @@ typedef uint32 uint64;
/* ----------------------------- Configuration ---------------------------- */ /* ----------------------------- Configuration ---------------------------- */
/* These defines are dependant on the configuration defines in m68kconf.h */ /* These defines are dependent on the configuration defines in m68kconf.h */
/* Disable certain comparisons if we're not using all CPU types */ /* Disable certain comparisons if we're not using all CPU types */
#if M68K_EMULATE_040 #if M68K_EMULATE_040
@ -2015,7 +2015,7 @@ static inline void m68ki_exception_illegal(void)
USE_CYCLES(CYC_EXCEPTION[EXCEPTION_ILLEGAL_INSTRUCTION_M68K] - CYC_INSTRUCTION[REG_IR]); USE_CYCLES(CYC_EXCEPTION[EXCEPTION_ILLEGAL_INSTRUCTION_M68K] - CYC_INSTRUCTION[REG_IR]);
} }
/* Exception for format errror in RTE */ /* Exception for format error in RTE */
static inline void m68ki_exception_format_error(void) static inline void m68ki_exception_format_error(void)
{ {
uint sr = m68ki_init_exception(); uint sr = m68ki_init_exception();
@ -2052,7 +2052,7 @@ static inline void m68ki_exception_address_error(void)
/* Use up some clock cycles. Note that we don't need to undo the /* Use up some clock cycles. Note that we don't need to undo the
instruction's cycles here as we've longjmp:ed directly from the instruction's cycles here as we've longjmp:ed directly from the
instruction handler without passing the part of the excecute loop instruction handler without passing the part of the execute loop
that deducts instruction cycles */ that deducts instruction cycles */
USE_CYCLES(CYC_EXCEPTION[EXCEPTION_ADDRESS_ERROR]); USE_CYCLES(CYC_EXCEPTION[EXCEPTION_ADDRESS_ERROR]);
} }

4
AltairZ80/m68k/m68kdasm.c
View file

@ -156,7 +156,7 @@ uint read_imm_8(void);
uint read_imm_16(void); uint read_imm_16(void);
uint read_imm_32(void); uint read_imm_32(void);
/* Read data at the PC but don't imcrement the PC */ /* Read data at the PC but don't increment the PC */
uint peek_imm_8(void); uint peek_imm_8(void);
uint peek_imm_16(void); uint peek_imm_16(void);
uint peek_imm_32(void); uint peek_imm_32(void);
@ -3721,7 +3721,7 @@ static void build_opcode_table(void)
/* ================================= API ================================== */ /* ================================= API ================================== */
/* ======================================================================== */ /* ======================================================================== */
/* Disasemble one instruction at pc and store in str_buff */ /* Disassemble one instruction at pc and store in str_buff */
unsigned int m68k_disassemble(char* str_buff, unsigned int pc, unsigned int cpu_type) unsigned int m68k_disassemble(char* str_buff, unsigned int pc, unsigned int cpu_type)
{ {
if(!g_initialized) if(!g_initialized)

8
AltairZ80/m68ksim.c
View file

@ -1,6 +1,6 @@
/* m68kcpmsim.c: CP/M for Motorola 68000 definitions /* m68kcpmsim.c: CP/M for Motorola 68000 definitions
Copyright (c) 2014, Peter Schorn Copyright (c) 2014 - 2023, Peter Schorn
Permission is hereby granted, free of charge, to any person obtaining a Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"), copy of this software and associated documentation files (the "Software"),
@ -48,7 +48,7 @@
sector number to the sector register. This write triggers the requested sector number to the sector register. This write triggers the requested
operation. The status of the operation can be determined by reading the operation. The status of the operation can be determined by reading the
status register. status register.
A zero indicates that no error occured. A zero indicates that no error occurred.
Note that these operations invoke read() and write() system calls directly Note that these operations invoke read() and write() system calls directly
so that they will alter the image on the hard disk. KEEP BACKUPS! so that they will alter the image on the hard disk. KEEP BACKUPS!
@ -98,7 +98,7 @@
/* Memory-mapped IO ports */ /* Memory-mapped IO ports */
/* 6850 serial port like thing. Implements a reduced set of functionallity. */ /* 6850 serial port like thing. Implements a reduced set of functionality. */
#define MC6850_STAT 0xff1000L // command/status register #define MC6850_STAT 0xff1000L // command/status register
#define MC6850_DATA 0xff1002L // receive/transmit data register #define MC6850_DATA 0xff1002L // receive/transmit data register
@ -335,7 +335,7 @@ static int MC6850_device_ack(void) {
static void MC6850_data_write(uint32 value) { static void MC6850_data_write(uint32 value) {
sim_putchar(value); sim_putchar(value);
if ((m68k_MC6850_control & 0x60) == 0x20) { // transmit interupt enabled? if ((m68k_MC6850_control & 0x60) == 0x20) { // transmit interrupt enabled?
int_controller_clear(IRQ_MC6850); int_controller_clear(IRQ_MC6850);
int_controller_set(IRQ_MC6850); int_controller_set(IRQ_MC6850);
} }

2
AltairZ80/m68ksim.h
View file

@ -1,6 +1,6 @@
/* m68kcpmsim.h: CP/M for Motorola 68000 definitions /* m68kcpmsim.h: CP/M for Motorola 68000 definitions
Copyright (c) 2014, Peter Schorn Copyright (c) 2014 - 2023, Peter Schorn
Permission is hereby granted, free of charge, to any person obtaining a Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"), copy of this software and associated documentation files (the "Software"),

2
AltairZ80/nasm.h
View file

@ -11,8 +11,6 @@
#ifndef NASM_NASM_H #ifndef NASM_NASM_H
#define NASM_NASM_H #define NASM_NASM_H
#include <stdio.h>
#ifndef NULL #ifndef NULL
#define NULL 0 #define NULL 0
#endif #endif

10
AltairZ80/s100_2sio.c
View file

@ -65,7 +65,7 @@
We get many calls on how to interface terminals to the 2SIO. The We get many calls on how to interface terminals to the 2SIO. The
problem is that the Asynchronous Communications Interface Adapter's problem is that the Asynchronous Communications Interface Adapter's
(ACIA) handshaking signals make interfacing with the 2SIO a (ACIA) handshaking signals make interfacing with the 2SIO a
somewhat complicated matter. An explaination of the signals and somewhat complicated matter. An explanation of the signals and
their function should make the job easier. The three handshaking their function should make the job easier. The three handshaking
signals--Data Carrier Detect (DCD), Request to Send (RTS) and signals--Data Carrier Detect (DCD), Request to Send (RTS) and
Clear to Send (CTS)--permit limited control of a modem or Clear to Send (CTS)--permit limited control of a modem or
@ -79,8 +79,8 @@
section is inhibited and no data can be received by the ACIA. section is inhibited and no data can be received by the ACIA.
Information from the two input signals, CTS and DCD, is present in Information from the two input signals, CTS and DCD, is present in
the ACIA status register. Bit 2 represents *DCD, and bit 3 repre- the ACIA status register. Bit 2 represents *DCD, and bit 3
sents *CTS. When bit 2 is high, DCD is inactive. When bit 3 is high, represents *CTS. When bit 2 is high, DCD is inactive. When bit 3 is high,
CTS is inactive. When bit 2 goes low, valid data is sent to the ACIA. CTS is inactive. When bit 2 goes low, valid data is sent to the ACIA.
When bit 3 goes low, data can be transmitted. When bit 3 goes low, data can be transmitted.
@ -395,7 +395,7 @@ static t_stat m2sio_reset(DEVICE *dptr, int32 (*routine)(const int32, const int3
c = getClockFrequency() / 5; c = getClockFrequency() / 5;
dptr->units[0].wait = (c && c < 1000) ? c : 1000; dptr->units[0].wait = (c && c < 1000) ? c : 1000;
/* Enable TMXR modem control passthru */ /* Enable TMXR modem control passthrough */
tmxr_set_modem_control_passthru(xptr->tmxr); tmxr_set_modem_control_passthru(xptr->tmxr);
/* Reset status registers */ /* Reset status registers */
@ -665,7 +665,7 @@ static t_stat m2sio_config_line(UNIT *uptr)
** to run irrelevant, old software, that use TMXR and ** to run irrelevant, old software, that use TMXR and
** rely on some semblance of timing (Remote CP/M, BYE, ** rely on some semblance of timing (Remote CP/M, BYE,
** RBBS, PCGET/PUT, Xmodem, MEX, Modem7, or most ** RBBS, PCGET/PUT, Xmodem, MEX, Modem7, or most
** other communications software), on contemprary ** other communications software), on contemporary
** hardware. ** hardware.
** **
** Serial ports are self-limiting and sockets will run ** Serial ports are self-limiting and sockets will run

2
AltairZ80/s100_64fdc.c
View file

@ -258,7 +258,7 @@ DEVICE cromfdc_dev = {
}; };
/* This is the CROMFDC RDOS-II ROM. /* This is the CROMFDC RDOS-II ROM.
* The CROMFDC has a single 8K ROM; however ths simulation includes * The CROMFDC has a single 8K ROM; however this simulation includes
* two different versions of RDOS: * two different versions of RDOS:
* RDOS 2.52 and RDOS 3.12 * RDOS 2.52 and RDOS 3.12
* RDOS 2.52 is the default, but RDOS 3.12 can be * RDOS 2.52 is the default, but RDOS 3.12 can be

2
AltairZ80/s100_adcs6.c
View file

@ -313,7 +313,7 @@ static uint8 adcs6_rom[2][ADCS6_ROM_SIZE] = {
* *
* MONITOR COMMANDS : * MONITOR COMMANDS :
* B = Load disk boot loader * B = Load disk boot loader
* C = Load disk boot loader from cartriage * C = Load disk boot loader from cartridge
* DSSSS,QQQQ = Dump memory in hex from S to Q * DSSSS,QQQQ = Dump memory in hex from S to Q
* FSSSS,QQQQ,BB = Fill memory from S to Q with B * FSSSS,QQQQ,BB = Fill memory from S to Q with B
* GAAAA = Go to address A * GAAAA = Go to address A

10
AltairZ80/s100_disk2.c
View file

@ -78,8 +78,8 @@ typedef struct {
uint8 sel_drive; /* Currently selected drive */ uint8 sel_drive; /* Currently selected drive */
uint8 head_sel; /* Head select (signals to drive itself) */ uint8 head_sel; /* Head select (signals to drive itself) */
uint8 head; /* Head set by write to the HEAD register */ uint8 head; /* Head set by write to the HEAD register */
uint8 cyl; /* Cyl that the current operation is targetting */ uint8 cyl; /* Cyl that the current operation is targeting */
uint8 sector; /* Sector the current READ/WRITE operation is targetting */ uint8 sector; /* Sector the current READ/WRITE operation is targeting */
uint8 hdr_sector; /* Current sector for WRITE_HEADER */ uint8 hdr_sector; /* Current sector for WRITE_HEADER */
uint8 ctl_attn; uint8 ctl_attn;
uint8 ctl_run; uint8 ctl_run;
@ -152,11 +152,11 @@ static REG disk2_reg[] = {
{ HRDATAD (SEL_DRIVE, disk2_info_data.sel_drive, 3, { HRDATAD (SEL_DRIVE, disk2_info_data.sel_drive, 3,
"Currently selected drive"), }, "Currently selected drive"), },
{ HRDATAD (CYL, disk2_info_data.cyl, 8, { HRDATAD (CYL, disk2_info_data.cyl, 8,
"Cylinder that the current operation is targetting"), }, "Cylinder that the current operation is targeting"), },
{ HRDATAD (HEAD, disk2_info_data.head, 8, { HRDATAD (HEAD, disk2_info_data.head, 8,
"Head that the current operation is targetting"), }, "Head that the current operation is targeting"), },
{ HRDATAD (SECTOR, disk2_info_data.sector, 8, { HRDATAD (SECTOR, disk2_info_data.sector, 8,
"Sector that the current operation is targetting"), }, "Sector that the current operation is targeting"), },
{ NULL } { NULL }
}; };

2
AltairZ80/s100_dj2d.c
View file

@ -973,7 +973,7 @@ static DEBTAB dj2d_dt[] = {
{ "WRITE", WR_DATA_MSG, "Write messages" }, { "WRITE", WR_DATA_MSG, "Write messages" },
{ "STATUS", STATUS_MSG, "Status messages" }, { "STATUS", STATUS_MSG, "Status messages" },
{ "RDDETAIL", RD_DATA_DETAIL_MSG, "Read detail messages" }, { "RDDETAIL", RD_DATA_DETAIL_MSG, "Read detail messages" },
{ "WRDETAIL", WR_DATA_DETAIL_MSG, "Write detail messags" }, { "WRDETAIL", WR_DATA_DETAIL_MSG, "Write detail messages" },
{ "VERBOSE", VERBOSE_MSG, "Verbose messages" }, { "VERBOSE", VERBOSE_MSG, "Verbose messages" },
{ "DEBUG", DEBUG_MSG, "Debug messages" }, { "DEBUG", DEBUG_MSG, "Debug messages" },
{ NULL, 0 } { NULL, 0 }

2
AltairZ80/s100_djhdc.c
View file

@ -529,7 +529,7 @@ static uint8 DJHDC_Write(const uint32 Addr, uint8 cData)
/* Point IOPB to new link */ /* Point IOPB to new link */
djhdc_info->link_addr = next_link; djhdc_info->link_addr = next_link;
/* Read remaineder of IOPB */ /* Read remainder of IOPB */
for(i = 0; i < DJHDC_IOPB_LEN-3; i++) { for(i = 0; i < DJHDC_IOPB_LEN-3; i++) {
djhdc_info->iopb[i] = GetByteDMA((djhdc_info->link_addr) + i); djhdc_info->iopb[i] = GetByteDMA((djhdc_info->link_addr) + i);
} }

2
AltairZ80/s100_fif.c
View file

@ -2,7 +2,7 @@
IMSAI FIF Disk Controller by Ernie Price IMSAI FIF Disk Controller by Ernie Price
Based on altairz80_dsk.c, Copyright (c) 2002-2014, Peter Schorn Based on altairz80_dsk.c, Copyright (c) 2002-2023, Peter Schorn
Plug-n-Play added by Howard M. Harte Plug-n-Play added by Howard M. Harte

6
AltairZ80/s100_hayes.c
View file

@ -27,7 +27,7 @@
This device emulates D.C. Hayes 80-103A and Micromodem 100 communications This device emulates D.C. Hayes 80-103A and Micromodem 100 communications
adapters. adapters.
To provide any useful funcationality, this device need to be attached to To provide any useful functionality, this device need to be attached to
a socket or serial port. Enter "HELP HAYES" at the "simh>" prompt for a socket or serial port. Enter "HELP HAYES" at the "simh>" prompt for
additional information. additional information.
*/ */
@ -243,7 +243,7 @@ static t_stat hayes_reset(DEVICE *dptr)
/* Set DEVICE for this UNIT */ /* Set DEVICE for this UNIT */
dptr->units[0].dptr = dptr; dptr->units[0].dptr = dptr;
/* Enable TMXR modem control passthru */ /* Enable TMXR modem control passthrough */
tmxr_set_modem_control_passthru(hayes_ctx.tmxr); tmxr_set_modem_control_passthru(hayes_ctx.tmxr);
/* Reset status registers */ /* Reset status registers */
@ -505,7 +505,7 @@ static t_stat hayes_config_line(UNIT *uptr)
** to run irrelevant, old software, that use TMXR and ** to run irrelevant, old software, that use TMXR and
** rely on some semblance of timing (Remote CP/M, BYE, ** rely on some semblance of timing (Remote CP/M, BYE,
** RBBS, PCGET/PUT, Xmodem, MEX, Modem7, or most ** RBBS, PCGET/PUT, Xmodem, MEX, Modem7, or most
** other communications software), on contemprary ** other communications software), on contemporary
** hardware. ** hardware.
** **
** Serial ports are self-limiting and sockets will run ** Serial ports are self-limiting and sockets will run

6
AltairZ80/s100_hdc1001.c
View file

@ -261,7 +261,7 @@ static t_stat hdc1001_attach(UNIT *uptr, CONST char *cptr)
/* Defaults for the Quantum 2020 Drive */ /* Defaults for the Quantum 2020 Drive */
pDrive->ready = 0; pDrive->ready = 0;
if (pDrive->ncyls == 0) { if (pDrive->ncyls == 0) {
/* If geometry was not specified, default to Quantun 2020 */ /* If geometry was not specified, default to Quantum 2020 */
pDrive->ncyls = 512; pDrive->ncyls = 512;
pDrive->nheads = 4; pDrive->nheads = 4;
pDrive->nsectors = 16; pDrive->nsectors = 16;
@ -448,7 +448,7 @@ static uint8 HDC1001_Write(const uint32 Addr, uint8 cData)
break; break;
case 2: case 2:
sim_debug(ERROR_MSG, &hdc1001_dev,DEV_NAME "%d: " ADDRESS_FORMAT sim_debug(ERROR_MSG, &hdc1001_dev,DEV_NAME "%d: " ADDRESS_FORMAT
" Invalid sector size specified in SDH registrer.\n", hdc1001_info->sel_drive, PCX); " Invalid sector size specified in SDH register.\n", hdc1001_info->sel_drive, PCX);
pDrive->cur_sectsize = 512; pDrive->cur_sectsize = 512;
break; break;
case 3: case 3:
@ -458,7 +458,7 @@ static uint8 HDC1001_Write(const uint32 Addr, uint8 cData)
if (pDrive->sectsize != pDrive->cur_sectsize) { if (pDrive->sectsize != pDrive->cur_sectsize) {
sim_debug(ERROR_MSG, &hdc1001_dev,DEV_NAME "%d: " ADDRESS_FORMAT sim_debug(ERROR_MSG, &hdc1001_dev,DEV_NAME "%d: " ADDRESS_FORMAT
" Sector size specified in SDH registrer (0x%x) does not match disk geometry (0x%x.)\n", " Sector size specified in SDH register (0x%x) does not match disk geometry (0x%x.)\n",
hdc1001_info->sel_drive, PCX, pDrive->cur_sectsize, pDrive->sectsize); hdc1001_info->sel_drive, PCX, pDrive->cur_sectsize, pDrive->sectsize);
} }
/* fall through */ /* fall through */

2
AltairZ80/s100_icom.c
View file

@ -655,7 +655,7 @@ static DEBTAB icom_dt[] = {
{ "WRITE", WR_DATA_MSG, "Write messages" }, { "WRITE", WR_DATA_MSG, "Write messages" },
{ "STATUS", STATUS_MSG, "Status messages" }, { "STATUS", STATUS_MSG, "Status messages" },
{ "RDDETAIL", RD_DATA_DETAIL_MSG, "Read detail messages" }, { "RDDETAIL", RD_DATA_DETAIL_MSG, "Read detail messages" },
{ "WRDETAIL", WR_DATA_DETAIL_MSG, "Write detail messags" }, { "WRDETAIL", WR_DATA_DETAIL_MSG, "Write detail messages" },
{ NULL, 0 } { NULL, 0 }
}; };

6
AltairZ80/s100_jadedd.c
View file

@ -31,7 +31,7 @@
and memory address space. and memory address space.
While the Double D is capable to loading many different operating systems, While the Double D is capable to loading many different operating systems,
this emulator is centered around Digital Reasearch's CP/M 2 operating this emulator is centered around Digital Research's CP/M 2 operating
system as it was released by Jade. system as it was released by Jade.
The process of booting CP/M with the DD is a bit more complicated than The process of booting CP/M with the DD is a bit more complicated than
@ -312,7 +312,7 @@ static uint8 jade_prom[JADE_PROM_SIZE] = {
#define CMD_MD0 0x01 /* Select DD bank 0 */ #define CMD_MD0 0x01 /* Select DD bank 0 */
#define CMD_MD1 0x03 /* Select DD bank 1 */ #define CMD_MD1 0x03 /* Select DD bank 1 */
#define CMD_SOT 0x00 /* Switch DD mem out of system */ #define CMD_SOT 0x00 /* Switch DD mem out of system */
#define CMD_INT 0x02 /* Isssue DD Z80A interrupt */ #define CMD_INT 0x02 /* Issue DD Z80A interrupt */
#define CMD_BGN 0x80 /* Reset Z80 and execute */ #define CMD_BGN 0x80 /* Reset Z80 and execute */
#define DC_LOG 0x00 /* Log on diskette */ #define DC_LOG 0x00 /* Log on diskette */
@ -494,7 +494,7 @@ static DEBTAB jade_dt[] = {
{ "WRITE", WR_DATA_MSG, "Write messages" }, { "WRITE", WR_DATA_MSG, "Write messages" },
{ "STATUS", STATUS_MSG, "Status messages" }, { "STATUS", STATUS_MSG, "Status messages" },
{ "RDDETAIL", RD_DATA_DETAIL_MSG, "Read detail messages" }, { "RDDETAIL", RD_DATA_DETAIL_MSG, "Read detail messages" },
{ "WRDETAIL", WR_DATA_DETAIL_MSG, "Write detail messags" }, { "WRDETAIL", WR_DATA_DETAIL_MSG, "Write detail messages" },
{ NULL, 0 } { NULL, 0 }
}; };

2
AltairZ80/s100_mdsa.c
View file

@ -190,7 +190,7 @@ static DEBTAB mdsa_dt[] = {
{ "WRITE", WR_DATA_MSG, "Write messages" }, { "WRITE", WR_DATA_MSG, "Write messages" },
{ "STATUS", STATUS_MSG, "Status messages" }, { "STATUS", STATUS_MSG, "Status messages" },
{ "RDDETAIL", RD_DATA_DETAIL_MSG, "Read detail messages" }, { "RDDETAIL", RD_DATA_DETAIL_MSG, "Read detail messages" },
{ "WRDETAIL", WR_DATA_DETAIL_MSG, "Write detail messags" }, { "WRDETAIL", WR_DATA_DETAIL_MSG, "Write detail messages" },
{ NULL, 0 } { NULL, 0 }
}; };

4
AltairZ80/s100_mdsad.c
View file

@ -111,7 +111,7 @@ typedef struct {
typedef struct { typedef struct {
uint8 dd; /* Controls density on write DD=1 for double density and DD=0 for single density. */ uint8 dd; /* Controls density on write DD=1 for double density and DD=0 for single density. */
uint8 ss; /* Specifies the side of a double-sided diskette. The bottom side (and only side of a single-sided diskette) is selected when SS=0. The second (top) side is selected when SS=1. */ uint8 ss; /* Specifies the side of a double-sided diskette. The bottom side (and only side of a single-sided diskette) is selected when SS=0. The second (top) side is selected when SS=1. */
uint8 dp; /* has shared use. During stepping operations, DP=O specifies a step out and DP=1 specifies a step in. During write operations, write procompensation is invoked if and only if DP=1. */ uint8 dp; /* has shared use. During stepping operations, DP=O specifies a step out and DP=1 specifies a step in. During write operations, write precompensation is invoked if and only if DP=1. */
uint8 st; /* controls the level of the head step signal to the disk drives. */ uint8 st; /* controls the level of the head step signal to the disk drives. */
uint8 pst; /* value of step signal (st) on previous order */ uint8 pst; /* value of step signal (st) on previous order */
uint8 ds; /* is the drive select field, encoded as follows: */ uint8 ds; /* is the drive select field, encoded as follows: */
@ -270,7 +270,7 @@ static DEBTAB mdsad_dt[] = {
{ "STATUS", STATUS_MSG, "Status messages" }, { "STATUS", STATUS_MSG, "Status messages" },
{ "ORDERS", ORDERS_MSG, "Orders messages" }, { "ORDERS", ORDERS_MSG, "Orders messages" },
{ "RDDETAIL", RD_DATA_DETAIL_MSG, "Read detail messages" }, { "RDDETAIL", RD_DATA_DETAIL_MSG, "Read detail messages" },
{ "WRDETAIL", WR_DATA_DETAIL_MSG, "Write detail messags" }, { "WRDETAIL", WR_DATA_DETAIL_MSG, "Write detail messages" },
{ NULL, 0 } { NULL, 0 }
}; };

6
AltairZ80/s100_pmmi.c
View file

@ -37,7 +37,7 @@
that most software written for the MM-103 should function in some useful that most software written for the MM-103 should function in some useful
fashion. fashion.
To provide any useful funcationality, this device need to be attached to To provide any useful functionality, this device need to be attached to
a socket or serial port. Enter "HELP PMMI" at the "simh>" prompt for a socket or serial port. Enter "HELP PMMI" at the "simh>" prompt for
additional information. additional information.
*/ */
@ -266,7 +266,7 @@ static t_stat pmmi_reset(DEVICE *dptr)
/* Set DEVICE for this UNIT */ /* Set DEVICE for this UNIT */
dptr->units[0].dptr = dptr; dptr->units[0].dptr = dptr;
/* Enable TMXR modem control passthru */ /* Enable TMXR modem control passthrough */
tmxr_set_modem_control_passthru(pmmi_ctx.tmxr); tmxr_set_modem_control_passthru(pmmi_ctx.tmxr);
/* Reset status registers */ /* Reset status registers */
@ -571,7 +571,7 @@ static t_stat pmmi_config_line(UNIT *uptr)
** to run irrelevant, old software, that use TMXR and ** to run irrelevant, old software, that use TMXR and
** rely on some semblance of timing (Remote CP/M, BYE, ** rely on some semblance of timing (Remote CP/M, BYE,
** RBBS, PCGET/PUT, Xmodem, MEX, Modem7, or most ** RBBS, PCGET/PUT, Xmodem, MEX, Modem7, or most
** other communications software), on contemprary ** other communications software), on contemporary
** hardware. ** hardware.
** **
** Serial ports are self-limiting and sockets will run ** Serial ports are self-limiting and sockets will run

4
AltairZ80/s100_scp300f.c
View file

@ -190,7 +190,7 @@ static REG scp300f_reg[] = {
{ HRDATAD(SPIC_OCW2, scp300f_pic[SLAVE_PIC].OCW2, 8, "Slave OCW2 register"), }, { HRDATAD(SPIC_OCW2, scp300f_pic[SLAVE_PIC].OCW2, 8, "Slave OCW2 register"), },
{ HRDATAD(SPIC_OCW3, scp300f_pic[SLAVE_PIC].OCW3, 8, "Slave OCW3 register"), }, { HRDATAD(SPIC_OCW3, scp300f_pic[SLAVE_PIC].OCW3, 8, "Slave OCW3 register"), },
{ HRDATAD(9513_HUND, data9513[0], 8, "9513 Hundreths"), }, { HRDATAD(9513_HUND, data9513[0], 8, "9513 Hundredths"), },
{ HRDATAD(9513_SS, data9513[1], 8, "9513 Seconds"), }, { HRDATAD(9513_SS, data9513[1], 8, "9513 Seconds"), },
{ HRDATAD(9513_MM, data9513[2], 8, "9513 Minutes"), }, { HRDATAD(9513_MM, data9513[2], 8, "9513 Minutes"), },
{ HRDATAD(9513_HH, data9513[3], 8, "9513 Hours"), }, { HRDATAD(9513_HH, data9513[3], 8, "9513 Hours"), },
@ -709,7 +709,7 @@ static uint8 SCP300F_Write(const uint32 Addr, uint8 cData)
switch(Addr & SCP300F_IO_MASK) { switch(Addr & SCP300F_IO_MASK) {
case SCP300F_SPIC_0: case SCP300F_SPIC_0:
sel_pic = SLAVE_PIC; /* intentional falltrough */ sel_pic = SLAVE_PIC; /* intentional fallthrough */
case SCP300F_MPIC_0: case SCP300F_MPIC_0:
if (cData & 0x10) { if (cData & 0x10) {
sim_debug(PIC_MSG, &scp300f_dev, "SCP300F: " ADDRESS_FORMAT sim_debug(PIC_MSG, &scp300f_dev, "SCP300F: " ADDRESS_FORMAT

2
AltairZ80/s100_ss1.c
View file

@ -483,7 +483,7 @@ static uint8 SS1_Write(const uint32 Addr, uint8 cData)
switch(Addr & 0x0F) { switch(Addr & 0x0F) {
case SS1_S8259_L: case SS1_S8259_L:
sel_pic = SLAVE_PIC; /* intentional falltrough */ sel_pic = SLAVE_PIC; /* intentional fallthrough */
case SS1_M8259_L: case SS1_M8259_L:
if(cData & 0x10) { if(cData & 0x10) {
sim_debug(PIC_MSG, &ss1_dev, "SS1: " ADDRESS_FORMAT sim_debug(PIC_MSG, &ss1_dev, "SS1: " ADDRESS_FORMAT

2
AltairZ80/s100_tarbell.c
View file

@ -332,7 +332,7 @@ static DEBTAB tarbell_dt[] = {
{ "WRITE", WR_DATA_MSG, "Write messages" }, { "WRITE", WR_DATA_MSG, "Write messages" },
{ "STATUS", STATUS_MSG, "Status messages" }, { "STATUS", STATUS_MSG, "Status messages" },
{ "RDDETAIL", RD_DATA_DETAIL_MSG, "Read detail messages" }, { "RDDETAIL", RD_DATA_DETAIL_MSG, "Read detail messages" },
{ "WRDETAIL", WR_DATA_DETAIL_MSG, "Write detail messags" }, { "WRDETAIL", WR_DATA_DETAIL_MSG, "Write detail messages" },
{ NULL, 0 } { NULL, 0 }
}; };

2
AltairZ80/wd179x.c
View file

@ -1091,7 +1091,7 @@ static uint8 Do1793Command(uint8 cCommand)
sdata.raw[wd179x_info->fdc_dataindex] = wd179x_info->fdc_data; sdata.raw[wd179x_info->fdc_dataindex] = wd179x_info->fdc_data;
if (wd179x_info->external_fifo_len) { if (wd179x_info->external_fifo_len) {
/* For external FIFO, write the sector immediately, as the sofware pre-fills a FIFO, which is then read out into the FDC using DRQ */ /* For external FIFO, write the sector immediately, as the software pre-fills a FIFO, which is then read out into the FDC using DRQ */
wd179x_info->fdc_status &= ~(WD179X_STAT_DRQ | WD179X_STAT_BUSY); /* Clear DRQ, BUSY */ wd179x_info->fdc_status &= ~(WD179X_STAT_DRQ | WD179X_STAT_BUSY); /* Clear DRQ, BUSY */
wd179x_info->drq = 0; wd179x_info->drq = 0;
wd179x_info->intrq = 1; wd179x_info->intrq = 1;