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VAX: Added support for the DEQNA device on Ultrix 1.x. Henry Bent observed that the deqna driver in this OS counted on older DEQNA firmware which automatically enabled interrupts after a software reset.

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CPU Idle detection for this OS is now supported and the combination of SET CPU IDLE=ULTRIX-1.X and explicitly using a DEQNA device (SET XQ TYPE=DEQNA) will enable the automatic enabling of device interrupt generation.
This commit is contained in:
Mark Pizzolato 2014-07-14 12:29:53 -07:00
parent a0a7eb27b6
commit 4d817f1deb
4 changed files with 21 additions and 7 deletions
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7
PDP11/pdp11_xq.c
View file

@ -2088,7 +2088,7 @@ void xqb_read_callback(int status)
void xq_sw_reset(CTLR* xq) void xq_sw_reset(CTLR* xq)
{ {
const uint16 set_bits = XQ_CSR_XL | XQ_CSR_RL; uint16 set_bits = XQ_CSR_XL | XQ_CSR_RL;
int i; int i;
sim_debug(DBG_TRC, xq->dev, "xq_sw_reset()\n"); sim_debug(DBG_TRC, xq->dev, "xq_sw_reset()\n");
@ -2100,6 +2100,11 @@ void xq_sw_reset(CTLR* xq)
xq->var->iba = xq->var->srr = 0; xq->var->iba = xq->var->srr = 0;
} }
/* Old DEQNA firmware also enabled interrupts and */
/* the Ultrix 1.X driver counts on that behavior */
if ((xq->var->type == XQ_T_DEQNA) && xq->dib->vec && (ULTRIX1X))
set_bits |= XQ_CSR_IE;
/* reset csr bits */ /* reset csr bits */
xq_csr_set_clr(xq, set_bits, (uint16) ~set_bits); xq_csr_set_clr(xq, set_bits, (uint16) ~set_bits);

4
PDP11/pdp11_xq.h
View file

@ -75,12 +75,14 @@
extern int32 PSL; /* PSL */ extern int32 PSL; /* PSL */
extern int32 fault_PC; /* fault PC */ extern int32 fault_PC; /* fault PC */
extern int32 int_req[IPL_HLVL]; extern int32 int_req[IPL_HLVL];
uint32 cpu_idle_mask; /* idle mask (OS type) */
#define ULTRIX1X (cpu_idle_mask&VAX_IDLE_ULT1X)
#else /* PDP-11 version */ #else /* PDP-11 version */
#include "pdp11_defs.h" #include "pdp11_defs.h"
#define XQ_RDX 8 #define XQ_RDX 8
#define XQ_WID 16 #define XQ_WID 16
extern int32 int_req[IPL_HLVL]; extern int32 int_req[IPL_HLVL];
#define ULTRIX1X 0
#endif #endif
#include "sim_ether.h" #include "sim_ether.h"

8
VAX/vax_cpu.c
View file

@ -2541,6 +2541,11 @@ for ( ;; ) {
temp = op_ffs (r, op1); /* find first 1 */ temp = op_ffs (r, op1); /* find first 1 */
WRITE_L (op0 + temp); /* store result */ WRITE_L (op0 + temp); /* store result */
cc = r? 0: CC_Z; /* set cc's */ cc = r? 0: CC_Z; /* set cc's */
if ((cc == CC_Z) && /* No set bits found? */
(cpu_idle_mask & VAX_IDLE_ULT1X) && /* running Ultrix 1.X" */
(PSL_GETIPL (PSL) == 0x0) && /* at IPL 0? */
(fault_PC & 0x80000000)) /* in system space? */
cpu_idle(); /* idle loop */
break; break;
case FFC: case FFC:
@ -3527,11 +3532,12 @@ static struct os_idle os_tab[] = {
{ "NETBSD", VAX_IDLE_BSDNEW }, { "NETBSD", VAX_IDLE_BSDNEW },
{ "ULTRIX", VAX_IDLE_ULT }, { "ULTRIX", VAX_IDLE_ULT },
{ "ULTRIXOLD", VAX_IDLE_ULTOLD }, { "ULTRIXOLD", VAX_IDLE_ULTOLD },
{ "ULTRIX-1.X", VAX_IDLE_ULT1X },
{ "OPENBSDOLD", VAX_IDLE_QUAD }, { "OPENBSDOLD", VAX_IDLE_QUAD },
{ "OPENBSD", VAX_IDLE_BSDNEW }, { "OPENBSD", VAX_IDLE_BSDNEW },
{ "QUASIJARUS", VAX_IDLE_QUAD }, { "QUASIJARUS", VAX_IDLE_QUAD },
{ "32V", VAX_IDLE_QUAD }, { "32V", VAX_IDLE_QUAD },
{ "ALL", VAX_IDLE_VMS|VAX_IDLE_ULTOLD|VAX_IDLE_ULT|VAX_IDLE_QUAD|VAX_IDLE_BSDNEW }, { "ALL", VAX_IDLE_VMS|VAX_IDLE_ULTOLD|VAX_IDLE_ULT|VAX_IDLE_ULT1X|VAX_IDLE_QUAD|VAX_IDLE_BSDNEW },
{ NULL, 0 } { NULL, 0 }
}; };

9
VAX/vax_defs.h
View file

@ -719,10 +719,11 @@ enum opcodes {
if (((uint32) s1) < ((uint32) s2)) cc = cc | CC_C if (((uint32) s1) < ((uint32) s2)) cc = cc | CC_C
#define VAX_IDLE_VMS 0x01 #define VAX_IDLE_VMS 0x01
#define VAX_IDLE_ULT 0x02 #define VAX_IDLE_ULT 0x02 /* Ultrix more recent versions */
#define VAX_IDLE_ULTOLD 0x04 #define VAX_IDLE_ULTOLD 0x04 /* Ultrix older versions */
#define VAX_IDLE_QUAD 0x08 #define VAX_IDLE_ULT1X 0x08 /* Ultrix 1.x */
#define VAX_IDLE_BSDNEW 0x10 #define VAX_IDLE_QUAD 0x10
#define VAX_IDLE_BSDNEW 0x20
extern uint32 cpu_idle_mask; /* idle mask */ extern uint32 cpu_idle_mask; /* idle mask */
void cpu_idle (void); void cpu_idle (void);