PDP11: FP fix from Bob Supnik: MMR1 does not track register changes (Johnny Billquist) Fix #44
This commit is contained in:
Mark Pizzolato
parent
6bf32c0687
commit
4da7f5e028
1 changed files with 215 additions and 107 deletions
322
PDP11/pdp11_fp.c
322
PDP11/pdp11_fp.c
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@ -1,6 +1,6 @@
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/* pdp11_fp.c: PDP-11 floating point simulator (32b version)
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Copyright (c) 1993-2013, Robert M Supnik
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Copyright (c) 1993-2015, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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@ -23,6 +23,7 @@
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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24-Mar-15 RMS MMR1 does not track register changes (Johnny Billquist)
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20-Apr-13 RMS MMR1 does not track PC changes (Johnny Billquist)
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22-Sep-05 RMS Fixed declarations (Sterling Garwood)
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04-Oct-04 RMS Added FIS instructions
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@ -69,10 +70,8 @@
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and exception enable bits for individual error conditions. Exceptions
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cause a trap through 0244, unless the individual exception, or all
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exceptions, are disabled. Illegal address mode, undefined variable,
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and divide by zero abort the current instruction; all other exceptions
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permit the instruction to complete. (Aborts are implemented as traps
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that request an "interrupt" trap. If an interrupt is pending, it is
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serviced; if not, trap_req is updated and processing continues.)
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and divide by zero NOP the current instruction; all other exceptions
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permit the instruction to complete.
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Floating point specifiers are similar to integer specifiers, with
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the length of the operand being up to 8 bytes. In two specific cases,
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@ -85,7 +84,14 @@
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immediate for integers or floating point, only 16b are
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accessed; if the operand is 32b or 64b, these
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are the high order 16b of the operand
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are the high order 16b of the operand.
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The FP11 cannot update MMR1 on specifier changes, because the
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quantity field is too narrow for +8 or -8. Instead, the simulator
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records changes to be made and only commits them at instruction
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completion. Instructions that can overwrite a general register
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(STFPS, STST, STEXP, STCFi in mode 0) need not check for conflicts;
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in mode 0, no general register changes occur in the specifier flow.
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*/
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#include "pdp11_defs.h"
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@ -107,7 +113,7 @@
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#define FPS_C (1u << FPS_V_C)
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#define FPS_CC (FPS_N + FPS_Z + FPS_V + FPS_C)
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#define FPS_RW (FPS_ER + FPS_ID + FPS_IUV + FPS_IU + FPS_IV + \
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FPS_IC + FPS_D + FPS_L + FPS_T + FPS_CC)
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FPS_IC + FPS_D + FPS_L + FPS_T + FPS_CC)
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/* Floating point exception codes */
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@ -144,6 +150,14 @@
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#define LONG 4
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#define QUAD 8
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/* Reg change word */
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#define FPCHG(v,r) (((v) << FPCHG_V_VAL) | (r))
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#define FPCHG_REG 07 /* register number */
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#define FPCHG_V_VAL 3 /* offset to value */
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#define FPCHG_GETREG(x) ((x) & FPCHG_REG)
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#define FPCHG_GETVAL(x) ((x) >> FPCHG_V_VAL)
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/* Double precision operations on 64b quantities */
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#define F_LOAD(qd,ac,ds) \
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@ -231,11 +245,13 @@ static const uint32 and_mask[33] = { 0,
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0x1FFFFFFF, 0x3FFFFFFF, 0x7FFFFFFF, 0xFFFFFFFF
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};
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int32 backup_PC;
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int32 fpnotrap (int32 code);
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int32 GeteaFP (int32 spec, int32 len);
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int32 fp_change;
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int32 fpnotrap (int32 code);
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int32 GeteaFW (int32 spec);
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int32 GeteaFP (int32 spec, int32 len);
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uint32 ReadI (int32 addr, int32 spec, int32 len);
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void ReadFP (fpac_t *fac, int32 addr, int32 spec, int32 len);
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t_bool ReadFP (fpac_t *fac, int32 addr, int32 spec, int32 len);
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void WriteI (int32 data, int32 addr, int32 spec, int32 len);
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void WriteFP (fpac_t *data, int32 addr, int32 spec, int32 len);
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int32 setfcc (int32 old_status, int32 result_high, int32 newV);
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@ -247,7 +263,6 @@ void frac_mulfp11 (fpac_t *src1, fpac_t *src2);
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int32 roundfp11 (fpac_t *src);
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int32 round_and_pack (fpac_t *fac, int32 exp, fpac_t *frac, int r);
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extern int32 GeteaW (int32 spec);
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extern int32 ReadW (int32 addr);
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extern void WriteW (int32 data, int32 addr);
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extern void set_stack_trap (int32 adr);
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@ -266,6 +281,7 @@ static const uint32 i_limit[2][2] = {
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};
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backup_PC = PC; /* save PC for FEA */
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fp_change = 0; /* assume no reg chg */
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ac = (IR >> 6) & 03; /* fac is IR<7:6> */
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dstspec = IR & 077;
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qdouble = FPS & FPS_D;
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@ -294,7 +310,7 @@ switch ((IR >> 8) & 017) { /* decode IR<11:8> */
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break;
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case 1: /* LDFPS */
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dst = (dstspec <= 07)? R[dstspec]: ReadW (GeteaW (dstspec));
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dst = (dstspec <= 07)? R[dstspec]: ReadW (GeteaFW (dstspec));
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FPS = dst & FPS_RW;
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break;
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@ -302,7 +318,7 @@ switch ((IR >> 8) & 017) { /* decode IR<11:8> */
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FPS = FPS & FPS_RW;
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if (dstspec <= 07)
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R[dstspec] = FPS;
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else WriteW (FPS, GeteaW (dstspec));
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else WriteW (FPS, GeteaFW (dstspec));
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break;
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case 3: /* STST */
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@ -323,34 +339,37 @@ switch ((IR >> 8) & 017) { /* decode IR<11:8> */
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break;
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case 1: /* TSTf */
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ReadFP (&fsrc, GeteaFP (dstspec, lenf), dstspec, lenf);
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FPS = setfcc (FPS, fsrc.h, 0);
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if (ReadFP (&fsrc, GeteaFP (dstspec, lenf), dstspec, lenf))
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FPS = setfcc (FPS, fsrc.h, 0);
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break;
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case 2: /* ABSf */
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ReadFP (&fsrc, ea = GeteaFP (dstspec, lenf), dstspec, lenf);
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if (GET_EXP (fsrc.h) == 0)
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fsrc = zero_fac;
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else fsrc.h = fsrc.h & ~FP_SIGN;
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WriteFP (&fsrc, ea, dstspec, lenf);
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FPS = setfcc (FPS, fsrc.h, 0);
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if (ReadFP (&fsrc, ea = GeteaFP (dstspec, lenf), dstspec, lenf)) {
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if (GET_EXP (fsrc.h) == 0)
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fsrc = zero_fac;
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else fsrc.h = fsrc.h & ~FP_SIGN;
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WriteFP (&fsrc, ea, dstspec, lenf);
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FPS = setfcc (FPS, fsrc.h, 0);
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}
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break;
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case 3: /* NEGf */
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ReadFP (&fsrc, ea = GeteaFP (dstspec, lenf), dstspec, lenf);
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if (GET_EXP (fsrc.h) == 0)
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fsrc = zero_fac;
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else fsrc.h = fsrc.h ^ FP_SIGN;
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WriteFP (&fsrc, ea, dstspec, lenf);
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FPS = setfcc (FPS, fsrc.h, 0);
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if (ReadFP (&fsrc, ea = GeteaFP (dstspec, lenf), dstspec, lenf)) {
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if (GET_EXP (fsrc.h) == 0)
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fsrc = zero_fac;
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else fsrc.h = fsrc.h ^ FP_SIGN;
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WriteFP (&fsrc, ea, dstspec, lenf);
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FPS = setfcc (FPS, fsrc.h, 0);
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}
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break;
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} /* end switch <7:6> */
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break; /* end case 1 */
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case 005: /* LDf */
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ReadFP (&fsrc, GeteaFP (dstspec, lenf), dstspec, lenf);
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F_STORE (qdouble, fsrc, FR[ac]);
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FPS = setfcc (FPS, fsrc.h, 0);
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if (ReadFP (&fsrc, GeteaFP (dstspec, lenf), dstspec, lenf)) {
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F_STORE (qdouble, fsrc, FR[ac]);
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FPS = setfcc (FPS, fsrc.h, 0);
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}
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break;
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case 010: /* STf */
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@ -359,14 +378,15 @@ switch ((IR >> 8) & 017) { /* decode IR<11:8> */
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break;
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case 017: /* LDCff' */
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ReadFP (&fsrc, GeteaFP (dstspec, 12 - lenf), dstspec, 12 - lenf);
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if (GET_EXP (fsrc.h) == 0)
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fsrc = zero_fac;
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if ((FPS & (FPS_D + FPS_T)) == 0)
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newV = roundfp11 (&fsrc);
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else newV = 0;
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F_STORE (qdouble, fsrc, FR[ac]);
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FPS = setfcc (FPS, fsrc.h, newV);
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if (ReadFP (&fsrc, GeteaFP (dstspec, 12 - lenf), dstspec, 12 - lenf)) {
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if (GET_EXP (fsrc.h) == 0)
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fsrc = zero_fac;
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if ((FPS & (FPS_D + FPS_T)) == 0)
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newV = roundfp11 (&fsrc);
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else newV = 0;
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F_STORE (qdouble, fsrc, FR[ac]);
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FPS = setfcc (FPS, fsrc.h, newV);
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}
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break;
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case 014: /* STCff' */
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@ -381,27 +401,29 @@ switch ((IR >> 8) & 017) { /* decode IR<11:8> */
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break;
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case 007: /* CMPf */
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ReadFP (&fsrc, GeteaFP (dstspec, lenf), dstspec, lenf);
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F_LOAD (qdouble, FR[ac], fac);
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if (GET_EXP (fsrc.h) == 0)
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fsrc = zero_fac;
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if (GET_EXP (fac.h) == 0)
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fac = zero_fac;
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if ((fsrc.h == fac.h) && (fsrc.l == fac.l)) { /* equal? */
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FPS = (FPS & ~FPS_CC) | FPS_Z;
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if ((fsrc.h | fsrc.l) == 0) { /* zero? */
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F_STORE (qdouble, zero_fac, FR[ac]);
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if (ReadFP (&fsrc, GeteaFP (dstspec, lenf), dstspec, lenf)) {
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F_LOAD (qdouble, FR[ac], fac);
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if (GET_EXP (fsrc.h) == 0)
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fsrc = zero_fac;
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if (GET_EXP (fac.h) == 0)
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fac = zero_fac;
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if ((fsrc.h == fac.h) && (fsrc.l == fac.l)) { /* equal? */
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FPS = (FPS & ~FPS_CC) | FPS_Z;
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if ((fsrc.h | fsrc.l) == 0) { /* zero? */
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F_STORE (qdouble, zero_fac, FR[ac]);
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}
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}
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else { /* unequal */
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FPS = (FPS & ~FPS_CC) | ((fsrc.h >> (FP_V_SIGN - PSW_V_N)) & FPS_N);
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if ((GET_SIGN (fsrc.h ^ fac.h) == 0) && (fac.h != 0) &&
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F_LT (fsrc, fac))
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FPS = FPS ^ FPS_N;
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}
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break;
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}
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FPS = (FPS & ~FPS_CC) | ((fsrc.h >> (FP_V_SIGN - PSW_V_N)) & FPS_N);
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if ((GET_SIGN (fsrc.h ^ fac.h) == 0) && (fac.h != 0) &&
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F_LT (fsrc, fac))
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FPS = FPS ^ FPS_N;
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break;
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case 015: /* LDEXP */
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dst = (dstspec <= 07)? R[dstspec]: ReadW (GeteaW (dstspec));
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dst = (dstspec <= 07)? R[dstspec]: ReadW (GeteaFW (dstspec));
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F_LOAD (qdouble, FR[ac], fac);
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fac.h = (fac.h & ~FP_EXP) | (((dst + FP_BIAS) & FP_M_EXP) << FP_V_EXP);
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newV = 0;
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@ -429,7 +451,7 @@ switch ((IR >> 8) & 017) { /* decode IR<11:8> */
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FPS = (FPS & ~FPS_CC) | (N << PSW_V_N) | (Z << PSW_V_Z);
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if (dstspec <= 07)
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R[dstspec] = dst;
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else WriteW (dst, GeteaW (dstspec));
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else WriteW (dst, GeteaFW (dstspec));
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break;
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case 016: /* LDCif */
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@ -500,56 +522,131 @@ switch ((IR >> 8) & 017) { /* decode IR<11:8> */
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break;
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case 002: /* MULf */
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ReadFP (&fsrc, GeteaFP (dstspec, lenf), dstspec, lenf);
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F_LOAD (qdouble, FR[ac], fac);
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newV = mulfp11 (&fac, &fsrc);
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F_STORE (qdouble, fac, FR[ac]);
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FPS = setfcc (FPS, fac.h, newV);
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if (ReadFP (&fsrc, GeteaFP (dstspec, lenf), dstspec, lenf)) {
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F_LOAD (qdouble, FR[ac], fac);
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newV = mulfp11 (&fac, &fsrc);
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F_STORE (qdouble, fac, FR[ac]);
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FPS = setfcc (FPS, fac.h, newV);
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}
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break;
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case 003: /* MODf */
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ReadFP (&fsrc, GeteaFP (dstspec, lenf), dstspec, lenf);
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if (ReadFP (&fsrc, GeteaFP (dstspec, lenf), dstspec, lenf)) {
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F_LOAD (qdouble, FR[ac], fac);
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newV = modfp11 (&fac, &fsrc, &modfrac);
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F_STORE (qdouble, fac, FR[ac | 1]);
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F_STORE (qdouble, modfrac, FR[ac]);
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FPS = setfcc (FPS, modfrac.h, newV);
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newV = modfp11 (&fac, &fsrc, &modfrac);
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F_STORE (qdouble, fac, FR[ac | 1]);
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F_STORE (qdouble, modfrac, FR[ac]);
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FPS = setfcc (FPS, modfrac.h, newV);
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}
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break;
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case 004: /* ADDf */
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ReadFP (&fsrc, GeteaFP (dstspec, lenf), dstspec, lenf);
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F_LOAD (qdouble, FR[ac], fac);
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newV = addfp11 (&fac, &fsrc);
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F_STORE (qdouble, fac, FR[ac]);
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FPS = setfcc (FPS, fac.h, newV);
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if (ReadFP (&fsrc, GeteaFP (dstspec, lenf), dstspec, lenf)) {
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F_LOAD (qdouble, FR[ac], fac);
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newV = addfp11 (&fac, &fsrc);
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F_STORE (qdouble, fac, FR[ac]);
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FPS = setfcc (FPS, fac.h, newV);
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}
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break;
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case 006: /* SUBf */
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ReadFP (&fsrc, GeteaFP (dstspec, lenf), dstspec, lenf);
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F_LOAD (qdouble, FR[ac], fac);
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if (GET_EXP (fsrc.h) != 0)
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fsrc.h = fsrc.h ^ FP_SIGN;
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newV = addfp11 (&fac, &fsrc);
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F_STORE (qdouble, fac, FR[ac]);
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FPS = setfcc (FPS, fac.h, newV);
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if (ReadFP (&fsrc, GeteaFP (dstspec, lenf), dstspec, lenf)) {
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F_LOAD (qdouble, FR[ac], fac);
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if (GET_EXP (fsrc.h) != 0)
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fsrc.h = fsrc.h ^ FP_SIGN;
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newV = addfp11 (&fac, &fsrc);
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F_STORE (qdouble, fac, FR[ac]);
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FPS = setfcc (FPS, fac.h, newV);
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}
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break;
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case 011: /* DIVf */
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ReadFP (&fsrc, GeteaFP (dstspec, lenf), dstspec, lenf);
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F_LOAD (qdouble, FR[ac], fac);
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if (GET_EXP (fsrc.h) == 0) { /* divide by zero? */
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fpnotrap (FEC_DZRO);
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ABORT (TRAP_INT);
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if (ReadFP (&fsrc, GeteaFP (dstspec, lenf), dstspec, lenf)) {
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F_LOAD (qdouble, FR[ac], fac);
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if (GET_EXP (fsrc.h) == 0) /* divide by zero? */
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fpnotrap (FEC_DZRO);
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else { /* no, do divide */
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newV = divfp11 (&fac, &fsrc);
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F_STORE (qdouble, fac, FR[ac]);
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FPS = setfcc (FPS, fac.h, newV);
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}
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}
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newV = divfp11 (&fac, &fsrc);
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F_STORE (qdouble, fac, FR[ac]);
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FPS = setfcc (FPS, fac.h, newV);
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break;
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} /* end switch fop */
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/* Now process any general register modification */
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if (fp_change != 0) {
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int32 reg = FPCHG_GETREG (fp_change); /* get register */
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int32 val = FPCHG_GETVAL (fp_change); /* get value */
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if (val & 020) /* negative? */
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val = val | (-16); /* ensure proper sext */
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R[reg] = (R[reg] + val) & 0177777; /* commit change */
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}
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return;
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}
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/* Effective address calculation for word integers */
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int32 GeteaFW (int32 spec)
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{
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int32 adr, reg, ds;
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reg = spec & 07; /* register number */
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ds = (reg == 7)? isenable: dsenable; /* dspace if not PC */
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switch (spec >> 3) { /* decode spec<5:3> */
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default: /* can't get here */
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case 1: /* (R) */
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return (R[reg] | ds);
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case 2: /* (R)+ */
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adr = R[reg]; /* post increment */
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if (reg == 7) /* commit PC chg now */
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R[reg] = (R[reg] + 2) & 0177777;
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else fp_change = FPCHG (2, reg); /* others, update later */
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return (adr | ds);
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case 3: /* @(R)+ */
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adr = R[reg]; /* post increment */
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if (reg == 7) /* commit PC chg now */
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R[reg] = (R[reg] + 2) & 0177777;
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else fp_change = FPCHG (2, reg); /* others, update later */
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adr = ReadW (adr | ds);
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return (adr | dsenable);
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case 4: /* -(R) */
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adr = (R[reg] - 2) & 0177777; /* predecrement */
|
||||
if (reg == 7) /* commit PC chg now */
|
||||
R[reg] = adr;
|
||||
else fp_change = FPCHG (-2, reg); /* others, update later */
|
||||
if ((reg == 6) && (cm == MD_KER) && (adr < (STKLIM + STKL_Y)))
|
||||
set_stack_trap (adr);
|
||||
return (adr | ds);
|
||||
|
||||
case 5: /* @-(R) */
|
||||
adr = (R[reg] - 2) & 0177777; /* predecrement */
|
||||
if (reg == 7) /* commit PC chg now */
|
||||
R[reg] = adr;
|
||||
else fp_change = FPCHG (-2, reg); /* others, update later */
|
||||
if ((reg == 6) && (cm == MD_KER) && (adr < (STKLIM + STKL_Y)))
|
||||
set_stack_trap (adr);
|
||||
adr = ReadW (adr | ds);
|
||||
return (adr | dsenable);
|
||||
|
||||
case 6: /* d(r) */
|
||||
adr = ReadW (PC | isenable);
|
||||
PC = (PC + 2) & 0177777;
|
||||
return (((R[reg] + adr) & 0177777) | dsenable);
|
||||
|
||||
case 7: /* @d(R) */
|
||||
adr = ReadW (PC | isenable);
|
||||
PC = (PC + 2) & 0177777;
|
||||
adr = ReadW (((R[reg] + adr) & 0177777) | dsenable);
|
||||
return (adr | dsenable);
|
||||
} /* end switch */
|
||||
}
|
||||
|
||||
/* Effective address calculation for fp operands
|
||||
|
||||
Inputs:
|
||||
|
|
@ -561,6 +658,9 @@ return;
|
|||
Warnings:
|
||||
- Do not call this routine for integer mode 0 operands
|
||||
- Do not call this routine more than once per instruction
|
||||
|
||||
Note that for modes 06 and 07, it is OKAY to bail out of the FP
|
||||
instruction immediately; no general register updates can occur.
|
||||
*/
|
||||
|
||||
int32 GeteaFP (int32 spec, int32 len)
|
||||
|
|
@ -574,7 +674,7 @@ switch (spec >> 3) { /* case on spec */
|
|||
case 0: /* floating AC */
|
||||
if (reg >= 06) {
|
||||
fpnotrap (FEC_OP);
|
||||
ABORT (TRAP_INT);
|
||||
ABORT (TRAP_INT); /* scuttle instr */
|
||||
}
|
||||
return 0;
|
||||
|
||||
|
|
@ -582,33 +682,35 @@ switch (spec >> 3) { /* case on spec */
|
|||
return (R[reg] | ds);
|
||||
|
||||
case 2: /* (R)+ */
|
||||
if (reg == 7)
|
||||
len = 2;
|
||||
R[reg] = ((adr = R[reg]) + len) & 0177777;
|
||||
if (update_MM && (reg != 7))
|
||||
MMR1 = (len << 3) | reg;
|
||||
adr = R[reg]; /* post increment */
|
||||
if (reg == 7) /* commit PC chg now */
|
||||
R[reg] = (R[reg] + 2) & 0177777;
|
||||
else fp_change = FPCHG (len, reg); /* others, update later */
|
||||
return (adr | ds);
|
||||
|
||||
case 3: /* @(R)+ */
|
||||
R[reg] = ((adr = R[reg]) + 2) & 0177777;
|
||||
if (update_MM && (reg != 7))
|
||||
MMR1 = 020 | reg;
|
||||
adr = R[reg]; /* post increment */
|
||||
if (reg == 7) /* commit PC chg now */
|
||||
R[reg] = (R[reg] + 2) & 0177777;
|
||||
else fp_change = FPCHG (2, reg); /* others, update later */
|
||||
adr = ReadW (adr | ds);
|
||||
return (adr | dsenable);
|
||||
|
||||
case 4: /* -(R) */
|
||||
adr = R[reg] = (R[reg] - len) & 0177777;
|
||||
if (update_MM && (reg != 7))
|
||||
MMR1 = (((-len) & 037) << 3) | reg;
|
||||
adr = (R[reg] - len) & 0177777; /* predecrement */
|
||||
if (reg == 7) /* commit PC chg now */
|
||||
R[reg] = adr;
|
||||
else fp_change = FPCHG (-len, reg); /* others, udpate later */
|
||||
if ((reg == 6) && (cm == MD_KER) && (adr < (STKLIM + STKL_Y)))
|
||||
set_stack_trap (adr);
|
||||
return (adr | ds);
|
||||
|
||||
case 5: /* @-(R) */
|
||||
adr = R[reg] = (R[reg] - 2) & 0177777;
|
||||
if (update_MM && (reg != 7))
|
||||
MMR1 = 0360 | reg;
|
||||
if ((reg == 6) && (cm == MD_KER) && (adr < (STKLIM + STKL_Y)))
|
||||
adr = (R[reg] - 2) & 0177777; /* predecrement */
|
||||
if (reg == 7) /* commit PC chg now */
|
||||
R[reg] = adr;
|
||||
else fp_change = FPCHG (-2, reg); /* others, update later */
|
||||
if ((reg == 6) && (cm == MD_KER) && ((adr - 2) < (STKLIM + STKL_Y)))
|
||||
set_stack_trap (adr);
|
||||
adr = ReadW (adr | ds);
|
||||
return (adr | dsenable);
|
||||
|
|
@ -653,15 +755,18 @@ return ((ReadW (VA) << 16) |
|
|||
VA = virtual address, VA<18:16> = mode, I/D space
|
||||
spec = specifier
|
||||
len = length (4/8 bytes)
|
||||
Output:
|
||||
TRUE if read succeeded
|
||||
FALSE if instruction must be NOP'd
|
||||
*/
|
||||
|
||||
void ReadFP (fpac_t *fptr, int32 VA, int32 spec, int32 len)
|
||||
t_bool ReadFP (fpac_t *fptr, int32 VA, int32 spec, int32 len)
|
||||
{
|
||||
int32 exta;
|
||||
|
||||
if (spec <= 07) {
|
||||
F_LOAD_P (len == QUAD, FR[spec], fptr);
|
||||
return;
|
||||
return TRUE;
|
||||
}
|
||||
if (spec == 027) {
|
||||
fptr->h = (ReadW (VA) << FP_V_F0);
|
||||
|
|
@ -676,9 +781,11 @@ else {
|
|||
(ReadW (exta | ((VA + 6) & 0177777)) << FP_V_F3);
|
||||
else fptr->l = 0;
|
||||
}
|
||||
if ((GET_SIGN (fptr->h) != 0) && (GET_EXP (fptr->h) == 0) &&
|
||||
(fpnotrap (FEC_UNDFV) == 0)) ABORT (TRAP_INT);
|
||||
return;
|
||||
if ((GET_SIGN (fptr->h) != 0) &&
|
||||
(GET_EXP (fptr->h) == 0) &&
|
||||
(fpnotrap (FEC_UNDFV) == 0))
|
||||
return FALSE;
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
/* Write integer result
|
||||
|
|
@ -1228,7 +1335,8 @@ int32 fpnotrap (int32 code)
|
|||
{
|
||||
static const int32 test_code[] = { 0, 0, 0, FPS_IC, FPS_IV, FPS_IU, FPS_IUV };
|
||||
|
||||
if ((code >= FEC_ICVT) && (code <= FEC_UNDFV) &&
|
||||
if ((code >= FEC_ICVT) &&
|
||||
(code <= FEC_UNDFV) &&
|
||||
((FPS & test_code[code >> 1]) == 0))
|
||||
return TRUE;
|
||||
FPS = FPS | FPS_ER;
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue