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Notes For V2.10-1

Browse source 
WARNING: V2.10 has reorganized and renamed some of the definition
files for the PDP-10, PDP-11, and VAX.  Be sure to delete all
previous source files before you unpack the Zip archive, or
unpack it into a new directory structure.

WARNING: V2.10 has a new, more comprehensive save file format.
Restoring save files from previous releases will cause 'invalid
register' errors and loss of CPU option flags, device enable/
disable flags, unit online/offline flags, and unit writelock
flags.

WARNING: If you are using Visual Studio .NET through the IDE,
be sure to turn off the /Wp64 flag in the project settings, or
dozens of spurious errors will be generated.

WARNING: Compiling Ethernet support under Windows requires
extra steps; see the Ethernet readme file.  Ethernet support is
currently available only for Windows, Linux, NetBSD, and OpenBSD.

1. New Features

1.1 SCP and Libraries

- The VT emulation package has been replaced by the capability
  to remote the console to a Telnet session.  Telnet clients
  typically have more complete and robust VT100 emulation.
- Simulated devices may now have statically allocated buffers,
  in addition to dynamically allocated buffers or disk-based
  data stores.
- The DO command now takes substitutable arguments (max 9).
  In command files, %n represents substitutable argument n.
- The initial command line is now interpreted as the command
  name and substitutable arguments for a DO command.  This is
  backward compatible to prior versions.
- The initial command line parses switches.  -Q is interpreted
  as quiet mode; informational messages are suppressed.
- The HELP command now takes an optional argument.  HELP <cmd>
  types help on the specified command.
- Hooks have been added for implementing GUI-based consoles,
  as well as simulator-specific command extensions.  A few
  internal data structures and definitions have changed.
- Two new routines (tmxr_open_master, tmxr_close_master) have
  been added to sim_tmxr.c.  The calling sequence for
  sim_accept_conn has been changed in sim_sock.c.
- The calling sequence for the VM boot routine has been modified
  to add an additional parameter.
- SAVE now saves, and GET now restores, controller and unit flags.
- Library sim_ether.c has been added for Ethernet support.

1.2 VAX

- Non-volatile RAM (NVR) can behave either like a memory or like
  a disk-based peripheral.  If unattached, it behaves like memory
  and is saved and restored by SAVE and RESTORE, respectively.
  If attached, its contents are loaded from disk by ATTACH and
  written back to disk at DETACH and EXIT.
- SHOW <device> VECTOR displays the device's interrupt vector.
  A few devices allow the vector to be changed with SET
  <device> VECTOR=nnn.
- SHOW CPU IOSPACE displays the I/O space address map.
- The TK50 (TMSCP tape) has been added.
- The DEQNA/DELQA (Qbus Ethernet controllers) have been added.
- Autoconfiguration support has been added.
- The paper tape reader has been removed from vax_stddev.c and
  now references a common implementation file, dec_pt.h.
- Examine and deposit switches now work on all devices, not just
  the CPU.
- Device address conflicts are not detected until simulation starts.

1.3 PDP-11

- SHOW <device> VECTOR displays the device's interrupt vector.
  Most devices allow the vector to be changed with SET
  <device> VECTOR=nnn.
- SHOW CPU IOSPACE displays the I/O space address map.
- The TK50 (TMSCP tape), RK611/RK06/RK07 (cartridge disk),
  RX211 (double density floppy), and KW11P programmable clock
  have been added.
- The DEQNA/DELQA (Qbus Ethernet controllers) have been added.
- Autoconfiguration support has been added.
- The paper tape reader has been removed from pdp11_stddev.c and
  now references a common implementation file, dec_pt.h.
- Device bootstraps now use the actual CSR specified by the
  SET ADDRESS command, rather than just the default CSR.  Note
  that PDP-11 operating systems may NOT support booting with
  non-standard addresses.
- Specifying more than 256KB of memory, or changing the bus
  configuration, causes all peripherals that are not compatible
  with the current bus configuration to be disabled.
- Device address conflicts are not detected until simulation starts.

1.4 PDP-10

- SHOW <device> VECTOR displays the device's interrupt vector.
  A few devices allow the vector to be changed with SET
  <device> VECTOR=nnn.
- SHOW CPU IOSPACE displays the I/O space address map.
- The RX211 (double density floppy) has been added; it is off
  by default.
- The paper tape now references a common implementation file,
  dec_pt.h.
- Device address conflicts are not detected until simulation starts.

1.5 PDP-1

- DECtape (then known as MicroTape) support has been added.
- The line printer and DECtape can be disabled and enabled.

1.6 PDP-8

- The RX28 (double density floppy) has been added as an option to
  the existing RX8E controller.
- SHOW <device> DEVNO displays the device's device number.  Most
  devices allow the device number to be changed with SET <device>
  DEVNO=nnn.
- Device number conflicts are not detected until simulation starts.

1.7 IBM 1620

- The IBM 1620 simulator has been released.

1.8 AltairZ80

- A hard drive has been added for increased storage.
- Several bugs have been fixed.

1.9 HP 2100

- The 12845A has been added and made the default line printer (LPT).
  The 12653A has been renamed LPS and is off by default.  It also
  supports the diagnostic functions needed to run the DCPC and DMS
  diagnostics.
- The 12557A/13210A disk defaults to the 13210A (7900/7901).
- The 12559A magtape is off by default.
- New CPU options (EAU/NOEAU) enable/disable the extended arithmetic
  instructions for the 2116.  These instructions are standard on
  the 2100 and 21MX.
- New CPU options (MPR/NOMPR) enable/disable memory protect for the
  2100 and 21MX.
- New CPU options (DMS/NODMS) enable/disable the dynamic mapping
  instructions for the 21MX.
- The 12539 timebase generator autocalibrates.

1.10 Simulated Magtapes

- Simulated magtapes recognize end of file and the marker
  0xFFFFFFFF as end of medium.  Only the TMSCP tape simulator
  can generate an end of medium marker.
- The error handling in simulated magtapes was overhauled to be
  consistent through all simulators.

1.11 Simulated DECtapes

- Added support for RT11 image file format (256 x 16b) to DECtapes.

2. Release Notes

2.1 Bugs Fixed

- TS11/TSV05 was not simulating the XS0_MOT bit, causing failures
  under VMS.  In addition, two of the CTL options were coded
  interchanged.
- IBM 1401 tape was not setting a word mark under group mark for
  load mode reads.  This caused the diagnostics to crash.
- SCP bugs in ssh_break and set_logon were fixed (found by Dave
  Hittner).
- Numerous bugs in the HP 2100 extended arithmetic, floating point,
  21MX, DMS, and IOP instructions were fixed.  Bugs were also fixed
  in the memory protect and DMS functions.  The moving head disks
  (DP, DQ) were revised to simulate the hardware more accurately.
  Missing functions in DQ (address skip, read address) were added.
- PDP-10 tape wouldn't boot, and then wouldn't read (reported by
  Michael Thompson and Harris Newman, respectively)
- PDP-1 typewriter is half duplex, with only one shift state for
  both input and output (found by Derek Peschel)

2.2 HP 2100 Debugging

- The HP 2100 CPU nows runs all of the CPU diagnostics.
- The peripherals run most of the peripheral diagnostics.  There
  is still a problem in overlapped seek operation on the disks.
  See the file hp2100_diag.txt for details.

3. In Progress

These simulators are not finished and are available in a separate
Zip archive distribution.

- Interdata 16b/32b: coded, partially tested.  See the file
  id_diag.txt for details.
- SDS 940: coded, partially tested.
This commit is contained in:
Bob Supnik 2002-11-21 19:43:00 -08:00 • committed by Mark Pizzolato
parent 2c2dd5ea33
commit 4ea745b3ad
14 changed files with 3528 additions and 134 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

6
0readme_210.txt
View file

@ -1,4 +1,4 @@
Notes For V2.10-0
Notes For V2.10-1
WARNING: V2.10 has reorganized and renamed some of the definition
files for the PDP-10, PDP-11, and VAX. Be sure to delete all
@ -171,6 +171,10 @@ currently available only for Windows, Linux, NetBSD, and OpenBSD.
in the memory protect and DMS functions. The moving head disks
(DP, DQ) were revised to simulate the hardware more accurately.
Missing functions in DQ (address skip, read address) were added.
- PDP-10 tape wouldn't boot, and then wouldn't read (reported by
Michael Thompson and Harris Newman, respectively)
- PDP-1 typewriter is half duplex, with only one shift state for
both input and output (found by Derek Peschel)
2.2 HP 2100 Debugging

40
PDP1/pdp1_doc.txt
View file

@ -61,7 +61,7 @@ name(s)
CPU PDP-1 CPU with up to 64KW of memory
PTR,PTP integral paper tape reader/punch
TTI,TTO Flexowriter typewriter input/output
TTY console typewriter
LPT Type 62 line printer
DT Type 550 Microtape (DECtape)
@ -187,32 +187,30 @@ Error handling is as follows:
OS I/O error x report error and stop
2.2.3 Terminal Input (TTI)
2.2.3 Console Typewriter (TTY)
The terminal input (TTI) polls the console keyboard for input. It
implements these registers:
The Typewriter is a half-duplex electric typewriter (originally a
Friden Flexowriter, later an IBM Sorobon B). It has only a single
buffer and a single carriage state but distinct input and output
done and interrupt flags. The typewriter input (TTY unit 0) polls
the console keyboard for input. The typewriter output (TTY unit 1)
writes to the simulator console window.
The typewriter implements these registers:
name size comments
BUF 8 last data item processed
DONE 1 device done flag
POS 32 number of characters input
TIME 24 keyboard polling interval
2.2.4 Terminal Output (TTO)
The terminal output (TTO) writes to the simulator console window.
It implements these registers:
name size comments
BUF 8 last data item processed
DONE 1 device done flag
BUF 6 typewriter buffer
UC 1 upper case/lower case state flag
RPLS 1 return restart pulse flag
POS 32 number of characters output
TIME 24 time from I/O initiation to interrupt
KDONE 1 input ready flag
KPOS 32 number of characters input
KTIME 24 keyboard polling interval
TDONE 1 output done flag
TPOS 32 number of characters output
TTIME 24 time from I/O initiation to interrupt
2.2.5 Type 62 Line Printer (LPT)
2.2.4 Type 62 Line Printer (LPT)
The paper line printer (LPT) writes data to a disk file. The POS
register specifies the number of the next data item to be written.

173
PDP1/pdp1_stddev.c
View file

@ -28,6 +28,7 @@
tti keyboard
tto teleprinter
21-Nov-02 RMS Changed typewriter to half duplex (found by Derek Peschel)
06-Oct-02 RMS Revised for V2.10
30-May-02 RMS Widened POS to 32b
29-Nov-01 RMS Added read only unit support
@ -40,18 +41,23 @@
#define FIODEC_UC 074
#define FIODEC_LC 072
#define UC 0100 /* upper case */
#define BOTH 0200 /* both cases */
#define CW 0400 /* char waiting */
#define UC_V 6 /* upper case */
#define UC (1 << UC_V)
#define BOTH (1 << (UC_V + 1)) /* both cases */
#define CW (1 << (UC_V + 2)) /* char waiting */
#define TT_WIDTH 077
#define TTI 0
#define TTO 1
extern int32 sbs, ioc, iosta, PF, IO, PC;
extern int32 M[];
int32 ptr_rpls = 0, ptr_stopioe = 0, ptr_state = 0;
int32 ptp_rpls = 0, ptp_stopioe = 0;
int32 tti_state = 0;
int32 tto_rpls = 0, tto_state = 0;
int32 tti_hold = 0; /* tti hold buf */
int32 tto_rpls = 0; /* tto restart */
int32 tty_buf = 0; /* tty buffer */
int32 tty_uc = 0; /* tty uc/lc */
t_stat ptr_svc (UNIT *uptr);
t_stat ptp_svc (UNIT *uptr);
@ -59,8 +65,7 @@ t_stat tti_svc (UNIT *uptr);
t_stat tto_svc (UNIT *uptr);
t_stat ptr_reset (DEVICE *dptr);
t_stat ptp_reset (DEVICE *dptr);
t_stat tti_reset (DEVICE *dptr);
t_stat tto_reset (DEVICE *dptr);
t_stat tty_reset (DEVICE *dptr);
t_stat ptr_boot (int32 unitno, DEVICE *dptr);
/* Character translation tables */
@ -155,52 +160,34 @@ DEVICE ptp_dev = {
NULL, NULL, NULL,
NULL, 0 };
/* TTI data structures
/* TTY data structures
tti_dev TTI device descriptor
tti_unit TTI unit
tti_reg TTI register list
tty_dev TTY device descriptor
tty_unit TTY unit
tty_reg TTY register list
*/
UNIT tti_unit = { UDATA (&tti_svc, 0, 0), KBD_POLL_WAIT };
UNIT tty_unit[] = {
{ UDATA (&tti_svc, 0, 0), KBD_POLL_WAIT },
{ UDATA (&tto_svc, 0, 0), SERIAL_OUT_WAIT } };
REG tti_reg[] = {
{ ORDATA (BUF, tti_unit.buf, 6) },
{ FLDATA (DONE, iosta, IOS_V_TTI) },
{ ORDATA (STATE, tti_state, 10), REG_HRO },
{ DRDATA (POS, tti_unit.pos, 32), PV_LEFT },
{ DRDATA (TIME, tti_unit.wait, 24), REG_NZ + PV_LEFT },
{ NULL } };
DEVICE tti_dev = {
"TTI", &tti_unit, tti_reg, NULL,
1, 10, 31, 1, 8, 8,
NULL, NULL, &tti_reset,
NULL, NULL, NULL,
NULL, 0 };
/* TTO data structures
tto_dev TTO device descriptor
tto_unit TTO unit
tto_reg TTO register list
*/
UNIT tto_unit = { UDATA (&tto_svc, 0, 0), SERIAL_OUT_WAIT };
REG tto_reg[] = {
{ ORDATA (BUF, tto_unit.buf, 6) },
{ FLDATA (DONE, iosta, IOS_V_TTO) },
REG tty_reg[] = {
{ ORDATA (BUF, tty_buf, 6) },
{ FLDATA (UC, tty_uc, UC_V) },
{ FLDATA (RPLS, tto_rpls, 0) },
{ ORDATA (STATE, tto_state, 10), REG_HRO },
{ DRDATA (POS, tto_unit.pos, 32), PV_LEFT },
{ DRDATA (TIME, tto_unit.wait, 24), PV_LEFT },
{ ORDATA (HOLD, tti_hold, 9), REG_HRO },
{ FLDATA (KDONE, iosta, IOS_V_TTI) },
{ DRDATA (KTIME, tty_unit[TTI].wait, 24), REG_NZ + PV_LEFT },
{ DRDATA (KPOS, tty_unit[TTI].pos, 32), PV_LEFT },
{ FLDATA (TDONE, iosta, IOS_V_TTO) },
{ DRDATA (TTIME, tty_unit[TTO].wait, 24), PV_LEFT },
{ DRDATA (TPOS, tty_unit[TTO].pos, 32), PV_LEFT },
{ NULL } };
DEVICE tto_dev = {
"TTO", &tto_unit, tto_reg, NULL,
1, 10, 31, 1, 8, 8,
NULL, NULL, &tto_reset,
DEVICE tty_dev = {
"TTY", tty_unit, tty_reg, NULL,
2, 10, 31, 1, 8, 8,
NULL, NULL, &tty_reset,
NULL, NULL, NULL,
NULL, 0 };
@ -326,26 +313,38 @@ sim_cancel (&ptp_unit); /* deactivate unit */
return SCPE_OK;
}
/* Terminal input: IOT routine */
/* Typewriter IOT routines */
int32 tti (int32 inst, int32 dev, int32 data)
{
iosta = iosta & ~IOS_TTI; /* clear flag */
if (inst & (IO_WAIT | IO_CPLS)) /* wait or sync? */
return (STOP_RSRV << IOT_V_REASON) | (tti_unit.buf & 077);
return tti_unit.buf & 077;
return (STOP_RSRV << IOT_V_REASON) | (tty_buf & 077);
return tty_buf & 077;
}
/* Unit service */
int32 tto (int32 inst, int32 dev, int32 data)
{
iosta = iosta & ~IOS_TTO; /* clear flag */
tto_rpls = 0;
tty_buf = data & TT_WIDTH; /* load buffer */
sim_activate (&tty_unit[TTO], tty_unit[TTO].wait); /* activate unit */
if (GEN_CPLS (inst)) { /* comp pulse? */
ioc = 0;
tto_rpls = 1; }
return data;
}
/* Unit service routines */
t_stat tti_svc (UNIT *uptr)
{
int32 in, temp;
sim_activate (&tti_unit, tti_unit.wait); /* continue poll */
if (tti_state & CW) { /* char waiting? */
tti_unit.buf = tti_state & TT_WIDTH; /* return char */
tti_state = tti_state & ~CW; } /* not waiting */
sim_activate (uptr, uptr->wait); /* continue poll */
if (tti_hold & CW) { /* char waiting? */
tty_buf = tti_hold & TT_WIDTH; /* return char */
tti_hold = 0; } /* not waiting */
else { if ((temp = sim_poll_kbd ()) < SCPE_KFLAG) return temp;
temp = temp & 0177;
if (temp == 0177) temp = '\b'; /* rubout? bs */
@ -353,44 +352,18 @@ else { if ((temp = sim_poll_kbd ()) < SCPE_KFLAG) return temp;
if (temp == '\r') sim_putchar ('\n'); /* cr? add nl */
in = ascii_to_fiodec[temp]; /* translate char */
if (in == 0) return SCPE_OK; /* no xlation? */
if ((in & BOTH) || ((in & UC) == (tti_state & UC)))
tti_unit.buf = in & TT_WIDTH;
else { tti_unit.buf = (in & UC)? FIODEC_UC: FIODEC_LC;
tti_state = in | CW; } } /* set 2nd waiting */
if ((in & BOTH) || ((in & UC) == (tty_uc & UC)))
tty_buf = in & TT_WIDTH;
else { tty_uc = in & UC; /* shift case */
tty_buf = tty_uc? FIODEC_UC: FIODEC_LC;
tti_hold = in | CW; } } /* set 2nd waiting */
iosta = iosta | IOS_TTI; /* set flag */
sbs = sbs | SB_RQ; /* req seq break */
PF = PF | 040; /* set prog flag 1 */
tti_unit.pos = tti_unit.pos + 1;
uptr->pos = uptr->pos + 1;
return SCPE_OK;
}
/* Reset routine */
t_stat tti_reset (DEVICE *dptr)
{
tti_unit.buf = 0; /* clear buffer */
tti_state = 0; /* clear state */
iosta = iosta & ~IOS_TTI; /* clear flag */
sim_activate (&tti_unit, tti_unit.wait); /* activate unit */
return SCPE_OK;
}
/* Terminal output: IOT routine */
int32 tto (int32 inst, int32 dev, int32 data)
{
iosta = iosta & ~IOS_TTO; /* clear flag */
tto_rpls = 0;
tto_unit.buf = data & TT_WIDTH; /* load buffer */
sim_activate (&tto_unit, tto_unit.wait); /* activate unit */
if (GEN_CPLS (inst)) { /* comp pulse? */
ioc = 0;
tto_rpls = 1; }
return data;
}
/* Unit service */
t_stat tto_svc (UNIT *uptr)
{
int32 out;
@ -398,30 +371,32 @@ int32 out;
iosta = iosta | IOS_TTO; /* set flag */
sbs = sbs | SB_RQ; /* req seq break */
ioc = ioc | tto_rpls; /* process restart */
if (tto_unit.buf == FIODEC_UC) { /* upper case? */
tto_state = UC;
if (tty_buf == FIODEC_UC) { /* upper case? */
tty_uc = UC;
return SCPE_OK; }
if (tto_unit.buf == FIODEC_LC) { /* lower case? */
tto_state = 0;
if (tty_buf == FIODEC_LC) { /* lower case? */
tty_uc = 0;
return SCPE_OK; }
out = fiodec_to_ascii[tto_unit.buf | tto_state]; /* translate */
out = fiodec_to_ascii[tty_buf | tty_uc]; /* translate */
if (out == 0) return SCPE_OK; /* no translation? */
sim_putchar (out);
tto_unit.pos = tto_unit.pos + 1;
uptr->pos = uptr->pos + 1;
if (out == '\r') { /* cr? add lf */
sim_putchar ('\n');
tto_unit.pos = tto_unit.pos + 1; }
uptr->pos = uptr->pos + 1; }
return SCPE_OK;
}
/* Reset routine */
t_stat tto_reset (DEVICE *dptr)
t_stat tty_reset (DEVICE *dptr)
{
tto_unit.buf = 0; /* clear buffer */
tto_state = 0; /* clear state */
tto_rpls = 0;
iosta = iosta & ~IOS_TTO; /* clear flag */
sim_cancel (&tto_unit); /* deactivate unit */
tty_buf = 0; /* clear buffer */
tty_uc = 0; /* clear case */
tti_hold = 0; /* clear hold buf */
tto_rpls = 0; /* clear reset pulse */
iosta = iosta & ~(IOS_TTI | IOS_TTO); /* clear flag */
sim_activate (&tty_unit[TTI], tty_unit[TTI].wait); /* activate keyboard */
sim_cancel (&tty_unit[TTO]); /* stop printer */
return SCPE_OK;
}

6
PDP1/pdp1_sys.c
View file

@ -23,6 +23,7 @@
be used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Robert M Supnik.
21-Nov-02 RMS Changed typewriter to half duplex
20-Aug-02 RMS Added DECtape support
17-Sep-01 RMS Removed multiconsole support
13-Jul-01 RMS Fixed RIM loader format
@ -39,7 +40,7 @@
extern DEVICE cpu_dev;
extern DEVICE ptr_dev, ptp_dev;
extern DEVICE tti_dev, tto_dev;
extern DEVICE tty_dev;
extern DEVICE lpt_dev, dt_dev;
extern UNIT cpu_unit;
extern REG cpu_reg[];
@ -68,8 +69,7 @@ DEVICE *sim_devices[] = {
&cpu_dev,
&ptr_dev,
&ptp_dev,
&tti_dev,
&tto_dev,
&tty_dev,
&lpt_dev,
&dt_dev,
NULL };

9
PDP10/pdp10_rp.c
View file

@ -25,6 +25,7 @@
rp RH/RP/RM moving head disks
21-Nov-02 RMS Fixed bug in bootstrap (reported by Michael Thompson)
29-Sep-02 RMS Added variable vector support
New data structures
30-Nov-01 RMS Added read only unit, extended SET/SHOW support support
@ -1029,8 +1030,8 @@ return SCPE_OK;
static const d10 boot_rom_dec[] = {
0515040000001, /* boot:hrlzi 1,1 ; uba # */
0201000140001, /* movei 0,140001 ; vld,fst,pg 1 */
0713001000000+IOBA_UBMAP+1, /* wrio 0,763001(1); set ubmap */
0435040000000+IOBA_RP, /* iori 1,776700 ; rh addr */
0713001000000+(IOBA_UBMAP+1 & RMASK), /* wrio 0,763001(1); set ubmap */
0435040000000+(IOBA_RP & RMASK), /* iori 1,776700 ; rh addr */
0202040000000+FE_RHBASE, /* movem 1,FE_RHBASE */
0201000000040, /* movei 0,40 ; ctrl reset */
0713001000010, /* wrio 0,10(1) ; ->RPCS2 */
@ -1076,8 +1077,8 @@ static const d10 boot_rom_dec[] = {
static const d10 boot_rom_its[] = {
0515040000001, /* boot:hrlzi 1,1 ; uba # */
0201000140001, /* movei 0,140001 ; vld,fst,pg 1 */
0715000000000+IOBA_UBMAP+1, /* iowrq 0,763001 ; set ubmap */
0435040000000+IOBA_RP, /* iori 1,776700 ; rh addr */
0715000000000+(IOBA_UBMAP+1 & RMASK), /* iowrq 0,763001 ; set ubmap */
0435040000000+(IOBA_RP & RMASK), /* iori 1,776700 ; rh addr */
0202040000000+FE_RHBASE, /* movem 1,FE_RHBASE */
0201000000040, /* movei 0,40 ; ctrl reset */
0715001000010, /* iowrq 0,10(1) ; ->RPCS2 */

13
PDP10/pdp10_tu.c
View file

@ -25,6 +25,8 @@
tu RH11/TM03/TU45 magtape
21-Nov-02 RMS Fixed bug in bootstrap (reported by Michael Thompson)
Fixed bug in read (reported by Harris Newman)
29-Sep-02 RMS Added variable vector support
New data structures
28-Aug-02 RMS Added end of medium support
@ -359,7 +361,7 @@ REG tu_reg[] = {
{ FLDATA (STOP_IOE, tu_stopioe, 0) },
{ DRDATA (TIME, tu_time, 24), PV_LEFT },
{ URDATA (UST, tu_unit[0].USTAT, 8, 17, 0, TU_NUMDR, 0) },
{ URDATA (POS, tu_unit[0].pos, 8, 32, 0,
{ URDATA (POS, tu_unit[0].pos, 10, 32, 0,
TU_NUMDR, PV_LEFT | REG_RO) },
{ ORDATA (LOG, tu_log, 8), REG_HIDDEN },
{ NULL } };
@ -758,7 +760,6 @@ case FNC_WCHKF: /* wcheck = read */
tufs = tufs | FS_ID; /* PE BOT? ID burst */
TXFR (ba, wc, 0); /* validate transfer */
if (tu_rdlntf (uptr, &tbc, &err)) break; /* read rec lnt, err? */
fseek (uptr->fileref, uptr->pos, SEEK_SET);
if (MTRF (tbc)) { /* bad record? */
tuer = tuer | ER_CRC; /* set error flag */
uptr->pos = uptr->pos + ((MTRL (tbc) + 1) & ~1) +
@ -1017,8 +1018,8 @@ return SCPE_OK;
static const d10 boot_rom_dec[] = {
0515040000003, /* boot:hrlzi 1,3 ; uba # */
0201000040001, /* movei 0,40001 ; vld,pg 1 */
0713001000000+IOBA_UBMAP+1, /* wrio 0,763001(1); set ubmap */
0435040000000+IOBA_TU, /* iori 1,772440 ; rh addr */
0713001000000+(IOBA_UBMAP+1 & RMASK), /* wrio 0,763001(1); set ubmap */
0435040000000+(IOBA_TU & RMASK), /* iori 1,772440 ; rh addr */
0202040000000+FE_RHBASE, /* movem 1,FE_RHBASE */
0201000000040, /* movei 0,40 ; ctrl reset */
0713001000010, /* wrio 0,10(1) ; ->MTFS */
@ -1055,8 +1056,8 @@ static const d10 boot_rom_dec[] = {
static const d10 boot_rom_its[] = {
0515040000003, /* boot:hrlzi 1,3 ; uba # - not used */
0201000040001, /* movei 0,40001 ; vld,pg 1 */
0714000000000+IOBA_UBMAP+1, /* iowri 0,763001 ; set ubmap */
0435040000000+IOBA_TU, /* iori 1,772440 ; rh addr */
0714000000000+(IOBA_UBMAP+1 & RMASK), /* iowri 0,763001 ; set ubmap */
0435040000000+(IOBA_TU & RMASK), /* iori 1,772440 ; rh addr */
0202040000000+FE_RHBASE, /* movem 1,FE_RHBASE */
0201000000040, /* movei 0,40 ; ctrl reset */
0714001000010, /* iowri 0,10(1) ; ->MTFS */

795
PDP1o/pdp1_cpu.c Normal file
View file

@ -0,0 +1,795 @@
/* pdp1_cpu.c: PDP-1 CPU simulator
Copyright (c) 1993-2002, Robert M. Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
Except as contained in this notice, the name of Robert M Supnik shall not
be used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Robert M Supnik.
cpu PDP-1 central processor
06-Oct-02 RMS Revised for V2.10
20-Aug-02 RMS Added DECtape support
30-Dec-01 RMS Added old PC queue
07-Dec-01 RMS Revised to use breakpoint package
30-Nov-01 RMS Added extended SET/SHOW support
16-Dec-00 RMS Fixed bug in XCT address calculation
14-Apr-99 RMS Changed t_addr to unsigned
The PDP-1 was Digital's first computer. Although Digital built four
other 18b computers, the later systems (the PDP-4, PDP-7, PDP-9, and
PDP-15) were similar to each other and quite different from the PDP-1.
Accordingly, the PDP-1 requires a distinct simulator.
The register state for the PDP-1 is:
AC<0:17> accumulator
IO<0:17> IO register
OV overflow flag
PC<0:15> program counter
IOSTA I/O status register
SBS<0:2> sequence break flip flops
IOH I/O halt flip flop
IOC I/O completion flip flop
EXTM extend mode
PF<1:6> program flags
SS<1:6> sense switches
TW<0:17> test word (switch register)
Questions:
cks: which bits are line printer print done and space done?
cks: is there a bit for sequence break enabled (yes, according
to the 1963 Handbook)
sbs: do sequence breaks accumulate while the system is disabled
(yes, according to the Maintenance Manual)
*/
/* The PDP-1 has six instruction formats: memory reference, skips,
shifts, load immediate, I/O transfer, and operate. The memory
reference format is:
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
| op |in| address | memory reference
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
<0:4> <5> mnemonic action
00
02 AND AC = AC & M[MA]
04 IOR AC = AC | M[MA]
06 XOR AC = AC ^ M[MA]
10 XCT M[MA] is executed as an instruction
12
14
16 0 CAL M[100] = AC, AC = PC, PC = 101
16 1 JDA M[MA] = AC, AC = PC, PC = MA + 1
20 LAC AC = M[MA]
22 LIO IO = M[MA]
24 DAC M[MA] = AC
26 DAP M[MA]<6:17> = AC<6:17>
30 DIP M[MA]<0:5> = AC<0:5>
32 DIO M[MA] = IO
34 DZM M[MA] = 0
36
40 ADD AC = AC + M[MA]
42 SUB AC = AC - M[MA]
44 IDX AC = M[MA] = M[MA] + 1
46 ISP AC = M[MA] = M[MA] + 1, skip if AC >= 0
50 SAD skip if AC != M[MA]
52 SAS skip if AC == M[MA]
54 MUL AC'IO = AC * M[MA]
56 DIV AC, IO = AC'IO / M[MA]
60 JMP PC = MA
62 JSP AC = PC, PC = MA
Memory reference instructions can access an address space of 64K words.
The address space is divided into sixteen 4K word fields. An
instruction can directly address, via its 12b address, the entire
current field. If extend mode is off, indirect addresses access
the current field, and indirect addressing is multi-level; if off,
they can access all 64K, and indirect addressing is single level.
*/
/* The skip format is:
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
| 1 1 0 1 0| | | | | | | | | | | | | | skip
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
| | | | | | \______/ \______/
| | | | | | | |
| | | | | | | +---- program flags
| | | | | | +------------- sense switches
| | | | | +------------------- AC == 0
| | | | +---------------------- AC >= 0
| | | +------------------------- AC < 0
| | +---------------------------- OV == 0
| +------------------------------- IO >= 0
+------------------------------------- invert skip
The shift format is:
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
| 1 1 0 1 1| subopcode | encoded count | shift
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
The load immediate format is:
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
| 1 1 1 0 0| S| immediate | LAW
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
<0:4> mnemonic action
70 LAW if S = 0, AC = IR<6:17>
else AC = ~IR<6:17>
*/
/* The I/O transfer format is:
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
| 1 1 1 0 1| W| C| subopcode | device | I/O transfer
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
The IO transfer instruction sends the the specified subopcode to
specified I/O device. The I/O device may take data from the IO or
return data to the IO, initiate or cancel operations, etc. The
W bit specifies whether the CPU waits for completion, the C bit
whether a completion pulse will be returned from the device.
The operate format is:
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
| 1 1 1 1 1| | | | | | | | | | | | | | operate
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
| | | | | | | \______/
| | | | | | | |
| | | | | | | +---- PF select
| | | | | | +---------- clear/set PF
| | | | | +------------------- or PC
| | | | +---------------------- clear AC
| | | +------------------------- halt
| | +---------------------------- CMA
| +------------------------------- or TW
+---------------------------------- clear IO
The operate instruction can be microprogrammed.
*/
/* This routine is the instruction decode routine for the PDP-1.
It is called from the simulator control program to execute
instructions in simulated memory, starting at the simulated PC.
It runs until 'reason' is set non-zero.
General notes:
1. Reasons to stop. The simulator can be stopped by:
HALT instruction
breakpoint encountered
unimplemented instruction and STOP_INST flag set
XCT loop
indirect address loop
infinite wait state
I/O error in I/O simulator
2. Interrupts. With a single channel sequence break system, the
PDP-1 has a single break request (flop b2, here sbs<SB_V_RQ>).
If sequence breaks are enabled (flop sbm, here sbs<SB_V_ON>),
and one is not already in progress (flop b4, here sbs<SB_V_IP>),
a sequence break occurs.
3. Arithmetic. The PDP-1 is a 1's complement system. In 1's
complement arithmetic, a negative number is represented by the
complement (XOR 0777777) of its absolute value. Addition of 1's
complement numbers requires propagating the carry out of the high
order bit back to the low order bit.
4. Adding I/O devices. Three modules must be modified:
pdp1_defs.h add interrupt request definition
pdp1_cpu.c add IOT dispatch code
pdp1_sys.c add sim_devices table entry
*/
#include "pdp1_defs.h"
#define PCQ_SIZE 64 /* must be 2**n */
#define PCQ_MASK (PCQ_SIZE - 1)
#define PCQ_ENTRY pcq[pcq_p = (pcq_p - 1) & PCQ_MASK] = PC
#define UNIT_V_MDV (UNIT_V_UF + 0) /* mul/div */
#define UNIT_V_MSIZE (UNIT_V_UF + 1) /* dummy mask */
#define UNIT_MDV (1 << UNIT_V_MDV)
#define UNIT_MSIZE (1 << UNIT_V_MSIZE)
int32 M[MAXMEMSIZE] = { 0 }; /* memory */
int32 AC = 0; /* AC */
int32 IO = 0; /* IO */
int32 PC = 0; /* PC */
int32 OV = 0; /* overflow */
int32 SS = 0; /* sense switches */
int32 PF = 0; /* program flags */
int32 TW = 0; /* test word */
int32 iosta = 0; /* status reg */
int32 sbs = 0; /* sequence break */
int32 sbs_init = 0; /* seq break startup */
int32 ioh = 0; /* I/O halt */
int32 ioc = 0; /* I/O completion */
int32 extm = 0; /* ext mem mode */
int32 extm_init = 0; /* ext mem startup */
int32 stop_inst = 0; /* stop on rsrv inst */
int32 xct_max = 16; /* nested XCT limit */
int32 ind_max = 16; /* nested ind limit */
uint16 pcq[PCQ_SIZE] = { 0 }; /* PC queue */
int32 pcq_p = 0; /* PC queue ptr */
REG *pcq_r = NULL; /* PC queue reg ptr */
extern UNIT *sim_clock_queue;
extern int32 sim_int_char;
extern int32 sim_brk_types, sim_brk_dflt, sim_brk_summ; /* breakpoint info */
t_stat cpu_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw);
t_stat cpu_dep (t_value val, t_addr addr, UNIT *uptr, int32 sw);
t_stat cpu_reset (DEVICE *dptr);
t_stat cpu_set_size (UNIT *uptr, int32 val, char *cptr, void *desc);
extern int32 ptr (int32 inst, int32 dev, int32 IO);
extern int32 ptp (int32 inst, int32 dev, int32 IO);
extern int32 tti (int32 inst, int32 dev, int32 IO);
extern int32 tto (int32 inst, int32 dev, int32 IO);
extern int32 lpt (int32 inst, int32 dev, int32 IO);
extern int32 dt (int32 inst, int32 dev, int32 IO);
int32 sc_map[512] = {
0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4, /* 00000xxxx */
1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, /* 00001xxxx */
1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, /* 00010xxxx */
2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, /* 00011xxxx */
1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, /* 00100xxxx */
2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, /* 00101xxxx */
2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, /* 00110xxxx */
3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, /* 00111xxxx */
1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, /* 01000xxxx */
2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, /* 01001xxxx */
2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, /* 01010xxxx */
3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, /* 01011xxxx */
2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, /* 01100xxxx */
3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, /* 01101xxxx */
3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, /* 01110xxxx */
4, 5, 5, 6, 5, 6, 6, 7, 5, 6, 6, 7, 6, 7, 7, 8, /* 01111xxxx */
1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, /* 10000xxxx */
2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, /* 10001xxxx */
2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, /* 10010xxxx */
3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, /* 10011xxxx */
2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, /* 10100xxxx */
3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, /* 10101xxxx */
3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, /* 10110xxxx */
4, 5, 5, 6, 5, 6, 6, 7, 5, 6, 6, 7, 6, 7, 7, 8, /* 11011xxxx */
2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, /* 11000xxxx */
3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, /* 11001xxxx */
3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, /* 11010xxxx */
4, 5, 5, 6, 5, 6, 6, 7, 5, 6, 6, 7, 6, 7, 7, 8, /* 11011xxxx */
3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, /* 11100xxxx */
4, 5, 5, 6, 5, 6, 6, 7, 5, 6, 6, 7, 6, 7, 7, 8, /* 11101xxxx */
4, 5, 5, 6, 5, 6, 6, 7, 5, 6, 6, 7, 6, 7, 7, 8, /* 11110xxxx */
5, 6, 6, 7, 6, 7, 7, 8, 6, 7, 7, 8, 7, 8, 8, 9 /* 11111xxxx */
};
/* CPU data structures
cpu_dev CPU device descriptor
cpu_unit CPU unit
cpu_reg CPU register list
cpu_mod CPU modifier list
*/
UNIT cpu_unit = { UDATA (NULL, UNIT_FIX + UNIT_BINK, MAXMEMSIZE) };
REG cpu_reg[] = {
{ ORDATA (PC, PC, ASIZE) },
{ ORDATA (AC, AC, 18) },
{ ORDATA (IO, IO, 18) },
{ FLDATA (OV, OV, 0) },
{ ORDATA (PF, PF, 6) },
{ ORDATA (SS, SS, 6) },
{ ORDATA (TW, TW, 18) },
{ FLDATA (EXTM, extm, 0) },
{ ORDATA (IOSTA, iosta, 18), REG_RO },
{ FLDATA (SBON, sbs, SB_V_ON) },
{ FLDATA (SBRQ, sbs, SB_V_RQ) },
{ FLDATA (SBIP, sbs, SB_V_IP) },
{ FLDATA (IOH, ioh, 0) },
{ FLDATA (IOC, ioc, 0) },
{ BRDATA (PCQ, pcq, 8, ASIZE, PCQ_SIZE), REG_RO+REG_CIRC },
{ ORDATA (PCQP, pcq_p, 6), REG_HRO },
{ FLDATA (STOP_INST, stop_inst, 0) },
{ FLDATA (SBS_INIT, sbs_init, SB_V_ON) },
{ FLDATA (EXTM_INIT, extm_init, 0) },
{ DRDATA (XCT_MAX, xct_max, 8), PV_LEFT + REG_NZ },
{ DRDATA (IND_MAX, ind_max, 8), PV_LEFT + REG_NZ },
{ ORDATA (WRU, sim_int_char, 8) },
{ NULL } };
MTAB cpu_mod[] = {
{ UNIT_MDV, UNIT_MDV, "multiply/divide", "MDV", NULL },
{ UNIT_MDV, 0, "no multiply/divide", "NOMDV", NULL },
{ UNIT_MSIZE, 4096, NULL, "4K", &cpu_set_size },
{ UNIT_MSIZE, 8192, NULL, "8K", &cpu_set_size },
{ UNIT_MSIZE, 12288, NULL, "12K", &cpu_set_size },
{ UNIT_MSIZE, 16384, NULL, "16K", &cpu_set_size },
{ UNIT_MSIZE, 20480, NULL, "20K", &cpu_set_size },
{ UNIT_MSIZE, 24576, NULL, "24K", &cpu_set_size },
{ UNIT_MSIZE, 28672, NULL, "28K", &cpu_set_size },
{ UNIT_MSIZE, 32768, NULL, "32K", &cpu_set_size },
{ UNIT_MSIZE, 49152, NULL, "48K", &cpu_set_size },
{ UNIT_MSIZE, 65536, NULL, "64K", &cpu_set_size },
{ 0 } };
DEVICE cpu_dev = {
"CPU", &cpu_unit, cpu_reg, cpu_mod,
1, 8, ASIZE, 1, 8, 18,
&cpu_ex, &cpu_dep, &cpu_reset,
NULL, NULL, NULL,
NULL, 0 };
t_stat sim_instr (void)
{
extern int32 sim_interval;
int32 IR, MA, op, i, t, xct_count;
int32 sign, signd, v;
int32 dev, io_data, sc, skip;
t_stat reason;
static int32 fs_test[8] = {
0, 040, 020, 010, 04, 02, 01, 077 };
#define EPC_WORD ((OV << 17) | (extm << 16) | PC)
#define INCR_ADDR(x) (((x) & EPCMASK) | (((x) + 1) & DAMASK))
#define DECR_ADDR(x) (((x) & EPCMASK) | (((x) - 1) & DAMASK))
#define ABS(x) ((x) ^ (((x) & 0400000)? 0777777: 0))
/* Main instruction fetch/decode loop: check events and interrupts */
reason = 0;
while (reason == 0) { /* loop until halted */
if (sim_interval <= 0) { /* check clock queue */
if (reason = sim_process_event ()) break; }
if (sbs == (SB_ON | SB_RQ)) { /* interrupt? */
sbs = SB_ON | SB_IP; /* set in prog flag */
PCQ_ENTRY; /* save old PC */
M[0] = AC; /* save state */
M[1] = EPC_WORD;
M[2] = IO;
PC = 3; /* fetch next from 3 */
extm = 0; /* extend off */
OV = 0; } /* clear overflow */
if (sim_brk_summ && sim_brk_test (PC, SWMASK ('E'))) { /* breakpoint? */
reason = STOP_IBKPT; /* stop simulation */
break; }
/* Fetch, decode instruction */
MA = PC; /* PC to MA */
IR = M[MA]; /* fetch instruction */
PC = INCR_ADDR (PC); /* increment PC */
xct_count = 0; /* track nested XCT's */
sim_interval = sim_interval - 1;
xct_instr: /* label for XCT */
if ((IR == 0610001) && ((MA & EPCMASK) == 0) && (sbs & SB_ON)) {
sbs = sbs & ~SB_IP; /* seq debreak */
PCQ_ENTRY; /* save old PC */
OV = (M[1] >> 17) & 1; /* restore OV */
extm = (M[1] >> 16) & 1; /* restore ext mode */
PC = M[1] & AMASK; /* JMP I 1 */
continue; }
op = ((IR >> 13) & 037); /* get opcode */
if ((op < 032) && (op != 007)) { /* mem ref instr */
MA = (MA & EPCMASK) | (IR & DAMASK); /* direct address */
if (IR & IA) { /* indirect addr? */
if (extm) MA = M[MA] & AMASK; /* if ext, one level */
else { for (i = 0; i < ind_max; i++) { /* count indirects */
t = M[MA]; /* get indirect word */
MA = (MA & EPCMASK) | (t & DAMASK);
if ((t & IA) == 0) break; }
if (i >= ind_max) { /* indirect loop? */
reason = STOP_IND;
break; } } } }
switch (op) { /* decode IR<0:4> */
/* Logical, load, store instructions */
case 001: /* AND */
AC = AC & M[MA];
break;
case 002: /* IOR */
AC = AC | M[MA];
break;
case 003: /* XOR */
AC = AC ^ M[MA];
break;
case 004: /* XCT */
if (xct_count >= xct_max) { /* too many XCT's? */
reason = STOP_XCT;
break; }
xct_count = xct_count + 1; /* count XCT's */
IR = M[MA]; /* get instruction */
goto xct_instr; /* go execute */
case 007: /* CAL, JDA */
MA = (PC & EPCMASK) | ((IR & IA)? (IR & DAMASK): 0100);
PCQ_ENTRY;
M[MA] = AC;
AC = EPC_WORD;
PC = INCR_ADDR (MA);
break;
case 010: /* LAC */
AC = M[MA];
break;
case 011: /* LIO */
IO = M[MA];
break;
case 012: /* DAC */
if (MEM_ADDR_OK (MA)) M[MA] = AC;
break;
case 013: /* DAP */
if (MEM_ADDR_OK (MA)) M[MA] = (AC & DAMASK) | (M[MA] & ~DAMASK);
break;
case 014: /* DIP */
if (MEM_ADDR_OK (MA)) M[MA] = (AC & ~DAMASK) | (M[MA] & DAMASK);
break;
case 015: /* DIO */
if (MEM_ADDR_OK (MA)) M[MA] = IO;
break;
case 016: /* DZM */
if (MEM_ADDR_OK (MA)) M[MA] = 0;
break;
/* Add, subtract, control
Add is performed in sequential steps, as follows:
1. add
2. end around carry propagate
3. overflow check
4. -0 cleanup
Subtract is performed in sequential steps, as follows:
1. complement AC
2. add
3. end around carry propagate
4. overflow check
5. complement AC
Because no -0 check is done, (-0) - (+0) yields a result of -0
*/
case 020: /* ADD */
t = AC;
AC = AC + M[MA];
if (AC > 0777777) AC = (AC + 1) & 0777777; /* end around carry */
if (((~t ^ M[MA]) & (t ^ AC)) & 0400000) OV = 1;
if (AC == 0777777) AC = 0; /* minus 0 cleanup */
break;
case 021: /* SUB */
t = AC ^ 0777777; /* complement AC */
AC = t + M[MA]; /* -AC + MB */
if (AC > 0777777) AC = (AC + 1) & 0777777; /* end around carry */
if (((~t ^ M[MA]) & (t ^ AC)) & 0400000) OV = 1;
AC = AC ^ 0777777; /* recomplement AC */
break;
case 022: /* IDX */
AC = M[MA] + 1;
if (AC >= 0777777) AC = (AC + 1) & 0777777;
if (MEM_ADDR_OK (MA)) M[MA] = AC;
break;
case 023: /* ISP */
AC = M[MA] + 1;
if (AC >= 0777777) AC = (AC + 1) & 0777777;
if (MEM_ADDR_OK (MA)) M[MA] = AC;
if (AC < 0400000) PC = INCR_ADDR (PC);
break;
case 024: /* SAD */
if (AC != M[MA]) PC = INCR_ADDR (PC);
break;
case 025: /* SAS */
if (AC == M[MA]) PC = INCR_ADDR (PC);
break;
case 030: /* JMP */
PCQ_ENTRY;
PC = MA;
break;
case 031: /* JSP */
AC = EPC_WORD;
PCQ_ENTRY;
PC = MA;
break;
case 034: /* LAW */
AC = (IR & 07777) ^ ((IR & IA)? 0777777: 0);
break;
/* Multiply and divide
Multiply and divide step and hardware multiply are exact implementations.
Hardware divide is a 2's complement analog to the actual hardware.
*/
case 026: /* MUL */
if (cpu_unit.flags & UNIT_MDV) { /* hardware? */
sign = AC ^ M[MA]; /* result sign */
IO = ABS (AC); /* IO = |AC| */
v = ABS (M[MA]); /* v = |mpy| */
for (i = AC = 0; i < 17; i++) {
if (IO & 1) AC = AC + v;
IO = (IO >> 1) | ((AC & 1) << 17);
AC = AC >> 1; }
if ((sign & 0400000) && (AC | IO)) { /* negative, > 0? */
AC = AC ^ 0777777;
IO = IO ^ 0777777; } }
else { if (IO & 1) AC = AC + M[MA]; /* multiply step */
if (AC > 0777777) AC = (AC + 1) & 0777777;
if (AC == 0777777) AC = 0;
IO = (IO >> 1) | ((AC & 1) << 17);
AC = AC >> 1; }
break;
case 027: /* DIV */
if (cpu_unit.flags & UNIT_MDV) { /* hardware */
sign = AC ^ M[MA]; /* result sign */
signd = AC; /* remainder sign */
if (AC & 0400000) {
AC = AC ^ 0777777; /* AC'IO = |AC'IO| */
IO = IO ^ 0777777; }
v = ABS (M[MA]); /* v = |divr| */
if (AC >= v) break; /* overflow? */
for (i = t = 0; i < 18; i++) {
if (t) AC = (AC + v) & 0777777;
else AC = (AC - v) & 0777777;
t = AC >> 17;
if (i != 17) AC = ((AC << 1) | (IO >> 17)) & 0777777;
IO = ((IO << 1) | (t ^ 1)) & 0777777; }
if (t) AC = (AC + v) & 0777777; /* correct remainder */
t = ((signd & 0400000) && AC)? AC ^ 0777777: AC;
AC = ((sign & 0400000) && IO)? IO ^ 0777777: IO;
IO = t;
PC = INCR_ADDR (PC); } /* skip */
else { t = AC >> 17; /* divide step */
AC = ((AC << 1) | (IO >> 17)) & 0777777;
IO = ((IO << 1) | (t ^ 1)) & 0777777;
if (IO & 1) AC = AC + (M[MA] ^ 0777777);
else AC = AC + M[MA] + 1;
if (AC > 0777777) AC = (AC + 1) & 0777777;
if (AC == 0777777) AC = 0; }
break;
/* Skip and operate
Operates execute in the order shown; there are no timing conflicts
*/
case 032: /* skip */
v = (IR >> 3) & 07; /* sense switches */
t = IR & 07; /* program flags */
skip = (((IR & 02000) && (IO < 0400000)) || /* SPI */
((IR & 01000) && (OV == 0)) || /* SZO */
((IR & 00400) && (AC >= 0400000)) || /* SMA */
((IR & 00200) && (AC < 0400000)) || /* SPA */
((IR & 00100) && (AC == 0)) || /* SZA */
(v && ((SS & fs_test[v]) == 0)) || /* SZSn */
(t && ((PF & fs_test[t]) == 0))); /* SZFn */
if (IR & IA) skip = skip ^ 1; /* invert skip? */
if (skip) PC = INCR_ADDR (PC);
if (IR & 01000) OV = 0; /* SOV clears OV */
break;
case 037: /* operate */
if (IR & 04000) IO = 0; /* CLI */
if (IR & 00200) AC = 0; /* CLA */
if (IR & 02000) AC = AC | TW; /* LAT */
if (IR & 00100) AC = AC | EPC_WORD; /* LAP */
if (IR & 01000) AC = AC ^ 0777777; /* CMA */
if (IR & 00400) reason = STOP_HALT; /* HALT */
t = IR & 07; /* flag select */
if (IR & 010) PF = PF | fs_test[t]; /* STFn */
else PF = PF & ~fs_test[t]; /* CLFn */
break;
/* Shifts */
case 033:
sc = sc_map[IR & 0777]; /* map shift count */
switch ((IR >> 9) & 017) { /* case on IR<5:8> */
case 001: /* RAL */
AC = ((AC << sc) | (AC >> (18 - sc))) & 0777777;
break;
case 002: /* RIL */
IO = ((IO << sc) | (IO >> (18 - sc))) & 0777777;
break;
case 003: /* RCL */
t = AC;
AC = ((AC << sc) | (IO >> (18 - sc))) & 0777777;
IO = ((IO << sc) | (t >> (18 - sc))) & 0777777;
break;
case 005: /* SAL */
t = (AC & 0400000)? 0777777: 0;
AC = (AC & 0400000) | ((AC << sc) & 0377777) |
(t >> (18 - sc));
break;
case 006: /* SIL */
t = (IO & 0400000)? 0777777: 0;
IO = (IO & 0400000) | ((IO << sc) & 0377777) |
(t >> (18 - sc));
break;
case 007: /* SCL */
t = (AC & 0400000)? 0777777: 0;
AC = (AC & 0400000) | ((AC << sc) & 0377777) |
(IO >> (18 - sc));
IO = ((IO << sc) | (t >> (18 - sc))) & 0777777;
break;
case 011: /* RAR */
AC = ((AC >> sc) | (AC << (18 - sc))) & 0777777;
break;
case 012: /* RIR */
IO = ((IO >> sc) | (IO << (18 - sc))) & 0777777;
break;
case 013: /* RCR */
t = IO;
IO = ((IO >> sc) | (AC << (18 - sc))) & 0777777;
AC = ((AC >> sc) | (t << (18 - sc))) & 0777777;
break;
case 015: /* SAR */
t = (AC & 0400000)? 0777777: 0;
AC = ((AC >> sc) | (t << (18 - sc))) & 0777777;
break;
case 016: /* SIR */
t = (IO & 0400000)? 0777777: 0;
IO = ((IO >> sc) | (t << (18 - sc))) & 0777777;
break;
case 017: /* SCR */
t = (AC & 0400000)? 0777777: 0;
IO = ((IO >> sc) | (AC << (18 - sc))) & 0777777;
AC = ((AC >> sc) | (t << (18 - sc))) & 0777777;
break;
default: /* undefined */
reason = stop_inst;
break; } /* end switch shifts */
break;
/* IOT */
case 035:
if (IR & IO_WAIT) { /* wait? */
if (ioh) { /* I/O halt? */
if (ioc) ioh = 0; /* comp pulse? done */
else { sim_interval = 0; /* force event */
PC = DECR_ADDR (PC); } /* re-execute */
break; } /* skip iot */
ioh = 1; /* turn on halt */
PC = DECR_ADDR (PC); } /* re-execute */
dev = IR & 077; /* get dev addr */
io_data = IO; /* default data */
switch (dev) { /* case on dev */
case 000: /* I/O wait */
break;
case 001:
if (IR & 003700) io_data = dt (IR, dev, IO); /* DECtape */
else io_data = ptr (IR, dev, IO); /* paper tape rdr */
break;
case 002: case 030: /* paper tape rdr */
io_data = ptr (IR, dev, IO);
break;
case 003: /* typewriter */
io_data = tto (IR, dev, IO);
break;
case 004: /* keyboard */
io_data = tti (IR, dev, IO);
break;
case 005: case 006: /* paper tape punch */
io_data = ptp (IR, dev, IO);
break;
case 033: /* check status */
io_data = iosta | ((sbs & SB_ON)? IOS_SQB: 0);
break;
case 045: /* line printer */
io_data = lpt (IR, dev, IO);
break;
case 054: /* seq brk off */
sbs = sbs & ~SB_ON;
break;
case 055: /* seq brk on */
sbs = sbs | SB_ON;
break;
case 056: /* clear seq brk */
sbs = sbs & ~SB_IP;
break;
case 074: /* extend mode */
extm = (IR >> 11) & 1; /* set from IR<6> */
break;
default: /* undefined */
reason = stop_inst;
break; } /* end switch dev */
IO = io_data & 0777777;
if (io_data >= IOT_REASON) reason = io_data >> IOT_V_REASON;
break;
default: /* undefined */
reason = STOP_RSRV; /* halt */
break; } /* end switch opcode */
} /* end while */
pcq_r->qptr = pcq_p; /* update pc q ptr */
return reason;
}
/* Reset routine */
t_stat cpu_reset (DEVICE *dptr)
{
sbs = sbs_init;
extm = extm_init;
ioh = ioc = 0;
OV = 0;
PF = 0;
pcq_r = find_reg ("PCQ", NULL, dptr);
if (pcq_r) pcq_r->qptr = 0;
else return SCPE_IERR;
sim_brk_types = sim_brk_dflt = SWMASK ('E');
return SCPE_OK;
}
/* Memory examine */
t_stat cpu_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw)
{
if (addr >= MEMSIZE) return SCPE_NXM;
if (vptr != NULL) *vptr = M[addr] & 0777777;
return SCPE_OK;
}
/* Memory deposit */
t_stat cpu_dep (t_value val, t_addr addr, UNIT *uptr, int32 sw)
{
if (addr >= MEMSIZE) return SCPE_NXM;
M[addr] = val & 0777777;
return SCPE_OK;
}
/* Change memory size */
t_stat cpu_set_size (UNIT *uptr, int32 val, char *cptr, void *desc)
{
int32 mc = 0;
t_addr i;
if ((val <= 0) || (val > MAXMEMSIZE) || ((val & 07777) != 0))
return SCPE_ARG;
for (i = val; i < MEMSIZE; i++) mc = mc | M[i];
if ((mc != 0) && (!get_yn ("Really truncate memory [N]?", FALSE)))
return SCPE_OK;
MEMSIZE = val;
for (i = MEMSIZE; i < MAXMEMSIZE; i++) M[i] = 0;
return SCPE_OK;
}

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/* pdp1_defs.h: 18b PDP simulator definitions
Copyright (c) 1993-2002, Robert M. Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
Except as contained in this notice, the name of Robert M Supnik shall not
be used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Robert M Supnik.
14-Apr-99 RMS Changed t_addr to unsigned
The PDP-1 was Digital's first computer. The system design evolved during
its life, and as a result, specifications are sketchy or contradictory.
This simulator is based on the 1962 maintenance manual.
This simulator implements the following options:
Automatic multiply/divide Type 10
Memory extension control Type 15
Line printer control Type 62
*/
#include "sim_defs.h"
/* Simulator stop codes */
#define STOP_RSRV 1 /* must be 1 */
#define STOP_HALT 2 /* HALT */
#define STOP_IBKPT 3 /* breakpoint */
#define STOP_XCT 4 /* nested XCT's */
#define STOP_IND 5 /* nested indirects */
#define STOP_WAIT 6 /* wait state */
/* Memory */
#define ASIZE 16 /* address bits */
#define MAXMEMSIZE (1u << ASIZE) /* max mem size */
#define AMASK (MAXMEMSIZE - 1) /* address mask */
#define MEMSIZE (cpu_unit.capac) /* actual memory size */
#define MEM_ADDR_OK(x) (((t_addr) (x)) < MEMSIZE)
/* Architectural constants */
#define DMASK 0777777 /* data mask */
#define DAMASK 007777 /* direct addr */
#define EPCMASK (AMASK & ~DAMASK) /* extended addr */
#define IA 010000 /* indirect flag */
#define IO_WAIT 010000 /* I/O sync wait */
#define IO_CPLS 004000 /* completion pulse */
#define GEN_CPLS(x) (((x) ^ ((x) << 1)) & IO_WAIT) /* completion pulse? */
/* IOT subroutine return codes */
#define IOT_V_REASON 18 /* reason */
#define IOT_REASON (1 << IOT_V_REASON)
#define IORETURN(f,v) ((f)? (v): SCPE_OK) /* stop on error */
/* I/O status flags */
#define IOS_V_LPN 17 /* light pen */
#define IOS_V_PTR 16 /* paper tape reader */
#define IOS_V_TTO 15 /* typewriter out */
#define IOS_V_TTI 14 /* typewriter in */
#define IOS_V_PTP 13 /* paper tape punch */
#define IOS_V_DRM 12 /* drum */
#define IOS_V_SQB 11 /* sequence break */
#define IOS_V_PNT 2 /* print done */
#define IOS_V_SPC 1 /* space done */
#define IOS_LPN (1 << IOS_V_LPN)
#define IOS_PTR (1 << IOS_V_PTR)
#define IOS_TTO (1 << IOS_V_TTO)
#define IOS_TTI (1 << IOS_V_TTI)
#define IOS_PTP (1 << IOS_V_PTP)
#define IOS_DRM (1 << IOS_V_DRM)
#define IOS_SQB (1 << IOS_V_SQB)
#define IOS_PNT (1 << IOS_V_PNT)
#define IOS_SPC (1 << IOS_V_SPC)
/* Sequence break flags */
#define SB_V_IP 0 /* in progress */
#define SB_V_RQ 1 /* request */
#define SB_V_ON 2 /* enabled */
#define SB_IP (1 << SB_V_IP)
#define SB_RQ (1 << SB_V_RQ)
#define SB_ON (1 << SB_V_ON)

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To: Users
From: Bob Supnik
Subj: PDP-1 Simulator Usage
Date: 15-Nov-2002
COPYRIGHT NOTICE
The following copyright notice applies to both the SIMH source and binary:
Original code published in 1993-2002, written by Robert M Supnik
Copyright (c) 1993-2002, Robert M Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
Except as contained in this notice, the name of Robert M Supnik shall not
be used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Robert M Supnik.
This memorandum documents the PDP-1 simulator.
1. Simulator Files
sim/ sim_defs.h
sim_rev.h
sim_sock.h
sim_tmxr.h
scp.c
scp_tty.c
sim_sock.c
sim_tmxr.c
sim/pdp1/ pdp1_defs.h
pdp1_cpu.c
pdp1_dt.c
pdp1_lp.c
pdp1_stddev.c
pdp1_sys.c
2. PDP-1 Features
The PDP-1 is configured as follows:
device simulates
name(s)
CPU PDP-1 CPU with up to 64KW of memory
PTR,PTP integral paper tape reader/punch
TTI,TTO Flexowriter typewriter input/output
LPT Type 62 line printer
DT Type 550 Microtape (DECtape)
The PDP-1 simulator implements the following unique stop conditions:
- an unimplemented instruction is decoded, and register
STOP_INST is set
- more than INDMAX indirect addresses are detected during
memory reference address decoding
- more than XCTMAX nested executes are detected during
instruction execution
- wait state entered, and no I/O operations outstanding
(ie, no interrupt can ever occur)
The PDP-1 loader supports RIM format tapes. The DUMP command is not
implemented.
2.1 CPU
The only CPU options are the presence of hardware multiply/divide and the
size of main memory.
SET CPU MDV enable multiply/divide
SET CPU NOMDV disable multiply/divide
SET CPU 4K set memory size = 4K
SET CPU 8K set memory size = 8K
SET CPU 12K set memory size = 12K
SET CPU 16K set memory size = 16K
SET CPU 20K set memory size = 20K
SET CPU 24K set memory size = 24K
SET CPU 28K set memory size = 28K
SET CPU 32K set memory size = 32K
SET CPU 48K set memory size = 48K
SET CPU 64K set memory size = 64K
If memory size is being reduced, and the memory being truncated contains
non-zero data, the simulator asks for confirmation. Data in the truncated
portion of memory is lost. Initial memory size is 64K.
CPU registers include the visible state of the processor as well as the
control registers for the interrupt system.
name size comments
PC 16 program counter
AC 18 accumulator
IO 18 IO register
OV 1 overflow flag
PF 6 program flags<1:6>
SS 6 sense switches<1:6>
TW 18 test word (front panel switches)
EXTM 1 extend mode
IOSTA 18 IO status register
SBON 1 sequence break enable
SBRQ 1 sequence break request
SBIP 1 sequence break in progress
IOH 1 I/O halt in progress
IOC 1 I/O continue
PCQ[0:63] 16 PC prior to last jump or interrupt;
most recent PC change first
STOP_INST 1 stop on undefined instruction
SBS_INIT 1 initial state of sequence break enable
EXTM_INIT 1 initial state of extend mode
WRU 8 interrupt character
2.2 Programmed I/O Devices
2.2.1 Paper Tape Reader (PTR)
The paper tape reader (PTR) reads data from or a disk file. The POS
register specifies the number of the next data item to be read. Thus,
by changing POS, the user can backspace or advance the reader.
The paper tape reader supports the BOOT command. BOOT PTR copies the
RIM loader into memory and starts it running.
The paper tape reader implements these registers:
name size comments
BUF 8 last data item processed
DONE 1 device done flag
RPLS 1 return restart pulse flag
POS 32 position in the input file
TIME 24 time from I/O initiation to interrupt
STOP_IOE 1 stop on I/O error
Error handling is as follows:
error STOP_IOE processed as
not attached 1 report error and stop
0 out of tape
end of file 1 report error and stop
0 out of tape
OS I/O error x report error and stop
2.2.2 Paper Tape Punch (PTP)
The paper tape punch (PTP) writes data to a disk file. The POS
register specifies the number of the next data item to be written.
Thus, by changing POS, the user can backspace or advance the punch.
The paper tape punch implements these registers:
name size comments
BUF 8 last data item processed
DONE 1 device done flag
RPLS 1 return restart pulse flag
POS 32 position in the output file
TIME 24 time from I/O initiation to interrupt
STOP_IOE 1 stop on I/O error
Error handling is as follows:
error STOP_IOE processed as
not attached 1 report error and stop
0 out of tape
OS I/O error x report error and stop
2.2.3 Terminal Input (TTI)
The terminal input (TTI) polls the console keyboard for input. It
implements these registers:
name size comments
BUF 8 last data item processed
DONE 1 device done flag
POS 32 number of characters input
TIME 24 keyboard polling interval
2.2.4 Terminal Output (TTO)
The terminal output (TTO) writes to the simulator console window.
It implements these registers:
name size comments
BUF 8 last data item processed
DONE 1 device done flag
RPLS 1 return restart pulse flag
POS 32 number of characters output
TIME 24 time from I/O initiation to interrupt
2.2.5 Type 62 Line Printer (LPT)
The paper line printer (LPT) writes data to a disk file. The POS
register specifies the number of the next data item to be written.
Thus, by changing POS, the user can backspace or advance the printer.
The line printer can be disabled and enabled with the SET LPT DISABLED
and SET LPT ENABLED commands, respectively.
The line printer implements these registers:
name size comments
BUF 8 last data item processed
PNT 1 printing done flag
SPC 1 spacing done flag
RPLS 1 return restart pulse flag
BPTR 6 print buffer pointer
POS 32 position in the output file
TIME 24 time from I/O initiation to interrupt
STOP_IOE 1 stop on I/O error
LBUF[0:119] 8 line buffer
Error handling is as follows:
error STOP_IOE processed as
not attached 1 report error and stop
0 out of tape or paper
OS I/O error x report error and stop
2.3 Type 550/555 Microtape (DECtape) (DT)
The PDP-1 used the Type 550 Microtape (later renamed DECtape), a programmed
I/O controller. PDP-1 DECtape format had 4 18b words in its block headers
and trailers.
DECtapes drives are numbered 1-8; in the simulator, drive 8 is unit 0.
DECtape options include the ability to make units write enabled or write
locked.
SET DTn WRITEENABLED set unit n write enabled
SET DTn LOCKED set unit n write locked
Units can also be set ONLINE or OFFLINE.
The DECtape controller can be disabled and enabled with the SET DT DISABLED
and SET DT ENABLED commands, respectively.
The Type 550 supports PDP-8 format, PDP-11 format, and 18b format DECtape
images. ATTACH tries to determine the tape format from the DECtape image;
the user can force a particular format with switches:
-r PDP-8 format
-s PDP-11 format
-t 18b format
The DECtape controller is a data-only simulator; the timing and mark
track, and block header and trailer, are not stored. Thus, the WRITE
TIMING AND MARK TRACK function is not supported; the READ ALL function
always returns the hardware standard block header and trailer; and the
WRITE ALL function dumps non-data words into the bit bucket.
The DECtape controller implements these registers:
name size comments
DTSA 12 status register A
DTSB 12 status register B
DTDB 18 data buffer
DTF 1 DECtape flag
BEF 1 block end flag
ERF 1 error flag
LTIME 31 time between lines
ACTIME 31 time to accelerate to full speed
DCTIME 31 time to decelerate to a full stop
SUBSTATE 2 read/write command substate
POS[0:7] 32 position, in lines, units 0-7
STATT[0:7] 18 unit state, units 0-7
It is critically important to maintain certain timing relationships
among the DECtape parameters, or the DECtape simulator will fail to
operate correctly.
- LTIME must be at least 6
- ACTIME must be less than DCTIME, and both need to be at
least 100 times LTIME
2.4 Symbolic Display and Input
The PDP-1 simulator implements symbolic display and input. Display is
controlled by command line switches:
-a display as ASCII character
-c display as FIODEC character string
-m display instruction mnemonics
Input parsing is controlled by the first character typed in or by command
line switches:
' or -a ASCII character
" or -c three character FIODEC string
alphabetic instruction mnemonic
numeric octal number
Instruction input uses modified PDP-1 assembler syntax. There are six
instruction classes: memory reference, shift, skip, operate, IOT, and
LAW.
Memory reference instructions have the format
memref {I} address
where I signifies indirect reference. The address is an octal number in
the range 0 - 0177777.
Shift instructions have the format
shift shift_count
The shift count is an octal number in the range 0-9.
Skip instructions consist of single mnemonics, eg, SZA, SZS4. Skip
instructions may be or'd together
skip skip skip...
The sense of a skip can be inverted by including the mnemonic I.
Operate instructions consist of single mnemonics, eg, CLA, CLI. Operate
instructions may be or'd together
opr opr opr...
IOT instructions consist of single mnemonics, eg, TYI, TYO. IOT
instructions may include an octal numeric modifier or the modifier I:
iot modifier
The simulator does not check the legality of skip, operate, or IOT
combinations.
Finally, the LAW instruction has the format
LAW {I} immediate
where immediate is in the range 0 to 07777.
2.5 Character Sets
The PDP-1's console was a Frieden Flexowriter; its character encoding
was known as FIODEC. The PDP-1's line printer used a modified Hollerith
character set. The following table provides equivalences between ASCII
characters and the PDP-1's I/O devices. In the console table, UC stands
for upper case.
PDP-1 PDP-1
ASCII console line printer
000 - 007 none none
bs 075 none
tab 036 none
012 - 014 none none
cr 077 none
016 - 037 none none
space 000 000
! {OR} UC+005 none
" UC+001 none
# {IMPLIES} UC+004 none
$ none none
% none none
& {AND} UC+006 none
' UC+002 none
( 057 057
) 055 055
* {TIMES} UC+073 072
+ UC+054 074
, 033 033
- 054 054
. 073 073
/ 021 021
0 020 020
1 001 001
2 002 002
3 003 003
4 004 004
5 005 005
6 006 006
7 007 007
8 010 010
9 011 011
: none none
; none none
< UC+007 034
= UC+033 053
> UC+010 034
? UC+021 037
@ {MID DOT} 040 {MID DOT} 040
A UC+061 061
B UC+062 062
C UC+063 063
D UC+064 064
E UC+065 065
F UC+066 066
G UC+067 067
H UC+070 070
I UC+071 071
J UC+041 041
K UC+042 042
L UC+043 043
M UC+044 044
N UC+045 045
O UC+046 046
P UC+047 047
Q UC+050 050
R UC+051 051
S UC+022 022
T UC+023 023
U UC+024 024
V UC+025 025
W UC+026 026
X UC+027 027
Y UC+030 030
Z UC+031 031
[ UC+057 none
\ {OVERLINE} 056 {OVERLINE} 056
] UC+055 none
^ {UP ARROW} UC+011 {UP ARROW} 035
_ UC+040 UC+040
` {RT ARROW} UC+020 036
a 061 none
b 062 none
c 063 none
d 064 none
e 065 none
f 066 none
g 067 none
h 070 none
i 071 none
j 041 none
k 042 none
l 043 none
m 044 none
n 045 none
o 046 none
p 047 none
q 050 none
r 051 none
s 022 none
t 023 none
u 024 none
v 025 none
w 026 none
x 027 none
y 030 none
z 031 none
{ none none
| UC+056 076
} none none
~ UC+003 013
del 075 none

976
PDP1o/pdp1_dt.c Normal file
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@ -0,0 +1,976 @@
/* pdp1_dt.c: 18b DECtape simulator
Copyright (c) 1993-2002, Robert M Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
Except as contained in this notice, the name of Robert M Supnik shall not
be used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Robert M Supnik.
dt Type 550/555 DECtape
17-Oct-02 RMS Fixed bug in end of reel logic
06-Oct-02 RMS Added device disable support
13-Aug-02 RMS Cloned from pdp18b_dt.c
18b DECtapes are represented in memory by fixed length buffer of 32b words.
Three file formats are supported:
18b/36b 256 words per block [256 x 18b]
16b 256 words per block [256 x 16b]
12b 129 words per block [129 x 12b]
When a 16b or 12b DECtape file is read in, it is converted to 18b/36b format.
DECtape motion is measured in 3b lines. Time between lines is 33.33us.
Tape density is nominally 300 lines per inch. The format of a DECtape is
reverse end zone 36000 lines ~ 10 feet
block 0
:
block n
forward end zone 36000 lines ~ 10 feet
A block consists of five 18b header words, a tape-specific number of data
words, and five 18b trailer words. All systems except the PDP-8 use a
standard block length of 256 words; the PDP-8 uses a standard block length
of 86 words (x 18b = 129 words x 12b). [A PDP-1/4/7 DECtape has only four 18b
header words; for consistency, the PDP-1/4/7 uses the same format as the PDP-9/15
but skips the missing header words.]
Because a DECtape file only contains data, the simulator cannot support
write timing and mark track and can only do a limited implementation
of read all and write all. Read all assumes that the tape has been
conventionally written forward:
header word 0 0
header word 1 block number (for forward reads)
header words 2,3 0
header word 4 0
:
trailer word 4 checksum
trailer words 3,2 0
trailer word 1 block number (for reverse reads)
trailer word 0 0
Write all writes only the data words and dumps the interblock words in the
bit bucket.
The Type 550 controller has a 4b unit select field, for units 1-8; the TC02
has a 3b unit select field, with unit 8 being represented as 0. The code
assumes that the GETUNIT macro returns a unit number in the range of 0-7,
with 8 represented as 0, and an invalid unit as -1.
*/
#include "pdp1_defs.h"
#define DT_NUMDR 8 /* #drives */
#define UNIT_V_WLK (UNIT_V_UF + 0) /* write locked */
#define UNIT_V_8FMT (UNIT_V_UF + 1) /* 12b format */
#define UNIT_V_11FMT (UNIT_V_UF + 2) /* 16b format */
#define UNIT_WLK (1 << UNIT_V_WLK)
#define UNIT_8FMT (1 << UNIT_V_8FMT)
#define UNIT_11FMT (1 << UNIT_V_11FMT)
#define STATE u3 /* unit state */
#define LASTT u4 /* last time update */
#define DT_WC 030 /* word count */
#define DT_CA 031 /* current addr */
#define UNIT_WPRT (UNIT_WLK | UNIT_RO) /* write protect */
/* System independent DECtape constants */
#define DT_EZLIN 36000 /* end zone length */
#define DT_HTLIN 30 /* header/trailer lines */
#define DT_BLKLN 6 /* blk no line in h/t */
#define DT_CSMLN 24 /* checksum line in h/t */
#define DT_HTWRD (DT_HTLIN / DT_WSIZE) /* header/trailer words */
#define DT_BLKWD (DT_BLKLN / DT_WSIZE) /* blk no word in h/t */
#define DT_CSMWD (DT_CSMLN / DT_WSIZE) /* checksum word in h/t */
/* 16b, 18b, 36b DECtape constants */
#define D18_WSIZE 6 /* word size in lines */
#define D18_BSIZE 256 /* block size in 18b */
#define D18_TSIZE 578 /* tape size */
#define D18_LPERB (DT_HTLIN + (D18_BSIZE * DT_WSIZE) + DT_HTLIN)
#define D18_FWDEZ (DT_EZLIN + (D18_LPERB * D18_TSIZE))
#define D18_CAPAC (D18_TSIZE * D18_BSIZE) /* tape capacity */
#define D11_FILSIZ (D18_CAPAC * sizeof (int16))
/* 12b DECtape constants */
#define D8_WSIZE 4 /* word size in lines */
#define D8_BSIZE 86 /* block size in 18b */
#define D8_TSIZE 1474 /* tape size */
#define D8_LPERB (DT_HTLIN + (D8_BSIZE * DT_WSIZE) + DT_HTLIN)
#define D8_FWDEZ (DT_EZLIN + (D8_LPERB * D8_TSIZE))
#define D8_CAPAC (D8_TSIZE * D8_BSIZE) /* tape capacity */
#define D8_NBSIZE ((D8_BSIZE * D18_WSIZE) / D8_WSIZE)
#define D8_FILSIZ (D8_NBSIZE * D8_TSIZE * sizeof (int16))
/* This controller */
#define DT_CAPAC D18_CAPAC /* default */
#define DT_WSIZE D18_WSIZE
/* Calculated constants, per unit */
#define DTU_BSIZE(u) (((u)->flags & UNIT_8FMT)? D8_BSIZE: D18_BSIZE)
#define DTU_TSIZE(u) (((u)->flags & UNIT_8FMT)? D8_TSIZE: D18_TSIZE)
#define DTU_LPERB(u) (((u)->flags & UNIT_8FMT)? D8_LPERB: D18_LPERB)
#define DTU_FWDEZ(u) (((u)->flags & UNIT_8FMT)? D8_FWDEZ: D18_FWDEZ)
#define DTU_CAPAC(u) (((u)->flags & UNIT_8FMT)? D8_CAPAC: D18_CAPAC)
#define DT_LIN2BL(p,u) (((p) - DT_EZLIN) / DTU_LPERB (u))
#define DT_LIN2OF(p,u) (((p) - DT_EZLIN) % DTU_LPERB (u))
#define DT_LIN2WD(p,u) ((DT_LIN2OF (p,u) - DT_HTLIN) / DT_WSIZE)
#define DT_BLK2LN(p,u) (((p) * DTU_LPERB (u)) + DT_EZLIN)
#define DT_QREZ(u) (((u)->pos) < DT_EZLIN)
#define DT_QFEZ(u) (((u)->pos) >= ((uint32) DTU_FWDEZ (u)))
#define DT_QEZ(u) (DT_QREZ (u) || DT_QFEZ (u))
/* Status register A */
#define DTA_V_UNIT 12 /* unit select */
#define DTA_M_UNIT 017
#define DTA_UNIT (DTA_M_UNIT << DTA_V_UNIT)
#define DTA_V_MOT 4 /* motion */
#define DTA_M_MOT 03
#define DTA_V_FNC 0 /* function */
#define DTA_M_FNC 07
#define FNC_MOVE 00 /* move */
#define FNC_SRCH 01 /* search */
#define FNC_READ 02 /* read */
#define FNC_WRIT 03 /* write */
#define FNC_RALL 05 /* read all */
#define FNC_WALL 06 /* write all */
#define FNC_WMRK 07 /* write timing */
#define DTA_STSTP (1u << (DTA_V_MOT + 1))
#define DTA_FWDRV (1u << DTA_V_MOT)
#define DTA_MODE 0 /* not implemented */
#define DTA_RW 077
#define DTA_GETUNIT(x) map_unit[(((x) >> DTA_V_UNIT) & DTA_M_UNIT)]
#define DT_UPDINT if (dtsb & (DTB_DTF | DTB_BEF | DTB_ERF)) \
sbs = sbs | SB_RQ;
#define DTA_GETMOT(x) (((x) >> DTA_V_MOT) & DTA_M_MOT)
#define DTA_GETFNC(x) (((x) >> DTA_V_FNC) & DTA_M_FNC)
/* Status register B */
#define DTB_V_DTF 17 /* data flag */
#define DTB_V_BEF 16 /* block end flag */
#define DTB_V_ERF 15 /* error flag */
#define DTB_V_END 14 /* end of tape */
#define DTB_V_TIM 13 /* timing err */
#define DTB_V_REV 12 /* reverse */
#define DTB_V_GO 11 /* go */
#define DTB_V_MRK 10 /* mark trk err */
#define DTB_V_SEL 9 /* select err */
#define DTB_DTF (1u << DTB_V_DTF)
#define DTB_BEF (1u << DTB_V_BEF)
#define DTB_ERF (1u << DTB_V_ERF)
#define DTB_END (1u << DTB_V_END)
#define DTB_TIM (1u << DTB_V_TIM)
#define DTB_REV (1u << DTB_V_REV)
#define DTB_GO (1u << DTB_V_GO)
#define DTB_MRK (1u << DTB_V_MRK)
#define DTB_SEL (1u << DTB_V_SEL)
#define DTB_ALLERR (DTB_END | DTB_TIM | DTB_MRK | DTB_SEL)
/* DECtape state */
#define DTS_V_MOT 3 /* motion */
#define DTS_M_MOT 07
#define DTS_STOP 0 /* stopped */
#define DTS_DECF 2 /* decel, fwd */
#define DTS_DECR 3 /* decel, rev */
#define DTS_ACCF 4 /* accel, fwd */
#define DTS_ACCR 5 /* accel, rev */
#define DTS_ATSF 6 /* @speed, fwd */
#define DTS_ATSR 7 /* @speed, rev */
#define DTS_DIR 01 /* dir mask */
#define DTS_V_FNC 0 /* function */
#define DTS_M_FNC 07
#define DTS_OFR 7 /* "off reel" */
#define DTS_GETMOT(x) (((x) >> DTS_V_MOT) & DTS_M_MOT)
#define DTS_GETFNC(x) (((x) >> DTS_V_FNC) & DTS_M_FNC)
#define DTS_V_2ND 6 /* next state */
#define DTS_V_3RD (DTS_V_2ND + DTS_V_2ND) /* next next */
#define DTS_STA(y,z) (((y) << DTS_V_MOT) | ((z) << DTS_V_FNC))
#define DTS_SETSTA(y,z) uptr->STATE = DTS_STA (y, z)
#define DTS_SET2ND(y,z) uptr->STATE = (uptr->STATE & 077) | \
((DTS_STA (y, z)) << DTS_V_2ND)
#define DTS_SET3RD(y,z) uptr->STATE = (uptr->STATE & 07777) | \
((DTS_STA (y, z)) << DTS_V_3RD)
#define DTS_NXTSTA(x) (x >> DTS_V_2ND)
/* Operation substates */
#define DTO_WCO 1 /* wc overflow */
#define DTO_SOB 2 /* start of block */
/* Logging */
#define LOG_MS 001 /* move, search */
#define LOG_RW 002 /* read, write */
#define LOG_RA 004 /* read all */
#define LOG_BL 010 /* block # lblk */
#define ABS(x) (((x) < 0)? (-(x)): (x))
extern int32 M[];
extern int32 sbs;
extern int32 stop_inst;
extern UNIT cpu_unit;
extern int32 sim_switches;
extern int32 sim_is_running;
int32 dtsa = 0; /* status A */
int32 dtsb = 0; /* status B */
int32 dtdb = 0; /* data buffer */
int32 dt_ltime = 12; /* interline time */
int32 dt_actime = 54000; /* accel time */
int32 dt_dctime = 72000; /* decel time */
int32 dt_substate = 0;
int32 dt_log = 0;
int32 dt_logblk = 0;
static const int32 map_unit[16] = { /* Type 550 unit map */
-1, 1, 2, 3, 4, 5, 6, 7,
0, -1, -1, -1, -1, -1, -1, -1 };
t_stat dt_svc (UNIT *uptr);
t_stat dt_reset (DEVICE *dptr);
t_stat dt_attach (UNIT *uptr, char *cptr);
t_stat dt_detach (UNIT *uptr);
void dt_deselect (int32 oldf);
void dt_newsa (int32 newf);
void dt_newfnc (UNIT *uptr, int32 newsta);
t_bool dt_setpos (UNIT *uptr);
void dt_schedez (UNIT *uptr, int32 dir);
void dt_seterr (UNIT *uptr, int32 e);
int32 dt_comobv (int32 val);
int32 dt_csum (UNIT *uptr, int32 blk);
int32 dt_gethdr (UNIT *uptr, int32 blk, int32 relpos);
/* DT data structures
dt_dev DT device descriptor
dt_unit DT unit list
dt_reg DT register list
dt_mod DT modifier list
*/
UNIT dt_unit[] = {
{ UDATA (&dt_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+
UNIT_ROABLE, DT_CAPAC) },
{ UDATA (&dt_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+
UNIT_ROABLE, DT_CAPAC) },
{ UDATA (&dt_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+
UNIT_ROABLE, DT_CAPAC) },
{ UDATA (&dt_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+
UNIT_ROABLE, DT_CAPAC) },
{ UDATA (&dt_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+
UNIT_ROABLE, DT_CAPAC) },
{ UDATA (&dt_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+
UNIT_ROABLE, DT_CAPAC) },
{ UDATA (&dt_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+
UNIT_ROABLE, DT_CAPAC) },
{ UDATA (&dt_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+
UNIT_ROABLE, DT_CAPAC) } };
REG dt_reg[] = {
{ ORDATA (DTSA, dtsa, 18) },
{ ORDATA (DTSB, dtsb, 18) },
{ ORDATA (DTDB, dtdb, 18) },
{ FLDATA (DTF, dtsb, DTB_V_DTF) },
{ FLDATA (BEF, dtsb, DTB_V_BEF) },
{ FLDATA (ERF, dtsb, DTB_V_ERF) },
{ DRDATA (LTIME, dt_ltime, 31), REG_NZ },
{ DRDATA (ACTIME, dt_actime, 31), REG_NZ },
{ DRDATA (DCTIME, dt_dctime, 31), REG_NZ },
{ ORDATA (SUBSTATE, dt_substate, 2) },
{ ORDATA (LOG, dt_log, 4), REG_HIDDEN },
{ DRDATA (LBLK, dt_logblk, 12), REG_HIDDEN },
{ URDATA (POS, dt_unit[0].pos, 10, 32, 0,
DT_NUMDR, PV_LEFT | REG_RO) },
{ URDATA (STATT, dt_unit[0].STATE, 8, 18, 0,
DT_NUMDR, REG_RO) },
{ URDATA (LASTT, dt_unit[0].LASTT, 10, 32, 0,
DT_NUMDR, REG_HRO) },
{ NULL } };
MTAB dt_mod[] = {
{ UNIT_WLK, 0, "write enabled", "WRITEENABLED", NULL },
{ UNIT_WLK, UNIT_WLK, "write locked", "LOCKED", NULL },
{ UNIT_8FMT + UNIT_11FMT, 0, "18b", NULL, NULL },
{ UNIT_8FMT + UNIT_11FMT, UNIT_8FMT, "12b", NULL, NULL },
{ UNIT_8FMT + UNIT_11FMT, UNIT_11FMT, "16b", NULL, NULL },
{ 0 } };
DEVICE dt_dev = {
"DT", dt_unit, dt_reg, dt_mod,
DT_NUMDR, 8, 24, 1, 8, 18,
NULL, NULL, &dt_reset,
NULL, &dt_attach, &dt_detach,
NULL, DEV_DISABLE };
int32 dt (int32 IR, int32 dev, int32 IO)
{
int32 pulse = (IR >> 6) & 037;
int32 fnc, mot, unum;
UNIT *uptr = NULL;
if (dt_dev.flags & DEV_DIS) /* disabled? */
return (stop_inst << IOT_V_REASON) | IO; /* stop if requested */
unum = DTA_GETUNIT (dtsa); /* get unit no */
if (unum >= 0) uptr = dt_dev.units + unum; /* get unit */
if (pulse == 003) { /* MSE */
if ((dtsa ^ IO) & DTA_UNIT) dt_deselect (dtsa); /* new unit? */
dtsa = (dtsa & ~DTA_UNIT) | (IO & DTA_UNIT);
dtsb = dtsb & ~(DTB_DTF | DTB_BEF | DTB_ERF | DTB_ALLERR); }
if (pulse == 004) { /* MLC */
dtsa = (dtsa & ~DTA_RW) | (IO & DTA_RW); /* load dtsa */
dtsb = dtsb & ~(DTB_DTF | DTB_BEF | DTB_ERF | DTB_ALLERR);
fnc = DTA_GETFNC (dtsa); /* get fnc */
if ((uptr == NULL) || /* invalid? */
((uptr->flags) & UNIT_DIS) || /* disabled? */
(fnc >= FNC_WMRK) || /* write mark? */
((fnc == FNC_WRIT) && (uptr->flags & UNIT_WLK)) ||
((fnc == FNC_WALL) && (uptr->flags & UNIT_WLK)))
dt_seterr (uptr, DTB_SEL); /* select err */
else dt_newsa (dtsa); }
if (pulse == 005) { /* MRD */
IO = (IO & ~DMASK) | dtdb;
dtsb = dtsb & ~(DTB_DTF | DTB_BEF); }
if (pulse == 006) { /* MWR */
dtdb = IO & DMASK;
dtsb = dtsb & ~(DTB_DTF | DTB_BEF); }
if (pulse == 007) { /* MRS */
dtsb = dtsb & ~(DTB_REV | DTB_GO); /* clr rev, go */
if (uptr) { /* valid unit? */
mot = DTS_GETMOT (uptr->STATE); /* get motion */
if (mot & DTS_DIR) dtsb = dtsb | DTB_REV; /* rev? set */
if ((mot >= DTS_ACCF) || (uptr->STATE & 0777700))
dtsb = dtsb | DTB_GO; } /* accel? go */
IO = (IO & ~DMASK) | dtsb; }
DT_UPDINT;
return IO;
}
/* Unit deselect */
void dt_deselect (int32 oldf)
{
int32 old_unit, old_mot;
UNIT *uptr;
old_unit = DTA_GETUNIT (oldf); /* get unit no */
if (old_unit < 0) return; /* invalid? */
uptr = dt_dev.units + old_unit; /* get unit */
old_mot = DTS_GETMOT (uptr->STATE);
if (old_mot >= DTS_ATSF) /* at speed? */
dt_newfnc (uptr, DTS_STA (old_mot, DTS_OFR));
else if (old_mot >= DTS_ACCF) /* accelerating? */
DTS_SET2ND (DTS_ATSF | (old_mot & DTS_DIR), DTS_OFR);
return;
}
/* Command register change
1. If change in motion, stop to start
- schedule acceleration
- set function as next state
2. If change in motion, start to stop
- if not already decelerating (could be reversing),
schedule deceleration
3. If change in direction,
- if not decelerating, schedule deceleration
- set accelerating (other dir) as next state
- set function as next next state
4. If not accelerating or at speed,
- schedule acceleration
- set function as next state
5. If not yet at speed,
- set function as next state
6. If at speed,
- set function as current state, schedule function
*/
void dt_newsa (int32 newf)
{
int32 new_unit, prev_mot, new_fnc;
int32 prev_mving, new_mving, prev_dir, new_dir;
UNIT *uptr;
new_unit = DTA_GETUNIT (newf); /* new unit */
if (new_unit < 0) return; /* invalid? */
uptr = dt_dev.units + new_unit;
if ((uptr->flags & UNIT_ATT) == 0) { /* new unit attached? */
dt_seterr (uptr, DTB_SEL); /* no, error */
return; }
prev_mot = DTS_GETMOT (uptr->STATE); /* previous motion */
prev_mving = prev_mot != DTS_STOP; /* previous moving? */
prev_dir = prev_mot & DTS_DIR; /* previous dir? */
new_mving = (newf & DTA_STSTP) != 0; /* new moving? */
new_dir = (newf & DTA_FWDRV) != 0; /* new dir? */
new_fnc = DTA_GETFNC (newf); /* new function? */
if ((prev_mving | new_mving) == 0) return; /* stop to stop */
if (new_mving & ~prev_mving) { /* start? */
if (dt_setpos (uptr)) return; /* update pos */
sim_cancel (uptr); /* stop current */
sim_activate (uptr, dt_actime); /* schedule accel */
DTS_SETSTA (DTS_ACCF | new_dir, 0); /* state = accel */
DTS_SET2ND (DTS_ATSF | new_dir, new_fnc); /* next = fnc */
return; }
if (prev_mving & ~new_mving) { /* stop? */
if ((prev_mot & ~DTS_DIR) != DTS_DECF) { /* !already stopping? */
if (dt_setpos (uptr)) return; /* update pos */
sim_cancel (uptr); /* stop current */
sim_activate (uptr, dt_dctime); } /* schedule decel */
DTS_SETSTA (DTS_DECF | prev_dir, 0); /* state = decel */
return; }
if (prev_dir ^ new_dir) { /* dir chg? */
if ((prev_mot & ~DTS_DIR) != DTS_DECF) { /* !already stopping? */
if (dt_setpos (uptr)) return; /* update pos */
sim_cancel (uptr); /* stop current */
sim_activate (uptr, dt_dctime); } /* schedule decel */
DTS_SETSTA (DTS_DECF | prev_dir, 0); /* state = decel */
DTS_SET2ND (DTS_ACCF | new_dir, 0); /* next = accel */
DTS_SET3RD (DTS_ATSF | new_dir, new_fnc); /* next next = fnc */
return; }
if (prev_mot < DTS_ACCF) { /* not accel/at speed? */
if (dt_setpos (uptr)) return; /* update pos */
sim_cancel (uptr); /* cancel cur */
sim_activate (uptr, dt_actime); /* schedule accel */
DTS_SETSTA (DTS_ACCF | new_dir, 0); /* state = accel */
DTS_SET2ND (DTS_ATSF | new_dir, new_fnc); /* next = fnc */
return; }
if (prev_mot < DTS_ATSF) { /* not at speed? */
DTS_SET2ND (DTS_ATSF | new_dir, new_fnc); /* next = fnc */
return; }
dt_newfnc (uptr, DTS_STA (DTS_ATSF | new_dir, new_fnc));/* state = fnc */
return;
}
/* Schedule new DECtape function
This routine is only called if
- the selected unit is attached
- the selected unit is at speed (forward or backward)
This routine
- updates the selected unit's position
- updates the selected unit's state
- schedules the new operation
*/
void dt_newfnc (UNIT *uptr, int32 newsta)
{
int32 fnc, dir, blk, unum, newpos;
uint32 oldpos;
oldpos = uptr->pos; /* save old pos */
if (dt_setpos (uptr)) return; /* update pos */
uptr->STATE = newsta; /* update state */
fnc = DTS_GETFNC (uptr->STATE); /* set variables */
dir = DTS_GETMOT (uptr->STATE) & DTS_DIR;
unum = uptr - dt_dev.units;
if (oldpos == uptr->pos) /* bump pos */
uptr->pos = uptr->pos + (dir? -1: 1);
blk = DT_LIN2BL (uptr->pos, uptr);
if (dir? DT_QREZ (uptr): DT_QFEZ (uptr)) { /* wrong ez? */
dt_seterr (uptr, DTB_END); /* set ez flag, stop */
return; }
sim_cancel (uptr); /* cancel cur op */
dt_substate = DTO_SOB; /* substate = block start */
switch (fnc) { /* case function */
case DTS_OFR: /* off reel */
if (dir) newpos = -1000; /* rev? < start */
else newpos = DTU_FWDEZ (uptr) + DT_EZLIN + 1000; /* fwd? > end */
break;
case FNC_MOVE: /* move */
dt_schedez (uptr, dir); /* sched end zone */
if (dt_log & LOG_MS) printf ("[DT%d: moving %s]\n", unum, (dir?
"backward": "forward"));
return; /* done */
case FNC_SRCH: /* search */
if (dir) newpos = DT_BLK2LN ((DT_QFEZ (uptr)?
DTU_TSIZE (uptr): blk), uptr) - DT_BLKLN - DT_WSIZE;
else newpos = DT_BLK2LN ((DT_QREZ (uptr)?
0: blk + 1), uptr) + DT_BLKLN + (DT_WSIZE - 1);
if (dt_log & LOG_MS) printf ("[DT%d: searching %s]\n", unum,
(dir? "backward": "forward"));
break;
case FNC_WRIT: /* write */
case FNC_READ: /* read */
case FNC_RALL: /* read all */
case FNC_WALL: /* write all */
if (DT_QEZ (uptr)) { /* in "ok" end zone? */
if (dir) newpos = DTU_FWDEZ (uptr) - DT_WSIZE;
else newpos = DT_EZLIN + (DT_WSIZE - 1); }
else { newpos = ((uptr->pos) / DT_WSIZE) * DT_WSIZE;
if (!dir) newpos = newpos + (DT_WSIZE - 1); }
if ((dt_log & LOG_RA) || ((dt_log & LOG_BL) && (blk == dt_logblk)))
printf ("[DT%d: read all block %d %s%s\n",
unum, blk, (dir? "backward": "forward"),
((dtsa & DTA_MODE)? " continuous]": "]"));
break;
default:
dt_seterr (uptr, DTB_SEL); /* bad state */
return; }
if ((fnc == FNC_WRIT) || (fnc == FNC_WALL)) { /* write function? */
dtsb = dtsb | DTB_DTF; /* set data flag */
DT_UPDINT; }
sim_activate (uptr, ABS (newpos - ((int32) uptr->pos)) * dt_ltime);
return;
}
/* Update DECtape position
DECtape motion is modeled as a constant velocity, with linear
acceleration and deceleration. The motion equations are as follows:
t = time since operation started
tmax = time for operation (accel, decel only)
v = at speed velocity in lines (= 1/dt_ltime)
Then:
at speed dist = t * v
accel dist = (t^2 * v) / (2 * tmax)
decel dist = (((2 * t * tmax) - t^2) * v) / (2 * tmax)
This routine uses the relative (integer) time, rather than the absolute
(floating point) time, to allow save and restore of the start times.
*/
t_bool dt_setpos (UNIT *uptr)
{
uint32 new_time, ut, ulin, udelt;
int32 mot = DTS_GETMOT (uptr->STATE);
int32 unum, delta;
new_time = sim_grtime (); /* current time */
ut = new_time - uptr->LASTT; /* elapsed time */
if (ut == 0) return FALSE; /* no time gone? exit */
uptr->LASTT = new_time; /* update last time */
switch (mot & ~DTS_DIR) { /* case on motion */
case DTS_STOP: /* stop */
delta = 0;
break;
case DTS_DECF: /* slowing */
ulin = ut / (uint32) dt_ltime; udelt = dt_dctime / dt_ltime;
delta = ((ulin * udelt * 2) - (ulin * ulin)) / (2 * udelt);
break;
case DTS_ACCF: /* accelerating */
ulin = ut / (uint32) dt_ltime; udelt = dt_actime / dt_ltime;
delta = (ulin * ulin) / (2 * udelt);
break;
case DTS_ATSF: /* at speed */
delta = ut / (uint32) dt_ltime;
break; }
if (mot & DTS_DIR) uptr->pos = uptr->pos - delta; /* update pos */
else uptr->pos = uptr->pos + delta;
if (((int32) uptr->pos < 0) ||
((int32) uptr->pos > (DTU_FWDEZ (uptr) + DT_EZLIN))) {
detach_unit (uptr); /* off reel? */
uptr->STATE = uptr->pos = 0;
unum = uptr - dt_dev.units;
if (unum == DTA_GETUNIT (dtsa)) /* if selected, */
dt_seterr (uptr, DTB_SEL); /* error */
return TRUE; }
return FALSE;
}
/* Unit service
Unit must be attached, detach cancels operation
*/
t_stat dt_svc (UNIT *uptr)
{
int32 mot = DTS_GETMOT (uptr->STATE);
int32 dir = mot & DTS_DIR;
int32 fnc = DTS_GETFNC (uptr->STATE);
int32 *bptr = uptr->filebuf;
int32 unum = uptr - dt_dev.units;
int32 blk, wrd, ma, relpos;
t_addr ba;
/* Motion cases
Decelerating - if next state != stopped, must be accel reverse
Accelerating - next state must be @speed, schedule function
At speed - do functional processing
*/
switch (mot) {
case DTS_DECF: case DTS_DECR: /* decelerating */
if (dt_setpos (uptr)) return SCPE_OK; /* update pos */
uptr->STATE = DTS_NXTSTA (uptr->STATE); /* advance state */
if (uptr->STATE) /* not stopped? */
sim_activate (uptr, dt_actime); /* must be reversing */
return SCPE_OK;
case DTS_ACCF: case DTS_ACCR: /* accelerating */
dt_newfnc (uptr, DTS_NXTSTA (uptr->STATE)); /* adv state, sched */
return SCPE_OK;
case DTS_ATSF: case DTS_ATSR: /* at speed */
break; /* check function */
default: /* other */
dt_seterr (uptr, DTB_SEL); /* state error */
return SCPE_OK; }
/* Functional cases
Move - must be at end zone
Search - transfer block number, schedule next block
Off reel - detach unit (it must be deselected)
*/
if (dt_setpos (uptr)) return SCPE_OK; /* update pos */
if (DT_QEZ (uptr)) { /* in end zone? */
dt_seterr (uptr, DTB_END); /* end zone error */
return SCPE_OK; }
blk = DT_LIN2BL (uptr->pos, uptr); /* get block # */
switch (fnc) { /* at speed, check fnc */
case FNC_MOVE: /* move */
dt_seterr (uptr, DTB_END); /* end zone error */
return SCPE_OK;
case DTS_OFR: /* off reel */
detach_unit (uptr); /* must be deselected */
uptr->STATE = uptr->pos = 0; /* no visible action */
break;
/* Search */
case FNC_SRCH: /* search */
if (dtsb & DTB_DTF) { /* DTF set? */
dt_seterr (uptr, DTB_TIM); /* timing error */
return SCPE_OK; }
sim_activate (uptr, DTU_LPERB (uptr) * dt_ltime);/* sched next block */
dtdb = blk; /* store block # */
dtsb = dtsb | DTB_DTF; /* set DTF */
break;
/* Read and read all */
case FNC_READ: case FNC_RALL:
if (dtsb & DTB_DTF) { /* DTF set? */
dt_seterr (uptr, DTB_TIM); /* timing error */
return SCPE_OK; }
sim_activate (uptr, DT_WSIZE * dt_ltime); /* sched next word */
relpos = DT_LIN2OF (uptr->pos, uptr); /* cur pos in blk */
if ((relpos >= DT_HTLIN) && /* in data zone? */
(relpos < (DTU_LPERB (uptr) - DT_HTLIN))) {
wrd = DT_LIN2WD (uptr->pos, uptr);
ba = (blk * DTU_BSIZE (uptr)) + wrd;
dtdb = bptr[ba]; /* get tape word */
dtsb = dtsb | DTB_DTF; } /* set flag */
else { ma = (2 * DT_HTWRD) + DTU_BSIZE (uptr) - DT_CSMWD - 1;
wrd = relpos / DT_WSIZE; /* hdr start = wd 0 */
if ((wrd == 0) || /* skip 1st, last */
(wrd == ((2 * DT_HTWRD) + DTU_BSIZE (uptr) - 1))) break;
if ((fnc == FNC_READ) && /* read, skip if not */
(wrd != DT_CSMWD) && /* fwd, rev cksum */
(wrd != ma)) break;
dtdb = dt_gethdr (uptr, blk, relpos);
if (wrd == (dir? DT_CSMWD: ma)) /* at end csum? */
dtsb = dtsb | DTB_BEF; /* end block */
else dtsb = dtsb | DTB_DTF; } /* else next word */
if (dir) dtdb = dt_comobv (dtdb);
break;
/* Write and write all */
case FNC_WRIT: case FNC_WALL:
if (dtsb & DTB_DTF) { /* DTF set? */
dt_seterr (uptr, DTB_TIM); /* timing error */
return SCPE_OK; }
sim_activate (uptr, DT_WSIZE * dt_ltime); /* sched next word */
relpos = DT_LIN2OF (uptr->pos, uptr); /* cur pos in blk */
if ((relpos >= DT_HTLIN) && /* in data zone? */
(relpos < (DTU_LPERB (uptr) - DT_HTLIN))) {
wrd = DT_LIN2WD (uptr->pos, uptr);
ba = (blk * DTU_BSIZE (uptr)) + wrd;
if (dir) bptr[ba] = dt_comobv (dtdb); /* get data word */
else bptr[ba] = dtdb;
if (ba >= uptr->hwmark) uptr->hwmark = ba + 1;
if (wrd == (dir? 0: DTU_BSIZE (uptr) - 1))
dtsb = dtsb | DTB_BEF; /* end block */
else dtsb = dtsb | DTB_DTF; } /* else next word */
else { wrd = relpos / DT_WSIZE; /* hdr start = wd 0 */
if ((wrd == 0) || /* skip 1st, last */
(wrd == ((2 * DT_HTWRD) + DTU_BSIZE (uptr) - 1))) break;
if ((fnc == FNC_WRIT) && /* wr, skip if !csm */
(wrd != ((2 * DT_HTWRD) + DTU_BSIZE (uptr) - DT_CSMWD - 1)))
break;
dtsb = dtsb | DTB_DTF; } /* set flag */
break;
default:
dt_seterr (uptr, DTB_SEL); /* impossible state */
break; }
DT_UPDINT; /* update interrupts */
return SCPE_OK;
}
/* Utility routines */
/* Set error flag */
void dt_seterr (UNIT *uptr, int32 e)
{
int32 mot = DTS_GETMOT (uptr->STATE);
dtsa = dtsa & ~DTA_STSTP; /* clear go */
dtsb = dtsb | DTB_ERF | e; /* set error flag */
if (mot >= DTS_ACCF) { /* ~stopped or stopping? */
sim_cancel (uptr); /* cancel activity */
if (dt_setpos (uptr)) return; /* update position */
sim_activate (uptr, dt_dctime); /* sched decel */
DTS_SETSTA (DTS_DECF | (mot & DTS_DIR), 0); } /* state = decel */
DT_UPDINT;
return;
}
/* Schedule end zone */
void dt_schedez (UNIT *uptr, int32 dir)
{
int32 newpos;
if (dir) newpos = DT_EZLIN - DT_WSIZE; /* rev? rev ez */
else newpos = DTU_FWDEZ (uptr) + DT_WSIZE; /* fwd? fwd ez */
sim_activate (uptr, ABS (newpos - ((int32) uptr->pos)) * dt_ltime);
return;
}
/* Complement obverse routine */
int32 dt_comobv (int32 dat)
{
dat = dat ^ 0777777; /* compl obverse */
dat = ((dat >> 15) & 07) | ((dat >> 9) & 070) |
((dat >> 3) & 0700) | ((dat & 0700) << 3) |
((dat & 070) << 9) | ((dat & 07) << 15);
return dat;
}
/* Checksum routine */
int32 dt_csum (UNIT *uptr, int32 blk)
{
int32 *bptr = uptr->filebuf;
int32 ba = blk * DTU_BSIZE (uptr);
int32 i, csum, wrd;
csum = 0777777;
for (i = 0; i < DTU_BSIZE (uptr); i++) { /* loop thru buf */
wrd = bptr[ba + i]; /* get word */
csum = csum + wrd; /* 1's comp add */
if (csum > 0777777) csum = (csum + 1) & 0777777; }
return (csum ^ 0777777); /* 1's comp res */
}
/* Get header word */
int32 dt_gethdr (UNIT *uptr, int32 blk, int32 relpos)
{
int32 wrd = relpos / DT_WSIZE;
if (wrd == DT_BLKWD) return blk; /* fwd blknum */
if (wrd == DT_CSMWD) return 0777777; /* rev csum */
if (wrd == (2 * DT_HTWRD + DTU_BSIZE (uptr) - DT_CSMWD - 1)) /* fwd csum */
return (dt_csum (uptr, blk));
if (wrd == (2 * DT_HTWRD + DTU_BSIZE (uptr) - DT_BLKWD - 1)) /* rev blkno */
return dt_comobv (blk);
return 0; /* all others */
}
/* Reset routine */
t_stat dt_reset (DEVICE *dptr)
{
int32 i, prev_mot;
UNIT *uptr;
for (i = 0; i < DT_NUMDR; i++) { /* stop all drives */
uptr = dt_dev.units + i;
if (sim_is_running) { /* CAF? */
prev_mot = DTS_GETMOT (uptr->STATE); /* get motion */
if ((prev_mot & ~DTS_DIR) > DTS_DECF) { /* accel or spd? */
if (dt_setpos (uptr)) continue; /* update pos */
sim_cancel (uptr);
sim_activate (uptr, dt_dctime); /* sched decel */
DTS_SETSTA (DTS_DECF | (prev_mot & DTS_DIR), 0);
} }
else { sim_cancel (uptr); /* sim reset */
uptr->STATE = 0;
uptr->LASTT = sim_grtime (); } }
dtsa = dtsb = 0; /* clear status */
DT_UPDINT; /* reset interrupt */
return SCPE_OK;
}
/* IORS routine */
int32 dt_iors (void)
{
#if defined IOS_DTA
return ((dtsb & (DTB_ERF | DTB_DTF))? IOS_DTA: 0);
#else
return 0;
#endif
}
/* Attach routine
Determine 12b, 16b, or 18b/36b format
Allocate buffer
If 12b, read 12b format and convert to 18b in buffer
If 16b, read 16b format and convert to 18b in buffer
If 18b/36b, read data into buffer
*/
t_stat dt_attach (UNIT *uptr, char *cptr)
{
uint16 pdp8b[D8_NBSIZE];
uint16 pdp11b[D18_BSIZE];
uint32 k, p, *bptr;
t_stat r;
t_addr ba;
r = attach_unit (uptr, cptr); /* attach */
if (r != SCPE_OK) return r; /* error? */
uptr->flags = uptr->flags & ~(UNIT_8FMT | UNIT_11FMT); /* default 18b */
if (sim_switches & SWMASK ('R')) /* att 12b? */
uptr->flags = uptr->flags | UNIT_8FMT;
else if (sim_switches & SWMASK ('S')) /* att 16b? */
uptr->flags = uptr->flags | UNIT_11FMT;
else if (!(sim_switches & SWMASK ('T')) && /* autosize? */
(fseek (uptr->fileref, 0, SEEK_END) == 0) &&
((p = ftell (uptr->fileref)) != 0)) {
if (p == D8_FILSIZ) uptr->flags = uptr->flags | UNIT_8FMT;
if (p == D11_FILSIZ) uptr->flags = uptr->flags | UNIT_11FMT; }
uptr->capac = DTU_CAPAC (uptr); /* set capacity */
uptr->filebuf = calloc (uptr->capac, sizeof (int32));
if (uptr->filebuf == NULL) { /* can't alloc? */
detach_unit (uptr);
return SCPE_MEM; }
bptr = uptr->filebuf; /* file buffer */
if (uptr->flags & UNIT_8FMT) printf ("DT: 12b format");
else if (uptr->flags & UNIT_11FMT) printf ("DT: 16b format");
else printf ("DT: 18b/36b format");
printf (", buffering file in memory\n");
rewind (uptr->fileref); /* start of file */
if (uptr->flags & UNIT_8FMT) { /* 12b? */
for (ba = 0; ba < uptr->capac; ) { /* loop thru file */
k = fxread (pdp8b, sizeof (int16), D8_NBSIZE, uptr->fileref);
if (k == 0) break;
for ( ; k < D8_NBSIZE; k++) pdp8b[k] = 0;
for (k = 0; k < D8_NBSIZE; k = k + 3) { /* loop thru blk */
bptr[ba] = ((uint32) (pdp8b[k] & 07777) << 6) |
((uint32) (pdp8b[k + 1] >> 6) & 077);
bptr[ba + 1] = ((uint32) (pdp8b[k + 1] & 077) << 12) |
(pdp8b[k + 2] & 07777);
ba = ba + 2; } /* end blk loop */
} /* end file loop */
uptr->hwmark = ba; } /* end if */
else if (uptr->flags & UNIT_11FMT) { /* 16b? */
for (ba = 0; ba < uptr->capac; ) { /* loop thru file */
k = fxread (pdp11b, sizeof (int16), D18_BSIZE, uptr->fileref);
if (k == 0) break;
for ( ; k < D18_BSIZE; k++) pdp11b[k] = 0;
for (k = 0; k < D18_BSIZE; k++)
bptr[ba++] = pdp11b[k]; }
uptr->hwmark = ba; } /* end elif */
else uptr->hwmark = fxread (uptr->filebuf, sizeof (int32),
uptr->capac, uptr->fileref);
uptr->flags = uptr->flags | UNIT_BUF; /* set buf flag */
uptr->pos = DT_EZLIN; /* beyond leader */
uptr->LASTT = sim_grtime (); /* last pos update */
return SCPE_OK;
}
/* Detach routine
Cancel in progress operation
If 12b, convert 18b buffer to 12b and write to file
If 16b, convert 18b buffer to 16b and write to file
If 18b/36b, write buffer to file
Deallocate buffer
*/
t_stat dt_detach (UNIT* uptr)
{
uint16 pdp8b[D8_NBSIZE];
uint16 pdp11b[D18_BSIZE];
uint32 k, *bptr;
int32 unum = uptr - dt_dev.units;
t_addr ba;
if (!(uptr->flags & UNIT_ATT)) return SCPE_OK;
if (sim_is_active (uptr)) {
sim_cancel (uptr);
if ((unum == DTA_GETUNIT (dtsa)) && (dtsa & DTA_STSTP)) {
dtsb = dtsb | DTB_ERF | DTB_SEL | DTB_DTF;
DT_UPDINT; }
uptr->STATE = uptr->pos = 0; }
bptr = uptr->filebuf; /* file buffer */
if (uptr->hwmark && ((uptr->flags & UNIT_RO) == 0)) { /* any data? */
printf ("DT: writing buffer to file\n");
rewind (uptr->fileref); /* start of file */
if (uptr->flags & UNIT_8FMT) { /* 12b? */
for (ba = 0; ba < uptr->hwmark; ) { /* loop thru file */
for (k = 0; k < D8_NBSIZE; k = k + 3) { /* loop blk */
pdp8b[k] = (bptr[ba] >> 6) & 07777;
pdp8b[k + 1] = ((bptr[ba] & 077) << 6) |
((bptr[ba + 1] >> 12) & 077);
pdp8b[k + 2] = bptr[ba + 1] & 07777;
ba = ba + 2; } /* end loop blk */
fxwrite (pdp8b, sizeof (int16), D8_NBSIZE, uptr->fileref);
if (ferror (uptr->fileref)) break; } /* end loop file */
} /* end if 12b */
else if (uptr->flags & UNIT_11FMT) { /* 16b? */
for (ba = 0; ba < uptr->hwmark; ) { /* loop thru file */
for (k = 0; k < D18_BSIZE; k++) /* loop blk */
pdp11b[k] = bptr[ba++] & 0177777;
fxwrite (pdp11b, sizeof (int16), D18_BSIZE, uptr->fileref);
if (ferror (uptr->fileref)) break; } /* end loop file */
} /* end if 16b */
else fxwrite (uptr->filebuf, sizeof (int32), /* write file */
uptr->hwmark, uptr->fileref);
if (ferror (uptr->fileref)) perror ("I/O error"); } /* end if hwmark */
free (uptr->filebuf); /* release buf */
uptr->flags = uptr->flags & ~UNIT_BUF; /* clear buf flag */
uptr->filebuf = NULL; /* clear buf ptr */
uptr->flags = uptr->flags & ~(UNIT_8FMT | UNIT_11FMT); /* default fmt */
uptr->capac = DT_CAPAC; /* default size */
return detach_unit (uptr);
}

172
PDP1o/pdp1_lp.c Normal file
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@ -0,0 +1,172 @@
/* pdp1_lp.c: PDP-1 line printer simulator
Copyright (c) 1993-2002, Robert M. Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
Except as contained in this notice, the name of Robert M Supnik shall not
be used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Robert M Supnik.
lpt Type 62 line printer for the PDP-1
30-May-02 RMS Widened POS to 32b
13-Apr-01 RMS Revised for register arrays
*/
#include "pdp1_defs.h"
#define BPTR_MAX 40 /* pointer max */
#define LPT_BSIZE (BPTR_MAX * 3) /* line size */
#define BPTR_MASK 077 /* buf ptr mask */
extern int32 ioc, sbs, iosta;
extern int32 stop_inst;
int32 lpt_rpls = 0, lpt_iot = 0, lpt_stopioe = 0, bptr = 0;
char lpt_buf[LPT_BSIZE + 1] = { 0 };
static const unsigned char lpt_trans[64] = {
' ','1','2','3','4','5','6','7','8','9','\'','~','#','V','^','<',
'0','/','S','T','U','V','W','X','Y','Z','"',',','>','^','-','?',
'@','J','K','L','M','N','O','P','Q','R','$','=','-',')','-','(',
'_','A','B','C','D','E','F','G','H','I','*','.','+',']','|','[' };
t_stat lpt_svc (UNIT *uptr);
t_stat lpt_reset (DEVICE *dptr);
/* LPT data structures
lpt_dev LPT device descriptor
lpt_unit LPT unit
lpt_reg LPT register list
*/
UNIT lpt_unit = {
UDATA (&lpt_svc, UNIT_SEQ+UNIT_ATTABLE, 0), SERIAL_OUT_WAIT };
REG lpt_reg[] = {
{ ORDATA (BUF, lpt_unit.buf, 8) },
{ FLDATA (PNT, iosta, IOS_V_PNT) },
{ FLDATA (SPC, iosta, IOS_V_SPC) },
{ FLDATA (RPLS, lpt_rpls, 0) },
{ DRDATA (BPTR, bptr, 6) },
{ ORDATA (LPT_STATE, lpt_iot, 6), REG_HRO },
{ DRDATA (POS, lpt_unit.pos, 32), PV_LEFT },
{ DRDATA (TIME, lpt_unit.wait, 24), PV_LEFT },
{ FLDATA (STOP_IOE, lpt_stopioe, 0) },
{ BRDATA (LBUF, lpt_buf, 8, 8, LPT_BSIZE) },
{ NULL } };
DEVICE lpt_dev = {
"LPT", &lpt_unit, lpt_reg, NULL,
1, 10, 31, 1, 8, 8,
NULL, NULL, &lpt_reset,
NULL, NULL, NULL,
NULL, DEV_DISABLE };
/* Line printer IOT routine */
int32 lpt (int32 inst, int32 dev, int32 data)
{
int32 i;
if (lpt_dev.flags & DEV_DIS) /* disabled? */
return (stop_inst << IOT_V_REASON) | data; /* stop if requested */
if ((inst & 0700) == 0100) { /* fill buf */
if (bptr < BPTR_MAX) { /* limit test ptr */
i = bptr * 3; /* cvt to chr ptr */
lpt_buf[i] = lpt_trans[(data >> 12) & 077];
lpt_buf[i + 1] = lpt_trans[(data >> 6) & 077];
lpt_buf[i + 2] = lpt_trans[data & 077]; }
bptr = (bptr + 1) & BPTR_MASK;
return data; }
lpt_rpls = 0;
if ((inst & 0700) == 0200) { /* space */
iosta = iosta & ~IOS_SPC; /* space, clear flag */
lpt_iot = (inst >> 6) & 077; } /* state = space n */
else { iosta = iosta & ~IOS_PNT; /* clear flag */
lpt_iot = 0; } /* state = print */
if (GEN_CPLS (inst)) { /* comp pulse? */
ioc = 0; /* clear flop */
lpt_rpls = 1; } /* request completion */
sim_activate (&lpt_unit, lpt_unit.wait); /* activate */
return data;
}
/* Unit service, printer is in one of three states
lpt_iot = 000 write buffer to file, set state to
lpt_iot = 010 write cr, then write buffer to file
lpt_iot = 02x space command x, then set state to 0
*/
t_stat lpt_svc (UNIT *uptr)
{
int32 i;
static const char *lpt_cc[] = {
"\n",
"\n\n",
"\n\n\n",
"\n\n\n\n\n\n",
"\n\n\n\n\n\n\n\n\n\n\n",
"\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n",
"\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n",
"\f" };
sbs = sbs | SB_RQ; /* req seq break */
ioc = ioc | lpt_rpls; /* restart */
if (lpt_iot & 020) { /* space? */
iosta = iosta | IOS_SPC; /* set flag */
if ((lpt_unit.flags & UNIT_ATT) == 0) /* attached? */
return IORETURN (lpt_stopioe, SCPE_UNATT);
fputs (lpt_cc[lpt_iot & 07], lpt_unit.fileref); /* print cctl */
if (ferror (lpt_unit.fileref)) { /* error? */
perror ("LPT I/O error");
clearerr (lpt_unit.fileref);
return SCPE_IOERR; }
lpt_iot = 0; } /* clear state */
else { iosta = iosta | IOS_PNT; /* print */
if ((lpt_unit.flags & UNIT_ATT) == 0) /* attached? */
return IORETURN (lpt_stopioe, SCPE_UNATT);
if (lpt_iot & 010) fputc ('\r', lpt_unit.fileref);
fputs (lpt_buf, lpt_unit.fileref); /* print buffer */
if (ferror (lpt_unit.fileref)) { /* test error */
perror ("LPT I/O error");
clearerr (lpt_unit.fileref);
return SCPE_IOERR; }
bptr = 0;
for (i = 0; i <= LPT_BSIZE; i++) lpt_buf[i] = 0; /* clear buffer */
lpt_iot = 010; } /* set state */
lpt_unit.pos = ftell (lpt_unit.fileref); /* update position */
return SCPE_OK;
}
/* Reset routine */
t_stat lpt_reset (DEVICE *dptr)
{
int32 i;
iosta = iosta & ~(IOS_PNT | IOS_SPC); /* clear flags */
bptr = 0; /* clear buffer ptr */
for (i = 0; i <= LPT_BSIZE; i++) lpt_buf[i] = 0; /* clear buffer */
lpt_iot = 0; /* clear state */
lpt_rpls = 0;
sim_cancel (&lpt_unit); /* deactivate unit */
return SCPE_OK;
}

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/* pdp1_stddev.c: PDP-1 standard devices
Copyright (c) 1993-2002, Robert M. Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
Except as contained in this notice, the name of Robert M Supnik shall not
be used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Robert M Supnik.
ptr paper tape reader
ptp paper tape punch
tti keyboard
tto teleprinter
06-Oct-02 RMS Revised for V2.10
30-May-02 RMS Widened POS to 32b
29-Nov-01 RMS Added read only unit support
07-Sep-01 RMS Moved function prototypes
10-Jun-01 RMS Fixed comment
30-Oct-00 RMS Standardized device naming
*/
#include "pdp1_defs.h"
#define FIODEC_UC 074
#define FIODEC_LC 072
#define UC 0100 /* upper case */
#define BOTH 0200 /* both cases */
#define CW 0400 /* char waiting */
#define TT_WIDTH 077
extern int32 sbs, ioc, iosta, PF, IO, PC;
extern int32 M[];
int32 ptr_rpls = 0, ptr_stopioe = 0, ptr_state = 0;
int32 ptp_rpls = 0, ptp_stopioe = 0;
int32 tti_state = 0;
int32 tto_rpls = 0, tto_state = 0;
t_stat ptr_svc (UNIT *uptr);
t_stat ptp_svc (UNIT *uptr);
t_stat tti_svc (UNIT *uptr);
t_stat tto_svc (UNIT *uptr);
t_stat ptr_reset (DEVICE *dptr);
t_stat ptp_reset (DEVICE *dptr);
t_stat tti_reset (DEVICE *dptr);
t_stat tto_reset (DEVICE *dptr);
t_stat ptr_boot (int32 unitno, DEVICE *dptr);
/* Character translation tables */
int32 fiodec_to_ascii[128] = {
' ', '1', '2', '3', '4', '5', '6', '7', /* lower case */
'8', '9', 0, 0, 0, 0, 0, 0,
'0', '/', 's', 't', 'u', 'v', 'w', 'x',
'y', 'z', 0, ',', 0, 0, '\t', 0,
'@', 'j', 'k', 'l', 'm', 'n', 'o', 'p',
'q', 'r', 0, 0, '-', ')', '\\', '(',
0, 'a', 'b', 'c', 'd', 'e', 'f', 'g',
'h', 'i', '{', '.', '}', '\b', 0, '\r',
' ', '"', '\'', '~', '#', '!', '&', '<', /* upper case */
'>', '^', 0, 0, 0, 0, 0, 0,
'`', '?', 'S', 'T', 'U', 'V', 'W', 'X',
'Y', 'Z', 0, '=', 0, 0, '\t', 0,
'_', 'J', 'K', 'L', 'M', 'N', 'O', 'P',
'Q', 'R', 0, 0, '+', ']', '|', '[',
0, 'A', 'B', 'C', 'D', 'E', 'F', 'G',
'H', 'I', '{', '*', '}', '\b', 0, '\r' };
int32 ascii_to_fiodec[128] = {
0, 0, 0, 0, 0, 0, 0, 0,
BOTH+075, BOTH+036, 0, 0, 0, BOTH+077, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
BOTH+0, UC+005, UC+001, UC+004, 0, 0, UC+006, UC+002,
057, 055, UC+073, UC+054, 033, 054, 073, 021,
020, 001, 002, 003, 004, 005, 006, 007,
010, 011, 0, 0, UC+007, UC+033, UC+010, UC+021,
040, UC+061, UC+062, UC+063, UC+064, UC+065, UC+066, UC+067,
UC+070, UC+071, UC+041, UC+042, UC+043, UC+044, UC+045, UC+046,
UC+047, UC+050, UC+051, UC+022, UC+023, UC+024, UC+025, UC+026,
UC+027, UC+030, UC+031, UC+057, 056, UC+055, UC+011, UC+040,
UC+020, 061, 062, 063, 064, 065, 066, 067,
070, 071, 041, 042, 043, 044, 045, 046,
047, 050, 051, 022, 023, 024, 025, 026,
027, 030, 031, 0, UC+056, 0, UC+003, BOTH+075 };
/* PTR data structures
ptr_dev PTR device descriptor
ptr_unit PTR unit
ptr_reg PTR register list
*/
UNIT ptr_unit = {
UDATA (&ptr_svc, UNIT_SEQ+UNIT_ATTABLE+UNIT_ROABLE, 0),
SERIAL_IN_WAIT };
REG ptr_reg[] = {
{ ORDATA (BUF, ptr_unit.buf, 18) },
{ FLDATA (DONE, iosta, IOS_V_PTR) },
{ FLDATA (RPLS, ptr_rpls, 0) },
{ ORDATA (STATE, ptr_state, 5), REG_HRO },
{ DRDATA (POS, ptr_unit.pos, 32), PV_LEFT },
{ DRDATA (TIME, ptr_unit.wait, 24), PV_LEFT },
{ FLDATA (STOP_IOE, ptr_stopioe, 0) },
{ NULL } };
DEVICE ptr_dev = {
"PTR", &ptr_unit, ptr_reg, NULL,
1, 10, 31, 1, 8, 8,
NULL, NULL, &ptr_reset,
&ptr_boot, NULL, NULL,
NULL, 0 };
/* PTP data structures
ptp_dev PTP device descriptor
ptp_unit PTP unit
ptp_reg PTP register list
*/
UNIT ptp_unit = {
UDATA (&ptp_svc, UNIT_SEQ+UNIT_ATTABLE, 0), SERIAL_OUT_WAIT };
REG ptp_reg[] = {
{ ORDATA (BUF, ptp_unit.buf, 8) },
{ FLDATA (DONE, iosta, IOS_V_PTP) },
{ FLDATA (RPLS, ptp_rpls, 0) },
{ DRDATA (POS, ptp_unit.pos, 32), PV_LEFT },
{ DRDATA (TIME, ptp_unit.wait, 24), PV_LEFT },
{ FLDATA (STOP_IOE, ptp_stopioe, 0) },
{ NULL } };
DEVICE ptp_dev = {
"PTP", &ptp_unit, ptp_reg, NULL,
1, 10, 31, 1, 8, 8,
NULL, NULL, &ptp_reset,
NULL, NULL, NULL,
NULL, 0 };
/* TTI data structures
tti_dev TTI device descriptor
tti_unit TTI unit
tti_reg TTI register list
*/
UNIT tti_unit = { UDATA (&tti_svc, 0, 0), KBD_POLL_WAIT };
REG tti_reg[] = {
{ ORDATA (BUF, tti_unit.buf, 6) },
{ FLDATA (DONE, iosta, IOS_V_TTI) },
{ ORDATA (STATE, tti_state, 10), REG_HRO },
{ DRDATA (POS, tti_unit.pos, 32), PV_LEFT },
{ DRDATA (TIME, tti_unit.wait, 24), REG_NZ + PV_LEFT },
{ NULL } };
DEVICE tti_dev = {
"TTI", &tti_unit, tti_reg, NULL,
1, 10, 31, 1, 8, 8,
NULL, NULL, &tti_reset,
NULL, NULL, NULL,
NULL, 0 };
/* TTO data structures
tto_dev TTO device descriptor
tto_unit TTO unit
tto_reg TTO register list
*/
UNIT tto_unit = { UDATA (&tto_svc, 0, 0), SERIAL_OUT_WAIT };
REG tto_reg[] = {
{ ORDATA (BUF, tto_unit.buf, 6) },
{ FLDATA (DONE, iosta, IOS_V_TTO) },
{ FLDATA (RPLS, tto_rpls, 0) },
{ ORDATA (STATE, tto_state, 10), REG_HRO },
{ DRDATA (POS, tto_unit.pos, 32), PV_LEFT },
{ DRDATA (TIME, tto_unit.wait, 24), PV_LEFT },
{ NULL } };
DEVICE tto_dev = {
"TTO", &tto_unit, tto_reg, NULL,
1, 10, 31, 1, 8, 8,
NULL, NULL, &tto_reset,
NULL, NULL, NULL,
NULL, 0 };
/* Paper tape reader: IOT routine */
int32 ptr (int32 inst, int32 dev, int32 data)
{
iosta = iosta & ~IOS_PTR; /* clear flag */
if (dev == 0030) return ptr_unit.buf; /* RRB */
ptr_state = (dev == 0002)? 18: 0; /* mode = bin/alp */
ptr_rpls = 0;
ptr_unit.buf = 0; /* clear buffer */
sim_activate (&ptr_unit, ptr_unit.wait);
if (GEN_CPLS (inst)) { /* comp pulse? */
ioc = 0;
ptr_rpls = 1; }
return data;
}
/* Unit service */
t_stat ptr_svc (UNIT *uptr)
{
int32 temp;
if ((ptr_unit.flags & UNIT_ATT) == 0) /* attached? */
return IORETURN (ptr_stopioe, SCPE_UNATT);
if ((temp = getc (ptr_unit.fileref)) == EOF) { /* end of file? */
if (feof (ptr_unit.fileref)) {
if (ptr_stopioe) printf ("PTR end of file\n");
else return SCPE_OK; }
else perror ("PTR I/O error");
clearerr (ptr_unit.fileref);
return SCPE_IOERR; }
ptr_unit.pos = ptr_unit.pos + 1;
if (ptr_state == 0) ptr_unit.buf = temp & 0377; /* alpha */
else if (temp & 0200) { /* binary */
ptr_state = ptr_state - 6;
ptr_unit.buf = ptr_unit.buf | ((temp & 077) << ptr_state); }
if (ptr_state == 0) { /* done? */
if (ptr_rpls) IO = ptr_unit.buf; /* restart? fill IO */
iosta = iosta | IOS_PTR; /* set flag */
sbs = sbs | SB_RQ; /* req seq break */
ioc = ioc | ptr_rpls; } /* restart */
else sim_activate (&ptr_unit, ptr_unit.wait); /* get next char */
return SCPE_OK;
}
/* Reset routine */
t_stat ptr_reset (DEVICE *dptr)
{
ptr_state = 0; /* clear state */
ptr_unit.buf = 0;
ptr_rpls = 0;
iosta = iosta & ~IOS_PTR; /* clear flag */
sim_cancel (&ptr_unit); /* deactivate unit */
return SCPE_OK;
}
/* Bootstrap routine */
#define BOOT_START 07772
#define BOOT_LEN (sizeof (boot_rom) / sizeof (int))
static const int32 boot_rom[] = {
0730002, /* r, rpb + wait */
0327776, /* dio x */
0107776, /* xct x */
0730002, /* rpb + wait */
0760400, /* x, halt */
0607772 /* jmp r */
};
t_stat ptr_boot (int32 unitno, DEVICE *dptr)
{
int32 i;
for (i = 0; i < BOOT_LEN; i++) M[BOOT_START + i] = boot_rom[i];
PC = BOOT_START;
return SCPE_OK;
}
/* Paper tape punch: IOT routine */
int32 ptp (int32 inst, int32 dev, int32 data)
{
iosta = iosta & ~IOS_PTP; /* clear flag */
ptp_rpls = 0;
ptp_unit.buf = (dev == 0006)? ((data >> 12) | 0200): (data & 0377);
sim_activate (&ptp_unit, ptp_unit.wait); /* start unit */
if (GEN_CPLS (inst)) { /* comp pulse? */
ioc = 0;
ptp_rpls = 1; }
return data;
}
/* Unit service */
t_stat ptp_svc (UNIT *uptr)
{
iosta = iosta | IOS_PTP; /* set flag */
sbs = sbs | SB_RQ; /* req seq break */
ioc = ioc | ptp_rpls; /* process restart */
if ((ptp_unit.flags & UNIT_ATT) == 0) /* not attached? */
return IORETURN (ptp_stopioe, SCPE_UNATT);
if (putc (ptp_unit.buf, ptp_unit.fileref) == EOF) { /* I/O error? */
perror ("PTP I/O error");
clearerr (ptp_unit.fileref);
return SCPE_IOERR; }
ptp_unit.pos = ptp_unit.pos + 1;
return SCPE_OK;
}
/* Reset routine */
t_stat ptp_reset (DEVICE *dptr)
{
ptp_unit.buf = 0; /* clear state */
ptp_rpls = 0;
iosta = iosta & ~IOS_PTP; /* clear flag */
sim_cancel (&ptp_unit); /* deactivate unit */
return SCPE_OK;
}
/* Terminal input: IOT routine */
int32 tti (int32 inst, int32 dev, int32 data)
{
iosta = iosta & ~IOS_TTI; /* clear flag */
if (inst & (IO_WAIT | IO_CPLS)) /* wait or sync? */
return (STOP_RSRV << IOT_V_REASON) | (tti_unit.buf & 077);
return tti_unit.buf & 077;
}
/* Unit service */
t_stat tti_svc (UNIT *uptr)
{
int32 in, temp;
sim_activate (&tti_unit, tti_unit.wait); /* continue poll */
if (tti_state & CW) { /* char waiting? */
tti_unit.buf = tti_state & TT_WIDTH; /* return char */
tti_state = tti_state & ~CW; } /* not waiting */
else { if ((temp = sim_poll_kbd ()) < SCPE_KFLAG) return temp;
temp = temp & 0177;
if (temp == 0177) temp = '\b'; /* rubout? bs */
sim_putchar (temp); /* echo */
if (temp == '\r') sim_putchar ('\n'); /* cr? add nl */
in = ascii_to_fiodec[temp]; /* translate char */
if (in == 0) return SCPE_OK; /* no xlation? */
if ((in & BOTH) || ((in & UC) == (tti_state & UC)))
tti_unit.buf = in & TT_WIDTH;
else { tti_unit.buf = (in & UC)? FIODEC_UC: FIODEC_LC;
tti_state = in | CW; } } /* set 2nd waiting */
iosta = iosta | IOS_TTI; /* set flag */
sbs = sbs | SB_RQ; /* req seq break */
PF = PF | 040; /* set prog flag 1 */
tti_unit.pos = tti_unit.pos + 1;
return SCPE_OK;
}
/* Reset routine */
t_stat tti_reset (DEVICE *dptr)
{
tti_unit.buf = 0; /* clear buffer */
tti_state = 0; /* clear state */
iosta = iosta & ~IOS_TTI; /* clear flag */
sim_activate (&tti_unit, tti_unit.wait); /* activate unit */
return SCPE_OK;
}
/* Terminal output: IOT routine */
int32 tto (int32 inst, int32 dev, int32 data)
{
iosta = iosta & ~IOS_TTO; /* clear flag */
tto_rpls = 0;
tto_unit.buf = data & TT_WIDTH; /* load buffer */
sim_activate (&tto_unit, tto_unit.wait); /* activate unit */
if (GEN_CPLS (inst)) { /* comp pulse? */
ioc = 0;
tto_rpls = 1; }
return data;
}
/* Unit service */
t_stat tto_svc (UNIT *uptr)
{
int32 out;
iosta = iosta | IOS_TTO; /* set flag */
sbs = sbs | SB_RQ; /* req seq break */
ioc = ioc | tto_rpls; /* process restart */
if (tto_unit.buf == FIODEC_UC) { /* upper case? */
tto_state = UC;
return SCPE_OK; }
if (tto_unit.buf == FIODEC_LC) { /* lower case? */
tto_state = 0;
return SCPE_OK; }
out = fiodec_to_ascii[tto_unit.buf | tto_state]; /* translate */
if (out == 0) return SCPE_OK; /* no translation? */
sim_putchar (out);
tto_unit.pos = tto_unit.pos + 1;
if (out == '\r') { /* cr? add lf */
sim_putchar ('\n');
tto_unit.pos = tto_unit.pos + 1; }
return SCPE_OK;
}
/* Reset routine */
t_stat tto_reset (DEVICE *dptr)
{
tto_unit.buf = 0; /* clear buffer */
tto_state = 0; /* clear state */
tto_rpls = 0;
iosta = iosta & ~IOS_TTO; /* clear flag */
sim_cancel (&tto_unit); /* deactivate unit */
return SCPE_OK;
}

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/* pdp1_sys.c: PDP-1 simulator interface
Copyright (c) 1993-2002, Robert M. Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
Except as contained in this notice, the name of Robert M Supnik shall not
be used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Robert M Supnik.
20-Aug-02 RMS Added DECtape support
17-Sep-01 RMS Removed multiconsole support
13-Jul-01 RMS Fixed RIM loader format
27-May-01 RMS Added multiconsole support
14-Mar-01 RMS Revised load/dump interface (again)
30-Oct-00 RMS Added support for examine to file
27-Oct-98 RMS V2.4 load interface
20-Oct-97 RMS Fixed endian-dependence in RIM loader
(found by Michael Somos)
*/
#include "pdp1_defs.h"
#include <ctype.h>
extern DEVICE cpu_dev;
extern DEVICE ptr_dev, ptp_dev;
extern DEVICE tti_dev, tto_dev;
extern DEVICE lpt_dev, dt_dev;
extern UNIT cpu_unit;
extern REG cpu_reg[];
extern int32 M[];
extern int32 PC;
extern int32 ascii_to_fiodec[], fiodec_to_ascii[];
extern int32 sc_map[];
/* SCP data structures and interface routines
sim_name simulator name string
sim_PC pointer to saved PC register descriptor
sim_emax number of words for examine
sim_devices array of pointers to simulated devices
sim_stop_messages array of pointers to stop messages
sim_load binary loader
*/
char sim_name[] = "PDP-1";
REG *sim_PC = &cpu_reg[0];
int32 sim_emax = 1;
DEVICE *sim_devices[] = {
&cpu_dev,
&ptr_dev,
&ptp_dev,
&tti_dev,
&tto_dev,
&lpt_dev,
&dt_dev,
NULL };
const char *sim_stop_messages[] = {
"Unknown error",
"Undefined instruction",
"HALT instruction",
"Breakpoint",
"Nested XCT's",
"Nested indirect addresses",
"Infinite wait state" };
/* Binary loader
At the moment, implements RIM loader format
*/
int32 getword (FILE *fileref)
{
int32 i, tmp, word;
word = 0;
for (i = 0; i < 3;) {
if ((tmp = getc (fileref)) == EOF) return -1;
if (tmp & 0200) {
word = (word << 6) | (tmp & 077);
i++; } }
return word;
}
t_stat sim_load (FILE *fileref, char *cptr, char *fnam, int flag)
{
int32 origin, val;
if ((*cptr != 0) || (flag != 0)) return SCPE_ARG;
for (;;) {
if ((val = getword (fileref)) < 0) return SCPE_FMT;
if (((val & 0770000) == 0320000) || /* DIO? */
((val & 0770000) == 0240000)) { /* DAC? - incorrect */
origin = val & 07777;
if ((val = getword (fileref)) < 0) return SCPE_FMT;
if (MEM_ADDR_OK (origin)) M[origin++] = val; }
else if ((val & 0770000) == 0600000) { /* JMP? */
PC = val & 007777;
break; }
}
return SCPE_OK; /* done */
}
/* Symbol tables */
#define I_V_FL 18 /* inst class */
#define I_M_FL 07 /* class mask */
#define I_V_NPN 0 /* no operand */
#define I_V_IOT 1 /* IOT */
#define I_V_LAW 2 /* LAW */
#define I_V_MRF 3 /* memory reference */
#define I_V_MRI 4 /* mem ref no ind */
#define I_V_OPR 5 /* OPR */
#define I_V_SKP 6 /* skip */
#define I_V_SHF 7 /* shift */
#define I_NPN (I_V_NPN << I_V_FL) /* no operand */
#define I_IOT (I_V_IOT << I_V_FL) /* IOT */
#define I_LAW (I_V_LAW << I_V_FL) /* LAW */
#define I_MRF (I_V_MRF << I_V_FL) /* memory reference */
#define I_MRI (I_V_MRI << I_V_FL) /* mem ref no ind */
#define I_OPR (I_V_OPR << I_V_FL) /* OPR */
#define I_SKP (I_V_SKP << I_V_FL) /* skip */
#define I_SHF (I_V_SHF << I_V_FL) /* shift */
static const int32 masks[] = {
0777777, 0763777, 0760000, 0760000,
0770000, 0760017, 0760077, 0777000 };
static const char *opcode[] = {
"AND", "IOR", "XOR", "XCT", /* mem refs */
"LAC", "LIO", "DAC", "DAP",
"DIP", "DIO", "DZM", "ADD",
"SUB", "IDX", "ISP", "SAD",
"SAS", "MUL", "DIV", "JMP", "JSP",
"CAL", "JDA", /* mem ref no ind */
"IOH", "RPA", "RPB", "RRB", /* I/O instructions */
"PPA", "PPB", "TYO", "TYI",
"LSM", "ESM", "CBS",
"LEM", "EEM", "CKS",
"MSE", "MLC", "MRD", "MWR", "MRS",
"SKP", "SKP I", "CLO",
"SFT", "LAW", "OPR",
"RAL", "RIL", "RCL", /* shifts */
"SAL", "SIL", "SCL",
"RAR", "RIR", "RCR",
"SAR", "SIR", "SCR",
"SZF1", "SZF2", "SZF3", /* skips */
"SZF4", "SZF5", "SZF6", "SZF7",
"SZS1", "SZS1 SZF1", "SZS1 SZF2", "SZS1 SZ3",
"SZS1 SZF4", "SZS1 SZF5", "SZS1 SZF6", "SZS1 SZF7",
"SZS2", "SZS2 SZF1", "SZS2 SZF2", "SZS2 SZ3",
"SZS2 SZF4", "SZS2 SZF5", "SZS2 SZF6", "SZS2 SZF7",
"SZS3", "SZS3 SZF1", "SZS3 SZF2", "SZS3 SZ3",
"SZS3 SZF4", "SZS3 SZF5", "SZS3 SZF6", "SZS3 SZF7",
"SZS4", "SZS4 SZF1", "SZS4 SZF2", "SZS4 SZ3",
"SZS4 SZF4", "SZS4 SZF5", "SZS4 SZF6", "SZS4 SZF7",
"SZS5", "SZS5 SZF1", "SZS5 SZF2", "SZS5 SZ3",
"SZS5 SZF4", "SZS5 SZF5", "SZS5 SZF6", "SZS5 SZF7",
"SZS6", "SZS6 SZF1", "SZS6 SZF2", "SZS6 SZ3",
"SZS6 SZF4", "SZS6 SZF5", "SZS6 SZF6", "SZS6 SZF7",
"SZS7", "SZS7 SZF1", "SZS7 SZF2", "SZS7 SZ3",
"SZS7 SZF4", "SZS7 SZF5", "SZS7 SZF6", "SZS7 SZF7",
"CLF1", "CLF2", "CLF3", /* operates */
"CLF4", "CLF5", "CLF6", "CLF7",
"STF1", "STF2", "STF3",
"STF4", "STF5", "STF6", "STF7",
"SZA", "SPA", "SMA", /* encode only */
"SZO", "SPI", "I",
"LAP", "CLA", "HLT",
"CMA", "LAT", "CLI",
NULL, NULL, /* decode only */
NULL };
static const int32 opc_val[] = {
0020000+I_MRF, 0040000+I_MRF, 0060000+I_MRF, 0100000+I_MRF,
0200000+I_MRF, 0220000+I_MRF, 0240000+I_MRF, 0260000+I_MRF,
0300000+I_MRF, 0320000+I_MRF, 0340000+I_MRF, 0400000+I_MRF,
0420000+I_MRF, 0440000+I_MRF, 0460000+I_MRF, 0500000+I_MRF,
0520000+I_MRF, 0540000+I_MRF, 0560000+I_MRF, 0600000+I_MRF, 0620000+I_MRF,
0160000+I_MRI, 0170000+I_MRI,
0730000+I_NPN, 0720001+I_IOT, 0720002+I_IOT, 0720030+I_IOT,
0720005+I_IOT, 0720006+I_IOT, 0720003+I_IOT, 0720004+I_IOT,
0720054+I_NPN, 0720055+I_NPN, 0720056+I_NPN,
0720074+I_NPN, 0724074+I_NPN, 0720033+I_NPN,
0720301+I_NPN, 0720401+I_NPN, 0720501+I_NPN, 0720601+I_NPN, 0720701+I_NPN,
0640000+I_NPN, 0650000+I_NPN, 0651600+I_NPN,
0660000+I_NPN, 0700000+I_LAW, 0760000+I_NPN,
0661000+I_SHF, 0662000+I_SHF, 0663000+I_SHF,
0665000+I_SHF, 0666000+I_SHF, 0667000+I_SHF,
0671000+I_SHF, 0672000+I_SHF, 0673000+I_SHF,
0675000+I_SHF, 0676000+I_SHF, 0677000+I_SHF,
0640001+I_SKP, 0640002+I_SKP, 0640003+I_SKP,
0640004+I_SKP, 0640005+I_SKP, 0640006+I_SKP, 0640007+I_SKP,
0640010+I_SKP, 0640011+I_SKP, 0640012+I_SKP, 0640013+I_SKP,
0640014+I_SKP, 0640015+I_SKP, 0640016+I_SKP, 0640017+I_SKP,
0640020+I_SKP, 0640021+I_SKP, 0640022+I_SKP, 0640023+I_SKP,
0640024+I_SKP, 0640025+I_SKP, 0640026+I_SKP, 0640027+I_SKP,
0640030+I_SKP, 0640031+I_SKP, 0640032+I_SKP, 0640033+I_SKP,
0640034+I_SKP, 0640035+I_SKP, 0640036+I_SKP, 0640037+I_SKP,
0640040+I_SKP, 0640041+I_SKP, 0640042+I_SKP, 0640043+I_SKP,
0640044+I_SKP, 0640045+I_SKP, 0640046+I_SKP, 0640047+I_SKP,
0640050+I_SKP, 0640051+I_SKP, 0640052+I_SKP, 0640053+I_SKP,
0640054+I_SKP, 0640055+I_SKP, 0640056+I_SKP, 0640057+I_SKP,
0640060+I_SKP, 0640061+I_SKP, 0640062+I_SKP, 0640063+I_SKP,
0640064+I_SKP, 0640065+I_SKP, 0640066+I_SKP, 0640067+I_SKP,
0640070+I_SKP, 0640071+I_SKP, 0640072+I_SKP, 0640073+I_SKP,
0640074+I_SKP, 0640075+I_SKP, 0640076+I_SKP, 0640077+I_SKP,
0760001+I_OPR, 0760002+I_OPR, 0760003+I_OPR,
0760004+I_OPR, 0760005+I_OPR, 0760006+I_OPR, 0760007+I_OPR,
0760011+I_OPR, 0760012+I_OPR, 0760013+I_OPR,
0760014+I_OPR, 0760015+I_OPR, 0760016+I_OPR, 0760017+I_OPR,
0640100+I_SKP, 0640200+I_SKP, 0640400+I_SKP, /* encode only */
0641000+I_SKP, 0642000+I_SKP, 0010000+I_SKP,
0760100+I_OPR, 0760200+I_OPR, 0760400+I_OPR,
0761000+I_OPR, 0762000+I_OPR, 0764000+I_OPR,
0640000+I_SKP, 0760000+I_OPR, /* decode only */
-1 };
/* Operate or skip decode
Inputs:
*of = output stream
inst = mask bits
class = instruction class code
sp = space needed?
Outputs:
status = space needed?
*/
int32 fprint_opr (FILE *of, int32 inst, int32 class, int32 sp)
{
int32 i, j;
for (i = 0; opc_val[i] >= 0; i++) { /* loop thru ops */
j = (opc_val[i] >> I_V_FL) & I_M_FL; /* get class */
if ((j == class) && (opc_val[i] & inst)) { /* same class? */
inst = inst & ~opc_val[i]; /* mask bit set? */
fprintf (of, (sp? " %s": "%s"), opcode[i]);
sp = 1; } }
return sp;
}
/* Symbolic decode
Inputs:
*of = output stream
addr = current PC
*val = pointer to values
*uptr = pointer to unit
sw = switches
Outputs:
return = status code
*/
#define FMTASC(x) ((x) < 040)? "<%03o>": "%c", (x)
#define SIXTOASC(x) fiodec_to_ascii[x]
#define ASCTOSIX(x) (ascii_to_fiodec[x] & 077)
t_stat fprint_sym (FILE *of, t_addr addr, t_value *val,
UNIT *uptr, int32 sw)
{
int32 cflag, i, j, sp, inst, disp, ma;
inst = val[0];
cflag = (uptr == NULL) || (uptr == &cpu_unit);
if (sw & SWMASK ('A')) { /* ASCII? */
if (inst > 0377) return SCPE_ARG;
fprintf (of, FMTASC (inst & 0177));
return SCPE_OK; }
if (sw & SWMASK ('C')) { /* character? */
fprintf (of, "%c", SIXTOASC ((inst >> 12) & 077));
fprintf (of, "%c", SIXTOASC ((inst >> 6) & 077));
fprintf (of, "%c", SIXTOASC (inst & 077));
return SCPE_OK; }
if (!(sw & SWMASK ('M'))) return SCPE_ARG;
/* Instruction decode */
disp = inst & 007777;
ma = (addr & EPCMASK) | disp;
for (i = 0; opc_val[i] >= 0; i++) { /* loop thru ops */
j = (opc_val[i] >> I_V_FL) & I_M_FL; /* get class */
if ((opc_val[i] & 0777777) == (inst & masks[j])) { /* match? */
switch (j) { /* case on class */
case I_V_NPN: /* no operands */
fprintf (of, "%s", opcode[i]); /* opcode */
break;
case I_V_IOT: /* IOT */
disp = (inst - opc_val[i]) & 017777;
if (disp == IA) fprintf (of, "%s I", opcode[i]);
else if (disp) fprintf (of, "%s %-o", opcode[i], disp);
else fprintf (of, "%s", opcode[i]);
break;
case I_V_LAW: /* LAW */
cflag = 0; /* fall thru to MRF */
case I_V_MRF: /* mem ref */
fprintf (of, "%s%s%-o", opcode[i],
((inst & IA)? " I ": " "), (cflag? ma: disp));
break;
case I_V_MRI: /* mem ref no ind */
fprintf (of, "%s %-o", opcode[i], (cflag? ma: disp));
break;
case I_V_OPR: /* operates */
sp = fprint_opr (of, inst & 007700, j, 0);
if (opcode[i]) fprintf (of, (sp? " %s": "%s"), opcode[i]);
break;
case I_V_SKP: /* skips */
sp = fprint_opr (of, inst & 007700, j, 0);
if (opcode[i]) sp = fprintf (of, (sp? " %s": "%s"), opcode[i]);
if (inst & IA) fprintf (of, sp? " I": "I");
break;
case I_V_SHF: /* shifts */
fprintf (of, "%s %-d", opcode[i], sc_map[inst & 0777]);
break; } /* end case */
return SCPE_OK; } /* end if */
} /* end for */
return SCPE_ARG;
}
/* Get 18b signed number
Inputs:
*cptr = pointer to input string
*sign = pointer to sign
*status = pointer to error status
Outputs:
val = output value
*/
t_value get_sint (char *cptr, int32 *sign, t_stat *status)
{
*sign = 1;
if (*cptr == '+') {
*sign = 0;
cptr++; }
else if (*cptr == '-') {
*sign = -1;
cptr++; }
return get_uint (cptr, 8, 0777777, status);
}
/* Symbolic input
Inputs:
*cptr = pointer to input string
addr = current PC
uptr = pointer to unit
*val = pointer to output values
sw = switches
Outputs:
status = error status
*/
t_stat parse_sym (char *cptr, t_addr addr, UNIT *uptr, t_value *val, int32 sw)
{
int32 cflag, d, i, j, k, sign;
t_stat r;
static int32 sc_enc[10] = { 0, 01, 03, 07, 017, 037, 077, 0177, 0377, 0777 };
char gbuf[CBUFSIZE];
cflag = (uptr == NULL) || (uptr == &cpu_unit);
while (isspace (*cptr)) cptr++;
for (i = 1; (i < 3) && (cptr[i] != 0); i++)
if (cptr[i] == 0) for (j = i + 1; j <= 3; j++) cptr[j] = 0;
if ((sw & SWMASK ('A')) || ((*cptr == '\'') && cptr++)) { /* ASCII char? */
if (cptr[0] == 0) return SCPE_ARG; /* must have 1 char */
val[0] = (t_value) cptr[0];
return SCPE_OK; }
if ((sw & SWMASK ('C')) || ((*cptr == '"') && cptr++)) { /* sixbit string? */
if (cptr[0] == 0) return SCPE_ARG; /* must have 1 char */
val[0] = (ASCTOSIX (cptr[0] & 077) << 12) |
(ASCTOSIX (cptr[1] & 077) << 6) |
ASCTOSIX (cptr[2] & 077);
return SCPE_OK; }
/* Symbolic input, continued */
cptr = get_glyph (cptr, gbuf, 0); /* get opcode */
for (i = 0; (opcode[i] != NULL) && (strcmp (opcode[i], gbuf) != 0) ; i++) ;
if (opcode[i] == NULL) return SCPE_ARG;
val[0] = opc_val[i] & 0777777; /* get value */
j = (opc_val[i] >> I_V_FL) & I_M_FL; /* get class */
switch (j) { /* case on class */
case I_V_LAW: /* LAW */
cflag = 0; /* fall through */
case I_V_MRF: case I_V_MRI: /* mem ref */
cptr = get_glyph (cptr, gbuf, 0); /* get next field */
if ((j != I_V_MRI) && strcmp (gbuf, "I") == 0) { /* indirect? */
val[0] = val[0] | IA;
cptr = get_glyph (cptr, gbuf, 0); }
d = get_uint (gbuf, 8, AMASK, &r);
if (r != SCPE_OK) return SCPE_ARG;
if (d <= DAMASK) val[0] = val[0] | d;
else if (cflag && (((addr ^ d) & EPCMASK) == 0))
val[0] = val[0] | (d & DAMASK);
else return SCPE_ARG;
break;
case I_V_SHF: /* shift */
cptr = get_glyph (cptr, gbuf, 0);
d = get_uint (gbuf, 10, 9, &r);
if (r != SCPE_OK) return SCPE_ARG;
val[0] = val[0] | sc_enc[d];
break;
case I_V_NPN: case I_V_IOT: case I_V_OPR: case I_V_SKP:
for (cptr = get_glyph (cptr, gbuf, 0); gbuf[0] != 0;
cptr = get_glyph (cptr, gbuf, 0)) {
for (i = 0; (opcode[i] != NULL) &&
(strcmp (opcode[i], gbuf) != 0) ; i++) ;
if (opcode[i] != NULL) {
k = opc_val[i] & 0777777;
if ((k != IA) && (((k ^ val[0]) & 0760000) != 0))
return SCPE_ARG;
val[0] = val[0] | k; }
else { d = get_sint (gbuf, &sign, &r);
if (r != SCPE_OK) return SCPE_ARG;
if (sign == 0) val[0] = val[0] + d;
else if (sign < 0) val[0] = val[0] - d;
else val[0] = val[0] | d; } }
break; } /* end case */
if (*cptr != 0) return SCPE_ARG; /* junk at end? */
return SCPE_OK;
}

7
sim_rev.h
View file

@ -32,6 +32,13 @@
patch date module(s) and fix(es)
1 21-Nov-02 pdp1_stddev.c: changed typewriter to half duplex
(found by Derek Peschel)
pdp10_tu.c:
-- fixed bug in bootstrap (reported by Michael Thompson)
-- fixed bug in read (reported by Harris Newman)
0 15-Nov-02 SCP and libraries
scp.c:
-- added Telnet console support