ALL: Revert "ALL: make sure all useful state is in simh registers while processing events"

This reverts commit 5551a0dd9c.

The original idea was that the state being put into simh registers would be required to have all useful information available when remote console executed commands.  These steps were taken from the code that sim_instr() executed as it was exiting.  After this change was made it was realized that once a remote console command executed it might change state that directly affected instruction execution.  To solve this, the logic that executes before the instructions in sim_instr() would then need to be executed whenever the event dispatch processing completed.  This approach is messy, burdensome and potentially a lot of overhead for every event dispatch even though almost none of the event dispatches would be for remote console command execution.  A completely different approach was suggested by J. David Bryan.  That alternative approach would be to have remote console commands execute outside of the sim_instr() routine.  Thus allowing the existing prelude and postlude code in sim_instr() to be performed naturally and let the remote console activities run in the same context as all other simh commands.  Recent changes to scp and sim_console implement this alternative approach and thus these original changes are completely irrelevant and are thus being removed.

ALTAIR/altair_cpu.c

@@ -310,8 +310,6 @@ t_stat sim_instr (void)
 
     while (reason == 0) {                               /* loop until halted */
         if (sim_interval <= 0) {                        /* check clock queue */
-            /* make sure all useful state is in simh registers while processing events */
-            saved_PC = PC;
             if ((reason = sim_process_event ())) break;
         }
 

GRI/gri_cpu.c

@@ -417,9 +417,6 @@ ao_update ();                                           /* update AO */
 while (reason == 0) {                                   /* loop until halted */
 
     if (sim_interval <= 0) {                            /* check clock queue */
-        /* make sure all useful state is in simh registers while processing events */
-        ao_update ();                                   /* update AO */
-        scq_r->qptr = scq_p;                            /* update sc q ptr */
         if ((reason = sim_process_event ()))
             break;
         }

H316/h316_cpu.c

@@ -441,11 +441,6 @@ reason = 0;
 while (reason == 0) {                                   /* loop until halted */
 
 if (sim_interval <= 0) {                                /* check clock queue */
-    /* make sure all useful state is in simh registers while processing events */
-    saved_AR = AR & DMASK;
-    saved_BR = BR & DMASK;
-    saved_XR = XR & DMASK;
-    pcq_r->qptr = pcq_p;                                /* update pc q ptr */
     if ((reason = sim_process_event ()))
         break;
     }

I1401/i1401_cpu.c

@@ -550,12 +550,6 @@ while (reason == 0) {                                   /* loop until halted */
 
     saved_IS = IS;                                      /* commit prev instr */
     if (sim_interval <= 0) {                            /* check clock queue */
-        /* make sure all useful state is in simh registers while processing events */
-        as_err = ADDR_ERR (AS);                         /* get addr err flags */
-        bs_err = ADDR_ERR (BS);
-        AS = AS & ADDRMASK;                             /* clean addresses */
-        BS = BS & ADDRMASK;
-        pcq_r->qptr = pcq_p;                            /* update pc q ptr */
         if ((reason = sim_process_event ()))
             break;
         }

I1620/i1620_cpu.c

@@ -488,9 +488,6 @@ while (reason == 0) {                                   /* loop until halted */
 
     saved_PC = PC;                                      /* commit prev instr */
     if (sim_interval <= 0) {                            /* check clock queue */
-        /* make sure all useful state is in simh registers while processing events */
-        pcq_r->qptr = pcq_p;                            /* update pc q ptr */
-        upd_ind ();
         if ((reason = sim_process_event ()))
             break;
         }

I7094/i7094_cpu.c

@@ -659,8 +659,6 @@ while (reason == SCPE_OK) {                             /* loop until error */
         }
 
     if (sim_interval <= 0) {                            /* intv cnt expired? */
-        /* make sure all useful state is in simh registers while processing events */
-        pcq_r->qptr = pcq_p;                            /* update pc q ptr */
         if ((reason = sim_process_event ()))            /* process events */
             break;
         chtr_pend = chtr_eval (NULL);                   /* eval chan traps */

Interdata/id16_cpu.c

@@ -599,10 +599,6 @@ while (reason == 0) {                                   /* loop until halted */
     int32 sr, st;
 
     if (sim_interval <= 0) {                            /* check clock queue */
-        /* make sure all useful state is in simh registers while processing events */
-        PSW = BUILD_PSW (cc);
-        PC = PC & VAMASK;
-        pcq_r->qptr = pcq_p;                            /* update pc q ptr */
         if ((reason = sim_process_event ()))
             break;
         int_eval ();

Interdata/id32_cpu.c

@@ -658,11 +658,6 @@ while (reason == 0) {                                   /* loop until halted */
     int32 sr, st;
 
     if (sim_interval <= 0) {                            /* check clock queue */
-        /* make sure all useful state is in simh registers while processing events */
-        PSW = BUILD_PSW (cc);
-        PC = PC & VAMASK;
-        set_r_display (R);
-        pcq_r->qptr = pcq_p;                            /* update pc q ptr */
         if ((reason = sim_process_event ()))
             break;
         int_eval ();

LGP/lgp_cpu.c

@@ -283,8 +283,6 @@ if (lgp21_sov) {                                        /* stop sense pending? *
 
 do {
     if (sim_interval <= 0) {                            /* check clock queue */
-        /* make sure all useful state is in simh registers while processing events */
-        pcq_r->qptr = pcq_p;                            /* update pc q ptr */
         if ((r = sim_process_event ()))
             break;
         }

NOVA/eclipse_cpu.c

@@ -737,8 +737,6 @@ if (MapInit == 0) {
 
 while (reason == 0) {                                   /* loop until halted */
 if (sim_interval <= 0) {                                /* check clock queue */
-    /* make sure all useful state is in simh registers while processing events */
-    saved_PC = PC;
     if ((reason = sim_process_event ())) 
         break;
 }

NOVA/nova_cpu.c

@@ -428,9 +428,6 @@ reason = 0;
 while (reason == 0) {                                   /* loop until halted */
 
     if (sim_interval <= 0) {                            /* check clock queue */
-        /* make sure all useful state is in simh registers while processing events */
-        saved_PC = PC;
-        pcq_r->qptr = pcq_p;                            /* update pc q ptr */
         if ( (reason = sim_process_event ()) )
             break;
         }

PDP1/pdp1_cpu.c

@@ -546,8 +546,6 @@ reason = 0;
 while (reason == 0) {                                   /* loop until halted */
 
     if (sim_interval <= 0) {                            /* check clock queue */
-        /* Make sure all intermediate state is visible in simh registers */
-        pcq_r->qptr = pcq_p;                            /* update pc q ptr */
         if ((reason = sim_process_event ()))
             break;
         sbs_lvl = sbs_eval ();                          /* eval sbs system */

PDP18B/pdp18b_cpu.c

@@ -597,9 +597,6 @@ while (reason == 0) {                                   /* loop until halted */
     int32 link_init, fill;
 
     if (sim_interval <= 0) {                            /* check clock queue */
-        /* Make sure all intermediate state is visible in simh registers */
-        iors = upd_iors ();                             /* get IORS */
-        pcq_r->qptr = pcq_p;                            /* update pc q ptr */
         if ((reason = sim_process_event ()))
             break;
         api_int = api_eval (&int_pend);                 /* eval API */

PDP8/pdp8_cpu.c

@@ -339,12 +339,6 @@ reason = 0;
 while (reason == 0) {                                   /* loop until halted */
 
     if (sim_interval <= 0) {                            /* check clock queue */
-        /* Make sure all intermediate state is visible in simh registers */
-        saved_PC = IF | (PC & 07777);                   /* save copies */
-        saved_DF = DF & 070000;
-        saved_LAC = LAC & 017777;
-        saved_MQ = MQ & 07777;
-        pcq_r->qptr = pcq_p;                            /* update pc q ptr */
         if ((reason = sim_process_event ()))
             break;
         }

S3/s3_cpu.c

@@ -521,8 +521,6 @@ reason = 0;
 
 while (reason == 0) {                                   /* loop until halted */
 if (sim_interval <= 0) {                                /* check clock queue */
-    /* make sure all useful state is in simh registers while processing events */
-    saved_PC = PC;
     if ((reason = sim_process_event ())) break;
 }
 

SDS/sds_cpu.c

@@ -382,8 +382,6 @@ while (reason == 0) {                                   /* loop until halted */
         }
 
     if (sim_interval <= 0) {                            /* event queue? */
-        /* make sure all useful state is in simh registers while processing events */
-        pcq_r->qptr = pcq_p;                            /* update pc q ptr */
         if ((reason = sim_process_event ()))            /* process */
             break;
         int_reqhi = api_findreq ();                     /* recalc int req */

TX-0/tx0_cpu.c

@@ -462,8 +462,6 @@ t_stat sim_instr (void)
     while (reason == 0) {                                   /* loop until halted */
 
         if (sim_interval <= 0) {                            /* check clock queue */
-            /* make sure all useful state is in simh registers while processing events */
-            pcq_r->qptr = pcq_p;                            /* update pc q ptr */
             reason = sim_process_event ();
             if (reason != SCPE_OK)
                 break;

alpha/alpha_cpu.c

@@ -393,11 +393,6 @@ while (reason == 0) {
         }
 
     if (sim_interval <= 0) {                            /* chk clock queue */
-        /* make sure all useful state is in simh registers while processing events */
-        pcc_l = pcc_l & M32;
-        pcq_r->qptr = pcq_p;                            /* update pc q ptr */
-        pc_align = ((uint32) PC) & 3;                   /* separate PC<1:0> */
-        PC = PC & 0xFFFFFFFFFFFFFFFC;
         if ((reason = sim_process_event ())) break;
         intr_summ = pal_eval_intr (1);                  /* eval interrupts */
         }

sigma/sigma_cpu.c

@@ -433,10 +433,6 @@ while (reason == 0) {                                   /* loop until stop */
         }
 
     if (sim_interval <= 0) {                            /* event queue? */
-        /* make sure all useful state is in simh registers while processing events */
-        pcq_r->qptr = pcq_p;                            /* update pc q ptr */
-        cpu_assemble_PSD ();                            /* visible PSD */
-        set_rf_display (R);                             /* visible registers */
         if (reason = sim_process_event ())              /* process */
             break;
         int_hireq = io_eval_int ();                     /* re-evaluate intr */