PDP-1: Added register descriptions to all devices.
This commit is contained in:
Ray Jewhurst
Mark Pizzolato
parent
3fadb7e376
commit
54b3ca04a1
7 changed files with 104 additions and 103 deletions
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@ -59,7 +59,7 @@ UNIT clk_unit = {
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};
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REG clk_reg[] = {
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{ ORDATA (CNTR, clk_cntr, 16) },
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{ ORDATAD (CNTR, clk_cntr, 16, "clock counter, 0-59999(base 10)") },
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{ DRDATA (SBS32LVL, clk32ms_sbs, 4), REG_HRO },
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{ DRDATA (SBS1MLVL, clk1min_sbs, 4), REG_HRO },
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{ NULL }
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@ -434,41 +434,41 @@ const int32 byt_shf[4] = { 0, 0, 6, 12 };
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UNIT cpu_unit = { UDATA (NULL, UNIT_FIX + UNIT_BINK, MAXMEMSIZE) };
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REG cpu_reg[] = {
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{ ORDATA (PC, PC, ASIZE) },
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{ ORDATA (AC, AC, 18) },
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{ ORDATA (IO, IO, 18) },
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{ ORDATAD (PC, PC, ASIZE, "program counter") },
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{ ORDATAD (AC, AC, 18, "accumulator") },
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{ ORDATAD (IO, IO, 18, "I/O register") },
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{ ORDATA (MA, MA, 16) },
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{ ORDATA (MB, MB, 18) },
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{ FLDATA (OV, OV, 0) },
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{ ORDATA (PF, PF, 8) },
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{ ORDATA (SS, SS, 6) },
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{ ORDATA (TA, TA, ASIZE) },
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{ ORDATA (TW, TW, 18) },
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{ FLDATA (EXTM, extm, 0) },
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{ FLDATA (RNGM, PF, PF_V_RNG) },
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{ FLDATA (L, PF, PF_V_L) },
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{ FLDATA (RM, rm, 0) },
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{ ORDATA (RMASK, rmask, 18) },
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{ ORDATA (RTB, rtb, 18) },
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{ BRDATA (RNAME, rname, 8, 2, RN45_SIZE) },
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{ FLDATA (SBON, sbs, SB_V_ON) },
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{ FLDATA (SBRQ, sbs, SB_V_RQ) },
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{ FLDATA (SBIP, sbs, SB_V_IP) },
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{ ORDATA (SBSREQ, sbs_req, 16) },
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{ ORDATA (SBSENB, sbs_enb, 16) },
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{ ORDATA (SBSACT, sbs_act, 16) },
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{ ORDATA (IOSTA, iosta, 18), REG_RO },
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{ FLDATAD (OV, OV, 0, "overflow flag") },
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{ ORDATAD (PF, PF, 8, "programs flags <1:6>") },
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{ ORDATAD (SS, SS, 6, "sense switches <1:6>") },
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{ ORDATAD (TA, TA, ASIZE, "address switches") },
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{ ORDATAD (TW, TW, 18, "test word (front panel switches)") },
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{ FLDATAD (EXTM, extm, 0, "extend mode") },
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{ FLDATAD (RNGM, PF, PF_V_RNG, "ring mode (PDP-1D only)") },
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{ FLDATAD (L, PF, PF_V_L, "link (PDP-1D #45 only)") },
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{ FLDATAD (RM, rm, 0, "restrict mode (PDP-1D)") },
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{ ORDATAD (RMASK, rmask, 18, "restrict memory mask (PDP-1D)") },
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{ ORDATAD (RTB, rtb, 18, "restrict trap buffer (PDP-1D #45 only)") },
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{ BRDATAD (RNAME, rname, 8, 2, RN45_SIZE, "rename map (PDP-1D #45 only)") },
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{ FLDATAD (SBON, sbs, SB_V_ON, "sequence break enable") },
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{ FLDATAD (SBRQ, sbs, SB_V_RQ, "sequence break request") },
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{ FLDATAD (SBIP, sbs, SB_V_IP, "sequence break in progress") },
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{ ORDATAD (SBSREQ, sbs_req, 16, "pending sequence break requests") },
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{ ORDATAD (SBSENB, sbs_enb, 16, "enabled sequence break levels") },
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{ ORDATAD (SBSACT, sbs_act, 16, "active sequence break levels") },
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{ ORDATAD (IOSTA, iosta, 18, "I/O status register"), REG_RO },
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{ ORDATA (CPLS, cpls, 6) },
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{ FLDATA (IOH, ioh, 0) },
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{ FLDATA (IOS, ios, 0) },
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{ BRDATA (PCQ, pcq, 8, ASIZE, PCQ_SIZE), REG_RO+REG_CIRC },
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{ FLDATAD (IOH, ioh, 0, "I/O halt in progress") },
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{ FLDATAD (IOS, ios, 0, "I/O synchronizer (completion)") },
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{ BRDATAD (PCQ, pcq, 8, ASIZE, PCQ_SIZE, "PC prior to last jump or interrupt; most recent PC change first"), REG_RO+REG_CIRC },
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{ ORDATA (PCQP, pcq_p, 6), REG_HRO },
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{ FLDATA (STOP_INST, stop_inst, 0) },
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{ FLDATA (SBS_INIT, sbs_init, SB_V_ON) },
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{ FLDATA (EXTM_INIT, extm_init, 0) },
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{ DRDATA (XCT_MAX, xct_max, 8), PV_LEFT + REG_NZ },
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{ DRDATA (IND_MAX, ind_max, 8), PV_LEFT + REG_NZ },
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{ ORDATA (WRU, sim_int_char, 8) },
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{ FLDATAD (STOP_INST, stop_inst, 0, "stop on undefined instruction") },
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{ FLDATAD (SBS_INIT, sbs_init, SB_V_ON, "initial state of sequence break enable") },
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{ FLDATAD (EXTM_INIT, extm_init, 0, "initial state of extend mode") },
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{ DRDATAD (XCT_MAX, xct_max, 8, "maximum XCT chain"), PV_LEFT + REG_NZ },
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{ DRDATAD (IND_MAX, ind_max, 8, "maximum nested indirect addresses"), PV_LEFT + REG_NZ },
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{ ORDATAD (WRU, sim_int_char, 8, "interrupt character") },
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{ NULL }
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};
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@ -72,11 +72,11 @@ void dcs_scan_next (t_bool unlk);
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UNIT dcs_unit = { UDATA (&dcsi_svc, UNIT_ATTABLE, 0) };
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REG dcs_reg[] = {
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{ BRDATA (BUF, dcs_buf, 8, 8, DCS_LINES) },
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{ BRDATA (FLAGS, dcs_flg, 8, 1, DCS_LINES) },
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{ FLDATA (SCNF, iosta, IOS_V_DCS) },
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{ ORDATA (SCAN, dcs_scan, 5) },
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{ ORDATA (SEND, dcs_send, 5) },
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{ BRDATAD (BUF, dcs_buf, 8, 8, DCS_LINES, "input buffer, lines 0 to 31") },
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{ BRDATAD (FLAGS, dcs_flg, 8, 1, DCS_LINES, "line ready flag, lines 0 to 31") },
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{ FLDATAD (SCNF, iosta, IOS_V_DCS, "scanner ready flag") },
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{ ORDATAD (SCAN, dcs_scan, 5, "scanner line number") },
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{ ORDATAD (SEND, dcs_send, 5, "output line number") },
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{ DRDATA (SBSLVL, dcs_sbs, 4), REG_HRO },
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{ NULL }
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};
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@ -163,8 +163,8 @@ MTAB dcsl_mod[] = {
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};
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REG dcsl_reg[] = {
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{ URDATA (TIME, dcsl_unit[0].wait, 10, 24, 0,
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DCS_LINES, REG_NZ + PV_LEFT) },
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{ URDATAD (TIME, dcsl_unit[0].wait, 10, 24, 0,
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DCS_LINES, REG_NZ + PV_LEFT, "time from I/O initiation to interrupt, lines 0 to 31") },
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{ NULL }
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};
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@ -120,14 +120,14 @@ UNIT drm_unit = {
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};
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REG drm_reg[] = {
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{ ORDATA (DA, drm_da, 9) },
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{ ORDATA (MA, drm_ma, 16) },
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{ FLDATA (DONE, iosta, IOS_V_DRM) },
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{ FLDATA (ERR, drm_err, 0) },
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{ ORDATA (WLK, drm_wlk, 32) },
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{ DRDATA (TIME, drm_time, 24), REG_NZ + PV_LEFT },
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{ ORDATAD (DA, drm_da, 9, "drum address (sector number)") },
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{ ORDATAD (MA, drm_ma, 16, "current memory address") },
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{ FLDATAD (DONE, iosta, IOS_V_DRM, "device done flag") },
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{ FLDATAD (ERR, drm_err, 0, "error flag") },
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{ ORDATAD (WLK, drm_wlk, 32, "write lock switches") },
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{ DRDATAD (TIME, drm_time, 24, "rotational latency, per word"), REG_NZ + PV_LEFT },
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{ DRDATA (SBSLVL, drm_sbs, 4), REG_HRO },
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{ FLDATA (STOP_IOE, drm_stopioe, 0) },
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{ FLDATAD (STOP_IOE, drm_stopioe, 0, "stop on I/O error") },
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{ NULL }
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};
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@ -158,17 +158,17 @@ UNIT drp_unit = {
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};
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REG drp_reg[] = {
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{ ORDATA (TA, drp_ta, 12) },
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{ ORDATA (RDF, drp_rdf, 5) },
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{ FLDATA (RDE, drp_rde, 0) },
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{ FLDATA (WRF, drp_wrf, 5) },
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{ FLDATA (WRE, drp_wre, 0) },
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{ ORDATA (MA, drp_ma, 16) },
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{ ORDATA (WC, drp_wc, 12) },
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{ FLDATA (BUSY, iosta, IOS_V_DRP) },
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{ FLDATA (ERR, drp_err, 0) },
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{ DRDATA (TIME, drp_time, 24), REG_NZ + PV_LEFT },
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{ FLDATA (STOP_IOE, drp_stopioe, 0) },
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{ ORDATAD (TA, drp_ta, 12, "track address") },
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{ ORDATAD (RDF, drp_rdf, 5, "read field") },
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{ FLDATAD (RDE, drp_rde, 0, "read enable flag") },
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{ FLDATAD (WRF, drp_wrf, 5, "write field") },
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{ FLDATAD (WRE, drp_wre, 0, "write enable flag") },
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{ ORDATAD (MA, drp_ma, 16, "current memory address") },
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{ ORDATAD (WC, drp_wc, 12, "word count" ) },
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{ FLDATAD (BUSY, iosta, IOS_V_DRP, "device busy flag") },
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{ FLDATAD (ERR, drp_err, 0, "error flag") },
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{ DRDATAD (TIME, drp_time, 24, "rotational latency, per word"), REG_NZ + PV_LEFT },
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{ FLDATAD (STOP_IOE, drp_stopioe, 0, "stop on I/O error") },
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{ DRDATA (SBSLVL, drm_sbs, 4), REG_HRO },
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{ NULL }
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};
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@ -370,3 +370,4 @@ sim_cancel (&drp_unit);
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drp_unit.FUNC = 0;
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return SCPE_OK;
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}
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@ -308,23 +308,23 @@ UNIT dt_unit[] = {
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};
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REG dt_reg[] = {
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{ ORDATA (DTSA, dtsa, 18) },
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{ ORDATA (DTSB, dtsb, 18) },
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{ ORDATA (DTDB, dtdb, 18) },
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{ FLDATA (DTF, dtsb, DTB_V_DTF) },
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{ FLDATA (BEF, dtsb, DTB_V_BEF) },
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{ FLDATA (ERF, dtsb, DTB_V_ERF) },
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{ DRDATA (LTIME, dt_ltime, 31), REG_NZ },
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{ DRDATA (DCTIME, dt_dctime, 31), REG_NZ },
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{ ORDATA (SUBSTATE, dt_substate, 2) },
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{ ORDATAD (DTSA, dtsa, 18, "status register A") },
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{ ORDATAD (DTSB, dtsb, 18, "status register B") },
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{ ORDATAD (DTDB, dtdb, 18, "data buffer") },
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{ FLDATAD (DTF, dtsb, DTB_V_DTF, "DECtape flag") },
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{ FLDATAD (BEF, dtsb, DTB_V_BEF, "block end flag") },
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{ FLDATAD (ERF, dtsb, DTB_V_ERF, "error flag") },
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{ DRDATAD (LTIME, dt_ltime, 31, "time between lines"), REG_NZ },
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{ DRDATAD (DCTIME, dt_dctime, 31, "time to declarate to a full stop"), REG_NZ },
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{ ORDATAD (SUBSTATE, dt_substate, 2, "read/write command substate") },
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{ DRDATA (LBLK, dt_logblk, 12), REG_HIDDEN },
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{ URDATA (POS, dt_unit[0].pos, 10, T_ADDR_W, 0,
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DT_NUMDR, PV_LEFT | REG_RO) },
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{ URDATA (STATT, dt_unit[0].STATE, 8, 18, 0,
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DT_NUMDR, REG_RO) },
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{ URDATAD (POS, dt_unit[0].pos, 10, T_ADDR_W, 0,
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DT_NUMDR, PV_LEFT | REG_RO, "position, in lines, units 0-7") },
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{ URDATAD (STATT, dt_unit[0].STATE, 8, 18, 0,
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DT_NUMDR, REG_RO, "unit state, units 0-7") },
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{ URDATA (LASTT, dt_unit[0].LASTT, 10, 32, 0,
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DT_NUMDR, REG_HRO) },
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{ FLDATA (STOP_OFFR, dt_stopoffr, 0) },
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{ FLDATAD (STOP_OFFR, dt_stopoffr, 0, "stop on off-reel error") },
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{ DRDATA (SBSLVL, dt_sbs, 4), REG_HRO },
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{ NULL }
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};
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@ -72,17 +72,17 @@ UNIT lpt_unit = {
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};
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REG lpt_reg[] = {
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{ ORDATA (BUF, lpt_unit.buf, 8) },
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{ FLDATA (PNT, iosta, IOS_V_PNT) },
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{ FLDATA (SPC, iosta, IOS_V_SPC) },
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{ FLDATA (RPLS, cpls, CPLS_V_LPT) },
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{ DRDATA (BPTR, lpt_bptr, 6) },
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{ ORDATAD (BUF, lpt_unit.buf, 8, "last data item processed") },
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{ FLDATAD (PNT, iosta, IOS_V_PNT, "printing done flag") },
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{ FLDATAD (SPC, iosta, IOS_V_SPC, "spacing done flag") },
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{ FLDATAD (RPLS, cpls, CPLS_V_LPT, "return restart pulse flag") },
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{ DRDATAD (BPTR, lpt_bptr, 6, "print buffer pointer") },
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{ ORDATA (LPT_STATE, lpt_spc, 6), REG_HRO },
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{ FLDATA (LPT_OVRPR, lpt_ovrpr, 0), REG_HRO },
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{ DRDATA (POS, lpt_unit.pos, T_ADDR_W), PV_LEFT },
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{ DRDATA (TIME, lpt_unit.wait, 24), PV_LEFT },
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{ FLDATA (STOP_IOE, lpt_stopioe, 0) },
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{ BRDATA (LBUF, lpt_buf, 8, 8, LPT_BSIZE) },
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{ DRDATAD (POS, lpt_unit.pos, T_ADDR_W, "position in the output file"), PV_LEFT },
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{ DRDATAD (TIME, lpt_unit.wait, 24, "time from I/O initiation to interrupt"), PV_LEFT },
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{ FLDATAD (STOP_IOE, lpt_stopioe, 0, "stop on I/O error") },
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{ BRDATAD (LBUF, lpt_buf, 8, 8, LPT_BSIZE, "line buffer") },
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{ DRDATA (SBSLVL, lpt_sbs, 4), REG_HRO },
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{ NULL }
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};
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@ -149,17 +149,17 @@ UNIT ptr_unit = {
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};
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REG ptr_reg[] = {
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{ ORDATA (BUF, ptr_unit.buf, 18) },
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{ ORDATAD (BUF, ptr_unit.buf, 18, "last data item processed") },
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{ FLDATA (UC, ptr_uc, UC_V) },
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{ FLDATA (DONE, iosta, IOS_V_PTR) },
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{ FLDATA (RPLS, cpls, CPLS_V_PTR) },
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{ FLDATAD (DONE, iosta, IOS_V_PTR, "device done flag") },
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{ FLDATAD (RPLS, cpls, CPLS_V_PTR, "return restart pulse flag") },
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{ ORDATA (HOLD, ptr_hold, 9), REG_HRO },
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{ ORDATA (STATE, ptr_state, 5), REG_HRO },
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{ FLDATA (WAIT, ptr_wait, 0), REG_HRO },
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{ DRDATA (POS, ptr_unit.pos, T_ADDR_W), PV_LEFT },
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{ DRDATA (TIME, ptr_unit.wait, 24), PV_LEFT },
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{ DRDATAD (POS, ptr_unit.pos, T_ADDR_W, "position in the input file"), PV_LEFT },
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{ DRDATAD (TIME, ptr_unit.wait, 24, "time from I/O initiation to interrupt"), PV_LEFT },
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{ DRDATA (LEADER, ptr_leader, 6), REG_HRO },
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{ FLDATA (STOP_IOE, ptr_stopioe, 0) },
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{ FLDATAD (STOP_IOE, ptr_stopioe, 0, "stop on I/O error") },
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{ DRDATA (SBSLVL, ptr_sbs, 4), REG_HRO },
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{ NULL }
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};
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@ -192,12 +192,12 @@ UNIT ptp_unit = {
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};
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REG ptp_reg[] = {
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{ ORDATA (BUF, ptp_unit.buf, 8) },
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{ FLDATA (DONE, iosta, IOS_V_PTP) },
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{ FLDATA (RPLS, cpls, CPLS_V_PTP) },
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{ DRDATA (POS, ptp_unit.pos, T_ADDR_W), PV_LEFT },
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{ DRDATA (TIME, ptp_unit.wait, 24), PV_LEFT },
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{ FLDATA (STOP_IOE, ptp_stopioe, 0) },
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{ ORDATAD (BUF, ptp_unit.buf, 8, "last data item processed") },
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{ FLDATAD (DONE, iosta, IOS_V_PTP, "device done flag") },
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{ FLDATAD (RPLS, cpls, CPLS_V_PTP, "return restart pulse flag") },
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{ DRDATAD (POS, ptp_unit.pos, T_ADDR_W, "position in the output file"), PV_LEFT },
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{ DRDATAD (TIME, ptp_unit.wait, 24, "time from I/O initiation to interrupt"), PV_LEFT },
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{ FLDATAD (STOP_IOE, ptp_stopioe, 0, "stop on I/O error") },
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{ DRDATA (SBSLVL, ptp_sbs, 4), REG_HRO },
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{ NULL }
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};
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@ -226,12 +226,12 @@ DEVICE ptp_dev = {
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UNIT tti_unit = { UDATA (&tti_svc, 0, 0), KBD_POLL_WAIT };
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REG tti_reg[] = {
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{ ORDATA (BUF, tty_buf, 6) },
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{ FLDATA (UC, tty_uc, UC_V) },
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{ ORDATAD (BUF, tty_buf, 6, "typewriter buffer (shared)") },
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{ FLDATAD (UC, tty_uc, UC_V, "upper case/lower case state (shared)") },
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{ ORDATA (HOLD, tti_hold, 9), REG_HRO },
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{ FLDATA (DONE, iosta, IOS_V_TTI) },
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{ DRDATA (POS, tti_unit.pos, T_ADDR_W), PV_LEFT },
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{ DRDATA (TIME, tti_unit.wait, 24), REG_NZ + PV_LEFT },
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{ FLDATAD (DONE, iosta, IOS_V_TTI, "input ready flag") },
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{ DRDATAD (POS, tti_unit.pos, T_ADDR_W, "number of characters input"), PV_LEFT },
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{ DRDATAD (TIME, tti_unit.wait, 24, "keyboard polling interval"), REG_NZ + PV_LEFT },
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{ DRDATA (SBSLVL, tti_sbs, 4), REG_HRO },
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{ NULL }
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};
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@ -260,12 +260,12 @@ DEVICE tti_dev = {
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UNIT tto_unit = { UDATA (&tto_svc, 0, 0), SERIAL_OUT_WAIT * 10 };
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REG tto_reg[] = {
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{ ORDATA (BUF, tty_buf, 6) },
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{ FLDATA (UC, tty_uc, UC_V) },
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{ FLDATA (RPLS, cpls, CPLS_V_TTO) },
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{ FLDATA (DONE, iosta, IOS_V_TTO) },
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{ DRDATA (POS, tto_unit.pos, T_ADDR_W), PV_LEFT },
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{ DRDATA (TIME, tto_unit.wait, 24), PV_LEFT },
|
||||
{ ORDATAD (BUF, tty_buf, 6, "typewriter buffer (shared)") },
|
||||
{ FLDATAD (UC, tty_uc, UC_V, "upper case/lower case state (shared") },
|
||||
{ FLDATAD (RPLS, cpls, CPLS_V_TTO, "return restart pulse flag") },
|
||||
{ FLDATAD (DONE, iosta, IOS_V_TTO, "output done flag") },
|
||||
{ DRDATAD (POS, tto_unit.pos, T_ADDR_W, "number of characters output"), PV_LEFT },
|
||||
{ DRDATAD (TIME, tto_unit.wait, 24, "time from I/O initiation interrupt"), PV_LEFT },
|
||||
{ DRDATA (SBSLVL, tto_sbs, 4), REG_HRO },
|
||||
{ NULL }
|
||||
};
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue