From 5551a0dd9c0e9e3161ba974c1665c09380381a1b Mon Sep 17 00:00:00 2001 From: Mark Pizzolato Date: Thu, 15 Jan 2015 12:37:07 -0800 Subject: [PATCH] ALL: make sure all useful state is in simh registers while processing events --- ALTAIR/altair_cpu.c | 2 ++ GRI/gri_cpu.c | 3 +++ H316/h316_cpu.c | 5 +++++ I1401/i1401_cpu.c | 6 ++++++ I1620/i1620_cpu.c | 3 +++ I7094/i7094_cpu.c | 2 ++ Interdata/id16_cpu.c | 4 ++++ Interdata/id32_cpu.c | 5 +++++ LGP/lgp_cpu.c | 2 ++ NOVA/eclipse_cpu.c | 2 ++ NOVA/nova_cpu.c | 3 +++ PDP1/pdp1_cpu.c | 2 ++ PDP18B/pdp18b_cpu.c | 3 +++ PDP8/pdp8_cpu.c | 6 ++++++ S3/s3_cpu.c | 2 ++ SDS/sds_cpu.c | 2 ++ TX-0/tx0_cpu.c | 2 ++ alpha/alpha_cpu.c | 5 +++++ sigma/sigma_cpu.c | 4 ++++ 19 files changed, 63 insertions(+) diff --git a/ALTAIR/altair_cpu.c b/ALTAIR/altair_cpu.c index 74a62635..8a01f63a 100644 --- a/ALTAIR/altair_cpu.c +++ b/ALTAIR/altair_cpu.c @@ -309,6 +309,8 @@ t_stat sim_instr (void) while (reason == 0) { /* loop until halted */ if (sim_interval <= 0) { /* check clock queue */ + /* make sure all useful state is in simh registers while processing events */ + saved_PC = PC; if ((reason = sim_process_event ())) break; } diff --git a/GRI/gri_cpu.c b/GRI/gri_cpu.c index c3b35d5c..d16490d1 100644 --- a/GRI/gri_cpu.c +++ b/GRI/gri_cpu.c @@ -417,6 +417,9 @@ ao_update (); /* update AO */ while (reason == 0) { /* loop until halted */ if (sim_interval <= 0) { /* check clock queue */ + /* make sure all useful state is in simh registers while processing events */ + ao_update (); /* update AO */ + scq_r->qptr = scq_p; /* update sc q ptr */ if ((reason = sim_process_event ())) break; } diff --git a/H316/h316_cpu.c b/H316/h316_cpu.c index 92e77eac..f78aa814 100644 --- a/H316/h316_cpu.c +++ b/H316/h316_cpu.c @@ -441,6 +441,11 @@ reason = 0; while (reason == 0) { /* loop until halted */ if (sim_interval <= 0) { /* check clock queue */ + /* make sure all useful state is in simh registers while processing events */ + saved_AR = AR & DMASK; + saved_BR = BR & DMASK; + saved_XR = XR & DMASK; + pcq_r->qptr = pcq_p; /* update pc q ptr */ if ((reason = sim_process_event ())) break; } diff --git a/I1401/i1401_cpu.c b/I1401/i1401_cpu.c index 8594f5ec..b41be76b 100644 --- a/I1401/i1401_cpu.c +++ b/I1401/i1401_cpu.c @@ -550,6 +550,12 @@ while (reason == 0) { /* loop until halted */ saved_IS = IS; /* commit prev instr */ if (sim_interval <= 0) { /* check clock queue */ + /* make sure all useful state is in simh registers while processing events */ + as_err = ADDR_ERR (AS); /* get addr err flags */ + bs_err = ADDR_ERR (BS); + AS = AS & ADDRMASK; /* clean addresses */ + BS = BS & ADDRMASK; + pcq_r->qptr = pcq_p; /* update pc q ptr */ if ((reason = sim_process_event ())) break; } diff --git a/I1620/i1620_cpu.c b/I1620/i1620_cpu.c index 0c6fd9d4..424d6de9 100644 --- a/I1620/i1620_cpu.c +++ b/I1620/i1620_cpu.c @@ -488,6 +488,9 @@ while (reason == 0) { /* loop until halted */ saved_PC = PC; /* commit prev instr */ if (sim_interval <= 0) { /* check clock queue */ + /* make sure all useful state is in simh registers while processing events */ + pcq_r->qptr = pcq_p; /* update pc q ptr */ + upd_ind (); if ((reason = sim_process_event ())) break; } diff --git a/I7094/i7094_cpu.c b/I7094/i7094_cpu.c index 64c406db..ed28e833 100644 --- a/I7094/i7094_cpu.c +++ b/I7094/i7094_cpu.c @@ -659,6 +659,8 @@ while (reason == SCPE_OK) { /* loop until error */ } if (sim_interval <= 0) { /* intv cnt expired? */ + /* make sure all useful state is in simh registers while processing events */ + pcq_r->qptr = pcq_p; /* update pc q ptr */ if ((reason = sim_process_event ())) /* process events */ break; chtr_pend = chtr_eval (NULL); /* eval chan traps */ diff --git a/Interdata/id16_cpu.c b/Interdata/id16_cpu.c index 6d575deb..a0b731c8 100644 --- a/Interdata/id16_cpu.c +++ b/Interdata/id16_cpu.c @@ -599,6 +599,10 @@ while (reason == 0) { /* loop until halted */ int32 sr, st; if (sim_interval <= 0) { /* check clock queue */ + /* make sure all useful state is in simh registers while processing events */ + PSW = BUILD_PSW (cc); + PC = PC & VAMASK; + pcq_r->qptr = pcq_p; /* update pc q ptr */ if ((reason = sim_process_event ())) break; int_eval (); diff --git a/Interdata/id32_cpu.c b/Interdata/id32_cpu.c index f9eb0416..985b60b1 100644 --- a/Interdata/id32_cpu.c +++ b/Interdata/id32_cpu.c @@ -658,6 +658,11 @@ while (reason == 0) { /* loop until halted */ int32 sr, st; if (sim_interval <= 0) { /* check clock queue */ + /* make sure all useful state is in simh registers while processing events */ + PSW = BUILD_PSW (cc); + PC = PC & VAMASK; + set_r_display (R); + pcq_r->qptr = pcq_p; /* update pc q ptr */ if ((reason = sim_process_event ())) break; int_eval (); diff --git a/LGP/lgp_cpu.c b/LGP/lgp_cpu.c index b91d6b82..67eca5ab 100644 --- a/LGP/lgp_cpu.c +++ b/LGP/lgp_cpu.c @@ -283,6 +283,8 @@ if (lgp21_sov) { /* stop sense pending? * do { if (sim_interval <= 0) { /* check clock queue */ + /* make sure all useful state is in simh registers while processing events */ + pcq_r->qptr = pcq_p; /* update pc q ptr */ if ((r = sim_process_event ())) break; } diff --git a/NOVA/eclipse_cpu.c b/NOVA/eclipse_cpu.c index ddc0e788..1867d6a4 100644 --- a/NOVA/eclipse_cpu.c +++ b/NOVA/eclipse_cpu.c @@ -737,6 +737,8 @@ if (MapInit == 0) { while (reason == 0) { /* loop until halted */ if (sim_interval <= 0) { /* check clock queue */ + /* make sure all useful state is in simh registers while processing events */ + saved_PC = PC; if ((reason = sim_process_event ())) break; } diff --git a/NOVA/nova_cpu.c b/NOVA/nova_cpu.c index c71b6680..f5afa1c4 100644 --- a/NOVA/nova_cpu.c +++ b/NOVA/nova_cpu.c @@ -428,6 +428,9 @@ reason = 0; while (reason == 0) { /* loop until halted */ if (sim_interval <= 0) { /* check clock queue */ + /* make sure all useful state is in simh registers while processing events */ + saved_PC = PC; + pcq_r->qptr = pcq_p; /* update pc q ptr */ if ( (reason = sim_process_event ()) ) break; } diff --git a/PDP1/pdp1_cpu.c b/PDP1/pdp1_cpu.c index b59c469e..5fdee5f3 100644 --- a/PDP1/pdp1_cpu.c +++ b/PDP1/pdp1_cpu.c @@ -546,6 +546,8 @@ reason = 0; while (reason == 0) { /* loop until halted */ if (sim_interval <= 0) { /* check clock queue */ + /* Make sure all intermediate state is visible in simh registers */ + pcq_r->qptr = pcq_p; /* update pc q ptr */ if ((reason = sim_process_event ())) break; sbs_lvl = sbs_eval (); /* eval sbs system */ diff --git a/PDP18B/pdp18b_cpu.c b/PDP18B/pdp18b_cpu.c index 3e2f0cd1..7a4a9880 100644 --- a/PDP18B/pdp18b_cpu.c +++ b/PDP18B/pdp18b_cpu.c @@ -597,6 +597,9 @@ while (reason == 0) { /* loop until halted */ int32 link_init, fill; if (sim_interval <= 0) { /* check clock queue */ + /* Make sure all intermediate state is visible in simh registers */ + iors = upd_iors (); /* get IORS */ + pcq_r->qptr = pcq_p; /* update pc q ptr */ if ((reason = sim_process_event ())) break; api_int = api_eval (&int_pend); /* eval API */ diff --git a/PDP8/pdp8_cpu.c b/PDP8/pdp8_cpu.c index cb4471c3..62b4451f 100644 --- a/PDP8/pdp8_cpu.c +++ b/PDP8/pdp8_cpu.c @@ -339,6 +339,12 @@ reason = 0; while (reason == 0) { /* loop until halted */ if (sim_interval <= 0) { /* check clock queue */ + /* Make sure all intermediate state is visible in simh registers */ + saved_PC = IF | (PC & 07777); /* save copies */ + saved_DF = DF & 070000; + saved_LAC = LAC & 017777; + saved_MQ = MQ & 07777; + pcq_r->qptr = pcq_p; /* update pc q ptr */ if ((reason = sim_process_event ())) break; } diff --git a/S3/s3_cpu.c b/S3/s3_cpu.c index b732cbe1..e32f77ed 100644 --- a/S3/s3_cpu.c +++ b/S3/s3_cpu.c @@ -521,6 +521,8 @@ reason = 0; while (reason == 0) { /* loop until halted */ if (sim_interval <= 0) { /* check clock queue */ + /* make sure all useful state is in simh registers while processing events */ + saved_PC = PC; if ((reason = sim_process_event ())) break; } diff --git a/SDS/sds_cpu.c b/SDS/sds_cpu.c index 60121712..7537cfc8 100644 --- a/SDS/sds_cpu.c +++ b/SDS/sds_cpu.c @@ -382,6 +382,8 @@ while (reason == 0) { /* loop until halted */ } if (sim_interval <= 0) { /* event queue? */ + /* make sure all useful state is in simh registers while processing events */ + pcq_r->qptr = pcq_p; /* update pc q ptr */ if ((reason = sim_process_event ())) /* process */ break; int_reqhi = api_findreq (); /* recalc int req */ diff --git a/TX-0/tx0_cpu.c b/TX-0/tx0_cpu.c index 93e99b12..82fd2cdc 100644 --- a/TX-0/tx0_cpu.c +++ b/TX-0/tx0_cpu.c @@ -462,6 +462,8 @@ t_stat sim_instr (void) while (reason == 0) { /* loop until halted */ if (sim_interval <= 0) { /* check clock queue */ + /* make sure all useful state is in simh registers while processing events */ + pcq_r->qptr = pcq_p; /* update pc q ptr */ reason = sim_process_event (); if (reason != SCPE_OK) break; diff --git a/alpha/alpha_cpu.c b/alpha/alpha_cpu.c index 7a6d7c1c..81a7e369 100644 --- a/alpha/alpha_cpu.c +++ b/alpha/alpha_cpu.c @@ -393,6 +393,11 @@ while (reason == 0) { } if (sim_interval <= 0) { /* chk clock queue */ + /* make sure all useful state is in simh registers while processing events */ + pcc_l = pcc_l & M32; + pcq_r->qptr = pcq_p; /* update pc q ptr */ + pc_align = ((uint32) PC) & 3; /* separate PC<1:0> */ + PC = PC & 0xFFFFFFFFFFFFFFFC; if ((reason = sim_process_event ())) break; intr_summ = pal_eval_intr (1); /* eval interrupts */ } diff --git a/sigma/sigma_cpu.c b/sigma/sigma_cpu.c index dd6d4631..b2506366 100644 --- a/sigma/sigma_cpu.c +++ b/sigma/sigma_cpu.c @@ -433,6 +433,10 @@ while (reason == 0) { /* loop until stop */ } if (sim_interval <= 0) { /* event queue? */ + /* make sure all useful state is in simh registers while processing events */ + pcq_r->qptr = pcq_p; /* update pc q ptr */ + cpu_assemble_PSD (); /* visible PSD */ + set_rf_display (R); /* visible registers */ if (reason = sim_process_event ()) /* process */ break; int_hireq = io_eval_int (); /* re-evaluate intr */