PDP11, DZ: Properly set CSR bits character output processing.
Declare output unit to facilitate proper character output completion scheduling. Proper completion scheduling removes the need to sleeping waiting for character I/O completion. This should fix #521 and #504
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1 changed files with 12 additions and 6 deletions
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@ -302,7 +302,8 @@ DIB dz_dib = {
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UNIT dz_unit[2] = {
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{ UDATA (&dz_svc, UNIT_IDLE|UNIT_ATTABLE|DZ_8B_DFLT, 0) },
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{ UDATA (&dz_xmt_svc, UNIT_DIS, 0), SERIAL_OUT_WAIT } };
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{ UDATA (&dz_xmt_svc, UNIT_DIS, 0) }
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};
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REG dz_reg[] = {
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{ BRDATADF (CSR, dz_csr, DEV_RDX, 16, MAX_DZ_MUXES, "control/status register", dz_csr_bits) },
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@ -531,9 +532,11 @@ switch ((PA >> 1) & 03) { /* case on PA<2:1> */
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line = (dz * DZ_LINES) + CSR_GETTL (dz_csr[dz]);
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lp = &dz_ldsc[line]; /* get line desc */
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c = sim_tt_outcvt (dz_tdr[dz], TT_GET_MODE (dz_unit[0].flags));
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if (c >= 0) /* store char */
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if (c >= 0) { /* store char */
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tmxr_putc_ln (lp, c);
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sim_activate (&dz_unit[1], dz_unit[1].wait);/* */
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dz_update_xmti ();
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sim_activate_after_abs (&dz_unit[1], lp->txdelta);/* */
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}
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}
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break;
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}
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@ -671,7 +674,8 @@ for (dz = 0; dz < dz_desc.lines/DZ_LINES; dz++) { /* loop thru muxes */
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}
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if ((dz_csr[dz] & CSR_TIE) && (dz_csr[dz] & CSR_TRDY)) /* ready plus int? */
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dz_set_txint (dz);
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else dz_clr_txint (dz); /* no int req */
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else
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dz_clr_txint (dz); /* no int req */
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}
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return;
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}
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@ -792,11 +796,13 @@ return auto_config (dptr->name, ndev); /* auto config */
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t_stat dz_attach (UNIT *uptr, CONST char *cptr)
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{
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int32 dz, muxln;
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int32 dz, muxln, ln;
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t_stat r;
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if ((sim_switches & SWMASK ('M')) || dz_mctl) /* modem control? */
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tmxr_set_modem_control_passthru (&dz_desc);
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for (ln = 0; ln < dz_desc.lines; ln++)
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tmxr_set_line_output_unit (&dz_desc, ln, &dz_unit[1]);
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r = tmxr_attach (&dz_desc, uptr, cptr); /* attach mux */
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if (r != SCPE_OK) { /* error? */
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tmxr_clear_modem_control_passthru (&dz_desc);
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