Intel-Systems: Cleanup Coverity identified issues and address range issues
This commit is contained in:
Bill Beech
parent
82d897712c
commit
58c5fe417f
28 changed files with 451 additions and 606 deletions
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@ -36,71 +36,6 @@
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All I/O is via programmed I/O. The i3214 has a status port
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All I/O is via programmed I/O. The i3214 has a status port
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and two data port.
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and two data port.
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save for now!
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A write to the status port can select some options for the device:
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Asynchronous Mode Instruction
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7 6 5 4 3 2 1 0
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+---+---+---+---+---+---+---+---+
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| S2 S1 EP PEN L2 L1 B2 B1|
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+---+---+---+---+---+---+---+---+
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Baud Rate Factor
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B2 0 1 0 1
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B1 0 0 1 1
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sync 1X 16X 64X
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mode
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Character Length
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L2 0 1 0 1
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L1 0 0 1 1
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5 6 7 8
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bits bits bits bits
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EP - A 1 in this bit position selects even parity.
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PEN - A 1 in this bit position enables parity.
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Number of Stop Bits
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S2 0 1 0 1
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S1 0 0 1 1
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invalid 1 1.5 2
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bit bits bits
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Command Instruction Format
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7 6 5 4 3 2 1 0
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+---+---+---+---+---+---+---+---+
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| EH IR RTS ER SBRK RxE DTR TxE|
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+---+---+---+---+---+---+---+---+
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TxE - A 1 in this bit position enables transmit.
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DTR - A 1 in this bit position forces *DTR to zero.
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RxE - A 1 in this bit position enables receive.
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SBRK - A 1 in this bit position forces TxD to zero.
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ER - A 1 in this bit position resets the error bits
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RTS - A 1 in this bit position forces *RTS to zero.
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IR - A 1 in this bit position returns the 8251 to Mode Instruction Format.
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EH - A 1 in this bit position enables search for sync characters.
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A read of the status port gets the port status:
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Status Read Format
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7 6 5 4 3 2 1 0
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+---+---+---+---+---+---+---+---+
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|DSR SD FE OE PE TxE RxR TxR|
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+---+---+---+---+---+---+---+---+
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TxR - A 1 in this bit position signals transmit ready to receive a character.
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RxR - A 1 in this bit position signals receiver has a character.
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TxE - A 1 in this bit position signals transmitter has no more characters to transmit.
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PE - A 1 in this bit signals a parity error.
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OE - A 1 in this bit signals an transmit overrun error.
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FE - A 1 in this bit signals a framing error.
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SD - A 1 in this bit position returns the 8251 to Mode Instruction Format.
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DSR - A 1 in this bit position signals *DSR is at zero.
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A read from the data port gets the typed character, a write
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to the data port writes the character to the device.
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*/
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*/
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#include "system_defs.h"
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#include "system_defs.h"
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@ -475,12 +475,14 @@ int32 sim_instr(void)
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IR = OP = fetch_byte(0); /* instruction fetch */
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IR = OP = fetch_byte(0); /* instruction fetch */
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/*
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if (GET_XACK(1) == 0) { // no XACK for instruction fetch
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if (GET_XACK(1) == 0) { // no XACK for instruction fetch
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// reason = STOP_XACK;
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reason = STOP_XACK;
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if (uptr->flags & UNIT_XACK)
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// if (uptr->flags & UNIT_XACK)
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sim_printf("Failed XACK for Instruction Fetch from %04X\n", PCX);
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sim_printf("Failed XACK for Instruction Fetch from %04X\n", PCX);
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// continue;
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continue;
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}
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}
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*/
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// first instruction decode
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// first instruction decode
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if (OP == 0x76) { /* HLT Instruction*/
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if (OP == 0x76) { /* HLT Instruction*/
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@ -886,11 +888,13 @@ int32 sim_instr(void)
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case 0xDB: /* IN */
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case 0xDB: /* IN */
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port = fetch_byte(1);
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port = fetch_byte(1);
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A = dev_table[port].routine(0, 0, dev_table[port].devnum);
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A = dev_table[port].routine(0, 0, dev_table[port].devnum);
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SET_XACK(1); /* good I/O address */
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break;
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break;
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case 0xD3: /* OUT */
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case 0xD3: /* OUT */
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port = fetch_byte(1);
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port = fetch_byte(1);
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dev_table[port].routine(1, A, dev_table[port].devnum);
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dev_table[port].routine(1, A, dev_table[port].devnum);
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SET_XACK(1); /* good I/O address */
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break;
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break;
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default: /* undefined opcode */
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default: /* undefined opcode */
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@ -902,17 +906,19 @@ int32 sim_instr(void)
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}
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}
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loop_end:
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loop_end:
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/*
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if (GET_XACK(1) == 0) { // no XACK for operand fetch
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if (GET_XACK(1) == 0) { // no XACK for operand fetch
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// reason = STOP_XACK;
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reason = STOP_XACK;
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if (OP == 0xD3 || OP == 0xDB) {
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if (OP == 0xD3 || OP == 0xDB) {
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if (uptr->flags & UNIT_XACK)
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// if (uptr->flags & UNIT_XACK)
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sim_printf("Failed XACK for Port %02X Fetch from %04X\n", port, PCX);
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sim_printf("Failed XACK for Port %02X Fetch from %04X\n", port, PCX);
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} else {
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} else {
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if (uptr->flags & UNIT_XACK)
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// if (uptr->flags & UNIT_XACK)
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sim_printf("Failed XACK for Operand %04X Fetch from %04X\n", addr, PCX);
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sim_printf("Failed XACK for Operand %04X Fetch from %04X\n", addr, PCX);
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// continue;
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continue;
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}
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}
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}
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}
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*/;
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}
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}
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/* Simulation halted */
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/* Simulation halted */
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@ -237,40 +237,35 @@
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/* external globals */
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/* external globals */
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extern uint16 port; //port called in dev_table[port]
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/* internal function prototypes */
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/* internal function prototypes */
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t_stat i8237_svc (UNIT *uptr);
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t_stat i8237_svc (UNIT *uptr);
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t_stat i8237_reset (DEVICE *dptr, uint16 base);
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t_stat i8237_reset (DEVICE *dptr);
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void i8237_reset1 (void);
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void i8237_reset_dev (uint8 devnum);
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t_stat i8237_set_mode (UNIT *uptr, int32 val, CONST char *cptr, void *desc);
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t_stat i8237_set_mode (UNIT *uptr, int32 val, CONST char *cptr, void *desc);
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uint8 i8237_r0x(t_bool io, uint8 data);
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uint8 i8237_r0x(t_bool io, uint8 data, uint8 devnum);
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uint8 i8237_r1x(t_bool io, uint8 data);
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uint8 i8237_r1x(t_bool io, uint8 data, uint8 devnum);
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uint8 i8237_r2x(t_bool io, uint8 data);
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uint8 i8237_r2x(t_bool io, uint8 data, uint8 devnum);
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uint8 i8237_r3x(t_bool io, uint8 data);
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uint8 i8237_r3x(t_bool io, uint8 data, uint8 devnum);
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uint8 i8237_r4x(t_bool io, uint8 data);
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uint8 i8237_r4x(t_bool io, uint8 data, uint8 devnum);
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uint8 i8237_r5x(t_bool io, uint8 data);
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uint8 i8237_r5x(t_bool io, uint8 data, uint8 devnum);
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uint8 i8237_r6x(t_bool io, uint8 data);
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uint8 i8237_r6x(t_bool io, uint8 data, uint8 devnum);
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uint8 i8237_r7x(t_bool io, uint8 data);
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uint8 i8237_r7x(t_bool io, uint8 data, uint8 devnum);
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uint8 i8237_r8x(t_bool io, uint8 data);
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uint8 i8237_r8x(t_bool io, uint8 data, uint8 devnum);
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uint8 i8237_r9x(t_bool io, uint8 data);
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uint8 i8237_r9x(t_bool io, uint8 data, uint8 devnum);
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uint8 i8237_rAx(t_bool io, uint8 data);
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uint8 i8237_rAx(t_bool io, uint8 data, uint8 devnum);
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uint8 i8237_rBx(t_bool io, uint8 data);
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uint8 i8237_rBx(t_bool io, uint8 data, uint8 devnum);
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uint8 i8237_rCx(t_bool io, uint8 data);
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uint8 i8237_rCx(t_bool io, uint8 data, uint8 devnum);
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uint8 i8237_rDx(t_bool io, uint8 data);
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uint8 i8237_rDx(t_bool io, uint8 data, uint8 devnum);
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uint8 i8237_rEx(t_bool io, uint8 data);
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uint8 i8237_rEx(t_bool io, uint8 data, uint8 devnum);
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uint8 i8237_rFx(t_bool io, uint8 data);
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uint8 i8237_rFx(t_bool io, uint8 data, uint8 devnum);
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/* external function prototypes */
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/* external function prototypes */
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extern uint8 reg_dev(uint8 (*routine)(t_bool, uint8, uint8), uint8);
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extern uint8 reg_dev(uint8 (*routine)(t_bool, uint8, uint8), uint8, uint8);
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/* globals */
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/* globals */
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int32 i8237_devnum = 0; //actual number of 8253 instances + 1
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uint16 i8237_port[4]; //base port registered to each instance
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/* 8237 physical register definitions */
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/* 8237 physical register definitions */
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uint16 i8237_r0[4]; // 8237 ch 0 address register
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uint16 i8237_r0[4]; // 8237 ch 0 address register
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@ -405,7 +400,7 @@ DEVICE i8237_dev = {
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8, //dwidth
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8, //dwidth
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NULL, //examine
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NULL, //examine
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NULL, //deposit
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NULL, //deposit
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NULL, //reset
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i8237_reset, //reset
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NULL, //boot
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NULL, //boot
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NULL, //attach
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NULL, //attach
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NULL, //detach
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NULL, //detach
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@ -419,6 +414,30 @@ DEVICE i8237_dev = {
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/* Service routines to handle simulator functions */
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/* Service routines to handle simulator functions */
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// i8251 configuration
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t_stat i8237_cfg(uint8 base, uint8 devnum)
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{
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sim_printf(" i8237[%d]: at base port 0%02XH\n",
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devnum, base & 0xFF);
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reg_dev(i8237_r1x, base + 1, devnum);
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reg_dev(i8237_r2x, base + 2, devnum);
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reg_dev(i8237_r3x, base + 3, devnum);
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reg_dev(i8237_r4x, base + 4, devnum);
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reg_dev(i8237_r5x, base + 5, devnum);
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reg_dev(i8237_r6x, base + 6, devnum);
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reg_dev(i8237_r7x, base + 7, devnum);
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reg_dev(i8237_r8x, base + 8, devnum);
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reg_dev(i8237_r9x, base + 9, devnum);
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reg_dev(i8237_rAx, base + 10, devnum);
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reg_dev(i8237_rBx, base + 11, devnum);
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reg_dev(i8237_rCx, base + 12, devnum);
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reg_dev(i8237_rDx, base + 13, devnum);
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reg_dev(i8237_rEx, base + 14, devnum);
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reg_dev(i8237_rFx, base + 15, devnum);
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return SCPE_OK;
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}
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/* service routine - actually does the simulated DMA */
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/* service routine - actually does the simulated DMA */
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t_stat i8237_svc(UNIT *uptr)
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t_stat i8237_svc(UNIT *uptr)
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@ -431,52 +450,20 @@ t_stat i8237_svc(UNIT *uptr)
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t_stat i8237_reset(DEVICE *dptr)
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t_stat i8237_reset(DEVICE *dptr)
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{
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{
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if (i8237_devnum > I8237_NUM) {
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uint8 devnum;
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sim_printf("i8237_reset: too many devices!\n");
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return SCPE_MEM;
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for (devnum=0; devnum<I8237_NUM; devnum++) {
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i8237_reset_dev(devnum);
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sim_activate (&i8237_unit[devnum], i8237_unit[devnum].wait); /* activate unit */
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}
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}
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i8237_port[i8237_devnum] = reg_dev(i8237_r0x, base);
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reg_dev(i8237_r1x, base + 1);
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reg_dev(i8237_r2x, base + 2);
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reg_dev(i8237_r3x, base + 3);
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reg_dev(i8237_r4x, base + 4);
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reg_dev(i8237_r5x, base + 5);
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reg_dev(i8237_r6x, base + 6);
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reg_dev(i8237_r7x, base + 7);
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reg_dev(i8237_r8x, base + 8);
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reg_dev(i8237_r9x, base + 9);
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reg_dev(i8237_rAx, base + 10);
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reg_dev(i8237_rBx, base + 11);
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reg_dev(i8237_rCx, base + 12);
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reg_dev(i8237_rDx, base + 13);
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reg_dev(i8237_rEx, base + 14);
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reg_dev(i8237_rFx, base + 15);
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sim_printf(" 8237 Reset\n");
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sim_printf(" 8237: Registered at %03X\n", base);
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sim_activate (&i8237_unit[i8237_devnum], i8237_unit[i8237_devnum].wait); /* activate unit */
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if ((i8237_dev.flags & DEV_DIS) == 0)
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i8237_reset1();
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i8237_devnum++;
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return SCPE_OK;
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return SCPE_OK;
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}
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}
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uint8 i8237_get_dn(void)
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void i8237_reset_dev(uint8 devnum)
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{
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int i;
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for (i=0; i<I8237_NUM; i++)
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if (port >=i8237_port[i] && port <= i8237_port[i] + 16)
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return i;
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sim_printf("i8237_get_dn: port %03X not in 8237 device table\n", port);
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return 0xFF;
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}
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void i8237_reset1(void)
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{
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{
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int32 i;
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int32 i;
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UNIT *uptr;
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UNIT *uptr;
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static int flag = 1;
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static int flag = 1;
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uint8 devnum;
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for (i = 0; i < 1; i++) { /* handle all units */
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for (i = 0; i < 1; i++) { /* handle all units */
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uptr = i8237_dev.units + i;
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uptr = i8237_dev.units + i;
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@ -525,411 +512,331 @@ t_stat i8237_set_mode(UNIT *uptr, int32 val, CONST char *cptr, void *desc)
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to the device.
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to the device.
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*/
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*/
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uint8 i8237_r0x(t_bool io, uint8 data)
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uint8 i8237_r0x(t_bool io, uint8 data, uint8 devnum)
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{
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{
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uint8 devnum;
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if (io == 0) { /* read current address CH 0 */
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if (i8237_rD[devnum]) { /* high byte */
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if ((devnum = i8237_get_dn()) != 0xFF) {
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if (io == 0) { /* read current address CH 0 */
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if (i8237_rD[devnum]) { /* high byte */
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i8237_rD[devnum] = 0;
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sim_debug (DEBUG_reg, &i8237_dev, "i8237_r0[devnum](H) read as %04X\n", i8237_r0[devnum]);
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return (i8237_r0[devnum] >> 8);
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} else { /* low byte */
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i8237_rD[devnum]++;
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sim_debug (DEBUG_reg, &i8237_dev, "i8237_r0[devnum](L) read as %04X\n", i8237_r0[devnum]);
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return (i8237_r0[devnum] & 0xFF);
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}
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} else { /* write base & current address CH 0 */
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if (i8237_rD[devnum]) { /* high byte */
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i8237_rD[devnum] = 0;
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i8237_r0[devnum] |= (data << 8);
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sim_debug (DEBUG_reg, &i8237_dev, "i8237_r0[devnum](H) set to %04X\n", i8237_r0[devnum]);
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} else { /* low byte */
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i8237_rD[devnum]++;
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i8237_r0[devnum] = data & 0xFF;
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sim_debug (DEBUG_reg, &i8237_dev, "i8237_r0[devnum](L) set to %04X\n", i8237_r0[devnum]);
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}
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return 0;
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}
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}
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
uint8 i8237_r1x(t_bool io, uint8 data)
|
|
||||||
{
|
|
||||||
uint8 devnum;
|
|
||||||
|
|
||||||
if ((devnum = i8237_get_dn()) != 0xFF) {
|
|
||||||
if (io == 0) { /* read current word count CH 0 */
|
|
||||||
if (i8237_rD[devnum]) { /* high byte */
|
|
||||||
i8237_rD[devnum] = 0;
|
|
||||||
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r1[devnum](H) read as %04X\n", i8237_r1[devnum]);
|
|
||||||
return (i8237_r1[devnum] >> 8);
|
|
||||||
} else { /* low byte */
|
|
||||||
i8237_rD[devnum]++;
|
|
||||||
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r1[devnum](L) read as %04X\n", i8237_r1[devnum]);
|
|
||||||
return (i8237_r1[devnum] & 0xFF);
|
|
||||||
}
|
|
||||||
} else { /* write base & current address CH 0 */
|
|
||||||
if (i8237_rD[devnum]) { /* high byte */
|
|
||||||
i8237_rD[devnum] = 0;
|
|
||||||
i8237_r1[devnum] |= (data << 8);
|
|
||||||
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r1[devnum](H) set to %04X\n", i8237_r1[devnum]);
|
|
||||||
} else { /* low byte */
|
|
||||||
i8237_rD[devnum]++;
|
|
||||||
i8237_r1[devnum] = data & 0xFF;
|
|
||||||
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r1[devnum](L) set to %04X\n", i8237_r1[devnum]);
|
|
||||||
}
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
uint8 i8237_r2x(t_bool io, uint8 data)
|
|
||||||
{
|
|
||||||
uint8 devnum;
|
|
||||||
|
|
||||||
if ((devnum = i8237_get_dn()) != 0xFF) {
|
|
||||||
if (io == 0) { /* read current address CH 1 */
|
|
||||||
if (i8237_rD[devnum]) { /* high byte */
|
|
||||||
i8237_rD[devnum] = 0;
|
|
||||||
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r2[devnum](H) read as %04X\n", i8237_r2[devnum]);
|
|
||||||
return (i8237_r2[devnum] >> 8);
|
|
||||||
} else { /* low byte */
|
|
||||||
i8237_rD[devnum]++;
|
|
||||||
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r2[devnum](L) read as %04X\n", i8237_r2[devnum]);
|
|
||||||
return (i8237_r2[devnum] & 0xFF);
|
|
||||||
}
|
|
||||||
} else { /* write base & current address CH 1 */
|
|
||||||
if (i8237_rD[devnum]) { /* high byte */
|
|
||||||
i8237_rD[devnum] = 0;
|
|
||||||
i8237_r2[devnum] |= (data << 8);
|
|
||||||
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r2[devnum](H) set to %04X\n", i8237_r2[devnum]);
|
|
||||||
} else { /* low byte */
|
|
||||||
i8237_rD[devnum]++;
|
|
||||||
i8237_r2[devnum] = data & 0xFF;
|
|
||||||
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r2[devnum](L) set to %04X\n", i8237_r2[devnum]);
|
|
||||||
}
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
uint8 i8237_r3x(t_bool io, uint8 data)
|
|
||||||
{
|
|
||||||
uint8 devnum;
|
|
||||||
|
|
||||||
if ((devnum = i8237_get_dn()) != 0xFF) {
|
|
||||||
if (io == 0) { /* read current word count CH 1 */
|
|
||||||
if (i8237_rD[devnum]) { /* high byte */
|
|
||||||
i8237_rD[devnum] = 0;
|
|
||||||
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r3[devnum](H) read as %04X\n", i8237_r3[devnum]);
|
|
||||||
return (i8237_r3[devnum] >> 8);
|
|
||||||
} else { /* low byte */
|
|
||||||
i8237_rD[devnum]++;
|
|
||||||
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r3[devnum](L) read as %04X\n", i8237_r3[devnum]);
|
|
||||||
return (i8237_r3[devnum] & 0xFF);
|
|
||||||
}
|
|
||||||
} else { /* write base & current address CH 1 */
|
|
||||||
if (i8237_rD[devnum]) { /* high byte */
|
|
||||||
i8237_rD[devnum] = 0;
|
|
||||||
i8237_r3[devnum] |= (data << 8);
|
|
||||||
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r3[devnum](H) set to %04X\n", i8237_r3[devnum]);
|
|
||||||
} else { /* low byte */
|
|
||||||
i8237_rD[devnum]++;
|
|
||||||
i8237_r3[devnum] = data & 0xFF;
|
|
||||||
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r3[devnum](L) set to %04X\n", i8237_r3[devnum]);
|
|
||||||
}
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
uint8 i8237_r4x(t_bool io, uint8 data)
|
|
||||||
{
|
|
||||||
uint8 devnum;
|
|
||||||
|
|
||||||
if ((devnum = i8237_get_dn()) != 0xFF) {
|
|
||||||
if (io == 0) { /* read current address CH 2 */
|
|
||||||
if (i8237_rD[devnum]) { /* high byte */
|
|
||||||
i8237_rD[devnum] = 0;
|
|
||||||
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r4[devnum](H) read as %04X\n", i8237_r4[devnum]);
|
|
||||||
return (i8237_r4[devnum] >> 8);
|
|
||||||
} else { /* low byte */
|
|
||||||
i8237_rD[devnum]++;
|
|
||||||
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r4[devnum](L) read as %04X\n", i8237_r4[devnum]);
|
|
||||||
return (i8237_r4[devnum] & 0xFF);
|
|
||||||
}
|
|
||||||
} else { /* write base & current address CH 2 */
|
|
||||||
if (i8237_rD[devnum]) { /* high byte */
|
|
||||||
i8237_rD[devnum] = 0;
|
|
||||||
i8237_r4[devnum] |= (data << 8);
|
|
||||||
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r4[devnum](H) set to %04X\n", i8237_r4[devnum]);
|
|
||||||
} else { /* low byte */
|
|
||||||
i8237_rD[devnum]++;
|
|
||||||
i8237_r4[devnum] = data & 0xFF;
|
|
||||||
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r4[devnum](L) set to %04X\n", i8237_r4[devnum]);
|
|
||||||
}
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
uint8 i8237_r5x(t_bool io, uint8 data)
|
|
||||||
{
|
|
||||||
uint8 devnum;
|
|
||||||
|
|
||||||
if ((devnum = i8237_get_dn()) != 0xFF) {
|
|
||||||
if (io == 0) { /* read current word count CH 2 */
|
|
||||||
if (i8237_rD[devnum]) { /* high byte */
|
|
||||||
i8237_rD[devnum] = 0;
|
|
||||||
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r5[devnum](H) read as %04X\n", i8237_r5[devnum]);
|
|
||||||
return (i8237_r5[devnum] >> 8);
|
|
||||||
} else { /* low byte */
|
|
||||||
i8237_rD[devnum]++;
|
|
||||||
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r5[devnum](L) read as %04X\n", i8237_r5[devnum]);
|
|
||||||
return (i8237_r5[devnum] & 0xFF);
|
|
||||||
}
|
|
||||||
} else { /* write base & current address CH 2 */
|
|
||||||
if (i8237_rD[devnum]) { /* high byte */
|
|
||||||
i8237_rD[devnum] = 0;
|
|
||||||
i8237_r5[devnum] |= (data << 8);
|
|
||||||
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r5[devnum](H) set to %04X\n", i8237_r5[devnum]);
|
|
||||||
} else { /* low byte */
|
|
||||||
i8237_rD[devnum]++;
|
|
||||||
i8237_r5[devnum] = data & 0xFF;
|
|
||||||
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r5[devnum](L) set to %04X\n", i8237_r5[devnum]);
|
|
||||||
}
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
uint8 i8237_r6x(t_bool io, uint8 data)
|
|
||||||
{
|
|
||||||
uint8 devnum;
|
|
||||||
|
|
||||||
if ((devnum = i8237_get_dn()) != 0xFF) {
|
|
||||||
if (io == 0) { /* read current address CH 3 */
|
|
||||||
if (i8237_rD[devnum]) { /* high byte */
|
|
||||||
i8237_rD[devnum] = 0;
|
|
||||||
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r6[devnum](H) read as %04X\n", i8237_r6[devnum]);
|
|
||||||
return (i8237_r6[devnum] >> 8);
|
|
||||||
} else { /* low byte */
|
|
||||||
i8237_rD[devnum]++;
|
|
||||||
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r6[devnum](L) read as %04X\n", i8237_r6[devnum]);
|
|
||||||
return (i8237_r6[devnum] & 0xFF);
|
|
||||||
}
|
|
||||||
} else { /* write base & current address CH 3 */
|
|
||||||
if (i8237_rD[devnum]) { /* high byte */
|
|
||||||
i8237_rD[devnum] = 0;
|
|
||||||
i8237_r6[devnum] |= (data << 8);
|
|
||||||
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r6[devnum](H) set to %04X\n", i8237_r6[devnum]);
|
|
||||||
} else { /* low byte */
|
|
||||||
i8237_rD[devnum]++;
|
|
||||||
i8237_r6[devnum] = data & 0xFF;
|
|
||||||
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r6[devnum](L) set to %04X\n", i8237_r6[devnum]);
|
|
||||||
}
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
uint8 i8237_r7x(t_bool io, uint8 data)
|
|
||||||
{
|
|
||||||
uint8 devnum;
|
|
||||||
|
|
||||||
if ((devnum = i8237_get_dn()) != 0xFF) {
|
|
||||||
if (io == 0) { /* read current word count CH 3 */
|
|
||||||
if (i8237_rD[devnum]) { /* high byte */
|
|
||||||
i8237_rD[devnum] = 0;
|
|
||||||
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r7[devnum](H) read as %04X\n", i8237_r7[devnum]);
|
|
||||||
return (i8237_r7[devnum] >> 8);
|
|
||||||
} else { /* low byte */
|
|
||||||
i8237_rD[devnum]++;
|
|
||||||
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r7[devnum](L) read as %04X\n", i8237_r7[devnum]);
|
|
||||||
return (i8237_r7[devnum] & 0xFF);
|
|
||||||
}
|
|
||||||
} else { /* write base & current address CH 3 */
|
|
||||||
if (i8237_rD[devnum]) { /* high byte */
|
|
||||||
i8237_rD[devnum] = 0;
|
|
||||||
i8237_r7[devnum] |= (data << 8);
|
|
||||||
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r7[devnum](H) set to %04X\n", i8237_r7[devnum]);
|
|
||||||
} else { /* low byte */
|
|
||||||
i8237_rD[devnum]++;
|
|
||||||
i8237_r7[devnum] = data & 0xFF;
|
|
||||||
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r7[devnum](L) set to %04X\n", i8237_r7[devnum]);
|
|
||||||
}
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
uint8 i8237_r8x(t_bool io, uint8 data)
|
|
||||||
{
|
|
||||||
uint8 devnum;
|
|
||||||
|
|
||||||
if ((devnum = i8237_get_dn()) != 0xFF) {
|
|
||||||
if (io == 0) { /* read status register */
|
|
||||||
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r8[devnum] (status) read as %02X\n", i8237_r8[devnum]);
|
|
||||||
return (i8237_r8[devnum]);
|
|
||||||
} else { /* write command register */
|
|
||||||
i8237_r9[devnum] = data & 0xFF;
|
|
||||||
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r9[devnum] (command) set to %02X\n", i8237_r9[devnum]);
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
uint8 i8237_r9x(t_bool io, uint8 data)
|
|
||||||
{
|
|
||||||
uint8 devnum;
|
|
||||||
|
|
||||||
if ((devnum = i8237_get_dn()) != 0xFF) {
|
|
||||||
if (io == 0) {
|
|
||||||
sim_debug (DEBUG_reg, &i8237_dev, "Illegal read of i8237_r9[devnum]\n");
|
|
||||||
return 0;
|
|
||||||
} else { /* write request register */
|
|
||||||
i8237_rC[devnum] = data & 0xFF;
|
|
||||||
sim_debug (DEBUG_reg, &i8237_dev, "i8237_rC[devnum] (request) set to %02X\n", i8237_rC[devnum]);
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
uint8 i8237_rAx(t_bool io, uint8 data)
|
|
||||||
{
|
|
||||||
uint8 devnum;
|
|
||||||
|
|
||||||
if ((devnum = i8237_get_dn()) != 0xFF) {
|
|
||||||
if (io == 0) {
|
|
||||||
sim_debug (DEBUG_reg, &i8237_dev, "Illegal read of i8237_rA[devnum]\n");
|
|
||||||
return 0;
|
|
||||||
} else { /* write single mask register */
|
|
||||||
switch(data & 0x03) {
|
|
||||||
case 0:
|
|
||||||
if (data & 0x04)
|
|
||||||
i8237_rB[devnum] |= 1;
|
|
||||||
else
|
|
||||||
i8237_rB[devnum] &= ~1;
|
|
||||||
break;
|
|
||||||
case 1:
|
|
||||||
if (data & 0x04)
|
|
||||||
i8237_rB[devnum] |= 2;
|
|
||||||
else
|
|
||||||
i8237_rB[devnum] &= ~2;
|
|
||||||
break;
|
|
||||||
case 2:
|
|
||||||
if (data & 0x04)
|
|
||||||
i8237_rB[devnum] |= 4;
|
|
||||||
else
|
|
||||||
i8237_rB[devnum] &= ~4;
|
|
||||||
break;
|
|
||||||
case 3:
|
|
||||||
if (data & 0x04)
|
|
||||||
i8237_rB[devnum] |= 8;
|
|
||||||
else
|
|
||||||
i8237_rB[devnum] &= ~8;
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
sim_debug (DEBUG_reg, &i8237_dev, "i8237_rB[devnum] (mask) set to %02X\n", i8237_rB[devnum]);
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
uint8 i8237_rBx(t_bool io, uint8 data)
|
|
||||||
{
|
|
||||||
uint8 devnum;
|
|
||||||
|
|
||||||
if ((devnum = i8237_get_dn()) != 0xFF) {
|
|
||||||
if (io == 0) {
|
|
||||||
sim_debug (DEBUG_reg, &i8237_dev, "Illegal read of i8237_rB[devnum]\n");
|
|
||||||
return 0;
|
|
||||||
} else { /* write mode register */
|
|
||||||
i8237_rA[devnum] = data & 0xFF;
|
|
||||||
sim_debug (DEBUG_reg, &i8237_dev, "i8237_rA[devnum] (mode) set to %02X\n", i8237_rA[devnum]);
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
uint8 i8237_rCx(t_bool io, uint8 data)
|
|
||||||
{
|
|
||||||
uint8 devnum;
|
|
||||||
|
|
||||||
if ((devnum = i8237_get_dn()) != 0xFF) {
|
|
||||||
if (io == 0) {
|
|
||||||
sim_debug (DEBUG_reg, &i8237_dev, "Illegal read of i8237_rC[devnum]\n");
|
|
||||||
return 0;
|
|
||||||
} else { /* clear byte pointer FF */
|
|
||||||
i8237_rD[devnum] = 0;
|
i8237_rD[devnum] = 0;
|
||||||
sim_debug (DEBUG_reg, &i8237_dev, "i8237_rD[devnum] (FF) cleared\n");
|
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r0[devnum](H) read as %04X\n", i8237_r0[devnum]);
|
||||||
return 0;
|
return (i8237_r0[devnum] >> 8);
|
||||||
|
} else { /* low byte */
|
||||||
|
i8237_rD[devnum]++;
|
||||||
|
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r0[devnum](L) read as %04X\n", i8237_r0[devnum]);
|
||||||
|
return (i8237_r0[devnum] & 0xFF);
|
||||||
|
}
|
||||||
|
} else { /* write base & current address CH 0 */
|
||||||
|
if (i8237_rD[devnum]) { /* high byte */
|
||||||
|
i8237_rD[devnum] = 0;
|
||||||
|
i8237_r0[devnum] |= (data << 8);
|
||||||
|
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r0[devnum](H) set to %04X\n", i8237_r0[devnum]);
|
||||||
|
} else { /* low byte */
|
||||||
|
i8237_rD[devnum]++;
|
||||||
|
i8237_r0[devnum] = data & 0xFF;
|
||||||
|
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r0[devnum](L) set to %04X\n", i8237_r0[devnum]);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
uint8 i8237_rDx(t_bool io, uint8 data)
|
uint8 i8237_r1x(t_bool io, uint8 data, uint8 devnum)
|
||||||
{
|
{
|
||||||
uint8 devnum;
|
if (io == 0) { /* read current word count CH 0 */
|
||||||
|
if (i8237_rD[devnum]) { /* high byte */
|
||||||
if ((devnum = i8237_get_dn()) != 0xFF) {
|
i8237_rD[devnum] = 0;
|
||||||
if (io == 0) { /* read temporary register */
|
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r1[devnum](H) read as %04X\n", i8237_r1[devnum]);
|
||||||
sim_debug (DEBUG_reg, &i8237_dev, "Illegal read of i8237_rD[devnum]\n");
|
return (i8237_r1[devnum] >> 8);
|
||||||
return 0;
|
} else { /* low byte */
|
||||||
} else { /* master clear */
|
i8237_rD[devnum]++;
|
||||||
i8237_reset1();
|
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r1[devnum](L) read as %04X\n", i8237_r1[devnum]);
|
||||||
sim_debug (DEBUG_reg, &i8237_dev, "i8237 master clear\n");
|
return (i8237_r1[devnum] & 0xFF);
|
||||||
return 0;
|
}
|
||||||
|
} else { /* write base & current address CH 0 */
|
||||||
|
if (i8237_rD[devnum]) { /* high byte */
|
||||||
|
i8237_rD[devnum] = 0;
|
||||||
|
i8237_r1[devnum] |= (data << 8);
|
||||||
|
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r1[devnum](H) set to %04X\n", i8237_r1[devnum]);
|
||||||
|
} else { /* low byte */
|
||||||
|
i8237_rD[devnum]++;
|
||||||
|
i8237_r1[devnum] = data & 0xFF;
|
||||||
|
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r1[devnum](L) set to %04X\n", i8237_r1[devnum]);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
uint8 i8237_rEx(t_bool io, uint8 data)
|
uint8 i8237_r2x(t_bool io, uint8 data, uint8 devnum)
|
||||||
{
|
{
|
||||||
uint8 devnum;
|
if (io == 0) { /* read current address CH 1 */
|
||||||
|
if (i8237_rD[devnum]) { /* high byte */
|
||||||
if ((devnum = i8237_get_dn()) != 0xFF) {
|
i8237_rD[devnum] = 0;
|
||||||
if (io == 0) {
|
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r2[devnum](H) read as %04X\n", i8237_r2[devnum]);
|
||||||
sim_debug (DEBUG_reg, &i8237_dev, "Illegal read of i8237_rE[devnum]\n");
|
return (i8237_r2[devnum] >> 8);
|
||||||
return 0;
|
} else { /* low byte */
|
||||||
} else { /* clear mask register */
|
i8237_rD[devnum]++;
|
||||||
i8237_rB[devnum] = 0;
|
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r2[devnum](L) read as %04X\n", i8237_r2[devnum]);
|
||||||
sim_debug (DEBUG_reg, &i8237_dev, "i8237_rB[devnum] (mask) cleared\n");
|
return (i8237_r2[devnum] & 0xFF);
|
||||||
return 0;
|
}
|
||||||
|
} else { /* write base & current address CH 1 */
|
||||||
|
if (i8237_rD[devnum]) { /* high byte */
|
||||||
|
i8237_rD[devnum] = 0;
|
||||||
|
i8237_r2[devnum] |= (data << 8);
|
||||||
|
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r2[devnum](H) set to %04X\n", i8237_r2[devnum]);
|
||||||
|
} else { /* low byte */
|
||||||
|
i8237_rD[devnum]++;
|
||||||
|
i8237_r2[devnum] = data & 0xFF;
|
||||||
|
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r2[devnum](L) set to %04X\n", i8237_r2[devnum]);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
uint8 i8237_rFx(t_bool io, uint8 data)
|
uint8 i8237_r3x(t_bool io, uint8 data, uint8 devnum)
|
||||||
{
|
{
|
||||||
uint8 devnum;
|
if (io == 0) { /* read current word count CH 1 */
|
||||||
|
if (i8237_rD[devnum]) { /* high byte */
|
||||||
if ((devnum = i8237_get_dn()) != 0xFF) {
|
i8237_rD[devnum] = 0;
|
||||||
if (io == 0) {
|
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r3[devnum](H) read as %04X\n", i8237_r3[devnum]);
|
||||||
sim_debug (DEBUG_reg, &i8237_dev, "Illegal read of i8237_rF[devnum]\n");
|
return (i8237_r3[devnum] >> 8);
|
||||||
return 0;
|
} else { /* low byte */
|
||||||
} else { /* write all mask register bits */
|
i8237_rD[devnum]++;
|
||||||
i8237_rB[devnum] = data & 0x0F;
|
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r3[devnum](L) read as %04X\n", i8237_r3[devnum]);
|
||||||
sim_debug (DEBUG_reg, &i8237_dev, "i8237_rB[devnum] (mask) set to %02X\n", i8237_rB[devnum]);
|
return (i8237_r3[devnum] & 0xFF);
|
||||||
return 0;
|
|
||||||
}
|
}
|
||||||
|
} else { /* write base & current address CH 1 */
|
||||||
|
if (i8237_rD[devnum]) { /* high byte */
|
||||||
|
i8237_rD[devnum] = 0;
|
||||||
|
i8237_r3[devnum] |= (data << 8);
|
||||||
|
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r3[devnum](H) set to %04X\n", i8237_r3[devnum]);
|
||||||
|
} else { /* low byte */
|
||||||
|
i8237_rD[devnum]++;
|
||||||
|
i8237_r3[devnum] = data & 0xFF;
|
||||||
|
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r3[devnum](L) set to %04X\n", i8237_r3[devnum]);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
uint8 i8237_r4x(t_bool io, uint8 data, uint8 devnum)
|
||||||
|
{
|
||||||
|
if (io == 0) { /* read current address CH 2 */
|
||||||
|
if (i8237_rD[devnum]) { /* high byte */
|
||||||
|
i8237_rD[devnum] = 0;
|
||||||
|
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r4[devnum](H) read as %04X\n", i8237_r4[devnum]);
|
||||||
|
return (i8237_r4[devnum] >> 8);
|
||||||
|
} else { /* low byte */
|
||||||
|
i8237_rD[devnum]++;
|
||||||
|
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r4[devnum](L) read as %04X\n", i8237_r4[devnum]);
|
||||||
|
return (i8237_r4[devnum] & 0xFF);
|
||||||
|
}
|
||||||
|
} else { /* write base & current address CH 2 */
|
||||||
|
if (i8237_rD[devnum]) { /* high byte */
|
||||||
|
i8237_rD[devnum] = 0;
|
||||||
|
i8237_r4[devnum] |= (data << 8);
|
||||||
|
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r4[devnum](H) set to %04X\n", i8237_r4[devnum]);
|
||||||
|
} else { /* low byte */
|
||||||
|
i8237_rD[devnum]++;
|
||||||
|
i8237_r4[devnum] = data & 0xFF;
|
||||||
|
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r4[devnum](L) set to %04X\n", i8237_r4[devnum]);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
uint8 i8237_r5x(t_bool io, uint8 data, uint8 devnum)
|
||||||
|
{
|
||||||
|
if (io == 0) { /* read current word count CH 2 */
|
||||||
|
if (i8237_rD[devnum]) { /* high byte */
|
||||||
|
i8237_rD[devnum] = 0;
|
||||||
|
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r5[devnum](H) read as %04X\n", i8237_r5[devnum]);
|
||||||
|
return (i8237_r5[devnum] >> 8);
|
||||||
|
} else { /* low byte */
|
||||||
|
i8237_rD[devnum]++;
|
||||||
|
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r5[devnum](L) read as %04X\n", i8237_r5[devnum]);
|
||||||
|
return (i8237_r5[devnum] & 0xFF);
|
||||||
|
}
|
||||||
|
} else { /* write base & current address CH 2 */
|
||||||
|
if (i8237_rD[devnum]) { /* high byte */
|
||||||
|
i8237_rD[devnum] = 0;
|
||||||
|
i8237_r5[devnum] |= (data << 8);
|
||||||
|
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r5[devnum](H) set to %04X\n", i8237_r5[devnum]);
|
||||||
|
} else { /* low byte */
|
||||||
|
i8237_rD[devnum]++;
|
||||||
|
i8237_r5[devnum] = data & 0xFF;
|
||||||
|
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r5[devnum](L) set to %04X\n", i8237_r5[devnum]);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
uint8 i8237_r6x(t_bool io, uint8 data, uint8 devnum)
|
||||||
|
{
|
||||||
|
if (io == 0) { /* read current address CH 3 */
|
||||||
|
if (i8237_rD[devnum]) { /* high byte */
|
||||||
|
i8237_rD[devnum] = 0;
|
||||||
|
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r6[devnum](H) read as %04X\n", i8237_r6[devnum]);
|
||||||
|
return (i8237_r6[devnum] >> 8);
|
||||||
|
} else { /* low byte */
|
||||||
|
i8237_rD[devnum]++;
|
||||||
|
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r6[devnum](L) read as %04X\n", i8237_r6[devnum]);
|
||||||
|
return (i8237_r6[devnum] & 0xFF);
|
||||||
|
}
|
||||||
|
} else { /* write base & current address CH 3 */
|
||||||
|
if (i8237_rD[devnum]) { /* high byte */
|
||||||
|
i8237_rD[devnum] = 0;
|
||||||
|
i8237_r6[devnum] |= (data << 8);
|
||||||
|
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r6[devnum](H) set to %04X\n", i8237_r6[devnum]);
|
||||||
|
} else { /* low byte */
|
||||||
|
i8237_rD[devnum]++;
|
||||||
|
i8237_r6[devnum] = data & 0xFF;
|
||||||
|
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r6[devnum](L) set to %04X\n", i8237_r6[devnum]);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
uint8 i8237_r7x(t_bool io, uint8 data, uint8 devnum)
|
||||||
|
{
|
||||||
|
if (io == 0) { /* read current word count CH 3 */
|
||||||
|
if (i8237_rD[devnum]) { /* high byte */
|
||||||
|
i8237_rD[devnum] = 0;
|
||||||
|
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r7[devnum](H) read as %04X\n", i8237_r7[devnum]);
|
||||||
|
return (i8237_r7[devnum] >> 8);
|
||||||
|
} else { /* low byte */
|
||||||
|
i8237_rD[devnum]++;
|
||||||
|
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r7[devnum](L) read as %04X\n", i8237_r7[devnum]);
|
||||||
|
return (i8237_r7[devnum] & 0xFF);
|
||||||
|
}
|
||||||
|
} else { /* write base & current address CH 3 */
|
||||||
|
if (i8237_rD[devnum]) { /* high byte */
|
||||||
|
i8237_rD[devnum] = 0;
|
||||||
|
i8237_r7[devnum] |= (data << 8);
|
||||||
|
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r7[devnum](H) set to %04X\n", i8237_r7[devnum]);
|
||||||
|
} else { /* low byte */
|
||||||
|
i8237_rD[devnum]++;
|
||||||
|
i8237_r7[devnum] = data & 0xFF;
|
||||||
|
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r7[devnum](L) set to %04X\n", i8237_r7[devnum]);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
uint8 i8237_r8x(t_bool io, uint8 data, uint8 devnum)
|
||||||
|
{
|
||||||
|
if (io == 0) { /* read status register */
|
||||||
|
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r8[devnum] (status) read as %02X\n", i8237_r8[devnum]);
|
||||||
|
return (i8237_r8[devnum]);
|
||||||
|
} else { /* write command register */
|
||||||
|
i8237_r9[devnum] = data & 0xFF;
|
||||||
|
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r9[devnum] (command) set to %02X\n", i8237_r9[devnum]);
|
||||||
|
}
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
uint8 i8237_r9x(t_bool io, uint8 data, uint8 devnum)
|
||||||
|
{
|
||||||
|
if (io == 0) {
|
||||||
|
sim_debug (DEBUG_reg, &i8237_dev, "Illegal read of i8237_r9[devnum]\n");
|
||||||
|
return 0;
|
||||||
|
} else { /* write request register */
|
||||||
|
i8237_rC[devnum] = data & 0xFF;
|
||||||
|
sim_debug (DEBUG_reg, &i8237_dev, "i8237_rC[devnum] (request) set to %02X\n", i8237_rC[devnum]);
|
||||||
|
}
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
uint8 i8237_rAx(t_bool io, uint8 data, uint8 devnum)
|
||||||
|
{
|
||||||
|
if (io == 0) {
|
||||||
|
sim_debug (DEBUG_reg, &i8237_dev, "Illegal read of i8237_rA[devnum]\n");
|
||||||
|
return 0;
|
||||||
|
} else { /* write single mask register */
|
||||||
|
switch(data & 0x03) {
|
||||||
|
case 0:
|
||||||
|
if (data & 0x04)
|
||||||
|
i8237_rB[devnum] |= 1;
|
||||||
|
else
|
||||||
|
i8237_rB[devnum] &= ~1;
|
||||||
|
break;
|
||||||
|
case 1:
|
||||||
|
if (data & 0x04)
|
||||||
|
i8237_rB[devnum] |= 2;
|
||||||
|
else
|
||||||
|
i8237_rB[devnum] &= ~2;
|
||||||
|
break;
|
||||||
|
case 2:
|
||||||
|
if (data & 0x04)
|
||||||
|
i8237_rB[devnum] |= 4;
|
||||||
|
else
|
||||||
|
i8237_rB[devnum] &= ~4;
|
||||||
|
break;
|
||||||
|
case 3:
|
||||||
|
if (data & 0x04)
|
||||||
|
i8237_rB[devnum] |= 8;
|
||||||
|
else
|
||||||
|
i8237_rB[devnum] &= ~8;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
sim_debug (DEBUG_reg, &i8237_dev, "i8237_rB[devnum] (mask) set to %02X\n", i8237_rB[devnum]);
|
||||||
|
}
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
uint8 i8237_rBx(t_bool io, uint8 data, uint8 devnum)
|
||||||
|
{
|
||||||
|
if (io == 0) {
|
||||||
|
sim_debug (DEBUG_reg, &i8237_dev, "Illegal read of i8237_rB[devnum]\n");
|
||||||
|
return 0;
|
||||||
|
} else { /* write mode register */
|
||||||
|
i8237_rA[devnum] = data & 0xFF;
|
||||||
|
sim_debug (DEBUG_reg, &i8237_dev, "i8237_rA[devnum] (mode) set to %02X\n", i8237_rA[devnum]);
|
||||||
|
}
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
uint8 i8237_rCx(t_bool io, uint8 data, uint8 devnum)
|
||||||
|
{
|
||||||
|
if (io == 0) {
|
||||||
|
sim_debug (DEBUG_reg, &i8237_dev, "Illegal read of i8237_rC[devnum]\n");
|
||||||
|
return 0;
|
||||||
|
} else { /* clear byte pointer FF */
|
||||||
|
i8237_rD[devnum] = 0;
|
||||||
|
sim_debug (DEBUG_reg, &i8237_dev, "i8237_rD[devnum] (FF) cleared\n");
|
||||||
|
}
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
uint8 i8237_rDx(t_bool io, uint8 data, uint8 devnum)
|
||||||
|
{
|
||||||
|
if (io == 0) { /* read temporary register */
|
||||||
|
sim_debug (DEBUG_reg, &i8237_dev, "Illegal read of i8237_rD[devnum]\n");
|
||||||
|
return 0;
|
||||||
|
} else { /* master clear */
|
||||||
|
i8237_reset_dev(devnum);
|
||||||
|
sim_debug (DEBUG_reg, &i8237_dev, "i8237 master clear\n");
|
||||||
|
}
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
uint8 i8237_rEx(t_bool io, uint8 data, uint8 devnum)
|
||||||
|
{
|
||||||
|
if (io == 0) {
|
||||||
|
sim_debug (DEBUG_reg, &i8237_dev, "Illegal read of i8237_rE[devnum]\n");
|
||||||
|
return 0;
|
||||||
|
} else { /* clear mask register */
|
||||||
|
i8237_rB[devnum] = 0;
|
||||||
|
sim_debug (DEBUG_reg, &i8237_dev, "i8237_rB[devnum] (mask) cleared\n");
|
||||||
|
}
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
uint8 i8237_rFx(t_bool io, uint8 data, uint8 devnum)
|
||||||
|
{
|
||||||
|
if (io == 0) {
|
||||||
|
sim_debug (DEBUG_reg, &i8237_dev, "Illegal read of i8237_rF[devnum]\n");
|
||||||
|
return 0;
|
||||||
|
} else { /* write all mask register bits */
|
||||||
|
i8237_rB[devnum] = data & 0x0F;
|
||||||
|
sim_debug (DEBUG_reg, &i8237_dev, "i8237_rB[devnum] (mask) set to %02X\n", i8237_rB[devnum]);
|
||||||
}
|
}
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
|
||||||
|
|
@ -135,14 +135,16 @@ uint8 EPROM_get_mbyte(uint16 addr)
|
||||||
{
|
{
|
||||||
uint8 val;
|
uint8 val;
|
||||||
|
|
||||||
if ((addr >= EPROM_unit.u3) && ((uint32) addr <= (EPROM_unit.u3 + EPROM_unit.capac))) {
|
if ((addr >= EPROM_unit.u3) && ((uint16) addr <= (EPROM_unit.u3 + EPROM_unit.capac))) {
|
||||||
SET_XACK(1); /* good memory address */
|
SET_XACK(1); /* good memory address */
|
||||||
val = *((uint8 *)EPROM_unit.filebuf + (addr - EPROM_unit.u3));
|
val = *((uint8 *)EPROM_unit.filebuf + (addr - EPROM_unit.u3));
|
||||||
val &= 0xFF;
|
val &= 0xFF;
|
||||||
return val;
|
return val;
|
||||||
} else {
|
} else {
|
||||||
|
SET_XACK(0); /* bad memory address */
|
||||||
sim_printf("EPROM: Out of range\n");
|
sim_printf("EPROM: Out of range\n");
|
||||||
}
|
}
|
||||||
|
SET_XACK(0); /* bad memory address */
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -136,7 +136,7 @@ uint8 EPROM1_get_mbyte(uint16 addr)
|
||||||
{
|
{
|
||||||
uint8 val;
|
uint8 val;
|
||||||
|
|
||||||
if ((addr >= EPROM1_unit->u3) && ((uint32) addr <= (EPROM1_unit->u3 + EPROM1_unit->capac))) {
|
if ((addr >= EPROM1_unit->u3) && ((uint16) addr <= (EPROM1_unit->u3 + EPROM1_unit->capac))) {
|
||||||
SET_XACK(1); /* good memory address */
|
SET_XACK(1); /* good memory address */
|
||||||
val = *((uint8 *)EPROM1_unit->filebuf + (addr - EPROM1_unit->u3));
|
val = *((uint8 *)EPROM1_unit->filebuf + (addr - EPROM1_unit->u3));
|
||||||
val &= 0xFF;
|
val &= 0xFF;
|
||||||
|
|
|
||||||
|
|
@ -92,7 +92,7 @@ t_stat SBC_config(void)
|
||||||
i8255_cfg(I8255_BASE_0, 0);
|
i8255_cfg(I8255_BASE_0, 0);
|
||||||
i8255_cfg(I8255_BASE_1, 1);
|
i8255_cfg(I8255_BASE_1, 1);
|
||||||
i8259_cfg(I8259_BASE_0, 0);
|
i8259_cfg(I8259_BASE_0, 0);
|
||||||
i8259_cfg(I8259_BASE_1, 0);
|
i8259_cfg(I8259_BASE_1, 1);
|
||||||
ipc_cont_cfg(ICONT_BASE, 0);
|
ipc_cont_cfg(ICONT_BASE, 0);
|
||||||
ioc_cont_cfg(DBB_BASE, 0);
|
ioc_cont_cfg(DBB_BASE, 0);
|
||||||
EPROM_cfg(ROM_BASE, ROM_SIZE);
|
EPROM_cfg(ROM_BASE, ROM_SIZE);
|
||||||
|
|
|
||||||
|
|
@ -94,7 +94,7 @@ t_stat SBC_config(void)
|
||||||
i8255_cfg(I8255_BASE_0, 0);
|
i8255_cfg(I8255_BASE_0, 0);
|
||||||
i8255_cfg(I8255_BASE_1, 1);
|
i8255_cfg(I8255_BASE_1, 1);
|
||||||
i8259_cfg(I8259_BASE_0, 0);
|
i8259_cfg(I8259_BASE_0, 0);
|
||||||
i8259_cfg(I8259_BASE_1, 0);
|
i8259_cfg(I8259_BASE_1, 1);
|
||||||
ipc_cont_cfg(ICONT_BASE, 0);
|
ipc_cont_cfg(ICONT_BASE, 0);
|
||||||
ioc_cont_cfg(DBB_BASE, 0);
|
ioc_cont_cfg(DBB_BASE, 0);
|
||||||
EPROM_cfg(ROM_BASE, ROM_SIZE);
|
EPROM_cfg(ROM_BASE, ROM_SIZE);
|
||||||
|
|
|
||||||
|
|
@ -118,11 +118,12 @@ uint8 RAM_get_mbyte(uint16 addr)
|
||||||
{
|
{
|
||||||
uint8 val;
|
uint8 val;
|
||||||
|
|
||||||
if ((addr >= RAM_unit.u3) && ((uint32) addr < (RAM_unit.u3 + RAM_unit.capac))) {
|
if ((addr >= RAM_unit.u3) && ((uint32) addr <= (RAM_unit.u3 + RAM_unit.capac))) {
|
||||||
SET_XACK(1); /* good memory address */
|
SET_XACK(1); /* good memory address */
|
||||||
val = *((uint8 *)RAM_unit.filebuf + (addr - RAM_unit.u3));
|
val = *((uint8 *)RAM_unit.filebuf + (addr - RAM_unit.u3));
|
||||||
return (val & 0xFF);
|
return (val & 0xFF);
|
||||||
} else {
|
} else {
|
||||||
|
SET_XACK(0); /* bad memory address */
|
||||||
return 0xFF;
|
return 0xFF;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
@ -131,11 +132,12 @@ uint8 RAM_get_mbyte(uint16 addr)
|
||||||
|
|
||||||
void RAM_put_mbyte(uint16 addr, uint8 val)
|
void RAM_put_mbyte(uint16 addr, uint8 val)
|
||||||
{
|
{
|
||||||
if ((addr >= RAM_unit.u3) && ((uint32)addr < RAM_unit.u3 + RAM_unit.capac)) {
|
if ((addr >= RAM_unit.u3) && ((uint32)addr <= RAM_unit.u3 + RAM_unit.capac)) {
|
||||||
SET_XACK(1); /* good memory address */
|
SET_XACK(1); /* good memory address */
|
||||||
*((uint8 *)RAM_unit.filebuf + (addr - RAM_unit.u3)) = val & 0xFF;
|
*((uint8 *)RAM_unit.filebuf + (addr - RAM_unit.u3)) = val & 0xFF;
|
||||||
return;
|
return;
|
||||||
} else {
|
} else {
|
||||||
|
SET_XACK(0); /* bad memory address */
|
||||||
return;
|
return;
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
|
||||||
|
|
@ -159,10 +159,12 @@ uint8 isbc064_get_mbyte(uint16 addr)
|
||||||
return (val & 0xFF);
|
return (val & 0xFF);
|
||||||
} else {
|
} else {
|
||||||
sim_printf("isbc064_get_mbyte: Read-Enabled Out of range addr=%04X PC=%04X\n", addr, PCX);
|
sim_printf("isbc064_get_mbyte: Read-Enabled Out of range addr=%04X PC=%04X\n", addr, PCX);
|
||||||
|
SET_XACK(0); /* bad memory address */
|
||||||
return 0xff; /* multibus has active high pullups and inversion */
|
return 0xff; /* multibus has active high pullups and inversion */
|
||||||
}
|
}
|
||||||
} //device is disabled/not installed
|
} //device is disabled/not installed
|
||||||
sim_printf ("isbc064_get_mbyte: Read-Disabled addr=%04X PC=%04X\n", addr, PCX);
|
sim_printf ("isbc064_get_mbyte: Read-Disabled addr=%04X PC=%04X\n", addr, PCX);
|
||||||
|
SET_XACK(0); /* bad memory address */
|
||||||
return 0xff; /* multibus has active high pullups and inversion */
|
return 0xff; /* multibus has active high pullups and inversion */
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
@ -171,16 +173,18 @@ uint8 isbc064_get_mbyte(uint16 addr)
|
||||||
void isbc064_put_mbyte(uint16 addr, uint8 val)
|
void isbc064_put_mbyte(uint16 addr, uint8 val)
|
||||||
{
|
{
|
||||||
if ((isbc064_dev.flags & DEV_DIS) == 0) { //device is enabled
|
if ((isbc064_dev.flags & DEV_DIS) == 0) { //device is enabled
|
||||||
if ((addr >= isbc064_unit.u3) && (addr < (isbc064_unit.u3 + isbc064_unit.capac))) {
|
if ((addr >= isbc064_unit.u3) && (addr <= (isbc064_unit.u3 + isbc064_unit.capac))) {
|
||||||
SET_XACK(1); /* good memory address */
|
SET_XACK(1); /* good memory address */
|
||||||
*((uint8 *)isbc064_unit.filebuf + (addr - isbc064_unit.u3)) = val & 0xFF;
|
*((uint8 *)isbc064_unit.filebuf + (addr - isbc064_unit.u3)) = val & 0xFF;
|
||||||
return;
|
return;
|
||||||
} else {
|
} else {
|
||||||
sim_printf("isbc064_put_mbyte: Write Out of range addr=%04X PC=%04X\n", addr, PCX);
|
sim_printf("isbc064_put_mbyte: Write Out of range addr=%04X PC=%04X\n", addr, PCX);
|
||||||
|
SET_XACK(0); /* bad memory address */
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
} //device is disabled/not installed
|
} //device is disabled/not installed
|
||||||
sim_printf ("isbc064_put_mbyte: Write-Disabled addr=%04X PC=%04X\n", addr, PCX);
|
sim_printf ("isbc064_put_mbyte: Write-Disabled addr=%04X PC=%04X\n", addr, PCX);
|
||||||
|
SET_XACK(0); /* bad memory address */
|
||||||
}
|
}
|
||||||
|
|
||||||
/* end of isbc064.c */
|
/* end of isbc064.c */
|
||||||
|
|
|
||||||
|
|
@ -421,13 +421,8 @@ uint8 isbc202r1(t_bool io, uint8 data, uint8 devnum)
|
||||||
if (io == 0) { /* read data port */
|
if (io == 0) { /* read data port */
|
||||||
fdc202.intff = 0; //clear interrupt FF
|
fdc202.intff = 0; //clear interrupt FF
|
||||||
fdc202.stat &= ~FDCINT;
|
fdc202.stat &= ~FDCINT;
|
||||||
if (fdc202.rdychg) {
|
fdc202.rtype = ROK;
|
||||||
fdc202.rtype = ROK;
|
return fdc202.rtype;
|
||||||
return fdc202.rtype;
|
|
||||||
} else {
|
|
||||||
fdc202.rtype = ROK;
|
|
||||||
return fdc202.rtype;
|
|
||||||
}
|
|
||||||
} else { /* write data port */
|
} else { /* write data port */
|
||||||
fdc202.iopb = data;
|
fdc202.iopb = data;
|
||||||
}
|
}
|
||||||
|
|
|
||||||
|
|
@ -395,13 +395,8 @@ uint8 isbc206r1(t_bool io, uint8 data, uint8 devnum)
|
||||||
if (io == 0) { /* read data port */
|
if (io == 0) { /* read data port */
|
||||||
hdc206.intff = 0; //clear interrupt FF
|
hdc206.intff = 0; //clear interrupt FF
|
||||||
hdc206.stat &= ~(HDCINT + 0x80);
|
hdc206.stat &= ~(HDCINT + 0x80);
|
||||||
if (hdc206.rdychg) {
|
hdc206.rtype = ROK;
|
||||||
hdc206.rtype = ROK;
|
return hdc206.rtype;
|
||||||
return hdc206.rtype;
|
|
||||||
} else {
|
|
||||||
hdc206.rtype = ROK;
|
|
||||||
return hdc206.rtype;
|
|
||||||
}
|
|
||||||
} else { /* write data port */
|
} else { /* write data port */
|
||||||
hdc206.iopb = data;
|
hdc206.iopb = data;
|
||||||
}
|
}
|
||||||
|
|
|
||||||
|
|
@ -840,7 +840,7 @@ t_stat isbc208_svc (UNIT *uptr)
|
||||||
} else { // get image addr for this d, h, c, s
|
} else { // get image addr for this d, h, c, s
|
||||||
if (fddst[uptr->u6] & TS)
|
if (fddst[uptr->u6] & TS)
|
||||||
imgadr = (cyl * bpc) /*+ (h * bpt)*/ + ((sec - 1) * ssize);
|
imgadr = (cyl * bpc) /*+ (h * bpt)*/ + ((sec - 1) * ssize);
|
||||||
else
|
else {
|
||||||
imgadr = (cyl * bpt) + ((sec - 1) * ssize);
|
imgadr = (cyl * bpt) + ((sec - 1) * ssize);
|
||||||
for (i=0; i<=i8237_r1; i++) { /* copy selected sector to memory */
|
for (i=0; i<=i8237_r1; i++) { /* copy selected sector to memory */
|
||||||
data = *(fbuf + (imgadr + i));
|
data = *(fbuf + (imgadr + i));
|
||||||
|
|
@ -860,6 +860,7 @@ t_stat isbc208_svc (UNIT *uptr)
|
||||||
if (h) { // on head one?
|
if (h) { // on head one?
|
||||||
i8272_w2++; // yes, step cylinder
|
i8272_w2++; // yes, step cylinder
|
||||||
h = 0; // back to head 0
|
h = 0; // back to head 0
|
||||||
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
i8272_w5 = secn;
|
i8272_w5 = secn;
|
||||||
|
|
@ -893,7 +894,7 @@ t_stat isbc208_svc (UNIT *uptr)
|
||||||
} else { // get image addr for this d, h, c, s
|
} else { // get image addr for this d, h, c, s
|
||||||
if (fddst[uptr->u6] == TS)
|
if (fddst[uptr->u6] == TS)
|
||||||
imgadr = (cyl * bpc) /*+ (h * bpt)*/ + ((sec - 1) * ssize);
|
imgadr = (cyl * bpc) /*+ (h * bpt)*/ + ((sec - 1) * ssize);
|
||||||
else
|
else {
|
||||||
imgadr = (cyl * bpt) + ((sec - 1) * ssize);
|
imgadr = (cyl * bpt) + ((sec - 1) * ssize);
|
||||||
for (i=0; i<=i8237_r1; i++) { /* copy selected memory to image */
|
for (i=0; i<=i8237_r1; i++) { /* copy selected memory to image */
|
||||||
data = multibus_get_mbyte(i8237_r0 + i);
|
data = multibus_get_mbyte(i8237_r0 + i);
|
||||||
|
|
@ -909,6 +910,7 @@ t_stat isbc208_svc (UNIT *uptr)
|
||||||
fclose(fp);
|
fclose(fp);
|
||||||
*/
|
*/
|
||||||
//*** need to step return results IAW table 3-11 in 143078-001
|
//*** need to step return results IAW table 3-11 in 143078-001
|
||||||
|
}
|
||||||
i8272_w2 = cyl; /* generate a current address mark */
|
i8272_w2 = cyl; /* generate a current address mark */
|
||||||
i8272_w3 = hed >> 2;
|
i8272_w3 = hed >> 2;
|
||||||
i8272_w4 = ++sec; /* next sector */
|
i8272_w4 = ++sec; /* next sector */
|
||||||
|
|
|
||||||
|
|
@ -33,8 +33,6 @@
|
||||||
|
|
||||||
#include "system_defs.h"
|
#include "system_defs.h"
|
||||||
|
|
||||||
#define SET_XACK(VAL) (xack = VAL)
|
|
||||||
|
|
||||||
/* prototypes */
|
/* prototypes */
|
||||||
|
|
||||||
t_stat isbc064_cfg(uint16 base, uint16 size);
|
t_stat isbc064_cfg(uint16 base, uint16 size);
|
||||||
|
|
@ -144,10 +142,12 @@ uint8 isbc464_get_mbyte(uint16 addr)
|
||||||
return (val & 0xFF);
|
return (val & 0xFF);
|
||||||
} else {
|
} else {
|
||||||
sim_printf("isbc464_get_mbyte: Out of range\n");
|
sim_printf("isbc464_get_mbyte: Out of range\n");
|
||||||
|
SET_XACK(0); /* bad memory address */
|
||||||
return 0; /* multibus has active high pullups and inversion */
|
return 0; /* multibus has active high pullups and inversion */
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
sim_printf ("isbc464_put_mbyte: Write-Disabled addr=%04X\n", addr);
|
sim_printf ("isbc464_put_mbyte: Write-Disabled addr=%04X\n", addr);
|
||||||
|
SET_XACK(0); /* bad memory address */
|
||||||
return 0; /* multibus has active high pullups and inversion */
|
return 0; /* multibus has active high pullups and inversion */
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
@ -161,15 +161,17 @@ void isbc464_put_mbyte(uint16 addr, uint8 val)
|
||||||
org = isbc464_unit.u3;
|
org = isbc464_unit.u3;
|
||||||
len = isbc464_unit.capac;
|
len = isbc464_unit.capac;
|
||||||
if ((addr >= org) && (addr < (org + len))) {
|
if ((addr >= org) && (addr < (org + len))) {
|
||||||
// SET_XACK(1); /* good memory address */
|
SET_XACK(0); /* bad memory address */
|
||||||
sim_printf ("isbc464_put_mbyte: Read-only Memory\n");
|
sim_printf ("isbc464_put_mbyte: Read-only Memory\n");
|
||||||
return;
|
return;
|
||||||
} else {
|
} else {
|
||||||
sim_printf ("isbc464_put_mbyte: Out of range\n");
|
sim_printf ("isbc464_put_mbyte: Out of range\n");
|
||||||
|
SET_XACK(0); /* bad memory address */
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
sim_printf ("isbc464_put_mbyte: Disabled\n");
|
sim_printf ("isbc464_put_mbyte: Disabled\n");
|
||||||
|
SET_XACK(0); /* bad memory address */
|
||||||
}
|
}
|
||||||
|
|
||||||
/* end of isbc464.c */
|
/* end of isbc464.c */
|
||||||
|
|
|
||||||
|
|
@ -334,7 +334,7 @@ void multibus_put_mbyte(uint16 addr, uint8 val)
|
||||||
{
|
{
|
||||||
SET_XACK(0); /* set no XACK */
|
SET_XACK(0); /* set no XACK */
|
||||||
if ((isbc064_dev.flags & DEV_DIS) == 0) { //device is enabled
|
if ((isbc064_dev.flags & DEV_DIS) == 0) { //device is enabled
|
||||||
if (addr >= SBC064_BASE && addr <= (SBC064_BASE + SBC064_SIZE - 1))
|
if ((addr >= SBC064_BASE) && (addr <= (SBC064_BASE + SBC064_SIZE - 1)))
|
||||||
isbc064_put_mbyte(addr, val);
|
isbc064_put_mbyte(addr, val);
|
||||||
} else {
|
} else {
|
||||||
return;
|
return;
|
||||||
|
|
|
||||||
|
|
@ -491,13 +491,8 @@ uint8 zx200ar1SD(t_bool io, uint8 data, uint8 devnum)
|
||||||
zx200a.intff = 0; //clear interrupt FF
|
zx200a.intff = 0; //clear interrupt FF
|
||||||
if (zx200a.intff)
|
if (zx200a.intff)
|
||||||
zx200a.SDstat &= ~FDCINT;
|
zx200a.SDstat &= ~FDCINT;
|
||||||
if (zx200a.rdychg) {
|
zx200a.rtype = ROK;
|
||||||
zx200a.rtype = ROK;
|
return zx200a.rtype;
|
||||||
return zx200a.rtype;
|
|
||||||
} else {
|
|
||||||
zx200a.rtype = ROK;
|
|
||||||
return zx200a.rtype;
|
|
||||||
}
|
|
||||||
} else { /* write control port */
|
} else { /* write control port */
|
||||||
zx200a.iopb = data;
|
zx200a.iopb = data;
|
||||||
}
|
}
|
||||||
|
|
|
||||||
|
|
@ -64,13 +64,13 @@ extern void RAM_put_mbyte(uint32 addr, uint8 val);
|
||||||
extern UNIT i8255_unit[];
|
extern UNIT i8255_unit[];
|
||||||
extern UNIT EPROM_unit;
|
extern UNIT EPROM_unit;
|
||||||
extern UNIT RAM_unit;
|
extern UNIT RAM_unit;
|
||||||
extern t_stat i8237_reset (DEVICE *dptr, uint16 base);
|
extern t_stat i8237_reset (DEVICE *dptr);
|
||||||
extern t_stat i8253_reset (DEVICE *dptr, uint16 base);
|
extern t_stat i8253_reset (DEVICE *dptr);
|
||||||
extern t_stat i8255_reset (DEVICE *dptr, uint16 base);
|
extern t_stat i8255_reset (DEVICE *dptr);
|
||||||
extern t_stat i8259_reset (DEVICE *dptr, uint16 base);
|
extern t_stat i8259_reset (DEVICE *dptr);
|
||||||
extern t_stat EPROM_reset (DEVICE *dptr, uint32 base, uint32 size);
|
extern t_stat EPROM_reset (DEVICE *dptr);
|
||||||
extern t_stat RAM_reset (DEVICE *dptr, uint32 base, uint32 size);
|
extern t_stat RAM_reset (DEVICE *dptr);
|
||||||
extern uint16 reg_dev(uint8 (*routine)(t_bool, uint8), uint16);
|
extern uint16 reg_dev(uint8 (*routine)(t_bool, uint8, uint8), uint16, uint8);
|
||||||
|
|
||||||
/* SBC reset routine */
|
/* SBC reset routine */
|
||||||
|
|
||||||
|
|
@ -158,12 +158,12 @@ uint8 enbnmi(t_bool io, uint8 data)
|
||||||
uint8 get_mbyte(uint32 addr)
|
uint8 get_mbyte(uint32 addr)
|
||||||
{
|
{
|
||||||
/* if local EPROM handle it */
|
/* if local EPROM handle it */
|
||||||
if ((addr >= (uint32)EPROM_unit.u3) && (addr < (uint32)(EPROM_unit.u3 + EPROM_unit.capac))) {
|
if ((addr >= (uint32)EPROM_unit.u3) && (addr <= (uint32)(EPROM_unit.u3 + EPROM_unit.capac))) {
|
||||||
// sim_printf("Write to R/O memory address %05X - ignored\n", addr);
|
// sim_printf("Write to R/O memory address %05X - ignored\n", addr);
|
||||||
return EPROM_get_mbyte(addr);
|
return EPROM_get_mbyte(addr);
|
||||||
}
|
}
|
||||||
/* if local RAM handle it */
|
/* if local RAM handle it */
|
||||||
if ((addr >= (uint32)RAM_unit.u3) && (addr < (uint32)(RAM_unit.u3 + RAM_unit.capac))) {
|
if ((addr >= (uint32)RAM_unit.u3) && (addr <= (uint32)(RAM_unit.u3 + RAM_unit.capac))) {
|
||||||
return RAM_get_mbyte(addr);
|
return RAM_get_mbyte(addr);
|
||||||
}
|
}
|
||||||
/* otherwise, try the pcbus */
|
/* otherwise, try the pcbus */
|
||||||
|
|
|
||||||
|
|
@ -59,11 +59,11 @@
|
||||||
|
|
||||||
/* set the base and size for the EPROM on the IBM PC */
|
/* set the base and size for the EPROM on the IBM PC */
|
||||||
#define ROM_BASE 0xFE000
|
#define ROM_BASE 0xFE000
|
||||||
#define ROM_SIZE 0x02000
|
#define ROM_SIZE 0x01FFF
|
||||||
|
|
||||||
/* set the base and size for the RAM on the IBM PC */
|
/* set the base and size for the RAM on the IBM PC */
|
||||||
#define RAM_BASE 0x00000
|
#define RAM_BASE 0x00000
|
||||||
#define RAM_SIZE 0x40000
|
#define RAM_SIZE 0x3FFFF
|
||||||
|
|
||||||
/* set INTR for CPU on the 8088 */
|
/* set INTR for CPU on the 8088 */
|
||||||
#define INT_R INT_1
|
#define INT_R INT_1
|
||||||
|
|
|
||||||
|
|
@ -127,10 +127,10 @@
|
||||||
|
|
||||||
/* Memory */
|
/* Memory */
|
||||||
|
|
||||||
#define MAXMEMSIZE 0x10000 /* 8080 max memory size */
|
#define MAXMEMSIZE 0x0FFFF /* 8080 max memory size */
|
||||||
#define MEMSIZE (i8080_unit.capac) /* 8080 actual memory size */
|
#define MEMSIZE (i8080_unit.capac) /* 8080 actual memory size */
|
||||||
#define ADDRMASK (MAXMEMSIZE - 1) /* 8080 address mask */
|
#define ADDRMASK (MAXMEMSIZE) /* 8080 address mask */
|
||||||
#define MEM_ADDR_OK(x) (((uint32) (x)) < MEMSIZE)
|
#define MEM_ADDR_OK(x) (((uint16) (x)) <= MEMSIZE)
|
||||||
|
|
||||||
/* debug definitions */
|
/* debug definitions */
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -127,10 +127,10 @@
|
||||||
|
|
||||||
/* Memory */
|
/* Memory */
|
||||||
|
|
||||||
#define MAXMEMSIZE 0x10000 /* 8080 max memory size */
|
#define MAXMEMSIZE 0x0FFFF /* 8080 max memory size */
|
||||||
#define MEMSIZE (i8080_unit.capac) /* 8080 actual memory size */
|
#define MEMSIZE (i8080_unit.capac) /* 8080 actual memory size */
|
||||||
#define ADDRMASK (MAXMEMSIZE - 1) /* 8080 address mask */
|
#define ADDRMASK (MAXMEMSIZE) /* 8080 address mask */
|
||||||
#define MEM_ADDR_OK(x) (((uint32) (x)) < MEMSIZE)
|
#define MEM_ADDR_OK(x) (((uint16) (x)) <= MEMSIZE)
|
||||||
|
|
||||||
/* debug definitions */
|
/* debug definitions */
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -101,7 +101,7 @@
|
||||||
|
|
||||||
/* set the base and size for the iSBC 464 ROM */
|
/* set the base and size for the iSBC 464 ROM */
|
||||||
#define SBC464_BASE 0xA800
|
#define SBC464_BASE 0xA800
|
||||||
#define SBC464_SIZE 0x4800
|
#define SBC464_SIZE 0x47FF
|
||||||
#define SBC464_NUM 0
|
#define SBC464_NUM 0
|
||||||
|
|
||||||
/* set INTR for CPU */
|
/* set INTR for CPU */
|
||||||
|
|
@ -127,10 +127,10 @@
|
||||||
|
|
||||||
/* Memory */
|
/* Memory */
|
||||||
|
|
||||||
#define MAXMEMSIZE 0x10000 /* 8080 max memory size */
|
#define MAXMEMSIZE 0x0FFFF /* 8080 max memory size */
|
||||||
#define MEMSIZE (i8080_unit.capac) /* 8080 actual memory size */
|
#define MEMSIZE (i8080_unit.capac) /* 8080 actual memory size */
|
||||||
#define ADDRMASK (MAXMEMSIZE - 1) /* 8080 address mask */
|
#define ADDRMASK (MAXMEMSIZE) /* 8080 address mask */
|
||||||
#define MEM_ADDR_OK(x) (((uint32) (x)) < MEMSIZE)
|
#define MEM_ADDR_OK(x) (((uint16) (x)) <= MEMSIZE)
|
||||||
|
|
||||||
/* debug definitions */
|
/* debug definitions */
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -71,7 +71,7 @@
|
||||||
/* set the base I/O address for the iSBC 201 */
|
/* set the base I/O address for the iSBC 201 */
|
||||||
#define SBC201_BASE 0x78
|
#define SBC201_BASE 0x78
|
||||||
#define SBC201_INT INT_2
|
#define SBC201_INT INT_2
|
||||||
#define SBC201_NUM 1
|
#define SBC201_NUM 0
|
||||||
|
|
||||||
/* set the base I/O address for the iSBC 202 */
|
/* set the base I/O address for the iSBC 202 */
|
||||||
#define SBC202_BASE 0x78
|
#define SBC202_BASE 0x78
|
||||||
|
|
@ -91,11 +91,11 @@
|
||||||
/* set the base for the zx-200a disk controller */
|
/* set the base for the zx-200a disk controller */
|
||||||
#define ZX200A_BASE 0x78
|
#define ZX200A_BASE 0x78
|
||||||
#define ZX200A_INT INT_2
|
#define ZX200A_INT INT_2
|
||||||
#define ZX200A_NUM 1
|
#define ZX200A_NUM 0
|
||||||
|
|
||||||
/* set the base and size for the iSBC 464 ROM */
|
/* set the base and size for the iSBC 464 ROM */
|
||||||
#define SBC464_BASE 0xA800
|
#define SBC464_BASE 0xA800
|
||||||
#define SBC464_SIZE 0x4800
|
#define SBC464_SIZE 0x47FF
|
||||||
#define SBC464_NUM 0
|
#define SBC464_NUM 0
|
||||||
|
|
||||||
/* set the base and size for the iSBC 064 RAM */
|
/* set the base and size for the iSBC 064 RAM */
|
||||||
|
|
@ -126,10 +126,10 @@
|
||||||
|
|
||||||
/* Memory */
|
/* Memory */
|
||||||
|
|
||||||
#define MAXMEMSIZE 0x10000 /* 8080 max memory size */
|
#define MAXMEMSIZE 0x0FFFF /* 8080 max memory size */
|
||||||
#define MEMSIZE (i8080_unit.capac) /* 8080 actual memory size */
|
#define MEMSIZE (i8080_unit.capac) /* 8080 actual memory size */
|
||||||
#define ADDRMASK (MAXMEMSIZE - 1) /* 8080 address mask */
|
#define ADDRMASK (MAXMEMSIZE) /* 8080 address mask */
|
||||||
#define MEM_ADDR_OK(x) (((uint32) (x)) < MEMSIZE)
|
#define MEM_ADDR_OK(x) (((uint16) (x)) <= MEMSIZE)
|
||||||
|
|
||||||
/* debug definitions */
|
/* debug definitions */
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -104,13 +104,13 @@ uint8 get_mbyte(uint16 addr)
|
||||||
{
|
{
|
||||||
uint8 val;
|
uint8 val;
|
||||||
|
|
||||||
if (((monitor_boot & 0x04) == 0) && (addr >= ROM0_BASE && addr <= ROM0_BASE + ROM0_SIZE))
|
if (((monitor_boot & 0x04) == 0) && (addr >= ROM0_BASE) && (addr <= (ROM0_BASE + ROM0_SIZE)))
|
||||||
val = EPROM_get_mbyte(addr);
|
val = EPROM_get_mbyte(addr);
|
||||||
else if (ROM1_SIZE && addr >= ROM1_BASE && addr <= ROM1_BASE + ROM1_SIZE)
|
else if (ROM1_SIZE && (addr >= ROM1_BASE) && (addr <= (ROM1_BASE + ROM1_SIZE)))
|
||||||
val = EPROM1_get_mbyte(addr);
|
val = EPROM1_get_mbyte(addr);
|
||||||
else val = multibus_get_mbyte(addr);
|
else val = multibus_get_mbyte(addr);
|
||||||
val &= 0xFF;
|
val &= 0xFF;
|
||||||
return(val);
|
return val;
|
||||||
}
|
}
|
||||||
|
|
||||||
/* get a word from memory */
|
/* get a word from memory */
|
||||||
|
|
|
||||||
|
|
@ -110,10 +110,10 @@
|
||||||
|
|
||||||
/* Memory */
|
/* Memory */
|
||||||
|
|
||||||
#define MAXMEMSIZE 0x10000 /* 8080 max memory size */
|
#define MAXMEMSIZE 0x0FFFF /* 8080 max memory size */
|
||||||
#define MEMSIZE (i8080_unit.capac) /* 8080 actual memory size */
|
#define MEMSIZE (i8080_unit.capac) /* 8080 actual memory size */
|
||||||
#define ADDRMASK (MAXMEMSIZE - 1) /* 8080 address mask */
|
#define ADDRMASK (MAXMEMSIZE) /* 8080 address mask */
|
||||||
#define MEM_ADDR_OK(x) (((uint32) (x)) < MEMSIZE)
|
#define MEM_ADDR_OK(x) (((uint16) (x)) <= MEMSIZE)
|
||||||
|
|
||||||
/* debug definitions */
|
/* debug definitions */
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -110,10 +110,10 @@
|
||||||
|
|
||||||
/* Memory */
|
/* Memory */
|
||||||
|
|
||||||
#define MAXMEMSIZE 0x10000 /* 8080 max memory size */
|
#define MAXMEMSIZE 0x0FFFF /* 8080 max memory size */
|
||||||
#define MEMSIZE (i8080_unit.capac) /* 8080 actual memory size */
|
#define MEMSIZE (i8080_unit.capac) /* 8080 actual memory size */
|
||||||
#define ADDRMASK (MAXMEMSIZE - 1) /* 8080 address mask */
|
#define ADDRMASK (MAXMEMSIZE) /* 8080 address mask */
|
||||||
#define MEM_ADDR_OK(x) (((uint32) (x)) < MEMSIZE)
|
#define MEM_ADDR_OK(x) (((uint16) (x)) <= MEMSIZE)
|
||||||
|
|
||||||
/* debug definitions */
|
/* debug definitions */
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -90,7 +90,7 @@
|
||||||
|
|
||||||
/* set the base and size for the iSBC 464 ROM */
|
/* set the base and size for the iSBC 464 ROM */
|
||||||
#define SBC464_BASE 0xA800
|
#define SBC464_BASE 0xA800
|
||||||
#define SBC464_SIZE 0x4800
|
#define SBC464_SIZE 0x47FF
|
||||||
#define SBC464_NUM 0
|
#define SBC464_NUM 0
|
||||||
|
|
||||||
/* multibus interrupt definitions */
|
/* multibus interrupt definitions */
|
||||||
|
|
@ -113,10 +113,10 @@
|
||||||
|
|
||||||
/* Memory */
|
/* Memory */
|
||||||
|
|
||||||
#define MAXMEMSIZE 0x10000 /* 8080 max memory size */
|
#define MAXMEMSIZE 0x0FFFF /* 8080 max memory size */
|
||||||
#define MEMSIZE (i8080_unit.capac) /* 8080 actual memory size */
|
#define MEMSIZE (i8080_unit.capac) /* 8080 actual memory size */
|
||||||
#define ADDRMASK (MAXMEMSIZE - 1) /* 8080 address mask */
|
#define ADDRMASK (MAXMEMSIZE) /* 8080 address mask */
|
||||||
#define MEM_ADDR_OK(x) (((uint32) (x)) < MEMSIZE)
|
#define MEM_ADDR_OK(x) (((uint16) (x)) <= MEMSIZE)
|
||||||
|
|
||||||
/* debug definitions */
|
/* debug definitions */
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -97,7 +97,7 @@
|
||||||
|
|
||||||
/* set the base and size for the iSBC 464 ROM */
|
/* set the base and size for the iSBC 464 ROM */
|
||||||
#define SBC464_BASE 0xA800
|
#define SBC464_BASE 0xA800
|
||||||
#define SBC464_SIZE 0x4800
|
#define SBC464_SIZE 0x47FF
|
||||||
#define SBC464_NUM 0
|
#define SBC464_NUM 0
|
||||||
|
|
||||||
/* multibus interrupt definitions */
|
/* multibus interrupt definitions */
|
||||||
|
|
@ -120,10 +120,10 @@
|
||||||
|
|
||||||
/* Memory */
|
/* Memory */
|
||||||
|
|
||||||
#define MAXMEMSIZE 0x10000 /* 8080 max memory size */
|
#define MAXMEMSIZE 0x0FFFF /* 8080 max memory size */
|
||||||
#define MEMSIZE (i8080_unit.capac) /* 8080 actual memory size */
|
#define MEMSIZE (i8080_unit.capac) /* 8080 actual memory size */
|
||||||
#define ADDRMASK (MAXMEMSIZE - 1) /* 8080 address mask */
|
#define ADDRMASK (MAXMEMSIZE) /* 8080 address mask */
|
||||||
#define MEM_ADDR_OK(x) (((uint32) (x)) < MEMSIZE)
|
#define MEM_ADDR_OK(x) (((uint16) (x)) <= MEMSIZE)
|
||||||
|
|
||||||
/* debug definitions */
|
/* debug definitions */
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -105,7 +105,7 @@
|
||||||
|
|
||||||
/* set the base and size for the iSBC 464 ROM */
|
/* set the base and size for the iSBC 464 ROM */
|
||||||
#define SBC464_BASE 0xA800
|
#define SBC464_BASE 0xA800
|
||||||
#define SBC464_SIZE 0x4800
|
#define SBC464_SIZE 0x47FF
|
||||||
#define SBC464_NUM 0
|
#define SBC464_NUM 0
|
||||||
|
|
||||||
/* multibus interrupt definitions */
|
/* multibus interrupt definitions */
|
||||||
|
|
@ -128,10 +128,10 @@
|
||||||
|
|
||||||
/* Memory */
|
/* Memory */
|
||||||
|
|
||||||
#define MAXMEMSIZE 0x10000 /* 8080 max memory size */
|
#define MAXMEMSIZE 0x0FFFF /* 8080 max memory size */
|
||||||
#define MEMSIZE (i8080_unit.capac) /* 8080 actual memory size */
|
#define MEMSIZE (i8080_unit.capac) /* 8080 actual memory size */
|
||||||
#define ADDRMASK (MAXMEMSIZE - 1) /* 8080 address mask */
|
#define ADDRMASK (MAXMEMSIZE) /* 8080 address mask */
|
||||||
#define MEM_ADDR_OK(x) (((uint32) (x)) < MEMSIZE)
|
#define MEM_ADDR_OK(x) (((uint16) (x)) <= MEMSIZE)
|
||||||
|
|
||||||
/* debug definitions */
|
/* debug definitions */
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -100,7 +100,7 @@
|
||||||
|
|
||||||
/* set the base and size for the iSBC 464 ROM */
|
/* set the base and size for the iSBC 464 ROM */
|
||||||
#define SBC464_BASE 0xA800
|
#define SBC464_BASE 0xA800
|
||||||
#define SBC464_SIZE 0x4800
|
#define SBC464_SIZE 0x47FF
|
||||||
#define SBC464_NUM 0
|
#define SBC464_NUM 0
|
||||||
|
|
||||||
/* multibus interrupt definitions */
|
/* multibus interrupt definitions */
|
||||||
|
|
@ -123,10 +123,10 @@
|
||||||
|
|
||||||
/* Memory */
|
/* Memory */
|
||||||
|
|
||||||
#define MAXMEMSIZE 0x10000 /* 8080 max memory size */
|
#define MAXMEMSIZE 0x0FFFF /* 8080 max memory size */
|
||||||
#define MEMSIZE (i8080_unit.capac) /* 8080 actual memory size */
|
#define MEMSIZE (i8080_unit.capac) /* 8080 actual memory size */
|
||||||
#define ADDRMASK (MAXMEMSIZE - 1) /* 8080 address mask */
|
#define ADDRMASK (MAXMEMSIZE) /* 8080 address mask */
|
||||||
#define MEM_ADDR_OK(x) (((uint32) (x)) < MEMSIZE)
|
#define MEM_ADDR_OK(x) (((uint16) (x)) <= MEMSIZE)
|
||||||
|
|
||||||
/* debug definitions */
|
/* debug definitions */
|
||||||
|
|
||||||
|
|
|
||||||
Loading…
Add table
Reference in a new issue