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Intel-Systems: Cleanup Coverity identified issues and address range issues

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This commit is contained in:
Bill Beech 2019-10-31 14:53:14 -07:00
parent 82d897712c
commit 58c5fe417f
28 changed files with 451 additions and 606 deletions
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65
Intel-Systems/common/i3214.c
View file

@ -36,71 +36,6 @@
All I/O is via programmed I/O. The i3214 has a status port
and two data port.
save for now!
A write to the status port can select some options for the device:
Asynchronous Mode Instruction
7 6 5 4 3 2 1 0
+---+---+---+---+---+---+---+---+
| S2 S1 EP PEN L2 L1 B2 B1|
+---+---+---+---+---+---+---+---+
Baud Rate Factor
B2 0 1 0 1
B1 0 0 1 1
sync 1X 16X 64X
mode
Character Length
L2 0 1 0 1
L1 0 0 1 1
5 6 7 8
bits bits bits bits
EP - A 1 in this bit position selects even parity.
PEN - A 1 in this bit position enables parity.
Number of Stop Bits
S2 0 1 0 1
S1 0 0 1 1
invalid 1 1.5 2
bit bits bits
Command Instruction Format
7 6 5 4 3 2 1 0
+---+---+---+---+---+---+---+---+
| EH IR RTS ER SBRK RxE DTR TxE|
+---+---+---+---+---+---+---+---+
TxE - A 1 in this bit position enables transmit.
DTR - A 1 in this bit position forces *DTR to zero.
RxE - A 1 in this bit position enables receive.
SBRK - A 1 in this bit position forces TxD to zero.
ER - A 1 in this bit position resets the error bits
RTS - A 1 in this bit position forces *RTS to zero.
IR - A 1 in this bit position returns the 8251 to Mode Instruction Format.
EH - A 1 in this bit position enables search for sync characters.
A read of the status port gets the port status:
Status Read Format
7 6 5 4 3 2 1 0
+---+---+---+---+---+---+---+---+
|DSR SD FE OE PE TxE RxR TxR|
+---+---+---+---+---+---+---+---+
TxR - A 1 in this bit position signals transmit ready to receive a character.
RxR - A 1 in this bit position signals receiver has a character.
TxE - A 1 in this bit position signals transmitter has no more characters to transmit.
PE - A 1 in this bit signals a parity error.
OE - A 1 in this bit signals an transmit overrun error.
FE - A 1 in this bit signals a framing error.
SD - A 1 in this bit position returns the 8251 to Mode Instruction Format.
DSR - A 1 in this bit position signals *DSR is at zero.
A read from the data port gets the typed character, a write
to the data port writes the character to the device.
*/
#include "system_defs.h"

20
Intel-Systems/common/i8080.c
View file

@ -475,12 +475,14 @@ int32 sim_instr(void)
IR = OP = fetch_byte(0); /* instruction fetch */
/*
if (GET_XACK(1) == 0) { // no XACK for instruction fetch
// reason = STOP_XACK;
if (uptr->flags & UNIT_XACK)
reason = STOP_XACK;
// if (uptr->flags & UNIT_XACK)
sim_printf("Failed XACK for Instruction Fetch from %04X\n", PCX);
// continue;
continue;
}
*/
// first instruction decode
if (OP == 0x76) { /* HLT Instruction*/
@ -886,11 +888,13 @@ int32 sim_instr(void)
case 0xDB: /* IN */
port = fetch_byte(1);
A = dev_table[port].routine(0, 0, dev_table[port].devnum);
SET_XACK(1); /* good I/O address */
break;
case 0xD3: /* OUT */
port = fetch_byte(1);
dev_table[port].routine(1, A, dev_table[port].devnum);
SET_XACK(1); /* good I/O address */
break;
default: /* undefined opcode */
@ -902,17 +906,19 @@ int32 sim_instr(void)
}
loop_end:
/*
if (GET_XACK(1) == 0) { // no XACK for operand fetch
// reason = STOP_XACK;
reason = STOP_XACK;
if (OP == 0xD3 || OP == 0xDB) {
if (uptr->flags & UNIT_XACK)
// if (uptr->flags & UNIT_XACK)
sim_printf("Failed XACK for Port %02X Fetch from %04X\n", port, PCX);
} else {
if (uptr->flags & UNIT_XACK)
// if (uptr->flags & UNIT_XACK)
sim_printf("Failed XACK for Operand %04X Fetch from %04X\n", addr, PCX);
// continue;
continue;
}
}
*/;
}
/* Simulation halted */

801
Intel-Systems/common/i8237.c
View file

@ -237,40 +237,35 @@
/* external globals */
extern uint16 port; //port called in dev_table[port]
/* internal function prototypes */
t_stat i8237_svc (UNIT *uptr);
t_stat i8237_reset (DEVICE *dptr, uint16 base);
void i8237_reset1 (void);
t_stat i8237_reset (DEVICE *dptr);
void i8237_reset_dev (uint8 devnum);
t_stat i8237_set_mode (UNIT *uptr, int32 val, CONST char *cptr, void *desc);
uint8 i8237_r0x(t_bool io, uint8 data);
uint8 i8237_r1x(t_bool io, uint8 data);
uint8 i8237_r2x(t_bool io, uint8 data);
uint8 i8237_r3x(t_bool io, uint8 data);
uint8 i8237_r4x(t_bool io, uint8 data);
uint8 i8237_r5x(t_bool io, uint8 data);
uint8 i8237_r6x(t_bool io, uint8 data);
uint8 i8237_r7x(t_bool io, uint8 data);
uint8 i8237_r8x(t_bool io, uint8 data);
uint8 i8237_r9x(t_bool io, uint8 data);
uint8 i8237_rAx(t_bool io, uint8 data);
uint8 i8237_rBx(t_bool io, uint8 data);
uint8 i8237_rCx(t_bool io, uint8 data);
uint8 i8237_rDx(t_bool io, uint8 data);
uint8 i8237_rEx(t_bool io, uint8 data);
uint8 i8237_rFx(t_bool io, uint8 data);
uint8 i8237_r0x(t_bool io, uint8 data, uint8 devnum);
uint8 i8237_r1x(t_bool io, uint8 data, uint8 devnum);
uint8 i8237_r2x(t_bool io, uint8 data, uint8 devnum);
uint8 i8237_r3x(t_bool io, uint8 data, uint8 devnum);
uint8 i8237_r4x(t_bool io, uint8 data, uint8 devnum);
uint8 i8237_r5x(t_bool io, uint8 data, uint8 devnum);
uint8 i8237_r6x(t_bool io, uint8 data, uint8 devnum);
uint8 i8237_r7x(t_bool io, uint8 data, uint8 devnum);
uint8 i8237_r8x(t_bool io, uint8 data, uint8 devnum);
uint8 i8237_r9x(t_bool io, uint8 data, uint8 devnum);
uint8 i8237_rAx(t_bool io, uint8 data, uint8 devnum);
uint8 i8237_rBx(t_bool io, uint8 data, uint8 devnum);
uint8 i8237_rCx(t_bool io, uint8 data, uint8 devnum);
uint8 i8237_rDx(t_bool io, uint8 data, uint8 devnum);
uint8 i8237_rEx(t_bool io, uint8 data, uint8 devnum);
uint8 i8237_rFx(t_bool io, uint8 data, uint8 devnum);
/* external function prototypes */
extern uint8 reg_dev(uint8 (*routine)(t_bool, uint8, uint8), uint8);
extern uint8 reg_dev(uint8 (*routine)(t_bool, uint8, uint8), uint8, uint8);
/* globals */
int32 i8237_devnum = 0; //actual number of 8253 instances + 1
uint16 i8237_port[4]; //base port registered to each instance
/* 8237 physical register definitions */
uint16 i8237_r0[4]; // 8237 ch 0 address register
@ -405,7 +400,7 @@ DEVICE i8237_dev = {
8, //dwidth
NULL, //examine
NULL, //deposit
NULL, //reset
i8237_reset, //reset
NULL, //boot
NULL, //attach
NULL, //detach
@ -419,6 +414,30 @@ DEVICE i8237_dev = {
/* Service routines to handle simulator functions */
// i8251 configuration
t_stat i8237_cfg(uint8 base, uint8 devnum)
{
sim_printf(" i8237[%d]: at base port 0%02XH\n",
devnum, base & 0xFF);
reg_dev(i8237_r1x, base + 1, devnum);
reg_dev(i8237_r2x, base + 2, devnum);
reg_dev(i8237_r3x, base + 3, devnum);
reg_dev(i8237_r4x, base + 4, devnum);
reg_dev(i8237_r5x, base + 5, devnum);
reg_dev(i8237_r6x, base + 6, devnum);
reg_dev(i8237_r7x, base + 7, devnum);
reg_dev(i8237_r8x, base + 8, devnum);
reg_dev(i8237_r9x, base + 9, devnum);
reg_dev(i8237_rAx, base + 10, devnum);
reg_dev(i8237_rBx, base + 11, devnum);
reg_dev(i8237_rCx, base + 12, devnum);
reg_dev(i8237_rDx, base + 13, devnum);
reg_dev(i8237_rEx, base + 14, devnum);
reg_dev(i8237_rFx, base + 15, devnum);
return SCPE_OK;
}
/* service routine - actually does the simulated DMA */
t_stat i8237_svc(UNIT *uptr)
@ -431,52 +450,20 @@ t_stat i8237_svc(UNIT *uptr)
t_stat i8237_reset(DEVICE *dptr)
{
if (i8237_devnum > I8237_NUM) {
sim_printf("i8237_reset: too many devices!\n");
return SCPE_MEM;
uint8 devnum;
for (devnum=0; devnum<I8237_NUM; devnum++) {
i8237_reset_dev(devnum);
sim_activate (&i8237_unit[devnum], i8237_unit[devnum].wait); /* activate unit */
}
i8237_port[i8237_devnum] = reg_dev(i8237_r0x, base);
reg_dev(i8237_r1x, base + 1);
reg_dev(i8237_r2x, base + 2);
reg_dev(i8237_r3x, base + 3);
reg_dev(i8237_r4x, base + 4);
reg_dev(i8237_r5x, base + 5);
reg_dev(i8237_r6x, base + 6);
reg_dev(i8237_r7x, base + 7);
reg_dev(i8237_r8x, base + 8);
reg_dev(i8237_r9x, base + 9);
reg_dev(i8237_rAx, base + 10);
reg_dev(i8237_rBx, base + 11);
reg_dev(i8237_rCx, base + 12);
reg_dev(i8237_rDx, base + 13);
reg_dev(i8237_rEx, base + 14);
reg_dev(i8237_rFx, base + 15);
sim_printf(" 8237 Reset\n");
sim_printf(" 8237: Registered at %03X\n", base);
sim_activate (&i8237_unit[i8237_devnum], i8237_unit[i8237_devnum].wait); /* activate unit */
if ((i8237_dev.flags & DEV_DIS) == 0)
i8237_reset1();
i8237_devnum++;
return SCPE_OK;
}
uint8 i8237_get_dn(void)
{
int i;
for (i=0; i<I8237_NUM; i++)
if (port >=i8237_port[i] && port <= i8237_port[i] + 16)
return i;
sim_printf("i8237_get_dn: port %03X not in 8237 device table\n", port);
return 0xFF;
}
void i8237_reset1(void)
void i8237_reset_dev(uint8 devnum)
{
int32 i;
UNIT *uptr;
static int flag = 1;
uint8 devnum;
for (i = 0; i < 1; i++) { /* handle all units */
uptr = i8237_dev.units + i;
@ -525,411 +512,331 @@ t_stat i8237_set_mode(UNIT *uptr, int32 val, CONST char *cptr, void *desc)
to the device.
*/
uint8 i8237_r0x(t_bool io, uint8 data)
uint8 i8237_r0x(t_bool io, uint8 data, uint8 devnum)
{
uint8 devnum;
if ((devnum = i8237_get_dn()) != 0xFF) {
if (io == 0) { /* read current address CH 0 */
if (i8237_rD[devnum]) { /* high byte */
i8237_rD[devnum] = 0;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r0[devnum](H) read as %04X\n", i8237_r0[devnum]);
return (i8237_r0[devnum] >> 8);
} else { /* low byte */
i8237_rD[devnum]++;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r0[devnum](L) read as %04X\n", i8237_r0[devnum]);
return (i8237_r0[devnum] & 0xFF);
}
} else { /* write base & current address CH 0 */
if (i8237_rD[devnum]) { /* high byte */
i8237_rD[devnum] = 0;
i8237_r0[devnum] |= (data << 8);
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r0[devnum](H) set to %04X\n", i8237_r0[devnum]);
} else { /* low byte */
i8237_rD[devnum]++;
i8237_r0[devnum] = data & 0xFF;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r0[devnum](L) set to %04X\n", i8237_r0[devnum]);
}
return 0;
}
}
return 0;
}
uint8 i8237_r1x(t_bool io, uint8 data)
{
uint8 devnum;
if ((devnum = i8237_get_dn()) != 0xFF) {
if (io == 0) { /* read current word count CH 0 */
if (i8237_rD[devnum]) { /* high byte */
i8237_rD[devnum] = 0;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r1[devnum](H) read as %04X\n", i8237_r1[devnum]);
return (i8237_r1[devnum] >> 8);
} else { /* low byte */
i8237_rD[devnum]++;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r1[devnum](L) read as %04X\n", i8237_r1[devnum]);
return (i8237_r1[devnum] & 0xFF);
}
} else { /* write base & current address CH 0 */
if (i8237_rD[devnum]) { /* high byte */
i8237_rD[devnum] = 0;
i8237_r1[devnum] |= (data << 8);
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r1[devnum](H) set to %04X\n", i8237_r1[devnum]);
} else { /* low byte */
i8237_rD[devnum]++;
i8237_r1[devnum] = data & 0xFF;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r1[devnum](L) set to %04X\n", i8237_r1[devnum]);
}
return 0;
}
}
return 0;
}
uint8 i8237_r2x(t_bool io, uint8 data)
{
uint8 devnum;
if ((devnum = i8237_get_dn()) != 0xFF) {
if (io == 0) { /* read current address CH 1 */
if (i8237_rD[devnum]) { /* high byte */
i8237_rD[devnum] = 0;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r2[devnum](H) read as %04X\n", i8237_r2[devnum]);
return (i8237_r2[devnum] >> 8);
} else { /* low byte */
i8237_rD[devnum]++;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r2[devnum](L) read as %04X\n", i8237_r2[devnum]);
return (i8237_r2[devnum] & 0xFF);
}
} else { /* write base & current address CH 1 */
if (i8237_rD[devnum]) { /* high byte */
i8237_rD[devnum] = 0;
i8237_r2[devnum] |= (data << 8);
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r2[devnum](H) set to %04X\n", i8237_r2[devnum]);
} else { /* low byte */
i8237_rD[devnum]++;
i8237_r2[devnum] = data & 0xFF;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r2[devnum](L) set to %04X\n", i8237_r2[devnum]);
}
return 0;
}
}
return 0;
}
uint8 i8237_r3x(t_bool io, uint8 data)
{
uint8 devnum;
if ((devnum = i8237_get_dn()) != 0xFF) {
if (io == 0) { /* read current word count CH 1 */
if (i8237_rD[devnum]) { /* high byte */
i8237_rD[devnum] = 0;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r3[devnum](H) read as %04X\n", i8237_r3[devnum]);
return (i8237_r3[devnum] >> 8);
} else { /* low byte */
i8237_rD[devnum]++;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r3[devnum](L) read as %04X\n", i8237_r3[devnum]);
return (i8237_r3[devnum] & 0xFF);
}
} else { /* write base & current address CH 1 */
if (i8237_rD[devnum]) { /* high byte */
i8237_rD[devnum] = 0;
i8237_r3[devnum] |= (data << 8);
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r3[devnum](H) set to %04X\n", i8237_r3[devnum]);
} else { /* low byte */
i8237_rD[devnum]++;
i8237_r3[devnum] = data & 0xFF;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r3[devnum](L) set to %04X\n", i8237_r3[devnum]);
}
return 0;
}
}
return 0;
}
uint8 i8237_r4x(t_bool io, uint8 data)
{
uint8 devnum;
if ((devnum = i8237_get_dn()) != 0xFF) {
if (io == 0) { /* read current address CH 2 */
if (i8237_rD[devnum]) { /* high byte */
i8237_rD[devnum] = 0;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r4[devnum](H) read as %04X\n", i8237_r4[devnum]);
return (i8237_r4[devnum] >> 8);
} else { /* low byte */
i8237_rD[devnum]++;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r4[devnum](L) read as %04X\n", i8237_r4[devnum]);
return (i8237_r4[devnum] & 0xFF);
}
} else { /* write base & current address CH 2 */
if (i8237_rD[devnum]) { /* high byte */
i8237_rD[devnum] = 0;
i8237_r4[devnum] |= (data << 8);
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r4[devnum](H) set to %04X\n", i8237_r4[devnum]);
} else { /* low byte */
i8237_rD[devnum]++;
i8237_r4[devnum] = data & 0xFF;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r4[devnum](L) set to %04X\n", i8237_r4[devnum]);
}
return 0;
}
}
return 0;
}
uint8 i8237_r5x(t_bool io, uint8 data)
{
uint8 devnum;
if ((devnum = i8237_get_dn()) != 0xFF) {
if (io == 0) { /* read current word count CH 2 */
if (i8237_rD[devnum]) { /* high byte */
i8237_rD[devnum] = 0;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r5[devnum](H) read as %04X\n", i8237_r5[devnum]);
return (i8237_r5[devnum] >> 8);
} else { /* low byte */
i8237_rD[devnum]++;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r5[devnum](L) read as %04X\n", i8237_r5[devnum]);
return (i8237_r5[devnum] & 0xFF);
}
} else { /* write base & current address CH 2 */
if (i8237_rD[devnum]) { /* high byte */
i8237_rD[devnum] = 0;
i8237_r5[devnum] |= (data << 8);
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r5[devnum](H) set to %04X\n", i8237_r5[devnum]);
} else { /* low byte */
i8237_rD[devnum]++;
i8237_r5[devnum] = data & 0xFF;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r5[devnum](L) set to %04X\n", i8237_r5[devnum]);
}
return 0;
}
}
return 0;
}
uint8 i8237_r6x(t_bool io, uint8 data)
{
uint8 devnum;
if ((devnum = i8237_get_dn()) != 0xFF) {
if (io == 0) { /* read current address CH 3 */
if (i8237_rD[devnum]) { /* high byte */
i8237_rD[devnum] = 0;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r6[devnum](H) read as %04X\n", i8237_r6[devnum]);
return (i8237_r6[devnum] >> 8);
} else { /* low byte */
i8237_rD[devnum]++;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r6[devnum](L) read as %04X\n", i8237_r6[devnum]);
return (i8237_r6[devnum] & 0xFF);
}
} else { /* write base & current address CH 3 */
if (i8237_rD[devnum]) { /* high byte */
i8237_rD[devnum] = 0;
i8237_r6[devnum] |= (data << 8);
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r6[devnum](H) set to %04X\n", i8237_r6[devnum]);
} else { /* low byte */
i8237_rD[devnum]++;
i8237_r6[devnum] = data & 0xFF;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r6[devnum](L) set to %04X\n", i8237_r6[devnum]);
}
return 0;
}
}
return 0;
}
uint8 i8237_r7x(t_bool io, uint8 data)
{
uint8 devnum;
if ((devnum = i8237_get_dn()) != 0xFF) {
if (io == 0) { /* read current word count CH 3 */
if (i8237_rD[devnum]) { /* high byte */
i8237_rD[devnum] = 0;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r7[devnum](H) read as %04X\n", i8237_r7[devnum]);
return (i8237_r7[devnum] >> 8);
} else { /* low byte */
i8237_rD[devnum]++;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r7[devnum](L) read as %04X\n", i8237_r7[devnum]);
return (i8237_r7[devnum] & 0xFF);
}
} else { /* write base & current address CH 3 */
if (i8237_rD[devnum]) { /* high byte */
i8237_rD[devnum] = 0;
i8237_r7[devnum] |= (data << 8);
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r7[devnum](H) set to %04X\n", i8237_r7[devnum]);
} else { /* low byte */
i8237_rD[devnum]++;
i8237_r7[devnum] = data & 0xFF;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r7[devnum](L) set to %04X\n", i8237_r7[devnum]);
}
return 0;
}
}
return 0;
}
uint8 i8237_r8x(t_bool io, uint8 data)
{
uint8 devnum;
if ((devnum = i8237_get_dn()) != 0xFF) {
if (io == 0) { /* read status register */
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r8[devnum] (status) read as %02X\n", i8237_r8[devnum]);
return (i8237_r8[devnum]);
} else { /* write command register */
i8237_r9[devnum] = data & 0xFF;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r9[devnum] (command) set to %02X\n", i8237_r9[devnum]);
return 0;
}
}
return 0;
}
uint8 i8237_r9x(t_bool io, uint8 data)
{
uint8 devnum;
if ((devnum = i8237_get_dn()) != 0xFF) {
if (io == 0) {
sim_debug (DEBUG_reg, &i8237_dev, "Illegal read of i8237_r9[devnum]\n");
return 0;
} else { /* write request register */
i8237_rC[devnum] = data & 0xFF;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_rC[devnum] (request) set to %02X\n", i8237_rC[devnum]);
return 0;
}
}
return 0;
}
uint8 i8237_rAx(t_bool io, uint8 data)
{
uint8 devnum;
if ((devnum = i8237_get_dn()) != 0xFF) {
if (io == 0) {
sim_debug (DEBUG_reg, &i8237_dev, "Illegal read of i8237_rA[devnum]\n");
return 0;
} else { /* write single mask register */
switch(data & 0x03) {
case 0:
if (data & 0x04)
i8237_rB[devnum] |= 1;
else
i8237_rB[devnum] &= ~1;
break;
case 1:
if (data & 0x04)
i8237_rB[devnum] |= 2;
else
i8237_rB[devnum] &= ~2;
break;
case 2:
if (data & 0x04)
i8237_rB[devnum] |= 4;
else
i8237_rB[devnum] &= ~4;
break;
case 3:
if (data & 0x04)
i8237_rB[devnum] |= 8;
else
i8237_rB[devnum] &= ~8;
break;
}
sim_debug (DEBUG_reg, &i8237_dev, "i8237_rB[devnum] (mask) set to %02X\n", i8237_rB[devnum]);
return 0;
}
}
return 0;
}
uint8 i8237_rBx(t_bool io, uint8 data)
{
uint8 devnum;
if ((devnum = i8237_get_dn()) != 0xFF) {
if (io == 0) {
sim_debug (DEBUG_reg, &i8237_dev, "Illegal read of i8237_rB[devnum]\n");
return 0;
} else { /* write mode register */
i8237_rA[devnum] = data & 0xFF;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_rA[devnum] (mode) set to %02X\n", i8237_rA[devnum]);
return 0;
}
}
return 0;
}
uint8 i8237_rCx(t_bool io, uint8 data)
{
uint8 devnum;
if ((devnum = i8237_get_dn()) != 0xFF) {
if (io == 0) {
sim_debug (DEBUG_reg, &i8237_dev, "Illegal read of i8237_rC[devnum]\n");
return 0;
} else { /* clear byte pointer FF */
if (io == 0) { /* read current address CH 0 */
if (i8237_rD[devnum]) { /* high byte */
i8237_rD[devnum] = 0;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_rD[devnum] (FF) cleared\n");
return 0;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r0[devnum](H) read as %04X\n", i8237_r0[devnum]);
return (i8237_r0[devnum] >> 8);
} else { /* low byte */
i8237_rD[devnum]++;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r0[devnum](L) read as %04X\n", i8237_r0[devnum]);
return (i8237_r0[devnum] & 0xFF);
}
} else { /* write base & current address CH 0 */
if (i8237_rD[devnum]) { /* high byte */
i8237_rD[devnum] = 0;
i8237_r0[devnum] |= (data << 8);
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r0[devnum](H) set to %04X\n", i8237_r0[devnum]);
} else { /* low byte */
i8237_rD[devnum]++;
i8237_r0[devnum] = data & 0xFF;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r0[devnum](L) set to %04X\n", i8237_r0[devnum]);
}
}
return 0;
}
uint8 i8237_rDx(t_bool io, uint8 data)
uint8 i8237_r1x(t_bool io, uint8 data, uint8 devnum)
{
uint8 devnum;
if ((devnum = i8237_get_dn()) != 0xFF) {
if (io == 0) { /* read temporary register */
sim_debug (DEBUG_reg, &i8237_dev, "Illegal read of i8237_rD[devnum]\n");
return 0;
} else { /* master clear */
i8237_reset1();
sim_debug (DEBUG_reg, &i8237_dev, "i8237 master clear\n");
return 0;
if (io == 0) { /* read current word count CH 0 */
if (i8237_rD[devnum]) { /* high byte */
i8237_rD[devnum] = 0;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r1[devnum](H) read as %04X\n", i8237_r1[devnum]);
return (i8237_r1[devnum] >> 8);
} else { /* low byte */
i8237_rD[devnum]++;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r1[devnum](L) read as %04X\n", i8237_r1[devnum]);
return (i8237_r1[devnum] & 0xFF);
}
} else { /* write base & current address CH 0 */
if (i8237_rD[devnum]) { /* high byte */
i8237_rD[devnum] = 0;
i8237_r1[devnum] |= (data << 8);
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r1[devnum](H) set to %04X\n", i8237_r1[devnum]);
} else { /* low byte */
i8237_rD[devnum]++;
i8237_r1[devnum] = data & 0xFF;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r1[devnum](L) set to %04X\n", i8237_r1[devnum]);
}
}
return 0;
}
uint8 i8237_rEx(t_bool io, uint8 data)
uint8 i8237_r2x(t_bool io, uint8 data, uint8 devnum)
{
uint8 devnum;
if ((devnum = i8237_get_dn()) != 0xFF) {
if (io == 0) {
sim_debug (DEBUG_reg, &i8237_dev, "Illegal read of i8237_rE[devnum]\n");
return 0;
} else { /* clear mask register */
i8237_rB[devnum] = 0;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_rB[devnum] (mask) cleared\n");
return 0;
if (io == 0) { /* read current address CH 1 */
if (i8237_rD[devnum]) { /* high byte */
i8237_rD[devnum] = 0;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r2[devnum](H) read as %04X\n", i8237_r2[devnum]);
return (i8237_r2[devnum] >> 8);
} else { /* low byte */
i8237_rD[devnum]++;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r2[devnum](L) read as %04X\n", i8237_r2[devnum]);
return (i8237_r2[devnum] & 0xFF);
}
} else { /* write base & current address CH 1 */
if (i8237_rD[devnum]) { /* high byte */
i8237_rD[devnum] = 0;
i8237_r2[devnum] |= (data << 8);
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r2[devnum](H) set to %04X\n", i8237_r2[devnum]);
} else { /* low byte */
i8237_rD[devnum]++;
i8237_r2[devnum] = data & 0xFF;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r2[devnum](L) set to %04X\n", i8237_r2[devnum]);
}
}
return 0;
}
uint8 i8237_rFx(t_bool io, uint8 data)
uint8 i8237_r3x(t_bool io, uint8 data, uint8 devnum)
{
uint8 devnum;
if ((devnum = i8237_get_dn()) != 0xFF) {
if (io == 0) {
sim_debug (DEBUG_reg, &i8237_dev, "Illegal read of i8237_rF[devnum]\n");
return 0;
} else { /* write all mask register bits */
i8237_rB[devnum] = data & 0x0F;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_rB[devnum] (mask) set to %02X\n", i8237_rB[devnum]);
return 0;
if (io == 0) { /* read current word count CH 1 */
if (i8237_rD[devnum]) { /* high byte */
i8237_rD[devnum] = 0;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r3[devnum](H) read as %04X\n", i8237_r3[devnum]);
return (i8237_r3[devnum] >> 8);
} else { /* low byte */
i8237_rD[devnum]++;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r3[devnum](L) read as %04X\n", i8237_r3[devnum]);
return (i8237_r3[devnum] & 0xFF);
}
} else { /* write base & current address CH 1 */
if (i8237_rD[devnum]) { /* high byte */
i8237_rD[devnum] = 0;
i8237_r3[devnum] |= (data << 8);
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r3[devnum](H) set to %04X\n", i8237_r3[devnum]);
} else { /* low byte */
i8237_rD[devnum]++;
i8237_r3[devnum] = data & 0xFF;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r3[devnum](L) set to %04X\n", i8237_r3[devnum]);
}
}
return 0;
}
uint8 i8237_r4x(t_bool io, uint8 data, uint8 devnum)
{
if (io == 0) { /* read current address CH 2 */
if (i8237_rD[devnum]) { /* high byte */
i8237_rD[devnum] = 0;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r4[devnum](H) read as %04X\n", i8237_r4[devnum]);
return (i8237_r4[devnum] >> 8);
} else { /* low byte */
i8237_rD[devnum]++;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r4[devnum](L) read as %04X\n", i8237_r4[devnum]);
return (i8237_r4[devnum] & 0xFF);
}
} else { /* write base & current address CH 2 */
if (i8237_rD[devnum]) { /* high byte */
i8237_rD[devnum] = 0;
i8237_r4[devnum] |= (data << 8);
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r4[devnum](H) set to %04X\n", i8237_r4[devnum]);
} else { /* low byte */
i8237_rD[devnum]++;
i8237_r4[devnum] = data & 0xFF;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r4[devnum](L) set to %04X\n", i8237_r4[devnum]);
}
}
return 0;
}
uint8 i8237_r5x(t_bool io, uint8 data, uint8 devnum)
{
if (io == 0) { /* read current word count CH 2 */
if (i8237_rD[devnum]) { /* high byte */
i8237_rD[devnum] = 0;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r5[devnum](H) read as %04X\n", i8237_r5[devnum]);
return (i8237_r5[devnum] >> 8);
} else { /* low byte */
i8237_rD[devnum]++;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r5[devnum](L) read as %04X\n", i8237_r5[devnum]);
return (i8237_r5[devnum] & 0xFF);
}
} else { /* write base & current address CH 2 */
if (i8237_rD[devnum]) { /* high byte */
i8237_rD[devnum] = 0;
i8237_r5[devnum] |= (data << 8);
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r5[devnum](H) set to %04X\n", i8237_r5[devnum]);
} else { /* low byte */
i8237_rD[devnum]++;
i8237_r5[devnum] = data & 0xFF;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r5[devnum](L) set to %04X\n", i8237_r5[devnum]);
}
}
return 0;
}
uint8 i8237_r6x(t_bool io, uint8 data, uint8 devnum)
{
if (io == 0) { /* read current address CH 3 */
if (i8237_rD[devnum]) { /* high byte */
i8237_rD[devnum] = 0;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r6[devnum](H) read as %04X\n", i8237_r6[devnum]);
return (i8237_r6[devnum] >> 8);
} else { /* low byte */
i8237_rD[devnum]++;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r6[devnum](L) read as %04X\n", i8237_r6[devnum]);
return (i8237_r6[devnum] & 0xFF);
}
} else { /* write base & current address CH 3 */
if (i8237_rD[devnum]) { /* high byte */
i8237_rD[devnum] = 0;
i8237_r6[devnum] |= (data << 8);
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r6[devnum](H) set to %04X\n", i8237_r6[devnum]);
} else { /* low byte */
i8237_rD[devnum]++;
i8237_r6[devnum] = data & 0xFF;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r6[devnum](L) set to %04X\n", i8237_r6[devnum]);
}
}
return 0;
}
uint8 i8237_r7x(t_bool io, uint8 data, uint8 devnum)
{
if (io == 0) { /* read current word count CH 3 */
if (i8237_rD[devnum]) { /* high byte */
i8237_rD[devnum] = 0;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r7[devnum](H) read as %04X\n", i8237_r7[devnum]);
return (i8237_r7[devnum] >> 8);
} else { /* low byte */
i8237_rD[devnum]++;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r7[devnum](L) read as %04X\n", i8237_r7[devnum]);
return (i8237_r7[devnum] & 0xFF);
}
} else { /* write base & current address CH 3 */
if (i8237_rD[devnum]) { /* high byte */
i8237_rD[devnum] = 0;
i8237_r7[devnum] |= (data << 8);
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r7[devnum](H) set to %04X\n", i8237_r7[devnum]);
} else { /* low byte */
i8237_rD[devnum]++;
i8237_r7[devnum] = data & 0xFF;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r7[devnum](L) set to %04X\n", i8237_r7[devnum]);
}
}
return 0;
}
uint8 i8237_r8x(t_bool io, uint8 data, uint8 devnum)
{
if (io == 0) { /* read status register */
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r8[devnum] (status) read as %02X\n", i8237_r8[devnum]);
return (i8237_r8[devnum]);
} else { /* write command register */
i8237_r9[devnum] = data & 0xFF;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r9[devnum] (command) set to %02X\n", i8237_r9[devnum]);
}
return 0;
}
uint8 i8237_r9x(t_bool io, uint8 data, uint8 devnum)
{
if (io == 0) {
sim_debug (DEBUG_reg, &i8237_dev, "Illegal read of i8237_r9[devnum]\n");
return 0;
} else { /* write request register */
i8237_rC[devnum] = data & 0xFF;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_rC[devnum] (request) set to %02X\n", i8237_rC[devnum]);
}
return 0;
}
uint8 i8237_rAx(t_bool io, uint8 data, uint8 devnum)
{
if (io == 0) {
sim_debug (DEBUG_reg, &i8237_dev, "Illegal read of i8237_rA[devnum]\n");
return 0;
} else { /* write single mask register */
switch(data & 0x03) {
case 0:
if (data & 0x04)
i8237_rB[devnum] |= 1;
else
i8237_rB[devnum] &= ~1;
break;
case 1:
if (data & 0x04)
i8237_rB[devnum] |= 2;
else
i8237_rB[devnum] &= ~2;
break;
case 2:
if (data & 0x04)
i8237_rB[devnum] |= 4;
else
i8237_rB[devnum] &= ~4;
break;
case 3:
if (data & 0x04)
i8237_rB[devnum] |= 8;
else
i8237_rB[devnum] &= ~8;
break;
}
sim_debug (DEBUG_reg, &i8237_dev, "i8237_rB[devnum] (mask) set to %02X\n", i8237_rB[devnum]);
}
return 0;
}
uint8 i8237_rBx(t_bool io, uint8 data, uint8 devnum)
{
if (io == 0) {
sim_debug (DEBUG_reg, &i8237_dev, "Illegal read of i8237_rB[devnum]\n");
return 0;
} else { /* write mode register */
i8237_rA[devnum] = data & 0xFF;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_rA[devnum] (mode) set to %02X\n", i8237_rA[devnum]);
}
return 0;
}
uint8 i8237_rCx(t_bool io, uint8 data, uint8 devnum)
{
if (io == 0) {
sim_debug (DEBUG_reg, &i8237_dev, "Illegal read of i8237_rC[devnum]\n");
return 0;
} else { /* clear byte pointer FF */
i8237_rD[devnum] = 0;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_rD[devnum] (FF) cleared\n");
}
return 0;
}
uint8 i8237_rDx(t_bool io, uint8 data, uint8 devnum)
{
if (io == 0) { /* read temporary register */
sim_debug (DEBUG_reg, &i8237_dev, "Illegal read of i8237_rD[devnum]\n");
return 0;
} else { /* master clear */
i8237_reset_dev(devnum);
sim_debug (DEBUG_reg, &i8237_dev, "i8237 master clear\n");
}
return 0;
}
uint8 i8237_rEx(t_bool io, uint8 data, uint8 devnum)
{
if (io == 0) {
sim_debug (DEBUG_reg, &i8237_dev, "Illegal read of i8237_rE[devnum]\n");
return 0;
} else { /* clear mask register */
i8237_rB[devnum] = 0;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_rB[devnum] (mask) cleared\n");
}
return 0;
}
uint8 i8237_rFx(t_bool io, uint8 data, uint8 devnum)
{
if (io == 0) {
sim_debug (DEBUG_reg, &i8237_dev, "Illegal read of i8237_rF[devnum]\n");
return 0;
} else { /* write all mask register bits */
i8237_rB[devnum] = data & 0x0F;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_rB[devnum] (mask) set to %02X\n", i8237_rB[devnum]);
}
return 0;
}

4
Intel-Systems/common/ieprom.c
View file

@ -135,14 +135,16 @@ uint8 EPROM_get_mbyte(uint16 addr)
{
uint8 val;
if ((addr >= EPROM_unit.u3) && ((uint32) addr <= (EPROM_unit.u3 + EPROM_unit.capac))) {
if ((addr >= EPROM_unit.u3) && ((uint16) addr <= (EPROM_unit.u3 + EPROM_unit.capac))) {
SET_XACK(1); /* good memory address */
val = *((uint8 *)EPROM_unit.filebuf + (addr - EPROM_unit.u3));
val &= 0xFF;
return val;
} else {
SET_XACK(0); /* bad memory address */
sim_printf("EPROM: Out of range\n");
}
SET_XACK(0); /* bad memory address */
return 0;
}

2
Intel-Systems/common/ieprom1.c
View file

@ -136,7 +136,7 @@ uint8 EPROM1_get_mbyte(uint16 addr)
{
uint8 val;
if ((addr >= EPROM1_unit->u3) && ((uint32) addr <= (EPROM1_unit->u3 + EPROM1_unit->capac))) {
if ((addr >= EPROM1_unit->u3) && ((uint16) addr <= (EPROM1_unit->u3 + EPROM1_unit->capac))) {
SET_XACK(1); /* good memory address */
val = *((uint8 *)EPROM1_unit->filebuf + (addr - EPROM1_unit->u3));
val &= 0xFF;

2
Intel-Systems/common/ipb.c
View file

@ -92,7 +92,7 @@ t_stat SBC_config(void)
i8255_cfg(I8255_BASE_0, 0);
i8255_cfg(I8255_BASE_1, 1);
i8259_cfg(I8259_BASE_0, 0);
i8259_cfg(I8259_BASE_1, 0);
i8259_cfg(I8259_BASE_1, 1);
ipc_cont_cfg(ICONT_BASE, 0);
ioc_cont_cfg(DBB_BASE, 0);
EPROM_cfg(ROM_BASE, ROM_SIZE);

2
Intel-Systems/common/ipc.c
View file

@ -94,7 +94,7 @@ t_stat SBC_config(void)
i8255_cfg(I8255_BASE_0, 0);
i8255_cfg(I8255_BASE_1, 1);
i8259_cfg(I8259_BASE_0, 0);
i8259_cfg(I8259_BASE_1, 0);
i8259_cfg(I8259_BASE_1, 1);
ipc_cont_cfg(ICONT_BASE, 0);
ioc_cont_cfg(DBB_BASE, 0);
EPROM_cfg(ROM_BASE, ROM_SIZE);

6
Intel-Systems/common/iram8.c
View file

@ -118,11 +118,12 @@ uint8 RAM_get_mbyte(uint16 addr)
{
uint8 val;
if ((addr >= RAM_unit.u3) && ((uint32) addr < (RAM_unit.u3 + RAM_unit.capac))) {
if ((addr >= RAM_unit.u3) && ((uint32) addr <= (RAM_unit.u3 + RAM_unit.capac))) {
SET_XACK(1); /* good memory address */
val = *((uint8 *)RAM_unit.filebuf + (addr - RAM_unit.u3));
return (val & 0xFF);
} else {
SET_XACK(0); /* bad memory address */
return 0xFF;
}
}
@ -131,11 +132,12 @@ uint8 RAM_get_mbyte(uint16 addr)
void RAM_put_mbyte(uint16 addr, uint8 val)
{
if ((addr >= RAM_unit.u3) && ((uint32)addr < RAM_unit.u3 + RAM_unit.capac)) {
if ((addr >= RAM_unit.u3) && ((uint32)addr <= RAM_unit.u3 + RAM_unit.capac)) {
SET_XACK(1); /* good memory address */
*((uint8 *)RAM_unit.filebuf + (addr - RAM_unit.u3)) = val & 0xFF;
return;
} else {
SET_XACK(0); /* bad memory address */
return;
}

6
Intel-Systems/common/isbc064.c
View file

@ -159,10 +159,12 @@ uint8 isbc064_get_mbyte(uint16 addr)
return (val & 0xFF);
} else {
sim_printf("isbc064_get_mbyte: Read-Enabled Out of range addr=%04X PC=%04X\n", addr, PCX);
SET_XACK(0); /* bad memory address */
return 0xff; /* multibus has active high pullups and inversion */
}
} //device is disabled/not installed
sim_printf ("isbc064_get_mbyte: Read-Disabled addr=%04X PC=%04X\n", addr, PCX);
SET_XACK(0); /* bad memory address */
return 0xff; /* multibus has active high pullups and inversion */
}
@ -171,16 +173,18 @@ uint8 isbc064_get_mbyte(uint16 addr)
void isbc064_put_mbyte(uint16 addr, uint8 val)
{
if ((isbc064_dev.flags & DEV_DIS) == 0) { //device is enabled
if ((addr >= isbc064_unit.u3) && (addr < (isbc064_unit.u3 + isbc064_unit.capac))) {
if ((addr >= isbc064_unit.u3) && (addr <= (isbc064_unit.u3 + isbc064_unit.capac))) {
SET_XACK(1); /* good memory address */
*((uint8 *)isbc064_unit.filebuf + (addr - isbc064_unit.u3)) = val & 0xFF;
return;
} else {
sim_printf("isbc064_put_mbyte: Write Out of range addr=%04X PC=%04X\n", addr, PCX);
SET_XACK(0); /* bad memory address */
return;
}
} //device is disabled/not installed
sim_printf ("isbc064_put_mbyte: Write-Disabled addr=%04X PC=%04X\n", addr, PCX);
SET_XACK(0); /* bad memory address */
}
/* end of isbc064.c */

9
Intel-Systems/common/isbc202.c
View file

@ -421,13 +421,8 @@ uint8 isbc202r1(t_bool io, uint8 data, uint8 devnum)
if (io == 0) { /* read data port */
fdc202.intff = 0; //clear interrupt FF
fdc202.stat &= ~FDCINT;
if (fdc202.rdychg) {
fdc202.rtype = ROK;
return fdc202.rtype;
} else {
fdc202.rtype = ROK;
return fdc202.rtype;
}
fdc202.rtype = ROK;
return fdc202.rtype;
} else { /* write data port */
fdc202.iopb = data;
}

9
Intel-Systems/common/isbc206.c
View file

@ -395,13 +395,8 @@ uint8 isbc206r1(t_bool io, uint8 data, uint8 devnum)
if (io == 0) { /* read data port */
hdc206.intff = 0; //clear interrupt FF
hdc206.stat &= ~(HDCINT + 0x80);
if (hdc206.rdychg) {
hdc206.rtype = ROK;
return hdc206.rtype;
} else {
hdc206.rtype = ROK;
return hdc206.rtype;
}
hdc206.rtype = ROK;
return hdc206.rtype;
} else { /* write data port */
hdc206.iopb = data;
}

6
Intel-Systems/common/isbc208.c
View file

@ -840,7 +840,7 @@ t_stat isbc208_svc (UNIT *uptr)
} else { // get image addr for this d, h, c, s
if (fddst[uptr->u6] & TS)
imgadr = (cyl * bpc) /*+ (h * bpt)*/ + ((sec - 1) * ssize);
else
else {
imgadr = (cyl * bpt) + ((sec - 1) * ssize);
for (i=0; i<=i8237_r1; i++) { /* copy selected sector to memory */
data = *(fbuf + (imgadr + i));
@ -860,6 +860,7 @@ t_stat isbc208_svc (UNIT *uptr)
if (h) { // on head one?
i8272_w2++; // yes, step cylinder
h = 0; // back to head 0
}
}
}
i8272_w5 = secn;
@ -893,7 +894,7 @@ t_stat isbc208_svc (UNIT *uptr)
} else { // get image addr for this d, h, c, s
if (fddst[uptr->u6] == TS)
imgadr = (cyl * bpc) /*+ (h * bpt)*/ + ((sec - 1) * ssize);
else
else {
imgadr = (cyl * bpt) + ((sec - 1) * ssize);
for (i=0; i<=i8237_r1; i++) { /* copy selected memory to image */
data = multibus_get_mbyte(i8237_r0 + i);
@ -909,6 +910,7 @@ t_stat isbc208_svc (UNIT *uptr)
fclose(fp);
*/
//*** need to step return results IAW table 3-11 in 143078-001
}
i8272_w2 = cyl; /* generate a current address mark */
i8272_w3 = hed >> 2;
i8272_w4 = ++sec; /* next sector */

8
Intel-Systems/common/isbc464.c
View file

@ -33,8 +33,6 @@
#include "system_defs.h"
#define SET_XACK(VAL) (xack = VAL)
/* prototypes */
t_stat isbc064_cfg(uint16 base, uint16 size);
@ -144,10 +142,12 @@ uint8 isbc464_get_mbyte(uint16 addr)
return (val & 0xFF);
} else {
sim_printf("isbc464_get_mbyte: Out of range\n");
SET_XACK(0); /* bad memory address */
return 0; /* multibus has active high pullups and inversion */
}
}
sim_printf ("isbc464_put_mbyte: Write-Disabled addr=%04X\n", addr);
SET_XACK(0); /* bad memory address */
return 0; /* multibus has active high pullups and inversion */
}
@ -161,15 +161,17 @@ void isbc464_put_mbyte(uint16 addr, uint8 val)
org = isbc464_unit.u3;
len = isbc464_unit.capac;
if ((addr >= org) && (addr < (org + len))) {
// SET_XACK(1); /* good memory address */
SET_XACK(0); /* bad memory address */
sim_printf ("isbc464_put_mbyte: Read-only Memory\n");
return;
} else {
sim_printf ("isbc464_put_mbyte: Out of range\n");
SET_XACK(0); /* bad memory address */
return;
}
}
sim_printf ("isbc464_put_mbyte: Disabled\n");
SET_XACK(0); /* bad memory address */
}
/* end of isbc464.c */

2
Intel-Systems/common/multibus.c
View file

@ -334,7 +334,7 @@ void multibus_put_mbyte(uint16 addr, uint8 val)
{
SET_XACK(0); /* set no XACK */
if ((isbc064_dev.flags & DEV_DIS) == 0) { //device is enabled
if (addr >= SBC064_BASE && addr <= (SBC064_BASE + SBC064_SIZE - 1))
if ((addr >= SBC064_BASE) && (addr <= (SBC064_BASE + SBC064_SIZE - 1)))
isbc064_put_mbyte(addr, val);
} else {
return;

9
Intel-Systems/common/zx200a.c
View file

@ -491,13 +491,8 @@ uint8 zx200ar1SD(t_bool io, uint8 data, uint8 devnum)
zx200a.intff = 0; //clear interrupt FF
if (zx200a.intff)
zx200a.SDstat &= ~FDCINT;
if (zx200a.rdychg) {
zx200a.rtype = ROK;
return zx200a.rtype;
} else {
zx200a.rtype = ROK;
return zx200a.rtype;
}
zx200a.rtype = ROK;
return zx200a.rtype;
} else { /* write control port */
zx200a.iopb = data;
}

18
Intel-Systems/ibmpc/ibmpc.c
View file

@ -64,13 +64,13 @@ extern void RAM_put_mbyte(uint32 addr, uint8 val);
extern UNIT i8255_unit[];
extern UNIT EPROM_unit;
extern UNIT RAM_unit;
extern t_stat i8237_reset (DEVICE *dptr, uint16 base);
extern t_stat i8253_reset (DEVICE *dptr, uint16 base);
extern t_stat i8255_reset (DEVICE *dptr, uint16 base);
extern t_stat i8259_reset (DEVICE *dptr, uint16 base);
extern t_stat EPROM_reset (DEVICE *dptr, uint32 base, uint32 size);
extern t_stat RAM_reset (DEVICE *dptr, uint32 base, uint32 size);
extern uint16 reg_dev(uint8 (*routine)(t_bool, uint8), uint16);
extern t_stat i8237_reset (DEVICE *dptr);
extern t_stat i8253_reset (DEVICE *dptr);
extern t_stat i8255_reset (DEVICE *dptr);
extern t_stat i8259_reset (DEVICE *dptr);
extern t_stat EPROM_reset (DEVICE *dptr);
extern t_stat RAM_reset (DEVICE *dptr);
extern uint16 reg_dev(uint8 (*routine)(t_bool, uint8, uint8), uint16, uint8);
/* SBC reset routine */
@ -158,12 +158,12 @@ uint8 enbnmi(t_bool io, uint8 data)
uint8 get_mbyte(uint32 addr)
{
/* if local EPROM handle it */
if ((addr >= (uint32)EPROM_unit.u3) && (addr < (uint32)(EPROM_unit.u3 + EPROM_unit.capac))) {
if ((addr >= (uint32)EPROM_unit.u3) && (addr <= (uint32)(EPROM_unit.u3 + EPROM_unit.capac))) {
// sim_printf("Write to R/O memory address %05X - ignored\n", addr);
return EPROM_get_mbyte(addr);
}
/* if local RAM handle it */
if ((addr >= (uint32)RAM_unit.u3) && (addr < (uint32)(RAM_unit.u3 + RAM_unit.capac))) {
if ((addr >= (uint32)RAM_unit.u3) && (addr <= (uint32)(RAM_unit.u3 + RAM_unit.capac))) {
return RAM_get_mbyte(addr);
}
/* otherwise, try the pcbus */

4
Intel-Systems/ibmpc/system_defs.h
View file

@ -59,11 +59,11 @@
/* set the base and size for the EPROM on the IBM PC */
#define ROM_BASE 0xFE000
#define ROM_SIZE 0x02000
#define ROM_SIZE 0x01FFF
/* set the base and size for the RAM on the IBM PC */
#define RAM_BASE 0x00000
#define RAM_SIZE 0x40000
#define RAM_SIZE 0x3FFFF
/* set INTR for CPU on the 8088 */
#define INT_R INT_1

6
Intel-Systems/imds-210/system_defs.h
View file

@ -127,10 +127,10 @@
/* Memory */
#define MAXMEMSIZE 0x10000 /* 8080 max memory size */
#define MAXMEMSIZE 0x0FFFF /* 8080 max memory size */
#define MEMSIZE (i8080_unit.capac) /* 8080 actual memory size */
#define ADDRMASK (MAXMEMSIZE - 1) /* 8080 address mask */
#define MEM_ADDR_OK(x) (((uint32) (x)) < MEMSIZE)
#define ADDRMASK (MAXMEMSIZE) /* 8080 address mask */
#define MEM_ADDR_OK(x) (((uint16) (x)) <= MEMSIZE)
/* debug definitions */

6
Intel-Systems/imds-220/system_defs.h
View file

@ -127,10 +127,10 @@
/* Memory */
#define MAXMEMSIZE 0x10000 /* 8080 max memory size */
#define MAXMEMSIZE 0x0FFFF /* 8080 max memory size */
#define MEMSIZE (i8080_unit.capac) /* 8080 actual memory size */
#define ADDRMASK (MAXMEMSIZE - 1) /* 8080 address mask */
#define MEM_ADDR_OK(x) (((uint32) (x)) < MEMSIZE)
#define ADDRMASK (MAXMEMSIZE) /* 8080 address mask */
#define MEM_ADDR_OK(x) (((uint16) (x)) <= MEMSIZE)
/* debug definitions */

8
Intel-Systems/imds-225/system_defs.h
View file

@ -101,7 +101,7 @@
/* set the base and size for the iSBC 464 ROM */
#define SBC464_BASE 0xA800
#define SBC464_SIZE 0x4800
#define SBC464_SIZE 0x47FF
#define SBC464_NUM 0
/* set INTR for CPU */
@ -127,10 +127,10 @@
/* Memory */
#define MAXMEMSIZE 0x10000 /* 8080 max memory size */
#define MAXMEMSIZE 0x0FFFF /* 8080 max memory size */
#define MEMSIZE (i8080_unit.capac) /* 8080 actual memory size */
#define ADDRMASK (MAXMEMSIZE - 1) /* 8080 address mask */
#define MEM_ADDR_OK(x) (((uint32) (x)) < MEMSIZE)
#define ADDRMASK (MAXMEMSIZE) /* 8080 address mask */
#define MEM_ADDR_OK(x) (((uint16) (x)) <= MEMSIZE)
/* debug definitions */

12
Intel-Systems/imds-230/system_defs.h
View file

@ -71,7 +71,7 @@
/* set the base I/O address for the iSBC 201 */
#define SBC201_BASE 0x78
#define SBC201_INT INT_2
#define SBC201_NUM 1
#define SBC201_NUM 0
/* set the base I/O address for the iSBC 202 */
#define SBC202_BASE 0x78
@ -91,11 +91,11 @@
/* set the base for the zx-200a disk controller */
#define ZX200A_BASE 0x78
#define ZX200A_INT INT_2
#define ZX200A_NUM 1
#define ZX200A_NUM 0
/* set the base and size for the iSBC 464 ROM */
#define SBC464_BASE 0xA800
#define SBC464_SIZE 0x4800
#define SBC464_SIZE 0x47FF
#define SBC464_NUM 0
/* set the base and size for the iSBC 064 RAM */
@ -126,10 +126,10 @@
/* Memory */
#define MAXMEMSIZE 0x10000 /* 8080 max memory size */
#define MAXMEMSIZE 0x0FFFF /* 8080 max memory size */
#define MEMSIZE (i8080_unit.capac) /* 8080 actual memory size */
#define ADDRMASK (MAXMEMSIZE - 1) /* 8080 address mask */
#define MEM_ADDR_OK(x) (((uint32) (x)) < MEMSIZE)
#define ADDRMASK (MAXMEMSIZE) /* 8080 address mask */
#define MEM_ADDR_OK(x) (((uint16) (x)) <= MEMSIZE)
/* debug definitions */

6
Intel-Systems/imds-800/cpu.c
View file

@ -104,13 +104,13 @@ uint8 get_mbyte(uint16 addr)
{
uint8 val;
if (((monitor_boot & 0x04) == 0) && (addr >= ROM0_BASE && addr <= ROM0_BASE + ROM0_SIZE))
if (((monitor_boot & 0x04) == 0) && (addr >= ROM0_BASE) && (addr <= (ROM0_BASE + ROM0_SIZE)))
val = EPROM_get_mbyte(addr);
else if (ROM1_SIZE && addr >= ROM1_BASE && addr <= ROM1_BASE + ROM1_SIZE)
else if (ROM1_SIZE && (addr >= ROM1_BASE) && (addr <= (ROM1_BASE + ROM1_SIZE)))
val = EPROM1_get_mbyte(addr);
else val = multibus_get_mbyte(addr);
val &= 0xFF;
return(val);
return val;
}
/* get a word from memory */

6
Intel-Systems/imds-800/system_defs.h
View file

@ -110,10 +110,10 @@
/* Memory */
#define MAXMEMSIZE 0x10000 /* 8080 max memory size */
#define MAXMEMSIZE 0x0FFFF /* 8080 max memory size */
#define MEMSIZE (i8080_unit.capac) /* 8080 actual memory size */
#define ADDRMASK (MAXMEMSIZE - 1) /* 8080 address mask */
#define MEM_ADDR_OK(x) (((uint32) (x)) < MEMSIZE)
#define ADDRMASK (MAXMEMSIZE) /* 8080 address mask */
#define MEM_ADDR_OK(x) (((uint16) (x)) <= MEMSIZE)
/* debug definitions */

6
Intel-Systems/imds-810/system_defs.h
View file

@ -110,10 +110,10 @@
/* Memory */
#define MAXMEMSIZE 0x10000 /* 8080 max memory size */
#define MAXMEMSIZE 0x0FFFF /* 8080 max memory size */
#define MEMSIZE (i8080_unit.capac) /* 8080 actual memory size */
#define ADDRMASK (MAXMEMSIZE - 1) /* 8080 address mask */
#define MEM_ADDR_OK(x) (((uint32) (x)) < MEMSIZE)
#define ADDRMASK (MAXMEMSIZE) /* 8080 address mask */
#define MEM_ADDR_OK(x) (((uint16) (x)) <= MEMSIZE)
/* debug definitions */

8
Intel-Systems/isys8010/system_defs.h
View file

@ -90,7 +90,7 @@
/* set the base and size for the iSBC 464 ROM */
#define SBC464_BASE 0xA800
#define SBC464_SIZE 0x4800
#define SBC464_SIZE 0x47FF
#define SBC464_NUM 0
/* multibus interrupt definitions */
@ -113,10 +113,10 @@
/* Memory */
#define MAXMEMSIZE 0x10000 /* 8080 max memory size */
#define MAXMEMSIZE 0x0FFFF /* 8080 max memory size */
#define MEMSIZE (i8080_unit.capac) /* 8080 actual memory size */
#define ADDRMASK (MAXMEMSIZE - 1) /* 8080 address mask */
#define MEM_ADDR_OK(x) (((uint32) (x)) < MEMSIZE)
#define ADDRMASK (MAXMEMSIZE) /* 8080 address mask */
#define MEM_ADDR_OK(x) (((uint16) (x)) <= MEMSIZE)
/* debug definitions */

8
Intel-Systems/isys8020/system_defs.h
View file

@ -97,7 +97,7 @@
/* set the base and size for the iSBC 464 ROM */
#define SBC464_BASE 0xA800
#define SBC464_SIZE 0x4800
#define SBC464_SIZE 0x47FF
#define SBC464_NUM 0
/* multibus interrupt definitions */
@ -120,10 +120,10 @@
/* Memory */
#define MAXMEMSIZE 0x10000 /* 8080 max memory size */
#define MAXMEMSIZE 0x0FFFF /* 8080 max memory size */
#define MEMSIZE (i8080_unit.capac) /* 8080 actual memory size */
#define ADDRMASK (MAXMEMSIZE - 1) /* 8080 address mask */
#define MEM_ADDR_OK(x) (((uint32) (x)) < MEMSIZE)
#define ADDRMASK (MAXMEMSIZE) /* 8080 address mask */
#define MEM_ADDR_OK(x) (((uint16) (x)) <= MEMSIZE)
/* debug definitions */

10
Intel-Systems/isys8024/system_defs.h
View file

@ -105,7 +105,7 @@
/* set the base and size for the iSBC 464 ROM */
#define SBC464_BASE 0xA800
#define SBC464_SIZE 0x4800
#define SBC464_SIZE 0x47FF
#define SBC464_NUM 0
/* multibus interrupt definitions */
@ -128,10 +128,10 @@
/* Memory */
#define MAXMEMSIZE 0x10000 /* 8080 max memory size */
#define MEMSIZE (i8080_unit.capac) /* 8080 actual memory size */
#define ADDRMASK (MAXMEMSIZE - 1) /* 8080 address mask */
#define MEM_ADDR_OK(x) (((uint32) (x)) < MEMSIZE)
#define MAXMEMSIZE 0x0FFFF /* 8080 max memory size */
#define MEMSIZE (i8080_unit.capac) /* 8080 actual memory size */
#define ADDRMASK (MAXMEMSIZE) /* 8080 address mask */
#define MEM_ADDR_OK(x) (((uint16) (x)) <= MEMSIZE)
/* debug definitions */

8
Intel-Systems/isys8030/system_defs.h
View file

@ -100,7 +100,7 @@
/* set the base and size for the iSBC 464 ROM */
#define SBC464_BASE 0xA800
#define SBC464_SIZE 0x4800
#define SBC464_SIZE 0x47FF
#define SBC464_NUM 0
/* multibus interrupt definitions */
@ -123,10 +123,10 @@
/* Memory */
#define MAXMEMSIZE 0x10000 /* 8080 max memory size */
#define MAXMEMSIZE 0x0FFFF /* 8080 max memory size */
#define MEMSIZE (i8080_unit.capac) /* 8080 actual memory size */
#define ADDRMASK (MAXMEMSIZE - 1) /* 8080 address mask */
#define MEM_ADDR_OK(x) (((uint32) (x)) < MEMSIZE)
#define ADDRMASK (MAXMEMSIZE) /* 8080 address mask */
#define MEM_ADDR_OK(x) (((uint16) (x)) <= MEMSIZE)
/* debug definitions */