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SDS: Do not reload channel interlace register if already alerted

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From actual monitor code, sequence used to read drum:
             EOD*  10000B   Alert Interlace
GDAC3: EOD    14202    I/O control mode EOD (mode 1)
                                        A=0  High order memory address bits
                                        Hicount=2 (Word count=04000=2KW)
             POT      GDBCL+2  Low-order memory address bits.
             RRF                    (EOD 2226) Read RAD file (mode 0)

Problem is that RRF is clearing the interlace information saved by the previous POT and sets up for a new POT. That is, in sds_io.c, mod 0 of op_eomd always assumes that a POT will follow if the channel is C or greater. Have to add tests of chan_flag.  If interlace is active, do not capture new information from this EOM/EOD.

Also removed superfluous trailing blanks from lines in file.
This commit is contained in:
Mark Emmer 2014-03-02 22:24:28 -06:00
parent d5acbc6f7a
commit 5b479c7ab2
1 changed files with 22 additions and 15 deletions
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37
SDS/sds_io.c
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@ -148,7 +148,7 @@ extern void set_dyn_map (void);
Channels could, optionally, handle 12b or 24b characters. The simulator can
support all widths.
*/
t_stat chan_show_reg (FILE *st, UNIT *uptr, int32 val, void *desc);
struct aldisp {
@ -233,11 +233,11 @@ t_stat (*dev3_dsp[64])() = { NULL };
struct aldisp dev_alt[] = {
{ NULL, NULL },
{ NULL, &pot_ilc }, { NULL, &pot_ilc },
{ NULL, &pot_ilc }, { NULL, &pot_ilc },
{ NULL, &pot_ilc }, { NULL, &pot_ilc },
{ NULL, &pot_ilc }, { NULL, &pot_ilc },
{ NULL, &pot_ilc }, { NULL, &pot_ilc },
{ NULL, &pot_ilc }, { NULL, &pot_ilc },
{ NULL, &pot_dcr }, { NULL, &pot_dcr },
{ NULL, &pot_dcr }, { NULL, &pot_dcr },
{ NULL, &pot_dcr }, { NULL, &pot_dcr },
{ NULL, &pot_dcr }, { NULL, &pot_dcr },
{ NULL, &pot_dcr }, { NULL, &pot_dcr },
{ &pin_adr, NULL }, { &pin_adr, NULL },
@ -330,15 +330,22 @@ switch (mod) {
if (INV_DEV (dev, ch)) /* inv dev? err */
CRETDEV;
chan_war[ch] = chan_cnt[ch] = 0; /* init chan */
chan_flag[ch] = chan_dcr[ch] = 0;
chan_mode[ch] = chan_uar[ch] = 0;
if (ch >= CHAN_E)
chan_mode[ch] = CHM_CE;
chan_dcr[ch] = 0;
chan_uar[ch] = 0;
if (!(chan_flag[ch] & CHF_ILCE) && /* ignore if ilc */
!QAILCE (alert)) { /* already alerted */
chan_flag[ch] = chan_mode[ch] = 0;
if (ch >= CHAN_E)
chan_mode[ch] = CHM_CE;
}
if ((r = dev_dsp[dev][ch] (IO_CONN, inst, NULL)))/* connect */
return r;
if ((inst & I_IND) || (ch >= CHAN_C)) { /* C-H? alert ilc */
alert = POT_ILCY + ch;
chan_mar[ch] = chan_wcr[ch] = 0;
if (!(chan_flag[ch] & CHF_ILCE) && /* ignore if ilc */
!QAILCE (alert)) { /* already alerted */
if ((inst & I_IND) || (ch >= CHAN_C)) { /* C-H? alert ilc */
alert = POT_ILCY + ch;
chan_mar[ch] = chan_wcr[ch] = 0;
}
}
if (chan_flag[ch] & CHF_24B) /* 24B? 1 ch/wd */
chan_cpw[ch] = 0;
@ -390,7 +397,7 @@ switch (mod) {
} /* end else change scan */
} /* end else term output */
} /* end else chan EOM */
break;
break;
case 2: /* internal */
if (ch >= CHAN_E) { /* EOD? */
@ -494,7 +501,7 @@ switch (mod) {
case 3: /* special */
dev = I_GETDEV3 (inst); /* special device */
if (dev3_dsp[dev])
dev3_dsp[dev] (IO_SKS, inst, dat);
dev3_dsp[dev] (IO_SKS, inst, dat);
else CRETINS;
} /* end case */
@ -568,7 +575,7 @@ return SCPE_OK;
Note that the channel can be disconnected if CHN_EOR is set, but must
not be if XFR_REQ is set */
t_stat chan_read (int32 ch)
{
uint32 dat = 0;
@ -626,7 +633,7 @@ if (TST_EOR (ch)) { /* end record? */
} /* end else if cnt */
return chan_eor (ch); /* eot/eor int */
}
return r;
return r;
}
void chan_write_mem (int32 ch)