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SDS: Do not reload channel interlace register if already alerted

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From actual monitor code, sequence used to read drum:
             EOD*  10000B   Alert Interlace
GDAC3: EOD    14202    I/O control mode EOD (mode 1)
                                        A=0  High order memory address bits
                                        Hicount=2 (Word count=04000=2KW)
             POT      GDBCL+2  Low-order memory address bits.
             RRF                    (EOD 2226) Read RAD file (mode 0)

Problem is that RRF is clearing the interlace information saved by the previous POT and sets up for a new POT. That is, in sds_io.c, mod 0 of op_eomd always assumes that a POT will follow if the channel is C or greater. Have to add tests of chan_flag.  If interlace is active, do not capture new information from this EOM/EOD.

Also removed superfluous trailing blanks from lines in file.
This commit is contained in:
Mark Emmer 2014-03-02 22:24:28 -06:00
parent d5acbc6f7a
commit 5b479c7ab2
1 changed files with 22 additions and 15 deletions
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21
SDS/sds_io.c
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@ -330,15 +330,22 @@ switch (mod) {
if (INV_DEV (dev, ch)) /* inv dev? err */
CRETDEV;
chan_war[ch] = chan_cnt[ch] = 0; /* init chan */
chan_flag[ch] = chan_dcr[ch] = 0;
chan_mode[ch] = chan_uar[ch] = 0;
if (ch >= CHAN_E)
chan_mode[ch] = CHM_CE;
chan_dcr[ch] = 0;
chan_uar[ch] = 0;
if (!(chan_flag[ch] & CHF_ILCE) && /* ignore if ilc */
!QAILCE (alert)) { /* already alerted */
chan_flag[ch] = chan_mode[ch] = 0;
if (ch >= CHAN_E)
chan_mode[ch] = CHM_CE;
}
if ((r = dev_dsp[dev][ch] (IO_CONN, inst, NULL)))/* connect */
return r;
if ((inst & I_IND) || (ch >= CHAN_C)) { /* C-H? alert ilc */
alert = POT_ILCY + ch;
chan_mar[ch] = chan_wcr[ch] = 0;
if (!(chan_flag[ch] & CHF_ILCE) && /* ignore if ilc */
!QAILCE (alert)) { /* already alerted */
if ((inst & I_IND) || (ch >= CHAN_C)) { /* C-H? alert ilc */
alert = POT_ILCY + ch;
chan_mar[ch] = chan_wcr[ch] = 0;
}
}
if (chan_flag[ch] & CHF_24B) /* 24B? 1 ch/wd */
chan_cpw[ch] = 0;