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VAX730, VAX750, VAX780, VAX8600: Fix interval timer ics value

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- When the running timer is explicitly stopped the ics value needs to be
    determined before canceling the active unit.
This commit is contained in:
Mark Pizzolato 2017-01-18 23:57:14 -08:00
parent e36873f466
commit 5cd0ea4d59
4 changed files with 6 additions and 6 deletions
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2
VAX/vax730_stddev.c
View file

@ -654,11 +654,11 @@ void iccs_wr (int32 val)
{ {
sim_debug_bits_hdr (TMR_DB_REG, &tmr_dev, "iccs_wr()", tmr_iccs_bits, tmr_iccs, val, TRUE); sim_debug_bits_hdr (TMR_DB_REG, &tmr_dev, "iccs_wr()", tmr_iccs_bits, tmr_iccs, val, TRUE);
if ((val & TMR_CSR_RUN) == 0) { /* clearing run? */ if ((val & TMR_CSR_RUN) == 0) { /* clearing run? */
sim_cancel (&tmr_unit); /* cancel timer */
if (tmr_iccs & TMR_CSR_RUN) { /* run 1 -> 0? */ if (tmr_iccs & TMR_CSR_RUN) { /* run 1 -> 0? */
tmr_icr = icr_rd (); /* update itr */ tmr_icr = icr_rd (); /* update itr */
sim_rtcn_calb (0, TMR_CLK); /* stop timer */ sim_rtcn_calb (0, TMR_CLK); /* stop timer */
} }
sim_cancel (&tmr_unit); /* cancel timer */
} }
if (val & CSR_DONE) /* Interrupt Acked? */ if (val & CSR_DONE) /* Interrupt Acked? */
sim_rtcn_tick_ack (20, TMR_CLK); /* Let timers know */ sim_rtcn_tick_ack (20, TMR_CLK); /* Let timers know */

4
VAX/vax750_stddev.c
View file

@ -642,7 +642,7 @@ return "console terminal output";
int32 iccs_rd (void) int32 iccs_rd (void)
{ {
sim_debug (TMR_DB_REG, &tmr_dev, "iccs_rd() = 0x%08X\n", tmr_iccs & TMR_CSR_RD); sim_debug_bits_hdr (TMR_DB_REG, &tmr_dev, "iccs_rd()", tmr_iccs_bits, tmr_iccs, tmr_iccs, TRUE);
return tmr_iccs & TMR_CSR_RD; return tmr_iccs & TMR_CSR_RD;
} }
@ -650,11 +650,11 @@ void iccs_wr (int32 val)
{ {
sim_debug_bits_hdr (TMR_DB_REG, &tmr_dev, "iccs_wr()", tmr_iccs_bits, tmr_iccs, val, TRUE); sim_debug_bits_hdr (TMR_DB_REG, &tmr_dev, "iccs_wr()", tmr_iccs_bits, tmr_iccs, val, TRUE);
if ((val & TMR_CSR_RUN) == 0) { /* clearing run? */ if ((val & TMR_CSR_RUN) == 0) { /* clearing run? */
sim_cancel (&tmr_unit); /* cancel timer */
if (tmr_iccs & TMR_CSR_RUN) { /* run 1 -> 0? */ if (tmr_iccs & TMR_CSR_RUN) { /* run 1 -> 0? */
tmr_icr = icr_rd (); /* update itr */ tmr_icr = icr_rd (); /* update itr */
sim_rtcn_calb (0, TMR_CLK); /* stop timer */ sim_rtcn_calb (0, TMR_CLK); /* stop timer */
} }
sim_cancel (&tmr_unit); /* cancel timer */
} }
if (val & CSR_DONE) /* Interrupt Acked? */ if (val & CSR_DONE) /* Interrupt Acked? */
sim_rtcn_tick_ack (20, TMR_CLK); /* Let timers know */ sim_rtcn_tick_ack (20, TMR_CLK); /* Let timers know */

4
VAX/vax780_stddev.c
View file

@ -620,11 +620,11 @@ void iccs_wr (int32 val)
{ {
sim_debug_bits_hdr (TMR_DB_REG, &tmr_dev, "iccs_wr()", tmr_iccs_bits, tmr_iccs, val, TRUE); sim_debug_bits_hdr (TMR_DB_REG, &tmr_dev, "iccs_wr()", tmr_iccs_bits, tmr_iccs, val, TRUE);
if ((val & TMR_CSR_RUN) == 0) { /* clearing run? */ if ((val & TMR_CSR_RUN) == 0) { /* clearing run? */
sim_cancel (&tmr_unit); /* cancel timer */
if (tmr_iccs & TMR_CSR_RUN) { /* run 1 -> 0? */ if (tmr_iccs & TMR_CSR_RUN) { /* run 1 -> 0? */
tmr_icr = icr_rd (); /* update itr */ tmr_icr = icr_rd (); /* update itr */
sim_rtcn_calb (0, TMR_CLK); /* stop timer */ sim_rtcn_calb (0, TMR_CLK); /* stop timer */
} }
sim_cancel (&tmr_unit); /* cancel timer */
} }
if (val & CSR_DONE) /* Interrupt Acked? */ if (val & CSR_DONE) /* Interrupt Acked? */
sim_rtcn_tick_ack (20, TMR_CLK); /* Let timers know */ sim_rtcn_tick_ack (20, TMR_CLK); /* Let timers know */
@ -673,7 +673,7 @@ int32 icr_rd (void)
int32 result; int32 result;
if (tmr_iccs & TMR_CSR_RUN) { /* running? */ if (tmr_iccs & TMR_CSR_RUN) { /* running? */
uint32 usecs_remaining = (uint32)sim_timer_activate_time_usecs (&tmr_unit); uint32 usecs_remaining = (uint32)sim_activate_time_usecs (&tmr_unit);
result = (int32)(~usecs_remaining + 1); result = (int32)(~usecs_remaining + 1);
} }

2
VAX/vax860_stddev.c
View file

@ -755,11 +755,11 @@ void iccs_wr (int32 val)
{ {
sim_debug_bits_hdr (TMR_DB_REG, &tmr_dev, "iccs_wr()", tmr_iccs_bits, tmr_iccs, val, TRUE); sim_debug_bits_hdr (TMR_DB_REG, &tmr_dev, "iccs_wr()", tmr_iccs_bits, tmr_iccs, val, TRUE);
if ((val & TMR_CSR_RUN) == 0) { /* clearing run? */ if ((val & TMR_CSR_RUN) == 0) { /* clearing run? */
sim_cancel (&tmr_unit); /* cancel timer */
if (tmr_iccs & TMR_CSR_RUN) { /* run 1 -> 0? */ if (tmr_iccs & TMR_CSR_RUN) { /* run 1 -> 0? */
tmr_icr = icr_rd (); /* update itr */ tmr_icr = icr_rd (); /* update itr */
sim_rtcn_calb (0, TMR_CLK); /* stop timer */ sim_rtcn_calb (0, TMR_CLK); /* stop timer */
} }
sim_cancel (&tmr_unit); /* cancel timer */
} }
if (val & CSR_DONE) /* Interrupt Acked? */ if (val & CSR_DONE) /* Interrupt Acked? */
sim_rtcn_tick_ack (20, TMR_CLK); /* Let timers know */ sim_rtcn_tick_ack (20, TMR_CLK); /* Let timers know */