VAX730, VAX750, VAX780, VAX8600: Fix interval timer ics value
- When the running timer is explicitly stopped the ics value needs to be determined before canceling the active unit.
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e36873f466
commit
5cd0ea4d59
4 changed files with 6 additions and 6 deletions
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@ -654,11 +654,11 @@ void iccs_wr (int32 val)
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{
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sim_debug_bits_hdr (TMR_DB_REG, &tmr_dev, "iccs_wr()", tmr_iccs_bits, tmr_iccs, val, TRUE);
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if ((val & TMR_CSR_RUN) == 0) { /* clearing run? */
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sim_cancel (&tmr_unit); /* cancel timer */
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if (tmr_iccs & TMR_CSR_RUN) { /* run 1 -> 0? */
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tmr_icr = icr_rd (); /* update itr */
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sim_rtcn_calb (0, TMR_CLK); /* stop timer */
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}
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sim_cancel (&tmr_unit); /* cancel timer */
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}
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if (val & CSR_DONE) /* Interrupt Acked? */
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sim_rtcn_tick_ack (20, TMR_CLK); /* Let timers know */
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@ -642,7 +642,7 @@ return "console terminal output";
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int32 iccs_rd (void)
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{
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sim_debug (TMR_DB_REG, &tmr_dev, "iccs_rd() = 0x%08X\n", tmr_iccs & TMR_CSR_RD);
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sim_debug_bits_hdr (TMR_DB_REG, &tmr_dev, "iccs_rd()", tmr_iccs_bits, tmr_iccs, tmr_iccs, TRUE);
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return tmr_iccs & TMR_CSR_RD;
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}
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@ -650,11 +650,11 @@ void iccs_wr (int32 val)
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{
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sim_debug_bits_hdr (TMR_DB_REG, &tmr_dev, "iccs_wr()", tmr_iccs_bits, tmr_iccs, val, TRUE);
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if ((val & TMR_CSR_RUN) == 0) { /* clearing run? */
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sim_cancel (&tmr_unit); /* cancel timer */
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if (tmr_iccs & TMR_CSR_RUN) { /* run 1 -> 0? */
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tmr_icr = icr_rd (); /* update itr */
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sim_rtcn_calb (0, TMR_CLK); /* stop timer */
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}
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sim_cancel (&tmr_unit); /* cancel timer */
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}
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if (val & CSR_DONE) /* Interrupt Acked? */
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sim_rtcn_tick_ack (20, TMR_CLK); /* Let timers know */
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@ -620,11 +620,11 @@ void iccs_wr (int32 val)
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{
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sim_debug_bits_hdr (TMR_DB_REG, &tmr_dev, "iccs_wr()", tmr_iccs_bits, tmr_iccs, val, TRUE);
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if ((val & TMR_CSR_RUN) == 0) { /* clearing run? */
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sim_cancel (&tmr_unit); /* cancel timer */
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if (tmr_iccs & TMR_CSR_RUN) { /* run 1 -> 0? */
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tmr_icr = icr_rd (); /* update itr */
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sim_rtcn_calb (0, TMR_CLK); /* stop timer */
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}
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sim_cancel (&tmr_unit); /* cancel timer */
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}
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if (val & CSR_DONE) /* Interrupt Acked? */
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sim_rtcn_tick_ack (20, TMR_CLK); /* Let timers know */
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@ -673,7 +673,7 @@ int32 icr_rd (void)
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int32 result;
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if (tmr_iccs & TMR_CSR_RUN) { /* running? */
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uint32 usecs_remaining = (uint32)sim_timer_activate_time_usecs (&tmr_unit);
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uint32 usecs_remaining = (uint32)sim_activate_time_usecs (&tmr_unit);
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result = (int32)(~usecs_remaining + 1);
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}
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@ -755,11 +755,11 @@ void iccs_wr (int32 val)
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{
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sim_debug_bits_hdr (TMR_DB_REG, &tmr_dev, "iccs_wr()", tmr_iccs_bits, tmr_iccs, val, TRUE);
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if ((val & TMR_CSR_RUN) == 0) { /* clearing run? */
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sim_cancel (&tmr_unit); /* cancel timer */
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if (tmr_iccs & TMR_CSR_RUN) { /* run 1 -> 0? */
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tmr_icr = icr_rd (); /* update itr */
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sim_rtcn_calb (0, TMR_CLK); /* stop timer */
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}
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sim_cancel (&tmr_unit); /* cancel timer */
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}
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if (val & CSR_DONE) /* Interrupt Acked? */
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sim_rtcn_tick_ack (20, TMR_CLK); /* Let timers know */
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