Revised HP2100 from Dave Bryan with his fixes to cleanup compiling under the LLVM clang compiler
This commit is contained in:
parent
b816a42177
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5d081f8d93
24 changed files with 401 additions and 215 deletions
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@ -1157,11 +1157,11 @@ if (baci_edsiw & (baci_status ^ baci_dsrw) & IN_MODEM) /* device interrupt? */
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baci_status = baci_status | IN_DEVINT; /* set flag */
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baci_status = baci_status | IN_DEVINT; /* set flag */
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if ((baci_status & IN_STDIRQ) || /* standard interrupt? */
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if ((baci_status & IN_STDIRQ) || /* standard interrupt? */
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(!(baci_icw & OUT_DCPC) && /* or under program control */
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!(baci_icw & OUT_DCPC) && /* or under program control */
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(baci_status & IN_FIFOIRQ)) || /* and FIFO interrupt? */
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(baci_status & IN_FIFOIRQ) || /* and FIFO interrupt? */
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((IO_MODE == RECV) && /* or receiving */
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(IO_MODE == RECV) && /* or receiving */
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(baci_edsiw & OUT_ENCM) && /* and char mode */
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(baci_edsiw & OUT_ENCM) && /* and char mode */
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(baci_fget != baci_fput))) { /* and FIFO not empty? */
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(baci_fget != baci_fput)) { /* and FIFO not empty? */
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if (baci.lockout) { /* interrupt lockout? */
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if (baci.lockout) { /* interrupt lockout? */
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if (DEBUG_PRI (baci_dev, DEB_CMDS))
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if (DEBUG_PRI (baci_dev, DEB_CMDS))
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@ -1185,8 +1185,8 @@ if ((baci_status & IN_STDIRQ) || /* standard interrupt? *
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}
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}
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if ((baci_icw & OUT_DCPC) && /* DCPC enabled? */
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if ((baci_icw & OUT_DCPC) && /* DCPC enabled? */
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(((IO_MODE == XMIT) && (baci_fcount < 128)) || /* and xmit and room in FIFO */
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((IO_MODE == XMIT) && (baci_fcount < 128) || /* and xmit and room in FIFO */
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((IO_MODE == RECV) && (baci_fcount > 0)))) { /* or recv and data in FIFO? */
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(IO_MODE == RECV) && (baci_fcount > 0))) { /* or recv and data in FIFO? */
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if (baci.lockout) { /* interrupt lockout? */
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if (baci.lockout) { /* interrupt lockout? */
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if (DEBUG_PRI (baci_dev, DEB_CMDS))
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if (DEBUG_PRI (baci_dev, DEB_CMDS))
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@ -1472,9 +1472,9 @@ if (baci_uart_clk > 0) { /* transfer in progress?
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if ((IO_MODE == XMIT) && /* transmit mode? */
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if ((IO_MODE == XMIT) && /* transmit mode? */
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((baci_uart_clk == 0) || /* and end of character? */
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((baci_uart_clk == 0) || /* and end of character? */
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((baci_uart_clk == 8) && /* or last stop bit */
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(baci_uart_clk == 8) && /* or last stop bit */
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(baci_cfcw & OUT_STBITS) && /* and extra stop bit requested */
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(baci_cfcw & OUT_STBITS) && /* and extra stop bit requested */
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((baci_cfcw & OUT_CHARSIZE) == 0)))) { /* and 1.5 stop bits used? */
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((baci_cfcw & OUT_CHARSIZE) == 0))) { /* and 1.5 stop bits used? */
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baci_uart_clk = 0; /* clear clock count */
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baci_uart_clk = 0; /* clear clock count */
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@ -1,6 +1,6 @@
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HP 2100 SIMULATOR BUG FIX WRITEUPS
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HP 2100 SIMULATOR BUG FIX WRITEUPS
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==================================
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==================================
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Last update: 2012-03-25
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Last update: 2012-05-07
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1. PROBLEM: Booting from magnetic tape reports "HALT instruction, P: 77756
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1. PROBLEM: Booting from magnetic tape reports "HALT instruction, P: 77756
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@ -6280,3 +6280,29 @@
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(hp2100_mt.c).
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(hp2100_mt.c).
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STATUS: Fixed in version 3.9-0.
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STATUS: Fixed in version 3.9-0.
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247. PROBLEM: The ICD disc read end-of-track delay is not optimal.
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VERSION: 3.9-0
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OBSERVATION: To avoid End of Cylinder errors when reading the last sector
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of a track, the ICD controller must delay more than the usual intersector
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time to allow the OS driver to send an Untalk if a read is to be
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terminated. Currently, the longer delay is used if an end-of-cylinder
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condition is present. However, the delay is needed only if the resulting
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seek attempt would cause an error if the read is continued; the normal
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delay should be used if the seek is permitted and would succeed.
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Also, if the host does send an Untalk during this time, the longer delay
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should be cancelled, and command termination should be scheduled for
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immediate processing.
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CAUSE: Suboptimal implementation.
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RESOLUTION: Modify "end_read" (hp_disclib.c) to use the longer time only
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if the seek would fail, and modify "complete_read" (hp2100_di_da.c) to
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cancel the intersector delay and schedule the completion phase immediately.
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STATUS: Patches prepared 2012-05-07.
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@ -29,6 +29,7 @@
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DMA1,DMA2 12607B/12578A/12895A direct memory access controller
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DMA1,DMA2 12607B/12578A/12895A direct memory access controller
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DCPC1,DCPC2 12897B dual channel port controller
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DCPC1,DCPC2 12897B dual channel port controller
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09-May-12 JDB Separated assignments from conditional expressions
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13-Jan-12 JDB Minor speedup in "is_mapped"
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13-Jan-12 JDB Minor speedup in "is_mapped"
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Added casts to cpu_mod, dmasio, dmapio, cpu_reset, dma_reset
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Added casts to cpu_mod, dmasio, dmapio, cpu_reset, dma_reset
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07-Apr-11 JDB Fixed I/O return status bug for DMA cycles
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07-Apr-11 JDB Fixed I/O return status bug for DMA cycles
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@ -1054,7 +1055,8 @@ for (i = OPTDEV; i <= MAXDEV; i++) /* default optional devi
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dtab [PWR] = &pwrf_dib; /* for now, powerfail is always present */
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dtab [PWR] = &pwrf_dib; /* for now, powerfail is always present */
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for (i = 0; (dptr = sim_devices [i]); i++) { /* loop thru dev */
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for (i = 0; sim_devices [i] != NULL; i++) { /* loop thru dev */
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dptr = sim_devices [i];
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dibptr = (DIB *) dptr->ctxt; /* get DIB */
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dibptr = (DIB *) dptr->ctxt; /* get DIB */
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if (dibptr && !(dptr->flags & DEV_DIS)) { /* handler exists and device is enabled? */
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if (dibptr && !(dptr->flags & DEV_DIS)) { /* handler exists and device is enabled? */
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@ -1464,17 +1466,17 @@ while (reason == SCPE_OK) { /* loop until halted */
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*/
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*/
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if ((sim_idle_enab) && (intrq == 0)) /* idle enabled w/o pending irq? */
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if ((sim_idle_enab) && (intrq == 0)) /* idle enabled w/o pending irq? */
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if ((((PC == err_PC) || /* RTE through RTE-IVB */
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if (((PC == err_PC) || /* RTE through RTE-IVB */
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((PC == (err_PC - 1)) && /* RTE-6/VM */
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((PC == (err_PC - 1)) && /* RTE-6/VM */
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((ReadW (PC) & I_MRG) == I_ISZ))) && /* RTE jump target */
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((ReadW (PC) & I_MRG) == I_ISZ))) && /* RTE jump target */
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(mp_fence == CLEAR) && (M [xeqt] == 0) && /* RTE idle indications */
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(mp_fence == CLEAR) && (M [xeqt] == 0) && /* RTE idle indications */
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(M [tbg] == clk_dib.select_code)) || /* RTE verification */
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(M [tbg] == clk_dib.select_code) || /* RTE verification */
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((PC == (err_PC - 3)) && /* DOS through DOS-III */
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(PC == (err_PC - 3)) && /* DOS through DOS-III */
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(ReadW (PC) == I_STF) && /* DOS jump target */
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(ReadW (PC) == I_STF) && /* DOS jump target */
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(AR == 0177777) && (BR == 0177777) && /* DOS idle indication */
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(AR == 0177777) && (BR == 0177777) && /* DOS idle indication */
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(M [m64] == 0177700) && /* DOS verification */
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(M [m64] == 0177700) && /* DOS verification */
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(M [p64] == 0000100))) /* DOS verification */
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(M [p64] == 0000100)) /* DOS verification */
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sim_idle (TMR_POLL, FALSE); /* idle the simulator */
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sim_idle (TMR_POLL, FALSE); /* idle the simulator */
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break;
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break;
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@ -3351,7 +3353,7 @@ t_stat status;
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uint32 ioresult;
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uint32 ioresult;
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IOCYCLE signals;
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IOCYCLE signals;
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if ((bytes && !even) || (dma [ch].cw3 != DMASK)) { /* normal cycle? */
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if (bytes && !even || dma [ch].cw3 != DMASK) { /* normal cycle? */
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if (input) /* input cycle? */
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if (input) /* input cycle? */
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signals = ioIOI | ioCLF; /* assert IOI and CLF */
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signals = ioIOI | ioCLF; /* assert IOI and CLF */
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else /* output cycle */
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else /* output cycle */
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@ -3611,7 +3613,8 @@ uint32 i, j, k;
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t_bool is_conflict = FALSE;
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t_bool is_conflict = FALSE;
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uint32 conflicts [MAXDEV + 1] = { 0 };
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uint32 conflicts [MAXDEV + 1] = { 0 };
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for (i = 0; (dptr = sim_devices[i]); i++) {
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for (i = 0; sim_devices [i] != NULL; i++) {
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dptr = sim_devices [i];
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dibptr = (DIB *) dptr->ctxt;
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dibptr = (DIB *) dptr->ctxt;
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if (dibptr && !(dptr->flags & DEV_DIS))
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if (dibptr && !(dptr->flags & DEV_DIS))
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if (++conflicts [dibptr->select_code] > 1)
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if (++conflicts [dibptr->select_code] > 1)
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@ -3629,9 +3632,10 @@ if (is_conflict) {
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if (sim_log)
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if (sim_log)
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fprintf (sim_log, "Select code %o conflict:", i);
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fprintf (sim_log, "Select code %o conflict:", i);
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for (j = 0; (dptr = sim_devices[j]); j++) {
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for (j = 0; sim_devices [j] != NULL; j++) {
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dptr = sim_devices [j];
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dibptr = (DIB *) dptr->ctxt;
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dibptr = (DIB *) dptr->ctxt;
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if (dibptr && !(dptr->flags & DEV_DIS) && (i == dibptr->select_code)) {
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if (dibptr && !(dptr->flags & DEV_DIS) && i == dibptr->select_code) {
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if (k < conflicts [i]) {
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if (k < conflicts [i]) {
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printf (" and");
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printf (" and");
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@ -1,6 +1,6 @@
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/* hp2100_cpu0.c: HP 1000 user microcode and unimplemented instruction set stubs
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/* hp2100_cpu0.c: HP 1000 user microcode and unimplemented instruction set stubs
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Copyright (c) 2006-2010, J. David Bryan
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Copyright (c) 2006-2012, J. David Bryan
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Permission is hereby granted, free of charge, to any person obtaining a
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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copy of this software and associated documentation files (the "Software"),
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@ -25,6 +25,7 @@
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CPU0 User microcode and unimplemented firmware options
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CPU0 User microcode and unimplemented firmware options
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09-May-12 JDB Separated assignments from conditional expressions
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04-Nov-10 JDB Removed DS note regarding PIF card (is now implemented)
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04-Nov-10 JDB Removed DS note regarding PIF card (is now implemented)
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18-Sep-08 JDB .FLUN and self-tests for VIS and SIGNAL are NOP if not present
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18-Sep-08 JDB .FLUN and self-tests for VIS and SIGNAL are NOP if not present
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11-Sep-08 JDB Moved microcode function prototypes to hp2100_cpu1.h
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11-Sep-08 JDB Moved microcode function prototypes to hp2100_cpu1.h
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@ -129,9 +130,11 @@ uint32 entry;
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entry = IR & 017; /* mask to entry point */
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entry = IR & 017; /* mask to entry point */
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if (op_ds[entry] != OP_N)
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if (op_ds [entry] != OP_N) {
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if ((reason = cpu_ops (op_ds[entry], op, intrq))) /* get instruction operands */
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reason = cpu_ops (op_ds[entry], op, intrq); /* get instruction operands */
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return reason;
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if (reason != SCPE_OK) /* did the evaluation fail? */
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return reason; /* return the reason for failure */
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}
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switch (entry) { /* decode IR<3:0> */
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switch (entry) { /* decode IR<3:0> */
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@ -191,23 +194,23 @@ switch (IR) {
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switch ((IR >> 4) & 037) { /* decode IR<8:4> */
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switch ((IR >> 4) & 037) { /* decode IR<8:4> */
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/* case 000: *//* 105000-105017 */
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/* case 000: ** 105000-105017 */
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/* return cpu_user_00 (IR, intrq); *//* uncomment to handle instruction */
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/* return cpu_user_00 (IR, intrq); ** uncomment to handle instruction */
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/* case 001: *//* 105020-105037 */
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/* case 001: ** 105020-105037 */
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/* return cpu_user_01 (IR, intrq); *//* uncomment to handle instruction */
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/* return cpu_user_01 (IR, intrq); ** uncomment to handle instruction */
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/* case 0nn: *//* other cases as needed */
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/* case 0nn: ** other cases as needed */
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/* return cpu_user_nn (IR, intrq); *//* uncomment to handle instruction */
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/* return cpu_user_nn (IR, intrq); ** uncomment to handle instruction */
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case 020: /* 10x400-10x417 */
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case 020: /* 10x400-10x417 */
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return cpu_user_20 (IR, intrq); /* call sample dispatcher */
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return cpu_user_20 (IR, intrq); /* call sample dispatcher */
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/* case 021: *//* 10x420-10x437 */
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/* case 021: ** 10x420-10x437 */
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/* return cpu_user_21 (IR, intrq); *//* uncomment to handle instruction */
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/* return cpu_user_21 (IR, intrq); ** uncomment to handle instruction */
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/* case 0nn: *//* other cases as needed */
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/* case 0nn: ** other cases as needed */
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/* return cpu_user_nn (IR, intrq); *//* uncomment to handle instruction */
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/* return cpu_user_nn (IR, intrq); ** uncomment to handle instruction */
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default: /* others undefined */
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default: /* others undefined */
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reason = stop_inst;
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reason = stop_inst;
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entry = IR & 017; /* mask to entry point */
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entry = IR & 017; /* mask to entry point */
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if (op_user_20 [entry] != OP_N)
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if (op_user_20 [entry] != OP_N) {
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if ((reason = cpu_ops (op_user_20 [entry], op, intrq))) /* get instruction operands */
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reason = cpu_ops (op_user_20 [entry], op, intrq); /* get instruction operands */
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return reason;
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if (reason != SCPE_OK) /* did the evaluation fail? */
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return reason; /* return the reason for failure */
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}
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switch (entry) { /* decode IR<4:0> */
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switch (entry) { /* decode IR<4:0> */
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case 000: /* 10x400 */
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case 000: /* 10x400 */
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/* break; *//* uncomment to handle instruction */
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/* break; ** uncomment to handle instruction */
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case 001: /* 10x401 */
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case 001: /* 10x401 */
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/* break; *//* uncomment to handle instruction */
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/* break; ** uncomment to handle instruction */
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/* case 0nn: *//* other cases as needed */
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/* case 0nn: ** other cases as needed */
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/* break; *//* uncomment to handle instruction */
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/* break; ** uncomment to handle instruction */
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default: /* others undefined */
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default: /* others undefined */
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reason = stop_inst;
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reason = stop_inst;
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@ -1,6 +1,6 @@
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/* hp2100_cpu1.c: HP 2100/1000 EAU simulator and UIG dispatcher
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/* hp2100_cpu1.c: HP 2100/1000 EAU simulator and UIG dispatcher
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Copyright (c) 2005-2008, Robert M. Supnik
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Copyright (c) 2005-2012, Robert M. Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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copy of this software and associated documentation files (the "Software"),
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@ -25,6 +25,7 @@
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CPU1 Extended arithmetic and optional microcode dispatchers
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CPU1 Extended arithmetic and optional microcode dispatchers
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09-May-12 JDB Separated assignments from conditional expressions
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11-Sep-08 JDB Moved microcode function prototypes to hp2100_cpu1.h
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11-Sep-08 JDB Moved microcode function prototypes to hp2100_cpu1.h
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05-Sep-08 JDB Moved option-present tests to UIG dispatchers
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05-Sep-08 JDB Moved option-present tests to UIG dispatchers
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Call "user microcode" dispatcher for unclaimed UIG instructions
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Call "user microcode" dispatcher for unclaimed UIG instructions
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@ -245,14 +246,15 @@ switch ((IR >> 8) & 0377) { /* decode IR<15:8> */
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case 010: /* MPY 100200 (OP_K) */
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case 010: /* MPY 100200 (OP_K) */
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MPY:
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MPY:
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if ((reason = cpu_ops (OP_K, op, intrq))) /* get operand */
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reason = cpu_ops (OP_K, op, intrq); /* get operand */
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break;
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if (reason == SCPE_OK) { /* successful eval? */
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sop1 = SEXT (AR); /* sext AR */
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sop1 = SEXT (AR); /* sext AR */
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sop2 = SEXT (op[0].word); /* sext mem */
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sop2 = SEXT (op[0].word); /* sext mem */
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sop1 = sop1 * sop2; /* signed mpy */
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sop1 = sop1 * sop2; /* signed mpy */
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BR = (sop1 >> 16) & DMASK; /* to BR'AR */
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BR = (sop1 >> 16) & DMASK; /* to BR'AR */
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AR = sop1 & DMASK;
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AR = sop1 & DMASK;
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O = 0; /* no overflow */
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O = 0; /* no overflow */
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}
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break;
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break;
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default: /* others undefined */
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default: /* others undefined */
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@ -262,9 +264,11 @@ switch ((IR >> 8) & 0377) { /* decode IR<15:8> */
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break;
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break;
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case 0201: /* DIV 100400 (OP_K) */
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case 0201: /* DIV 100400 (OP_K) */
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if ((reason = cpu_ops (OP_K, op, intrq))) /* get operand */
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reason = cpu_ops (OP_K, op, intrq); /* get operand */
|
||||||
|
if (reason != SCPE_OK) /* eval failed? */
|
||||||
break;
|
break;
|
||||||
if ((rs = qs = BR & SIGN)) { /* save divd sign, neg? */
|
rs = qs = BR & SIGN; /* save divd sign */
|
||||||
|
if (rs) { /* neg? */
|
||||||
AR = (~AR + 1) & DMASK; /* make B'A pos */
|
AR = (~AR + 1) & DMASK; /* make B'A pos */
|
||||||
BR = (~BR + (AR == 0)) & DMASK; /* make divd pos */
|
BR = (~BR + (AR == 0)) & DMASK; /* make divd pos */
|
||||||
}
|
}
|
||||||
|
@ -317,17 +321,19 @@ switch ((IR >> 8) & 0377) { /* decode IR<15:8> */
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case 0210: /* DLD 104200 (OP_D) */
|
case 0210: /* DLD 104200 (OP_D) */
|
||||||
if ((reason = cpu_ops (OP_D, op, intrq))) /* get operand */
|
reason = cpu_ops (OP_D, op, intrq); /* get operand */
|
||||||
break;
|
if (reason == SCPE_OK) { /* successful eval? */
|
||||||
AR = (op[0].dword >> 16) & DMASK; /* load AR */
|
AR = (op[0].dword >> 16) & DMASK; /* load AR */
|
||||||
BR = op[0].dword & DMASK; /* load BR */
|
BR = op[0].dword & DMASK; /* load BR */
|
||||||
|
}
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case 0211: /* DST 104400 (OP_A) */
|
case 0211: /* DST 104400 (OP_A) */
|
||||||
if ((reason = cpu_ops (OP_A, op, intrq))) /* get operand */
|
reason = cpu_ops (OP_A, op, intrq); /* get operand */
|
||||||
break;
|
if (reason == SCPE_OK) { /* successful eval? */
|
||||||
WriteW (op[0].word, AR); /* store AR */
|
WriteW (op[0].word, AR); /* store AR */
|
||||||
WriteW ((op[0].word + 1) & VAMASK, BR); /* store BR */
|
WriteW ((op[0].word + 1) & VAMASK, BR); /* store BR */
|
||||||
|
}
|
||||||
break;
|
break;
|
||||||
|
|
||||||
default: /* should never get here */
|
default: /* should never get here */
|
||||||
|
@ -733,9 +739,11 @@ uint32 i, MA;
|
||||||
for (i = 0; i < OP_N_F; i++) {
|
for (i = 0; i < OP_N_F; i++) {
|
||||||
flags = pattern & OP_M_FLAGS; /* get operand pattern */
|
flags = pattern & OP_M_FLAGS; /* get operand pattern */
|
||||||
|
|
||||||
if (flags >= OP_ADR) /* address operand? */
|
if (flags >= OP_ADR) { /* address operand? */
|
||||||
if ((reason = resolve (ReadW (PC), &MA, irq))) /* resolve indirects */
|
reason = resolve (ReadW (PC), &MA, irq); /* resolve indirects */
|
||||||
|
if (reason != SCPE_OK) /* resolution failed? */
|
||||||
return reason;
|
return reason;
|
||||||
|
}
|
||||||
|
|
||||||
switch (flags) {
|
switch (flags) {
|
||||||
case OP_NUL: /* null operand */
|
case OP_NUL: /* null operand */
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
/* hp2100_cpu2.c: HP 2100/1000 FP/DMS/EIG/IOP instructions
|
/* hp2100_cpu2.c: HP 2100/1000 FP/DMS/EIG/IOP instructions
|
||||||
|
|
||||||
Copyright (c) 2005-2008, Robert M. Supnik
|
Copyright (c) 2005-2012, Robert M. Supnik
|
||||||
|
|
||||||
Permission is hereby granted, free of charge, to any person obtaining a
|
Permission is hereby granted, free of charge, to any person obtaining a
|
||||||
copy of this software and associated documentation files (the "Software"),
|
copy of this software and associated documentation files (the "Software"),
|
||||||
|
@ -26,6 +26,7 @@
|
||||||
CPU2 Floating-point, dynamic mapping, extended, and I/O processor
|
CPU2 Floating-point, dynamic mapping, extended, and I/O processor
|
||||||
instructions
|
instructions
|
||||||
|
|
||||||
|
09-May-12 JDB Separated assignments from conditional expressions
|
||||||
11-Sep-08 JDB Moved microcode function prototypes to hp2100_cpu1.h
|
11-Sep-08 JDB Moved microcode function prototypes to hp2100_cpu1.h
|
||||||
05-Sep-08 JDB Removed option-present tests (now in UIG dispatchers)
|
05-Sep-08 JDB Removed option-present tests (now in UIG dispatchers)
|
||||||
05-Aug-08 JDB Updated mp_dms_jmp calling sequence
|
05-Aug-08 JDB Updated mp_dms_jmp calling sequence
|
||||||
|
@ -243,9 +244,12 @@ uint32 i, t, mapi, mapj;
|
||||||
absel = (IR & I_AB)? 1: 0; /* get A/B select */
|
absel = (IR & I_AB)? 1: 0; /* get A/B select */
|
||||||
entry = IR & 037; /* mask to entry point */
|
entry = IR & 037; /* mask to entry point */
|
||||||
|
|
||||||
if (op_dms[entry] != OP_N)
|
if (op_dms [entry] != OP_N) {
|
||||||
if ((reason = cpu_ops (op_dms[entry], op, intrq))) /* get instruction operands */
|
reason = cpu_ops (op_dms [entry], op, intrq); /* get instruction operands */
|
||||||
return reason;
|
|
||||||
|
if (reason != SCPE_OK) /* evaluation failed? */
|
||||||
|
return reason; /* return reason for failure */
|
||||||
|
}
|
||||||
|
|
||||||
switch (entry) { /* decode IR<3:0> */
|
switch (entry) { /* decode IR<3:0> */
|
||||||
|
|
||||||
|
@ -609,9 +613,12 @@ int32 sop1, sop2;
|
||||||
absel = (IR & I_AB)? 1: 0; /* get A/B select */
|
absel = (IR & I_AB)? 1: 0; /* get A/B select */
|
||||||
entry = IR & 037; /* mask to entry point */
|
entry = IR & 037; /* mask to entry point */
|
||||||
|
|
||||||
if (op_eig[entry] != OP_N)
|
if (op_eig [entry] != OP_N) {
|
||||||
if ((reason = cpu_ops (op_eig[entry], op, intrq))) /* get instruction operands */
|
reason = cpu_ops (op_eig [entry], op, intrq); /* get instruction operands */
|
||||||
return reason;
|
|
||||||
|
if (reason != SCPE_OK) /* evaluation failed? */
|
||||||
|
return reason; /* return reason for failure */
|
||||||
|
}
|
||||||
|
|
||||||
switch (entry) { /* decode IR<4:0> */
|
switch (entry) { /* decode IR<4:0> */
|
||||||
|
|
||||||
|
@ -988,9 +995,12 @@ else if (entry <= 057) /* IR = 10x440-457? */
|
||||||
|
|
||||||
entry = entry - 060; /* offset 10x460-477 */
|
entry = entry - 060; /* offset 10x460-477 */
|
||||||
|
|
||||||
if (op_iop[entry] != OP_N)
|
if (op_iop [entry] != OP_N) {
|
||||||
if ((reason = cpu_ops (op_iop[entry], op, intrq))) /* get instruction operands */
|
reason = cpu_ops (op_iop [entry], op, intrq); /* get instruction operands */
|
||||||
return reason;
|
|
||||||
|
if (reason != SCPE_OK) /* evaluation failed? */
|
||||||
|
return reason; /* return reason for failure */
|
||||||
|
}
|
||||||
|
|
||||||
switch (entry) { /* decode IR<5:0> */
|
switch (entry) { /* decode IR<5:0> */
|
||||||
|
|
||||||
|
|
|
@ -25,6 +25,7 @@
|
||||||
|
|
||||||
CPU3 Fast FORTRAN and Double Integer instructions
|
CPU3 Fast FORTRAN and Double Integer instructions
|
||||||
|
|
||||||
|
09-May-12 JDB Separated assignments from conditional expressions
|
||||||
11-Sep-08 JDB Moved microcode function prototypes to hp2100_cpu1.h
|
11-Sep-08 JDB Moved microcode function prototypes to hp2100_cpu1.h
|
||||||
05-Sep-08 JDB Removed option-present tests (now in UIG dispatchers)
|
05-Sep-08 JDB Removed option-present tests (now in UIG dispatchers)
|
||||||
05-Aug-08 JDB Updated mp_dms_jmp calling sequence
|
05-Aug-08 JDB Updated mp_dms_jmp calling sequence
|
||||||
|
@ -185,17 +186,23 @@ int32 i;
|
||||||
entry = IR & 037; /* mask to entry point */
|
entry = IR & 037; /* mask to entry point */
|
||||||
|
|
||||||
if (UNIT_CPU_MODEL != UNIT_1000_F) { /* 2100/M/E-Series? */
|
if (UNIT_CPU_MODEL != UNIT_1000_F) { /* 2100/M/E-Series? */
|
||||||
if (op_ffp_e[entry] != OP_N)
|
if (op_ffp_e [entry] != OP_N) {
|
||||||
if ((reason = cpu_ops (op_ffp_e[entry], op, intrq)))/* get instruction operands */
|
reason = cpu_ops (op_ffp_e [entry], op, intrq); /* get instruction operands */
|
||||||
return reason;
|
|
||||||
|
if (reason != SCPE_OK) /* evaluation failed? */
|
||||||
|
return reason; /* return reason for failure */
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
#if defined (HAVE_INT64) /* int64 support available */
|
#if defined (HAVE_INT64) /* int64 support available */
|
||||||
|
|
||||||
else { /* F-Series */
|
else { /* F-Series */
|
||||||
if (op_ffp_f[entry] != OP_N)
|
if (op_ffp_f [entry] != OP_N) {
|
||||||
if ((reason = cpu_ops (op_ffp_f[entry], op, intrq)))/* get instruction operands */
|
reason = cpu_ops (op_ffp_f [entry], op, intrq); /* get instruction operands */
|
||||||
return reason;
|
|
||||||
|
if (reason != SCPE_OK) /* evaluation failed? */
|
||||||
|
return reason; /* return reason for failure */
|
||||||
|
}
|
||||||
|
|
||||||
switch (entry) { /* decode IR<4:0> */
|
switch (entry) { /* decode IR<4:0> */
|
||||||
|
|
||||||
|
@ -417,7 +424,8 @@ switch (entry) { /* decode IR<4:0> */
|
||||||
sa = op[0].word - 1;
|
sa = op[0].word - 1;
|
||||||
|
|
||||||
da = ReadW (sa); /* get jump target */
|
da = ReadW (sa); /* get jump target */
|
||||||
if ((reason = resolve (da, &MA, intrq))) { /* resolve indirects */
|
reason = resolve (da, &MA, intrq); /* resolve indirects */
|
||||||
|
if (reason != SCPE_OK) { /* resolution failed? */
|
||||||
PC = err_PC; /* irq restarts instruction */
|
PC = err_PC; /* irq restarts instruction */
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
@ -435,7 +443,8 @@ switch (entry) { /* decode IR<4:0> */
|
||||||
op[1].word = op[1].word + /* compute element offset */
|
op[1].word = op[1].word + /* compute element offset */
|
||||||
(op[2].word - 1) * op[3].word;
|
(op[2].word - 1) * op[3].word;
|
||||||
else { /* 3-dim access */
|
else { /* 3-dim access */
|
||||||
if ((reason = cpu_ops (OP_KK, op2, intrq))) {/* get 1st, 2nd ranges */
|
reason = cpu_ops (OP_KK, op2, intrq); /* get 1st, 2nd ranges */
|
||||||
|
if (reason != SCPE_OK) { /* evaluation failed? */
|
||||||
PC = err_PC; /* irq restarts instruction */
|
PC = err_PC; /* irq restarts instruction */
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
@ -461,7 +470,8 @@ switch (entry) { /* decode IR<4:0> */
|
||||||
|
|
||||||
for (j = 0; j < sc; j++) {
|
for (j = 0; j < sc; j++) {
|
||||||
MA = ReadW (sa++); /* get addr of actual */
|
MA = ReadW (sa++); /* get addr of actual */
|
||||||
if ((reason = resolve (MA, &MA, intrq))) { /* resolve indirect */
|
reason = resolve (MA, &MA, intrq); /* resolve indirect */
|
||||||
|
if (reason != SCPE_OK) { /* resolution failed? */
|
||||||
PC = err_PC; /* irq restarts instruction */
|
PC = err_PC; /* irq restarts instruction */
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
@ -643,9 +653,11 @@ t_stat reason = SCPE_OK;
|
||||||
|
|
||||||
entry = IR & 017; /* mask to entry point */
|
entry = IR & 017; /* mask to entry point */
|
||||||
|
|
||||||
if (op_dbi[entry] != OP_N)
|
if (op_dbi[entry] != OP_N) {
|
||||||
if ((reason = cpu_ops (op_dbi[entry], op, intrq))) /* get instruction operands */
|
reason = cpu_ops (op_dbi [entry], op, intrq); /* get instruction operands */
|
||||||
return reason;
|
if (reason != SCPE_OK) /* evaluation failed? */
|
||||||
|
return reason; /* return reason for failure */
|
||||||
|
}
|
||||||
|
|
||||||
switch (entry) { /* decode IR<3:0> */
|
switch (entry) { /* decode IR<3:0> */
|
||||||
|
|
||||||
|
|
|
@ -25,6 +25,7 @@
|
||||||
|
|
||||||
CPU4 Floating Point Processor and Scientific Instruction Set
|
CPU4 Floating Point Processor and Scientific Instruction Set
|
||||||
|
|
||||||
|
09-May-12 JDB Separated assignments from conditional expressions
|
||||||
06-Feb-12 JDB Added OPSIZE casts to fp_accum calls in .FPWR/.TPWR
|
06-Feb-12 JDB Added OPSIZE casts to fp_accum calls in .FPWR/.TPWR
|
||||||
11-Sep-08 JDB Moved microcode function prototypes to hp2100_cpu1.h
|
11-Sep-08 JDB Moved microcode function prototypes to hp2100_cpu1.h
|
||||||
05-Sep-08 JDB Removed option-present tests (now in UIG dispatchers)
|
05-Sep-08 JDB Removed option-present tests (now in UIG dispatchers)
|
||||||
|
@ -260,9 +261,12 @@ else
|
||||||
|
|
||||||
entry = opcode & 0177; /* map to <6:0> */
|
entry = opcode & 0177; /* map to <6:0> */
|
||||||
|
|
||||||
if (op_fpp[entry] != OP_N)
|
if (op_fpp [entry] != OP_N) {
|
||||||
if ((reason = cpu_ops (op_fpp[entry], op, intrq))) /* get instruction operands */
|
reason = cpu_ops (op_fpp [entry], op, intrq); /* get instruction operands */
|
||||||
return reason;
|
|
||||||
|
if (reason != SCPE_OK) /* evaluation failed? */
|
||||||
|
return reason; /* return reason for failure */
|
||||||
|
}
|
||||||
|
|
||||||
switch (entry) { /* decode IR<6:0> */
|
switch (entry) { /* decode IR<6:0> */
|
||||||
case 0000: /* FAD 105000 (OP_RF) */
|
case 0000: /* FAD 105000 (OP_RF) */
|
||||||
|
@ -599,9 +603,12 @@ static const OP t_one = { { 0040000, 0000000, 0000000, 0000002 } }; /* DEY 1.
|
||||||
|
|
||||||
entry = IR & 017; /* mask to entry point */
|
entry = IR & 017; /* mask to entry point */
|
||||||
|
|
||||||
if (op_sis[entry] != OP_N)
|
if (op_sis [entry] != OP_N) {
|
||||||
if ((reason = cpu_ops (op_sis[entry], op, intrq))) /* get instruction operands */
|
reason = cpu_ops (op_sis [entry], op, intrq); /* get instruction operands */
|
||||||
return reason;
|
|
||||||
|
if (reason != SCPE_OK) /* evaluation failed? */
|
||||||
|
return reason; /* return reason for failure */
|
||||||
|
}
|
||||||
|
|
||||||
switch (entry) { /* decode IR<3:0> */
|
switch (entry) { /* decode IR<3:0> */
|
||||||
|
|
||||||
|
|
|
@ -26,6 +26,7 @@
|
||||||
|
|
||||||
CPU5 RTE-6/VM and RTE-IV firmware option instructions
|
CPU5 RTE-6/VM and RTE-IV firmware option instructions
|
||||||
|
|
||||||
|
09-May-12 JDB Separated assignments from conditional expressions
|
||||||
23-Mar-12 JDB Added sign extension for dim count in "cpu_ema_resolve"
|
23-Mar-12 JDB Added sign extension for dim count in "cpu_ema_resolve"
|
||||||
28-Dec-11 JDB Eliminated unused variable in "cpu_ema_vset"
|
28-Dec-11 JDB Eliminated unused variable in "cpu_ema_vset"
|
||||||
11-Sep-08 JDB Moved microcode function prototypes to hp2100_cpu1.h
|
11-Sep-08 JDB Moved microcode function prototypes to hp2100_cpu1.h
|
||||||
|
@ -649,9 +650,11 @@ t_bool debug = DEBUG_PRI (cpu_dev, DEB_VMA);
|
||||||
entry = IR & 017; /* mask to entry point */
|
entry = IR & 017; /* mask to entry point */
|
||||||
pattern = op_vma[entry]; /* get operand pattern */
|
pattern = op_vma[entry]; /* get operand pattern */
|
||||||
|
|
||||||
if (pattern != OP_N)
|
if (pattern != OP_N) {
|
||||||
if ((reason = cpu_ops (pattern, op, intrq))) /* get instruction operands */
|
reason = cpu_ops (pattern, op, intrq); /* get instruction operands */
|
||||||
return reason;
|
if (reason != SCPE_OK) /* evaluation failed? */
|
||||||
|
return reason; /* return reason for failure */
|
||||||
|
}
|
||||||
|
|
||||||
if (debug) { /* debugging? */
|
if (debug) { /* debugging? */
|
||||||
fprintf (sim_deb, ">>CPU VMA: IR = %06o (", IR); /* print preamble and IR */
|
fprintf (sim_deb, ">>CPU VMA: IR = %06o (", IR); /* print preamble and IR */
|
||||||
|
@ -1360,9 +1363,11 @@ t_bool debug = DEBUG_PRI (cpu_dev, DEB_EMA);
|
||||||
entry = IR & 017; /* mask to entry point */
|
entry = IR & 017; /* mask to entry point */
|
||||||
pattern = op_ema[entry]; /* get operand pattern */
|
pattern = op_ema[entry]; /* get operand pattern */
|
||||||
|
|
||||||
if (pattern != OP_N)
|
if (pattern != OP_N) {
|
||||||
if ((reason = cpu_ops (pattern, op, intrq))) /* get instruction operands */
|
reason = cpu_ops (pattern, op, intrq); /* get instruction operands */
|
||||||
return reason;
|
if (reason != SCPE_OK) /* evaluation failed? */
|
||||||
|
return reason; /* return reason for failure */
|
||||||
|
}
|
||||||
|
|
||||||
if (debug) { /* debugging? */
|
if (debug) { /* debugging? */
|
||||||
fprintf (sim_deb, ">>CPU EMA: PC = %06o, IR = %06o (", err_PC,IR); /* print preamble and IR */
|
fprintf (sim_deb, ">>CPU EMA: PC = %06o, IR = %06o (", err_PC,IR); /* print preamble and IR */
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
/* hp2100_cpu6.c: HP 1000 RTE-6/VM OS instructions
|
/* hp2100_cpu6.c: HP 1000 RTE-6/VM OS instructions
|
||||||
|
|
||||||
Copyright (c) 2006-2010, J. David Bryan
|
Copyright (c) 2006-2012, J. David Bryan
|
||||||
|
|
||||||
Permission is hereby granted, free of charge, to any person obtaining a
|
Permission is hereby granted, free of charge, to any person obtaining a
|
||||||
copy of this software and associated documentation files (the "Software"),
|
copy of this software and associated documentation files (the "Software"),
|
||||||
|
@ -25,6 +25,7 @@
|
||||||
|
|
||||||
CPU6 RTE-6/VM OS instructions
|
CPU6 RTE-6/VM OS instructions
|
||||||
|
|
||||||
|
09-May-12 JDB Separated assignments from conditional expressions
|
||||||
29-Oct-10 JDB DMA channels renamed from 0,1 to 1,2 to match documentation
|
29-Oct-10 JDB DMA channels renamed from 0,1 to 1,2 to match documentation
|
||||||
18-Sep-08 JDB Corrected .SIP debug formatting
|
18-Sep-08 JDB Corrected .SIP debug formatting
|
||||||
11-Sep-08 JDB Moved microcode function prototypes to hp2100_cpu1.h
|
11-Sep-08 JDB Moved microcode function prototypes to hp2100_cpu1.h
|
||||||
|
@ -393,11 +394,14 @@ static t_bool tbg_tick = FALSE; /* set if processing TBG
|
||||||
entry = IR & 017; /* mask to entry point */
|
entry = IR & 017; /* mask to entry point */
|
||||||
pattern = op_os[entry]; /* get operand pattern */
|
pattern = op_os[entry]; /* get operand pattern */
|
||||||
|
|
||||||
if (pattern != OP_N)
|
if (pattern != OP_N) {
|
||||||
if ((reason = cpu_ops (pattern, op, intrq))) /* get instruction operands */
|
reason = cpu_ops (pattern, op, intrq); /* get instruction operands */
|
||||||
return reason;
|
|
||||||
|
|
||||||
tbg_tick = tbg_tick || ((IR == 0105357) && iotrap); /* set TBG interrupting flag */
|
if (reason != SCPE_OK) /* evaluation failed? */
|
||||||
|
return reason; /* return reason for failure */
|
||||||
|
}
|
||||||
|
|
||||||
|
tbg_tick = tbg_tick || (IR == 0105357) && iotrap; /* set TBG interrupting flag */
|
||||||
|
|
||||||
debug_print = (DEBUG_PRI (cpu_dev, DEB_OS) && !tbg_tick) ||
|
debug_print = (DEBUG_PRI (cpu_dev, DEB_OS) && !tbg_tick) ||
|
||||||
(DEBUG_PRI (cpu_dev, DEB_OSTBG) && tbg_tick);
|
(DEBUG_PRI (cpu_dev, DEB_OSTBG) && tbg_tick);
|
||||||
|
@ -544,7 +548,9 @@ switch (entry) { /* decode IR<3:0> */
|
||||||
for (i = 0; i < count; i++) {
|
for (i = 0; i < count; i++) {
|
||||||
ma = ReadW (PC); /* get operand address */
|
ma = ReadW (PC); /* get operand address */
|
||||||
|
|
||||||
if ((reason = resolve (ma, &ma, intrq))) { /* resolve indirect */
|
reason = resolve (ma, &ma, intrq); /* resolve indirect */
|
||||||
|
|
||||||
|
if (reason != SCPE_OK) { /* resolution failed? */
|
||||||
PC = err_PC; /* IRQ restarts instruction */
|
PC = err_PC; /* IRQ restarts instruction */
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
@ -620,8 +626,8 @@ switch (entry) { /* decode IR<3:0> */
|
||||||
while ((AR != 0) && ((AR & SIGN) == 0)) { /* end of list or bad list? */
|
while ((AR != 0) && ((AR & SIGN) == 0)) { /* end of list or bad list? */
|
||||||
key = ReadW ((AR + op[1].word) & VAMASK); /* get key value */
|
key = ReadW ((AR + op[1].word) & VAMASK); /* get key value */
|
||||||
|
|
||||||
if (((E == 0) && (key == op[0].word)) || /* for E = 0, key = arg? */
|
if ((E == 0) && (key == op[0].word) || /* for E = 0, key = arg? */
|
||||||
((E != 0) && (key > op[0].word))) /* for E = 1, key > arg? */
|
(E != 0) && (key > op[0].word)) /* for E = 1, key > arg? */
|
||||||
break; /* search is done */
|
break; /* search is done */
|
||||||
|
|
||||||
BR = AR; /* B = last link */
|
BR = AR; /* B = last link */
|
||||||
|
@ -710,7 +716,9 @@ switch (entry) { /* decode IR<3:0> */
|
||||||
ma = ReadW (sa); /* get addr of actual */
|
ma = ReadW (sa); /* get addr of actual */
|
||||||
sa = (sa + 1) & VAMASK; /* increment address */
|
sa = (sa + 1) & VAMASK; /* increment address */
|
||||||
|
|
||||||
if ((reason = resolve (ma, &ma, intrq))) { /* resolve indirect */
|
reason = resolve (ma, &ma, intrq); /* resolve indirect */
|
||||||
|
|
||||||
|
if (reason != SCPE_OK) { /* resolution failed? */
|
||||||
PC = err_PC; /* irq restarts instruction */
|
PC = err_PC; /* irq restarts instruction */
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
|
|
@ -26,6 +26,7 @@
|
||||||
|
|
||||||
CPU7 Vector Instruction Set and SIGNAL firmware
|
CPU7 Vector Instruction Set and SIGNAL firmware
|
||||||
|
|
||||||
|
09-May-12 JDB Separated assignments from conditional expressions
|
||||||
06-Feb-12 JDB Corrected "opsize" parameter type in vis_abs
|
06-Feb-12 JDB Corrected "opsize" parameter type in vis_abs
|
||||||
11-Sep-08 JDB Moved microcode function prototypes to hp2100_cpu1.h
|
11-Sep-08 JDB Moved microcode function prototypes to hp2100_cpu1.h
|
||||||
05-Sep-08 JDB Removed option-present tests (now in UIG dispatchers)
|
05-Sep-08 JDB Removed option-present tests (now in UIG dispatchers)
|
||||||
|
@ -385,14 +386,16 @@ if (entry==0) { /* retrieve sub opcode
|
||||||
pattern = (subcode & 0400) ? OP_AAKAKK : OP_AKAKAKK; /* scalar or vector operation */
|
pattern = (subcode & 0400) ? OP_AAKAKK : OP_AKAKAKK; /* scalar or vector operation */
|
||||||
}
|
}
|
||||||
|
|
||||||
if (pattern != OP_N)
|
if (pattern != OP_N) {
|
||||||
if (op_ftnret[entry]) { /* most VIS instrs ignore RTN addr */
|
if (op_ftnret[entry]) { /* most VIS instrs ignore RTN addr */
|
||||||
ret = ReadOp(PC, in_s);
|
ret = ReadOp(PC, in_s);
|
||||||
rtn = rtn1 = ret.word; /* but save it just in case */
|
rtn = rtn1 = ret.word; /* but save it just in case */
|
||||||
PC = (PC + 1) & VAMASK; /* move to next argument */
|
PC = (PC + 1) & VAMASK; /* move to next argument */
|
||||||
}
|
}
|
||||||
if ((reason = cpu_ops (pattern, op, intrq))) /* get instruction operands */
|
reason = cpu_ops (pattern, op, intrq); /* get instruction operands */
|
||||||
return reason;
|
if (reason != SCPE_OK) /* evaluation failed? */
|
||||||
|
return reason; /* return reason for failure */
|
||||||
|
}
|
||||||
|
|
||||||
if (debug) { /* debugging? */
|
if (debug) { /* debugging? */
|
||||||
fprintf (sim_deb, ">>CPU VIS: IR = %06o/%06o (", /* print preamble and IR */
|
fprintf (sim_deb, ">>CPU VIS: IR = %06o/%06o (", /* print preamble and IR */
|
||||||
|
@ -652,9 +655,11 @@ t_bool debug = DEBUG_PRI (cpu_dev, DEB_SIG);
|
||||||
|
|
||||||
entry = IR & 017; /* mask to entry point */
|
entry = IR & 017; /* mask to entry point */
|
||||||
|
|
||||||
if (op_signal[entry] != OP_N)
|
if (op_signal [entry] != OP_N) {
|
||||||
if ((reason = cpu_ops (op_signal[entry], op, intrq)))/* get instruction operands */
|
reason = cpu_ops (op_signal [entry], op, intrq); /* get instruction operands */
|
||||||
return reason;
|
if (reason != SCPE_OK) /* evaluation failed? */
|
||||||
|
return reason; /* return reason for failure */
|
||||||
|
}
|
||||||
|
|
||||||
if (debug) { /* debugging? */
|
if (debug) { /* debugging? */
|
||||||
fprintf (sim_deb, ">>CPU SIG: IR = %06o (", IR); /* print preamble and IR */
|
fprintf (sim_deb, ">>CPU SIG: IR = %06o (", IR); /* print preamble and IR */
|
||||||
|
|
|
@ -23,6 +23,7 @@
|
||||||
be used in advertising or otherwise to promote the sale, use or other dealings
|
be used in advertising or otherwise to promote the sale, use or other dealings
|
||||||
in this Software without prior written authorization from Robert M Supnik.
|
in this Software without prior written authorization from Robert M Supnik.
|
||||||
|
|
||||||
|
09-May-12 JDB Added pragmas to suppress logical operator precedence warnings
|
||||||
10-Feb-12 JDB Added hp_setsc, hp_showsc functions to support SC modifier
|
10-Feb-12 JDB Added hp_setsc, hp_showsc functions to support SC modifier
|
||||||
28-Mar-11 JDB Tidied up signal handling
|
28-Mar-11 JDB Tidied up signal handling
|
||||||
29-Oct-10 JDB DMA channels renamed from 0,1 to 1,2 to match documentation
|
29-Oct-10 JDB DMA channels renamed from 0,1 to 1,2 to match documentation
|
||||||
|
@ -72,6 +73,14 @@
|
||||||
#include "sim_defs.h" /* simulator defns */
|
#include "sim_defs.h" /* simulator defns */
|
||||||
|
|
||||||
|
|
||||||
|
/* Required to quell Mark's Mystery Compiler's precedence warnings */
|
||||||
|
|
||||||
|
#if defined (__GNUC__)
|
||||||
|
#pragma GCC diagnostic ignored "-Wunknown-pragmas"
|
||||||
|
#pragma GCC diagnostic ignored "-Wlogical-op-parentheses"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
/* Simulator stop and notification codes */
|
/* Simulator stop and notification codes */
|
||||||
|
|
||||||
#define STOP_RSRV 1 /* must be 1 */
|
#define STOP_RSRV 1 /* must be 1 */
|
||||||
|
|
|
@ -1466,10 +1466,10 @@ if (assert != deny) /* was there any change
|
||||||
|
|
||||||
previous_state = di_card->srq; /* save the current SRQ state */
|
previous_state = di_card->srq; /* save the current SRQ state */
|
||||||
|
|
||||||
if (((di_card->cntl_register & CNTL_LSTN) && /* if the card is a listener */
|
if (di_card->cntl_register & CNTL_LSTN /* if the card is a listener */
|
||||||
(di_card->status_register & STAT_IRL)) || /* and the input register is loaded, */
|
&& di_card->status_register & STAT_IRL /* and the input register is loaded, */
|
||||||
((di_card->cntl_register & CNTL_TALK) && /* or the card is a talker */
|
|| di_card->cntl_register & CNTL_TALK /* or the card is a talker */
|
||||||
! FIFO_FULL)) /* and the FIFO is not full */
|
&& ! FIFO_FULL) /* and the FIFO is not full */
|
||||||
di_card->srq = SET; /* then request a DCPC cycle */
|
di_card->srq = SET; /* then request a DCPC cycle */
|
||||||
else
|
else
|
||||||
di_card->srq = CLEAR; /* otherwise, DCPC service is not needed */
|
di_card->srq = CLEAR; /* otherwise, DCPC service is not needed */
|
||||||
|
@ -1481,21 +1481,21 @@ if (DEBUG_PRJ (dptrs [card], DEB_CMDS)
|
||||||
dptrs [card]->name, di_card->srq == SET ? "set" : "cleared");
|
dptrs [card]->name, di_card->srq == SET ? "set" : "cleared");
|
||||||
|
|
||||||
|
|
||||||
if (((di_card->status_register & STAT_IRL) && /* is the input register loaded */
|
if (di_card->status_register & STAT_IRL /* is the input register loaded */
|
||||||
(di_card->cntl_register & CNTL_IRL)) || /* and notification is wanted? */
|
&& di_card->cntl_register & CNTL_IRL /* and notification is wanted? */
|
||||||
((di_card->status_register & STAT_LBO) && /* or is the last byte out */
|
|| di_card->status_register & STAT_LBO /* or is the last byte out */
|
||||||
(di_card->cntl_register & CNTL_LBO)) || /* and notification is wanted? */
|
&& di_card->cntl_register & CNTL_LBO /* and notification is wanted? */
|
||||||
((di_card->eor == SET) && /* or was the end of record seen */
|
|| di_card->eor == SET /* or was the end of record seen */
|
||||||
!(di_card->status_register & STAT_IRL)) || /* and the input register was unloaded? */
|
&& !(di_card->status_register & STAT_IRL) /* and the input register was unloaded? */
|
||||||
((di_card->bus_cntl & BUS_SRQ) && /* or is SRQ asserted on the bus */
|
|| di_card->bus_cntl & BUS_SRQ /* or is SRQ asserted on the bus */
|
||||||
(di_card->cntl_register & CNTL_SRQ) && /* and notification is wanted */
|
&& di_card->cntl_register & CNTL_SRQ /* and notification is wanted */
|
||||||
(di_card->cntl_register & CNTL_CIC)) || /* and the card is not controller? */
|
&& di_card->cntl_register & CNTL_CIC /* and the card is not controller? */
|
||||||
(!SW8_SYSCTL && /* or is the card not the system controller */
|
|| !SW8_SYSCTL /* or is the card not the system controller */
|
||||||
(di_card->bus_cntl & BUS_REN) && /* and REN is asserted on the bus */
|
&& di_card->bus_cntl & BUS_REN /* and REN is asserted on the bus */
|
||||||
(di_card->cntl_register & CNTL_REN)) || /* and notification is wanted? */
|
&& di_card->cntl_register & CNTL_REN /* and notification is wanted? */
|
||||||
(!SW8_SYSCTL && /* or is the card not the system controller */
|
|| !SW8_SYSCTL /* or is the card not the system controller */
|
||||||
(di_card->status_register & STAT_IFC) && /* and IFC is asserted on the bus */
|
&& di_card->status_register & STAT_IFC /* and IFC is asserted on the bus */
|
||||||
(di_card->cntl_register & CNTL_IFC))) { /* and notification is wanted? */
|
&& di_card->cntl_register & CNTL_IFC) { /* and notification is wanted? */
|
||||||
|
|
||||||
if (DEBUG_PRJ (dptrs [card], DEB_CMDS))
|
if (DEBUG_PRJ (dptrs [card], DEB_CMDS))
|
||||||
fprintf (sim_deb, ">>%s cmds: Flag set\n",
|
fprintf (sim_deb, ">>%s cmds: Flag set\n",
|
||||||
|
|
|
@ -25,6 +25,7 @@
|
||||||
|
|
||||||
DA 12821A Disc Interface with Amigo disc drives
|
DA 12821A Disc Interface with Amigo disc drives
|
||||||
|
|
||||||
|
07-May-12 JDB Cancel the intersector delay if an untalk is received
|
||||||
29-Mar-12 JDB First release
|
29-Mar-12 JDB First release
|
||||||
04-Nov-11 JDB Created DA device
|
04-Nov-11 JDB Created DA device
|
||||||
|
|
||||||
|
@ -1594,10 +1595,10 @@ if (di [da].bus_cntl & BUS_ATN) { /* is it a bus comma
|
||||||
da_unit [unit].wait = icd_cntlr [unit].cmd_time; /* these are always scheduled and */
|
da_unit [unit].wait = icd_cntlr [unit].cmd_time; /* these are always scheduled and */
|
||||||
initiated = TRUE; /* logged as initiated */
|
initiated = TRUE; /* logged as initiated */
|
||||||
|
|
||||||
if (((if_state [unit] == read_wait) && /* if we're waiting for a send data secondary */
|
if (if_state [unit] == read_wait /* if we're waiting for a send data secondary */
|
||||||
(message_address != 0x00)) || /* but it's not there */
|
&& message_address != 0x00 /* but it's not there */
|
||||||
((if_state [unit] == status_wait) && /* or a send status secondary, */
|
|| if_state [unit] == status_wait /* or a send status secondary, */
|
||||||
(message_address != 0x08))) /* but it's not there */
|
&& message_address != 0x08) /* but it's not there */
|
||||||
abort_command (unit, io_program_error, /* then abort the pending command */
|
abort_command (unit, io_program_error, /* then abort the pending command */
|
||||||
idle); /* and process the new command */
|
idle); /* and process the new command */
|
||||||
|
|
||||||
|
@ -1962,6 +1963,11 @@ return;
|
||||||
|
|
||||||
2. There is no need to test if we are processing a disc command, as the
|
2. There is no need to test if we are processing a disc command, as the
|
||||||
controller would not be busy otherwise.
|
controller would not be busy otherwise.
|
||||||
|
|
||||||
|
3. If an auto-seek will be needed to continue the read, but the seek will
|
||||||
|
fail, then an extra delay is inserted before the service call to start
|
||||||
|
the next sector. Once an Untalk is received, this delay is no longer
|
||||||
|
needed, so it is cancelled before rescheduling the service routine.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
static void complete_read (uint32 unit)
|
static void complete_read (uint32 unit)
|
||||||
|
@ -1974,7 +1980,9 @@ if ((if_state [unit] == command_exec /* is a command exec
|
||||||
|
|
||||||
if_state [unit] = command_exec; /* set to execute */
|
if_state [unit] = command_exec; /* set to execute */
|
||||||
da_unit [unit].PHASE = end_phase; /* the completion phase */
|
da_unit [unit].PHASE = end_phase; /* the completion phase */
|
||||||
da_unit [unit].wait = icd_cntlr [unit].data_time; /* ensure that the controller will finish */
|
|
||||||
|
sim_cancel (&da_unit [unit]); /* cancel the EOT delay */
|
||||||
|
da_unit [unit].wait = icd_cntlr [unit].data_time; /* reschedule for completion */
|
||||||
}
|
}
|
||||||
|
|
||||||
return;
|
return;
|
||||||
|
|
|
@ -26,6 +26,7 @@
|
||||||
DP 12557A 2871 disk subsystem
|
DP 12557A 2871 disk subsystem
|
||||||
13210A 7900 disk subsystem
|
13210A 7900 disk subsystem
|
||||||
|
|
||||||
|
09-May-12 JDB Separated assignments from conditional expressions
|
||||||
10-Feb-12 JDB Deprecated DEVNO in favor of SC
|
10-Feb-12 JDB Deprecated DEVNO in favor of SC
|
||||||
Added CNTLR_TYPE cast to dp_settype
|
Added CNTLR_TYPE cast to dp_settype
|
||||||
28-Mar-11 JDB Tidied up signal handling
|
28-Mar-11 JDB Tidied up signal handling
|
||||||
|
@ -190,7 +191,7 @@
|
||||||
#define STA_PROT 0002000 /* protected (13210) */
|
#define STA_PROT 0002000 /* protected (13210) */
|
||||||
#define STA_SKI 0001000 /* incomplete NI (u) */
|
#define STA_SKI 0001000 /* incomplete NI (u) */
|
||||||
#define STA_SKE 0000400 /* seek error */
|
#define STA_SKE 0000400 /* seek error */
|
||||||
/* 0000200 *//* unused */
|
/* 0000200 (unused) */
|
||||||
#define STA_NRDY 0000100 /* not ready (d) */
|
#define STA_NRDY 0000100 /* not ready (d) */
|
||||||
#define STA_EOC 0000040 /* end of cylinder */
|
#define STA_EOC 0000040 /* end of cylinder */
|
||||||
#define STA_AER 0000020 /* addr error */
|
#define STA_AER 0000020 /* addr error */
|
||||||
|
@ -694,7 +695,8 @@ void dp_goc (int32 fnc, int32 drv, int32 time)
|
||||||
{
|
{
|
||||||
int32 t;
|
int32 t;
|
||||||
|
|
||||||
if ((t = sim_is_active (&dpc_unit[drv]))) { /* still seeking? */
|
t = sim_is_active (&dpc_unit[drv]);
|
||||||
|
if (t) { /* still seeking? */
|
||||||
sim_cancel (&dpc_unit[drv]); /* stop seek */
|
sim_cancel (&dpc_unit[drv]); /* stop seek */
|
||||||
dpc_sta[drv] = dpc_sta[drv] & ~STA_BSY; /* clear busy */
|
dpc_sta[drv] = dpc_sta[drv] & ~STA_BSY; /* clear busy */
|
||||||
time = time + t; /* include seek time */
|
time = time + t; /* include seek time */
|
||||||
|
@ -906,10 +908,13 @@ switch (uptr->FNC) { /* case function */
|
||||||
dpc_rarh = dpc_rarh ^ 1; /* incr head */
|
dpc_rarh = dpc_rarh ^ 1; /* incr head */
|
||||||
dpc_eoc = ((dpc_rarh & 1) == 0); /* calc eoc */
|
dpc_eoc = ((dpc_rarh & 1) == 0); /* calc eoc */
|
||||||
}
|
}
|
||||||
if ((err = fseek (uptr->fileref, da * sizeof (int16),
|
err = fseek (uptr->fileref, da * sizeof (int16), SEEK_SET);
|
||||||
SEEK_SET))) break;
|
if (err) /* error? */
|
||||||
|
break;
|
||||||
fxread (dpxb, sizeof (int16), DP_NUMWD, uptr->fileref);
|
fxread (dpxb, sizeof (int16), DP_NUMWD, uptr->fileref);
|
||||||
if ((err = ferror (uptr->fileref))) break;
|
err = ferror (uptr->fileref);
|
||||||
|
if (err) /* error? */
|
||||||
|
break;
|
||||||
}
|
}
|
||||||
dpd_ibuf = dpxb[dp_ptr++]; /* get word */
|
dpd_ibuf = dpxb[dp_ptr++]; /* get word */
|
||||||
if (dp_ptr >= DP_NUMWD) { /* end of sector? */
|
if (dp_ptr >= DP_NUMWD) { /* end of sector? */
|
||||||
|
@ -953,10 +958,13 @@ switch (uptr->FNC) { /* case function */
|
||||||
dpc_rarh = dpc_rarh ^ 1; /* incr head */
|
dpc_rarh = dpc_rarh ^ 1; /* incr head */
|
||||||
dpc_eoc = ((dpc_rarh & 1) == 0); /* calc eoc */
|
dpc_eoc = ((dpc_rarh & 1) == 0); /* calc eoc */
|
||||||
}
|
}
|
||||||
if ((err = fseek (uptr->fileref, da * sizeof (int16),
|
err = fseek (uptr->fileref, da * sizeof (int16), SEEK_SET);
|
||||||
SEEK_SET))) break;
|
if (err) /* error? */
|
||||||
|
break;
|
||||||
fxwrite (dpxb, sizeof (int16), DP_NUMWD, uptr->fileref);
|
fxwrite (dpxb, sizeof (int16), DP_NUMWD, uptr->fileref);
|
||||||
if ((err = ferror (uptr->fileref))) break; /* error? */
|
err = ferror (uptr->fileref);
|
||||||
|
if (err) /* error? */
|
||||||
|
break;
|
||||||
dp_ptr = 0; /* next sector */
|
dp_ptr = 0; /* next sector */
|
||||||
}
|
}
|
||||||
if (dpd.command && dpd_xfer) /* dch on, xfer? */
|
if (dpd.command && dpd_xfer) /* dch on, xfer? */
|
||||||
|
|
|
@ -26,6 +26,7 @@
|
||||||
|
|
||||||
DQ 12565A 2883 disk system
|
DQ 12565A 2883 disk system
|
||||||
|
|
||||||
|
09-May-12 JDB Separated assignments from conditional expressions
|
||||||
10-Feb-12 JDB Deprecated DEVNO in favor of SC
|
10-Feb-12 JDB Deprecated DEVNO in favor of SC
|
||||||
28-Mar-11 JDB Tidied up signal handling
|
28-Mar-11 JDB Tidied up signal handling
|
||||||
26-Oct-10 JDB Changed I/O signal handler for revised signal model
|
26-Oct-10 JDB Changed I/O signal handler for revised signal model
|
||||||
|
@ -100,7 +101,7 @@
|
||||||
#define CW_V_FNC 12 /* function */
|
#define CW_V_FNC 12 /* function */
|
||||||
#define CW_M_FNC 017
|
#define CW_M_FNC 017
|
||||||
#define CW_GETFNC(x) (((x) >> CW_V_FNC) & CW_M_FNC)
|
#define CW_GETFNC(x) (((x) >> CW_V_FNC) & CW_M_FNC)
|
||||||
/* 000 *//* unused */
|
/* 000 (unused) */
|
||||||
#define FNC_STA 001 /* status check */
|
#define FNC_STA 001 /* status check */
|
||||||
#define FNC_RCL 002 /* recalibrate */
|
#define FNC_RCL 002 /* recalibrate */
|
||||||
#define FNC_SEEK 003 /* seek */
|
#define FNC_SEEK 003 /* seek */
|
||||||
|
@ -530,7 +531,9 @@ void dq_goc (int32 fnc, int32 drv, int32 time)
|
||||||
{
|
{
|
||||||
int32 t;
|
int32 t;
|
||||||
|
|
||||||
if ((t = sim_is_active (&dqc_unit[drv]))) { /* still seeking? */
|
t = sim_is_active (&dqc_unit[drv]);
|
||||||
|
|
||||||
|
if (t) { /* still seeking? */
|
||||||
sim_cancel (&dqc_unit[drv]); /* cancel */
|
sim_cancel (&dqc_unit[drv]); /* cancel */
|
||||||
time = time + t; /* include seek time */
|
time = time + t; /* include seek time */
|
||||||
}
|
}
|
||||||
|
@ -740,10 +743,13 @@ switch (uptr->FNC) { /* case function */
|
||||||
dqc_rars = (dqc_rars + 1) % DQ_NUMSC; /* incr sector */
|
dqc_rars = (dqc_rars + 1) % DQ_NUMSC; /* incr sector */
|
||||||
if (dqc_rars == 0) /* wrap? incr head */
|
if (dqc_rars == 0) /* wrap? incr head */
|
||||||
dqc_uhed[drv] = dqc_rarh = dqc_rarh + 1;
|
dqc_uhed[drv] = dqc_rarh = dqc_rarh + 1;
|
||||||
if ((err = fseek (uptr->fileref, da * sizeof (int16),
|
err = fseek (uptr->fileref, da * sizeof (int16), SEEK_SET);
|
||||||
SEEK_SET))) break;
|
if (err)
|
||||||
|
break;
|
||||||
fxread (dqxb, sizeof (int16), DQ_NUMWD, uptr->fileref);
|
fxread (dqxb, sizeof (int16), DQ_NUMWD, uptr->fileref);
|
||||||
if ((err = ferror (uptr->fileref))) break;
|
err = ferror (uptr->fileref);
|
||||||
|
if (err)
|
||||||
|
break;
|
||||||
}
|
}
|
||||||
dqd_ibuf = dqxb[dq_ptr++]; /* get word */
|
dqd_ibuf = dqxb[dq_ptr++]; /* get word */
|
||||||
if (dq_ptr >= DQ_NUMWD) { /* end of sector? */
|
if (dq_ptr >= DQ_NUMWD) { /* end of sector? */
|
||||||
|
@ -786,10 +792,13 @@ switch (uptr->FNC) { /* case function */
|
||||||
dqc_rars = (dqc_rars + 1) % DQ_NUMSC; /* incr sector */
|
dqc_rars = (dqc_rars + 1) % DQ_NUMSC; /* incr sector */
|
||||||
if (dqc_rars == 0) /* wrap? incr head */
|
if (dqc_rars == 0) /* wrap? incr head */
|
||||||
dqc_uhed[drv] = dqc_rarh = dqc_rarh + 1;
|
dqc_uhed[drv] = dqc_rarh = dqc_rarh + 1;
|
||||||
if ((err = fseek (uptr->fileref, da * sizeof (int16),
|
err = fseek (uptr->fileref, da * sizeof (int16), SEEK_SET);
|
||||||
SEEK_SET))) return TRUE;
|
if (err)
|
||||||
|
break;
|
||||||
fxwrite (dqxb, sizeof (int16), DQ_NUMWD, uptr->fileref);
|
fxwrite (dqxb, sizeof (int16), DQ_NUMWD, uptr->fileref);
|
||||||
if ((err = ferror (uptr->fileref))) break;
|
err = ferror (uptr->fileref);
|
||||||
|
if (err)
|
||||||
|
break;
|
||||||
dq_ptr = 0;
|
dq_ptr = 0;
|
||||||
}
|
}
|
||||||
if (dqd.command && dqd_xfer) { /* dch on, xfer? */
|
if (dqd.command && dqd_xfer) { /* dch on, xfer? */
|
||||||
|
|
|
@ -25,6 +25,7 @@
|
||||||
|
|
||||||
IPLI, IPLO 12875A interprocessor link
|
IPLI, IPLO 12875A interprocessor link
|
||||||
|
|
||||||
|
09-May-12 JDB Separated assignments from conditional expressions
|
||||||
10-Feb-12 JDB Deprecated DEVNO in favor of SC
|
10-Feb-12 JDB Deprecated DEVNO in favor of SC
|
||||||
Added CARD_INDEX casts to dib.card_index
|
Added CARD_INDEX casts to dib.card_index
|
||||||
07-Apr-11 JDB A failed STC may now be retried
|
07-Apr-11 JDB A failed STC may now be retried
|
||||||
|
@ -623,7 +624,8 @@ uptr->filename = tptr; /* save */
|
||||||
sim_activate (uptr, POLL_FIRST); /* activate first poll "immediately" */
|
sim_activate (uptr, POLL_FIRST); /* activate first poll "immediately" */
|
||||||
if (sim_switches & SWMASK ('W')) { /* wait? */
|
if (sim_switches & SWMASK ('W')) { /* wait? */
|
||||||
for (i = 0; i < 30; i++) { /* check for 30 sec */
|
for (i = 0; i < 30; i++) { /* check for 30 sec */
|
||||||
if ((t = ipl_check_conn (uptr))) /* established? */
|
t = ipl_check_conn (uptr);
|
||||||
|
if (t) /* established? */
|
||||||
break;
|
break;
|
||||||
if ((i % 10) == 0) /* status every 10 sec */
|
if ((i % 10) == 0) /* status every 10 sec */
|
||||||
printf ("Waiting for connnection\n");
|
printf ("Waiting for connnection\n");
|
||||||
|
|
|
@ -1926,8 +1926,8 @@ if (fast_binary_read) { /* fast binary read
|
||||||
else { /* normal service */
|
else { /* normal service */
|
||||||
tmxr_poll_tx (&mpx_desc); /* output any accumulated characters */
|
tmxr_poll_tx (&mpx_desc); /* output any accumulated characters */
|
||||||
|
|
||||||
if (((buf_avail (iowrite, port) < 2) && /* more to transmit? */
|
if ((buf_avail (iowrite, port) < 2) && /* more to transmit? */
|
||||||
!(mpx_flags [port] & (FL_WAITACK | FL_XOFF))) || /* and transmission not suspended */
|
!(mpx_flags [port] & (FL_WAITACK | FL_XOFF)) || /* and transmission not suspended */
|
||||||
tmxr_rqln (&mpx_ldsc [port])) /* or more to receive? */
|
tmxr_rqln (&mpx_ldsc [port])) /* or more to receive? */
|
||||||
sim_activate (uptr, uptr->wait); /* reschedule service */
|
sim_activate (uptr, uptr->wait); /* reschedule service */
|
||||||
else
|
else
|
||||||
|
|
|
@ -26,6 +26,7 @@
|
||||||
MS 13181A 7970B 800bpi nine track magnetic tape
|
MS 13181A 7970B 800bpi nine track magnetic tape
|
||||||
13183A 7970E 1600bpi nine track magnetic tape
|
13183A 7970E 1600bpi nine track magnetic tape
|
||||||
|
|
||||||
|
09-May-12 JDB Separated assignments from conditional expressions
|
||||||
10-Feb-12 JDB Deprecated DEVNO in favor of SC
|
10-Feb-12 JDB Deprecated DEVNO in favor of SC
|
||||||
Added CNTLR_TYPE cast to ms_settype
|
Added CNTLR_TYPE cast to ms_settype
|
||||||
28-Mar-11 JDB Tidied up signal handling
|
28-Mar-11 JDB Tidied up signal handling
|
||||||
|
@ -737,7 +738,8 @@ switch (uptr->FNC) { /* case on function */
|
||||||
fprintf (sim_deb,
|
fprintf (sim_deb,
|
||||||
">>MSC svc: Unit %d wrote initial gap\n",
|
">>MSC svc: Unit %d wrote initial gap\n",
|
||||||
unum);
|
unum);
|
||||||
if ((st = ms_write_gap (uptr))) { /* write initial gap; error? */
|
st = ms_write_gap (uptr); /* write initial gap*/
|
||||||
|
if (st != MTSE_OK) { /* error? */
|
||||||
r = ms_map_err (uptr, st); /* map error */
|
r = ms_map_err (uptr, st); /* map error */
|
||||||
break; /* terminate operation */
|
break; /* terminate operation */
|
||||||
}
|
}
|
||||||
|
@ -747,13 +749,15 @@ switch (uptr->FNC) { /* case on function */
|
||||||
fprintf (sim_deb,
|
fprintf (sim_deb,
|
||||||
">>MSC svc: Unit %d wrote file mark\n",
|
">>MSC svc: Unit %d wrote file mark\n",
|
||||||
unum);
|
unum);
|
||||||
if ((st = sim_tape_wrtmk (uptr))) /* write tmk, err? */
|
st = sim_tape_wrtmk (uptr); /* write tmk */
|
||||||
|
if (st != MTSE_OK) /* error? */
|
||||||
r = ms_map_err (uptr, st); /* map error */
|
r = ms_map_err (uptr, st); /* map error */
|
||||||
msc_sta = STA_EOF; /* set EOF status */
|
msc_sta = STA_EOF; /* set EOF status */
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case FNC_FSR: /* space forward */
|
case FNC_FSR: /* space forward */
|
||||||
if ((st = sim_tape_sprecf (uptr, &tbc))) /* space rec fwd, err? */
|
st = sim_tape_sprecf (uptr, &tbc); /* space rec fwd */
|
||||||
|
if (st != MTSE_OK) /* error? */
|
||||||
r = ms_map_err (uptr, st); /* map error */
|
r = ms_map_err (uptr, st); /* map error */
|
||||||
if (tbc & 1)
|
if (tbc & 1)
|
||||||
msc_sta = msc_sta | STA_ODD;
|
msc_sta = msc_sta | STA_ODD;
|
||||||
|
@ -761,7 +765,8 @@ switch (uptr->FNC) { /* case on function */
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case FNC_BSR: /* space reverse */
|
case FNC_BSR: /* space reverse */
|
||||||
if ((st = sim_tape_sprecr (uptr, &tbc))) /* space rec rev, err? */
|
st = sim_tape_sprecr (uptr, &tbc); /* space rec rev*/
|
||||||
|
if (st != MTSE_OK) /* error? */
|
||||||
r = ms_map_err (uptr, st); /* map error */
|
r = ms_map_err (uptr, st); /* map error */
|
||||||
if (tbc & 1)
|
if (tbc & 1)
|
||||||
msc_sta = msc_sta | STA_ODD;
|
msc_sta = msc_sta | STA_ODD;
|
||||||
|
@ -831,7 +836,8 @@ switch (uptr->FNC) { /* case on function */
|
||||||
fprintf (sim_deb,
|
fprintf (sim_deb,
|
||||||
">>MSC svc: Unit %d wrote initial gap\n",
|
">>MSC svc: Unit %d wrote initial gap\n",
|
||||||
unum);
|
unum);
|
||||||
if ((st = ms_write_gap (uptr))) { /* write initial gap; error? */
|
st = ms_write_gap (uptr); /* write initial gap */
|
||||||
|
if (st != MTSE_OK) { /* error? */
|
||||||
r = ms_map_err (uptr, st); /* map error */
|
r = ms_map_err (uptr, st); /* map error */
|
||||||
break; /* terminate operation */
|
break; /* terminate operation */
|
||||||
}
|
}
|
||||||
|
@ -855,7 +861,8 @@ switch (uptr->FNC) { /* case on function */
|
||||||
fprintf (sim_deb,
|
fprintf (sim_deb,
|
||||||
">>MSC svc: Unit %d wrote %d word record\n",
|
">>MSC svc: Unit %d wrote %d word record\n",
|
||||||
unum, ms_ptr / 2);
|
unum, ms_ptr / 2);
|
||||||
if ((st = sim_tape_wrrecf (uptr, msxb, ms_ptr))) { /* write, err? */
|
st = sim_tape_wrrecf (uptr, msxb, ms_ptr); /* write */
|
||||||
|
if (st != MTSE_OK) {
|
||||||
r = ms_map_err (uptr, st); /* map error */
|
r = ms_map_err (uptr, st); /* map error */
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
@ -894,7 +901,9 @@ t_stat st;
|
||||||
uint32 gap_len = ms_ctype ? GAP_13183 : GAP_13181; /* establish gap length */
|
uint32 gap_len = ms_ctype ? GAP_13183 : GAP_13181; /* establish gap length */
|
||||||
uint32 tape_bpi = ms_ctype ? BPI_13183 : BPI_13181; /* establish nominal bpi */
|
uint32 tape_bpi = ms_ctype ? BPI_13183 : BPI_13181; /* establish nominal bpi */
|
||||||
|
|
||||||
if ((st = sim_tape_wrgap (uptr, gap_len, tape_bpi))) /* write gap */
|
st = sim_tape_wrgap (uptr, gap_len, tape_bpi); /* write gap */
|
||||||
|
|
||||||
|
if (st != MTSE_OK)
|
||||||
return ms_map_err (uptr, st); /* map error if failure */
|
return ms_map_err (uptr, st); /* map error if failure */
|
||||||
else
|
else
|
||||||
return SCPE_OK;
|
return SCPE_OK;
|
||||||
|
@ -974,7 +983,9 @@ for (i = 0; i < MS_NUMDR; i++) { /* look for write in pro
|
||||||
fprintf (sim_deb,
|
fprintf (sim_deb,
|
||||||
">>MSC rws: Unit %d wrote %d word partial record\n", i, ms_ptr / 2);
|
">>MSC rws: Unit %d wrote %d word partial record\n", i, ms_ptr / 2);
|
||||||
|
|
||||||
if ((st = sim_tape_wrrecf (uptr, msxb, ms_ptr | MTR_ERF)))
|
st = sim_tape_wrrecf (uptr, msxb, ms_ptr | MTR_ERF);
|
||||||
|
|
||||||
|
if (st != MTSE_OK)
|
||||||
ms_map_err (uptr, st); /* discard any error */
|
ms_map_err (uptr, st); /* discard any error */
|
||||||
|
|
||||||
ms_ptr = 0; /* clear partial */
|
ms_ptr = 0; /* clear partial */
|
||||||
|
|
|
@ -25,6 +25,7 @@
|
||||||
|
|
||||||
MT 12559A 3030 nine track magnetic tape
|
MT 12559A 3030 nine track magnetic tape
|
||||||
|
|
||||||
|
09-May-12 JDB Separated assignments from conditional expressions
|
||||||
25-Mar-12 JDB Removed redundant MTAB_VUN from "format" MTAB entry
|
25-Mar-12 JDB Removed redundant MTAB_VUN from "format" MTAB entry
|
||||||
10-Feb-12 JDB Deprecated DEVNO in favor of SC
|
10-Feb-12 JDB Deprecated DEVNO in favor of SC
|
||||||
28-Mar-11 JDB Tidied up signal handling
|
28-Mar-11 JDB Tidied up signal handling
|
||||||
|
@ -495,7 +496,8 @@ switch (mtc_fnc) { /* case on function */
|
||||||
return sim_tape_detach (uptr); /* don't set cch flg */
|
return sim_tape_detach (uptr); /* don't set cch flg */
|
||||||
|
|
||||||
case FNC_WFM: /* write file mark */
|
case FNC_WFM: /* write file mark */
|
||||||
if ((st = sim_tape_wrtmk (uptr))) /* write tmk, err? */
|
st = sim_tape_wrtmk (uptr); /* write tmk */
|
||||||
|
if (st != MTSE_OK) /* error? */
|
||||||
r = mt_map_err (uptr, st); /* map error */
|
r = mt_map_err (uptr, st); /* map error */
|
||||||
mtc_sta = STA_EOF; /* set EOF status */
|
mtc_sta = STA_EOF; /* set EOF status */
|
||||||
break;
|
break;
|
||||||
|
@ -504,12 +506,14 @@ switch (mtc_fnc) { /* case on function */
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case FNC_FSR: /* space forward */
|
case FNC_FSR: /* space forward */
|
||||||
if ((st = sim_tape_sprecf (uptr, &tbc))) /* space rec fwd, err? */
|
st = sim_tape_sprecf (uptr, &tbc); /* space rec fwd */
|
||||||
|
if (st != MTSE_OK) /* error? */
|
||||||
r = mt_map_err (uptr, st); /* map error */
|
r = mt_map_err (uptr, st); /* map error */
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case FNC_BSR: /* space reverse */
|
case FNC_BSR: /* space reverse */
|
||||||
if ((st = sim_tape_sprecr (uptr, &tbc))) /* space rec rev, err? */
|
st = sim_tape_sprecr (uptr, &tbc); /* space rec rev */
|
||||||
|
if (st != MTSE_OK) /* error? */
|
||||||
r = mt_map_err (uptr, st); /* map error */
|
r = mt_map_err (uptr, st); /* map error */
|
||||||
break;
|
break;
|
||||||
|
|
||||||
|
@ -558,7 +562,8 @@ switch (mtc_fnc) { /* case on function */
|
||||||
return SCPE_OK;
|
return SCPE_OK;
|
||||||
}
|
}
|
||||||
if (mt_ptr) { /* write buffer */
|
if (mt_ptr) { /* write buffer */
|
||||||
if ((st = sim_tape_wrrecf (uptr, mtxb, mt_ptr))) { /* write, err? */
|
st = sim_tape_wrrecf (uptr, mtxb, mt_ptr); /* write */
|
||||||
|
if (st != MTSE_OK) { /* error? */
|
||||||
r = mt_map_err (uptr, st); /* map error */
|
r = mt_map_err (uptr, st); /* map error */
|
||||||
break; /* done */
|
break; /* done */
|
||||||
}
|
}
|
||||||
|
@ -627,7 +632,8 @@ t_stat st;
|
||||||
|
|
||||||
if (sim_is_active (&mtc_unit) && /* write in prog? */
|
if (sim_is_active (&mtc_unit) && /* write in prog? */
|
||||||
(mtc_fnc == FNC_WC) && (mt_ptr > 0)) { /* yes, bad rec */
|
(mtc_fnc == FNC_WC) && (mt_ptr > 0)) { /* yes, bad rec */
|
||||||
if ((st = sim_tape_wrrecf (&mtc_unit, mtxb, mt_ptr | MTR_ERF)))
|
st = sim_tape_wrrecf (&mtc_unit, mtxb, mt_ptr | MTR_ERF);
|
||||||
|
if (st != MTSE_OK)
|
||||||
mt_map_err (&mtc_unit, st);
|
mt_map_err (&mtc_unit, st);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -28,6 +28,7 @@
|
||||||
TTY 12531C buffered teleprinter interface
|
TTY 12531C buffered teleprinter interface
|
||||||
CLK 12539C time base generator
|
CLK 12539C time base generator
|
||||||
|
|
||||||
|
09-May-12 JDB Separated assignments from conditional expressions
|
||||||
12-Feb-12 JDB Add TBG as a logical name for the CLK device
|
12-Feb-12 JDB Add TBG as a logical name for the CLK device
|
||||||
10-Feb-12 JDB Deprecated DEVNO in favor of SC
|
10-Feb-12 JDB Deprecated DEVNO in favor of SC
|
||||||
28-Mar-11 JDB Tidied up signal handling
|
28-Mar-11 JDB Tidied up signal handling
|
||||||
|
@ -942,7 +943,9 @@ t_stat r;
|
||||||
if (tty_mode & TM_PRI) { /* printing? */
|
if (tty_mode & TM_PRI) { /* printing? */
|
||||||
c = sim_tt_outcvt (c, TT_GET_MODE (tty_unit[TTO].flags));
|
c = sim_tt_outcvt (c, TT_GET_MODE (tty_unit[TTO].flags));
|
||||||
if (c >= 0) { /* valid? */
|
if (c >= 0) { /* valid? */
|
||||||
if ((r = sim_putchar_s (c))) return r; /* output char */
|
r = sim_putchar_s (c); /* output char */
|
||||||
|
if (r != SCPE_OK)
|
||||||
|
return r;
|
||||||
tty_unit[TTO].pos = tty_unit[TTO].pos + 1;
|
tty_unit[TTO].pos = tty_unit[TTO].pos + 1;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
|
@ -23,6 +23,7 @@
|
||||||
used in advertising or otherwise to promote the sale, use or other dealings
|
used in advertising or otherwise to promote the sale, use or other dealings
|
||||||
in this Software without prior written authorization from Robert M Supnik.
|
in this Software without prior written authorization from Robert M Supnik.
|
||||||
|
|
||||||
|
09-May-12 JDB Quieted warnings for assignments in conditional expressions
|
||||||
10-Feb-12 JDB Deprecated DEVNO in favor of SC
|
10-Feb-12 JDB Deprecated DEVNO in favor of SC
|
||||||
Added hp_setsc, hp_showsc functions to support SC modifier
|
Added hp_setsc, hp_showsc functions to support SC modifier
|
||||||
15-Dec-11 JDB Added DA and dummy DC devices
|
15-Dec-11 JDB Added DA and dummy DC devices
|
||||||
|
|
|
@ -24,7 +24,8 @@
|
||||||
used in advertising or otherwise to promote the sale, use or other dealings
|
used in advertising or otherwise to promote the sale, use or other dealings
|
||||||
in this Software without prior written authorization from the authors.
|
in this Software without prior written authorization from the authors.
|
||||||
|
|
||||||
28-Mar-12 JDB First release
|
07-May-12 JDB Corrected end-of-track delay time logic
|
||||||
|
02-May-12 JDB First release
|
||||||
09-Nov-11 JDB Created disc controller common library from DS simulator
|
09-Nov-11 JDB Created disc controller common library from DS simulator
|
||||||
|
|
||||||
References:
|
References:
|
||||||
|
@ -761,8 +762,8 @@ else { /* for an ICD controller
|
||||||
uptr = units + unit_limit; /* and we use the indicated unit */
|
uptr = units + unit_limit; /* and we use the indicated unit */
|
||||||
}
|
}
|
||||||
|
|
||||||
if ((props->unit_check && !uptr) || /* if the unit number is checked and is invalid */
|
if (props->unit_check && !uptr /* if the unit number is checked and is invalid */
|
||||||
(props->seek_wait && (drive_status (uptr) & DL_S2STOPS))) { /* or if we're waiting for an offline drive */
|
|| props->seek_wait && (drive_status (uptr) & DL_S2STOPS)) { /* or if we're waiting for an offline drive */
|
||||||
dl_end_command (cvptr, status_2_error); /* then the command ends with a Status-2 error */
|
dl_end_command (cvptr, status_2_error); /* then the command ends with a Status-2 error */
|
||||||
uptr = NULL; /* prevent the command from starting */
|
uptr = NULL; /* prevent the command from starting */
|
||||||
}
|
}
|
||||||
|
@ -1817,28 +1818,61 @@ return SCPE_OK; /* the read was successf
|
||||||
|
|
||||||
On entry, the end-of-data flag is checked. If it is set, the current read is
|
On entry, the end-of-data flag is checked. If it is set, the current read is
|
||||||
completed. Otherwise, the command phase is reset to start the next sector,
|
completed. Otherwise, the command phase is reset to start the next sector,
|
||||||
and the disc service is scheduled to allow for the intersector delay.
|
and the disc service is set to allow for the intersector delay.
|
||||||
|
|
||||||
|
|
||||||
Implementation notes:
|
Implementation notes:
|
||||||
|
|
||||||
1. The intersector time is required to allow the ICD interface to set the
|
1. The CPU indicates the end of a read data transfer to an ICD controller by
|
||||||
end-of-data flag before the next sector begins. The CPU must have enough
|
untalking the drive. The untalk is done by the driver as soon as the
|
||||||
time to receive the last byte of the current sector and then unaddress
|
DCPC completion interrupt is processed. However, the time from the final
|
||||||
the disc controller before the first byte of the next sector is sent. If
|
DCPC transfer through driver entry to the point where the untalk is
|
||||||
the time is not long enough, the sector address will be incremented twice
|
asserted on the bus varies from 80 instructions (RTE-6/VM with OS
|
||||||
(e.g., a 128-word read of sector 0 will terminate with sector 2 as the
|
microcode and the buffer in the system map) to 152 instructions (RTE-IVB
|
||||||
next sector instead of sector 1).
|
with the buffer in the user map). The untalk must occur before the start
|
||||||
|
of the next sector, or the drive will begin the data transfer.
|
||||||
|
|
||||||
|
Normally, this is not a problem, as the driver clears the FIFO of any
|
||||||
|
received data after DCPC completion. However, if the read terminates
|
||||||
|
after the last sector of a track, and accessing the next sector would
|
||||||
|
require an intervening seek, and the file mask disables auto-seeking or
|
||||||
|
an enabled seek would move the positioner beyond the drive limits, then
|
||||||
|
the controller will indicate an End of Cylinder error if the untalk does
|
||||||
|
not arrive before the seek is initiated.
|
||||||
|
|
||||||
|
The RTE driver (DVA32) and various utilities that manage the disc
|
||||||
|
directly (e.g., SWTCH) do not appear to account for these bogus errors,
|
||||||
|
so the ICD controller hardware must avoid them in some unknown manner.
|
||||||
|
We work around the issue by extending the intersector delay to allow time
|
||||||
|
for a potential untalk whenever the next access would otherwise fail.
|
||||||
|
|
||||||
|
Note that this issue does not occur with writes because DCPC completion
|
||||||
|
asserts EOI concurrently with the final data byte to terminate the
|
||||||
|
command.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
static void end_read (CVPTR cvptr, UNIT *uptr)
|
static void end_read (CVPTR cvptr, UNIT *uptr)
|
||||||
{
|
{
|
||||||
|
uint32 limit;
|
||||||
|
|
||||||
if (cvptr->eod == SET) /* is the end of data indicated? */
|
if (cvptr->eod == SET) /* is the end of data indicated? */
|
||||||
dl_end_command (cvptr, normal_completion); /* complete the command */
|
dl_end_command (cvptr, normal_completion); /* complete the command */
|
||||||
|
|
||||||
else { /* reading continues */
|
else { /* reading continues */
|
||||||
uptr->PHASE = start_phase; /* reset to the start phase */
|
uptr->PHASE = start_phase; /* reset to the start phase */
|
||||||
uptr->wait = cvptr->sector_time; /* delay for the intersector time */
|
uptr->wait = cvptr->sector_time; /* delay for the intersector time */
|
||||||
|
|
||||||
|
if (cvptr->eoc == SET && cvptr->type == ICD) { /* seek will be required and controller is ICD? */
|
||||||
|
if (!(cvptr->file_mask & DL_FAUTSK)) /* if auto-seek is disabled */
|
||||||
|
limit = cvptr->cylinder; /* then the limit is the current cylinder */
|
||||||
|
else if (cvptr->file_mask & DL_FDECR) /* else if enabled and decremental seek */
|
||||||
|
limit = 0; /* then the limit is cylinder 0 */
|
||||||
|
else /* else the enabled limit is the last cylinder */
|
||||||
|
limit = drive_props [GET_MODEL (uptr->flags)].cylinders;
|
||||||
|
|
||||||
|
if (cvptr->cylinder == limit) /* is positioner at the limit? */
|
||||||
|
uptr->wait = cvptr->eot_time; /* seek will fail; delay to allow CPU to untalk */
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
return;
|
return;
|
||||||
|
@ -1879,8 +1913,8 @@ static void start_write (CVPTR cvptr, UNIT *uptr)
|
||||||
{
|
{
|
||||||
const t_bool verify = (CNTLR_OPCODE) uptr->OP == write; /* only Write verifies the sector address */
|
const t_bool verify = (CNTLR_OPCODE) uptr->OP == write; /* only Write verifies the sector address */
|
||||||
|
|
||||||
if ((uptr->flags & UNIT_WPROT) || /* is the unit write protected, */
|
if ((uptr->flags & UNIT_WPROT) /* is the unit write protected, */
|
||||||
(!verify && !(uptr->flags & UNIT_FMT))) /* or is formatting required but not enabled? */
|
|| !verify && !(uptr->flags & UNIT_FMT)) /* or is formatting required but not enabled? */
|
||||||
dl_end_command (cvptr, status_2_error); /* terminate the write with an error */
|
dl_end_command (cvptr, status_2_error); /* terminate the write with an error */
|
||||||
|
|
||||||
else if (position_sector (cvptr, uptr, verify)) { /* writing is permitted; position the sector */
|
else if (position_sector (cvptr, uptr, verify)) { /* writing is permitted; position the sector */
|
||||||
|
@ -1964,12 +1998,12 @@ return SCPE_OK;
|
||||||
|
|
||||||
/* Position the disc image file at the current sector.
|
/* Position the disc image file at the current sector.
|
||||||
|
|
||||||
The image file is positioned at the byte address corresponding to the
|
The image file is positioned at the byte address corresponding to the drive's
|
||||||
controller's current cylinder, head, and sector address. Positioning may
|
current cylinder and the controller's current head and sector addresses.
|
||||||
involve an auto-seek if a prior read or write addressed the final sector in a
|
Positioning may involve an auto-seek if a prior read or write addressed the
|
||||||
cylinder. If a seek is initiated or an error is detected, the routine
|
final sector of a cylinder. If a seek is initiated or an error is detected,
|
||||||
returns FALSE to indicate that the positioning was not performed. If the
|
the routine returns FALSE to indicate that the positioning was not performed.
|
||||||
file was positioned, the routine returns TRUE.
|
If the file was positioned, the routine returns TRUE.
|
||||||
|
|
||||||
On entry, if the controller's end-of-cylinder flag is set, a prior read or
|
On entry, if the controller's end-of-cylinder flag is set, a prior read or
|
||||||
write addressed the final sector in the current cylinder. If the file mask
|
write addressed the final sector in the current cylinder. If the file mask
|
||||||
|
@ -1983,21 +2017,23 @@ return SCPE_OK;
|
||||||
seek completion and the command state unchanged. When the service is
|
seek completion and the command state unchanged. When the service is
|
||||||
reentered, the read or write will continue on the new cylinder.
|
reentered, the read or write will continue on the new cylinder.
|
||||||
|
|
||||||
If the EOC flag was not set, the drive position is checked against the
|
If the EOC flag was not set, the drive's position is checked against the
|
||||||
controller position. If they are different (as may occur with an Address
|
controller's position if address verification is requested. If they are
|
||||||
Record command that specified a different location than the last Seek
|
different (as may occur with an Address Record command that specified a
|
||||||
command), a seek is started to the correct cylinder, and the routine returns
|
different location than the last Seek command), a seek is started to the
|
||||||
with the disc service scheduled for seek completion as above.
|
correct cylinder, and the routine returns with the disc service scheduled for
|
||||||
|
seek completion as above.
|
||||||
|
|
||||||
If the drive and controller positions agree, the controller CHS address is
|
If the drive and controller positions agree or verification is not requested,
|
||||||
validated against the drive limits. If they are invalid, Seek Check status
|
the CHS addresses are validated against the drive limits. If they are
|
||||||
is set, and the command is terminated with an error.
|
invalid, Seek Check status is set, and the command is terminated with an
|
||||||
|
error.
|
||||||
|
|
||||||
If the address is valid, the drive is checked to ensure that it is ready for
|
If the addresses are valid, the drive is checked to ensure that it is ready
|
||||||
positioning. If it is, the the byte offset in the image file is calculated
|
for positioning. If it is, the the byte offset in the image file is
|
||||||
from the CHS address, and the file is positioned. The disc service is
|
calculated from the CHS address, and the file is positioned. The disc
|
||||||
scheduled to begin the data transfer, and the routine returns TRUE to
|
service is scheduled to begin the data transfer, and the routine returns TRUE
|
||||||
indicate that the file position was set.
|
to indicate that the file position was set.
|
||||||
|
|
||||||
|
|
||||||
Implementation notes:
|
Implementation notes:
|
||||||
|
|
|
@ -24,7 +24,8 @@
|
||||||
used in advertising or otherwise to promote the sale, use or other dealings
|
used in advertising or otherwise to promote the sale, use or other dealings
|
||||||
in this Software without prior written authorization from the authors.
|
in this Software without prior written authorization from the authors.
|
||||||
|
|
||||||
30-Mar-12 JDB First release
|
07-May-12 JDB Added end-of-track delay time as a controller variable
|
||||||
|
02-May-12 JDB First release
|
||||||
09-Nov-11 JDB Created disc controller common library from DS simulator
|
09-Nov-11 JDB Created disc controller common library from DS simulator
|
||||||
|
|
||||||
|
|
||||||
|
@ -53,6 +54,7 @@
|
||||||
|
|
||||||
/* Default controller times */
|
/* Default controller times */
|
||||||
|
|
||||||
|
#define DL_EOT_TIME 160 /* end-of-track delay time */
|
||||||
#define DL_SEEK_TIME 100 /* seek delay time (per cylinder) */
|
#define DL_SEEK_TIME 100 /* seek delay time (per cylinder) */
|
||||||
#define DL_SECTOR_TIME 27 /* intersector delay time */
|
#define DL_SECTOR_TIME 27 /* intersector delay time */
|
||||||
#define DL_CMD_TIME 3 /* command start delay time */
|
#define DL_CMD_TIME 3 /* command start delay time */
|
||||||
|
@ -330,6 +332,7 @@ typedef struct {
|
||||||
uint32 index; /* data buffer current index */
|
uint32 index; /* data buffer current index */
|
||||||
uint32 length; /* data buffer valid length */
|
uint32 length; /* data buffer valid length */
|
||||||
UNIT *aux; /* MAC auxiliary units (controller and timer) */
|
UNIT *aux; /* MAC auxiliary units (controller and timer) */
|
||||||
|
int32 eot_time; /* end-of-track read delay time */
|
||||||
int32 seek_time; /* per-cylinder seek delay time */
|
int32 seek_time; /* per-cylinder seek delay time */
|
||||||
int32 sector_time; /* intersector delay time */
|
int32 sector_time; /* intersector delay time */
|
||||||
int32 cmd_time; /* command response time */
|
int32 cmd_time; /* command response time */
|
||||||
|
@ -354,7 +357,7 @@ typedef CNTLR_VARS *CVPTR; /* pointer to controller
|
||||||
CLEAR, CLEAR, \
|
CLEAR, CLEAR, \
|
||||||
0, 0, 0, 0, 0, 0, 0, 0, \
|
0, 0, 0, 0, 0, 0, 0, 0, \
|
||||||
(bufptr), 0, 0, (auxptr), \
|
(bufptr), 0, 0, (auxptr), \
|
||||||
DL_SEEK_TIME, DL_SECTOR_TIME, \
|
DL_EOT_TIME, DL_SEEK_TIME, DL_SECTOR_TIME, \
|
||||||
DL_CMD_TIME, DL_DATA_TIME, DL_WAIT_TIME
|
DL_CMD_TIME, DL_DATA_TIME, DL_WAIT_TIME
|
||||||
|
|
||||||
|
|
||||||
|
|
Loading…
Add table
Reference in a new issue