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B5500: Fixed Coverity errors, and fixed for current SCP.

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This commit is contained in:
Richard Cornwell 2017-03-12 22:33:06 -04:00
parent 14b9265af3
commit 5efbd203a3
6 changed files with 128 additions and 134 deletions
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9
B5500/b5500_cpu.c
View file

@ -101,7 +101,7 @@
#define UNIT_MSIZE (7 << UNIT_V_MSIZE)
#define MEMAMOUNT(x) (x << UNIT_V_MSIZE)
#define TMR_RTC 1
#define TMR_RTC 0
#define HIST_MAX 5000
#define HIST_MIN 64
@ -700,10 +700,6 @@ int mkint() {
B <<= 3;
exp_b--;
}
if (exp_b != 0) {
B = 0;
return 1;
}
}
if (f && B != 0)
B |= MSIGN;
@ -3855,8 +3851,7 @@ cpu_reset(DEVICE * dptr)
sim_brk_types = sim_brk_dflt = SWMASK('E') | SWMASK('A') | SWMASK('B');
hst_p = 0;
sim_register_clock_unit (&cpu_unit[0]);
sim_rtcn_init (cpu_unit[0].wait, TMR_RTC);
sim_rtcn_init_unit (&cpu_unit[0], cpu_unit[0].wait, TMR_RTC);
sim_activate(&cpu_unit[0], cpu_unit[0].wait) ;
return SCPE_OK;

64
B5500/b5500_defs.h
View file

@ -1,4 +1,4 @@
/* b5500_defs.h: Burroughs 5500 simulator definitions
/* b5500_defs.h: Burroughs 5500 simulator definitions
Copyright (c) 2016, Richard Cornwell
@ -52,18 +52,13 @@ extern uint8 loading; /* System booting flag *
/* Debuging controls */
#define DEBUG_CHAN 0x0000001 /* Show channel fetchs */
#define DEBUG_TRAP 0x0000002 /* Show CPU Traps */
#define DEBUG_CMD 0x0000004 /* Show device commands */
#define DEBUG_DATA 0x0000008 /* Show data transfers */
#define DEBUG_DETAIL 0x0000010 /* Show details */
#define DEBUG_EXP 0x0000020 /* Show error conditions */
#define DEBUG_SNS 0x0000040 /* Shows sense data for 7909 devs */
#define DEBUG_CTSS 0x0000080 /* Shows CTSS specail instructions */
#define DEBUG_PROT 0x0000100 /* Protection traps */
extern DEBTAB dev_debug[];
/* Returns from device commands */
#define SCPE_BUSY (1) /* Device is active */
#define SCPE_NODEV (2) /* No device exists */
@ -77,23 +72,6 @@ typedef struct _opcode
}
t_opcode;
/* I/O Command codes */
#define IO_RDS 1 /* Read record */
#define IO_BSR 2 /* Backspace one record */
#define IO_BSF 3 /* Backspace one file */
#define IO_WRS 4 /* Write one record */
#define IO_WEF 5 /* Write eof */
#define IO_REW 6 /* Rewind */
#define IO_DRS 7 /* Set unit offline */
#define IO_SDL 8 /* Set density low */
#define IO_SDH 9 /* Set density high */
#define IO_RUN 10 /* Rewind and unload unit */
#define IO_TRS 11 /* Check it unit ready */
#define IO_CTL 12 /* Io control device specific */
#define IO_RDB 13 /* Read backwards */
#define IO_SKR 14 /* Skip record forward */
#define IO_ERG 15 /* Erase next records from tape */
t_stat chan_reset(DEVICE *);
t_stat chan_boot(t_uint64);
@ -127,49 +105,49 @@ extern t_stat fprint_sym(FILE *, t_addr, t_value *, UNIT *, int32);
extern int32 tmxr_poll;
/* Generic devices common to all */
extern DEVICE cpu_dev;
extern UNIT cpu_unit[];
extern DEVICE cpu_dev;
extern UNIT cpu_unit[];
extern REG cpu_reg[];
extern DEVICE chan_dev;
extern DEVICE chan_dev;
/* Global device definitions */
#if (NUM_DEVS_CDR > 0) | (NUM_DEVS_CDP > 0)
extern DEVICE cdr_dev;
extern DEVICE cdr_dev;
extern t_stat card_cmd(uint16, uint16, uint8, uint16 *);
#endif
#if (NUM_DEVS_CDP > 0)
extern DEVICE cdp_dev;
extern DEVICE cdp_dev;
#endif
#if (NUM_DEVS_LPR > 0)
extern DEVICE lpr_dev;
extern DEVICE lpr_dev;
extern t_stat lpr_cmd(uint16, uint16, uint8, uint16 *);
#endif
#if (NUM_DEVS_CON > 0)
extern DEVICE con_dev;
extern DEVICE con_dev;
extern t_stat con_cmd(uint16, uint16, uint8, uint16 *);
#endif
#if (NUM_DEVS_DTC > 0)
extern DEVICE dtc_dev;
extern DEVICE dtc_dev;
extern t_stat dtc_cmd(uint16, uint16, uint8, uint16 *);
#endif
#if (NUM_DEVS_DR > 0)
extern DEVICE drm_dev;
#if (NUM_DEVS_DR > 0)
extern DEVICE drm_dev;
extern t_stat drm_cmd(uint16, uint16, uint8, uint16 *, uint8);
#endif
#if (NUM_DEVS_DSK > 0)
extern DEVICE dsk_dev;
extern DEVICE dsk_dev;
extern t_stat dsk_cmd(uint16, uint16, uint8, uint16 *);
extern DEVICE esu_dev;
extern DEVICE esu_dev;
#endif
#if (NUM_DEVS_MT > 0)
extern DEVICE mt_dev;
#if (NUM_DEVS_MT > 0)
extern DEVICE mt_dev;
extern t_stat mt_cmd(uint16, uint16, uint8, uint16 *);
#endif /* NUM_DEVS_MT */
@ -494,7 +472,7 @@ extern t_stat mt_cmd(uint16, uint16, uint8, uint16 *);
#define SSALF 00000010000000000LL
#define SVARF 00000000100000000LL
#define SCWMF 00000000000100000LL
#define FFIELD 00000007777700000LL
#define FFIELD 00000007777700000LL
#define FFIELD_V 15
#define REPFLD 00000770000000000LL
#define REPFLD_V 30
@ -503,7 +481,7 @@ extern t_stat mt_cmd(uint16, uint16, uint8, uint16 *);
#define PROGF 00400000000000000LL
#define RGH 00340700000000000LL /* Return Control Word +FFIELD and CORE */
#define RGH_V 33
#define RKV 00034070000000000LL
#define RKV 00034070000000000LL
#define RKV_V 30
#define RL 00003000000000000LL /* Save L register */
#define RL_V 36
@ -511,7 +489,7 @@ extern t_stat mt_cmd(uint16, uint16, uint8, uint16 *);
#define HMASK 00007777770000000LL
#define DEV_DRUM_RD 01000000000000000LL
#define DEVMASK 00760000000000000LL
#define D_MASK 00777777777777777LL
#define D_MASK 00777777777777777LL
#define DEV_V 40
#define DEV_WC 00017770000000000LL
#define DEV_WC_V 30
@ -535,9 +513,9 @@ extern t_stat mt_cmd(uint16, uint16, uint8, uint16 *);
#define DEV_EOF 00000000004000000LL /* D21 */
#define DEV_MEMERR 00000000010000000LL /* D22 */
#define DEV_RESULT 00000000037700000LL
#define DEV_EOT 01000100001000000LL
#define DEV_BOT 01000200001000000LL
#define DEV_BLANK 01000400001000000LL
#define DEV_EOT 01000100001000000LL
#define DEV_BOT 01000200001000000LL
#define DEV_BLANK 01000400001000000LL
#define DRUM1_DEV 004 /* 00100 (4) */
#define DSK1_DEV 006 /* 00110 (6) */

90
B5500/b5500_dtc.c
View file

@ -1,4 +1,4 @@
/* b5500_dtc.c: Burrioughs 5500 Data Communications
/* b5500_dtc.c: Burrioughs 5500 Data Communications
Copyright (c) 2016, Richard Cornwell
@ -26,7 +26,7 @@
#include "sim_sock.h"
#include "sim_tmxr.h"
#if (NUM_DEVS_DTC > 0)
#if (NUM_DEVS_DTC > 0)
#define UNIT_DTC UNIT_ATTABLE | UNIT_DISABLE | UNIT_IDLE
@ -44,8 +44,8 @@
#define DTCSTA_GM 0020 /* Ignore GM on transfer */
#define DTCSTA_BUF 0017 /* Buffer Number */
/* Interrogate
D28 - Busy DEV_ERROR
/* Interrogate
D28 - Busy DEV_ERROR
D27 - Write Ready DEV_EOF
D24 - Read Ready DEV_IORD */
/* Abnormal flag = DEV_WCFLG */
@ -85,11 +85,11 @@
BufIdle -> BufWrite (set GM if set.)
BufReadReady -> 0x20 (EOF).
BufInputBusy, BufWrite -> 0x30
-> 0x34 (EOF,ERROR)
-> 0x34 (EOF,ERROR)
BufWriteRdy -> BufWrite.
Write Done:
BufOutBusy.
BufOutBusy.
Read:
BufNotReady -> 0x34 (EOF,ERROR,NR)
@ -112,7 +112,7 @@
*/
/* Translate chars
output:
! -> LF.
< -> RO.
@ -121,23 +121,23 @@
~ -> End of message.
input:
~/_/CR -> End of message.
BufReadRdy, IRQ.
~/_/CR -> End of message.
BufReadRdy, IRQ.
</BS -> Back up one char.
!/ -> Disconnect insert }
BufReadRdy, IRQ.
^B -> Clear input.
BufReadRdy, IRQ.
^B -> Clear input.
BufIdle
^E -> set abnormal, buffer to BufWriteRdy.
^L -> Clear input.
BufIdle
? -> Set abnormal
Char: Buf to BufInputBsy. Insert char.
if Fullbuff, BufReadRdy, IRQ,
if Fullbuff, BufReadRdy, IRQ,
*/
t_stat dtc_srv(UNIT *);
t_stat dtco_srv(UNIT *);
@ -217,28 +217,28 @@ t_stat dtc_cmd(uint16 cmd, uint16 dev, uint8 chan, uint16 *wc)
uptr = &dtc_unit[0];
/* If unit disabled return error */
if (uptr->flags & UNIT_DIS)
if (uptr->flags & UNIT_DIS)
return SCPE_NODEV;
if ((uptr->flags & UNIT_ATT) == 0)
return SCPE_UNATT;
/* Check if drive is ready to recieve a command */
if ((uptr->u5 & DTC_RDY) == 0)
if ((uptr->u5 & DTC_RDY) == 0)
return SCPE_BUSY;
uptr->u5 = chan;
ttu = (*wc & DTCSTA_TTU) >> 5;
buf = (*wc & DTCSTA_BUF);
buf = (*wc & DTCSTA_BUF);
/* Set the Terminal unit. */
if (ttu == 0)
if (ttu == 0)
uptr->u4 = -1;
else {
uptr->u4 = buf + ((ttu-1) * 15);
}
if (*wc & DTCSTA_GM)
uptr->u5 |= DTC_IGNGM;
if (cmd & DTCSTA_READ)
if (cmd & DTCSTA_READ)
uptr->u5 |= DTC_RD;
else if (cmd & DTCSTA_INHIBIT)
uptr->u5 |= DTC_INQ;
@ -250,12 +250,12 @@ t_stat dtc_cmd(uint16 cmd, uint16 dev, uint8 chan, uint16 *wc)
sim_debug(DEBUG_CMD, &dtc_dev, "Datacomm access %s %06o %d %04o\n",
(uptr->u5 & DTC_RD) ? "read" : ((uptr->u5 & DTC_INQ) ? "inq" :
((uptr->u5 & DTC_WR) ? "write" : "unknown")),
((uptr->u5 & DTC_WR) ? "write" : "unknown")),
uptr->u5, uptr->u4, *wc);
sim_activate(uptr, 5000);
return SCPE_OK;
}
/* Handle processing terminal controller commands */
t_stat dtc_srv(UNIT * uptr)
@ -266,16 +266,15 @@ t_stat dtc_srv(UNIT * uptr)
int buf;
int i;
int line = uptr->u4;
/* Process interrage command */
if (uptr->u5 & DTC_INQ) {
if (line == -1) {
buf = -1;
for(i = 0; i < DTC_MLINES; i++) {
if (dtc_lstatus[i]& BufIRQ) {
if ((dtc_lstatus[i] & BufSMASK) == BufReadRdy)
if ((dtc_lstatus[i] & BufSMASK) == BufReadRdy)
buf = i;
if ((dtc_lstatus[i] & BufSMASK) == BufWriteRdy ||
(dtc_lstatus[i] & BufSMASK) == BufIdle) {
@ -306,7 +305,6 @@ t_stat dtc_srv(UNIT * uptr)
}
dtc_lstatus[line] &= ~BufIRQ;
}
sim_debug(DEBUG_DETAIL, &dtc_dev, " %03o ", dtc_lstatus[i]);
} else {
if (line > dtc_desc.lines) {
chan_set_notrdy(chan);
@ -359,7 +357,7 @@ t_stat dtc_srv(UNIT * uptr)
chan_set_end(chan);
uptr->u5 = DTC_RDY;
return SCPE_OK;
}
}
/* Validate that we can send data to buffer */
i = dtc_lstatus[line] & BufSMASK;
switch(i) {
@ -373,7 +371,7 @@ t_stat dtc_srv(UNIT * uptr)
chan_set_eof(chan);
chan_set_end(chan);
uptr->u5 = DTC_RDY;
sim_debug(DEBUG_DETAIL, &dtc_dev, "Datacomm write busy %d %d\n",
sim_debug(DEBUG_DETAIL, &dtc_dev, "Datacomm write busy %d %d\n",
line, i);
return SCPE_OK;
@ -390,7 +388,7 @@ t_stat dtc_srv(UNIT * uptr)
case BufWrite:
break;
}
if (chan_read_char(chan, &ch, dtc_bufptr[line] >= dtc_blimit[line])) {
sim_debug(DEBUG_DETAIL, &dtc_dev, "Datacomm write done %d %d ",
line, dtc_bufptr[line]);
@ -439,17 +437,22 @@ t_stat dtc_srv(UNIT * uptr)
chan_set_end(chan);
uptr->u5 = DTC_RDY;
return SCPE_OK;
}
}
/* Validate that we can send data to buffer */
i = dtc_lstatus[line] & BufSMASK;
switch(i) {
case BufNotReady:
chan_set_notrdy(chan);
/* Fall through */
case BufInputBusy:
chan_set_error(chan);
/* Fall through */
case BufWriteRdy:
/* Fall through */
case BufOutBusy:
/* Fall through */
case BufIdle:
/* Fall through */
case BufWrite:
chan_set_eof(chan);
chan_set_end(chan);
@ -479,7 +482,7 @@ t_stat dtc_srv(UNIT * uptr)
chan_set_gm(chan);
sim_debug(DEBUG_DETAIL, &dtc_dev, "gm ");
}
if (dtc_lstatus[line] & BufAbnormal)
if (dtc_lstatus[line] & BufAbnormal)
chan_set_wcflg(chan);
if (dtc_ldsc[line].conn == 0) /* connected? */
dtc_lstatus[line] = BufIRQ|BufNotReady;
@ -521,7 +524,7 @@ dtco_srv(UNIT * uptr)
dtc_lstatus[ln] = BufIRQ|BufAbnormal|BufWriteRdy;
IAR |= IRQ_12;
sim_debug(DEBUG_DETAIL, &dtc_dev, "Datacomm connect %d\n", ln);
}
}
/* For each line that is in idle state enable recieve */
for (ln = 0; ln < dtc_desc.lines; ln++) {
@ -536,8 +539,10 @@ dtco_srv(UNIT * uptr)
if (dtc_ldsc[ln].conn == 0) { /* connected? */
switch(dtc_lstatus[ln] & BufSMASK) {
case BufIdle: /* Idle, throw in EOT */
/* Fall through */
case BufWriteRdy: /* Awaiting output, terminate */
dtc_bufptr[ln] = 0;
/* Fall through */
case BufInputBusy: /* reading, terminate with EOT */
dtc_buf[ln][dtc_bufptr[ln]++] = 017;
dtc_bsize[ln] = dtc_bufptr[ln];
@ -549,7 +554,7 @@ dtco_srv(UNIT * uptr)
dtc_bsize[ln] = 0;
IAR |= IRQ_12;
break;
default: /* Other cases, ignore until
default: /* Other cases, ignore until
in better state */
break;
break;
@ -559,9 +564,9 @@ dtco_srv(UNIT * uptr)
switch(dtc_lstatus[ln] & BufSMASK) {
case BufIdle:
/* If we have any data to receive */
if (tmxr_rqln(&dtc_ldsc[ln]) > 0)
if (tmxr_rqln(&dtc_ldsc[ln]) > 0)
dtc_lstatus[ln] = BufInputBusy;
else
else
break; /* Nothing to do */
sim_debug(DEBUG_DETAIL, &dtc_dev, "Datacomm recieve %d idle\n",
ln);
@ -577,7 +582,7 @@ dtco_srv(UNIT * uptr)
dtc_lstatus[ln] &= ~(BufSMASK);
dtc_lstatus[ln] |= BufIRQ|BufAbnormal|BufWriteRdy;
IAR |= IRQ_12;
sim_debug(DEBUG_DETAIL, &dtc_dev,
sim_debug(DEBUG_DETAIL, &dtc_dev,
"Datacomm recieve ENQ %d\n", ln);
t = 0;
break;
@ -597,7 +602,9 @@ dtco_srv(UNIT * uptr)
/* Fall through to next */
case '\r':
/* Fall through */
case '\n':
/* Fall through */
case '~':
dtc_lstatus[ln] &= ~BufSMASK;
dtc_lstatus[ln] |= BufIRQ|BufReadRdy;
@ -625,11 +632,11 @@ dtco_srv(UNIT * uptr)
tmxr_putc_ln(&dtc_ldsc[ln], '\007');
}
c1 = 0;
sim_debug(DEBUG_DATA, &dtc_dev,
sim_debug(DEBUG_DATA, &dtc_dev,
"Datacomm recieve %d backspace %d\n", ln, dtc_bufptr[ln]);
break;
case '?':
sim_debug(DEBUG_DATA, &dtc_dev,
sim_debug(DEBUG_DATA, &dtc_dev,
"Datacomm recieve %d ?\n", ln);
dtc_lstatus[ln] |= BufAbnormal;
tmxr_putc_ln(&dtc_ldsc[ln], '?');
@ -655,7 +662,7 @@ dtco_srv(UNIT * uptr)
break;
}
}
break;
case BufOutBusy:
/* Get next char and send to output */
@ -684,7 +691,7 @@ dtco_srv(UNIT * uptr)
t = 0;
continue; /* On to next line */
}
sim_debug(DEBUG_DATA, &dtc_dev,
sim_debug(DEBUG_DATA, &dtc_dev,
"Datacomm transmit %d %02o %c\n", ln, c&077, c1);
tmxr_putc_ln(&dtc_ldsc[ln], c1);
if (c1 == '\n') {
@ -715,7 +722,7 @@ dtco_srv(UNIT * uptr)
}
t_stat
t_stat
dtc_reset(DEVICE *dptr) {
if (dtc_unit[0].flags & UNIT_ATT) {
sim_activate(&dtc_unit[1], 100); /* quick poll */
@ -777,6 +784,7 @@ t_stat dtc_setnl (UNIT *uptr, int32 val, CONST char *cptr, void *desc)
return r;
if ((newln == 0) || (newln > DTC_MLINES))
return SCPE_ARG;
newln--;
if (newln < dtc_desc.lines) {
for (i = newln, t = 0; i < dtc_desc.lines; i++)
t = t | dtc_ldsc[i].conn;

32
B5500/b5500_mt.c
View file

@ -159,7 +159,7 @@ mt_cmd(uint16 cmd, uint16 dev, uint8 chan, uint16 *wc)
int unit = dev >> 1;
/* Make sure valid drive number */
if (unit > NUM_DEVS_MT || unit < 0)
if (unit > (NUM_DEVS_MT - 1) || unit < 0)
return SCPE_NODEV;
uptr = &mt_unit[unit];
@ -199,7 +199,7 @@ mt_cmd(uint16 cmd, uint16 dev, uint8 chan, uint16 *wc)
*wc = 0; /* So no overide occurs */
/* Convert command to correct type */
/* Convert command to correct type */
if (cmd & URCSTA_DIRECT)
uptr->u5 |= MT_BACK;
uptr->u6 = 0;
@ -257,7 +257,7 @@ t_stat mt_error(UNIT * uptr, int chan, t_stat r, DEVICE * dptr)
sim_debug(DEBUG_EXP, dptr, "BOT ");
break;
case MTSE_UNATT: /* unattached */
default:
default:
sim_debug(DEBUG_EXP, dptr, "%d ", r);
}
uptr->u5 &= ~(MT_CMD|MT_BIN);
@ -309,8 +309,8 @@ t_stat mt_srv(UNIT * uptr)
switch (cmd) {
/* Handle interrogate */
case MT_INT:
if (sim_tape_wrp(uptr))
case MT_INT:
if (sim_tape_wrp(uptr))
chan_set_wrp(chan);
uptr->u5 &= ~(MT_CMD|MT_BIN);
uptr->u5 |= MT_RDY;
@ -334,7 +334,7 @@ t_stat mt_srv(UNIT * uptr)
ch = 017;
(void)chan_write_char(chan, &ch, 1);
sim_activate(uptr, 4000);
} else {
} else {
sim_debug(DEBUG_DETAIL, dptr, "r=%d\n", r);
sim_activate(uptr, 5000);
}
@ -369,7 +369,7 @@ t_stat mt_srv(UNIT * uptr)
}
}
if (chan_write_char(chan, &ch,
if (chan_write_char(chan, &ch,
(((uint32)uptr->u6) >= uptr->hwmark) ? 1 : 0)) {
sim_debug(DEBUG_DATA, dptr, "Read unit=%d %d EOR\n", unit,
uptr->hwmark-uptr->u6);
@ -398,7 +398,7 @@ t_stat mt_srv(UNIT * uptr)
ch = 017;
(void)chan_write_char(chan, &ch, 1);
sim_activate(uptr, 4000);
} else {
} else {
uptr->u5 |= MT_BSY;
sim_debug(DEBUG_DETAIL, dptr, "r=%d\n", r);
sim_activate(uptr, 100);
@ -465,7 +465,7 @@ t_stat mt_srv(UNIT * uptr)
sim_debug(DEBUG_DETAIL, dptr, "Write Mark unit=%d\n", unit);
r = sim_tape_wrtmk(uptr);
} else {
sim_debug(DEBUG_DETAIL, dptr,
sim_debug(DEBUG_DETAIL, dptr,
"Write unit=%d Block %d %s chars\n", unit, reclen,
(uptr->u5 & MT_BIN)? "bin": "bcd");
r = sim_tape_wrrecf(uptr, &mt_buffer[chan][0], reclen);
@ -477,10 +477,10 @@ t_stat mt_srv(UNIT * uptr)
/* Copy data to buffer */
ch &= 077;
ch |= parity_table[ch];
if ((uptr->u5 & MT_BIN))
if ((uptr->u5 & MT_BIN))
ch ^= 0100;
/* Don't write out even parity zeros */
if (ch != 0)
if (ch != 0)
mt_buffer[chan][uptr->u6++] = ch;
sim_debug(DEBUG_DATA, dptr, "Write data unit=%d %d %03o\n",
unit, uptr->u6, ch);
@ -505,7 +505,7 @@ t_stat mt_srv(UNIT * uptr)
sim_debug(DEBUG_DETAIL, dptr, "TM ");
reclen = 1;
chan_set_eof(chan);
} else {
} else {
sim_debug(DEBUG_DETAIL, dptr, "r=%d ", r);
reclen = 10;
}
@ -534,7 +534,7 @@ t_stat mt_srv(UNIT * uptr)
sim_debug(DEBUG_DETAIL, dptr, "TM ");
reclen = 1;
chan_set_eof(chan);
} else {
} else {
reclen = 10;
sim_debug(DEBUG_DETAIL, dptr, "r=%d ", r);
}
@ -572,7 +572,7 @@ mt_attach(UNIT * uptr, CONST char *file)
if ((r = sim_tape_attach(uptr, file)) != SCPE_OK)
return r;
uptr->u5 |= MT_LOADED|MT_BOT;
uptr->u5 |= MT_LOADED|MT_BOT;
sim_activate(uptr, 50000);
return SCPE_OK;
}
@ -590,8 +590,8 @@ mt_reset(DEVICE *dptr)
{
int i;
/* Scan all devices and enable those that
are loaded. This is to allow tapes that
/* Scan all devices and enable those that
are loaded. This is to allow tapes that
are mounted prior to boot to be recognized
at later. Also disconnect all devices no
longer connected. */

38
B5500/b5500_sys.c
View file

@ -90,8 +90,8 @@ DEBTAB dev_debug[] = {
};
uint8 parity_table[64] = {
/* 0 1 2 3 4 5 6 7 */
uint8 parity_table[64] = {
/* 0 1 2 3 4 5 6 7 */
0000, 0100, 0100, 0000, 0100, 0000, 0000, 0100,
0100, 0000, 0000, 0100, 0000, 0100, 0100, 0000,
0100, 0000, 0000, 0100, 0000, 0100, 0100, 0000,
@ -103,15 +103,15 @@ uint8 parity_table[64] = {
};
uint8 mem_to_ascii[64] = {
/* x0 x1 x2 x3 x4 x5 x6 x7 */
/* x0 x1 x2 x3 x4 x5 x6 x7 */
'0', '1', '2', '3', '4', '5', '6', '7', /* 0x */
'8', '9', '#', '@', '?', ':', '>', '}', /* 1x */
'+', 'A', 'B', 'C', 'D', 'E', 'F', 'G', /* 2x */
'H', 'I', '.', '[', '&', '(', '<', '~', /* 3x */
'|', 'J', 'K', 'L', 'M', 'N', 'O', 'P', /* 4x */
'Q', 'R', '$', '*', '-', ')', ';', '{', /* 5x */
' ', '/', 'S', 'T', 'U', 'V', 'W', 'X', /* 6x */
'Y', 'Z', ',', '%', '!', '=', ']', '"' /* 7x */
'|', 'J', 'K', 'L', 'M', 'N', 'O', 'P', /* 4x */
'Q', 'R', '$', '*', '-', ')', ';', '{', /* 5x */
' ', '/', 'S', 'T', 'U', 'V', 'W', 'X', /* 6x */
'Y', 'Z', ',', '%', '!', '=', ']', '"' /* 7x */
};
const char con_to_ascii[64] = {
@ -349,13 +349,13 @@ print_opcode(FILE * of, t_value val, t_opcode * tab)
while (tab->name != NULL) {
switch(tab->type) {
case TYPE_A:
if (op != tab->op)
if (op != tab->op)
break;
fputs(tab->name, of);
fputs(" ",of);
return;
case TYPE_B:
if ((op & 077) != tab->op)
if ((op & 077) != tab->op)
break;
fputs(tab->name, of);
fputc(' ',of);
@ -431,7 +431,7 @@ fprint_sym(FILE * of, t_addr addr, t_value * val, UNIT * uptr, int32 sw)
fputc('\'', of);
}
if (sw & SWMASK('F')) { /* Floating point/Descriptor */
}
}
return SCPE_OK;
}
@ -474,10 +474,10 @@ parse_sym(CONST char *cptr, t_addr addr, UNIT * uptr, t_value * val, int32 sw)
/* Grab opcode */
cptr = get_glyph(cptr, opcode, 0);
op = 0;
opr = -1;
if((op = find_opcode(opcode,
if((op = find_opcode(opcode,
(SWMASK('W') ? word_ops : char_ops))) == 0) {
return SCPE_UNK;
}
@ -492,25 +492,25 @@ parse_sym(CONST char *cptr, t_addr addr, UNIT * uptr, t_value * val, int32 sw)
cptr++;
switch (op->type) {
case TYPE_A:
if (opr >= 0)
if (opr >= 0)
return SCPE_2MARG;
*val = op->op;
return SCPE_OK;
case TYPE_B:
if (opr < 0 || opr > 64)
if (opr < 0 || opr > 64)
return SCPE_ARG;
*val = (opr << 6) | op->op;
return SCPE_OK;
case TYPE_C:
if (opr < 0 || opr > 16)
if (opr < 0 || opr > 16)
return SCPE_ARG;
*val = (opr << 8) | op->op;
return SCPE_OK;
case TYPE_D:
if (opr < 0 || opr > 1024)
if (opr < 0 || opr > 1024)
return SCPE_ARG;
*val = (opr << 2) | op->op;
return SCPE_OK;
@ -532,10 +532,4 @@ parse_sym(CONST char *cptr, t_addr addr, UNIT * uptr, t_value * val, int32 sw)
}
*val = d;
return SCPE_OK;
/* Symbolic input, continued */
if (*cptr != 0)
return SCPE_ARG; /* junk at end? */
return SCPE_OK;
}

29
B5500/b5500_urec.c
View file

@ -234,7 +234,7 @@ DEVICE con_dev = {
t_stat card_cmd(uint16 cmd, uint16 dev, uint8 chan, uint16 *wc)
{
UNIT *uptr;
int u;
int u;
if (dev == CARD1_DEV)
u = 0;
@ -355,7 +355,7 @@ cdr_srv(UNIT *uptr) {
/* Copy next column over */
if (uptr->u5 & URCSTA_CARD &&
uptr->u4 <= ((uptr->u5 & URCSTA_BIN) ? 160 : 80)) {
uptr->u4 < ((uptr->u5 & URCSTA_BIN) ? 160 : 80)) {
struct _card_data *data;
uint8 ch = 0;
int u = (uptr - cdr_unit);
@ -384,6 +384,8 @@ cdr_srv(UNIT *uptr) {
break; /* Translate ? to error*/
}
}
sim_debug(DEBUG_DATA, &cdr_dev, "cdr %d: Char > %03o '%c' %d\n", u, ch,
sim_six_to_ascii[ch & 077], uptr->u4);
if(chan_write_char(chan, &ch, 0)) {
uptr->u5 &= ~(URCSTA_ACTIVE|URCSTA_CARD);
chan_set_end(chan);
@ -396,8 +398,18 @@ cdr_srv(UNIT *uptr) {
uptr->u4++;
sim_activate(uptr, 100);
}
sim_debug(DEBUG_DATA, &cdr_dev, "cdr %d: Char > %03o '%c' %d\n", u, ch,
sim_six_to_ascii[ch & 077], uptr->u4);
}
/* Check if last column */
if (uptr->u5 & URCSTA_CARD &&
uptr->u4 == ((uptr->u5 & URCSTA_BIN) ? 160 : 80)) {
uptr->u5 &= ~(URCSTA_ACTIVE|URCSTA_CARD);
chan_set_end(chan);
/* Drop ready a bit after the last card is read */
if (sim_card_eof(uptr)) {
uptr->u5 |= URCSTA_EOF;
}
}
return SCPE_OK;
}
@ -502,7 +514,7 @@ cdp_srv(UNIT *uptr) {
}
/* Copy next column over */
if (uptr->u5 & URCSTA_ACTIVE && uptr->u4 <= 80) {
if (uptr->u5 & URCSTA_ACTIVE && uptr->u4 < 80) {
struct _card_data *data;
uint8 ch = 0;
@ -518,6 +530,12 @@ cdp_srv(UNIT *uptr) {
}
sim_activate(uptr, 10);
}
/* Check if last column */
if (uptr->u5 & URCSTA_ACTIVE && uptr->u4 == 80) {
uptr->u5 |= URCSTA_BUSY|URCSTA_FULL;
uptr->u5 &= ~URCSTA_ACTIVE;
}
return SCPE_OK;
}
@ -945,6 +963,7 @@ con_srv(UNIT *uptr) {
switch (ch) {
case 033:
con_data[0].inptr = 0;
/* Fall through */
case '\r':
case '\n':
uptr->u5 &= ~URCSTA_INPUT;