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Adding mode device help

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This commit is contained in:
Mark Pizzolato 2013-02-05 06:49:39 -08:00
parent 453890f3d7
commit 610ecaaa93
5 changed files with 296 additions and 216 deletions
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3
PDP11/pdp11_dz.c
View file

@ -903,7 +903,8 @@ fprintf (st, " sim> SHOW %s CONNECTIONS show current connections\n", dptr->n
fprintf (st, " sim> SHOW %s STATISTICS show statistics for active connections\n", dptr->name); fprintf (st, " sim> SHOW %s STATISTICS show statistics for active connections\n", dptr->name);
fprintf (st, " sim> SET %s DISCONNECT=linenumber disconnects the specified line.\n\n\n", dptr->name); fprintf (st, " sim> SET %s DISCONNECT=linenumber disconnects the specified line.\n\n\n", dptr->name);
fprintf (st, "All open connections are lost when the simulator shuts down or the %s is\n", dptr->name); fprintf (st, "All open connections are lost when the simulator shuts down or the %s is\n", dptr->name);
fprintf (st, "detached.\n"); fprintf (st, "detached.\n\n");
dz_help_attach (st, dptr, uptr, flag, cptr);
return SCPE_OK; return SCPE_OK;
} }

326
PDP11/pdp11_rq.c
View file

@ -798,6 +798,7 @@ t_stat rq_show_ctype (FILE *st, UNIT *uptr, int32 val, void *desc);
t_stat rq_show_wlk (FILE *st, UNIT *uptr, int32 val, void *desc); t_stat rq_show_wlk (FILE *st, UNIT *uptr, int32 val, void *desc);
t_stat rq_show_ctrl (FILE *st, UNIT *uptr, int32 val, void *desc); t_stat rq_show_ctrl (FILE *st, UNIT *uptr, int32 val, void *desc);
t_stat rq_show_unitq (FILE *st, UNIT *uptr, int32 val, void *desc); t_stat rq_show_unitq (FILE *st, UNIT *uptr, int32 val, void *desc);
t_stat rq_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr);
char *rq_description (DEVICE *dptr); char *rq_description (DEVICE *dptr);
t_bool rq_step4 (MSC *cp); t_bool rq_step4 (MSC *cp);
@ -873,45 +874,44 @@ UNIT rq_unit[] = {
}; };
REG rq_reg[] = { REG rq_reg[] = {
{ GRDATA (UBASE, rq_ctx.ubase, DEV_RDX, 8, 0), REG_RO }, { GRDATAD (UBASE, rq_ctx.ubase, DEV_RDX, 8, 0, "unit base"), REG_RO },
{ GRDATA (SA, rq_ctx.sa, DEV_RDX, 16, 0) }, { GRDATAD (SA, rq_ctx.sa, DEV_RDX, 16, 0, "status/address register") },
{ GRDATA (SAW, rq_ctx.saw, DEV_RDX, 16, 0) }, { GRDATAD (SAW, rq_ctx.saw, DEV_RDX, 16, 0, "written data") },
{ GRDATA (S1DAT, rq_ctx.s1dat, DEV_RDX, 16, 0) }, { GRDATAD (S1DAT, rq_ctx.s1dat, DEV_RDX, 16, 0, "step 1 init host data") },
{ GRDATA (COMM, rq_ctx.comm, DEV_RDX, 22, 0) }, { GRDATAD (COMM, rq_ctx.comm, DEV_RDX, 22, 0, "comm region") },
{ GRDATA (CQIOFF, rq_ctx.cq.ioff, DEV_RDX, 32, 0) }, { GRDATAD (CQIOFF, rq_ctx.cq.ioff, DEV_RDX, 32, 0, "command queue intr offset") },
{ GRDATA (CQBA, rq_ctx.cq.ba, DEV_RDX, 22, 0) }, { GRDATAD (CQBA, rq_ctx.cq.ba, DEV_RDX, 22, 0, "command queue base address") },
{ GRDATA (CQLNT, rq_ctx.cq.lnt, DEV_RDX, 32, 2), REG_NZ }, { GRDATAD (CQLNT, rq_ctx.cq.lnt, DEV_RDX, 32, 2, "command queue length"), REG_NZ },
{ GRDATA (CQIDX, rq_ctx.cq.idx, DEV_RDX, 8, 2) }, { GRDATAD (CQIDX, rq_ctx.cq.idx, DEV_RDX, 8, 2, "command queue index") },
{ GRDATA (RQIOFF, rq_ctx.rq.ioff, DEV_RDX, 32, 0) }, { GRDATAD (RQIOFF, rq_ctx.rq.ioff, DEV_RDX, 32, 0, "request queue intr offset") },
{ GRDATA (RQBA, rq_ctx.rq.ba, DEV_RDX, 22, 0) }, { GRDATAD (RQBA, rq_ctx.rq.ba, DEV_RDX, 22, 0, "request queue base address") },
{ GRDATA (RQLNT, rq_ctx.rq.lnt, DEV_RDX, 32, 2), REG_NZ }, { GRDATAD (RQLNT, rq_ctx.rq.lnt, DEV_RDX, 32, 2, "request queue length"), REG_NZ },
{ GRDATA (RQIDX, rq_ctx.rq.idx, DEV_RDX, 8, 2) }, { GRDATAD (RQIDX, rq_ctx.rq.idx, DEV_RDX, 8, 2, "request queue index") },
{ DRDATA (FREE, rq_ctx.freq, 5) }, { DRDATAD (FREE, rq_ctx.freq, 5, "head of free packet list") },
{ DRDATA (RESP, rq_ctx.rspq, 5) }, { DRDATAD (RESP, rq_ctx.rspq, 5, "head of response packet list") },
{ DRDATA (PBSY, rq_ctx.pbsy, 5) }, { DRDATAD (PBSY, rq_ctx.pbsy, 5, "number of busy packets") },
{ GRDATA (CFLGS, rq_ctx.cflgs, DEV_RDX, 16, 0) }, { GRDATAD (CFLGS, rq_ctx.cflgs, DEV_RDX, 16, 0, "controller flags") },
{ GRDATA (CSTA, rq_ctx.csta, DEV_RDX, 4, 0) }, { GRDATAD (CSTA, rq_ctx.csta, DEV_RDX, 4, 0, "controller state") },
{ GRDATA (PERR, rq_ctx.perr, DEV_RDX, 9, 0) }, { GRDATAD (PERR, rq_ctx.perr, DEV_RDX, 9, 0, "port error number") },
{ DRDATA (CRED, rq_ctx.credits, 5) }, { DRDATAD (CRED, rq_ctx.credits, 5, "host credits") },
{ DRDATA (HAT, rq_ctx.hat, 17) }, { DRDATAD (HAT, rq_ctx.hat, 17, "host available timer") },
{ DRDATA (HTMO, rq_ctx.htmo, 17) }, { DRDATAD (HTMO, rq_ctx.htmo, 17, "host timeout value") },
{ FLDATA (PRGI, rq_ctx.prgi, 0), REG_HIDDEN }, { FLDATA (PRGI, rq_ctx.prgi, 0), REG_HIDDEN },
{ FLDATA (PIP, rq_ctx.pip, 0), REG_HIDDEN }, { FLDATA (PIP, rq_ctx.pip, 0), REG_HIDDEN },
{ FLDATA (CTYPE, rq_ctx.ctype, 32), REG_HIDDEN }, { FLDATA (CTYPE, rq_ctx.ctype, 32), REG_HIDDEN },
{ DRDATA (ITIME, rq_itime, 24), PV_LEFT + REG_NZ }, { DRDATAD (ITIME, rq_itime, 24, "init time delay, except stage 4"), PV_LEFT + REG_NZ },
{ DRDATA (ITIME, rq_itime, 24), PV_LEFT + REG_NZ }, { DRDATAD (I4TIME, rq_itime4, 24, "init stage 4 delay"), PV_LEFT + REG_NZ },
{ DRDATA (I4TIME, rq_itime4, 24), PV_LEFT + REG_NZ }, { DRDATAD (QTIME, rq_qtime, 24, "response time for 'immediate' packets"), PV_LEFT + REG_NZ },
{ DRDATA (QTIME, rq_qtime, 24), PV_LEFT + REG_NZ }, { DRDATAD (XTIME, rq_xtime, 24, "response time for data transfers"), PV_LEFT + REG_NZ },
{ DRDATA (XTIME, rq_xtime, 24), PV_LEFT + REG_NZ }, { BRDATAD (PKTS, rq_ctx.pak, DEV_RDX, 16, sizeof(rq_ctx.pak)/2, "packet buffers, 33W each, 32 entries") },
{ BRDATA (PKTS, rq_ctx.pak, DEV_RDX, 16, sizeof(rq_ctx.pak)/2) }, { URDATAD (CPKT, rq_unit[0].cpkt, 10, 5, 0, RQ_NUMDR, 0, "current packet, units 0 to 3") },
{ URDATA (CPKT, rq_unit[0].cpkt, 10, 5, 0, RQ_NUMDR, 0) }, { URDATAD (UCNUM, rq_unit[0].cnum, 10, 5, 0, RQ_NUMDR, 0, "ctrl number, units 0 to 3") },
{ URDATA (UCNUM, rq_unit[0].cnum, 10, 5, 0, RQ_NUMDR, 0) }, { URDATAD (PKTQ, rq_unit[0].pktq, 10, 5, 0, RQ_NUMDR, 0, "packet queue, units 0 to 3") },
{ URDATA (PKTQ, rq_unit[0].pktq, 10, 5, 0, RQ_NUMDR, 0) }, { URDATAD (UFLG, rq_unit[0].uf, DEV_RDX, 16, 0, RQ_NUMDR, 0, "unit flags, units 0 to 3") },
{ URDATA (UFLG, rq_unit[0].uf, DEV_RDX, 16, 0, RQ_NUMDR, 0) }, { URDATA (CAPAC, rq_unit[0].capac, 10, T_ADDR_W, 0, RQ_NUMDR, PV_LEFT | REG_HRO) },
{ URDATA (CAPAC, rq_unit[0].capac, 10, T_ADDR_W, 0, RQ_NUMDR, PV_LEFT | REG_HRO) }, { GRDATA (DEVADDR, rq_dib.ba, DEV_RDX, 32, 0), REG_HRO },
{ GRDATA (DEVADDR, rq_dib.ba, DEV_RDX, 32, 0), REG_HRO }, { GRDATA (DEVVEC, rq_dib.vec, DEV_RDX, 16, 0), REG_HRO },
{ GRDATA (DEVVEC, rq_dib.vec, DEV_RDX, 16, 0), REG_HRO }, { DRDATA (DEVLBN, drv_tab[RA8U_DTYPE].lbn, 22), REG_HRO },
{ DRDATA (DEVLBN, drv_tab[RA8U_DTYPE].lbn, 22), REG_HRO },
{ NULL } { NULL }
}; };
@ -932,14 +932,14 @@ MTAB rq_mod[] = {
NULL, &rq_show_ctrl, NULL, "Display all unit queues" }, NULL, &rq_show_ctrl, NULL, "Display all unit queues" },
{ MTAB_XTD|MTAB_VDV|MTAB_NMO, RQ_SH_ALL, "ALL", NULL, { MTAB_XTD|MTAB_VDV|MTAB_NMO, RQ_SH_ALL, "ALL", NULL,
NULL, &rq_show_ctrl, NULL, "Display complete controller state" }, NULL, &rq_show_ctrl, NULL, "Display complete controller state" },
{ MTAB_XTD|MTAB_VDV, RQDX3_CTYPE, NULL, "RQDX3",
&rq_set_ctype, NULL, NULL, "Set RQDX3 Controller Type" },
{ MTAB_XTD|MTAB_VDV, UDA50_CTYPE, NULL, "UDA50",
&rq_set_ctype, NULL, NULL, "Set UDA50 Controller Type" },
{ MTAB_XTD|MTAB_VDV, KLESI_CTYPE, NULL, "KLESI", { MTAB_XTD|MTAB_VDV, KLESI_CTYPE, NULL, "KLESI",
&rq_set_ctype, NULL, NULL, "Set KLESI Controller Type" }, &rq_set_ctype, NULL, NULL, "Set KLESI Controller Type" },
{ MTAB_XTD|MTAB_VDV, RUX50_CTYPE, NULL, "RUX50", { MTAB_XTD|MTAB_VDV, RUX50_CTYPE, NULL, "RUX50",
&rq_set_ctype, NULL, NULL, "Set RUX50 Controller Type" }, &rq_set_ctype, NULL, NULL, "Set RUX50 Controller Type" },
{ MTAB_XTD|MTAB_VDV, UDA50_CTYPE, NULL, "UDA50",
&rq_set_ctype, NULL, NULL, "Set UDA50 Controller Type" },
{ MTAB_XTD|MTAB_VDV, RQDX3_CTYPE, NULL, "RQDX3",
&rq_set_ctype, NULL, NULL, "Set RQDX3 Controller Type" },
{ MTAB_XTD|MTAB_VUN|MTAB_NMO, 0, "UNITQ", NULL, { MTAB_XTD|MTAB_VUN|MTAB_NMO, 0, "UNITQ", NULL,
NULL, &rq_show_unitq, NULL, "Display unit queue" }, NULL, &rq_show_unitq, NULL, "Display unit queue" },
{ MTAB_XTD|MTAB_VUN, RX50_DTYPE, NULL, "RX50", { MTAB_XTD|MTAB_VUN, RX50_DTYPE, NULL, "RX50",
@ -1012,7 +1012,7 @@ DEVICE rq_dev = {
NULL, NULL, &rq_reset, NULL, NULL, &rq_reset,
&rq_boot, &rq_attach, &rq_detach, &rq_boot, &rq_attach, &rq_detach,
&rq_dib, DEV_DISABLE | DEV_UBUS | DEV_QBUS | DEV_DEBUG | DEV_DISK, &rq_dib, DEV_DISABLE | DEV_UBUS | DEV_QBUS | DEV_DEBUG | DEV_DISK,
0, rq_debug, NULL, NULL, NULL, NULL, NULL, 0, rq_debug, NULL, NULL, &rq_help, NULL, NULL,
&rq_description &rq_description
}; };
@ -1045,39 +1045,39 @@ UNIT rqb_unit[] = {
}; };
REG rqb_reg[] = { REG rqb_reg[] = {
{ GRDATA (UBASE, rqb_ctx.ubase, DEV_RDX, 8, 0), REG_RO }, { GRDATAD (UBASE, rqb_ctx.ubase, DEV_RDX, 8, 0, "unit base"), REG_RO },
{ GRDATA (SA, rqb_ctx.sa, DEV_RDX, 16, 0) }, { GRDATAD (SA, rqb_ctx.sa, DEV_RDX, 16, 0, "status/address register") },
{ GRDATA (SAW, rqb_ctx.saw, DEV_RDX, 16, 0) }, { GRDATAD (SAW, rqb_ctx.saw, DEV_RDX, 16, 0, "written data") },
{ GRDATA (S1DAT, rqb_ctx.s1dat, DEV_RDX, 16, 0) }, { GRDATAD (S1DAT, rqb_ctx.s1dat, DEV_RDX, 16, 0, "step 1 init host data") },
{ GRDATA (COMM, rqb_ctx.comm, DEV_RDX, 22, 0) }, { GRDATAD (COMM, rqb_ctx.comm, DEV_RDX, 22, 0, "comm region") },
{ GRDATA (CQIOFF, rqb_ctx.cq.ioff, DEV_RDX, 32, 0) }, { GRDATAD (CQIOFF, rqb_ctx.cq.ioff, DEV_RDX, 32, 0, "command queue intr offset") },
{ GRDATA (CQBA, rqb_ctx.cq.ba, DEV_RDX, 22, 0) }, { GRDATAD (CQBA, rqb_ctx.cq.ba, DEV_RDX, 22, 0, "command queue base address") },
{ GRDATA (CQLNT, rqb_ctx.cq.lnt, DEV_RDX, 32, 2), REG_NZ }, { GRDATAD (CQLNT, rqb_ctx.cq.lnt, DEV_RDX, 32, 2, "command queue length"), REG_NZ },
{ GRDATA (CQIDX, rqb_ctx.cq.idx, DEV_RDX, 8, 2) }, { GRDATAD (CQIDX, rqb_ctx.cq.idx, DEV_RDX, 8, 2, "command queue index") },
{ GRDATA (RQIOFF, rqb_ctx.rq.ioff, DEV_RDX, 32, 0) }, { GRDATAD (RQIOFF, rqb_ctx.rq.ioff, DEV_RDX, 32, 0, "request queue intr offset") },
{ GRDATA (RQBA, rqb_ctx.rq.ba, DEV_RDX, 22, 0) }, { GRDATAD (RQBA, rqb_ctx.rq.ba, DEV_RDX, 22, 0, "request queue base address") },
{ GRDATA (RQLNT, rqb_ctx.rq.lnt, DEV_RDX, 32, 2), REG_NZ }, { GRDATAD (RQLNT, rqb_ctx.rq.lnt, DEV_RDX, 32, 2, "request queue length"), REG_NZ },
{ GRDATA (RQIDX, rqb_ctx.rq.idx, DEV_RDX, 8, 2) }, { GRDATAD (RQIDX, rqb_ctx.rq.idx, DEV_RDX, 8, 2, "request queue index") },
{ DRDATA (FREE, rqb_ctx.freq, 5) }, { DRDATAD (FREE, rqb_ctx.freq, 5, "head of free packet list") },
{ DRDATA (RESP, rqb_ctx.rspq, 5) }, { DRDATAD (RESP, rqb_ctx.rspq, 5, "head of response packet list") },
{ DRDATA (PBSY, rqb_ctx.pbsy, 5) }, { DRDATAD (PBSY, rqb_ctx.pbsy, 5, "number of busy packets") },
{ GRDATA (CFLGS, rqb_ctx.cflgs, DEV_RDX, 16, 0) }, { GRDATAD (CFLGS, rqb_ctx.cflgs, DEV_RDX, 16, 0, "controller flags") },
{ GRDATA (CSTA, rqb_ctx.csta, DEV_RDX, 4, 0) }, { GRDATAD (CSTA, rqb_ctx.csta, DEV_RDX, 4, 0, "controller state") },
{ GRDATA (PERR, rqb_ctx.perr, DEV_RDX, 9, 0) }, { GRDATAD (PERR, rqb_ctx.perr, DEV_RDX, 9, 0, "port error number") },
{ DRDATA (CRED, rqb_ctx.credits, 5) }, { DRDATAD (CRED, rqb_ctx.credits, 5, "host credits") },
{ DRDATA (HAT, rqb_ctx.hat, 17) }, { DRDATAD (HAT, rqb_ctx.hat, 17, "host available timer") },
{ DRDATA (HTMO, rqb_ctx.htmo, 17) }, { DRDATAD (HTMO, rqb_ctx.htmo, 17, "host timeout value") },
{ FLDATA (PRGI, rqb_ctx.prgi, 0), REG_HIDDEN }, { FLDATA (PRGI, rqb_ctx.prgi, 0), REG_HIDDEN },
{ FLDATA (PIP, rqb_ctx.pip, 0), REG_HIDDEN }, { FLDATA (PIP, rqb_ctx.pip, 0), REG_HIDDEN },
{ FLDATA (CTYPE, rqb_ctx.ctype, 32), REG_HIDDEN }, { FLDATA (CTYPE, rqb_ctx.ctype, 32), REG_HIDDEN },
{ BRDATA (PKTS, rqb_ctx.pak, DEV_RDX, 16, sizeof(rqb_ctx.pak)/2) }, { BRDATAD (PKTS, rqb_ctx.pak, DEV_RDX, 16, sizeof(rq_ctx.pak)/2, "packet buffers, 33W each, 32 entries") },
{ URDATA (CPKT, rqb_unit[0].cpkt, 10, 5, 0, RQ_NUMDR, 0) }, { URDATAD (CPKT, rqb_unit[0].cpkt, 10, 5, 0, RQ_NUMDR, 0, "current packet, units 0 to 3") },
{ URDATA (UCNUM, rqb_unit[0].cnum, 10, 5, 0, RQ_NUMDR, 0) }, { URDATAD (UCNUM, rqb_unit[0].cnum, 10, 5, 0, RQ_NUMDR, 0, "ctrl number, units 0 to 3") },
{ URDATA (PKTQ, rqb_unit[0].pktq, 10, 5, 0, RQ_NUMDR, 0) }, { URDATAD (PKTQ, rqb_unit[0].pktq, 10, 5, 0, RQ_NUMDR, 0, "packet queue, units 0 to 3") },
{ URDATA (UFLG, rqb_unit[0].uf, DEV_RDX, 16, 0, RQ_NUMDR, 0) }, { URDATAD (UFLG, rqb_unit[0].uf, DEV_RDX, 16, 0, RQ_NUMDR, 0, "unit flags, units 0 to 3") },
{ URDATA (CAPAC, rqb_unit[0].capac, 10, T_ADDR_W, 0, RQ_NUMDR, PV_LEFT | REG_HRO) }, { URDATA (CAPAC, rqb_unit[0].capac, 10, T_ADDR_W, 0, RQ_NUMDR, PV_LEFT | REG_HRO) },
{ GRDATA (DEVADDR, rqb_dib.ba, DEV_RDX, 32, 0), REG_HRO }, { GRDATA (DEVADDR, rqb_dib.ba, DEV_RDX, 32, 0), REG_HRO },
{ GRDATA (DEVVEC, rqb_dib.vec, DEV_RDX, 16, 0), REG_HRO }, { GRDATA (DEVVEC, rqb_dib.vec, DEV_RDX, 16, 0), REG_HRO },
{ NULL } { NULL }
}; };
@ -1087,7 +1087,7 @@ DEVICE rqb_dev = {
NULL, NULL, &rq_reset, NULL, NULL, &rq_reset,
&rq_boot, &rq_attach, &rq_detach, &rq_boot, &rq_attach, &rq_detach,
&rqb_dib, DEV_DISABLE | DEV_DIS | DEV_UBUS | DEV_QBUS | DEV_DEBUG | DEV_DISK, &rqb_dib, DEV_DISABLE | DEV_DIS | DEV_UBUS | DEV_QBUS | DEV_DEBUG | DEV_DISK,
0, rq_debug, NULL, NULL, NULL, NULL, NULL, 0, rq_debug, NULL, NULL, &rq_help, NULL, NULL,
&rq_description &rq_description
}; };
@ -1120,39 +1120,39 @@ UNIT rqc_unit[] = {
}; };
REG rqc_reg[] = { REG rqc_reg[] = {
{ GRDATA (UBASE, rqc_ctx.ubase, DEV_RDX, 8, 0), REG_RO }, { GRDATAD (UBASE, rqc_ctx.ubase, DEV_RDX, 8, 0, "unit base"), REG_RO },
{ GRDATA (SA, rqc_ctx.sa, DEV_RDX, 16, 0) }, { GRDATAD (SA, rqc_ctx.sa, DEV_RDX, 16, 0, "status/address register") },
{ GRDATA (SAW, rqc_ctx.saw, DEV_RDX, 16, 0) }, { GRDATAD (SAW, rqc_ctx.saw, DEV_RDX, 16, 0, "written data") },
{ GRDATA (S1DAT, rqc_ctx.s1dat, DEV_RDX, 16, 0) }, { GRDATAD (S1DAT, rqc_ctx.s1dat, DEV_RDX, 16, 0, "step 1 init host data") },
{ GRDATA (COMM, rqc_ctx.comm, DEV_RDX, 22, 0) }, { GRDATAD (COMM, rqc_ctx.comm, DEV_RDX, 22, 0, "comm region") },
{ GRDATA (CQIOFF, rqc_ctx.cq.ioff, DEV_RDX, 32, 0) }, { GRDATAD (CQIOFF, rqc_ctx.cq.ioff, DEV_RDX, 32, 0, "command queue intr offset") },
{ GRDATA (CQBA, rqc_ctx.cq.ba, DEV_RDX, 22, 0) }, { GRDATAD (CQBA, rqc_ctx.cq.ba, DEV_RDX, 22, 0, "command queue base address") },
{ GRDATA (CQLNT, rqc_ctx.cq.lnt, DEV_RDX, 32, 2), REG_NZ }, { GRDATAD (CQLNT, rqc_ctx.cq.lnt, DEV_RDX, 32, 2, "command queue length"), REG_NZ },
{ GRDATA (CQIDX, rqc_ctx.cq.idx, DEV_RDX, 8, 2) }, { GRDATAD (CQIDX, rqc_ctx.cq.idx, DEV_RDX, 8, 2, "command queue index") },
{ GRDATA (RQIOFF, rqc_ctx.rq.ioff, DEV_RDX, 32, 0) }, { GRDATAD (RQIOFF, rqc_ctx.rq.ioff, DEV_RDX, 32, 0, "request queue intr offset") },
{ GRDATA (RQBA, rqc_ctx.rq.ba, DEV_RDX, 22, 0) }, { GRDATAD (RQBA, rqc_ctx.rq.ba, DEV_RDX, 22, 0, "request queue base address") },
{ GRDATA (RQLNT, rqc_ctx.rq.lnt, DEV_RDX, 32, 2), REG_NZ }, { GRDATAD (RQLNT, rqc_ctx.rq.lnt, DEV_RDX, 32, 2, "request queue length"), REG_NZ },
{ GRDATA (RQIDX, rqc_ctx.rq.idx, DEV_RDX, 8, 2) }, { GRDATAD (RQIDX, rqc_ctx.rq.idx, DEV_RDX, 8, 2, "request queue index") },
{ DRDATA (FREE, rqc_ctx.freq, 5) }, { DRDATAD (FREE, rqc_ctx.freq, 5, "head of free packet list") },
{ DRDATA (RESP, rqc_ctx.rspq, 5) }, { DRDATAD (RESP, rqc_ctx.rspq, 5, "head of response packet list") },
{ DRDATA (PBSY, rqc_ctx.pbsy, 5) }, { DRDATAD (PBSY, rqc_ctx.pbsy, 5, "number of busy packets") },
{ GRDATA (CFLGS, rqc_ctx.cflgs, DEV_RDX, 16, 0) }, { GRDATAD (CFLGS, rqc_ctx.cflgs, DEV_RDX, 16, 0, "controller flags") },
{ GRDATA (CSTA, rqc_ctx.csta, DEV_RDX, 4, 0) }, { GRDATAD (CSTA, rqc_ctx.csta, DEV_RDX, 4, 0, "controller state") },
{ GRDATA (PERR, rqc_ctx.perr, DEV_RDX, 9, 0) }, { GRDATAD (PERR, rqc_ctx.perr, DEV_RDX, 9, 0, "port error number") },
{ DRDATA (CRED, rqc_ctx.credits, 5) }, { DRDATAD (CRED, rqc_ctx.credits, 5, "host credits") },
{ DRDATA (HAT, rqc_ctx.hat, 17) }, { DRDATAD (HAT, rqc_ctx.hat, 17, "host available timer") },
{ DRDATA (HTMO, rqc_ctx.htmo, 17) }, { DRDATAD (HTMO, rqc_ctx.htmo, 17, "host timeout value") },
{ FLDATA (PRGI, rqc_ctx.prgi, 0), REG_HIDDEN }, { FLDATA (PRGI, rqc_ctx.prgi, 0), REG_HIDDEN },
{ FLDATA (PIP, rqc_ctx.pip, 0), REG_HIDDEN }, { FLDATA (PIP, rqc_ctx.pip, 0), REG_HIDDEN },
{ FLDATA (CTYPE, rqc_ctx.ctype, 32), REG_HIDDEN }, { FLDATA (CTYPE, rqc_ctx.ctype, 32), REG_HIDDEN },
{ BRDATA (PKTS, rqc_ctx.pak, DEV_RDX, 16, sizeof(rqc_ctx.pak)/2) }, { BRDATAD (PKTS, rqc_ctx.pak, DEV_RDX, 16, sizeof(rq_ctx.pak)/2, "packet buffers, 33W each, 32 entries") },
{ URDATA (CPKT, rqc_unit[0].cpkt, 10, 5, 0, RQ_NUMDR, 0) }, { URDATAD (CPKT, rqc_unit[0].cpkt, 10, 5, 0, RQ_NUMDR, 0, "current packet, units 0 to 3") },
{ URDATA (UCNUM, rqc_unit[0].cnum, 10, 5, 0, RQ_NUMDR, 0) }, { URDATAD (UCNUM, rqc_unit[0].cnum, 10, 5, 0, RQ_NUMDR, 0, "ctrl number, units 0 to 3") },
{ URDATA (PKTQ, rqc_unit[0].pktq, 10, 5, 0, RQ_NUMDR, 0) }, { URDATAD (PKTQ, rqc_unit[0].pktq, 10, 5, 0, RQ_NUMDR, 0, "packet queue, units 0 to 3") },
{ URDATA (UFLG, rqc_unit[0].uf, DEV_RDX, 16, 0, RQ_NUMDR, 0) }, { URDATAD (UFLG, rqc_unit[0].uf, DEV_RDX, 16, 0, RQ_NUMDR, 0, "unit flags, units 0 to 3") },
{ URDATA (CAPAC, rqc_unit[0].capac, 10, T_ADDR_W, 0, RQ_NUMDR, PV_LEFT | REG_HRO) }, { URDATA (CAPAC, rqc_unit[0].capac, 10, T_ADDR_W, 0, RQ_NUMDR, PV_LEFT | REG_HRO) },
{ GRDATA (DEVADDR, rqc_dib.ba, DEV_RDX, 32, 0), REG_HRO }, { GRDATA (DEVADDR, rqc_dib.ba, DEV_RDX, 32, 0), REG_HRO },
{ GRDATA (DEVVEC, rqc_dib.vec, DEV_RDX, 16, 0), REG_HRO }, { GRDATA (DEVVEC, rqc_dib.vec, DEV_RDX, 16, 0), REG_HRO },
{ NULL } { NULL }
}; };
@ -1162,7 +1162,7 @@ DEVICE rqc_dev = {
NULL, NULL, &rq_reset, NULL, NULL, &rq_reset,
&rq_boot, &rq_attach, &rq_detach, &rq_boot, &rq_attach, &rq_detach,
&rqc_dib, DEV_DISABLE | DEV_DIS | DEV_UBUS | DEV_QBUS | DEV_DEBUG | DEV_DISK, &rqc_dib, DEV_DISABLE | DEV_DIS | DEV_UBUS | DEV_QBUS | DEV_DEBUG | DEV_DISK,
0, rq_debug, NULL, NULL, NULL, NULL, NULL, 0, rq_debug, NULL, NULL, &rq_help, NULL, NULL,
&rq_description &rq_description
}; };
@ -1195,39 +1195,39 @@ UNIT rqd_unit[] = {
}; };
REG rqd_reg[] = { REG rqd_reg[] = {
{ GRDATA (UBASE, rqd_ctx.ubase, DEV_RDX, 8, 0), REG_RO }, { GRDATAD (UBASE, rqd_ctx.ubase, DEV_RDX, 8, 0, "unit base"), REG_RO },
{ GRDATA (SA, rqd_ctx.sa, DEV_RDX, 16, 0) }, { GRDATAD (SA, rqd_ctx.sa, DEV_RDX, 16, 0, "status/address register") },
{ GRDATA (SAW, rqd_ctx.saw, DEV_RDX, 16, 0) }, { GRDATAD (SAW, rqd_ctx.saw, DEV_RDX, 16, 0, "written data") },
{ GRDATA (S1DAT, rqd_ctx.s1dat, DEV_RDX, 16, 0) }, { GRDATAD (S1DAT, rqd_ctx.s1dat, DEV_RDX, 16, 0, "step 1 init host data") },
{ GRDATA (COMM, rqd_ctx.comm, DEV_RDX, 22, 0) }, { GRDATAD (COMM, rqd_ctx.comm, DEV_RDX, 22, 0, "comm region") },
{ GRDATA (CQIOFF, rqd_ctx.cq.ioff, DEV_RDX, 32, 0) }, { GRDATAD (CQIOFF, rqd_ctx.cq.ioff, DEV_RDX, 32, 0, "command queue intr offset") },
{ GRDATA (CQBA, rqd_ctx.cq.ba, DEV_RDX, 22, 0) }, { GRDATAD (CQBA, rqd_ctx.cq.ba, DEV_RDX, 22, 0, "command queue base address") },
{ GRDATA (CQLNT, rqd_ctx.cq.lnt, DEV_RDX, 32, 2), REG_NZ }, { GRDATAD (CQLNT, rqd_ctx.cq.lnt, DEV_RDX, 32, 2, "command queue length"), REG_NZ },
{ GRDATA (CQIDX, rqd_ctx.cq.idx, DEV_RDX, 8, 2) }, { GRDATAD (CQIDX, rqd_ctx.cq.idx, DEV_RDX, 8, 2, "command queue index") },
{ GRDATA (RQIOFF, rqd_ctx.rq.ioff, DEV_RDX, 32, 0) }, { GRDATAD (RQIOFF, rqd_ctx.rq.ioff, DEV_RDX, 32, 0, "request queue intr offset") },
{ GRDATA (RQBA, rqd_ctx.rq.ba, DEV_RDX, 22, 0) }, { GRDATAD (RQBA, rqd_ctx.rq.ba, DEV_RDX, 22, 0, "request queue base address") },
{ GRDATA (RQLNT, rqd_ctx.rq.lnt, DEV_RDX, 32, 2), REG_NZ }, { GRDATAD (RQLNT, rqd_ctx.rq.lnt, DEV_RDX, 32, 2, "request queue length"), REG_NZ },
{ GRDATA (RQIDX, rqd_ctx.rq.idx, DEV_RDX, 8, 2) }, { GRDATAD (RQIDX, rqd_ctx.rq.idx, DEV_RDX, 8, 2, "request queue index") },
{ DRDATA (FREE, rqd_ctx.freq, 5) }, { DRDATAD (FREE, rqd_ctx.freq, 5, "head of free packet list") },
{ DRDATA (RESP, rqd_ctx.rspq, 5) }, { DRDATAD (RESP, rqd_ctx.rspq, 5, "head of response packet list") },
{ DRDATA (PBSY, rqd_ctx.pbsy, 5) }, { DRDATAD (PBSY, rqd_ctx.pbsy, 5, "number of busy packets") },
{ GRDATA (CFLGS, rqd_ctx.cflgs, DEV_RDX, 16, 0) }, { GRDATAD (CFLGS, rqd_ctx.cflgs, DEV_RDX, 16, 0, "controller flags") },
{ GRDATA (CSTA, rqd_ctx.csta, DEV_RDX, 4, 0) }, { GRDATAD (CSTA, rqd_ctx.csta, DEV_RDX, 4, 0, "controller state") },
{ GRDATA (PERR, rqd_ctx.perr, DEV_RDX, 9, 0) }, { GRDATAD (PERR, rqd_ctx.perr, DEV_RDX, 9, 0, "port error number") },
{ DRDATA (CRED, rqd_ctx.credits, 5) }, { DRDATAD (CRED, rqd_ctx.credits, 5, "host credits") },
{ DRDATA (HAT, rqd_ctx.hat, 17) }, { DRDATAD (HAT, rqd_ctx.hat, 17, "host available timer") },
{ DRDATA (HTMO, rqd_ctx.htmo, 17) }, { DRDATAD (HTMO, rqd_ctx.htmo, 17, "host timeout value") },
{ FLDATA (PRGI, rqd_ctx.prgi, 0), REG_HIDDEN }, { FLDATA (PRGI, rqd_ctx.prgi, 0), REG_HIDDEN },
{ FLDATA (PIP, rqd_ctx.pip, 0), REG_HIDDEN }, { FLDATA (PIP, rqd_ctx.pip, 0), REG_HIDDEN },
{ FLDATA (CTYPE, rqd_ctx.ctype, 32), REG_HIDDEN }, { FLDATA (CTYPE, rqd_ctx.ctype, 32), REG_HIDDEN },
{ BRDATA (PKTS, rqd_ctx.pak, DEV_RDX, 16, sizeof(rqd_ctx.pak)/2) }, { BRDATAD (PKTS, rqd_ctx.pak, DEV_RDX, 16, sizeof(rq_ctx.pak)/2, "packet buffers, 33W each, 32 entries") },
{ URDATA (CPKT, rqd_unit[0].cpkt, 10, 5, 0, RQ_NUMDR, 0) }, { URDATAD (CPKT, rqd_unit[0].cpkt, 10, 5, 0, RQ_NUMDR, 0, "current packet, units 0 to 3") },
{ URDATA (UCNUM, rqd_unit[0].cnum, 10, 5, 0, RQ_NUMDR, 0) }, { URDATAD (UCNUM, rqd_unit[0].cnum, 10, 5, 0, RQ_NUMDR, 0, "ctrl number, units 0 to 3") },
{ URDATA (PKTQ, rqd_unit[0].pktq, 10, 5, 0, RQ_NUMDR, 0) }, { URDATAD (PKTQ, rqd_unit[0].pktq, 10, 5, 0, RQ_NUMDR, 0, "packet queue, units 0 to 3") },
{ URDATA (UFLG, rqd_unit[0].uf, DEV_RDX, 16, 0, RQ_NUMDR, 0) }, { URDATAD (UFLG, rqd_unit[0].uf, DEV_RDX, 16, 0, RQ_NUMDR, 0, "unit flags, units 0 to 3") },
{ URDATA (CAPAC, rqd_unit[0].capac, 10, T_ADDR_W, 0, RQ_NUMDR, PV_LEFT | REG_HRO) }, { URDATA (CAPAC, rqd_unit[0].capac, 10, T_ADDR_W, 0, RQ_NUMDR, PV_LEFT | REG_HRO) },
{ GRDATA (DEVADDR, rqd_dib.ba, DEV_RDX, 32, 0), REG_HRO }, { GRDATA (DEVADDR, rqd_dib.ba, DEV_RDX, 32, 0), REG_HRO },
{ GRDATA (DEVVEC, rqd_dib.vec, DEV_RDX, 16, 0), REG_HRO }, { GRDATA (DEVVEC, rqd_dib.vec, DEV_RDX, 16, 0), REG_HRO },
{ NULL } { NULL }
}; };
@ -1237,7 +1237,7 @@ DEVICE rqd_dev = {
NULL, NULL, &rq_reset, NULL, NULL, &rq_reset,
&rq_boot, &rq_attach, &rq_detach, &rq_boot, &rq_attach, &rq_detach,
&rqd_dib, DEV_DISABLE | DEV_DIS | DEV_UBUS | DEV_QBUS | DEV_DEBUG | DEV_DISK, &rqd_dib, DEV_DISABLE | DEV_DIS | DEV_UBUS | DEV_QBUS | DEV_DEBUG | DEV_DISK,
0, rq_debug, NULL, NULL, NULL, NULL, NULL, 0, rq_debug, NULL, NULL, &rq_help, NULL, NULL,
&rq_description &rq_description
}; };
@ -3082,6 +3082,40 @@ if (val & RQ_SH_UN) {
return SCPE_OK; return SCPE_OK;
} }
t_stat rq_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr)
{
fprintf (st, "UDA50 MSCP Disk Controller (%s)\n\n", dptr->name);
fprintf (st, "The simulator implements four MSCP disk controllers, RQ, RQB, RQC, RQD.\n");
fprintf (st, "Initially, RQB, RQC, and RQD are disabled. Each RQ controller simulates\n");
fprintf (st, "an MSCP disk controller with four drives. The MSCP controller type can be\n");
fprintf (st, "specified as one of RQDX3, UDA50, KLESI or RUX50. RQ options include the\n");
fprintf (st, "ability to set units write enabled or write locked, and to set the drive\n");
fprintf (st, "type to one of many disk types:\n");
fprint_set_help (st, dptr);
fprintf (st, "set RQn RAUSER{=n} Set disk type to RA82 with n MB's\n");
fprintf (st, "set -L RQn RAUSER{=n} Set disk type to RA82 with n LBN's\n\n");
fprintf (st, "The type options can be used only when a unit is not attached to a file.\n");
fprintf (st, "RAUSER is a \"user specified\" disk; the user can specify the size of the\n");
fprintf (st, "disk in either MB (1000000 bytes) or logical block numbers (LBN's, 512 bytes\n");
fprintf (st, "each). The minimum size is 5MB; the maximum size is 2GB without extended\n");
fprintf (st, "file support, 1TB with extended file support.\n\n");
fprintf (st, "The %s controllers support the BOOT command.\n\n", dptr->name);
fprint_show_help (st, dptr);
fprint_reg_help (st, dptr);
fprintf (st, "\nWhile VMS is not timing sensitive, most of the BSD-derived operating systems\n");
fprintf (st, "(NetBSD, OpenBSD, etc) are. The QTIME and XTIME parameters are set to values\n");
fprintf (st, "that allow these operating systems to run correctly.\n\n");
fprintf (st, "\nError handling is as follows:\n\n");
fprintf (st, " error processed as\n");
fprintf (st, " not attached disk not ready\n");
fprintf (st, " end of file assume rest of disk is zero\n");
fprintf (st, " OS I/O error report error and stop\n");
fprintf (st, "\nDisk drives on the %s device can be attacbed to simulated storage in the\n");
fprintf (st, "following ways:\n\n", dptr->name);
sim_disk_attach_help (st, dptr, uptr, flag, cptr);
return SCPE_OK;
}
char *rq_description (DEVICE *dptr) char *rq_description (DEVICE *dptr)
{ {
static char buf[80]; static char buf[80];

100
PDP11/pdp11_tq.c
View file

@ -359,6 +359,7 @@ t_stat tq_show_ctrl (FILE *st, UNIT *uptr, int32 val, void *desc);
t_stat tq_show_unitq (FILE *st, UNIT *uptr, int32 val, void *desc); t_stat tq_show_unitq (FILE *st, UNIT *uptr, int32 val, void *desc);
t_stat tq_set_type (UNIT *uptr, int32 val, char *cptr, void *desc); t_stat tq_set_type (UNIT *uptr, int32 val, char *cptr, void *desc);
t_stat tq_show_type (FILE *st, UNIT *uptr, int32 val, void *desc); t_stat tq_show_type (FILE *st, UNIT *uptr, int32 val, void *desc);
static t_stat tq_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr);
char *tq_description (DEVICE *dptr); char *tq_description (DEVICE *dptr);
t_bool tq_step4 (void); t_bool tq_step4 (void);
@ -432,44 +433,44 @@ UNIT tq_unit[] = {
#define TQ_QUEUE (TQ_TIMER + 1) #define TQ_QUEUE (TQ_TIMER + 1)
REG tq_reg[] = { REG tq_reg[] = {
{ GRDATA (SA, tq_sa, DEV_RDX, 16, 0) }, { GRDATAD (SA, tq_sa, DEV_RDX, 16, 0, "status/address register") },
{ GRDATA (SAW, tq_saw, DEV_RDX, 16, 0) }, { GRDATAD (SAW, tq_saw, DEV_RDX, 16, 0, "written data") },
{ GRDATA (S1DAT, tq_s1dat, DEV_RDX, 16, 0) }, { GRDATAD (S1DAT, tq_s1dat, DEV_RDX, 16, 0, "step 1 init host data") },
{ GRDATA (CQIOFF, tq_cq.ioff, DEV_RDX, 32, 0) }, { GRDATAD (CQIOFF, tq_cq.ioff, DEV_RDX, 32, 0, "command queue intr offset") },
{ GRDATA (CQBA, tq_cq.ba, DEV_RDX, 22, 0) }, { GRDATAD (CQBA, tq_cq.ba, DEV_RDX, 22, 0, "command queue base address") },
{ GRDATA (CQLNT, tq_cq.lnt, DEV_RDX, 8, 2), REG_NZ }, { GRDATAD (CQLNT, tq_cq.lnt, DEV_RDX, 8, 2, "command queue length"), REG_NZ },
{ GRDATA (CQIDX, tq_cq.idx, DEV_RDX, 8, 2) }, { GRDATAD (CQIDX, tq_cq.idx, DEV_RDX, 8, 2, "command queue index") },
{ GRDATA (TQIOFF, tq_rq.ioff, DEV_RDX, 32, 0) }, { GRDATAD (TQIOFF, tq_rq.ioff, DEV_RDX, 32, 0, "request queue intr offset") },
{ GRDATA (TQBA, tq_rq.ba, DEV_RDX, 22, 0) }, { GRDATAD (TQBA, tq_rq.ba, DEV_RDX, 22, 0, "request queue base address") },
{ GRDATA (TQLNT, tq_rq.lnt, DEV_RDX, 8, 2), REG_NZ }, { GRDATAD (TQLNT, tq_rq.lnt, DEV_RDX, 8, 2, "request queue length"), REG_NZ },
{ GRDATA (TQIDX, tq_rq.idx, DEV_RDX, 8, 2) }, { GRDATAD (TQIDX, tq_rq.idx, DEV_RDX, 8, 2, "request queue index") },
{ DRDATA (FREE, tq_freq, 5) }, { DRDATAD (FREE, tq_freq, 5, "head of free packet list") },
{ DRDATA (RESP, tq_rspq, 5) }, { DRDATAD (RESP, tq_rspq, 5, "head of response packet list") },
{ DRDATA (PBSY, tq_pbsy, 5) }, { DRDATAD (PBSY, tq_pbsy, 5, "number of busy packets") },
{ GRDATA (CFLGS, tq_cflgs, DEV_RDX, 16, 0) }, { GRDATAD (CFLGS, tq_cflgs, DEV_RDX, 16, 0, "controller flags") },
{ GRDATA (CSTA, tq_csta, DEV_RDX, 4, 0) }, { GRDATAD (CSTA, tq_csta, DEV_RDX, 4, 0, "controller state") },
{ GRDATA (PERR, tq_perr, DEV_RDX, 9, 0) }, { GRDATAD (PERR, tq_perr, DEV_RDX, 9, 0, "port error number") },
{ DRDATA (CRED, tq_credits, 5) }, { DRDATAD (CRED, tq_credits, 5, "host credits") },
{ DRDATA (HAT, tq_hat, 17) }, { DRDATAD (HAT, tq_hat, 17, "host available timer") },
{ DRDATA (HTMO, tq_htmo, 17) }, { DRDATAD (HTMO, tq_htmo, 17, "host timeout value") },
{ URDATA (CPKT, tq_unit[0].cpkt, 10, 5, 0, TQ_NUMDR, 0) }, { URDATAD (CPKT, tq_unit[0].cpkt, 10, 5, 0, TQ_NUMDR, 0, "current packet, units 0 to 3") },
{ URDATA (PKTQ, tq_unit[0].pktq, 10, 5, 0, TQ_NUMDR, 0) }, { URDATAD (PKTQ, tq_unit[0].pktq, 10, 5, 0, TQ_NUMDR, 0, "packet queue, units 0 to 3") },
{ URDATA (UFLG, tq_unit[0].uf, DEV_RDX, 16, 0, TQ_NUMDR, 0) }, { URDATAD (UFLG, tq_unit[0].uf, DEV_RDX, 16, 0, TQ_NUMDR, 0, "unit flags, units 0 to 3") },
{ URDATA (POS, tq_unit[0].pos, 10, T_ADDR_W, 0, TQ_NUMDR, 0) }, { URDATAD (POS, tq_unit[0].pos, 10, T_ADDR_W, 0, TQ_NUMDR, 0, "position, units 0 to 3") },
{ URDATA (OBJP, tq_unit[0].objp, 10, 32, 0, TQ_NUMDR, 0) }, { URDATAD (OBJP, tq_unit[0].objp, 10, 32, 0, TQ_NUMDR, 0, "object position, units 0 to 3") },
{ FLDATA (PRGI, tq_prgi, 0), REG_HIDDEN }, { FLDATA (PRGI, tq_prgi, 0), REG_HIDDEN },
{ FLDATA (PIP, tq_pip, 0), REG_HIDDEN }, { FLDATA (PIP, tq_pip, 0), REG_HIDDEN },
{ FLDATA (INT, IREQ (TQ), INT_V_TQ) }, { FLDATAD (INT, IREQ (TQ), INT_V_TQ, "interrupt pending flag") },
{ DRDATA (ITIME, tq_itime, 24), PV_LEFT + REG_NZ }, { DRDATAD (ITIME, tq_itime, 24, "init time delay, except stage 4"), PV_LEFT + REG_NZ },
{ DRDATA (I4TIME, tq_itime4, 24), PV_LEFT + REG_NZ }, { DRDATAD (I4TIME, tq_itime4, 24, "init stage 4 delay"), PV_LEFT + REG_NZ },
{ DRDATA (QTIME, tq_qtime, 24), PV_LEFT + REG_NZ }, { DRDATAD (QTIME, tq_qtime, 24, "response time for 'immediate' packets"), PV_LEFT + REG_NZ },
{ DRDATA (XTIME, tq_xtime, 24), PV_LEFT + REG_NZ }, { DRDATAD (XTIME, tq_xtime, 24, "response time for data transfers"), PV_LEFT + REG_NZ },
{ DRDATA (RWTIME, tq_rwtime, 32), PV_LEFT + REG_NZ }, { DRDATAD (RWTIME, tq_rwtime, 32, "rewind time 2 sec (adjusted later)"), PV_LEFT + REG_NZ },
{ BRDATA (PKTS, tq_pkt, DEV_RDX, 16, TQ_NPKTS * (TQ_PKT_SIZE_W + 1)) }, { BRDATAD (PKTS, tq_pkt, DEV_RDX, 16, TQ_NPKTS * (TQ_PKT_SIZE_W + 1), "packet buffers, 33W each, 32 entries") },
{ DRDATA (DEVTYPE, tq_typ, 2), REG_HRO }, { DRDATA (DEVTYPE, tq_typ, 2), REG_HRO },
{ DRDATA (DEVCAP, drv_tab[TQU_TYPE].cap, T_ADDR_W), PV_LEFT | REG_HRO }, { DRDATA (DEVCAP, drv_tab[TQU_TYPE].cap, T_ADDR_W), PV_LEFT | REG_HRO },
{ GRDATA (DEVADDR, tq_dib.ba, DEV_RDX, 32, 0), REG_HRO }, { GRDATA (DEVADDR, tq_dib.ba, DEV_RDX, 32, 0), REG_HRO },
{ GRDATA (DEVVEC, tq_dib.vec, DEV_RDX, 16, 0), REG_HRO }, { GRDATA (DEVVEC, tq_dib.vec, DEV_RDX, 16, 0), REG_HRO },
{ NULL } { NULL }
}; };
@ -543,7 +544,7 @@ DEVICE tq_dev = {
&tq_boot, &tq_attach, &tq_detach, &tq_boot, &tq_attach, &tq_detach,
&tq_dib, DEV_DISABLE | DEV_UBUS | DEV_QBUS | DEV_DEBUG | DEV_TAPE, &tq_dib, DEV_DISABLE | DEV_UBUS | DEV_QBUS | DEV_DEBUG | DEV_TAPE,
0, tq_debug, 0, tq_debug,
NULL, NULL, NULL, NULL, NULL, NULL, NULL, &tq_help, NULL, NULL,
&tq_description &tq_description
}; };
@ -2385,6 +2386,27 @@ fprintf (st, "%s (%dMB)", drv_tab[tq_typ].name, (uint32) (drv_tab[tq_typ].cap >>
return SCPE_OK; return SCPE_OK;
} }
t_stat tq_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr)
{
char *devtype = UNIBUS ? "TUK50" : "TQK50";
fprintf (st, "%s (TQ)\n\n", tq_description (dptr));
fprintf (st, "The TQ controller simulates the %s TMSCP disk controller. TQ options\n", devtype);
fprintf (st, "include the ability to set units write enabled or write locked, and to\n");
fprintf (st, "specify the controller type and tape length:\n");
fprint_set_help (st, dptr);
fprintf (st, "\nThe %s device supports the BOOT command.\n", devtype);
fprint_show_help (st, dptr);
fprint_reg_help (st, dptr);
fprintf (st, "\nError handling is as follows:\n\n");
fprintf (st, " error processed as\n");
fprintf (st, " not attached tape not ready\n\n");
fprintf (st, " end of file end of medium\n");
fprintf (st, " OS I/O error fatal tape error\n\n");
sim_tape_attach_help (st, dptr, uptr, flag, cptr);
return SCPE_OK;
}
char *tq_description (DEVICE *dptr) char *tq_description (DEVICE *dptr)
{ {
return (UNIBUS) ? "TUK50 TMSCP magnetic tape controller" : return (UNIBUS) ? "TUK50 TMSCP magnetic tape controller" :

80
PDP11/pdp11_ts.c
View file

@ -296,6 +296,7 @@ int32 ts_updxs0 (int32 t);
void ts_cmpendcmd (int32 s0, int32 s1); void ts_cmpendcmd (int32 s0, int32 s1);
void ts_endcmd (int32 ssf, int32 xs0f, int32 msg); void ts_endcmd (int32 ssf, int32 xs0f, int32 msg);
int32 ts_map_status (t_stat st); int32 ts_map_status (t_stat st);
t_stat ts_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr);
char *ts_description (DEVICE *dptr); char *ts_description (DEVICE *dptr);
/* TS data structures /* TS data structures
@ -316,34 +317,34 @@ DIB ts_dib = {
UNIT ts_unit = { UDATA (&ts_svc, UNIT_ATTABLE + UNIT_ROABLE + UNIT_DISABLE, 0) }; UNIT ts_unit = { UDATA (&ts_svc, UNIT_ATTABLE + UNIT_ROABLE + UNIT_DISABLE, 0) };
REG ts_reg[] = { REG ts_reg[] = {
{ GRDATA (TSSR, tssr, DEV_RDX, 16, 0) }, { GRDATAD (TSSR, tssr, DEV_RDX, 16, 0, "status register") },
{ GRDATA (TSBA, tsba, DEV_RDX, 22, 0) }, { GRDATAD (TSBA, tsba, DEV_RDX, 22, 0, "bus address register") },
{ GRDATA (TSDBX, tsdbx, DEV_RDX, 8, 0) }, { GRDATAD (TSDBX, tsdbx, DEV_RDX, 8, 0, "data buffer extension register") },
{ GRDATA (CHDR, cmdhdr, DEV_RDX, 16, 0) }, { GRDATAD (CHDR, cmdhdr, DEV_RDX, 16, 0, "command packet header") },
{ GRDATA (CADL, cmdadl, DEV_RDX, 16, 0) }, { GRDATAD (CADL, cmdadl, DEV_RDX, 16, 0, "command packet low address or count") },
{ GRDATA (CADH, cmdadh, DEV_RDX, 16, 0) }, { GRDATAD (CADH, cmdadh, DEV_RDX, 16, 0, "command packet high address") },
{ GRDATA (CLNT, cmdlnt, DEV_RDX, 16, 0) }, { GRDATAD (CLNT, cmdlnt, DEV_RDX, 16, 0, "command packet length") },
{ GRDATA (MHDR, msghdr, DEV_RDX, 16, 0) }, { GRDATAD (MHDR, msghdr, DEV_RDX, 16, 0, "message packet header") },
{ GRDATA (MRFC, msgrfc, DEV_RDX, 16, 0) }, { GRDATAD (MRFC, msgrfc, DEV_RDX, 16, 0, "message packet residual frame count") },
{ GRDATA (MXS0, msgxs0, DEV_RDX, 16, 0) }, { GRDATAD (MXS0, msgxs0, DEV_RDX, 16, 0, "message packet extended status 0") },
{ GRDATA (MXS1, msgxs1, DEV_RDX, 16, 0) }, { GRDATAD (MXS1, msgxs1, DEV_RDX, 16, 0, "message packet extended status 1") },
{ GRDATA (MXS2, msgxs2, DEV_RDX, 16, 0) }, { GRDATAD (MXS2, msgxs2, DEV_RDX, 16, 0, "message packet extended status 2") },
{ GRDATA (MXS3, msgxs3, DEV_RDX, 16, 0) }, { GRDATAD (MXS3, msgxs3, DEV_RDX, 16, 0, "message packet extended status 3") },
{ GRDATA (MSX4, msgxs4, DEV_RDX, 16, 0) }, { GRDATAD (MSX4, msgxs4, DEV_RDX, 16, 0, "message packet extended status 4") },
{ GRDATA (WADL, wchadl, DEV_RDX, 16, 0) }, { GRDATAD (WADL, wchadl, DEV_RDX, 16, 0, "write char packet low address") },
{ GRDATA (WADH, wchadh, DEV_RDX, 16, 0) }, { GRDATAD (WADH, wchadh, DEV_RDX, 16, 0, "write char packet high address") },
{ GRDATA (WLNT, wchlnt, DEV_RDX, 16, 0) }, { GRDATAD (WLNT, wchlnt, DEV_RDX, 16, 0, "write char packet length") },
{ GRDATA (WOPT, wchopt, DEV_RDX, 16, 0) }, { GRDATAD (WOPT, wchopt, DEV_RDX, 16, 0, "write char packet options") },
{ GRDATA (WXOPT, wchxopt, DEV_RDX, 16, 0) }, { GRDATAD (WXOPT, wchxopt, DEV_RDX, 16, 0, "write char packet extended options") },
{ FLDATA (INT, IREQ (TS), INT_V_TS) }, { FLDATAD (INT, IREQ (TS), INT_V_TS, "interrupt pending") },
{ FLDATA (ATTN, ts_qatn, 0) }, { FLDATAD (ATTN, ts_qatn, 0, "attention message pending") },
{ FLDATA (BOOT, ts_bcmd, 0) }, { FLDATAD (BOOT, ts_bcmd, 0, "boot request pending") },
{ FLDATA (OWNC, ts_ownc, 0) }, { FLDATAD (OWNC, ts_ownc, 0, "if set, tape owns command buffer") },
{ FLDATA (OWNM, ts_ownm, 0) }, { FLDATAD (OWNM, ts_ownm, 0, "if set, tape owns message buffer") },
{ DRDATA (TIME, ts_time, 24), PV_LEFT + REG_NZ }, { DRDATAD (TIME, ts_time, 24, "delay"), PV_LEFT + REG_NZ },
{ DRDATA (POS, ts_unit.pos, T_ADDR_W), PV_LEFT + REG_RO }, { DRDATAD (POS, ts_unit.pos, T_ADDR_W, "position"), PV_LEFT + REG_RO },
{ GRDATA (DEVADDR, ts_dib.ba, DEV_RDX, 32, 0), REG_HRO }, { GRDATA (DEVADDR, ts_dib.ba, DEV_RDX, 32, 0), REG_HRO },
{ GRDATA (DEVVEC, ts_dib.vec, DEV_RDX, 16, 0), REG_HRO }, { GRDATA (DEVVEC, ts_dib.vec, DEV_RDX, 16, 0), REG_HRO },
{ NULL } { NULL }
}; };
@ -369,7 +370,7 @@ DEVICE ts_dev = {
NULL, NULL, &ts_reset, NULL, NULL, &ts_reset,
&ts_boot, &ts_attach, &ts_detach, &ts_boot, &ts_attach, &ts_detach,
&ts_dib, DEV_DISABLE | TS_DIS | DEV_UBUS | DEV_QBUS | DEV_DEBUG | DEV_TAPE, 0, &ts_dib, DEV_DISABLE | TS_DIS | DEV_UBUS | DEV_QBUS | DEV_DEBUG | DEV_TAPE, 0,
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, &ts_help, NULL, NULL,
&ts_description &ts_description
}; };
@ -1177,6 +1178,27 @@ return SCPE_NOFNC;
} }
#endif #endif
t_stat ts_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr)
{
fprintf (st, "TS11 Magnetic Tape (TS)\n\n");
fprint_set_help (st, dptr);
fprint_show_help (st, dptr);
fprintf (st, "\nThe type options can be used only when a unit is not attached to a file. The\n");
fprintf (st, "bad block option can be used only when a unit is attached to a file.\n");
fprintf (st, "The TS11 does not support the BOOT command.\n");
#if defined (VM_PDP11)
fprintf (st, "The TS11 device supports the BOOT command.\n");
#endif
fprint_reg_help (st, dptr);
fprintf (st, "\nError handling is as follows:\n\n");
fprintf (st, " error processed as\n");
fprintf (st, " not attached tape not ready\n\n");
fprintf (st, " end of file bad tape\n");
fprintf (st, " OS I/O error fatal tape error\n\n");
sim_tape_attach_help (st, dptr, uptr, flag, cptr);
return SCPE_OK;
}
char *ts_description (DEVICE *dptr) char *ts_description (DEVICE *dptr)
{ {
return (UNIBUS) ? "TS11 magnetic tape controller" : return (UNIBUS) ? "TS11 magnetic tape controller" :

3
PDP11/pdp11_vh.c
View file

@ -1586,7 +1586,8 @@ fprintf (st, " sim> SHOW %s CONNECTIONS show current connections\n", dptr->n
fprintf (st, " sim> SHOW %s STATISTICS show statistics for active connections\n", dptr->name); fprintf (st, " sim> SHOW %s STATISTICS show statistics for active connections\n", dptr->name);
fprintf (st, " sim> SET %s DISCONNECT=linenumber disconnects the specified line.\n\n", dptr->name); fprintf (st, " sim> SET %s DISCONNECT=linenumber disconnects the specified line.\n\n", dptr->name);
fprintf (st, "The %s does not support save and restore. All open connections are lost\n", devtype); fprintf (st, "The %s does not support save and restore. All open connections are lost\n", devtype);
fprintf (st, "when the simulator shuts down or the %s is detached.\n", dptr->name); fprintf (st, "when the simulator shuts down or the %s is detached.\n\n", dptr->name);
vh_help_attach (st, dptr, uptr, flag, cptr);
return SCPE_OK; return SCPE_OK;
} }