From 621e97e1708be428c81b32b8aeeef9a1e880c9d2 Mon Sep 17 00:00:00 2001 From: Mark Pizzolato Date: Tue, 30 Apr 2019 14:28:37 -0700 Subject: [PATCH] MicroVAX1, all VAX: Add model specific instruction execution and emulation - Different VAX models had different groups of instructions which were implemented in hardware vs trappng to the OS for emulation. Functionality has been added to differentiate the various mix of instruction groups for different models and to display both the groups and the actual instructions. - Visibility to Instruction groups is provided by SHOW CPU INSTRUCTIONS and the list of the active instructions implemented and emulated via SHOW CPU -V INSTRUCTIONS. - The MicroVAX I CPU handled some execution fault conditions differently from other VAX systems these differences are now specifically handled. - Add build time test support to MicroVAX I running EHKAA v1.13 suggested in #683 - Add more CPU debug details relating to exception and interrupt processing --- VAX/is1000_defs.h | 5 +- VAX/is1000_sysdev.c | 4 +- VAX/tests/ehkaa-uv1.exe | Bin 0 -> 123392 bytes VAX/tests/vax-diag_test.ini | 9 +- VAX/vax410_defs.h | 4 +- VAX/vax410_sysdev.c | 4 +- VAX/vax420_defs.h | 9 +- VAX/vax43_defs.h | 4 +- VAX/vax43_sysdev.c | 4 +- VAX/vax440_defs.h | 7 +- VAX/vax440_sysdev.c | 4 +- VAX/vax610_defs.h | 9 +- VAX/vax610_stddev.c | 2 +- VAX/vax610_sysdev.c | 6 +- VAX/vax630_defs.h | 4 +- VAX/vax630_sysdev.c | 6 +- VAX/vax730_defs.h | 18 +- VAX/vax730_sys.c | 4 +- VAX/vax750_cmi.c | 4 +- VAX/vax750_defs.h | 18 +- VAX/vax780_defs.h | 18 +- VAX/vax780_sbi.c | 6 +- VAX/vax820_bi.c | 4 +- VAX/vax820_defs.h | 4 +- VAX/vax860_abus.c | 4 +- VAX/vax860_defs.h | 18 +- VAX/vax_cis.c | 86 +-- VAX/vax_cmode.c | 2 +- VAX/vax_cpu.c | 257 ++++++++- VAX/vax_cpu1.c | 70 +-- VAX/vax_defs.h | 86 ++- VAX/vax_fpa.c | 28 +- VAX/vax_octa.c | 14 +- VAX/vax_sys.c | 1037 ++++++++++++++++++----------------- VAX/vax_syscm.c | 34 +- VAX/vax_sysdev.c | 2 +- VAX/vaxmod_defs.h | 4 +- 37 files changed, 1048 insertions(+), 751 deletions(-) create mode 100644 VAX/tests/ehkaa-uv1.exe diff --git a/VAX/is1000_defs.h b/VAX/is1000_defs.h index 50548ec4..93953c0e 100644 --- a/VAX/is1000_defs.h +++ b/VAX/is1000_defs.h @@ -79,8 +79,7 @@ /* CPU */ -#define CPU_MODEL_MODIFIERS \ - { 0 } +#define CPU_MODEL_MODIFIERS /* Memory */ @@ -157,7 +156,7 @@ #define LP_MBZ84_TEST(r) #define LP_MBZ92_TEST(r) -#define MT_AST_TEST(r) if ((r) > AST_MAX) RSVD_OPND_FAULT +#define MT_AST_TEST(r) if ((r) > AST_MAX) RSVD_OPND_FAULT(MT_AST_TEST) /* Common CSI flags */ diff --git a/VAX/is1000_sysdev.c b/VAX/is1000_sysdev.c index 6354fb01..7ab7ff7a 100644 --- a/VAX/is1000_sysdev.c +++ b/VAX/is1000_sysdev.c @@ -582,7 +582,7 @@ switch (rg) { break; default: - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(ReadIPR); } return val; @@ -627,7 +627,7 @@ switch (rg) { break; default: - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(WriteIPR); } return; diff --git a/VAX/tests/ehkaa-uv1.exe b/VAX/tests/ehkaa-uv1.exe new file mode 100644 index 0000000000000000000000000000000000000000..5a38546211816beca1190693458d96fdf87d8b5a GIT binary patch literal 123392 zcmdqK2YeJo|3AKaNic+xMwdW9Kv5o@1yNK$K!IR;?s9j@1tJ0#dc;oh$Z;wvSO|y( zk!Aq_l^`O54Mb5u!tUV_>K#Qukg}mD2+8g5{h8Ul+aUV&`Ip!0_xo+KH#494wCSIn zot@D>$o7Psk+L(cP_Fh=pdz=tG$2V*t~=vI<2kJ)DPRI6KnbXM=1A|#0cD2_tp5wH z#&c@PQXrzAPILsEJDlkeJ;gA_!?%BOwR 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z9TBj|tGRe|FD|4oF6{H#2(Zd{Eh`Lp&474ac){z!u-91dS}f=&USl!6#)8*{eO?!ayeynVyC1I~i46jQJuS-m?OZvR#X(+TdUdu{CUNazGmt63=BVMSn#@}&+8Id-jb8999a~VEq1wv(vZY)CbQ?Ws>y~vfUY5C~4+VEwXkF~iHDWF2YrNzl%H?$#YbjdzLhE9m+gM6*(D>ah zV_}S!?%ZVYzr4WjT12Icj-xZfD`U4m$+*<0^!wdOvNR^2-Ls6fF)MDjaj}6u6i7|v za2qRQ8FyCrV#DuBmUAS|`zu_dWodlj;iDVtTX@)kClcB;9uFEa(e<<^>Zp1j?TI?7Ubair(e;c&)Y0{{C+6sS+7oe9 zy=?a)@yca%RC~9>_yoqRzaY1vP=@6FU>5rH#XO)7yG|B|gZ07E7x#cZ;z3{J11vuK zSXmlM(r1|;VP^68RU1$A@JMCWTAuQh^X=7HeIlx5*yy=1^}(nt2P+hl$_nxVF d!1tcTIPBnnY{-FJm AST_MAX) RSVD_OPND_FAULT +#define MT_AST_TEST(r) if ((r) > AST_MAX) RSVD_OPND_FAULT(MT_AST_TEST) /* Common CSI flags */ diff --git a/VAX/vax410_sysdev.c b/VAX/vax410_sysdev.c index b152660d..daf4d2b7 100644 --- a/VAX/vax410_sysdev.c +++ b/VAX/vax410_sysdev.c @@ -484,7 +484,7 @@ switch (rg) { break; default: - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(ReadIPR); } return val; @@ -516,7 +516,7 @@ switch (rg) { break; default: - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(WriteIPR); } return; diff --git a/VAX/vax420_defs.h b/VAX/vax420_defs.h index 906a5512..83b7a5a7 100644 --- a/VAX/vax420_defs.h +++ b/VAX/vax420_defs.h @@ -84,17 +84,16 @@ /* CPU */ #if defined (VAX_411) || defined (VAX_412) -#define CPU_MODEL_MODIFIERS \ - { 0 } +#define CPU_MODEL_MODIFIERS #else #if defined (VAX_41A) || defined (VAX_41D) #define CPU_MODEL_MODIFIERS \ { MTAB_XTD|MTAB_VDV, 0, "MODEL", "MODEL={MICROVAX|VAXSERVER}", \ - cpu_set_model, &cpu_show_model, NULL, "Set/Show the simulator CPU Model" } + cpu_set_model, &cpu_show_model, NULL, "Set/Show the simulator CPU Model" }, #else /* defined (VAX_42A) || defined (VAX_42B) */ #define CPU_MODEL_MODIFIERS \ { MTAB_XTD|MTAB_VDV, 0, "MODEL", "MODEL={MICROVAX|VAXSTATION|VAXSTATIONGPX|VAXSTATIONSPX}", \ - cpu_set_model, &cpu_show_model, NULL, "Set/Show the simulator CPU Model" } + cpu_set_model, &cpu_show_model, NULL, "Set/Show the simulator CPU Model" }, #endif #endif @@ -235,7 +234,7 @@ #define LP_MBZ84_TEST(r) #define LP_MBZ92_TEST(r) -#define MT_AST_TEST(r) if ((r) > AST_MAX) RSVD_OPND_FAULT +#define MT_AST_TEST(r) if ((r) > AST_MAX) RSVD_OPND_FAULT(MT_AST_TEST) /* Common CSI flags */ diff --git a/VAX/vax43_defs.h b/VAX/vax43_defs.h index ed9945c1..8427717a 100644 --- a/VAX/vax43_defs.h +++ b/VAX/vax43_defs.h @@ -93,7 +93,7 @@ #define CPU_MODEL_MODIFIERS \ { MTAB_XTD|MTAB_VDV, 0, "MODEL", "MODEL={MICROVAX|VAXSTATION|VAXSTATIONSPX}", \ - cpu_set_model, &cpu_show_model, NULL, "Set/Show the simulator CPU Model" } + cpu_set_model, &cpu_show_model, NULL, "Set/Show the simulator CPU Model" }, /* Memory */ @@ -230,7 +230,7 @@ #define LP_MBZ84_TEST(r) #define LP_MBZ92_TEST(r) -#define MT_AST_TEST(r) if ((r) > AST_MAX) RSVD_OPND_FAULT +#define MT_AST_TEST(r) if ((r) > AST_MAX) RSVD_OPND_FAULT(MT_AST_TEST) /* Common CSI flags */ diff --git a/VAX/vax43_sysdev.c b/VAX/vax43_sysdev.c index 956db4d6..27b2d652 100644 --- a/VAX/vax43_sysdev.c +++ b/VAX/vax43_sysdev.c @@ -603,7 +603,7 @@ switch (rg) { break; default: - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(ReadIPR); } return val; @@ -666,7 +666,7 @@ switch (rg) { break; default: - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(WriteIPR); } return; diff --git a/VAX/vax440_defs.h b/VAX/vax440_defs.h index 00c8ac20..a82fb4b7 100644 --- a/VAX/vax440_defs.h +++ b/VAX/vax440_defs.h @@ -98,10 +98,9 @@ #if defined (VAX_46) || defined (VAX_48) #define CPU_MODEL_MODIFIERS \ { MTAB_XTD|MTAB_VDV, 0, "MODEL", "MODEL={MICROVAX|VAXSTATION}", \ - cpu_set_model, &cpu_show_model, NULL, "Set/Show the simulator CPU Model" } + cpu_set_model, &cpu_show_model, NULL, "Set/Show the simulator CPU Model" }, #else -#define CPU_MODEL_MODIFIERS \ - { 0 } +#define CPU_MODEL_MODIFIERS #endif /* Memory */ @@ -210,7 +209,7 @@ #define LP_MBZ84_TEST(r) #define LP_MBZ92_TEST(r) -#define MT_AST_TEST(r) if ((r) > AST_MAX) RSVD_OPND_FAULT +#define MT_AST_TEST(r) if ((r) > AST_MAX) RSVD_OPND_FAULT(MT_AST_TEST) /* Common CSI flags */ diff --git a/VAX/vax440_sysdev.c b/VAX/vax440_sysdev.c index a372a527..9382514e 100644 --- a/VAX/vax440_sysdev.c +++ b/VAX/vax440_sysdev.c @@ -519,7 +519,7 @@ switch (rg) { break; default: - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(ReadIPR); } return val; @@ -576,7 +576,7 @@ switch (rg) { break; default: - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(WriteIPR); } return; diff --git a/VAX/vax610_defs.h b/VAX/vax610_defs.h index 9b3ab3eb..da787c15 100644 --- a/VAX/vax610_defs.h +++ b/VAX/vax610_defs.h @@ -96,7 +96,12 @@ #define CPU_MODEL_MODIFIERS { MTAB_XTD|MTAB_VDV, 0, "LEDS", NULL, \ NULL, &cpu_show_leds, NULL, "Display the CPU LED values" }, \ { MTAB_XTD|MTAB_VDV, 0, "MODEL", "MODEL={MicroVAX|VAXStation}", \ - &cpu_set_model, &cpu_show_model, NULL, "Set/Show the simulator CPU Model" } + &cpu_set_model, &cpu_show_model, NULL, "Set/Show the simulator CPU Model" }, +#define CPU_INSTRUCTION_SET (VAX_BASE | VAX_GFLOAT) +#define CPU_INST_MODIFIERS { MTAB_XTD|MTAB_VDV|MTAB_VALR|MTAB_NMO, 0, "INSTRUCTIONS", "INSTRUCTIONS={G-FLOAT|NOG-FLOAT|D-FLOAT|NOD-FLOAT}", \ + &cpu_set_instruction_set, NULL, NULL, "Set the CPU Instruction Set" }, \ + { MTAB_XTD|MTAB_VDV, 0, "INSTRUCTIONS", NULL, \ + NULL, &cpu_show_instruction_set, NULL, "Show the CPU Instruction Set (SHOW -V)" }, /* QVSS memory space */ @@ -150,7 +155,7 @@ extern t_stat cpu_show_memory (FILE* st, UNIT* uptr, int32 val, CONST void* desc #define LP_MBZ84_TEST(r) #define LP_MBZ92_TEST(r) -#define MT_AST_TEST(r) if ((r) > AST_MAX) RSVD_OPND_FAULT +#define MT_AST_TEST(r) if ((r) > AST_MAX) RSVD_OPND_FAULT(MT_AST_TEST) #define IDX_IMM_TEST /* Qbus I/O modes */ diff --git a/VAX/vax610_stddev.c b/VAX/vax610_stddev.c index 0f2df00f..cf0d119e 100644 --- a/VAX/vax610_stddev.c +++ b/VAX/vax610_stddev.c @@ -312,7 +312,7 @@ if (sel == TXDB_MISC) { /* misc function? */ } else if (sel != 0) - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(txdb_func); } diff --git a/VAX/vax610_sysdev.c b/VAX/vax610_sysdev.c index 16e34d30..2e88481a 100644 --- a/VAX/vax610_sysdev.c +++ b/VAX/vax610_sysdev.c @@ -184,7 +184,7 @@ switch (rg) { break; default: - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(ReadIPR); } return val; @@ -223,7 +223,7 @@ switch (rg) { case MT_CONISP: case MT_CONPC: case MT_CONPSL: /* halt reg */ - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(WriteIPR); case MT_NICR: /* NICR */ case MT_ICR: /* ICR */ @@ -249,7 +249,7 @@ switch (rg) { break; default: - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(WriteIPR); } return; diff --git a/VAX/vax630_defs.h b/VAX/vax630_defs.h index 28e9962d..88788f81 100644 --- a/VAX/vax630_defs.h +++ b/VAX/vax630_defs.h @@ -108,7 +108,7 @@ { MTAB_XTD|MTAB_VDV|MTAB_NMO, 1, "NOAUTOBOOT", "NOAUTOBOOT", \ &sysd_set_halt, &sysd_show_halt, NULL, "Disable autoboot (Enable Halt)" }, \ { MTAB_XTD|MTAB_VDV, 0, "LEDS", NULL, \ - NULL, &sysd_show_leds, NULL, "Display the CPU LED values" } + NULL, &sysd_show_leds, NULL, "Display the CPU LED values" }, /* Memory */ @@ -215,7 +215,7 @@ extern uint32 va_addr; /* QDSS memory offset */ #define LP_MBZ84_TEST(r) #define LP_MBZ92_TEST(r) -#define MT_AST_TEST(r) if ((r) > AST_MAX) RSVD_OPND_FAULT +#define MT_AST_TEST(r) if ((r) > AST_MAX) RSVD_OPND_FAULT(MT_AST_TEST) /* Qbus I/O modes */ diff --git a/VAX/vax630_sysdev.c b/VAX/vax630_sysdev.c index ea111ea6..1d180289 100644 --- a/VAX/vax630_sysdev.c +++ b/VAX/vax630_sysdev.c @@ -609,7 +609,7 @@ switch (rg) { break; default: - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(ReadIPR); } return val; @@ -648,7 +648,7 @@ switch (rg) { case MT_CONISP: case MT_CONPC: case MT_CONPSL: /* halt reg */ - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(WriteIPR); case MT_NICR: /* NICR */ case MT_ICR: /* ICR */ @@ -674,7 +674,7 @@ switch (rg) { break; default: - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(WriteIPR); } return; diff --git a/VAX/vax730_defs.h b/VAX/vax730_defs.h index 76fc558d..a6b48938 100644 --- a/VAX/vax730_defs.h +++ b/VAX/vax730_defs.h @@ -104,24 +104,24 @@ /* 780 microcode patch 37 - only test LR<23:0> for appropriate length */ -#define ML_LR_TEST(r) if (((uint32)((r) & 0xFFFFFF)) > 0x200000) RSVD_OPND_FAULT +#define ML_LR_TEST(r) if (((uint32)((r) & 0xFFFFFF)) > 0x200000) RSVD_OPND_FAULT(ML_LR_TEST) /* 780 microcode patch 38 - only test PxBR<31>=1, PxBR<30> = 0, and xBR<1:0> = 0 */ #define ML_PXBR_TEST(r) if (((((uint32)(r)) & 0x80000000) == 0) || \ - ((((uint32)(r)) & 0x40000003) != 0)) RSVD_OPND_FAULT -#define ML_SBR_TEST(r) if ((((uint32)(r)) & 0x00000003) != 0) RSVD_OPND_FAULT + ((((uint32)(r)) & 0x40000003) != 0)) RSVD_OPND_FAULT(ML_PXBR_TEST) +#define ML_SBR_TEST(r) if ((((uint32)(r)) & 0x00000003) != 0) RSVD_OPND_FAULT(ML_SBR_TEST) /* 780 microcode patch 78 - test xCBB<1:0> = 0 */ -#define ML_PA_TEST(r) if ((((uint32)(r)) & 0x00000003) != 0) RSVD_OPND_FAULT +#define ML_PA_TEST(r) if ((((uint32)(r)) & 0x00000003) != 0) RSVD_OPND_FAULT(ML_PA_TEST) -#define LP_AST_TEST(r) if ((r) > AST_MAX) RSVD_OPND_FAULT -#define LP_MBZ84_TEST(r) if ((((uint32)(r)) & 0xF8C00000) != 0) RSVD_OPND_FAULT -#define LP_MBZ92_TEST(r) if ((((uint32)(r)) & 0x7FC00000) != 0) RSVD_OPND_FAULT +#define LP_AST_TEST(r) if ((r) > AST_MAX) RSVD_OPND_FAULT(LP_AST_TEST) +#define LP_MBZ84_TEST(r) if ((((uint32)(r)) & 0xF8C00000) != 0) RSVD_OPND_FAULT(LP_MBZ84_TEST) +#define LP_MBZ92_TEST(r) if ((((uint32)(r)) & 0x7FC00000) != 0) RSVD_OPND_FAULT(LP_MBZ92_TEST) #define MT_AST_TEST(r) r = (r) & 07; \ - if ((r) > AST_MAX) RSVD_OPND_FAULT + if ((r) > AST_MAX) RSVD_OPND_FAULT(MT_AST_TEST) #define IDX_IMM_TEST /* Memory */ @@ -142,7 +142,7 @@ extern t_stat cpu_show_memory (FILE* st, UNIT* uptr, int32 val, CONST void* desc); #define CPU_MODEL_MODIFIERS \ { MTAB_XTD|MTAB_VDV, 0, "MODEL", NULL, \ - NULL, &cpu_show_model, NULL, "Display the simulator CPU Model" } + NULL, &cpu_show_model, NULL, "Display the simulator CPU Model" }, /* Unibus I/O registers */ diff --git a/VAX/vax730_sys.c b/VAX/vax730_sys.c index 0059a951..17d98fb8 100644 --- a/VAX/vax730_sys.c +++ b/VAX/vax730_sys.c @@ -289,7 +289,7 @@ switch (rg) { break; default: - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(ReadIPR); } return val; @@ -355,7 +355,7 @@ switch (rg) { break; default: - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(WriteIPR); } return; diff --git a/VAX/vax750_cmi.c b/VAX/vax750_cmi.c index bfc0ab00..64f99b3b 100644 --- a/VAX/vax750_cmi.c +++ b/VAX/vax750_cmi.c @@ -349,7 +349,7 @@ switch (rg) { break; default: - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(ReadIPR); } return val; @@ -418,7 +418,7 @@ switch (rg) { break; default: - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(WriteIPR); } return; diff --git a/VAX/vax750_defs.h b/VAX/vax750_defs.h index 5d4f8c10..14301ba4 100644 --- a/VAX/vax750_defs.h +++ b/VAX/vax750_defs.h @@ -125,24 +125,24 @@ /* 780 microcode patch 37 - only test LR<23:0> for appropriate length */ -#define ML_LR_TEST(r) if (((uint32)((r) & 0xFFFFFF)) > 0x200000) RSVD_OPND_FAULT +#define ML_LR_TEST(r) if (((uint32)((r) & 0xFFFFFF)) > 0x200000) RSVD_OPND_FAULT(ML_LR_TEST) /* 780 microcode patch 38 - only test PxBR<31>=1, PxBR<30> = 0, and xBR<1:0> = 0 */ #define ML_PXBR_TEST(r) if (((((uint32)(r)) & 0x80000000) == 0) || \ - ((((uint32)(r)) & 0x40000003) != 0)) RSVD_OPND_FAULT -#define ML_SBR_TEST(r) if ((((uint32)(r)) & 0x00000003) != 0) RSVD_OPND_FAULT + ((((uint32)(r)) & 0x40000003) != 0)) RSVD_OPND_FAULT(ML_PXBR_TEST) +#define ML_SBR_TEST(r) if ((((uint32)(r)) & 0x00000003) != 0) RSVD_OPND_FAULT(ML_SBR_TEST) /* 780 microcode patch 78 - test xCBB<1:0> = 0 */ -#define ML_PA_TEST(r) if ((((uint32)(r)) & 0x00000003) != 0) RSVD_OPND_FAULT +#define ML_PA_TEST(r) if ((((uint32)(r)) & 0x00000003) != 0) RSVD_OPND_FAULT(ML_PA_TEST) -#define LP_AST_TEST(r) if ((r) > AST_MAX) RSVD_OPND_FAULT -#define LP_MBZ84_TEST(r) if ((((uint32)(r)) & 0xF8C00000) != 0) RSVD_OPND_FAULT -#define LP_MBZ92_TEST(r) if ((((uint32)(r)) & 0x7FC00000) != 0) RSVD_OPND_FAULT +#define LP_AST_TEST(r) if ((r) > AST_MAX) RSVD_OPND_FAULT(LP_AST_TEST) +#define LP_MBZ84_TEST(r) if ((((uint32)(r)) & 0xF8C00000) != 0) RSVD_OPND_FAULT(LP_MBZ84_TEST) +#define LP_MBZ92_TEST(r) if ((((uint32)(r)) & 0x7FC00000) != 0) RSVD_OPND_FAULT(LP_MBZ92_TEST) #define MT_AST_TEST(r) r = (r) & 07; \ - if ((r) > AST_MAX) RSVD_OPND_FAULT + if ((r) > AST_MAX) RSVD_OPND_FAULT(MT_AST_TEST) #define IDX_IMM_TEST /* Memory */ @@ -168,7 +168,7 @@ extern t_stat cpu_show_memory (FILE* st, UNIT* uptr, int32 val, CONST void* desc #define CPU_MODEL_MODIFIERS { MTAB_XTD|MTAB_VDV, 0, "MODEL", NULL, \ NULL, &cpu_show_model, NULL, "Display the simulator CPU Model" }, \ { MTAB_XTD|MTAB_VDV, 0, "BOOTDEV", "BOOTDEV={A|B|C|D}", \ - &vax750_set_bootdev, &vax750_show_bootdev, NULL, "Set Boot Device" } + &vax750_set_bootdev, &vax750_show_bootdev, NULL, "Set Boot Device" }, extern t_stat vax750_set_bootdev (UNIT *uptr, int32 val, CONST char *cptr, void *desc); extern t_stat vax750_show_bootdev (FILE *st, UNIT *uptr, int32 val, CONST void *desc); diff --git a/VAX/vax780_defs.h b/VAX/vax780_defs.h index c389d3d9..86705413 100644 --- a/VAX/vax780_defs.h +++ b/VAX/vax780_defs.h @@ -144,24 +144,24 @@ /* 780 microcode patch 37 - only test LR<23:0> for appropriate length */ -#define ML_LR_TEST(r) if (((uint32)((r) & 0xFFFFFF)) > 0x200000) RSVD_OPND_FAULT +#define ML_LR_TEST(r) if (((uint32)((r) & 0xFFFFFF)) > 0x200000) RSVD_OPND_FAULT(ML_LR_TEST) /* 780 microcode patch 38 - only test PxBR<31>=1, PxBR<30> = 0, and xBR<1:0> = 0 */ #define ML_PXBR_TEST(r) if (((((uint32)(r)) & 0x80000000) == 0) || \ - ((((uint32)(r)) & 0x40000003) != 0)) RSVD_OPND_FAULT -#define ML_SBR_TEST(r) if ((((uint32)(r)) & 0x00000003) != 0) RSVD_OPND_FAULT + ((((uint32)(r)) & 0x40000003) != 0)) RSVD_OPND_FAULT(ML_PXBR_TEST) +#define ML_SBR_TEST(r) if ((((uint32)(r)) & 0x00000003) != 0) RSVD_OPND_FAULT(ML_SBR_TEST) /* 780 microcode patch 78 - test xCBB<1:0> = 0 */ -#define ML_PA_TEST(r) if ((((uint32)(r)) & 0x00000003) != 0) RSVD_OPND_FAULT +#define ML_PA_TEST(r) if ((((uint32)(r)) & 0x00000003) != 0) RSVD_OPND_FAULT(ML_PA_TEST) -#define LP_AST_TEST(r) if ((r) > AST_MAX) RSVD_OPND_FAULT -#define LP_MBZ84_TEST(r) if ((((uint32)(r)) & 0xF8C00000) != 0) RSVD_OPND_FAULT -#define LP_MBZ92_TEST(r) if ((((uint32)(r)) & 0x7FC00000) != 0) RSVD_OPND_FAULT +#define LP_AST_TEST(r) if ((r) > AST_MAX) RSVD_OPND_FAULT(LP_AST_TEST) +#define LP_MBZ84_TEST(r) if ((((uint32)(r)) & 0xF8C00000) != 0) RSVD_OPND_FAULT(LP_MBZ84_TEST) +#define LP_MBZ92_TEST(r) if ((((uint32)(r)) & 0x7FC00000) != 0) RSVD_OPND_FAULT(LP_MBZ92_TEST) #define MT_AST_TEST(r) r = (r) & 07; \ - if ((r) > AST_MAX) RSVD_OPND_FAULT + if ((r) > AST_MAX) RSVD_OPND_FAULT(MT_AST_TEST) #define IDX_IMM_TEST /* Memory */ @@ -186,7 +186,7 @@ extern t_stat cpu_show_memory (FILE* st, UNIT* uptr, int32 val, CONST void* desc); #define CPU_MODEL_MODIFIERS \ { MTAB_XTD|MTAB_VDV, 0, "MODEL", "MODEL={780|785}", \ - &cpu_set_model, &cpu_show_model, NULL, "Set/Show the simulator CPU Model" } + &cpu_set_model, &cpu_show_model, NULL, "Set/Show the simulator CPU Model" }, /* Unibus I/O registers */ diff --git a/VAX/vax780_sbi.c b/VAX/vax780_sbi.c index 9453909a..90d62161 100644 --- a/VAX/vax780_sbi.c +++ b/VAX/vax780_sbi.c @@ -387,7 +387,7 @@ switch (rg) { break; default: - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(ReadIPR); } return val; @@ -466,7 +466,7 @@ switch (rg) { case MT_SBIQC: /* SBIQC */ if (val & SBIQC_MBZ) { - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(WriteIPR); } WriteLP (val, 0); WriteLP (val + 4, 0); @@ -477,7 +477,7 @@ switch (rg) { break; default: - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(WriteIPR); } return; diff --git a/VAX/vax820_bi.c b/VAX/vax820_bi.c index f7e45f7b..69d5c5dd 100644 --- a/VAX/vax820_bi.c +++ b/VAX/vax820_bi.c @@ -390,7 +390,7 @@ switch (rg) { break; default: - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(ReadIPR); } return val; @@ -470,7 +470,7 @@ switch (rg) { break; default: - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(WriteIPR); } return; diff --git a/VAX/vax820_defs.h b/VAX/vax820_defs.h index 85cf7628..9d9321d5 100644 --- a/VAX/vax820_defs.h +++ b/VAX/vax820_defs.h @@ -149,13 +149,13 @@ #define LP_MBZ84_TEST(r) #define LP_MBZ92_TEST(r) #define MT_AST_TEST(r) r = (r) & 07; \ - if ((r) > AST_MAX) RSVD_OPND_FAULT + if ((r) > AST_MAX) RSVD_OPND_FAULT(MT_AST_TEST) /* CPU */ #define CPU_MODEL_MODIFIERS \ { MTAB_XTD|MTAB_VDV, 0, "MODEL", "MODEL={8200|8250}", \ - &cpu_set_model, &cpu_show_model, NULL, "Set/Display processor model" } + &cpu_set_model, &cpu_show_model, NULL, "Set/Display processor model" }, /* Memory */ diff --git a/VAX/vax860_abus.c b/VAX/vax860_abus.c index e190a105..500f13b1 100644 --- a/VAX/vax860_abus.c +++ b/VAX/vax860_abus.c @@ -486,7 +486,7 @@ switch (rg) { break; default: - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(ReadIPR); } return val; @@ -559,7 +559,7 @@ switch (rg) { break; default: - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(WriteIPR); } return; diff --git a/VAX/vax860_defs.h b/VAX/vax860_defs.h index b86b7d68..d7773f1f 100644 --- a/VAX/vax860_defs.h +++ b/VAX/vax860_defs.h @@ -162,24 +162,24 @@ /* 780 microcode patch 37 - only test LR<23:0> for appropriate length */ -#define ML_LR_TEST(r) if (((uint32)((r) & 0xFFFFFF)) > 0x200000) RSVD_OPND_FAULT +#define ML_LR_TEST(r) if (((uint32)((r) & 0xFFFFFF)) > 0x200000) RSVD_OPND_FAULT(ML_LR_TEST) /* 780 microcode patch 38 - only test PxBR<31>=1, PxBR<30> = 0, and xBR<1:0> = 0 */ #define ML_PXBR_TEST(r) if (((((uint32)(r)) & 0x80000000) == 0) || \ - ((((uint32)(r)) & 0x40000003) != 0)) RSVD_OPND_FAULT -#define ML_SBR_TEST(r) if ((((uint32)(r)) & 0x00000003) != 0) RSVD_OPND_FAULT + ((((uint32)(r)) & 0x40000003) != 0)) RSVD_OPND_FAULT(ML_PXBR_TEST) +#define ML_SBR_TEST(r) if ((((uint32)(r)) & 0x00000003) != 0) RSVD_OPND_FAULT(ML_SBR_TEST) /* 780 microcode patch 78 - test xCBB<1:0> = 0 */ -#define ML_PA_TEST(r) if ((((uint32)(r)) & 0x00000003) != 0) RSVD_OPND_FAULT +#define ML_PA_TEST(r) if ((((uint32)(r)) & 0x00000003) != 0) RSVD_OPND_FAULT(ML_PA_TEST) -#define LP_AST_TEST(r) if ((r) > AST_MAX) RSVD_OPND_FAULT -#define LP_MBZ84_TEST(r) if ((((uint32)(r)) & 0xF8C00000) != 0) RSVD_OPND_FAULT -#define LP_MBZ92_TEST(r) if ((((uint32)(r)) & 0x7FC00000) != 0) RSVD_OPND_FAULT +#define LP_AST_TEST(r) if ((r) > AST_MAX) RSVD_OPND_FAULT(LP_AST_TEST) +#define LP_MBZ84_TEST(r) if ((((uint32)(r)) & 0xF8C00000) != 0) RSVD_OPND_FAULT(LP_MBZ84_TEST) +#define LP_MBZ92_TEST(r) if ((((uint32)(r)) & 0x7FC00000) != 0) RSVD_OPND_FAULT(LP_MBZ92_TEST) #define MT_AST_TEST(r) r = (r) & 07; \ - if ((r) > AST_MAX) RSVD_OPND_FAULT + if ((r) > AST_MAX) RSVD_OPND_FAULT(MT_AST_TEST) #define IDX_IMM_TEST /* Memory */ @@ -206,7 +206,7 @@ extern t_stat cpu_show_memory (FILE* st, UNIT* uptr, int32 val, CONST void* desc #define CPU_MODEL_MODIFIERS \ { MTAB_XTD|MTAB_VDV, 0, "MODEL", "MODEL={8600|8650}", \ - &cpu_set_model, &cpu_show_model, NULL, "Set/Display processor model" } + &cpu_set_model, &cpu_show_model, NULL, "Set/Display processor model" }, /* Unibus I/O registers */ diff --git a/VAX/vax_cis.c b/VAX/vax_cis.c index 0b7cc123..bbc06274 100644 --- a/VAX/vax_cis.c +++ b/VAX/vax_cis.c @@ -418,7 +418,7 @@ switch (opc) { /* case on opcode */ case MOVP: if ((PSL & PSL_FPD) || (op[0] > 31)) - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(MOVP); ReadDstr (op[0], op[1], &dst, acc); /* read source */ cc = WriteDstr (op[0], op[2], &dst, 0, acc) | /* write dest */ (cc & CC_C); /* preserve C */ @@ -456,7 +456,7 @@ switch (opc) { /* case on opcode */ case ADDP6: case SUBP6: if ((PSL & PSL_FPD) || (op[0] > 31) || (op[2] > 31) || (op[4] > 31)) - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(ADDP-SUBP); ReadDstr (op[0], op[1], &src1, acc); /* get src1 */ ReadDstr (op[2], op[3], &src2, acc); /* get src2 */ if (opc & 2) /* sub? invert sign */ @@ -510,7 +510,7 @@ switch (opc) { /* case on opcode */ case MULP: if ((PSL & PSL_FPD) || (op[0] > 31) || (op[2] > 31) || (op[4] > 31)) - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(MULP); dst = Dstr_zero; /* clear result */ if (ReadDstr (op[0], op[1], &src1, acc) && /* read src1, src2 */ ReadDstr (op[2], op[3], &src2, acc)) { /* if both > 0 */ @@ -560,7 +560,7 @@ switch (opc) { /* case on opcode */ case DIVP: if ((PSL & PSL_FPD) || (op[0] > 31) || (op[2] > 31) || (op[4] > 31)) - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(DIVP); ldivr = ReadDstr (op[0], op[1], &src1, acc); /* get divisor */ if (ldivr == 0) { /* divisor = 0? */ SET_TRAP (TRAP_FLTDIV); /* dec div trap */ @@ -624,7 +624,7 @@ switch (opc) { /* case on opcode */ op[2] = op[0]; case CMPP4: if ((PSL & PSL_FPD) || (op[0] > 31) || (op[2] > 31)) - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(CMPP); ReadDstr (op[0], op[1], &src1, acc); /* get src1 */ ReadDstr (op[2], op[3], &src2, acc); /* get src2 */ cc = 0; @@ -664,7 +664,7 @@ switch (opc) { /* case on opcode */ case ASHP: if ((PSL & PSL_FPD) || (op[1] > 31) || (op[4] > 31)) - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(ASHP); ReadDstr (op[1], op[2], &src1, acc); /* get source */ V = 0; /* init V */ shift = op[0]; /* get shift count */ @@ -710,7 +710,7 @@ switch (opc) { /* case on opcode */ case CVTPL: if ((PSL & PSL_FPD) || (op[0] > 31)) - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(CVTPL); ReadDstr (op[0], op[1], &src1, acc); /* get source */ V = result = 0; /* clear V, result */ for (i = (DSTRLNT * 8) - 1; i > 0; i--) { /* loop thru digits */ @@ -759,7 +759,7 @@ switch (opc) { /* case on opcode */ case CVTLP: if ((PSL & PSL_FPD) || (op[1] > 31)) - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(CVTLP); dst = Dstr_zero; /* clear result */ result = op[0]; if ((result & LSIGN) != 0) { @@ -797,17 +797,17 @@ switch (opc) { /* case on opcode */ case CVTSP: if ((PSL & PSL_FPD) || (op[0] > 31) || (op[2] > 31)) - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(CVTSP); dst = Dstr_zero; /* clear result */ t = Read (op[1], L_BYTE, RA); /* read source sign */ if (t == C_MINUS) /* sign -, */ dst.sign = 1; else if ((t != C_PLUS) && (t != C_SPACE)) /* + or blank? */ - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(CVTSP); for (i = 1; i <= op[0]; i++) { /* loop thru chars */ c = Read ((op[1] + op[0] + 1 - i) & LMASK, L_BYTE, RA); if ((c < C_ZERO) || (c > C_NINE)) /* [0:9]? */ - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(CVTSP); d = c & 0xF; dst.val[i / 8] = dst.val[i / 8] | (d << ((i % 8) * 4)); } @@ -838,7 +838,7 @@ switch (opc) { /* case on opcode */ case CVTPS: if ((PSL & PSL_FPD) || (op[0] > 31) || (op[2] > 31)) - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(CVTPS); lenl = ReadDstr (op[0], op[1], &dst, acc); /* get source, lw len */ lenp = LntDstr (&dst, lenl); /* get exact nz src len */ ProbeDstr (op[2], op[3], WA); /* test dst write */ @@ -879,13 +879,13 @@ switch (opc) { /* case on opcode */ case CVTTP: if ((PSL & PSL_FPD) || (op[0] > 31) || (op[3] > 31)) - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(CVTTP); dst = Dstr_zero; /* clear result */ for (i = 1; i <= op[0]; i++) { /* loop thru char */ c = Read ((op[1] + op[0] - i) & LMASK, L_BYTE, RA); /* read char */ if (i != 1) { /* normal byte? */ if ((c < C_ZERO) || (c > C_NINE)) /* valid digit? */ - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(CVTTP); d = c & 0xF; } else { /* highest byte */ @@ -893,7 +893,7 @@ switch (opc) { /* case on opcode */ d = (t >> 4) & 0xF; /* digit */ t = t & 0xF; /* sign */ if ((d > 0x9) || (t < 0xA)) - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(CVTTP); if ((t == 0xB) || (t == 0xD)) dst.sign = 1; } @@ -927,7 +927,7 @@ switch (opc) { /* case on opcode */ case CVTPT: if ((PSL & PSL_FPD) || (op[0] > 31) || (op[3] > 31)) - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(CVTPT); lenl = ReadDstr (op[0], op[1], &dst, acc); /* get source, lw len */ lenp = LntDstr (&dst, lenl); /* get exact src len */ ProbeDstr (op[3], op[4], WA); /* test writeability */ @@ -1007,7 +1007,7 @@ switch (opc) { /* case on opcode */ } else { /* new instr */ if (op[0] > 31) /* lnt > 31? */ - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(EDITPC); t = Read ((op[1] + (op[0] / 2)) & LMASK, L_BYTE, RA) & 0xF; if ((t == 0xB) || (t == 0xD)) { cc = CC_N | CC_Z; @@ -1034,7 +1034,7 @@ switch (opc) { /* case on opcode */ if (pop & EO_RPT_FLAG) { /* repeat class? */ rpt = pop & EO_RPT_MASK; /* isolate count */ if (rpt == 0) /* can't be zero */ - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(EDITPC); pop = pop & ~EO_RPT_MASK; /* isolate op */ } switch (pop) { /* case on op */ @@ -1093,7 +1093,7 @@ switch (opc) { /* case on opcode */ case EO_BLANK_ZERO: /* blank zero */ t = Read ((R[3] + 1) & LMASK, L_BYTE, RA); if (t == 0) - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(EDITPC); if (cc & CC_Z) { /* zero? */ do { /* repeat and blank */ Write ((R[5] - t) & LMASK, fill, L_BYTE, WA); @@ -1105,7 +1105,7 @@ switch (opc) { /* case on opcode */ case EO_REPL_SIGN: /* replace sign */ t = Read ((R[3] + 1) & LMASK, L_BYTE, RA); if (t == 0) - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(EDITPC); if (cc & CC_Z) Write ((R[5] - t) & LMASK, fill, L_BYTE, WA); R[3]++; /* now fault safe */ @@ -1114,7 +1114,7 @@ switch (opc) { /* case on opcode */ case EO_ADJUST_LNT: /* adjust length */ t = Read ((R[3] + 1) & LMASK, L_BYTE, RA); if ((t == 0) || (t > 31)) - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(EDITPC); R[0] = R[0] & WMASK; /* clr old ld zero */ if (R[0] > t) { /* decrease */ for (i = 0; i < (R[0] - t); i++) { /* loop thru src */ @@ -1162,7 +1162,7 @@ switch (opc) { /* case on opcode */ break; default: /* undefined */ - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(EDITPC); } /* end case pattern */ R[3] = (R[3] + 1) & LMASK; /* next pattern byte */ @@ -1170,7 +1170,7 @@ switch (opc) { /* case on opcode */ } /* end for pattern */ if (R[0]) /* pattern too short */ - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(EDITPC); PSL = PSL & ~PSL_FPD; /* clear FPD */ if (cc & CC_Z) /* zero? clear n */ cc = cc & ~CC_N; @@ -1182,7 +1182,7 @@ switch (opc) { /* case on opcode */ return cc; default: - RSVD_INST_FAULT; + RSVD_INST_FAULT(opc); } /* end case op */ return cc; @@ -1614,7 +1614,7 @@ r1 = (R[1] + (inc / 2) + ((~R[0] & inc) & 1)) & LMASK; /* eff addr */ r0 = (R[0] - inc) & 0x1F; /* eff lnt left */ if (r0 == 0) { /* nothing left? */ R[0] = -1; /* out of input */ - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(edit_read_src); } c = Read (r1, L_BYTE, RA); return (((r0 & 1)? (c >> 4): c) & 0xF); @@ -1646,49 +1646,19 @@ return sign; #else +extern int32 cpu_emulate_exception (int32 *opnd, int32 cc, int32 opc, int32 acc); + /* CIS instructions - invoke emulator interface opnd[0:5] = six operands to be pushed (if PSL = 0) cc = condition codes opc = opcode - If FPD is set, push old PC and PSL on stack, vector thru SCB. - If FPD is clear, push opcode, old PC, operands, new PC, and PSL - on stack, vector thru SCB. - In both cases, the exception occurs in the current mode. */ int32 op_cis (int32 *opnd, int32 cc, int32 opc, int32 acc) { -int32 vec; - -if (PSL & PSL_FPD) { /* FPD set? */ - Read (SP - 1, L_BYTE, WA); /* wchk stack */ - Write (SP - 8, fault_PC, L_LONG, WA); /* push old PC */ - Write (SP - 4, PSL | cc, L_LONG, WA); /* push PSL */ - SP = SP - 8; /* decr stk ptr */ - vec = ReadLP ((SCBB + SCB_EMULFPD) & PAMASK); - } -else { - if (opc == CVTPL) /* CVTPL? .wl */ - opnd[2] = (opnd[2] >= 0)? ~opnd[2]: opnd[3]; - Read (SP - 1, L_BYTE, WA); /* wchk stack */ - Write (SP - 48, opc, L_LONG, WA); /* push opcode */ - Write (SP - 44, fault_PC, L_LONG, WA); /* push old PC */ - Write (SP - 40, opnd[0], L_LONG, WA); /* push operands */ - Write (SP - 36, opnd[1], L_LONG, WA); - Write (SP - 32, opnd[2], L_LONG, WA); - Write (SP - 28, opnd[3], L_LONG, WA); - Write (SP - 24, opnd[4], L_LONG, WA); - Write (SP - 20, opnd[5], L_LONG, WA); - Write (SP - 8, PC, L_LONG, WA); /* push cur PC */ - Write (SP - 4, PSL | cc, L_LONG, WA); /* push PSL */ - SP = SP - 48; /* decr stk ptr */ - vec = ReadLP ((SCBB + SCB_EMULATE) & PAMASK); - } -PSL = PSL & ~(PSL_TP | PSL_FPD | PSW_DV | PSW_FU | PSW_IV | PSW_T); -JUMP (vec & ~03); /* set new PC */ -return 0; /* set new cc's */ +return cpu_emulate_exception (opnd, cc, opc, acc); } #endif diff --git a/VAX/vax_cmode.c b/VAX/vax_cmode.c index 49d466a2..b744dc1c 100644 --- a/VAX/vax_cmode.c +++ b/VAX/vax_cmode.c @@ -1308,7 +1308,7 @@ return TRUE; /* always bad */ int32 op_cmode (int32 cc) { -RSVD_INST_FAULT; +RSVD_INST_FAULT(0); return cc; } diff --git a/VAX/vax_cpu.c b/VAX/vax_cpu.c index 1c646000..ec8b9ae9 100644 --- a/VAX/vax_cpu.c +++ b/VAX/vax_cpu.c @@ -262,6 +262,7 @@ int32 fault_PC; /* fault PC */ int32 mxpr_cc_vc = 0; /* MxPR V,C bits */ int32 pcq_p = 0; /* PC queue ptr */ int32 badabo = 0; +int32 cpu_instruction_set = CPU_INSTRUCTION_SET; /* Instruction Groups */ int32 cpu_astop = 0; int32 mchk_va, mchk_ref; /* mem ref param */ int32 ibufl, ibufh; /* prefetch buf */ @@ -307,7 +308,6 @@ const uint32 align[4] = { /* External and forward references */ extern int32 sys_model; -extern const char *opcode[]; t_stat cpu_reset (DEVICE *dptr); t_bool cpu_is_pc_a_subroutine_call (t_addr **ret_addrs); @@ -319,12 +319,15 @@ t_stat cpu_show_hist (FILE *st, UNIT *uptr, int32 val, CONST void *desc); t_stat cpu_show_virt (FILE *st, UNIT *uptr, int32 val, CONST void *desc); t_stat cpu_set_idle (UNIT *uptr, int32 val, CONST char *cptr, void *desc); t_stat cpu_show_idle (FILE *st, UNIT *uptr, int32 val, CONST void *desc); +t_stat cpu_set_instruction_set (UNIT *uptr, int32 val, CONST char *cptr, void *desc); +t_stat cpu_show_instruction_set (FILE *st, UNIT *uptr, int32 val, CONST void *desc); const char *cpu_description (DEVICE *dptr); int32 cpu_get_vsw (int32 sw); static SIM_INLINE int32 get_istr (int32 lnt, int32 acc); int32 ReadOcta (int32 va, int32 *opnd, int32 j, int32 acc); t_bool cpu_show_opnd (FILE *st, InstHistory *h, int32 line); t_stat cpu_show_hist_records (FILE *st, t_bool do_header, int32 start, int32 count); +int32 cpu_emulate_exception (int32 *opnd, int32 cc, int32 opc, int32 acc); void cpu_idle (void); /* CPU data structures @@ -342,7 +345,7 @@ UNIT cpu_unit = { const char *psl_modes[] = {"K", "E", "S", "U"}; -BITFIELD psl_bits[] = { +BITFIELD cpu_psl_bits[] = { BIT(C), /* Carry */ BIT(V), /* Overflow */ BIT(Z), /* Zero */ @@ -384,7 +387,7 @@ REG cpu_reg[] = { { HRDATAD (AP, R[nAP], 32, "Alias for R12") }, { HRDATAD (FP, R[nFP], 32, "Alias for R13") }, { HRDATAD (SP, R[nSP], 32, "Alias for R14") }, - { HRDATADF(PSL, PSL, 32, "processor status longword", psl_bits) }, + { HRDATADF(PSL, PSL, 32, "processor status longword", cpu_psl_bits) }, { HRDATAD (CC, PSL, 4, "condition codes, PSL<3:0>") }, { HRDATAD (KSP, KSP, 32, "kernel stack pointer") }, { HRDATAD (ESP, ESP, 32, "executive stack pointer") }, @@ -428,18 +431,21 @@ MTAB cpu_mod[] = { &cpu_set_hist, &cpu_show_hist, NULL, "Displays instruction history" }, { MTAB_XTD|MTAB_VDV|MTAB_NMO|MTAB_SHP, 0, "VIRTUAL", NULL, NULL, &cpu_show_virt, NULL, "show translation for address arg in KESU mode" }, - CPU_MODEL_MODIFIERS, /* Model specific cpu modifiers from vaxXXX_defs.h */ + CPU_MODEL_MODIFIERS /* Model specific cpu modifiers from vaxXXX_defs.h */ + CPU_INST_MODIFIERS /* Model specific cpu instruction modifiers from vaxXXX_defs.h */ { 0 } }; DEBTAB cpu_deb[] = { { "INTEXC", LOG_CPU_I, "interrupt and exception activities" }, { "REI", LOG_CPU_R, "REI activities" }, + { "ABORT", LOG_CPU_A, "Abort activities" }, { "CONTEXT", LOG_CPU_P, "context switching activities" }, { "RSVDFAULT", LOG_CPU_FAULT_RSVD, "reserved fault activities" }, { "FLTFAULT", LOG_CPU_FAULT_FLT, "floating fault activities" }, { "CMODFAULT", LOG_CPU_FAULT_CMODE, "cmode fault activities" }, { "MCHKFAULT", LOG_CPU_FAULT_MCHK, "machine check fault activities" }, + { "EMULFAULT", LOG_CPU_FAULT_EMUL, "instruction emulation fault activities" }, { NULL, 0 } }; @@ -527,6 +533,9 @@ else if (abortval < 0) { /* mm or rsrv or int */ else R[rrn] = R[rrn] + rlnt; } } + sim_debug (LOG_CPU_A, &cpu_dev, "abort=%08X, fault_PC=%08x, SP=%08x, PC=%08x, PSL=%08x ", + -abortval, fault_PC, PC, SP, PSL); + sim_debug_bits(LOG_CPU_A, &cpu_dev, cpu_psl_bits, PSL, PSL, 1); PSL = PSL & ~PSL_TP; /* clear */ recqptr = 0; /* clear queue */ delta = PC - fault_PC; /* save delta PC */ @@ -574,6 +583,8 @@ else if (abortval < 0) { /* mm or rsrv or int */ break; case SCB_MCHK: /* machine check */ + sim_debug (LOG_CPU_FAULT_MCHK, &cpu_dev, "%s fault_PC=%08x, PSL=%08x, cc=%08x, PC=%08x, delta-%08X, p1=%08X\n", + opcode[opc], fault_PC, PSL, cc, PC, delta, p1); cc = machine_check (p1, opc, cc, delta); /* system specific */ in_ie = 0; GET_CUR; /* PSL changed */ @@ -717,9 +728,27 @@ for ( ;; ) { opc = opc | 0x100; /* flag */ } numspec = drom[opc][0]; /* get # specs */ +#if !defined(FULL_VAX) + if (((DR_GETIGRP(numspec) == DR_GETIGRP(IG_BSDFL)) && (!(cpu_instruction_set & VAX_DFLOAT))) || + ((DR_GETIGRP(numspec) == DR_GETIGRP(IG_BSGFL)) && (!(cpu_instruction_set & VAX_GFLOAT))) || + (DR_GETIGRP(numspec) == DR_GETIGRP(IG_RSVD))) /* explicit reserved instruction? */ + RSVD_INST_FAULT(opc); +#endif +#if defined(VAX_610) + /* + * This case is formally UNPREDICTABLE, but how the MicroVAX I CPU + * worked. Instructions without the DR_F in their drom table entry + * are specifically uninterruptible instructions, so this would not + * ever happen during normal execution, but the MicroVAX I HCORE + * diagnostic contrives this as a test and expects thost cases to + * be ignored. + */ + if ((PSL & PSL_FPD) && (numspec & DR_F)) { +#else if (PSL & PSL_FPD) { if ((numspec & DR_F) == 0) - RSVD_INST_FAULT; + RSVD_INST_FAULT(opc); +#endif j = 0; /* no operands */ } else { @@ -1784,7 +1813,7 @@ for ( ;; ) { if (op1 >= 0) temp = R[op1] & WMASK; /* reg? ADDW2 */ else { if (op2 & 1) /* mem? chk align */ - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(ADAWI); temp = Read (op2, L_WORD, WA); /* ok, ADDW2 */ } r = (op0 + temp) & WMASK; @@ -2590,7 +2619,7 @@ for ( ;; ) { case HALT: if (PSL & PSL_CUR) /* not kern? rsvd inst */ - RSVD_INST_FAULT; + RSVD_INST_FAULT(HALT); else { /* allow potentially pending I/O (console output, or other devices) to complete before taking @@ -2628,14 +2657,14 @@ for ( ;; ) { case BISPSW: if (opnd[0] & PSW_MBZ) - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(BISPW); PSL = PSL | (opnd[0] & ~CC_MASK); cc = cc | (opnd[0] & CC_MASK); break; case BICPSW: if (opnd[0] & PSW_MBZ) - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(BICPSW); PSL = PSL & ~opnd[0]; cc = cc & ~opnd[0]; break; @@ -2694,6 +2723,12 @@ for ( ;; ) { break; case CMPC3: case CMPC5: +#if defined(VAX_610) + if (opc == CMPC5) { + cc = cpu_emulate_exception (opnd, cc, opc, acc); + break; + } +#endif cc = op_cmpc (opnd, opc & 4, acc); break; @@ -3095,6 +3130,10 @@ for ( ;; ) { /* Octaword or reserved instructions */ case PUSHAO: case MOVAO: case CLRO: case MOVO: +#if defined(VAX_610) + cc = cpu_emulate_exception (opnd, cc, opc, acc); + break; +#endif case TSTH: case MOVH: case MNEGH: case CMPH: case CVTBH: case CVTWH: case CVTLH: case CVTHB: case CVTHW: case CVTHL: case CVTRHL: @@ -3112,7 +3151,7 @@ for ( ;; ) { break; default: - RSVD_INST_FAULT; + RSVD_INST_FAULT(opc); break; } /* end case op */ } /* end for */ @@ -3185,6 +3224,59 @@ opnd[j++] = Read (va + 12, L_LONG, acc); return j; } + +/* CIS instructions - invoke emulator interface + + opnd[0:5] = six operands to be pushed (if PSL = 0) + cc = condition codes + opc = opcode + + If FPD is set, push old PC and PSL on stack, vector thru SCB. + If FPD is clear, push opcode, old PC, operands, new PC, and PSL + on stack, vector thru SCB. + In both cases, the exception occurs in the current mode. +*/ + +int32 cpu_emulate_exception (int32 *opnd, int32 cc, int32 opc, int32 acc) +{ +int32 vec; + +if (PSL & PSL_FPD) { /* FPD set? */ + Read (SP - 1, L_BYTE, WA); /* wchk stack */ + Write (SP - 8, fault_PC, L_LONG, WA); /* push old PC */ + Write (SP - 4, PSL | cc, L_LONG, WA); /* push PSL */ + SP = SP - 8; /* decr stk ptr */ + vec = ReadLP ((SCBB + SCB_EMULFPD) & PAMASK); + sim_debug (LOG_CPU_FAULT_EMUL, &cpu_dev, "FPD OP=%s, fault_PC=%08x, PC=%08x, PSL=%08x, SP=%08x, nPC=%08x ", + opcode[opc], fault_PC, PC, PSL, SP, vec); + sim_debug_bits(LOG_CPU_FAULT_EMUL, &cpu_dev, cpu_psl_bits, PSL, PSL, 1); + } +else { + if (opc == CVTPL) /* CVTPL? .wl */ + opnd[2] = (opnd[2] >= 0)? ~opnd[2]: opnd[3]; + Read (SP - 1, L_BYTE, WA); /* wchk stack */ + Write (SP - 48, opc, L_LONG, WA); /* push opcode */ + Write (SP - 44, fault_PC, L_LONG, WA); /* push old PC */ + Write (SP - 40, opnd[0], L_LONG, WA); /* push operands */ + Write (SP - 36, opnd[1], L_LONG, WA); + Write (SP - 32, opnd[2], L_LONG, WA); + Write (SP - 28, opnd[3], L_LONG, WA); + Write (SP - 24, opnd[4], L_LONG, WA); + Write (SP - 20, opnd[5], L_LONG, WA); + Write (SP - 8, PC, L_LONG, WA); /* push cur PC */ + Write (SP - 4, PSL | cc, L_LONG, WA); /* push PSL */ + SP = SP - 48; /* decr stk ptr */ + vec = ReadLP ((SCBB + SCB_EMULATE) & PAMASK); + sim_debug (LOG_CPU_FAULT_EMUL, &cpu_dev, "OP=%s, fault_PC=%08x, PC=%08x, PSL=%08x, SP=%08x, nPC=%08x ", + opcode[opc], fault_PC, PC, PSL, SP, vec); + sim_debug_bits(LOG_CPU_FAULT_EMUL, &cpu_dev, cpu_psl_bits, PSL, PSL, 1); + } +PSL = PSL & ~(PSL_TP | PSL_FPD | PSW_DV | PSW_FU | PSW_IV | PSW_T); +JUMP (vec & ~03); /* set new PC */ +return 0; /* set new cc's */ +} + + /* Idle before the next instruction */ void cpu_idle (void) @@ -3650,7 +3742,144 @@ if (sim_idle_enab && (cpu_idle_type != 0)) sim_show_idle (st, uptr, val, desc); return SCPE_OK; } + +static struct { + int32 mask; + const char *match; + const char *desc; + } inst_groups[] = { + {0, "", ""}, /* Reserved Opcode */ + {VAX_BASE, "BASE", "Base Group"}, /* Base Instruction Group */ + {VAX_GFLOAT, "G-FLOAT", "G-Float"}, /* Base subgroup G-Float */ + {VAX_DFLOAT, "D-FLOAT", "D-Float"}, /* Base subgroup D-Float */ + {VAX_PACKED, "PACKED", "Packed-Decimal-String-Group"}, /* packed-decimal-string group */ + {VAX_EXTAC, "EXTENDED", "Extended-Accuracy-Group"}, /* extended-accuracy group */ + {VAX_EMONL, "EMULATED", "Emulated-Only-Group"}, /* emulated only instructions */ +// {VAX_VECTR, "VECTOR", "Vector-Processing-Group"}, /* vector-processing group */ + {0, NULL, NULL} + }; +t_stat cpu_set_instruction_set (UNIT *uptr, int32 val, CONST char *cptr, void *desc) +{ +if (!cptr || !*cptr) + return SCPE_ARG; +while (1) { + int i; + t_bool invert = FALSE; + char gbuf[CBUFSIZE]; + + cptr = get_glyph (cptr, gbuf, ';'); + if (!gbuf[0]) + break; + if (0 == strncmp (gbuf, "NO", 2)) { + invert = TRUE; + memmove (gbuf, gbuf + 2, 1 + strlen (gbuf + 2)); + } + for (i=0; inst_groups[i].match != NULL; i++) + if (MATCH_CMD (gbuf, inst_groups[i].match) == 0) + break; + if (inst_groups[i].match == NULL) + return sim_messagef (SCPE_ARG, "unknown instruction set group: %s\n", gbuf); + if (invert) + cpu_instruction_set &= ~inst_groups[i].mask; + else + cpu_instruction_set |= inst_groups[i].mask; + } +return SCPE_OK; +} + +/* Used when sorting a list of opcode names */ +static int _opc_name_compare (const void *pa, const void *pb) +{ +const char **a = (const char **)pa; +const char **b = (const char **)pb; + +return strcmp (*a, *b); +} + +t_stat cpu_show_instruction_group (FILE *st, int32 groupmask) +{ +int opc; +int group; +int matches; +char const *opcd_tmp[NUM_INST]; + +for (opc=matches=0; opc SHOW CPU INSTRUCTIONS display the instructoin groups that are\n"); +fprintf (st, " implemented and emulated\n"); +fprintf (st, " sim> SHOW CPU -V INSTRUCTIONS disable the list of instructions implemented\n"); +fprintf (st, " and emulated\n\n"); return SCPE_OK; } diff --git a/VAX/vax_cpu1.c b/VAX/vax_cpu1.c index ae493f96..0adb355f 100644 --- a/VAX/vax_cpu1.c +++ b/VAX/vax_cpu1.c @@ -109,7 +109,7 @@ int32 by; if (rn != OP_MEM) { /* register? */ if (((uint32) pos) > 31) /* pos > 31? fault */ - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(op_bb_n); return (R[rn] >> pos) & 1; /* get bit */ } ea = opnd[2] + (pos >> 3); /* base byte addr */ @@ -127,7 +127,7 @@ int32 by, bit; if (rn != OP_MEM) { /* register? */ if (((uint32) pos) > 31) /* pos > 31? fault */ - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(op_bb_x); bit = (R[rn] >> pos) & 1; /* get bit */ R[rn] = newb? (R[rn] | (1u << pos)): (R[rn] & ~(1u << pos)); return bit; @@ -162,10 +162,10 @@ int32 ba, wd1 = 0; if (size == 0) /* size 0? field = 0 */ return 0; if (size > 32) /* size > 32? fault */ - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(op_extv); if (rn != OP_MEM) { /* register? */ if (((uint32) pos) > 31) /* pos > 31? fault */ - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(op_extv); if (((pos + size) > 32) && (rn >= nSP)) /* span 2 reg, PC? */ RSVD_ADDR_FAULT; /* fault */ if (pos) @@ -206,10 +206,10 @@ int32 val, mask, ba, wd, wd1; if (size == 0) /* size = 0? done */ return; if (size > 32) /* size > 32? fault */ - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(op_insv); if (rn != OP_MEM) { /* in registers? */ if (((uint32) pos) > 31) /* pos > 31? fault */ - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(op_insv); if ((pos + size) > 32) { /* span two reg? */ if (rn >= nSP) /* if PC, fault */ RSVD_ADDR_FAULT; @@ -341,7 +341,7 @@ int32 mask, stklen, tsp, wd; mask = Read (addr, L_WORD, RA); /* get proc mask */ if (mask & CALL_MBZ) /* test mbz */ - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(op_call); stklen = rcnt[mask & 077] + rcnt[(mask >> 6) & 077] + (gs? 24: 20); Read (SP - stklen, L_BYTE, WA); /* wchk stk */ if (gs) { @@ -386,7 +386,7 @@ int32 tsp = FP; spamask = Read (tsp + 4, L_LONG, RA); /* spa/s/mask/psw */ if (spamask & PSW_MBZ) /* test mbz */ - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(op_ret); stklen = rcnt[(spamask >> CALL_V_MASK) & 077] + rcnt[(spamask >> (CALL_V_MASK + 6)) & 077] + ((spamask & CALL_S)? 23: 19); Read (tsp + stklen, L_BYTE, RA); /* rchk stk end */ @@ -603,11 +603,11 @@ int32 a; int32 t; if ((h == d) || ((h | d) & 07)) /* h, d quad align? */ - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(op_insqhi); Read (d, L_BYTE, WA); /* wchk ent */ a = Read (h, L_LONG, WA); /* a <- (h), wchk */ if (a & 06) /* chk quad align */ - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(op_insqhi); if (a & 01) /* busy, cc = 0001 */ return CC_C; Write (h, a | 1, L_LONG, WA); /* get interlock */ @@ -629,20 +629,20 @@ int32 a, c; int32 t; if ((h == d) || ((h | d) & 07)) /* h, d quad align? */ - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(op_insqti); Read (d, L_BYTE, WA); /* wchk ent */ a = Read (h, L_LONG, WA); /* a <- (h), wchk */ if (a == 0) /* if empty, ins hd */ return op_insqhi (opnd, acc); if (a & 06) /* chk quad align */ - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(op_insqti); if (a & 01) /* busy, cc = 0001 */ return CC_C; Write (h, a | 1, L_LONG, WA); /* acquire interlock */ c = Read (h + 4, L_LONG, RA) + h; /* c <- (h+4) + h */ if (c & 07) { /* c quad aligned? */ Write (h, a, L_LONG, WA); /* release interlock */ - RSVD_OPND_FAULT; /* fault */ + RSVD_OPND_FAULT(op_insqti); /* fault */ } if (Test (c, WA, &t) < 0) /* wtst c, rls if err */ Write (h, a, L_LONG, WA); @@ -687,15 +687,15 @@ int32 ar, a, b; int32 t; if (h & 07) /* h quad aligned? */ - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(op_remqhi); if (opnd[1] == OP_MEM) { /* mem destination? */ if (h == opnd[2]) /* hdr = dst? */ - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(op_remqhi); Read (opnd[2], L_LONG, WA); /* wchk dst */ } ar = Read (h, L_LONG, WA); /* ar <- (h) */ if (ar & 06) /* a quad aligned? */ - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(op_remqhi); if (ar & 01) /* busy, cc = 0011 */ return CC_V | CC_C; a = ar + h; /* abs addr of a */ @@ -706,7 +706,7 @@ if (ar) { /* queue not empty? */ b = Read (a, L_LONG, RA) + a; /* b <- (a)+a, flt ok */ if (b & 07) { /* b quad aligned? */ Write (h, ar, L_LONG, WA); /* release interlock */ - RSVD_OPND_FAULT; /* fault */ + RSVD_OPND_FAULT(op_remqhi); /* fault */ } if (Test (b, WA, &t) < 0) /* write test b */ Write (h, ar, L_LONG, WA); /* release if err */ @@ -728,15 +728,15 @@ int32 ar, b, c; int32 t; if (h & 07) /* h quad aligned? */ - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(op_remqti); if (opnd[1] == OP_MEM) { /* mem destination? */ if (h == opnd[2]) /* hdr = dst? */ - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(op_remqti); Read (opnd[2], L_LONG, WA); /* wchk dst */ } ar = Read (h, L_LONG, WA); /* a <- (h) */ if (ar & 06) /* a quad aligned? */ - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(op_remqti); if (ar & 01) /* busy, cc = 0011 */ return CC_V | CC_C; if (ar) { /* queue not empty */ @@ -748,7 +748,7 @@ if (ar) { /* queue not empty */ } if (c & 07) { /* c quad aligned? */ Write (h, ar, L_LONG, WA); /* release interlock */ - RSVD_OPND_FAULT; /* fault */ + RSVD_OPND_FAULT(op_remqti); /* fault */ } c = c + h; /* abs addr of c */ if (Test (c + 4, RA, &t) < 0) /* read test c+4 */ @@ -756,7 +756,7 @@ if (ar) { /* queue not empty */ b = Read (c + 4, L_LONG, RA) + c; /* b <- (c+4)+c, flt ok */ if (b & 07) { /* b quad aligned? */ Write (h, ar, L_LONG, WA); /* release interlock */ - RSVD_OPND_FAULT; /* fault */ + RSVD_OPND_FAULT(op_remqti); /* fault */ } if (Test (b, WA, &t) < 0) /* write test b */ Write (h, ar, L_LONG, WA); /* release if error */ @@ -919,7 +919,7 @@ switch (R[5] & MVC_M_STATE) { /* case on state */ break; default: /* bad state */ - RSVD_OPND_FAULT; /* you lose */ + RSVD_OPND_FAULT(op_movc); /* you lose */ } PSL = PSL & ~PSL_FPD; /* clear FPD */ @@ -1131,8 +1131,9 @@ if (ei > 0) { /* if int, new IPL */ else PSL = newpsl | /* exc, old IPL/1F */ ((newpc & 1)? PSL_IPL1F: (oldpsl & PSL_IPL)) | (oldcur << PSL_V_PRV); -sim_debug (LOG_CPU_I, &cpu_dev, "PC=%08x, PSL=%08x, SP=%08x, VEC=%08x, nPSL=%08x, nSP=%08x\n", +sim_debug (LOG_CPU_I, &cpu_dev, "PC=%08x, PSL=%08x, SP=%08x, VEC=%08x, nPSL=%08x, nSP=%08x ", PC, oldpsl, oldsp, vec, PSL, SP); +sim_debug_bits(LOG_CPU_I, &cpu_dev, cpu_psl_bits, oldpsl, PSL, 1); acc = ACC_MASK (KERN); /* new mode is kernel */ Write (SP - 4, oldpsl, L_LONG, WA); /* push old PSL */ Write (SP - 8, PC, L_LONG, WA); /* push old PC */ @@ -1202,9 +1203,9 @@ Rule SRM formulation Comment */ #define REI_RSVD_FAULT(desc) do { \ - sim_debug (LOG_CPU_FAULT_RSVD, &cpu_dev, "PC=%08x, PSL=%08x, SP=%08x, nPC=%08x, nPSL=%08x, nSP=%08x - %s\n",\ + sim_debug (LOG_CPU_FAULT_RSVD, &cpu_dev, "REI Operand: PC=%08x, PSL=%08x, SP=%08x, nPC=%08x, nPSL=%08x, nSP=%08x - %s\n",\ PC, PSL, SP - 8, newpc, newpsl, ((newpsl & IS)? IS: STK[newcur]), desc); \ - RSVD_OPND_FAULT; } while (0) + RSVD_OPND_FAULT(REI); } while (0) int32 op_rei (int32 acc) { @@ -1242,8 +1243,9 @@ if (PSL & PSL_IS) /* save stack */ IS = SP; else STK[oldcur] = SP; -sim_debug (LOG_CPU_R, &cpu_dev, "PC=%08x, PSL=%08x, SP=%08x, nPC=%08x, nPSL=%08x, nSP=%08x\n", +sim_debug (LOG_CPU_R, &cpu_dev, "PC=%08x, PSL=%08x, SP=%08x, nPC=%08x, nPSL=%08x, nSP=%08x ", PC, PSL, SP - 8, newpc, newpsl, ((newpsl & IS)? IS: STK[newcur])); +sim_debug_bits(LOG_CPU_R, &cpu_dev, cpu_psl_bits, PSL, newpsl, 1); PSL = (PSL & PSL_TP) | (newpsl & ~CC_MASK); /* set PSL */ if (PSL & PSL_IS) /* set new stack */ SP = IS; @@ -1265,7 +1267,7 @@ void op_ldpctx (int32 acc) uint32 newpc, newpsl, pcbpa, t; if (PSL & PSL_CUR) /* must be kernel */ - RSVD_INST_FAULT; + RSVD_INST_FAULT(LDPCTX); pcbpa = PCBB & PAMASK; /* phys address */ KSP = ReadLP (pcbpa); /* restore stk ptrs */ ESP = ReadLP (pcbpa + 4); @@ -1327,7 +1329,7 @@ void op_svpctx (int32 acc) int32 savpc, savpsl, pcbpa; if (PSL & PSL_CUR) /* must be kernel */ - RSVD_INST_FAULT; + RSVD_INST_FAULT(SVPCTX); savpc = Read (SP, L_LONG, RA); /* pop PC, PSL */ savpsl = Read (SP + 4, L_LONG, RA); sim_debug (LOG_CPU_P, &cpu_dev, ">>SVP: PC=%08x, PSL=%08x, SP=%08x, oPC=%08x, oPSL=%08x\n", @@ -1429,9 +1431,9 @@ uint32 prn = (uint32)opnd[1]; int32 cc; if (PSL & PSL_CUR) /* must be kernel */ - RSVD_INST_FAULT; + RSVD_INST_FAULT(MTPR); if (prn > MT_MAX) /* reg# > max? fault */ - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(op_mtpr); CC_IIZZ_L (val); /* set cc's */ switch (prn) { /* case on reg # */ @@ -1560,9 +1562,9 @@ uint32 prn = (uint32)opnd[0]; int32 val; if (PSL & PSL_CUR) /* must be kernel */ - RSVD_INST_FAULT; + RSVD_INST_FAULT(MFPR); if (prn > MT_MAX) /* reg# > max? fault */ - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(op_mtpr); switch (prn) { /* case on reg# */ case MT_KSP: /* KSP */ @@ -1633,7 +1635,7 @@ switch (prn) { /* case on reg# */ case MT_TBIA: case MT_TBIS: case MT_TBCHK: - RSVD_OPND_FAULT; /* write only */ + RSVD_OPND_FAULT(op_mfpr); /* write only */ default: /* others */ val = ReadIPR (prn); /* read from SSC */ diff --git a/VAX/vax_defs.h b/VAX/vax_defs.h index 5ea0471a..0da28a39 100644 --- a/VAX/vax_defs.h +++ b/VAX/vax_defs.h @@ -79,24 +79,47 @@ #define ABORT_TNV (-SCB_TNV) /* transl not vaid */ #define ABORT(x) longjmp (save_env, (x)) /* abort */ extern jmp_buf save_env; -#define RSVD_INST_FAULT ABORT (ABORT_RESIN) +#define RSVD_INST_FAULT(opc) do { \ + char op_num[20]; \ + char const *opcd = opcode[opc]; \ + \ + if (sim_deb && !opcd) { \ + opcd = op_num; \ + sprintf (op_num, "Opcode 0x%X", opc); \ + sim_debug (LOG_CPU_FAULT_RSVD, &cpu_dev, "%s fault_PC=%08x, PSL=%08x, SP=%08x, PC=%08x\n", \ + opcd, fault_PC, PSL, SP, PC); \ + } \ + ABORT (ABORT_RESIN); } while (0) #define RSVD_ADDR_FAULT ABORT (ABORT_RESAD) -#define RSVD_OPND_FAULT ABORT (ABORT_RESOP) +#define RSVD_OPND_FAULT(opc) do { \ + sim_debug (LOG_CPU_FAULT_RSVD, &cpu_dev, #opc " fault_PC=%08x, PSL=%08x, SP=%08x, PC=%08x\n", \ + fault_PC, PSL, SP, PC); \ + ABORT (ABORT_RESOP); } while (0) #define FLT_OVFL_FAULT p1 = FLT_OVRFLO, ABORT (ABORT_ARITH) #define FLT_DZRO_FAULT p1 = FLT_DIVZRO, ABORT (ABORT_ARITH) #define FLT_UNFL_FAULT p1 = FLT_UNDFLO, ABORT (ABORT_ARITH) -#define CMODE_FAULT(cd) p1 = (cd), ABORT (ABORT_CMODE) -#define MACH_CHECK(cd) p1 = (cd), ABORT (ABORT_MCHK) +#define CMODE_FAULT(cd) do { \ + sim_debug (LOG_CPU_FAULT_CMODE, &cpu_dev, #cd " fault_PC=%08x, PSL=%08x, SP=%08x, PC=%08x\n", \ + fault_PC, PSL, SP, PC); \ + p1 = (cd); \ + ABORT (ABORT_CMODE); } while (0) +#define MACH_CHECK(cd) do { \ + sim_debug (LOG_CPU_FAULT_MCHK, &cpu_dev, #cd " fault_PC=%08x, PSL=%08x, SP=%08x, PC=%08x\n", \ + fault_PC, PSL, SP, PC); \ + p1 = (cd); \ + ABORT (ABORT_MCHK); } while (0) /* Logging */ #define LOG_CPU_I 0x001 /* intexc */ #define LOG_CPU_R 0x002 /* REI */ -#define LOG_CPU_P 0x004 /* process context */ -#define LOG_CPU_FAULT_RSVD 0x008 /* reserved faults */ -#define LOG_CPU_FAULT_FLT 0x010 /* floating faults*/ -#define LOG_CPU_FAULT_CMODE 0x020 /* cmode faults */ -#define LOG_CPU_FAULT_MCHK 0x040 /* machine check faults */ +#define LOG_CPU_A 0x004 /* Abort */ +#define LOG_CPU_P 0x008 /* process context */ +#define LOG_CPU_FAULT_RSVD 0x010 /* reserved faults */ +#define LOG_CPU_FAULT_FLT 0x020 /* floating faults*/ +#define LOG_CPU_FAULT_CMODE 0x040 /* cmode faults */ +#define LOG_CPU_FAULT_MCHK 0x080 /* machine check faults */ +#define LOG_CPU_FAULT_EMUL 0x100 /* emulated instruction fault */ /* Recovery queue */ @@ -425,6 +448,37 @@ extern jmp_buf save_env; #define RB_SP (14 << DR_V_RESMASK) /* @SP */ #define DR_GETRES(x) (((x) >> DR_V_RESMASK) & DR_M_RESMASK) +/* Extra bits in the opcode flag word of the Decode ROM array + to identify instruction group */ + +#define DR_V_IGMASK 12 +#define DR_M_IGMASK 0x0007 +#define IG_RSVD (0 << DR_V_IGMASK) /* Reserved Opcode */ +#define IG_BASE (1 << DR_V_IGMASK) /* Base Instruction Group */ +#define IG_BSGFL (2 << DR_V_IGMASK) /* Base subgroup G-Float */ +#define IG_BSDFL (3 << DR_V_IGMASK) /* Base subgroup D-Float */ +#define IG_PACKD (4 << DR_V_IGMASK) /* packed-decimal-string group */ +#define IG_EXTAC (5 << DR_V_IGMASK) /* extended-accuracy group */ +#define IG_EMONL (6 << DR_V_IGMASK) /* emulated-only group */ +#define IG_VECTR (7 << DR_V_IGMASK) /* vector-processing group */ +#define IG_MAX_GRP 7 /* Maximum Instruction groups */ +#define DR_GETIGRP(x) (((x) >> DR_V_IGMASK) & DR_M_IGMASK) + +#define VAX_FULL_BASE ((1 << DR_GETIGRP(IG_BASE)) | \ + (1 << DR_GETIGRP(IG_BSGFL)) | \ + (1 << DR_GETIGRP(IG_BSDFL))) +#define VAX_BASE (1 << DR_GETIGRP(IG_BASE)) +#define VAX_GFLOAT (1 << DR_GETIGRP(IG_BSGFL)) +#define VAX_DFLOAT (1 << DR_GETIGRP(IG_BSDFL)) +#define VAX_PACKED (1 << DR_GETIGRP(IG_PACKD)) +#define VAX_EXTAC (1 << DR_GETIGRP(IG_EXTAC)) +#define VAX_EMONL (1 << DR_GETIGRP(IG_EMONL)) +#define VAX_VECTR (1 << DR_GETIGRP(IG_VECTR)) +#define FULL_INSTRUCTION_SET (VAX_BASE | \ + (1 << DR_GETIGRP(IG_PACKD)) | \ + (1 << DR_GETIGRP(IG_EXTAC)) | \ + (1 << DR_GETIGRP(IG_EMONL))) + /* Decode ROM: specifier entry */ #define DR_ACMASK 0x300 /* type */ @@ -785,6 +839,9 @@ enum opcodes { #define VAX_IDLE_ELN 0x40 /* VAXELN */ extern uint32 cpu_idle_mask; /* idle mask */ extern int32 extra_bytes; /* bytes referenced by current string instruction */ +extern BITFIELD cpu_psl_bits[]; +extern char const * const opcode[]; +extern const uint16 drom[NUM_INST][MAX_SPEC + 1]; void cpu_idle (void); /* Instruction History */ @@ -941,9 +998,20 @@ extern void rom_wr_B (int32 pa, int32 val); #else /* VAX 3900 */ #include "vaxmod_defs.h" #endif +#ifndef CPU_INSTRUCTION_SET +#if defined (FULL_VAX) +#define CPU_INSTRUCTION_SET FULL_INSTRUCTION_SET +#else +#define CPU_INSTRUCTION_SET VAX_FULL_BASE +#endif +#endif #ifndef CPU_MODEL_MODIFIERS #define CPU_MODEL_MODIFIERS /* No model specific CPU modifiers */ #endif +#ifndef CPU_INST_MODIFIERS +#define CPU_INST_MODIFIERS { MTAB_XTD|MTAB_VDV, 0, "INSTRUCTIONS", "INSTRUCTIONS={F-FLOAT|D-FLOAT}", \ + &cpu_set_instruction_set, &cpu_show_instruction_set, NULL, "Set/Show the CPU Instruction Set" }, +#endif #ifndef IDX_IMM_TEST #define IDX_IMM_TEST RSVD_ADDR_FAULT #endif diff --git a/VAX/vax_fpa.c b/VAX/vax_fpa.c index f183e782..7f379084 100644 --- a/VAX/vax_fpa.c +++ b/VAX/vax_fpa.c @@ -196,12 +196,12 @@ t_uint64 n1, n2; if ((h1 & FD_EXP) == 0) { if (h1 & FPSIGN) - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(op_cmpfd); h1 = l1 = 0; } if ((h2 & FD_EXP) == 0) { if (h2 & FPSIGN) - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(op_cmpfd); h2 = l2 = 0; } if ((h1 ^ h2) & FPSIGN) @@ -219,12 +219,12 @@ t_uint64 n1, n2; if ((h1 & G_EXP) == 0) { if (h1 & FPSIGN) - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(op_cmpg); h1 = l1 = 0; } if ((h2 & G_EXP) == 0) { if (h2 & FPSIGN) - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(op_cmpg); h2 = l2 = 0; } if ((h1 ^ h2) & FPSIGN) @@ -508,7 +508,7 @@ r->sign = hi & FPSIGN; /* get sign */ r->exp = FD_GETEXP (hi); /* get exponent */ if (r->exp == 0) { /* exp = 0? */ if (r->sign) /* if -, rsvd op */ - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(unpackf); r->frac = 0; /* else 0 */ return; } @@ -523,7 +523,7 @@ r->sign = hi & FPSIGN; /* get sign */ r->exp = FD_GETEXP (hi); /* get exponent */ if (r->exp == 0) { /* exp = 0? */ if (r->sign) /* if -, rsvd op */ - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(unpackd); r->frac = 0; /* else 0 */ return; } @@ -538,7 +538,7 @@ r->sign = hi & FPSIGN; /* get sign */ r->exp = G_GETEXP (hi); /* get exponent */ if (r->exp == 0) { /* exp = 0? */ if (r->sign) /* if -, rsvd op */ - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(unpackg); r->frac = 0; /* else 0 */ return; } @@ -1327,7 +1327,7 @@ int32 op_movfd (int32 val) if (val & FD_EXP) return val; if (val & FPSIGN) - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(op_movfd); return 0; } @@ -1336,7 +1336,7 @@ int32 op_mnegfd (int32 val) if (val & FD_EXP) return (val ^ FPSIGN); if (val & FPSIGN) - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(op_mnegfd); return 0; } @@ -1345,7 +1345,7 @@ int32 op_movg (int32 val) if (val & G_EXP) return val; if (val & FPSIGN) - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(op_movg); return 0; } @@ -1354,7 +1354,7 @@ int32 op_mnegg (int32 val) if (val & G_EXP) return (val ^ FPSIGN); if (val & FPSIGN) - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(op_mnegg); return 0; } @@ -1504,7 +1504,7 @@ int32 ptr = opnd[2]; int32 i, wd, res; if (deg > 31) /* degree > 31? fault */ - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(op_polyf); unpackf (opnd[0], &a); /* unpack arg */ wd = Read (ptr, L_LONG, RD); /* get C0 */ ptr = ptr + 4; @@ -1533,7 +1533,7 @@ int32 ptr = opnd[3]; int32 i, wd, wd1, res, resh; if (deg > 31) /* degree > 31? fault */ - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(op_polyd); unpackd (opnd[0], opnd[1], &a); /* unpack arg */ wd = Read (ptr, L_LONG, RD); /* get C0 */ wd1 = Read (ptr + 4, L_LONG, RD); @@ -1567,7 +1567,7 @@ int32 ptr = opnd[3]; int32 i, wd, wd1, res, resh; if (deg > 31) /* degree > 31? fault */ - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(op_polyg); unpackg (opnd[0], opnd[1], &a); /* unpack arg */ wd = Read (ptr, L_LONG, RD); /* get C0 */ wd1 = Read (ptr + 4, L_LONG, RD); diff --git a/VAX/vax_octa.c b/VAX/vax_octa.c index 2891d2f6..3073e02a 100644 --- a/VAX/vax_octa.c +++ b/VAX/vax_octa.c @@ -433,7 +433,7 @@ switch (opc) { break; default: - RSVD_INST_FAULT; + RSVD_INST_FAULT(opc); } return cc; @@ -449,7 +449,7 @@ int32 op_tsth (int32 val) if (val & H_EXP) /* non-zero? */ return val; if (val & FPSIGN) /* reserved? */ - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(op_tsth); return 0; /* clean 0 */ } @@ -620,7 +620,7 @@ int32 ptr = opnd[5]; int32 i, wd[4], res[4]; if (deg > 31) /* deg > 31? fault */ - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(op_polyh); h_unpackh (&opnd[0], &a); /* unpack arg */ wd[0] = Read (ptr, L_LONG, RD); /* get C0 */ wd[1] = Read (ptr + 4, L_LONG, RD); @@ -1013,7 +1013,7 @@ r->exp = FD_GETEXP (hi); /* get exponent */ r->frac.f0 = r->frac.f1 = 0; /* low bits 0 */ if (r->exp == 0) { /* exp = 0? */ if (r->sign) /* if -, rsvd op */ - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(h_unpackfd); r->frac.f2 = r->frac.f3 = 0; /* else 0 */ return; } @@ -1030,7 +1030,7 @@ r->exp = G_GETEXP (hi); /* get exponent */ r->frac.f0 = r->frac.f1 = 0; /* low bits 0 */ if (r->exp == 0) { /* exp = 0? */ if (r->sign) /* if -, rsvd op */ - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(h_unpackg); r->frac.f2 = r->frac.f3 = 0; /* else 0 */ return; } @@ -1046,7 +1046,7 @@ r->sign = hflt[0] & FPSIGN; /* get sign */ r->exp = H_GETEXP (hflt[0]); /* get exponent */ if (r->exp == 0) { /* exp = 0? */ if (r->sign) /* if -, rsvd op */ - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(h_unpackh); r->frac.f0 = r->frac.f1 = 0; /* else 0 */ r->frac.f2 = r->frac.f3 = 0; return; @@ -1261,7 +1261,7 @@ return; int32 op_octa (int32 *opnd, int32 cc, int32 opc, int32 acc, int32 spec, int32 va, InstHistory *hst) { -RSVD_INST_FAULT; +RSVD_INST_FAULT(opc); return cc; } diff --git a/VAX/vax_sys.c b/VAX/vax_sys.c index 88dc9272..ea0d4d24 100644 --- a/VAX/vax_sys.c +++ b/VAX/vax_sys.c @@ -117,523 +117,534 @@ const char *sim_stop_messages[] = { const uint16 drom[NUM_INST][MAX_SPEC + 1] = { -{0, 0, 0, 0, 0, 0, 0}, /* HALT */ -{0, 0, 0, 0, 0, 0, 0}, /* NOP */ -{0, 0, 0, 0, 0, 0, 0}, /* REI */ -{0, 0, 0, 0, 0, 0, 0}, /* BPT */ -{0, 0, 0, 0, 0, 0, 0}, /* RET */ -{0, 0, 0, 0, 0, 0, 0}, /* RSB */ -{0, 0, 0, 0, 0, 0, 0}, /* LDPCTX */ -{0, 0, 0, 0, 0, 0, 0}, /* SVPCTX */ -{4+DR_F, RW, AB, RW, AB, 0, 0}, /* CVTPS */ -{4+DR_F, RW, AB, RW, AB, 0, 0}, /* CVTSP */ -{6 +RB_L, RL, RL, RL, RL, RL, WL}, /* INDEX */ -{4+DR_F +RB_L, AB, RL, RW, AB, 0, 0}, /* CRC */ -{3, RB, RW, AB, 0, 0, 0}, /* PROBER */ -{3, RB, RW, AB, 0, 0, 0}, /* PROBEW */ -{2, AB, AB, 0, 0, 0, 0}, /* INSQUE */ -{2, AB, WL, 0, 0, 0, 0}, /* REMQUE */ -{1, BB, 0, 0, 0, 0, 0}, /* BSBB */ -{1, BB, 0, 0, 0, 0, 0}, /* BRB */ -{1, BB, 0, 0, 0, 0, 0}, /* BNEQ */ -{1, BB, 0, 0, 0, 0, 0}, /* BEQL */ -{1, BB, 0, 0, 0, 0, 0}, /* BGTR */ -{1, BB, 0, 0, 0, 0, 0}, /* BLEQ */ -{1, AB, 0, 0, 0, 0, 0}, /* JSB */ -{1, AB, 0, 0, 0, 0, 0}, /* JMP */ -{1, BB, 0, 0, 0, 0, 0}, /* BGEQ */ -{1, BB, 0, 0, 0, 0, 0}, /* BLSS */ -{1, BB, 0, 0, 0, 0, 0}, /* BGTRU */ -{1, BB, 0, 0, 0, 0, 0}, /* BLEQU */ -{1, BB, 0, 0, 0, 0, 0}, /* BVC */ -{1, BB, 0, 0, 0, 0, 0}, /* BVS */ -{1, BB, 0, 0, 0, 0, 0}, /* BCC */ -{1, BB, 0, 0, 0, 0, 0}, /* BCS */ -{4+DR_F +RB_R3, RW, AB, RW, AB, 0, 0}, /* ADDP4 */ -{6+DR_F +RB_R5, RW, AB, RW, AB, RW, AB}, /* ADDP6 */ -{4+DR_F +RB_R3, RW, AB, RW, AB, 0, 0}, /* SUBP4 */ -{6+DR_F +RB_R5, RW, AB, RW, AB, RW, AB}, /* SUBP6 */ -{5+DR_F +RB_R3, RW, AB, AB, RW, AB, 0}, /* CVTPT */ -{6+DR_F +RB_R5, RW, AB, RW, AB, RW, AB}, /* MULP6 */ -{5+DR_F +RB_R3, RW, AB, AB, RW, AB, 0}, /* CVTTP */ -{6+DR_F +RB_R5, RW, AB, RW, AB, RW, AB}, /* DIVP6 */ -{3+DR_F +RB_R5, RW, AB, AB, 0, 0, 0}, /* MOVC3 */ -{3+DR_F +RB_R3, RW, AB, AB, 0, 0, 0}, /* CMPC3 */ -{4+DR_F +RB_R3, RW, AB, AB, RB, 0, 0}, /* SCANC */ -{4+DR_F +RB_R3, RW, AB, AB, RB, 0, 0}, /* SPANC */ -{5+DR_F +RB_R5, RW, AB, RB, RW, AB, 0}, /* MOVC5 */ -{5+DR_F +RB_R3, RW, AB, RB, RW, AB, 0}, /* CMPC5 */ -{6+DR_F +RB_R5, RW, AB, RB, AB, RW, AB}, /* MOVTC */ -{6+DR_F +RB_R3, RW, AB, RB, AB, RW, AB}, /* MOVTUC */ -{1, BW, 0, 0, 0, 0, 0}, /* BSBW */ -{1, BW, 0, 0, 0, 0, 0}, /* BRW */ -{2 +RB_L, RW, WL, 0, 0, 0, 0}, /* CVTWL */ -{2 +RB_B, RW, WB, 0, 0, 0, 0}, /* CVTWB */ -{3+DR_F +RB_R3, RW, AB, AB, 0, 0, 0}, /* MOVP */ -{3+DR_F +RB_R3, RW, AB, AB, 0, 0, 0}, /* CMPP3 */ -{3+DR_F +RB_L, RW, AB, WL, 0, 0, 0}, /* CVTPL */ -{4+DR_F +RB_R3, RW, AB, RW, AB, 0, 0}, /* CMPP4 */ -{4+DR_F +RB_R5, RW, AB, AB, AB, 0, 0}, /* EDITPC */ -{4+DR_F +RB_R3, RW, AB, RW, AB, 0, 0}, /* MATCHC */ -{3+DR_F +RB_R1, RB, RW, AB, 0, 0, 0}, /* LOCC */ -{3+DR_F +RB_R1, RB, RW, AB, 0, 0, 0}, /* SKPC */ -{2 +RB_L, RW, WL, 0, 0, 0, 0}, /* MOVZWL */ -{4, RW, RW, MW, BW, 0, 0}, /* ACBW */ -{2, AW, WL, 0, 0, 0, 0}, /* MOVAW */ -{1 +RB_SP, AW, 0, 0, 0, 0, 0}, /* PUSHAW */ -{2 +RB_L, RF, ML, 0, 0, 0, 0}, /* ADDF2 */ -{3 +RB_L, RF, RF, WL, 0, 0, 0}, /* ADDF3 */ -{2 +RB_L, RF, ML, 0, 0, 0, 0}, /* SUBF2 */ -{3 +RB_L, RF, RF, WL, 0, 0, 0}, /* SUBF3 */ -{2 +RB_L, RF, ML, 0, 0, 0, 0}, /* MULF2 */ -{3 +RB_L, RF, RF, WL, 0, 0, 0}, /* MULF3 */ -{2 +RB_L, RF, ML, 0, 0, 0, 0}, /* DIVF2 */ -{3 +RB_L, RF, RF, WL, 0, 0, 0}, /* DIVF3 */ -{2 +RB_B, RF, WB, 0, 0, 0, 0}, /* CVTFB */ -{2 +RB_W, RF, WW, 0, 0, 0, 0}, /* CVTFW */ -{2 +RB_L, RF, WL, 0, 0, 0, 0}, /* CVTFL */ -{2 +RB_L, RF, WL, 0, 0, 0, 0}, /* CVTRFL */ -{2 +RB_L, RB, WL, 0, 0, 0, 0}, /* CVTBF */ -{2 +RB_L, RW, WL, 0, 0, 0, 0}, /* CVTWF */ -{2 +RB_L, RL, WL, 0, 0, 0, 0}, /* CVTLF */ -{4, RF, RF, ML, BW, 0, 0}, /* ACBF */ -{2 +RB_L, RF, WL, 0, 0, 0, 0}, /* MOVF */ -{2, RF, RF, 0, 0, 0, 0}, /* CMPF */ -{2 +RB_L, RF, WL, 0, 0, 0, 0}, /* MNEGF */ -{1, RF, 0, 0, 0, 0, 0}, /* TSTF */ -{5, RF, RB, RF, WL, WL, 0}, /* EMODF */ -{3 +RB_R3, RF, RW, AB, 0, 0, 0}, /* POLYF */ -{2 +RB_Q, RF, WQ, 0, 0, 0, 0}, /* CVTFD */ -{0, 0, 0, 0, 0, 0, 0}, /* reserved */ -{2 +RB_W, RW, WW, 0, 0, 0, 0}, /* ADAWI */ -{0, 0, 0, 0, 0, 0, 0}, /* reserved */ -{0, 0, 0, 0, 0, 0, 0}, /* reserved */ -{0, 0, 0, 0, 0, 0, 0}, /* reserved */ -{2, AB, AQ, 0, 0, 0, 0}, /* INSQHI */ -{2, AB, AQ, 0, 0, 0, 0}, /* INSQTI */ -{2, AQ, WL, 0, 0, 0, 0}, /* REMQHI */ -{2, AQ, WL, 0, 0, 0, 0}, /* REMQTI */ -{2 +RB_Q, RD, MQ, 0, 0, 0, 0}, /* ADDD2 */ -{3 +RB_Q, RD, RD, WQ, 0, 0, 0}, /* ADDD3 */ -{2 +RB_Q, RD, MQ, 0, 0, 0, 0}, /* SUBD2 */ -{3 +RB_Q, RD, RD, WQ, 0, 0, 0}, /* SUBD3 */ -{2 +RB_Q, RD, MQ, 0, 0, 0, 0}, /* MULD2 */ -{3 +RB_Q, RD, RD, WQ, 0, 0, 0}, /* MULD3 */ -{2 +RB_Q, RD, MQ, 0, 0, 0, 0}, /* DIVD2 */ -{3 +RB_Q, RD, RD, WQ, 0, 0, 0}, /* DIVD3 */ -{2 +RB_B, RD, WB, 0, 0, 0, 0}, /* CVTDB */ -{2 +RB_W, RD, WW, 0, 0, 0, 0}, /* CVTDW */ -{2 +RB_L, RD, WL, 0, 0, 0, 0}, /* CVTDL */ -{2 +RB_L, RD, WL, 0, 0, 0, 0}, /* CVTRDL */ -{2 +RB_Q, RB, WQ, 0, 0, 0, 0}, /* CVTBD */ -{2 +RB_Q, RW, WQ, 0, 0, 0, 0}, /* CVTWD */ -{2 +RB_Q, RL, WQ, 0, 0, 0, 0}, /* CVTLD */ -{4, RD, RD, MQ, BW, 0, 0}, /* ACBD */ -{2 +RB_Q, RD, WQ, 0, 0, 0, 0}, /* MOVD */ -{2 +RB_Q, RD, RD, 0, 0, 0, 0}, /* CMPD */ -{2 +RB_Q, RD, WQ, 0, 0, 0, 0}, /* MNEGD */ -{1, RD, 0, 0, 0, 0, 0}, /* TSTD */ -{5, RD, RB, RD, WL, WQ, 0}, /* EMODD */ -{3 +RB_R5, RD, RW, AB, 0, 0, 0}, /* POLYD */ -{2 +RB_L, RD, WL, 0, 0, 0, 0}, /* CVTDF */ -{0, 0, 0, 0, 0, 0, 0}, /* reserved */ -{3 +RB_L, RB, RL, WL, 0, 0, 0}, /* ASHL */ -{3 +RB_Q, RB, RQ, WQ, 0, 0, 0}, /* ASHQ */ -{4, RL, RL, RL, WQ, 0, 0}, /* EMUL */ -{4, RL, RQ, WL, WL, 0, 0}, /* EDIV */ -{1 +RB_Q, WQ, 0, 0, 0, 0, 0}, /* CLRQ */ -{2 +RB_Q, RQ, WQ, 0, 0, 0, 0}, /* MOVQ */ -{2 +RB_L, AQ, WL, 0, 0, 0, 0}, /* MOVAQ */ -{1 +RB_SP, AQ, 0, 0, 0, 0, 0}, /* PUSHAQ */ -{2 +RB_B, RB, MB, 0, 0, 0, 0}, /* ADDB2 */ -{3 +RB_B, RB, RB, WB, 0, 0, 0}, /* ADDB3 */ -{2 +RB_B, RB, MB, 0, 0, 0, 0}, /* SUBB2 */ -{3 +RB_B, RB, RB, WB, 0, 0, 0}, /* SUBB3 */ -{2 +RB_B, RB, MB, 0, 0, 0, 0}, /* MULB2 */ -{3 +RB_B, RB, RB, WB, 0, 0, 0}, /* MULB3 */ -{2 +RB_B, RB, MB, 0, 0, 0, 0}, /* DIVB2 */ -{3 +RB_B, RB, RB, WB, 0, 0, 0}, /* DIVB3 */ -{2 +RB_B, RB, MB, 0, 0, 0, 0}, /* BISB2 */ -{3 +RB_B, RB, RB, WB, 0, 0, 0}, /* BISB3 */ -{2 +RB_B, RB, MB, 0, 0, 0, 0}, /* BICB2 */ -{3 +RB_B, RB, RB, WB, 0, 0, 0}, /* BICB3 */ -{2 +RB_B, RB, MB, 0, 0, 0, 0}, /* XORB2 */ -{3 +RB_B, RB, RB, WB, 0, 0, 0}, /* XORB3 */ -{2 +RB_B, RB, WB, 0, 0, 0, 0}, /* MNEGB */ -{3, RB, RB, RB, 0, 0, 0}, /* CASEB */ -{2 +RB_B, RB, WB, 0, 0, 0, 0}, /* MOVB */ -{2, RB, RB, 0, 0, 0, 0}, /* CMPB */ -{2 +RB_B, RB, WB, 0, 0, 0, 0}, /* MCOMB */ -{2 +RB_B, RB, RB, 0, 0, 0, 0}, /* BITB */ -{1 +RB_B, WB, 0, 0, 0, 0, 0}, /* CLRB */ -{1, RB, 0, 0, 0, 0, 0}, /* TSTB */ -{1 +RB_B, MB, 0, 0, 0, 0, 0}, /* INCB */ -{1 +RB_B, MB, 0, 0, 0, 0, 0}, /* DECB */ -{2 +RB_L, RB, WL, 0, 0, 0, 0}, /* CVTBL */ -{2 +RB_W, RB, WW, 0, 0, 0, 0}, /* CVTBW */ -{2 +RB_L, RB, WL, 0, 0, 0, 0}, /* MOVZBL */ -{2 +RB_W, RB, WW, 0, 0, 0, 0}, /* MOVZBW */ -{3 +RB_L, RB, RL, WL, 0, 0, 0}, /* ROTL */ -{4, RB, RB, MB, BW, 0, 0}, /* ACBB */ -{2 +RB_L, AB, WL, 0, 0, 0, 0}, /* MOVAB */ -{1 +RB_SP, AB, 0, 0, 0, 0, 0}, /* PUSHAB */ -{2 +RB_W, RW, MW, 0, 0, 0, 0}, /* ADDW2 */ -{3 +RB_W, RW, RW, WW, 0, 0, 0}, /* ADDW3 */ -{2 +RB_W, RW, MW, 0, 0, 0, 0}, /* SUBW2 */ -{3 +RB_W, RW, RW, WW, 0, 0, 0}, /* SUBW3 */ -{2 +RB_W, RW, MW, 0, 0, 0, 0}, /* MULW2 */ -{3 +RB_W, RW, RW, WW, 0, 0, 0}, /* MULW3 */ -{2 +RB_W, RW, MW, 0, 0, 0, 0}, /* DIVW2 */ -{3 +RB_W, RW, RW, WW, 0, 0, 0}, /* DIVW3 */ -{2 +RB_W, RW, MW, 0, 0, 0, 0}, /* BISW2 */ -{3 +RB_W, RW, RW, WW, 0, 0, 0}, /* BISW3 */ -{2 +RB_W, RW, MW, 0, 0, 0, 0}, /* BICW2 */ -{3 +RB_W, RW, RW, WW, 0, 0, 0}, /* BICW3 */ -{2 +RB_W, RW, MW, 0, 0, 0, 0}, /* XORW2 */ -{3 +RB_W, RW, RW, WW, 0, 0, 0}, /* XORW3 */ -{2 +RB_W, RW, WW, 0, 0, 0, 0}, /* MNEGW */ -{3, RW, RW, RW, 0, 0, 0}, /* CASEW */ -{2 +RB_W, RW, WW, 0, 0, 0, 0}, /* MOVW */ -{2, RW, RW, 0, 0, 0, 0}, /* CMPW */ -{2 +RB_W, RW, WW, 0, 0, 0, 0}, /* MCOMW */ -{2, RW, RW, 0, 0, 0, 0}, /* BITW */ -{1 +RB_W, WW, 0, 0, 0, 0, 0}, /* CLRW */ -{1, RW, 0, 0, 0, 0, 0}, /* TSTW */ -{1 +RB_W, MW, 0, 0, 0, 0, 0}, /* INCW */ -{1 +RB_W, MW, 0, 0, 0, 0, 0}, /* DECW */ -{1, RW, 0, 0, 0, 0, 0}, /* BISPSW */ -{1, RW, 0, 0, 0, 0, 0}, /* BICPSW */ -{1, RW, 0, 0, 0, 0, 0}, /* POPR */ -{1, RW, 0, 0, 0, 0, 0}, /* PUSHR */ -{1, RW, 0, 0, 0, 0, 0}, /* CHMK */ -{1, RW, 0, 0, 0, 0, 0}, /* CHME */ -{1, RW, 0, 0, 0, 0, 0}, /* CHMS */ -{1, RW, 0, 0, 0, 0, 0}, /* CHMU */ -{2 +RB_L, RL, ML, 0, 0, 0, 0}, /* ADDL2 */ -{3 +RB_L, RL, RL, WL, 0, 0, 0}, /* ADDL3 */ -{2 +RB_L, RL, ML, 0, 0, 0, 0}, /* SUBL2 */ -{3 +RB_L, RL, RL, WL, 0, 0, 0}, /* SUBL3 */ -{2 +RB_L, RL, ML, 0, 0, 0, 0}, /* MULL2 */ -{3 +RB_L, RL, RL, WL, 0, 0, 0}, /* MULL3 */ -{2 +RB_L, RL, ML, 0, 0, 0, 0}, /* DIVL2 */ -{3 +RB_L, RL, RL, WL, 0, 0, 0}, /* DIVL3 */ -{2 +RB_L, RL, ML, 0, 0, 0, 0}, /* BISL2 */ -{3 +RB_L, RL, RL, WL, 0, 0, 0}, /* BISL3 */ -{2 +RB_L, RL, ML, 0, 0, 0, 0}, /* BICL2 */ -{3 +RB_L, RL, RL, WL, 0, 0, 0}, /* BICL3 */ -{2 +RB_L, RL, ML, 0, 0, 0, 0}, /* XORL2 */ -{3 +RB_L, RL, RL, WL, 0, 0, 0}, /* XORL3 */ -{2 +RB_L, RL, WL, 0, 0, 0, 0}, /* MNEGL */ -{3, RL, RL, RL, 0, 0, 0}, /* CASEL */ -{2 +RB_L, RL, WL, 0, 0, 0, 0}, /* MOVL */ -{2, RL, RL, 0, 0, 0, 0}, /* CMPL */ -{2 +RB_L, RL, WL, 0, 0, 0, 0}, /* MCOML */ -{2, RL, RL, 0, 0, 0, 0}, /* BITL */ -{1 +RB_L, WL, 0, 0, 0, 0, 0}, /* CLRL */ -{1, RL, 0, 0, 0, 0, 0}, /* TSTL */ -{1 +RB_L, ML, 0, 0, 0, 0, 0}, /* INCL */ -{1 +RB_L, ML, 0, 0, 0, 0, 0}, /* DECL */ -{2 +RB_L, RL, ML, 0, 0, 0, 0}, /* ADWC */ -{2 +RB_L, RL, ML, 0, 0, 0, 0}, /* SBWC */ -{2, RL, RL, 0, 0, 0, 0}, /* MTPR */ -{2 +RB_L, RL, WL, 0, 0, 0, 0}, /* MFPR */ -{1 +RB_L, WL, 0, 0, 0, 0, 0}, /* MOVPSL */ -{1 +RB_SP, RL, 0, 0, 0, 0, 0}, /* PUSHL */ -{2 +RB_L, AL, WL, 0, 0, 0, 0}, /* MOVAL */ -{1 +RB_SP, AL, 0, 0, 0, 0, 0}, /* PUSHAL */ -{3, RL, VB, BB, 0, 0, 0}, /* BBS */ -{3, RL, VB, BB, 0, 0, 0}, /* BBC */ -{3, RL, VB, BB, 0, 0, 0}, /* BBSS */ -{3, RL, VB, BB, 0, 0, 0}, /* BBCS */ -{3, RL, VB, BB, 0, 0, 0}, /* BBSC */ -{3, RL, VB, BB, 0, 0, 0}, /* BBCC */ -{3, RL, VB, BB, 0, 0, 0}, /* BBSSI */ -{3, RL, VB, BB, 0, 0, 0}, /* BBCCI */ -{2, RL, BB, 0, 0, 0, 0}, /* BLBS */ -{2, RL, BB, 0, 0, 0, 0}, /* BLBC */ -{4 +RB_L, RL, RB, VB, WL, 0, 0}, /* FFS */ -{4 +RB_L, RL, RB, VB, WL, 0, 0}, /* FFC */ -{4, RL, RB, VB, RL, 0, 0}, /* CMPV */ -{4, RL, RB, VB, RL, 0, 0}, /* CMPZV */ -{4 +RB_L, RL, RB, VB, WL, 0, 0}, /* EXTV */ -{4 +RB_L, RL, RB, VB, WL, 0, 0}, /* EXTZV */ -{4, RL, RL, RB, VB, 0, 0}, /* INSV */ -{4, RL, RL, ML, BW, 0, 0}, /* ACBL */ -{3, RL, ML, BB, 0, 0, 0}, /* AOBLSS */ -{3, RL, ML, BB, 0, 0, 0}, /* AOBLEQ */ -{2, ML, BB, 0, 0, 0, 0}, /* SOBGEQ */ -{2, ML, BB, 0, 0, 0, 0}, /* SOBGTR */ -{2 +RB_B, RL, WB, 0, 0, 0, 0}, /* CVTLB */ -{2 +RB_W, RL, WW, 0, 0, 0, 0}, /* CVTLW */ -{6+DR_F+RB_R3, RB, RW, AB, RB, RW, AB}, /* ASHP */ -{3+DR_F+RB_R3, RL, RW, AB, 0, 0, 0}, /* CVTLP */ -{2, AB, AB, 0, 0, 0, 0}, /* CALLG */ -{2, RL, AB, 0, 0, 0, 0}, /* CALLS */ -{0, 0, 0, 0, 0, 0, 0}, /* XFC */ -{0, 0, 0, 0, 0, 0, 0}, /* 0FD */ -{0, 0, 0, 0, 0, 0, 0}, /* 0FE */ -{0, 0, 0, 0, 0, 0, 0}, /* 0FF */ -{0, 0, 0, 0, 0, 0, 0}, /* 100-10F */ -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, /* 110-11F */ -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, /* 120-12F */ -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, /* 130-13F */ -{0, 0, 0, 0, 0, 0, 0}, -{ODC(2) +RB_O, RD, WO, 0, 0, 0, 0}, /* CVTDH */ -{2 +RB_L, RG, WL, 0, 0, 0, 0}, /* CVTGF */ -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{2 +RB_Q, RG, MQ, 0, 0, 0, 0}, /* ADDG2 */ -{3 +RB_Q, RG, RG, WQ, 0, 0, 0}, /* ADDG3 */ -{2 +RB_Q, RG, MQ, 0, 0, 0, 0}, /* SUBG2 */ -{3 +RB_Q, RG, RG, WQ, 0, 0, 0}, /* SUBG3 */ -{2 +RB_Q, RG, MQ, 0, 0, 0, 0}, /* MULG2 */ -{3 +RB_Q, RG, RG, WQ, 0, 0, 0}, /* MULG3 */ -{2 +RB_Q, RG, MQ, 0, 0, 0, 0}, /* DIVG2 */ -{3 +RB_Q, RG, RG, WQ, 0, 0, 0}, /* DIVG3 */ -{2 +RB_B, RG, WB, 0, 0, 0, 0}, /* CVTGB */ -{2 +RB_W, RG, WW, 0, 0, 0, 0}, /* CVTGW */ -{2 +RB_L, RG, WL, 0, 0, 0, 0}, /* CVTGL */ -{2 +RB_L, RG, WL, 0, 0, 0, 0}, /* CVTRGL */ -{2 +RB_Q, RB, WQ, 0, 0, 0, 0}, /* CVTBG */ -{2 +RB_Q, RW, WQ, 0, 0, 0, 0}, /* CVTWG */ -{2 +RB_Q, RL, WQ, 0, 0, 0, 0}, /* CVTLG */ -{4, RG, RG, MQ, BW, 0, 0}, /* ACBG */ -{2 +RB_Q, RG, WQ, 0, 0, 0, 0}, /* MOVG */ -{2, RG, RG, 0, 0, 0, 0}, /* CMPG */ -{2 +RB_Q, RG, WQ, 0, 0, 0, 0}, /* MNEGG */ -{1, RG, 0, 0, 0, 0, 0}, /* TSTG */ -{5, RG, RW, RG, WL, WQ, 0}, /* EMODG */ -{3 +RB_R5, RG, RW, AB, 0, 0, 0}, /* POLYG */ -{ODC(2) +RB_O, RG, WO, 0, 0, 0, 0}, /* CVTGH */ -{0, 0, 0, 0, 0, 0, 0}, /* reserved */ -{0, 0, 0, 0, 0, 0, 0}, /* reserved */ -{0, 0, 0, 0, 0, 0, 0}, /* reserved */ -{0, 0, 0, 0, 0, 0, 0}, /* reserved */ -{0, 0, 0, 0, 0, 0, 0}, /* reserved */ -{0, 0, 0, 0, 0, 0, 0}, /* reserved */ -{0, 0, 0, 0, 0, 0, 0}, /* reserved */ -{0, 0, 0, 0, 0, 0, 0}, /* reserved */ -{0, 0, 0, 0, 0, 0, 0}, /* reserved */ -{ODC(2) +RB_O, RH, MO, 0, 0, 0, 0}, /* ADDH2 */ -{ODC(3) +RB_O, RH, RH, WO, 0, 0, 0}, /* ADDH3 */ -{ODC(2) +RB_O, RH, MO, 0, 0, 0, 0}, /* SUBH2 */ -{ODC(3) +RB_O, RH, RH, WO, 0, 0, 0}, /* SUBH3 */ -{ODC(2) +RB_O, RH, MO, 0, 0, 0, 0}, /* MULH2 */ -{ODC(3) +RB_O, RH, RH, WO, 0, 0, 0}, /* MULH3 */ -{ODC(2) +RB_O, RH, MO, 0, 0, 0, 0}, /* DIVH2 */ -{ODC(3) +RB_O, RH, RH, WO, 0, 0, 0}, /* DIVH3 */ -{ODC(2) +RB_OB, RH, WB, 0, 0, 0, 0}, /* CVTHB */ -{ODC(2) +RB_OW, RH, WW, 0, 0, 0, 0}, /* CVTHW */ -{ODC(2) +RB_OL, RH, WL, 0, 0, 0, 0}, /* CVTHL */ -{ODC(2) +RB_OL, RH, WL, 0, 0, 0, 0}, /* CVTRHL */ -{ODC(2) +RB_O, RB, WO, 0, 0, 0, 0}, /* CVTBH */ -{ODC(2) +RB_O, RW, WO, 0, 0, 0, 0}, /* CVTWH */ -{ODC(2) +RB_O, RL, WO, 0, 0, 0, 0}, /* CVTLH */ -{ODC(4) +RB_O, RH, RH, MO, BW, 0, 0}, /* ACBH */ -{ODC(2) +RB_O, RH, RO, 0, 0, 0, 0}, /* MOVH */ -{ODC(2), RH, RH, 0, 0, 0, 0}, /* CMPH */ -{ODC(2) +RB_O, RH, WO, 0, 0, 0, 0}, /* MNEGH */ -{ODC(1), RH, 0, 0, 0, 0, 0}, /* TSTH */ -{ODC(5) +RB_O, RH, RW, RH, WL, WO, 0}, /* EMODH */ -{ODC(3) +RB_R5, RH, RW, AB, 0, 0, 0}, /* POLYH */ -{ODC(2) +RB_OQ, RH, WQ, 0, 0, 0, 0}, /* CVTHG */ -{0, 0, 0, 0, 0, 0, 0}, /* reserved */ -{0, 0, 0, 0, 0, 0, 0}, /* reserved */ -{0, 0, 0, 0, 0, 0, 0}, /* reserved */ -{0, 0, 0, 0, 0, 0, 0}, /* reserved */ -{0, 0, 0, 0, 0, 0, 0}, /* reserved */ -{ODC(1) +RB_O, WO, 0, 0, 0, 0, 0}, /* CLRO */ -{ODC(2) +RB_O, RO, RO, 0, 0, 0, 0}, /* MOVO */ -{ODC(2) +RB_OL, AO, WL, 0, 0, 0, 0}, /* MOVAO*/ -{ODC(1) +RB_SP, AO, 0, 0, 0, 0, 0}, /* PUSHAO*/ -{0, 0, 0, 0, 0, 0, 0}, /* 180-18F */ -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, /* 190-19F */ -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{ODC(2) +RB_O, RF, WO, 0, 0, 0, 0}, /* CVTFH */ -{2 +RB_Q, RF, WQ, 0, 0, 0, 0}, /* CVTFG */ -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, /* 1A0-1AF */ -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, /* 1B0-1BF */ -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, /* 1C0-1CF */ -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, /* 1D0-1DF */ -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, /* 1E0-1EF */ -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, /* 1F0-1FF */ -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{ODC(2) +RB_OL, RH, WL, 0, 0, 0, 0}, /* CVTHF */ -{ODC(2) +RB_OQ, RH, WQ, 0, 0, 0, 0}, /* CVTHD */ -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0}, -{0, 0, 0, 0, 0, 0, 0} +{0 +IG_BASE, 0, 0, 0, 0, 0, 0}, /* HALT */ /* 000-00F */ +{0 +IG_BASE, 0, 0, 0, 0, 0, 0}, /* NOP */ +{0 +IG_BASE, 0, 0, 0, 0, 0, 0}, /* REI */ +{0 +IG_BASE, 0, 0, 0, 0, 0, 0}, /* BPT */ +{0 +IG_BASE, 0, 0, 0, 0, 0, 0}, /* RET */ +{0 +IG_BASE, 0, 0, 0, 0, 0, 0}, /* RSB */ +{0 +IG_BASE, 0, 0, 0, 0, 0, 0}, /* LDPCTX */ +{0 +IG_BASE, 0, 0, 0, 0, 0, 0}, /* SVPCTX */ +{4+DR_F +IG_PACKD, RW, AB, RW, AB, 0, 0}, /* CVTPS */ +{4+DR_F +IG_PACKD, RW, AB, RW, AB, 0, 0}, /* CVTSP */ +{6 +RB_L +IG_BASE, RL, RL, RL, RL, RL, WL}, /* INDEX */ +{4+DR_F +RB_L +IG_EMONL, AB, RL, RW, AB, 0, 0}, /* CRC */ +{3 +IG_BASE, RB, RW, AB, 0, 0, 0}, /* PROBER */ +{3 +IG_BASE, RB, RW, AB, 0, 0, 0}, /* PROBEW */ +{2 +IG_BASE, AB, AB, 0, 0, 0, 0}, /* INSQUE */ +{2 +IG_BASE, AB, WL, 0, 0, 0, 0}, /* REMQUE */ +{1 +IG_BASE, BB, 0, 0, 0, 0, 0}, /* BSBB */ /* 010-01F */ +{1 +IG_BASE, BB, 0, 0, 0, 0, 0}, /* BRB */ +{1 +IG_BASE, BB, 0, 0, 0, 0, 0}, /* BNEQ */ +{1 +IG_BASE, BB, 0, 0, 0, 0, 0}, /* BEQL */ +{1 +IG_BASE, BB, 0, 0, 0, 0, 0}, /* BGTR */ +{1 +IG_BASE, BB, 0, 0, 0, 0, 0}, /* BLEQ */ +{1 +IG_BASE, AB, 0, 0, 0, 0, 0}, /* JSB */ +{1 +IG_BASE, AB, 0, 0, 0, 0, 0}, /* JMP */ +{1 +IG_BASE, BB, 0, 0, 0, 0, 0}, /* BGEQ */ +{1 +IG_BASE, BB, 0, 0, 0, 0, 0}, /* BLSS */ +{1 +IG_BASE, BB, 0, 0, 0, 0, 0}, /* BGTRU */ +{1 +IG_BASE, BB, 0, 0, 0, 0, 0}, /* BLEQU */ +{1 +IG_BASE, BB, 0, 0, 0, 0, 0}, /* BVC */ +{1 +IG_BASE, BB, 0, 0, 0, 0, 0}, /* BVS */ +{1 +IG_BASE, BB, 0, 0, 0, 0, 0}, /* BCC */ +{1 +IG_BASE, BB, 0, 0, 0, 0, 0}, /* BCS */ +{4+DR_F +RB_R3 +IG_PACKD, RW, AB, RW, AB, 0, 0}, /* ADDP4 */ /* 020-02F */ +{6+DR_F +RB_R5 +IG_PACKD, RW, AB, RW, AB, RW, AB}, /* ADDP6 */ +{4+DR_F +RB_R3 +IG_PACKD, RW, AB, RW, AB, 0, 0}, /* SUBP4 */ +{6+DR_F +RB_R5 +IG_PACKD, RW, AB, RW, AB, RW, AB}, /* SUBP6 */ +{5+DR_F +RB_R3 +IG_PACKD, RW, AB, AB, RW, AB, 0}, /* CVTPT */ +{6+DR_F +RB_R5 +IG_PACKD, RW, AB, RW, AB, RW, AB}, /* MULP6 */ +{5+DR_F +RB_R3 +IG_PACKD, RW, AB, AB, RW, AB, 0}, /* CVTTP */ +{6+DR_F +RB_R5 +IG_PACKD, RW, AB, RW, AB, RW, AB}, /* DIVP6 */ +{3+DR_F +RB_R5 +IG_BASE, RW, AB, AB, 0, 0, 0}, /* MOVC3 */ +{3+DR_F +RB_R3 +IG_BASE, RW, AB, AB, 0, 0, 0}, /* CMPC3 */ +{4+DR_F +RB_R3 +IG_BASE, RW, AB, AB, RB, 0, 0}, /* SCANC */ +{4+DR_F +RB_R3 +IG_BASE, RW, AB, AB, RB, 0, 0}, /* SPANC */ +{5+DR_F +RB_R5 +IG_BASE, RW, AB, RB, RW, AB, 0}, /* MOVC5 */ +#if defined (VAX_610) +{5+DR_F +RB_R3 +IG_EMONL, RW, AB, RB, RW, AB, 0}, /* CMPC5 */ +#else +{5+DR_F +RB_R3 +IG_BASE, RW, AB, RB, RW, AB, 0}, /* CMPC5 */ +#endif +{6+DR_F +RB_R5 +IG_EMONL, RW, AB, RB, AB, RW, AB}, /* MOVTC */ +{6+DR_F +RB_R3 +IG_EMONL, RW, AB, RB, AB, RW, AB}, /* MOVTUC */ +{1 +IG_BASE, BW, 0, 0, 0, 0, 0}, /* BSBW */ /* 030-03F */ +{1 +IG_BASE, BW, 0, 0, 0, 0, 0}, /* BRW */ +{2 +RB_L +IG_BASE, RW, WL, 0, 0, 0, 0}, /* CVTWL */ +{2 +RB_B +IG_BASE, RW, WB, 0, 0, 0, 0}, /* CVTWB */ +{3+DR_F +RB_R3 +IG_PACKD, RW, AB, AB, 0, 0, 0}, /* MOVP */ +{3+DR_F +RB_R3 +IG_PACKD, RW, AB, AB, 0, 0, 0}, /* CMPP3 */ +{3+DR_F +RB_L +IG_PACKD, RW, AB, WL, 0, 0, 0}, /* CVTPL */ +{4+DR_F +RB_R3 +IG_PACKD, RW, AB, RW, AB, 0, 0}, /* CMPP4 */ +{4+DR_F +RB_R5 +IG_EMONL, RW, AB, AB, AB, 0, 0}, /* EDITPC */ +{4+DR_F +RB_R3 +IG_EMONL, RW, AB, RW, AB, 0, 0}, /* MATCHC */ +{3+DR_F +RB_R1 +IG_BASE, RB, RW, AB, 0, 0, 0}, /* LOCC */ +{3+DR_F +RB_R1 +IG_BASE, RB, RW, AB, 0, 0, 0}, /* SKPC */ +{2 +RB_L +IG_BASE, RW, WL, 0, 0, 0, 0}, /* MOVZWL */ +{4 +IG_BASE, RW, RW, MW, BW, 0, 0}, /* ACBW */ +{2 +IG_BASE, AW, WL, 0, 0, 0, 0}, /* MOVAW */ +{1 +RB_SP +IG_BASE, AW, 0, 0, 0, 0, 0}, /* PUSHAW */ +{2 +RB_L +IG_BASE, RF, ML, 0, 0, 0, 0}, /* ADDF2 */ /* 040-04F */ +{3 +RB_L +IG_BASE, RF, RF, WL, 0, 0, 0}, /* ADDF3 */ +{2 +RB_L +IG_BASE, RF, ML, 0, 0, 0, 0}, /* SUBF2 */ +{3 +RB_L +IG_BASE, RF, RF, WL, 0, 0, 0}, /* SUBF3 */ +{2 +RB_L +IG_BASE, RF, ML, 0, 0, 0, 0}, /* MULF2 */ +{3 +RB_L +IG_BASE, RF, RF, WL, 0, 0, 0}, /* MULF3 */ +{2 +RB_L +IG_BASE, RF, ML, 0, 0, 0, 0}, /* DIVF2 */ +{3 +RB_L +IG_BASE, RF, RF, WL, 0, 0, 0}, /* DIVF3 */ +{2 +RB_B +IG_BASE, RF, WB, 0, 0, 0, 0}, /* CVTFB */ +{2 +RB_W +IG_BASE, RF, WW, 0, 0, 0, 0}, /* CVTFW */ +{2 +RB_L +IG_BASE, RF, WL, 0, 0, 0, 0}, /* CVTFL */ +{2 +RB_L +IG_BASE, RF, WL, 0, 0, 0, 0}, /* CVTRFL */ +{2 +RB_L +IG_BASE, RB, WL, 0, 0, 0, 0}, /* CVTBF */ +{2 +RB_L +IG_BASE, RW, WL, 0, 0, 0, 0}, /* CVTWF */ +{2 +RB_L +IG_BASE, RL, WL, 0, 0, 0, 0}, /* CVTLF */ +{4 +IG_EMONL, RF, RF, ML, BW, 0, 0}, /* ACBF */ +{2 +RB_L +IG_BASE, RF, WL, 0, 0, 0, 0}, /* MOVF */ /* 050-05F */ +{2 +IG_BASE, RF, RF, 0, 0, 0, 0}, /* CMPF */ +{2 +RB_L +IG_BASE, RF, WL, 0, 0, 0, 0}, /* MNEGF */ +{1 +IG_BASE, RF, 0, 0, 0, 0, 0}, /* TSTF */ +{5 +IG_EMONL, RF, RB, RF, WL, WL, 0}, /* EMODF */ +{3 +RB_R3 +IG_EMONL, RF, RW, AB, 0, 0, 0}, /* POLYF */ +{2 +RB_Q +IG_BSDFL, RF, WQ, 0, 0, 0, 0}, /* CVTFD */ +{0 +IG_RSVD, 0, 0, 0, 0, 0, 0}, /* reserved */ +{2 +RB_W +IG_BASE, RW, WW, 0, 0, 0, 0}, /* ADAWI */ +{0 +IG_RSVD, 0, 0, 0, 0, 0, 0}, /* reserved */ +{0 +IG_RSVD, 0, 0, 0, 0, 0, 0}, /* reserved */ +{0 +IG_RSVD, 0, 0, 0, 0, 0, 0}, /* reserved */ +{2 +IG_BASE, AB, AQ, 0, 0, 0, 0}, /* INSQHI */ +{2 +IG_BASE, AB, AQ, 0, 0, 0, 0}, /* INSQTI */ +{2 +IG_BASE, AQ, WL, 0, 0, 0, 0}, /* REMQHI */ +{2 +IG_BASE, AQ, WL, 0, 0, 0, 0}, /* REMQTI */ +{2 +RB_Q +IG_BSDFL, RD, MQ, 0, 0, 0, 0}, /* ADDD2 */ /* 060-06F */ +{3 +RB_Q +IG_BSDFL, RD, RD, WQ, 0, 0, 0}, /* ADDD3 */ +{2 +RB_Q +IG_BSDFL, RD, MQ, 0, 0, 0, 0}, /* SUBD2 */ +{3 +RB_Q +IG_BSDFL, RD, RD, WQ, 0, 0, 0}, /* SUBD3 */ +{2 +RB_Q +IG_BSDFL, RD, MQ, 0, 0, 0, 0}, /* MULD2 */ +{3 +RB_Q +IG_BSDFL, RD, RD, WQ, 0, 0, 0}, /* MULD3 */ +{2 +RB_Q +IG_BSDFL, RD, MQ, 0, 0, 0, 0}, /* DIVD2 */ +{3 +RB_Q +IG_BSDFL, RD, RD, WQ, 0, 0, 0}, /* DIVD3 */ +{2 +RB_B +IG_BSDFL, RD, WB, 0, 0, 0, 0}, /* CVTDB */ +{2 +RB_W +IG_BSDFL, RD, WW, 0, 0, 0, 0}, /* CVTDW */ +{2 +RB_L +IG_BSDFL, RD, WL, 0, 0, 0, 0}, /* CVTDL */ +{2 +RB_L +IG_BSDFL, RD, WL, 0, 0, 0, 0}, /* CVTRDL */ +{2 +RB_Q +IG_BSDFL, RB, WQ, 0, 0, 0, 0}, /* CVTBD */ +{2 +RB_Q +IG_BSDFL, RW, WQ, 0, 0, 0, 0}, /* CVTWD */ +{2 +RB_Q +IG_BSDFL, RL, WQ, 0, 0, 0, 0}, /* CVTLD */ +{4 +IG_EMONL, RD, RD, MQ, BW, 0, 0}, /* ACBD */ +{2 +RB_Q +IG_BSDFL, RD, WQ, 0, 0, 0, 0}, /* MOVD */ /* 070-07F */ +{2 +RB_Q +IG_BSDFL, RD, RD, 0, 0, 0, 0}, /* CMPD */ +{2 +RB_Q +IG_BSDFL, RD, WQ, 0, 0, 0, 0}, /* MNEGD */ +{1 +IG_BSDFL, RD, 0, 0, 0, 0, 0}, /* TSTD */ +{5 +IG_EMONL, RD, RB, RD, WL, WQ, 0}, /* EMODD */ +{3 +RB_R5 +IG_EMONL, RD, RW, AB, 0, 0, 0}, /* POLYD */ +{2 +RB_L +IG_BSDFL, RD, WL, 0, 0, 0, 0}, /* CVTDF */ +{0 +IG_RSVD, 0, 0, 0, 0, 0, 0}, /* reserved */ +{3 +RB_L +IG_BASE, RB, RL, WL, 0, 0, 0}, /* ASHL */ +{3 +RB_Q +IG_BASE, RB, RQ, WQ, 0, 0, 0}, /* ASHQ */ +{4 +IG_BASE, RL, RL, RL, WQ, 0, 0}, /* EMUL */ +{4 +IG_BASE, RL, RQ, WL, WL, 0, 0}, /* EDIV */ +{1 +RB_Q +IG_BASE, WQ, 0, 0, 0, 0, 0}, /* CLRQ */ +{2 +RB_Q +IG_BASE, RQ, WQ, 0, 0, 0, 0}, /* MOVQ */ +{2 +RB_L +IG_BASE, AQ, WL, 0, 0, 0, 0}, /* MOVAQ */ +{1 +RB_SP +IG_BASE, AQ, 0, 0, 0, 0, 0}, /* PUSHAQ */ +{2 +RB_B +IG_BASE, RB, MB, 0, 0, 0, 0}, /* ADDB2 */ /* 080-08F */ +{3 +RB_B +IG_BASE, RB, RB, WB, 0, 0, 0}, /* ADDB3 */ +{2 +RB_B +IG_BASE, RB, MB, 0, 0, 0, 0}, /* SUBB2 */ +{3 +RB_B +IG_BASE, RB, RB, WB, 0, 0, 0}, /* SUBB3 */ +{2 +RB_B +IG_BASE, RB, MB, 0, 0, 0, 0}, /* MULB2 */ +{3 +RB_B +IG_BASE, RB, RB, WB, 0, 0, 0}, /* MULB3 */ +{2 +RB_B +IG_BASE, RB, MB, 0, 0, 0, 0}, /* DIVB2 */ +{3 +RB_B +IG_BASE, RB, RB, WB, 0, 0, 0}, /* DIVB3 */ +{2 +RB_B +IG_BASE, RB, MB, 0, 0, 0, 0}, /* BISB2 */ +{3 +RB_B +IG_BASE, RB, RB, WB, 0, 0, 0}, /* BISB3 */ +{2 +RB_B +IG_BASE, RB, MB, 0, 0, 0, 0}, /* BICB2 */ +{3 +RB_B +IG_BASE, RB, RB, WB, 0, 0, 0}, /* BICB3 */ +{2 +RB_B +IG_BASE, RB, MB, 0, 0, 0, 0}, /* XORB2 */ +{3 +RB_B +IG_BASE, RB, RB, WB, 0, 0, 0}, /* XORB3 */ +{2 +RB_B +IG_BASE, RB, WB, 0, 0, 0, 0}, /* MNEGB */ +{3 +IG_BASE, RB, RB, RB, 0, 0, 0}, /* CASEB */ +{2 +RB_B +IG_BASE, RB, WB, 0, 0, 0, 0}, /* MOVB */ /* 090-09F */ +{2 +IG_BASE, RB, RB, 0, 0, 0, 0}, /* CMPB */ +{2 +RB_B +IG_BASE, RB, WB, 0, 0, 0, 0}, /* MCOMB */ +{2 +RB_B +IG_BASE, RB, RB, 0, 0, 0, 0}, /* BITB */ +{1 +RB_B +IG_BASE, WB, 0, 0, 0, 0, 0}, /* CLRB */ +{1 +IG_BASE, RB, 0, 0, 0, 0, 0}, /* TSTB */ +{1 +RB_B +IG_BASE, MB, 0, 0, 0, 0, 0}, /* INCB */ +{1 +RB_B +IG_BASE, MB, 0, 0, 0, 0, 0}, /* DECB */ +{2 +RB_L +IG_BASE, RB, WL, 0, 0, 0, 0}, /* CVTBL */ +{2 +RB_W +IG_BASE, RB, WW, 0, 0, 0, 0}, /* CVTBW */ +{2 +RB_L +IG_BASE, RB, WL, 0, 0, 0, 0}, /* MOVZBL */ +{2 +RB_W +IG_BASE, RB, WW, 0, 0, 0, 0}, /* MOVZBW */ +{3 +RB_L +IG_BASE, RB, RL, WL, 0, 0, 0}, /* ROTL */ +{4 +IG_BASE, RB, RB, MB, BW, 0, 0}, /* ACBB */ +{2 +RB_L +IG_BASE, AB, WL, 0, 0, 0, 0}, /* MOVAB */ +{1 +RB_SP +IG_BASE, AB, 0, 0, 0, 0, 0}, /* PUSHAB */ +{2 +RB_W +IG_BASE, RW, MW, 0, 0, 0, 0}, /* ADDW2 */ /* 0A0-0AF */ +{3 +RB_W +IG_BASE, RW, RW, WW, 0, 0, 0}, /* ADDW3 */ +{2 +RB_W +IG_BASE, RW, MW, 0, 0, 0, 0}, /* SUBW2 */ +{3 +RB_W +IG_BASE, RW, RW, WW, 0, 0, 0}, /* SUBW3 */ +{2 +RB_W +IG_BASE, RW, MW, 0, 0, 0, 0}, /* MULW2 */ +{3 +RB_W +IG_BASE, RW, RW, WW, 0, 0, 0}, /* MULW3 */ +{2 +RB_W +IG_BASE, RW, MW, 0, 0, 0, 0}, /* DIVW2 */ +{3 +RB_W +IG_BASE, RW, RW, WW, 0, 0, 0}, /* DIVW3 */ +{2 +RB_W +IG_BASE, RW, MW, 0, 0, 0, 0}, /* BISW2 */ +{3 +RB_W +IG_BASE, RW, RW, WW, 0, 0, 0}, /* BISW3 */ +{2 +RB_W +IG_BASE, RW, MW, 0, 0, 0, 0}, /* BICW2 */ +{3 +RB_W +IG_BASE, RW, RW, WW, 0, 0, 0}, /* BICW3 */ +{2 +RB_W +IG_BASE, RW, MW, 0, 0, 0, 0}, /* XORW2 */ +{3 +RB_W +IG_BASE, RW, RW, WW, 0, 0, 0}, /* XORW3 */ +{2 +RB_W +IG_BASE, RW, WW, 0, 0, 0, 0}, /* MNEGW */ +{3 +IG_BASE, RW, RW, RW, 0, 0, 0}, /* CASEW */ +{2 +RB_W +IG_BASE, RW, WW, 0, 0, 0, 0}, /* MOVW */ /* 0B0-0BF */ +{2 +IG_BASE, RW, RW, 0, 0, 0, 0}, /* CMPW */ +{2 +RB_W +IG_BASE, RW, WW, 0, 0, 0, 0}, /* MCOMW */ +{2 +IG_BASE, RW, RW, 0, 0, 0, 0}, /* BITW */ +{1 +RB_W +IG_BASE, WW, 0, 0, 0, 0, 0}, /* CLRW */ +{1 +IG_BASE, RW, 0, 0, 0, 0, 0}, /* TSTW */ +{1 +RB_W +IG_BASE, MW, 0, 0, 0, 0, 0}, /* INCW */ +{1 +RB_W +IG_BASE, MW, 0, 0, 0, 0, 0}, /* DECW */ +{1 +IG_BASE, RW, 0, 0, 0, 0, 0}, /* BISPSW */ +{1 +IG_BASE, RW, 0, 0, 0, 0, 0}, /* BICPSW */ +{1 +IG_BASE, RW, 0, 0, 0, 0, 0}, /* POPR */ +{1 +IG_BASE, RW, 0, 0, 0, 0, 0}, /* PUSHR */ +{1 +IG_BASE, RW, 0, 0, 0, 0, 0}, /* CHMK */ +{1 +IG_BASE, RW, 0, 0, 0, 0, 0}, /* CHME */ +{1 +IG_BASE, RW, 0, 0, 0, 0, 0}, /* CHMS */ +{1 +IG_BASE, RW, 0, 0, 0, 0, 0}, /* CHMU */ +{2 +RB_L +IG_BASE, RL, ML, 0, 0, 0, 0}, /* ADDL2 */ /* 0C0-0CF */ +{3 +RB_L +IG_BASE, RL, RL, WL, 0, 0, 0}, /* ADDL3 */ +{2 +RB_L +IG_BASE, RL, ML, 0, 0, 0, 0}, /* SUBL2 */ +{3 +RB_L +IG_BASE, RL, RL, WL, 0, 0, 0}, /* SUBL3 */ +{2 +RB_L +IG_BASE, RL, ML, 0, 0, 0, 0}, /* MULL2 */ +{3 +RB_L +IG_BASE, RL, RL, WL, 0, 0, 0}, /* MULL3 */ +{2 +RB_L +IG_BASE, RL, ML, 0, 0, 0, 0}, /* DIVL2 */ +{3 +RB_L +IG_BASE, RL, RL, WL, 0, 0, 0}, /* DIVL3 */ +{2 +RB_L +IG_BASE, RL, ML, 0, 0, 0, 0}, /* BISL2 */ +{3 +RB_L +IG_BASE, RL, RL, WL, 0, 0, 0}, /* BISL3 */ +{2 +RB_L +IG_BASE, RL, ML, 0, 0, 0, 0}, /* BICL2 */ +{3 +RB_L +IG_BASE, RL, RL, WL, 0, 0, 0}, /* BICL3 */ +{2 +RB_L +IG_BASE, RL, ML, 0, 0, 0, 0}, /* XORL2 */ +{3 +RB_L +IG_BASE, RL, RL, WL, 0, 0, 0}, /* XORL3 */ +{2 +RB_L +IG_BASE, RL, WL, 0, 0, 0, 0}, /* MNEGL */ +{3 +IG_BASE, RL, RL, RL, 0, 0, 0}, /* CASEL */ +{2 +RB_L +IG_BASE, RL, WL, 0, 0, 0, 0}, /* MOVL */ /* 0D0-0DF */ +{2 +IG_BASE, RL, RL, 0, 0, 0, 0}, /* CMPL */ +{2 +RB_L +IG_BASE, RL, WL, 0, 0, 0, 0}, /* MCOML */ +{2 +IG_BASE, RL, RL, 0, 0, 0, 0}, /* BITL */ +{1 +RB_L +IG_BASE, WL, 0, 0, 0, 0, 0}, /* CLRL */ +{1 +IG_BASE, RL, 0, 0, 0, 0, 0}, /* TSTL */ +{1 +RB_L +IG_BASE, ML, 0, 0, 0, 0, 0}, /* INCL */ +{1 +RB_L +IG_BASE, ML, 0, 0, 0, 0, 0}, /* DECL */ +{2 +RB_L +IG_BASE, RL, ML, 0, 0, 0, 0}, /* ADWC */ +{2 +RB_L +IG_BASE, RL, ML, 0, 0, 0, 0}, /* SBWC */ +{2 +IG_BASE, RL, RL, 0, 0, 0, 0}, /* MTPR */ +{2 +RB_L +IG_BASE, RL, WL, 0, 0, 0, 0}, /* MFPR */ +{1 +RB_L +IG_BASE, WL, 0, 0, 0, 0, 0}, /* MOVPSL */ +{1 +RB_SP +IG_BASE, RL, 0, 0, 0, 0, 0}, /* PUSHL */ +{2 +RB_L +IG_BASE, AL, WL, 0, 0, 0, 0}, /* MOVAL */ +{1 +RB_SP +IG_BASE, AL, 0, 0, 0, 0, 0}, /* PUSHAL */ +{3 +IG_BASE, RL, VB, BB, 0, 0, 0}, /* BBS */ /* 0E0-0EF */ +{3 +IG_BASE, RL, VB, BB, 0, 0, 0}, /* BBC */ +{3 +IG_BASE, RL, VB, BB, 0, 0, 0}, /* BBSS */ +{3 +IG_BASE, RL, VB, BB, 0, 0, 0}, /* BBCS */ +{3 +IG_BASE, RL, VB, BB, 0, 0, 0}, /* BBSC */ +{3 +IG_BASE, RL, VB, BB, 0, 0, 0}, /* BBCC */ +{3 +IG_BASE, RL, VB, BB, 0, 0, 0}, /* BBSSI */ +{3 +IG_BASE, RL, VB, BB, 0, 0, 0}, /* BBCCI */ +{2 +IG_BASE, RL, BB, 0, 0, 0, 0}, /* BLBS */ +{2 +IG_BASE, RL, BB, 0, 0, 0, 0}, /* BLBC */ +{4 +RB_L +IG_BASE, RL, RB, VB, WL, 0, 0}, /* FFS */ +{4 +RB_L +IG_BASE, RL, RB, VB, WL, 0, 0}, /* FFC */ +{4 +IG_BASE, RL, RB, VB, RL, 0, 0}, /* CMPV */ +{4 +IG_BASE, RL, RB, VB, RL, 0, 0}, /* CMPZV */ +{4 +RB_L +IG_BASE, RL, RB, VB, WL, 0, 0}, /* EXTV */ +{4 +RB_L +IG_BASE, RL, RB, VB, WL, 0, 0}, /* EXTZV */ +{4 +IG_BASE, RL, RL, RB, VB, 0, 0}, /* INSV */ /* 0F0-0FF */ +{4 +IG_BASE, RL, RL, ML, BW, 0, 0}, /* ACBL */ +{3 +IG_BASE, RL, ML, BB, 0, 0, 0}, /* AOBLSS */ +{3 +IG_BASE, RL, ML, BB, 0, 0, 0}, /* AOBLEQ */ +{2 +IG_BASE, ML, BB, 0, 0, 0, 0}, /* SOBGEQ */ +{2 +IG_BASE, ML, BB, 0, 0, 0, 0}, /* SOBGTR */ +{2 +RB_B +IG_BASE, RL, WB, 0, 0, 0, 0}, /* CVTLB */ +{2 +RB_W +IG_BASE, RL, WW, 0, 0, 0, 0}, /* CVTLW */ +{6+DR_F+RB_R3 +IG_PACKD, RB, RW, AB, RB, RW, AB}, /* ASHP */ +{3+DR_F+RB_R3 +IG_PACKD, RL, RW, AB, 0, 0, 0}, /* CVTLP */ +{2 +IG_BASE, AB, AB, 0, 0, 0, 0}, /* CALLG */ +{2 +IG_BASE, RL, AB, 0, 0, 0, 0}, /* CALLS */ +{0 +IG_BASE, 0, 0, 0, 0, 0, 0}, /* XFC */ +{0, 0, 0, 0, 0, 0, 0}, /* 0FD */ +{0, 0, 0, 0, 0, 0, 0}, /* 0FE */ +{0, 0, 0, 0, 0, 0, 0}, /* 0FF */ +{0, 0, 0, 0, 0, 0, 0}, /* 100-10F */ +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, /* 110-11F */ +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, /* 120-12F */ +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, /* 130-13F */ +{0, 0, 0, 0, 0, 0, 0}, +{ODC(2) +RB_O +IG_EXTAC, RD, WO, 0, 0, 0, 0}, /* CVTDH */ +{2 +RB_L +IG_BSGFL, RG, WL, 0, 0, 0, 0}, /* CVTGF */ +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{2 +RB_Q +IG_BSGFL, RG, MQ, 0, 0, 0, 0}, /* ADDG2 */ /* 140-14F */ +{3 +RB_Q +IG_BSGFL, RG, RG, WQ, 0, 0, 0}, /* ADDG3 */ +{2 +RB_Q +IG_BSGFL, RG, MQ, 0, 0, 0, 0}, /* SUBG2 */ +{3 +RB_Q +IG_BSGFL, RG, RG, WQ, 0, 0, 0}, /* SUBG3 */ +{2 +RB_Q +IG_BSGFL, RG, MQ, 0, 0, 0, 0}, /* MULG2 */ +{3 +RB_Q +IG_BSGFL, RG, RG, WQ, 0, 0, 0}, /* MULG3 */ +{2 +RB_Q +IG_BSGFL, RG, MQ, 0, 0, 0, 0}, /* DIVG2 */ +{3 +RB_Q +IG_BSGFL, RG, RG, WQ, 0, 0, 0}, /* DIVG3 */ +{2 +RB_B +IG_BSGFL, RG, WB, 0, 0, 0, 0}, /* CVTGB */ +{2 +RB_W +IG_BSGFL, RG, WW, 0, 0, 0, 0}, /* CVTGW */ +{2 +RB_L +IG_BSGFL, RG, WL, 0, 0, 0, 0}, /* CVTGL */ +{2 +RB_L +IG_BSGFL, RG, WL, 0, 0, 0, 0}, /* CVTRGL */ +{2 +RB_Q +IG_BSGFL, RB, WQ, 0, 0, 0, 0}, /* CVTBG */ +{2 +RB_Q +IG_BSGFL, RW, WQ, 0, 0, 0, 0}, /* CVTWG */ +{2 +RB_Q +IG_BSGFL, RL, WQ, 0, 0, 0, 0}, /* CVTLG */ +{4 +IG_EMONL, RG, RG, MQ, BW, 0, 0}, /* ACBG */ +{2 +RB_Q +IG_BSGFL, RG, WQ, 0, 0, 0, 0}, /* MOVG */ /* 150-15F */ +{2 +IG_BSGFL, RG, RG, 0, 0, 0, 0}, /* CMPG */ +{2 +RB_Q +IG_BSGFL, RG, WQ, 0, 0, 0, 0}, /* MNEGG */ +{1 +IG_BSGFL, RG, 0, 0, 0, 0, 0}, /* TSTG */ +{5 +IG_EMONL, RG, RW, RG, WL, WQ, 0}, /* EMODG */ +{3 +RB_R5 +IG_EMONL, RG, RW, AB, 0, 0, 0}, /* POLYG */ +{ODC(2) +RB_O +IG_EXTAC, RG, WO, 0, 0, 0, 0}, /* CVTGH */ +{0 +IG_RSVD, 0, 0, 0, 0, 0, 0}, /* reserved */ +{0 +IG_RSVD, 0, 0, 0, 0, 0, 0}, /* reserved */ +{0 +IG_RSVD, 0, 0, 0, 0, 0, 0}, /* reserved */ +{0 +IG_RSVD, 0, 0, 0, 0, 0, 0}, /* reserved */ +{0 +IG_RSVD, 0, 0, 0, 0, 0, 0}, /* reserved */ +{0 +IG_RSVD, 0, 0, 0, 0, 0, 0}, /* reserved */ +{0 +IG_RSVD, 0, 0, 0, 0, 0, 0}, /* reserved */ +{0 +IG_RSVD, 0, 0, 0, 0, 0, 0}, /* reserved */ +{0 +IG_RSVD, 0, 0, 0, 0, 0, 0}, /* reserved */ +{ODC(2) +RB_O +IG_EXTAC, RH, MO, 0, 0, 0, 0}, /* ADDH2 */ /* 160-16F */ +{ODC(3) +RB_O +IG_EXTAC, RH, RH, WO, 0, 0, 0}, /* ADDH3 */ +{ODC(2) +RB_O +IG_EXTAC, RH, MO, 0, 0, 0, 0}, /* SUBH2 */ +{ODC(3) +RB_O +IG_EXTAC, RH, RH, WO, 0, 0, 0}, /* SUBH3 */ +{ODC(2) +RB_O +IG_EXTAC, RH, MO, 0, 0, 0, 0}, /* MULH2 */ +{ODC(3) +RB_O +IG_EXTAC, RH, RH, WO, 0, 0, 0}, /* MULH3 */ +{ODC(2) +RB_O +IG_EXTAC, RH, MO, 0, 0, 0, 0}, /* DIVH2 */ +{ODC(3) +RB_O +IG_EXTAC, RH, RH, WO, 0, 0, 0}, /* DIVH3 */ +{ODC(2) +RB_OB +IG_EXTAC, RH, WB, 0, 0, 0, 0}, /* CVTHB */ +{ODC(2) +RB_OW +IG_EXTAC, RH, WW, 0, 0, 0, 0}, /* CVTHW */ +{ODC(2) +RB_OL +IG_EXTAC, RH, WL, 0, 0, 0, 0}, /* CVTHL */ +{ODC(2) +RB_OL +IG_EXTAC, RH, WL, 0, 0, 0, 0}, /* CVTRHL */ +{ODC(2) +RB_O +IG_EXTAC, RB, WO, 0, 0, 0, 0}, /* CVTBH */ +{ODC(2) +RB_O +IG_EXTAC, RW, WO, 0, 0, 0, 0}, /* CVTWH */ +{ODC(2) +RB_O +IG_EXTAC, RL, WO, 0, 0, 0, 0}, /* CVTLH */ +{ODC(4) +RB_O +IG_EMONL, RH, RH, MO, BW, 0, 0}, /* ACBH */ +{ODC(2) +RB_O +IG_EXTAC, RH, RO, 0, 0, 0, 0}, /* MOVH */ /* 170-17F */ +{ODC(2) +IG_EXTAC, RH, RH, 0, 0, 0, 0}, /* CMPH */ +{ODC(2) +RB_O +IG_EXTAC, RH, WO, 0, 0, 0, 0}, /* MNEGH */ +{ODC(1) +IG_EXTAC, RH, 0, 0, 0, 0, 0}, /* TSTH */ +{ODC(5) +RB_O +IG_EMONL, RH, RW, RH, WL, WO, 0}, /* EMODH */ +{ODC(3) +RB_R5 +IG_EMONL, RH, RW, AB, 0, 0, 0}, /* POLYH */ +{ODC(2) +RB_OQ +IG_EXTAC, RH, WQ, 0, 0, 0, 0}, /* CVTHG */ +{0 +IG_RSVD, 0, 0, 0, 0, 0, 0}, /* reserved */ +{0 +IG_RSVD, 0, 0, 0, 0, 0, 0}, /* reserved */ +{0 +IG_RSVD, 0, 0, 0, 0, 0, 0}, /* reserved */ +{0 +IG_RSVD, 0, 0, 0, 0, 0, 0}, /* reserved */ +{0 +IG_RSVD, 0, 0, 0, 0, 0, 0}, /* reserved */ +#if defined(VAX_610) +{1 +RB_O +IG_EMONL, WO, 0, 0, 0, 0, 0}, /* CLRO */ +{2 +RB_O +IG_EMONL, RO, RO, 0, 0, 0, 0}, /* MOVO */ +{2 +RB_OL +IG_EMONL, AO, WL, 0, 0, 0, 0}, /* MOVAO*/ +{1 +RB_SP +IG_EMONL, AO, 0, 0, 0, 0, 0}, /* PUSHAO*/ +#else +{ODC(1) +RB_O +IG_EXTAC, WO, 0, 0, 0, 0, 0}, /* CLRO */ +{ODC(2) +RB_O +IG_EXTAC, RO, RO, 0, 0, 0, 0}, /* MOVO */ +{ODC(2) +RB_OL +IG_EXTAC, AO, WL, 0, 0, 0, 0}, /* MOVAO*/ +{ODC(1) +RB_SP +IG_EXTAC, AO, 0, 0, 0, 0, 0}, /* PUSHAO*/ +#endif +{0, 0, 0, 0, 0, 0, 0}, /* 180-18F */ +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, /* 190-19F */ +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{ODC(2) +RB_O +IG_EXTAC, RF, WO, 0, 0, 0, 0}, /* CVTFH */ +{2 +RB_Q +IG_BSGFL, RF, WQ, 0, 0, 0, 0}, /* CVTFG */ +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, /* 1A0-1AF */ +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, /* 1B0-1BF */ +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, /* 1C0-1CF */ +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, /* 1D0-1DF */ +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, /* 1E0-1EF */ +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, /* 1F0-1FF */ +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{ODC(2) +RB_OL +IG_EXTAC, RH, WL, 0, 0, 0, 0}, /* CVTHF */ +{ODC(2) +RB_OQ +IG_EXTAC, RH, WQ, 0, 0, 0, 0}, /* CVTHD */ +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0}, +{0, 0, 0, 0, 0, 0, 0} }; /* Opcode mnemonics table */ -const char *opcode[] = { +char const * const opcode[] = { "HALT", "NOP", "REI", "BPT", "RET", "RSB", "LDPCTX", "SVPCTX", "CVTPS", "CVTSP", "INDEX", "CRC", "PROBER", "PROBEW", "INSQUE", "REMQUE", "BSBB", "BRB", "BNEQ", "BEQL", "BGTR", "BLEQ", "JSB", "JMP", diff --git a/VAX/vax_syscm.c b/VAX/vax_syscm.c index fda851d7..373a1ebb 100644 --- a/VAX/vax_syscm.c +++ b/VAX/vax_syscm.c @@ -72,7 +72,7 @@ static const int32 masks[] = { 0177000 }; -static const char *opcode[] = { +static const char *cm_opcode[] = { "HALT","WAIT","RTI","BPT", "IOT","RESET","RTT","MFPT", "JMP","RTS","SPL", @@ -303,55 +303,55 @@ for (i = 0; opc_val[i] >= 0; i++) { /* loop thru ops */ switch (j) { /* case on class */ case I_V_NPN: case I_V_CCC: case I_V_CCS: /* no operands */ - fprintf (of, "%s", opcode[i]); + fprintf (of, "%s", cm_opcode[i]); break; case I_V_REG: /* reg */ - fprintf (of, "%s %-s", opcode[i], rname[dstr]); + fprintf (of, "%s %-s", cm_opcode[i], rname[dstr]); break; case I_V_SOP: /* sop */ - fprintf (of, "%s ", opcode[i]); + fprintf (of, "%s ", cm_opcode[i]); wd1 = fprint_spec (of, addr, dstm, val[1]); break; case I_V_3B: /* 3b */ - fprintf (of, "%s %-X", opcode[i], dstr); + fprintf (of, "%s %-X", cm_opcode[i], dstr); break; case I_V_6B: /* 6b */ - fprintf (of, "%s %-X", opcode[i], dstm); + fprintf (of, "%s %-X", cm_opcode[i], dstm); break; case I_V_BR: /* cond branch */ - fprintf (of, "%s ", opcode[i]); + fprintf (of, "%s ", cm_opcode[i]); brdisp = (l8b + l8b + ((l8b & 0200)? 0177002: 2)) & 0177777; fprintf (of, "%-X", (int32)((addr + brdisp) & 0177777)); break; case I_V_8B: /* 8b */ - fprintf (of, "%s %-X", opcode[i], l8b); + fprintf (of, "%s %-X", cm_opcode[i], l8b); break; case I_V_SOB: /* sob */ - fprintf (of, "%s %s,", opcode[i], rname[srcr]); + fprintf (of, "%s %s,", cm_opcode[i], rname[srcr]); brdisp = (dstm * 2) - 2; fprintf (of, "%-X", (int32)((addr - brdisp) & 0177777)); break; case I_V_RSOP: /* rsop */ - fprintf (of, "%s %s,", opcode[i], rname[srcr]); + fprintf (of, "%s %s,", cm_opcode[i], rname[srcr]); wd1 = fprint_spec (of, addr, dstm, val[1]); break; case I_V_SOPR: /* sopr */ - fprintf (of, "%s ", opcode[i]); + fprintf (of, "%s ", cm_opcode[i]); wd1 = fprint_spec (of, addr, dstm, val[1]); fprintf (of, ",%s", rname[srcr]); break; case I_V_DOP: /* dop */ - fprintf (of, "%s ", opcode[i]); + fprintf (of, "%s ", cm_opcode[i]); wd1 = fprint_spec (of, addr, srcm, val[1]); fprintf (of, ","); wd1 += fprint_spec (of, addr - wd1 - wd1, dstm, @@ -575,8 +575,8 @@ if (!(sw & SWMASK ('P')) || (ad32 & 1) || (ad32 > WMASK)) cptr = get_glyph (cptr, gbuf, 0); /* get opcode */ n1 = n2 = pflag = 0; -for (i = 0; (opcode[i] != NULL) && (strcmp (opcode[i], gbuf) != 0) ; i++) ; -if (opcode[i] == NULL) +for (i = 0; (cm_opcode[i] != NULL) && (strcmp (cm_opcode[i], gbuf) != 0) ; i++) ; +if (cm_opcode[i] == NULL) return SCPE_ARG; val[0] = opc_val[i] & 0177777; /* get value */ j = (opc_val[i] >> I_V_CL) & I_M_CL; /* get class */ @@ -666,10 +666,10 @@ switch (j) { /* case on class */ case I_V_CCC: case I_V_CCS: /* cond code oper */ for (cptr = get_glyph (cptr, gbuf, 0); gbuf[0] != 0; cptr = get_glyph (cptr, gbuf, 0)) { - for (i = 0; (opcode[i] != NULL) && - (strcmp (opcode[i], gbuf) != 0) ; i++) ; + for (i = 0; (cm_opcode[i] != NULL) && + (strcmp (cm_opcode[i], gbuf) != 0) ; i++) ; if ((((opc_val[i] >> I_V_CL) & I_M_CL) != j) || - (opcode[i] == NULL)) + (cm_opcode[i] == NULL)) return SCPE_ARG; val[0] = val[0] | (opc_val[i] & 0177777); } diff --git a/VAX/vax_sysdev.c b/VAX/vax_sysdev.c index 1d8bbfe1..e02c2c47 100644 --- a/VAX/vax_sysdev.c +++ b/VAX/vax_sysdev.c @@ -979,7 +979,7 @@ switch (rg) { case MT_SID: case MT_CONPC: case MT_CONPSL: /* halt reg */ - RSVD_OPND_FAULT; + RSVD_OPND_FAULT(WriteIPR); default: ssc_bto = ssc_bto | SSCBTO_BTO; /* set BTO */ diff --git a/VAX/vaxmod_defs.h b/VAX/vaxmod_defs.h index d21c2ad5..158a0353 100644 --- a/VAX/vaxmod_defs.h +++ b/VAX/vaxmod_defs.h @@ -138,7 +138,7 @@ extern t_stat cpu_show_memory (FILE* st, UNIT* uptr, int32 val, CONST void* desc { MTAB_XTD|MTAB_VDV, 0, "AUTOBOOT", "AUTOBOOT", \ &sysd_set_halt, &sysd_show_halt, NULL, "Enable autoboot (Disable Halt)" }, \ { MTAB_XTD|MTAB_VDV|MTAB_NMO, 1, "NOAUTOBOOT", "NOAUTOBOOT", \ - &sysd_set_halt, &sysd_show_halt, NULL, "Disable autoboot (Enable Halt)" } + &sysd_set_halt, &sysd_show_halt, NULL, "Disable autoboot (Enable Halt)" }, /* Cache diagnostic space */ @@ -247,7 +247,7 @@ extern t_stat cpu_show_memory (FILE* st, UNIT* uptr, int32 val, CONST void* desc #define LP_MBZ84_TEST(r) #define LP_MBZ92_TEST(r) -#define MT_AST_TEST(r) if ((r) > AST_MAX) RSVD_OPND_FAULT +#define MT_AST_TEST(r) if ((r) > AST_MAX) RSVD_OPND_FAULT(MT_AST_TEST) /* Qbus I/O modes */