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Remove stray tab characters which crept in over time

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This commit is contained in:
Mark Pizzolato 2013-06-03 06:29:01 -07:00
parent f7330bc09d
commit 651780c481
46 changed files with 928 additions and 928 deletions
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2
PDP10/pdp10_mdfp.c
View file

@ -803,7 +803,7 @@ if (r->sign) { /* negate? */
if (fdvneg) { /* fdvr special? */ if (fdvneg) { /* fdvr special? */
val[1] = ~val[1] & MMASK; /* 1's comp */ val[1] = ~val[1] & MMASK; /* 1's comp */
val[0] = ~val[0] & DMASK; val[0] = ~val[0] & DMASK;
} }
else { /* 2's comp */ else { /* 2's comp */
DMOVN (val); DMOVN (val);
} }

2
PDP10/pdp10_tim.c
View file

@ -200,7 +200,7 @@ tim_ttg = tim_period; /* reload */
apr_flg = apr_flg | APRF_TIM; /* request interrupt */ apr_flg = apr_flg | APRF_TIM; /* request interrupt */
if (Q_ITS) { /* ITS? */ if (Q_ITS) { /* ITS? */
if (pi_act == 0) if (pi_act == 0)
quant = (quant + TIM_ITS_QUANT) & DMASK; quant = (quant + TIM_ITS_QUANT) & DMASK;
if (TSTS (pcst)) { /* PC sampling? */ if (TSTS (pcst)) { /* PC sampling? */
WriteP ((a10) pcst & AMASK, pager_PC); /* store sample */ WriteP ((a10) pcst & AMASK, pager_PC); /* store sample */
pcst = AOB (pcst); /* add 1,,1 */ pcst = AOB (pcst); /* add 1,,1 */

1210
PDP11/pdp11_cr_dat.h
View file

File diff suppressed because it is too large Load diff

2
PDP11/pdp11_dc.c
View file

@ -278,7 +278,7 @@ if (ln > DCX_MAXMUX) /* validate line number
switch ((PA >> 1) & 03) { /* decode PA<2:1> */ switch ((PA >> 1) & 03) { /* decode PA<2:1> */
case 00: /* dci csr */ case 00: /* dci csr */
if (dci_csr[ln] & DCICSR_ALLERR) if (dci_csr[ln] & DCICSR_ALLERR)
dci_csr[ln] |= DCICSR_ERR; dci_csr[ln] |= DCICSR_ERR;
else dci_csr[ln] &= ~DCICSR_ERR; else dci_csr[ln] &= ~DCICSR_ERR;
*data = dci_csr[ln] & DCICSR_RD; *data = dci_csr[ln] & DCICSR_RD;

2
PDP11/pdp11_dmc.c
View file

@ -906,7 +906,7 @@ t_stat dmc_help_attach (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cp
fprintf (st, "The communication line performs input and output through a TCP session\n"); fprintf (st, "The communication line performs input and output through a TCP session\n");
fprintf (st, "connected to a user-specified port. The ATTACH command specifies the"); fprintf (st, "connected to a user-specified port. The ATTACH command specifies the");
fprintf (st, "port to be used:\n\n"); fprintf (st, "port to be used:\n\n");
fprintf (st, " sim> ATTACH %s {interface:}port set up listening port\n\n", dptr->name); fprintf (st, " sim> ATTACH %s {interface:}port set up listening port\n\n", dptr->name);
fprintf (st, "where port is a decimal number between 1 and 65535 that is not being used for\n"); fprintf (st, "where port is a decimal number between 1 and 65535 that is not being used for\n");
fprintf (st, "other TCP/IP activities. An ATTACH is required even if in PRIMARY mode. \n\n"); fprintf (st, "other TCP/IP activities. An ATTACH is required even if in PRIMARY mode. \n\n");
return SCPE_OK; return SCPE_OK;

22
PDP11/pdp11_dz.c
View file

@ -897,15 +897,15 @@ fprintf (st, "%s Terminal Multiplexer (DZ)\n\n", devtype);
fprintf (st, "The %s is a %d line terminal multiplexor. Up to %d %s's (%d lines) are\n", devtype, DZ_LINES, MAX_DZ_MUXES, devtype, DZ_LINES*MAX_DZ_MUXES); fprintf (st, "The %s is a %d line terminal multiplexor. Up to %d %s's (%d lines) are\n", devtype, DZ_LINES, MAX_DZ_MUXES, devtype, DZ_LINES*MAX_DZ_MUXES);
fprintf (st, "supported. The default number of lines is %d. The number of lines can\n", DZ_LINES*DZ_MUXES); fprintf (st, "supported. The default number of lines is %d. The number of lines can\n", DZ_LINES*DZ_MUXES);
fprintf (st, "be changed with the command\n\n"); fprintf (st, "be changed with the command\n\n");
fprintf (st, " sim> SET %s LINES=n set line count to n\n\n", dptr->name); fprintf (st, " sim> SET %s LINES=n set line count to n\n\n", dptr->name);
fprintf (st, "The line count must be a multiple of %d, with a maximum of %d.\n\n", DZ_LINES, DZ_LINES*MAX_DZ_MUXES); fprintf (st, "The line count must be a multiple of %d, with a maximum of %d.\n\n", DZ_LINES, DZ_LINES*MAX_DZ_MUXES);
fprintf (st, "The %s supports three character processing modes, 7P, 7B, and 8B:\n\n", devtype); fprintf (st, "The %s supports three character processing modes, 7P, 7B, and 8B:\n\n", devtype);
fprintf (st, " mode input characters output characters\n"); fprintf (st, " mode input characters output characters\n");
fprintf (st, " =============================================\n"); fprintf (st, " =============================================\n");
fprintf (st, " 7P high-order bit cleared high-order bit cleared,\n"); fprintf (st, " 7P high-order bit cleared high-order bit cleared,\n");
fprintf (st, " non-printing characters suppressed\n"); fprintf (st, " non-printing characters suppressed\n");
fprintf (st, " 7B high-order bit cleared high-order bit cleared\n"); fprintf (st, " 7B high-order bit cleared high-order bit cleared\n");
fprintf (st, " 8B no changes no changes\n\n"); fprintf (st, " 8B no changes no changes\n\n");
fprintf (st, "The default is 8B.\n\n"); fprintf (st, "The default is 8B.\n\n");
fprintf (st, "The %s supports logging on a per-line basis. The command\n\n", devtype); fprintf (st, "The %s supports logging on a per-line basis. The command\n\n", devtype);
fprintf (st, " sim> SET %s LOG=n=filename\n\n", dptr->name); fprintf (st, " sim> SET %s LOG=n=filename\n\n", dptr->name);
@ -921,9 +921,9 @@ fprintf (st, "are Telnet connections. The connection remains open until disconn
fprintf (st, "simulated program, the Telnet client, a SET %s DISCONNECT command, or a\n", dptr->name); fprintf (st, "simulated program, the Telnet client, a SET %s DISCONNECT command, or a\n", dptr->name);
fprintf (st, "DETACH %s command.\n\n", dptr->name); fprintf (st, "DETACH %s command.\n\n", dptr->name);
fprintf (st, "Other special %s commands:\n\n", dptr->name); fprintf (st, "Other special %s commands:\n\n", dptr->name);
fprintf (st, " sim> SHOW %s CONNECTIONS show current connections\n", dptr->name); fprintf (st, " sim> SHOW %s CONNECTIONS show current connections\n", dptr->name);
fprintf (st, " sim> SHOW %s STATISTICS show statistics for active connections\n", dptr->name); fprintf (st, " sim> SHOW %s STATISTICS show statistics for active connections\n", dptr->name);
fprintf (st, " sim> SET %s DISCONNECT=linenumber disconnects the specified line.\n\n\n", dptr->name); fprintf (st, " sim> SET %s DISCONNECT=linenumber disconnects the specified line.\n\n\n", dptr->name);
fprintf (st, "All open connections are lost when the simulator shuts down or the %s is\n", dptr->name); fprintf (st, "All open connections are lost when the simulator shuts down or the %s is\n", dptr->name);
fprintf (st, "detached.\n\n"); fprintf (st, "detached.\n\n");
dz_help_attach (st, dptr, uptr, flag, cptr); dz_help_attach (st, dptr, uptr, flag, cptr);
@ -937,7 +937,7 @@ char *devtype = (UNIBUS) ? "DZ11" : "DZV11";
tmxr_attach_help (st, dptr, uptr, flag, cptr); tmxr_attach_help (st, dptr, uptr, flag, cptr);
fprintf (st, "The terminal lines perform input and output through Telnet sessions connected\n"); fprintf (st, "The terminal lines perform input and output through Telnet sessions connected\n");
fprintf (st, "to a user-specified port. The ATTACH command specifies the port to be used:\n\n"); fprintf (st, "to a user-specified port. The ATTACH command specifies the port to be used:\n\n");
fprintf (st, " sim> ATTACH {-am} %s {interface:}port set up listening port\n\n", dptr->name); fprintf (st, " sim> ATTACH {-am} %s {interface:}port set up listening port\n\n", dptr->name);
fprintf (st, "where port is a decimal number between 1 and 65535 that is not being used for\n"); fprintf (st, "where port is a decimal number between 1 and 65535 that is not being used for\n");
fprintf (st, "other TCP/IP activities. The optional switch -m turns on the %s's modem\n", devtype); fprintf (st, "other TCP/IP activities. The optional switch -m turns on the %s's modem\n", devtype);
fprintf (st, "controls; the optional switch -a turns on active disconnects (disconnect\n"); fprintf (st, "controls; the optional switch -a turns on active disconnects (disconnect\n");

4
PDP11/pdp11_fp.c
View file

@ -745,7 +745,7 @@ if (IR & 000740) { /* defined? */
if (CPUT (CPUT_03)) /* 11/03 reads word */ if (CPUT (CPUT_03)) /* 11/03 reads word */
ReadW (exta | R[reg]); ReadW (exta | R[reg]);
ABORT (TRAP_ILL); ABORT (TRAP_ILL);
} }
FEC = 0; /* no errors */ FEC = 0; /* no errors */
FPS = FPS_IU|FPS_IV; /* trap ovf,unf */ FPS = FPS_IU|FPS_IV; /* trap ovf,unf */
@ -782,7 +782,7 @@ switch ((IR >> 3) & 3) { /* case IR<5:3> */
V = N = C = 1; /* set cc's */ V = N = C = 1; /* set cc's */
setTRAP (TRAP_FPE); /* set trap */ setTRAP (TRAP_FPE); /* set trap */
return SCPE_OK; return SCPE_OK;
} }
else divfp11 (&fac, &fsrc); else divfp11 (&fac, &fsrc);
break; break;
} }

8
PDP11/pdp11_hk.c
View file

@ -214,7 +214,7 @@ BITFIELD hk_da_bits[] = {
#define CS2_MBZ (CS2_CLR) #define CS2_MBZ (CS2_CLR)
#define CS2_RW 0000037 #define CS2_RW 0000037
#define CS2_ERR (CS2_UFE | CS2_MDS | CS2_PGE | CS2_NEM | \ #define CS2_ERR (CS2_UFE | CS2_MDS | CS2_PGE | CS2_NEM | \
CS2_NED | CS2_PE | CS2_WCE | CS2_DLT ) CS2_NED | CS2_PE | CS2_WCE | CS2_DLT )
#define GET_UNIT(x) (((x) >> CS2_V_UNIT) & CS2_M_UNIT) #define GET_UNIT(x) (((x) >> CS2_V_UNIT) & CS2_M_UNIT)
BITFIELD hk_cs2_bits[] = { BITFIELD hk_cs2_bits[] = {
@ -959,9 +959,9 @@ if (fnc_cyl[fnc] && /* need valid cyl */
((GET_CY (hkdc) >= HK_CYL (uptr)) || /* bad cylinder */ ((GET_CY (hkdc) >= HK_CYL (uptr)) || /* bad cylinder */
(GET_SF (hkda) >= HK_NUMSF) || /* bad surface */ (GET_SF (hkda) >= HK_NUMSF) || /* bad surface */
(GET_SC (hkda) >= HK_NUMSC))) { /* or bad sector? */ (GET_SC (hkda) >= HK_NUMSC))) { /* or bad sector? */
hk_cmderr (ER_IAE, drv); /* illegal addr */ hk_cmderr (ER_IAE, drv); /* illegal addr */
return; return;
} }
hkcs1 = (hkcs1 | CS1_GO) & ~CS1_DONE; /* set go, clear done */ hkcs1 = (hkcs1 | CS1_GO) & ~CS1_DONE; /* set go, clear done */
switch (fnc) { /* case on function */ switch (fnc) { /* case on function */

20
PDP11/pdp11_ke.c
View file

@ -38,13 +38,13 @@
/* KE11A I/O address offsets 0177300 - 0177316 */ /* KE11A I/O address offsets 0177300 - 0177316 */
#define KE_DIV 000 /* divide */ #define KE_DIV 000 /* divide */
#define KE_AC 002 /* accumulator */ #define KE_AC 002 /* accumulator */
#define KE_MQ 004 /* MQ */ #define KE_MQ 004 /* MQ */
#define KE_MUL 006 /* multiply */ #define KE_MUL 006 /* multiply */
#define KE_SC 010 /* step counter */ #define KE_SC 010 /* step counter */
#define KE_NOR 012 /* normalize */ #define KE_NOR 012 /* normalize */
#define KE_LSH 014 /* logical shift */ #define KE_LSH 014 /* logical shift */
#define KE_ASH 016 /* arithmetic shift */ #define KE_ASH 016 /* arithmetic shift */
/* Status register */ /* Status register */
@ -76,7 +76,7 @@ uint32 ke_set_SR (void);
DIB ke_dib = { IOBA_AUTO, IOLN_KE, &ke_rd, &ke_wr, 0 }; DIB ke_dib = { IOBA_AUTO, IOLN_KE, &ke_rd, &ke_wr, 0 };
UNIT ke_unit = { UNIT ke_unit = {
UDATA (NULL, UNIT_DISABLE, 0) UDATA (NULL, UNIT_DISABLE, 0)
}; };
REG ke_reg[] = { REG ke_reg[] = {
@ -237,9 +237,9 @@ switch (PA & 017) { /* decode PA<3:0> */
case KE_NOR: /* normalize */ case KE_NOR: /* normalize */
for (ke_SC = 0; ke_SC < 31; ke_SC++) { /* max 31 shifts */ for (ke_SC = 0; ke_SC < 31; ke_SC++) { /* max 31 shifts */
if (((ke_AC == 0140000) && (ke_MQ == 0)) || /* special case? */ if (((ke_AC == 0140000) && (ke_MQ == 0)) || /* special case? */
(GET_SIGN_W (ke_AC ^ (ke_AC << 1)))) /* AC<15> != AC<14>? */ (GET_SIGN_W (ke_AC ^ (ke_AC << 1)))) /* AC<15> != AC<14>? */
break; break;
ke_AC = ((ke_AC << 1) | (ke_MQ >> 15)) & DMASK; ke_AC = ((ke_AC << 1) | (ke_MQ >> 15)) & DMASK;
ke_MQ = (ke_MQ << 1) & DMASK; ke_MQ = (ke_MQ << 1) & DMASK;
} }

2
PDP11/pdp11_rf.c
View file

@ -366,7 +366,7 @@ do {
update_rfcs (0, RFDAE_NXM); update_rfcs (0, RFDAE_NXM);
break; break;
} }
fbuf[da] = dat; /* write word */ fbuf[da] = dat; /* write word */
rf_dbr = dat; rf_dbr = dat;
if (da >= uptr->hwmark) if (da >= uptr->hwmark)
uptr->hwmark = da + 1; uptr->hwmark = da + 1;

8
PDP11/pdp11_rk.c
View file

@ -430,9 +430,9 @@ if (((uptr->flags & UNIT_ATT) == 0) || /* not att or busy? */
} }
if ((rkcs & RKCS_FMT) && /* format and */ if ((rkcs & RKCS_FMT) && /* format and */
(func != RKCS_READ) && (func != RKCS_WRITE)) { /* not read or write? */ (func != RKCS_READ) && (func != RKCS_WRITE)) { /* not read or write? */
rk_set_done (RKER_PGE); rk_set_done (RKER_PGE);
return; return;
} }
if ((func == RKCS_WRITE) && /* write and locked? */ if ((func == RKCS_WRITE) && /* write and locked? */
(uptr->flags & UNIT_WPRT)) { (uptr->flags & UNIT_WPRT)) {
rk_set_done (RKER_WLK); rk_set_done (RKER_WLK);
@ -650,7 +650,7 @@ if (error != 0) {
rkcs = rkcs | RKCS_ERR; rkcs = rkcs | RKCS_ERR;
if (rker & RKER_HARD) if (rker & RKER_HARD)
rkcs = rkcs | RKCS_HERR; rkcs = rkcs | RKCS_HERR;
} }
if (rkcs & CSR_IE) { /* int enable? */ if (rkcs & CSR_IE) { /* int enable? */
rkintq = rkintq | RK_CTLI; /* set ctrl int */ rkintq = rkintq | RK_CTLI; /* set ctrl int */
SET_INT (RK); /* request int */ SET_INT (RK); /* request int */

22
PDP11/pdp11_rl.c
View file

@ -175,7 +175,7 @@ extern UNIT cpu_unit;
#define RLCS_WRITE (5) #define RLCS_WRITE (5)
#define RLCS_READ (6) #define RLCS_READ (6)
#define RLCS_RNOHDR (7) #define RLCS_RNOHDR (7)
#define RLCS_SPECIAL (8) /* internal function, drive state */ #define RLCS_SPECIAL (8) /* internal function, drive state */
#define RLCS_V_FUNC (1) #define RLCS_V_FUNC (1)
#define RLCS_M_MEX (03) /* memory extension */ #define RLCS_M_MEX (03) /* memory extension */
#define RLCS_V_MEX (4) #define RLCS_V_MEX (4)
@ -381,11 +381,11 @@ static const char * const state[] = {
/* I/O dispatch routines, I/O addresses 17774400 - 17774411 /* I/O dispatch routines, I/O addresses 17774400 - 17774411
17774400 RLCS read/write 17774400 RLCS read/write
17774402 RLBA read/write 17774402 RLBA read/write
17774404 RLDA read/write 17774404 RLDA read/write
17774406 RLMP read/write 17774406 RLMP read/write
17774410 RLBAE read/write 17774410 RLBAE read/write
*/ */
t_stat rl_rd (int32 *data, int32 PA, int32 access) t_stat rl_rd (int32 *data, int32 PA, int32 access)
@ -395,7 +395,7 @@ UNIT *uptr;
switch ((PA >> 1) & 07) { /* decode PA<2:1> */ switch ((PA >> 1) & 07) { /* decode PA<2:1> */
case 0: /* RLCS */ case 0: /* RLCS */
rlcs = (rlcs & ~RLCS_MEX) | ((rlbae & RLCS_M_MEX) << RLCS_V_MEX); rlcs = (rlcs & ~RLCS_MEX) | ((rlbae & RLCS_M_MEX) << RLCS_V_MEX);
/* /*
The DRDY signal is sent by the selected drive to indicate that it The DRDY signal is sent by the selected drive to indicate that it
is ready to read or write or seek. It is sent when the heads are is ready to read or write or seek. It is sent when the heads are
@ -513,7 +513,7 @@ bit is cleared by software. If set, check for interrupts and return.
if (newc != curr) if (newc != curr)
uptr->STAT = (uptr->STAT & ~RLDS_M_STATE) | RLDS_SEEK; /* move the positioner */ uptr->STAT = (uptr->STAT & ~RLDS_M_STATE) | RLDS_SEEK; /* move the positioner */
/* TBD: if a head switch, sector should be RL_NUMSC/2? */ /* TBD: if a head switch, sector should be RL_NUMSC/2? */
uptr->TRK = (newc << RLDA_V_CYL) | /* put on track */ uptr->TRK = (newc << RLDA_V_CYL) | /* put on track */
((rlda & RLDA_SK_HD)? RLDA_HD1: RLDA_HD0); ((rlda & RLDA_SK_HD)? RLDA_HD1: RLDA_HD0);
/* /*
Real timing: Real timing:
@ -782,7 +782,7 @@ was removed in a later ECO.
uptr->STAT = (uptr->STAT & ~RLDS_M_STATE) | RLDS_BRUSH; uptr->STAT = (uptr->STAT & ~RLDS_M_STATE) | RLDS_BRUSH;
} else { } else {
uptr->STAT |= RLDS_BHO; uptr->STAT |= RLDS_BHO;
uptr->STAT = (uptr->STAT & ~RLDS_M_STATE) | RLDS_HLOAD; uptr->STAT = (uptr->STAT & ~RLDS_M_STATE) | RLDS_HLOAD;
} }
sim_activate (uptr, 200 * rl_swait); sim_activate (uptr, 200 * rl_swait);
break; break;
@ -810,7 +810,7 @@ Initiated by depressing the Run (LOAD) switch.
*/ */
case RLDS_UNL: /* unload pressed, heads unloaded, spin down */ case RLDS_UNL: /* unload pressed, heads unloaded, spin down */
uptr->STAT = (uptr->STAT & ~RLDS_M_STATE) | RLDS_DOWN; uptr->STAT = (uptr->STAT & ~RLDS_M_STATE) | RLDS_DOWN;
uptr->STAT &= ~RLDS_HDO; /* retract heads */ uptr->STAT &= ~RLDS_HDO; /* retract heads */
/* actual time is ~30 seconds */ /* actual time is ~30 seconds */
sim_activate (uptr, 200 * rl_swait); sim_activate (uptr, 200 * rl_swait);
break; break;
@ -866,7 +866,7 @@ if (uptr->FNC == RLCS_RNOHDR) {
} else { } else {
/* bad cyl or sector? */ /* bad cyl or sector? */
if (((uptr->TRK & RLDA_CYL) != (rlda & RLDA_CYL)) || (GET_SECT (rlda) >= RL_NUMSC)) { if (((uptr->TRK & RLDA_CYL) != (rlda & RLDA_CYL)) || (GET_SECT (rlda) >= RL_NUMSC)) {
rl_set_done (RLCS_ERR | RLCS_HDE | RLCS_INCMP); /* wrong cylinder? */ rl_set_done (RLCS_ERR | RLCS_HDE | RLCS_INCMP); /* wrong cylinder? */
return (SCPE_OK); return (SCPE_OK);
} }
da = GET_DA (rlda) * RL_NUMWD; /* get disk addr */ da = GET_DA (rlda) * RL_NUMWD; /* get disk addr */

2
PDP11/pdp11_rp.c
View file

@ -31,7 +31,7 @@
to boot. to boot.
17-May-07 RMS CS1 DVA resides in device, not MBA 17-May-07 RMS CS1 DVA resides in device, not MBA
21-Nov-05 RMS Enable/disable device also enables/disables Massbus adapter 21-Nov-05 RMS Enable/disable device also enables/disables Massbus adapter
12-Nov-05 RMS Fixed DriveClear, does not clear disk address 12-Nov-05 RMS Fixed DriveClear, does not clear disk address
16-Aug-05 RMS Fixed C++ declaration and cast problems 16-Aug-05 RMS Fixed C++ declaration and cast problems
18-Mar-05 RMS Added attached test to detach routine 18-Mar-05 RMS Added attached test to detach routine
12-Sep-04 RMS Cloned from pdp11_rp.c 12-Sep-04 RMS Cloned from pdp11_rp.c

10
PDP11/pdp11_rq.c
View file

@ -1448,7 +1448,7 @@ if (cp->csta < CST_UP) { /* still init? */
if ((cp->saw & SA_S4H_LF) if ((cp->saw & SA_S4H_LF)
&& cp->perr) rq_plf (cp, cp->perr); && cp->perr) rq_plf (cp, cp->perr);
cp->perr = 0; cp->perr = 0;
} }
break; break;
} /* end switch */ } /* end switch */
@ -1675,9 +1675,9 @@ if ((uptr = rq_getucb (cp, lu)) && /* valid lu? */
(tpkt = uptr->cpkt) && /* queued pkt? */ (tpkt = uptr->cpkt) && /* queued pkt? */
(GETP32 (tpkt, CMD_REFL) == ref) && /* match ref? */ (GETP32 (tpkt, CMD_REFL) == ref) && /* match ref? */
(GETP (tpkt, CMD_OPC, OPC) >= OP_ACC)) { /* rd/wr cmd? */ (GETP (tpkt, CMD_OPC, OPC) >= OP_ACC)) { /* rd/wr cmd? */
cp->pak[pkt].d[GCS_STSL] = cp->pak[tpkt].d[RW_WBCL]; cp->pak[pkt].d[GCS_STSL] = cp->pak[tpkt].d[RW_WBCL];
cp->pak[pkt].d[GCS_STSH] = cp->pak[tpkt].d[RW_WBCH]; cp->pak[pkt].d[GCS_STSH] = cp->pak[tpkt].d[RW_WBCH];
} }
else { else {
cp->pak[pkt].d[GCS_STSL] = 0; /* return 0 */ cp->pak[pkt].d[GCS_STSL] = 0; /* return 0 */
cp->pak[pkt].d[GCS_STSH] = 0; cp->pak[pkt].d[GCS_STSH] = 0;
@ -3094,7 +3094,7 @@ fprintf (st, "ability to set units write enabled or write locked, and to set the
fprintf (st, "type to one of many disk types:\n"); fprintf (st, "type to one of many disk types:\n");
fprint_set_help (st, dptr); fprint_set_help (st, dptr);
fprintf (st, "set RQn RAUSER{=n} Set disk type to RA82 with n MB's\n"); fprintf (st, "set RQn RAUSER{=n} Set disk type to RA82 with n MB's\n");
fprintf (st, "set -L RQn RAUSER{=n} Set disk type to RA82 with n LBN's\n\n"); fprintf (st, "set -L RQn RAUSER{=n} Set disk type to RA82 with n LBN's\n\n");
fprintf (st, "The type options can be used only when a unit is not attached to a file.\n"); fprintf (st, "The type options can be used only when a unit is not attached to a file.\n");
fprintf (st, "RAUSER is a \"user specified\" disk; the user can specify the size of the\n"); fprintf (st, "RAUSER is a \"user specified\" disk; the user can specify the size of the\n");
fprintf (st, "disk in either MB (1000000 bytes) or logical block numbers (LBN's, 512 bytes\n"); fprintf (st, "disk in either MB (1000000 bytes) or logical block numbers (LBN's, 512 bytes\n");

88
PDP11/pdp11_ry.c
View file

@ -185,9 +185,9 @@ DIB ry_dib = {
UNIT ry_unit[] = { UNIT ry_unit[] = {
{ UDATA (&ry_svc, UNIT_DEN+UNIT_FIX+UNIT_ATTABLE+UNIT_BUFABLE+UNIT_MUSTBUF, { UDATA (&ry_svc, UNIT_DEN+UNIT_FIX+UNIT_ATTABLE+UNIT_BUFABLE+UNIT_MUSTBUF,
RY_SIZE) }, RY_SIZE) },
{ UDATA (&ry_svc, UNIT_DEN+UNIT_FIX+UNIT_ATTABLE+UNIT_BUFABLE+UNIT_MUSTBUF, { UDATA (&ry_svc, UNIT_DEN+UNIT_FIX+UNIT_ATTABLE+UNIT_BUFABLE+UNIT_MUSTBUF,
RY_SIZE) } RY_SIZE) }
}; };
REG ry_reg[] = { REG ry_reg[] = {
@ -485,59 +485,59 @@ switch (ry_state) { /* case on state */
sim_activate (uptr, ry_cwait * 100); /* schedule operation */ sim_activate (uptr, ry_cwait * 100); /* schedule operation */
break; break;
case SDXFR: /* erase disk */ case SDXFR: /* erase disk */
for (i = 0; i < (int32) uptr->capac; i++) for (i = 0; i < (int32) uptr->capac; i++)
fbuf[i] = 0; fbuf[i] = 0;
uptr->hwmark = (uint32) uptr->capac; uptr->hwmark = (uint32) uptr->capac;
if (ry_csr & RYCS_DEN) if (ry_csr & RYCS_DEN)
uptr->flags = uptr->flags | UNIT_DEN; uptr->flags = uptr->flags | UNIT_DEN;
else uptr->flags = uptr->flags & ~UNIT_DEN; else uptr->flags = uptr->flags & ~UNIT_DEN;
ry_done (0, 0); ry_done (0, 0);
break; break;
case ESBA: case ESBA:
ry_ba = ry_dbr; /* save WC */ ry_ba = ry_dbr; /* save WC */
ry_state = ESXFR; /* next state */ ry_state = ESXFR; /* next state */
sim_activate (uptr, ry_cwait); /* schedule xfer */ sim_activate (uptr, ry_cwait); /* schedule xfer */
return SCPE_OK; return SCPE_OK;
case ESXFR: case ESXFR:
estat[0] = ry_ecode; /* fill 8B status */ estat[0] = ry_ecode; /* fill 8B status */
estat[1] = ry_wc; estat[1] = ry_wc;
estat[2] = ry_unit[0].TRACK; estat[2] = ry_unit[0].TRACK;
estat[3] = ry_unit[1].TRACK; estat[3] = ry_unit[1].TRACK;
estat[4] = ry_track; estat[4] = ry_track;
estat[5] = ry_sector; estat[5] = ry_sector;
estat[6] = ((ry_csr & RYCS_DRV)? 0200: 0) | estat[6] = ((ry_csr & RYCS_DRV)? 0200: 0) |
((ry_unit[1].flags & UNIT_DEN)? 0100: 0) | ((ry_unit[1].flags & UNIT_DEN)? 0100: 0) |
((uptr->flags & UNIT_ATT)? 0040: 0) | ((uptr->flags & UNIT_ATT)? 0040: 0) |
((ry_unit[0].flags & UNIT_DEN)? 0020: 0) | ((ry_unit[0].flags & UNIT_DEN)? 0020: 0) |
((ry_csr & RYCS_DEN)? 0001: 0); ((ry_csr & RYCS_DEN)? 0001: 0);
estat[7] = uptr->TRACK; estat[7] = uptr->TRACK;
t = Map_WriteB (ba, 8, estat); /* DMA to memory */ t = Map_WriteB (ba, 8, estat); /* DMA to memory */
ry_done (t? RYES_NXM: 0, 0); /* done */ ry_done (t? RYES_NXM: 0, 0); /* done */
break; break;
case CMD_COMPLETE: /* command complete */ case CMD_COMPLETE: /* command complete */
ry_done (0, 0); ry_done (0, 0);
break; break;
case INIT_COMPLETE: /* init complete */ case INIT_COMPLETE: /* init complete */
ry_unit[0].TRACK = 1; /* drive 0 to trk 1 */ ry_unit[0].TRACK = 1; /* drive 0 to trk 1 */
ry_unit[1].TRACK = 0; /* drive 1 to trk 0 */ ry_unit[1].TRACK = 0; /* drive 1 to trk 0 */
if ((uptr->flags & UNIT_BUF) == 0) { /* not buffered? */ if ((uptr->flags & UNIT_BUF) == 0) { /* not buffered? */
ry_done (RYES_ID, 0010); /* init done, error */ ry_done (RYES_ID, 0010); /* init done, error */
break; break;
} }
da = CALC_DA (1, 1, bps); /* track 1, sector 1 */ da = CALC_DA (1, 1, bps); /* track 1, sector 1 */
for (i = 0; i < bps; i++) /* read sector */ for (i = 0; i < bps; i++) /* read sector */
rx2xb[i] = fbuf[da + i]; rx2xb[i] = fbuf[da + i];
ry_done (RYES_ID, 0); /* set done */ ry_done (RYES_ID, 0); /* set done */
if ((ry_unit[1].flags & UNIT_ATT) == 0) if ((ry_unit[1].flags & UNIT_ATT) == 0)
ry_ecode = 0020; ry_ecode = 0020;
break; break;
} /* end case state */ } /* end case state */
return SCPE_OK; return SCPE_OK;
} }

2
PDP11/pdp11_stddev.c
View file

@ -29,7 +29,7 @@
18-Apr-12 RMS Modified to use clock coscheduling 18-Apr-12 RMS Modified to use clock coscheduling
20-May-08 RMS Standardized clock delay at 1mips 20-May-08 RMS Standardized clock delay at 1mips
18-Jun-07 RMS Added UNIT_IDLE flag to console input, clock 18-Jun-07 RMS Added UNIT_IDLE flag to console input, clock
29-Oct-06 RMS Synced keyboard and clock 29-Oct-06 RMS Synced keyboard and clock
Added clock coscheduling support Added clock coscheduling support
05-Jul-06 RMS Added UC only support for early DOS/RSTS 05-Jul-06 RMS Added UC only support for early DOS/RSTS
22-Nov-05 RMS Revised for new terminal processing routines 22-Nov-05 RMS Revised for new terminal processing routines

24
PDP11/pdp11_tc.c
View file

@ -25,7 +25,7 @@
tc TC11/TU56 DECtape tc TC11/TU56 DECtape
23-Jun-06 RMS Fixed switch conflict in ATTACH 23-Jun-06 RMS Fixed switch conflict in ATTACH
10-Feb-06 RMS READ sets extended data bits in TCST (Alan Frisbie) 10-Feb-06 RMS READ sets extended data bits in TCST (Alan Frisbie)
16-Aug-05 RMS Fixed C++ declaration and cast problems 16-Aug-05 RMS Fixed C++ declaration and cast problems
07-Jul-05 RMS Removed extraneous externs 07-Jul-05 RMS Removed extraneous externs
@ -265,10 +265,10 @@
#define LOG_BL 0x4 #define LOG_BL 0x4
#define DT_SETDONE tccm = tccm | CSR_DONE; \ #define DT_SETDONE tccm = tccm | CSR_DONE; \
if (tccm & CSR_IE) \ if (tccm & CSR_IE) \
SET_INT (DTA) SET_INT (DTA)
#define DT_CLRDONE tccm = tccm & ~CSR_DONE; \ #define DT_CLRDONE tccm = tccm & ~CSR_DONE; \
CLR_INT (DTA) CLR_INT (DTA)
#define ABS(x) (((x) < 0)? (-(x)): (x)) #define ABS(x) (((x) < 0)? (-(x)): (x))
extern uint16 *M; /* memory */ extern uint16 *M; /* memory */
@ -708,7 +708,7 @@ switch (fnc) { /* case function */
if (dir) if (dir)
newpos = DT_BLK2LN (blk + 1, uptr) - DT_CSMLN - DT_WSIZE; newpos = DT_BLK2LN (blk + 1, uptr) - DT_CSMLN - DT_WSIZE;
else newpos = DT_BLK2LN (blk, uptr) + DT_CSMLN + (DT_WSIZE - 1); else newpos = DT_BLK2LN (blk, uptr) + DT_CSMLN + (DT_WSIZE - 1);
} }
if (fnc == FNC_WALL) sim_activate /* write all? */ if (fnc == FNC_WALL) sim_activate /* write all? */
(&dt_dev.units[DT_TIMER], dt_ctime); /* sched done */ (&dt_dev.units[DT_TIMER], dt_ctime); /* sched done */
if (DEBUG_PRI (dt_dev, LOG_RW) || if (DEBUG_PRI (dt_dev, LOG_RW) ||
@ -783,13 +783,13 @@ if (mot & DTS_DIR) /* update pos */
else uptr->pos = uptr->pos + delta; else uptr->pos = uptr->pos + delta;
if (((int32) uptr->pos < 0) || if (((int32) uptr->pos < 0) ||
((int32) uptr->pos > (DTU_FWDEZ (uptr) + DT_EZLIN))) { ((int32) uptr->pos > (DTU_FWDEZ (uptr) + DT_EZLIN))) {
detach_unit (uptr); /* off reel? */ detach_unit (uptr); /* off reel? */
uptr->STATE = uptr->pos = 0; uptr->STATE = uptr->pos = 0;
unum = (int32) (uptr - dt_dev.units); unum = (int32) (uptr - dt_dev.units);
if ((unum == CSR_GETUNIT (tccm)) && (CSR_GETFNC (tccm) != FNC_STOP)) if ((unum == CSR_GETUNIT (tccm)) && (CSR_GETFNC (tccm) != FNC_STOP))
dt_seterr (uptr, STA_SEL); /* error */ dt_seterr (uptr, STA_SEL); /* error */
return TRUE; return TRUE;
} }
return FALSE; return FALSE;
} }
@ -1303,7 +1303,7 @@ if (sim_is_active (uptr)) { /* active? cancel op */
tccm = tccm | CSR_ERR | CSR_DONE; tccm = tccm | CSR_ERR | CSR_DONE;
if (tccm & CSR_IE) if (tccm & CSR_IE)
SET_INT (DTA); SET_INT (DTA);
} }
uptr->STATE = uptr->pos = 0; uptr->STATE = uptr->pos = 0;
} }
fbuf = (uint32 *) uptr->filebuf; /* file buffer */ fbuf = (uint32 *) uptr->filebuf; /* file buffer */

2
PDP11/pdp11_tm.c
View file

@ -639,7 +639,7 @@ int32 u = uptr - tm_dev.units;
if ((uptr->flags & UNIT_ATT) && if ((uptr->flags & UNIT_ATT) &&
(val || sim_tape_wrp (uptr))) (val || sim_tape_wrp (uptr)))
uptr->USTAT = uptr->USTAT | STA_WLK; uptr->USTAT = uptr->USTAT | STA_WLK;
else uptr->USTAT = uptr->USTAT & ~STA_WLK; else uptr->USTAT = uptr->USTAT & ~STA_WLK;
if (u == GET_UNIT (tm_cmd)) if (u == GET_UNIT (tm_cmd))
tm_updcsta (uptr); tm_updcsta (uptr);

2
PDP11/pdp11_tu.c
View file

@ -744,7 +744,7 @@ switch (fnc) { /* case on function */
for (i = j = 0; j < xbc; j = j + 1) { for (i = j = 0; j < xbc; j = j + 1) {
xbuf[i++] = wbuf[j] & 0377; xbuf[i++] = wbuf[j] & 0377;
xbuf[i++] = (wbuf[j] >> 8) & 0377; xbuf[i++] = (wbuf[j] >> 8) & 0377;
} }
tbc = xbc; tbc = xbc;
} }
if ((st = sim_tape_wrrecf (uptr, xbuf, tbc))) /* write rec, err? */ if ((st = sim_tape_wrrecf (uptr, xbuf, tbc))) /* write rec, err? */

20
PDP11/pdp11_vh.c
View file

@ -1575,35 +1575,35 @@ fprintf (st, "and output of characters.\n\n");
fprintf (st, "By default, the DHV11 mode is selected, though DHU11 mode is recommended\n"); fprintf (st, "By default, the DHV11 mode is selected, though DHU11 mode is recommended\n");
fprintf (st, "for applications that can support it. The %s controller may be adjusted\n", dptr->name); fprintf (st, "for applications that can support it. The %s controller may be adjusted\n", dptr->name);
fprintf (st, "on a per controller basis as follows:\n\n"); fprintf (st, "on a per controller basis as follows:\n\n");
fprintf (st, " sim> SET %sn DHU use the DHU programming mode\n", dptr->name); fprintf (st, " sim> SET %sn DHU use the DHU programming mode\n", dptr->name);
fprintf (st, " sim> SET %sn DHV use the DHV programming mode\n\n", dptr->name); fprintf (st, " sim> SET %sn DHV use the DHV programming mode\n\n", dptr->name);
fprintf (st, "DMA output is supported. In a real %s, DMA is not initiated immediately\n", devtype); fprintf (st, "DMA output is supported. In a real %s, DMA is not initiated immediately\n", devtype);
fprintf (st, "upon receipt of TX.DMA.START but is dependent upon some internal processes.\n"); fprintf (st, "upon receipt of TX.DMA.START but is dependent upon some internal processes.\n");
fprintf (st, "The %s controller mimics this behavior by default. It may be desirable to\n", dptr->name); fprintf (st, "The %s controller mimics this behavior by default. It may be desirable to\n", dptr->name);
fprintf (st, "alter this and start immediately, though this may not be compatible with all\n"); fprintf (st, "alter this and start immediately, though this may not be compatible with all\n");
fprintf (st, "operating systems and diagnostics. You can change the behavior of the %s\n", dptr->name); fprintf (st, "operating systems and diagnostics. You can change the behavior of the %s\n", dptr->name);
fprintf (st, "controller as follows:\n\n"); fprintf (st, "controller as follows:\n\n");
fprintf (st, " sim> SET %sn NORMAL use normal DMA procedures\n", dptr->name); fprintf (st, " sim> SET %sn NORMAL use normal DMA procedures\n", dptr->name);
fprintf (st, " sim> SET %sn FASTDMA set DMA to initiate immediately\n\n", dptr->name); fprintf (st, " sim> SET %sn FASTDMA set DMA to initiate immediately\n\n", dptr->name);
fprintf (st, "The number of lines (and therefore the number of %s devices\n", devtype); fprintf (st, "The number of lines (and therefore the number of %s devices\n", devtype);
fprintf (st, "simulated) can be changed with the command:\n\n"); fprintf (st, "simulated) can be changed with the command:\n\n");
fprintf (st, " sim> SET %s LINES=n set line count to n\n\n", dptr->name); fprintf (st, " sim> SET %s LINES=n set line count to n\n\n", dptr->name);
fprintf (st, "The line count must be a multiple of %d, with a maximum of %d.\n\n", VH_LINES, VH_LINES*VH_MUXES); fprintf (st, "The line count must be a multiple of %d, with a maximum of %d.\n\n", VH_LINES, VH_LINES*VH_MUXES);
fprintf (st, "Modem and auto-disconnect support may be set on an individual controller\n"); fprintf (st, "Modem and auto-disconnect support may be set on an individual controller\n");
fprintf (st, "basis. The SET MODEM command directs the controller to report modem status\n"); fprintf (st, "basis. The SET MODEM command directs the controller to report modem status\n");
fprintf (st, "changes to the computer. The SET HANGUP command turns on active disconnects\n"); fprintf (st, "changes to the computer. The SET HANGUP command turns on active disconnects\n");
fprintf (st, "(disconnect session if computer clears Data Terminal Ready).\n\n"); fprintf (st, "(disconnect session if computer clears Data Terminal Ready).\n\n");
fprintf (st, " sim> SET %sn [NO]MODEM disable/enable modem control\n", dptr->name); fprintf (st, " sim> SET %sn [NO]MODEM disable/enable modem control\n", dptr->name);
fprintf (st, " sim> SET %sn [NO]HANGUP disable/enable disconnect on DTR drop\n\n", dptr->name); fprintf (st, " sim> SET %sn [NO]HANGUP disable/enable disconnect on DTR drop\n\n", dptr->name);
fprintf (st, "Once the %s devuce is attached and the simulator is running, the %s will\n", dptr->name, dptr->name); fprintf (st, "Once the %s devuce is attached and the simulator is running, the %s will\n", dptr->name, dptr->name);
fprintf (st, "listen for connections on the specified port. It assumes that the incoming\n"); fprintf (st, "listen for connections on the specified port. It assumes that the incoming\n");
fprintf (st, "connections are Telnet connections. The connection remains open until\n"); fprintf (st, "connections are Telnet connections. The connection remains open until\n");
fprintf (st, "disconnected by the simulated program, the Telnet client, a SET %s DISCONNECT\n", dptr->name); fprintf (st, "disconnected by the simulated program, the Telnet client, a SET %s DISCONNECT\n", dptr->name);
fprintf (st, "command, or a DETACH %s command.\n\n", dptr->name); fprintf (st, "command, or a DETACH %s command.\n\n", dptr->name);
fprintf (st, "Other special %s commands:\n\n", dptr->name); fprintf (st, "Other special %s commands:\n\n", dptr->name);
fprintf (st, " sim> SHOW %s CONNECTIONS show current connections\n", dptr->name); fprintf (st, " sim> SHOW %s CONNECTIONS show current connections\n", dptr->name);
fprintf (st, " sim> SHOW %s STATISTICS show statistics for active connections\n", dptr->name); fprintf (st, " sim> SHOW %s STATISTICS show statistics for active connections\n", dptr->name);
fprintf (st, " sim> SET %s DISCONNECT=linenumber disconnects the specified line.\n\n", dptr->name); fprintf (st, " sim> SET %s DISCONNECT=linenumber disconnects the specified line.\n\n", dptr->name);
fprintf (st, "The %s does not support save and restore. All open connections are lost\n", devtype); fprintf (st, "The %s does not support save and restore. All open connections are lost\n", devtype);
fprintf (st, "when the simulator shuts down or the %s is detached.\n\n", dptr->name); fprintf (st, "when the simulator shuts down or the %s is detached.\n\n", dptr->name);
vh_help_attach (st, dptr, uptr, flag, cptr); vh_help_attach (st, dptr, uptr, flag, cptr);

6
PDP11/pdp11_xq.c
View file

@ -326,7 +326,7 @@ struct xq_device xqb = {
#define IOLN_XQ 020 #define IOLN_XQ 020
DIB xqa_dib = { IOBA_AUTO, IOLN_XQ, &xq_rd, &xq_wr, DIB xqa_dib = { IOBA_AUTO, IOLN_XQ, &xq_rd, &xq_wr,
1, IVCL (XQ), 0, { &xq_int } }; 1, IVCL (XQ), 0, { &xq_int } };
UNIT xqa_unit[] = { UNIT xqa_unit[] = {
{ UDATA (&xq_svc, UNIT_IDLE|UNIT_ATTABLE|UNIT_DISABLE, 2047) }, /* receive timer */ { UDATA (&xq_svc, UNIT_IDLE|UNIT_ATTABLE|UNIT_DISABLE, 2047) }, /* receive timer */
@ -382,7 +382,7 @@ REG xqa_reg[] = {
}; };
DIB xqb_dib = { IOBA_AUTO, IOLN_XQ, &xq_rd, &xq_wr, DIB xqb_dib = { IOBA_AUTO, IOLN_XQ, &xq_rd, &xq_wr,
1, IVCL (XQ), 0, { &xq_int } }; 1, IVCL (XQ), 0, { &xq_int } };
UNIT xqb_unit[] = { UNIT xqb_unit[] = {
{ UDATA (&xq_svc, UNIT_IDLE|UNIT_ATTABLE|UNIT_DISABLE, 2047) }, /* receive timer */ { UDATA (&xq_svc, UNIT_IDLE|UNIT_ATTABLE|UNIT_DISABLE, 2047) }, /* receive timer */
@ -1381,7 +1381,7 @@ t_stat xq_process_xbdl(CTLR* xq)
else { else {
if (xq->var->coalesce_latency == 0) if (xq->var->coalesce_latency == 0)
xq_svc(&xq->unit[0]); /* service any received data */ xq_svc(&xq->unit[0]); /* service any received data */
} }
sim_debug(DBG_WRN, xq->dev, "XBDL completed processing write\n"); sim_debug(DBG_WRN, xq->dev, "XBDL completed processing write\n");
} /* loopback/non-loopback */ } /* loopback/non-loopback */

78
PDP11/pdp11_xu.c
View file

@ -56,7 +56,7 @@
probably need to be converted to Map_ReadW and Map_WriteW calls. probably need to be converted to Map_ReadW and Map_WriteW calls.
4) Some jerkiness seen during interactive I/O with remote systems; 4) Some jerkiness seen during interactive I/O with remote systems;
this is probably attributable to changed polling times from when this is probably attributable to changed polling times from when
the poll duration was standardized for idling support. the poll duration was standardized for idling support.
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
@ -222,11 +222,11 @@ DEBTAB xu_debug[] = {
DEVICE xu_dev = { DEVICE xu_dev = {
"XU", xua_unit, xua_reg, xu_mod, "XU", xua_unit, xua_reg, xu_mod,
2, XU_RDX, 8, 1, XU_RDX, 8, 2, XU_RDX, 8, 1, XU_RDX, 8,
&xu_ex, &xu_dep, &xu_reset, &xu_ex, &xu_dep, &xu_reset,
NULL, &xu_attach, &xu_detach, NULL, &xu_attach, &xu_detach,
&xua_dib, DEV_DISABLE | DEV_DIS | DEV_UBUS | DEV_DEBUG | DEV_ETHER, &xua_dib, DEV_DISABLE | DEV_DIS | DEV_UBUS | DEV_DEBUG | DEV_ETHER,
0, xu_debug, NULL, NULL, &xu_help, NULL, NULL, 0, xu_debug, NULL, NULL, &xu_help, NULL, NULL,
&xu_description &xu_description
}; };
@ -234,7 +234,7 @@ DEVICE xu_dev = {
#define IOLN_XU 010 #define IOLN_XU 010
DIB xub_dib = { IOBA_AUTO, IOLN_XU, &xu_rd, &xu_wr, DIB xub_dib = { IOBA_AUTO, IOLN_XU, &xu_rd, &xu_wr,
1, IVCL (XU), 0, { &xu_int } }; 1, IVCL (XU), 0, { &xu_int } };
UNIT xub_unit[] = { UNIT xub_unit[] = {
{ UDATA (&xu_svc, UNIT_IDLE|UNIT_ATTABLE|UNIT_DISABLE, 0) } /* receive timer */ { UDATA (&xu_svc, UNIT_IDLE|UNIT_ATTABLE|UNIT_DISABLE, 0) } /* receive timer */
@ -530,7 +530,7 @@ t_stat xu_process_local (CTLR* xu, ETH_PACK* pack)
void xu_read_callback(CTLR* xu, int status) void xu_read_callback(CTLR* xu, int status)
{ {
if (DBG_PCK & xu->dev->dctrl) if (DBG_PCK & xu->dev->dctrl)
eth_packet_trace_ex(xu->var->etherface, xu->var->read_buffer.msg, xu->var->read_buffer.len, "xu-recvd", DBG_DAT & xu->dev->dctrl, DBG_PCK); eth_packet_trace_ex(xu->var->etherface, xu->var->read_buffer.msg, xu->var->read_buffer.len, "xu-recvd", DBG_DAT & xu->dev->dctrl, DBG_PCK);
/* process any packets locally that can be */ /* process any packets locally that can be */
status = xu_process_local (xu, &xu->var->read_buffer); status = xu_process_local (xu, &xu->var->read_buffer);
@ -826,19 +826,19 @@ int32 xu_command(CTLR* xu)
case FC_NOOP: case FC_NOOP:
break; break;
case FC_RDPA: /* read default physical address */ case FC_RDPA: /* read default physical address */
wstatus = Map_WriteB(xu->var->pcbb + 2, 6, xu->var->mac); wstatus = Map_WriteB(xu->var->pcbb + 2, 6, xu->var->mac);
if (wstatus) if (wstatus)
return PCSR0_PCEI + 1; return PCSR0_PCEI + 1;
break; break;
case FC_RPA: /* read current physical address */ case FC_RPA: /* read current physical address */
wstatus = Map_WriteB(xu->var->pcbb + 2, 6, (uint8*)&xu->var->setup.macs[0]); wstatus = Map_WriteB(xu->var->pcbb + 2, 6, (uint8*)&xu->var->setup.macs[0]);
if (wstatus) if (wstatus)
return PCSR0_PCEI + 1; return PCSR0_PCEI + 1;
break; break;
case FC_WPA: /* write current physical address */ case FC_WPA: /* write current physical address */
rstatus = Map_ReadB(xu->var->pcbb + 2, 6, (uint8*)&xu->var->setup.macs[0]); rstatus = Map_ReadB(xu->var->pcbb + 2, 6, (uint8*)&xu->var->setup.macs[0]);
if (xu->var->pcb[1] & 1) if (xu->var->pcb[1] & 1)
return PCSR0_PCEI; return PCSR0_PCEI;
@ -874,7 +874,7 @@ int32 xu_command(CTLR* xu)
} }
break; break;
case FC_RRF: /* read ring format */ case FC_RRF: /* read ring format */
if ((xu->var->pcb[1] & 1) || (xu->var->pcb[2] & 0374)) if ((xu->var->pcb[1] & 1) || (xu->var->pcb[2] & 0374))
return PCSR0_PCEI; return PCSR0_PCEI;
xu->var->udb[0] = xu->var->tdrb & 0177776; xu->var->udb[0] = xu->var->tdrb & 0177776;
@ -891,7 +891,7 @@ int32 xu_command(CTLR* xu)
return PCSR0_PCEI+1; return PCSR0_PCEI+1;
break; break;
case FC_WRF: /* write ring format */ case FC_WRF: /* write ring format */
if ((xu->var->pcb[1] & 1) || (xu->var->pcb[2] & 0374)) if ((xu->var->pcb[1] & 1) || (xu->var->pcb[2] & 0374))
return PCSR0_PCEI; return PCSR0_PCEI;
if ((xu->var->pcsr1 & PCSR1_STATE) == STATE_RUNNING) if ((xu->var->pcsr1 & PCSR1_STATE) == STATE_RUNNING)
@ -975,14 +975,14 @@ int32 xu_command(CTLR* xu)
memset(stats, 0, sizeof(struct xu_stats)); memset(stats, 0, sizeof(struct xu_stats));
break; break;
case FC_RMODE: /* read mode register */ case FC_RMODE: /* read mode register */
value = xu->var->mode; value = xu->var->mode;
wstatus = Map_WriteW(xu->var->pcbb+2, 2, &value); wstatus = Map_WriteW(xu->var->pcbb+2, 2, &value);
if (wstatus) if (wstatus)
return PCSR0_PCEI + 1; return PCSR0_PCEI + 1;
break; break;
case FC_WMODE: /* write mode register */ case FC_WMODE: /* write mode register */
value = xu->var->mode; value = xu->var->mode;
xu->var->mode = xu->var->pcb[1]; xu->var->mode = xu->var->pcb[1];
sim_debug(DBG_TRC, xu->dev, "FC_WMODE: mode=%04x\n", xu->var->mode); sim_debug(DBG_TRC, xu->dev, "FC_WMODE: mode=%04x\n", xu->var->mode);
@ -998,8 +998,8 @@ int32 xu_command(CTLR* xu)
xu->var->setup.promiscuous); xu->var->setup.promiscuous);
break; break;
case FC_RSTAT: /* read extended status */ case FC_RSTAT: /* read extended status */
case FC_RCSTAT: /* read and clear extended status */ case FC_RCSTAT: /* read and clear extended status */
value = xu->var->stat; value = xu->var->stat;
wstatus = Map_WriteW(xu->var->pcbb+2, 2, &value); wstatus = Map_WriteW(xu->var->pcbb+2, 2, &value);
value = 10; value = 10;
@ -1010,7 +1010,7 @@ int32 xu_command(CTLR* xu)
return PCSR0_PCEI + 1; return PCSR0_PCEI + 1;
if (fnc == FC_RCSTAT) if (fnc == FC_RCSTAT)
xu->var->stat &= 0377; /* clear high byte */ xu->var->stat &= 0377; /* clear high byte */
break; break;
case FC_RSID: /* read system id parameters */ case FC_RSID: /* read system id parameters */
@ -1079,7 +1079,7 @@ int32 xu_command(CTLR* xu)
return PCSR0_PCEI + 1; return PCSR0_PCEI + 1;
break; break;
default: /* Unknown (unimplemented) command. */ default: /* Unknown (unimplemented) command. */
printf("%s: unknown ancilliary command 0%o requested !\n", xu->dev->name, fnc); printf("%s: unknown ancilliary command 0%o requested !\n", xu->dev->name, fnc);
return PCSR0_PCEI; return PCSR0_PCEI;
break; break;
@ -1160,7 +1160,7 @@ void xu_process_receive(CTLR* xu)
if (item->packet.len < ETH_MIN_PACKET) { if (item->packet.len < ETH_MIN_PACKET) {
int len = item->packet.len; int len = item->packet.len;
memset (&item->packet.msg[len], 0, ETH_MIN_PACKET - len); memset (&item->packet.msg[len], 0, ETH_MIN_PACKET - len);
item->packet.len = ETH_MIN_PACKET; item->packet.len = ETH_MIN_PACKET;
} }
} }
@ -1344,7 +1344,7 @@ void xu_process_transmit(CTLR* xu)
wstatus = eth_write(xu->var->etherface, &xu->var->write_buffer, xu->var->wcallback); wstatus = eth_write(xu->var->etherface, &xu->var->write_buffer, xu->var->wcallback);
if (wstatus) if (wstatus)
xu->var->pcsr0 |= PCSR0_PCEI; xu->var->pcsr0 |= PCSR0_PCEI;
else else
if (DBG_PCK & xu->dev->dctrl) if (DBG_PCK & xu->dev->dctrl)
eth_packet_trace_ex(xu->var->etherface, xu->var->write_buffer.msg, xu->var->write_buffer.len, "xu-write", DBG_DAT & xu->dev->dctrl, DBG_PCK); eth_packet_trace_ex(xu->var->etherface, xu->var->write_buffer.msg, xu->var->write_buffer.len, "xu-write", DBG_DAT & xu->dev->dctrl, DBG_PCK);
} }
@ -1432,38 +1432,38 @@ void xu_port_command (CTLR* xu)
sim_debug(DBG_TRC, xu->dev, "xu_port_command(), Command = %s [0%o]\n", commands[command], command); sim_debug(DBG_TRC, xu->dev, "xu_port_command(), Command = %s [0%o]\n", commands[command], command);
switch (command) { /* cases in order of most used to least used */ switch (command) { /* cases in order of most used to least used */
case CMD_PDMD: /* POLLING DEMAND */ case CMD_PDMD: /* POLLING DEMAND */
/* process transmit buffers, receive buffers are done in the service timer */ /* process transmit buffers, receive buffers are done in the service timer */
xu_process_transmit(xu); xu_process_transmit(xu);
xu->var->pcsr0 |= PCSR0_DNI; xu->var->pcsr0 |= PCSR0_DNI;
break; break;
case CMD_GETCMD: /* GET COMMAND */ case CMD_GETCMD: /* GET COMMAND */
xu_command(xu); xu_command(xu);
xu->var->pcsr0 |= PCSR0_DNI; xu->var->pcsr0 |= PCSR0_DNI;
break; break;
case CMD_GETPCBB: /* GET PCB-BASE */ case CMD_GETPCBB: /* GET PCB-BASE */
xu->var->pcbb = (xu->var->pcsr3 << 16) | xu->var->pcsr2; xu->var->pcbb = (xu->var->pcsr3 << 16) | xu->var->pcsr2;
xu->var->pcsr0 |= PCSR0_DNI; xu->var->pcsr0 |= PCSR0_DNI;
break; break;
case CMD_SELFTEST: /* SELFTEST */ case CMD_SELFTEST: /* SELFTEST */
/* /*
SELFTEST is a <=15-second self diagnostic test, setting various SELFTEST is a <=15-second self diagnostic test, setting various
error flags and the DONE (DNI) flag when complete. For simulation error flags and the DONE (DNI) flag when complete. For simulation
purposes, signal completion immediately with no errors. This purposes, signal completion immediately with no errors. This
inexact behavior could be incompatible with any guest machine inexact behavior could be incompatible with any guest machine
diagnostics that are expecting to be able to monitor the diagnostics that are expecting to be able to monitor the
controller's progress through the diagnostic testing. controller's progress through the diagnostic testing.
*/ */
xu->var->pcsr0 |= PCSR0_DNI; xu->var->pcsr0 |= PCSR0_DNI;
xu->var->pcsr0 &= ~PCSR0_USCI; xu->var->pcsr0 &= ~PCSR0_USCI;
xu->var->pcsr0 &= ~PCSR0_FATL; xu->var->pcsr0 &= ~PCSR0_FATL;
xu->var->pcsr1 = STATE_READY; xu->var->pcsr1 = STATE_READY;
break; break;
case CMD_START: /* START */ case CMD_START: /* START */
if (state == STATE_READY) { if (state == STATE_READY) {
xu->var->pcsr1 &= ~PCSR1_STATE; xu->var->pcsr1 &= ~PCSR1_STATE;
xu->var->pcsr1 |= STATE_RUNNING; xu->var->pcsr1 |= STATE_RUNNING;
@ -1487,7 +1487,7 @@ void xu_port_command (CTLR* xu)
xu->var->pcsr0 |= PCSR0_PCEI; xu->var->pcsr0 |= PCSR0_PCEI;
break; break;
case CMD_STOP: /* STOP */ case CMD_STOP: /* STOP */
if (state == STATE_RUNNING) { if (state == STATE_RUNNING) {
xu->var->pcsr1 &= ~PCSR1_STATE; xu->var->pcsr1 &= ~PCSR1_STATE;
xu->var->pcsr1 |= STATE_READY; xu->var->pcsr1 |= STATE_READY;
@ -1575,7 +1575,7 @@ t_stat xu_wr(int32 data, int32 PA, int32 access)
sim_debug(DBG_REG, xu->dev, "xu_wr(), PCSR%d, data=%08x, PA=%08x, access=%d[%s]\n", reg, data, PA, access, desc); sim_debug(DBG_REG, xu->dev, "xu_wr(), PCSR%d, data=%08x, PA=%08x, access=%d[%s]\n", reg, data, PA, access, desc);
switch (reg) { switch (reg) {
case 00: case 00:
/* Clear write-one-to-clear interrupt bits */ /* Clear write-one-to-clear interrupt bits */
if (access == WRITEB) { if (access == WRITEB) {
data &= 0377; data &= 0377;
if (PA & 1) { if (PA & 1) {
@ -1622,11 +1622,11 @@ t_stat xu_wr(int32 data, int32 PA, int32 access)
break; break;
case 02: case 02:
xu->var->pcsr2 = data & 0177776; /* store word, but not MBZ LSB */ xu->var->pcsr2 = data & 0177776; /* store word, but not MBZ LSB */
break; break;
case 03: case 03:
xu->var->pcsr3 = data & 0000003; /* store significant bits */ xu->var->pcsr3 = data & 0000003; /* store significant bits */
break; break;
} }
return SCPE_OK; return SCPE_OK;
@ -1766,7 +1766,7 @@ void xu_dump_rxring (CTLR* xu)
for (i=0; i<rrlen; i++) { for (i=0; i<rrlen; i++) {
uint16 rxhdr[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF}; uint16 rxhdr[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
uint32 ba = xu->var->rdrb + (xu->var->relen * 2) * i; uint32 ba = xu->var->rdrb + (xu->var->relen * 2) * i;
t_stat rstatus = Map_ReadW (ba, 8, rxhdr); /* get rxring entry[i] */ t_stat rstatus = Map_ReadW (ba, 8, rxhdr); /* get rxring entry[i] */
int own = (rxhdr[2] & RXR_OWN) >> 15; int own = (rxhdr[2] & RXR_OWN) >> 15;
int len = rxhdr[0]; int len = rxhdr[0];
uint32 addr = rxhdr[1] + ((rxhdr[2] & 3) << 16); uint32 addr = rxhdr[1] + ((rxhdr[2] & 3) << 16);
@ -1783,7 +1783,7 @@ void xu_dump_txring (CTLR* xu)
for (i=0; i<trlen; i++) { for (i=0; i<trlen; i++) {
uint16 txhdr[4]; uint16 txhdr[4];
uint32 ba = xu->var->tdrb + (xu->var->telen * 2) * i; uint32 ba = xu->var->tdrb + (xu->var->telen * 2) * i;
t_stat tstatus = Map_ReadW (ba, 8, txhdr); /* get rxring entry[i] */ t_stat tstatus = Map_ReadW (ba, 8, txhdr); /* get rxring entry[i] */
int own = (txhdr[2] & RXR_OWN) >> 15; int own = (txhdr[2] & RXR_OWN) >> 15;
int len = txhdr[0]; int len = txhdr[0];
uint32 addr = txhdr[1] + ((txhdr[2] & 3) << 16); uint32 addr = txhdr[1] + ((txhdr[2] & 3) << 16);

4
VAX/vax610_io.c
View file

@ -222,8 +222,8 @@ for (i = 0; int_req[l] && (i < 32); i++) {
if ((int_req[l] >> i) & 1) { if ((int_req[l] >> i) & 1) {
int_req[l] = int_req[l] & ~(1u << i); int_req[l] = int_req[l] & ~(1u << i);
if (int_ack[l][i]) if (int_ack[l][i])
return int_ack[l][i](); return int_ack[l][i]();
return int_vec[l][i]; return int_vec[l][i];
} }
} }
return 0; return 0;

4
VAX/vax630_io.c
View file

@ -263,8 +263,8 @@ for (i = 0; int_req[l] && (i < 32); i++) {
if ((int_req[l] >> i) & 1) { if ((int_req[l] >> i) & 1) {
int_req[l] = int_req[l] & ~(1u << i); int_req[l] = int_req[l] & ~(1u << i);
if (int_ack[l][i]) if (int_ack[l][i])
return int_ack[l][i](); return int_ack[l][i]();
return int_vec[l][i]; return int_vec[l][i];
} }
} }
return 0; return 0;

10
VAX/vax630_sysdev.c
View file

@ -106,8 +106,8 @@ CTAB vax630_cmd[] = {
#define MSER_MCD1 0x00000200 /* Mem Code 1 */ #define MSER_MCD1 0x00000200 /* Mem Code 1 */
#define MSER_MBZ 0xFFFFFC04 #define MSER_MBZ 0xFFFFFC04
#define MSER_RD (MSER_PE | MSER_WWP | MSER_LEB | \ #define MSER_RD (MSER_PE | MSER_WWP | MSER_LEB | \
MSER_DQPE | MSER_CQPE | MSER_CLPE | \ MSER_DQPE | MSER_CQPE | MSER_CLPE | \
MSER_NXM | MSER_MCD0 | MSER_MCD1) MSER_NXM | MSER_MCD0 | MSER_MCD1)
#define MSER_WR (MSER_PE | MSER_WWP) #define MSER_WR (MSER_PE | MSER_WWP)
#define MSER_RS (MSER_LEB | MSER_DQPE | MSER_CQPE | MSER_CLPE | MSER_NXM) #define MSER_RS (MSER_LEB | MSER_DQPE | MSER_CQPE | MSER_CLPE | MSER_NXM)
@ -409,7 +409,7 @@ fprintf (st, "Read-only memory (ROM)\n\n");
fprintf (st, "The boot ROM consists of a single unit, simulating the 64KB boot ROM. It has\n"); fprintf (st, "The boot ROM consists of a single unit, simulating the 64KB boot ROM. It has\n");
fprintf (st, "no registers. The boot ROM is loaded with a binary byte stream using the \n"); fprintf (st, "no registers. The boot ROM is loaded with a binary byte stream using the \n");
fprintf (st, "LOAD -r command:\n\n"); fprintf (st, "LOAD -r command:\n\n");
fprintf (st, " LOAD -r KA630.BIN load ROM image KA630.BIN\n\n"); fprintf (st, " LOAD -r KA630.BIN load ROM image KA630.BIN\n\n");
fprintf (st, "When the simulator starts running (via the BOOT command), if the ROM has\n"); fprintf (st, "When the simulator starts running (via the BOOT command), if the ROM has\n");
fprintf (st, "not yet been loaded, an attempt will be made to automatically load the\n"); fprintf (st, "not yet been loaded, an attempt will be made to automatically load the\n");
fprintf (st, "ROM image from the file ka655x.bin in the current working directory.\n"); fprintf (st, "ROM image from the file ka655x.bin in the current working directory.\n");
@ -825,8 +825,8 @@ p2 = mchk_va + 4; /* save vap */
st = 0; st = 0;
if (p1 & 0x80) { /* mref? */ if (p1 & 0x80) { /* mref? */
cc = intexc (SCB_MCHK, cc, 0, IE_EXC); /* take normal exception */ cc = intexc (SCB_MCHK, cc, 0, IE_EXC); /* take normal exception */
if (!(ka_mser & MSER_CQPE) && !(ka_mser & MSER_CLPE)) if (!(ka_mser & MSER_CQPE) && !(ka_mser & MSER_CLPE))
ka_mser |= MSER_NXM; ka_mser |= MSER_NXM;
} }
else cc = intexc (SCB_MCHK, cc, 0, IE_SVE); /* take severe exception */ else cc = intexc (SCB_MCHK, cc, 0, IE_SVE); /* take severe exception */
acc = ACC_MASK (KERN); /* in kernel mode */ acc = ACC_MASK (KERN); /* in kernel mode */

2
VAX/vax730_rb.c
View file

@ -103,7 +103,7 @@
#define RB02DS_ATT (RB02DS_HDO+RB02DS_BHO+RB02DS_LOCK) /* att status */ #define RB02DS_ATT (RB02DS_HDO+RB02DS_BHO+RB02DS_LOCK) /* att status */
#define RB02DS_UNATT (RB02DS_CVO+RB02DS_LOAD) /* unatt status */ #define RB02DS_UNATT (RB02DS_CVO+RB02DS_LOAD) /* unatt status */
#define RB02DS_ERR (RB02DS_WDE+RB02DS_HCE+RB02DS_STO+RB02DS_SPE+RB02DS_WGE+ \ #define RB02DS_ERR (RB02DS_WDE+RB02DS_HCE+RB02DS_STO+RB02DS_SPE+RB02DS_WGE+ \
RB02DS_VCK+RB02DS_DSE) /* errors bits */ RB02DS_VCK+RB02DS_DSE) /* errors bits */
#define RB80DS_SCNT 0x0000000F #define RB80DS_SCNT 0x0000000F
#define RB80DS_FLT 0x00000100 #define RB80DS_FLT 0x00000100

6
VAX/vax730_stddev.c
View file

@ -1070,15 +1070,15 @@ int32 sel = TXDB_GETSEL (data); /* get selection */
if (sel == TXDB_MISC) { /* misc function? */ if (sel == TXDB_MISC) { /* misc function? */
switch (data & MISC_MASK) { /* case on function */ switch (data & MISC_MASK) { /* case on function */
case MISC_CLWS: case MISC_CLWS:
case MISC_CLCS: case MISC_CLCS:
break; break;
case MISC_SWDN: case MISC_SWDN:
ABORT (STOP_SWDN); ABORT (STOP_SWDN);
break; break;
case MISC_BOOT: case MISC_BOOT:
ABORT (STOP_BOOT); ABORT (STOP_BOOT);
break; break;
} }

8
VAX/vax730_syslist.c
View file

@ -85,10 +85,10 @@ DEVICE *sim_devices[] = {
&tq_dev, &tq_dev,
&xu_dev, &xu_dev,
&xub_dev, &xub_dev,
&dmc_dev[0], &dmc_dev[0],
&dmc_dev[1], &dmc_dev[1],
&dmc_dev[2], &dmc_dev[2],
&dmc_dev[3], &dmc_dev[3],
&dup_dev, &dup_dev,
NULL NULL
}; };

2
VAX/vax730_uba.c
View file

@ -270,7 +270,7 @@ switch (ofs) { /* case on offset */
case UBADPR_OF + 2: case UBADPR_OF + 2:
break; /* ignore writes */ break; /* ignore writes */
case UBACSR_OF: /* CSR */ case UBACSR_OF: /* CSR */
if(val & 0x10000) uba_csr = 0; if(val & 0x10000) uba_csr = 0;
break; break;

8
VAX/vax750_syslist.c
View file

@ -90,10 +90,10 @@ DEVICE *sim_devices[] = {
&tq_dev, &tq_dev,
&xu_dev, &xu_dev,
&xub_dev, &xub_dev,
&dmc_dev[0], &dmc_dev[0],
&dmc_dev[1], &dmc_dev[1],
&dmc_dev[2], &dmc_dev[2],
&dmc_dev[3], &dmc_dev[3],
&dup_dev, &dup_dev,
NULL NULL
}; };

8
VAX/vax780_fload.c
View file

@ -68,10 +68,10 @@
/* RT11 directory entry offsets */ /* RT11 directory entry offsets */
#define DE_STATUS 0 /* status (odd byte) */ #define DE_STATUS 0 /* status (odd byte) */
#define TENTAT 001 /* tentative */ #define TENTAT 001 /* tentative */
#define EMPTY 002 #define EMPTY 002
#define PERM 004 #define PERM 004
#define ENDSEG 010 /* end of segment */ #define ENDSEG 010 /* end of segment */
#define DE_NAME 1 /* file name */ #define DE_NAME 1 /* file name */
#define DE_FLNT 4 /* file length */ #define DE_FLNT 4 /* file length */
#define DE_SIZE 7 /* entry size in words */ #define DE_SIZE 7 /* entry size in words */

8
VAX/vax780_syslist.c
View file

@ -92,10 +92,10 @@ DEVICE *sim_devices[] = {
&tq_dev, &tq_dev,
&xu_dev, &xu_dev,
&xub_dev, &xub_dev,
&dmc_dev[0], &dmc_dev[0],
&dmc_dev[1], &dmc_dev[1],
&dmc_dev[2], &dmc_dev[2],
&dmc_dev[3], &dmc_dev[3],
&dup_dev, &dup_dev,
NULL NULL
}; };

66
VAX/vax860_abus.c
View file

@ -466,29 +466,29 @@ switch (rg) {
val = VAX860_SID | VAX860_TYP | VAX860_ECO | VAX860_PLANT | VAX860_SN; val = VAX860_SID | VAX860_TYP | VAX860_ECO | VAX860_PLANT | VAX860_SN;
break; break;
case MT_PAMACC: /* PAMACC */ case MT_PAMACC: /* PAMACC */
val = pamm[pamloc >> 20]; val = pamm[pamloc >> 20];
val = val | (pamloc & PAMACC_ADDR); val = val | (pamloc & PAMACC_ADDR);
break; break;
case MT_PAMLOC: /* PAMLOC */ case MT_PAMLOC: /* PAMLOC */
val = pamloc & PAMLOC_ADDR; val = pamloc & PAMLOC_ADDR;
break; break;
case MT_MDCTL: /* MDCTL */ case MT_MDCTL: /* MDCTL */
val = mdctl & MDCTL_RW; val = mdctl & MDCTL_RW;
case MT_EHSR: /* EHSR */ case MT_EHSR: /* EHSR */
val = ehsr & EHSR_VMSE; val = ehsr & EHSR_VMSE;
break; break;
case MT_CSWP: /* CSWP */ case MT_CSWP: /* CSWP */
val = cswp & 0xF; val = cswp & 0xF;
break; break;
case MT_MERG: /* MERG */ case MT_MERG: /* MERG */
val = 0; val = 0;
break; break;
case MT_STXCS: /* STXCS */ case MT_STXCS: /* STXCS */
val = stxcs_rd (); val = stxcs_rd ();
@ -536,42 +536,42 @@ switch (rg) {
case MT_TXDB: /* TXDB */ case MT_TXDB: /* TXDB */
txdb_wr (val); txdb_wr (val);
break; break;
case MT_PAMACC: /* PAMACC (not impl) */ case MT_PAMACC: /* PAMACC (not impl) */
break; break;
case MT_PAMLOC: /* PAMLOC */ case MT_PAMLOC: /* PAMLOC */
pamloc = val & PAMLOC_ADDR; pamloc = val & PAMLOC_ADDR;
break; break;
case MT_MDCTL: /* MDCTL */ case MT_MDCTL: /* MDCTL */
mdctl = val & MDCTL_RW; mdctl = val & MDCTL_RW;
break; break;
case MT_EHSR: /* EHSR */ case MT_EHSR: /* EHSR */
ehsr = val & EHSR_VMSE; ehsr = val & EHSR_VMSE;
break; break;
case MT_CSWP: /* CSWP */ case MT_CSWP: /* CSWP */
cswp = val & 0xF; cswp = val & 0xF;
break; break;
case MT_MERG: /* MERG (not impl) */ case MT_MERG: /* MERG (not impl) */
break; break;
case MT_CRBT: /* CRBT (not impl) */ case MT_CRBT: /* CRBT (not impl) */
break; break;
case MT_STXCS: /* STXCS */ case MT_STXCS: /* STXCS */
stxcs_wr (val); stxcs_wr (val);
break; break;
case MT_STXDB: /* STXDB */ case MT_STXDB: /* STXDB */
stxdb_wr (val); stxdb_wr (val);
break; break;
default: default:
RSVD_OPND_FAULT; RSVD_OPND_FAULT;
} }
@ -613,7 +613,7 @@ return 0;
void WriteReg (int32 pa, int32 val, int32 lnt) void WriteReg (int32 pa, int32 val, int32 lnt)
{ {
if (ADDR_IS_SBIA (pa)) { /* SBI adapter space? */ if (ADDR_IS_SBIA (pa)) { /* SBI adapter space? */
sbia_wr (pa, val, lnt); sbia_wr (pa, val, lnt);
SET_IRQL; SET_IRQL;
return; return;
} }

96
VAX/vax860_sbia.c
View file

@ -134,42 +134,42 @@ DEVICE sbia_dev = {
int32 sbia_rd (int32 pa, int32 lnt) int32 sbia_rd (int32 pa, int32 lnt)
{ {
int32 rg = (pa >> 2) & 0x1F; int32 rg = (pa >> 2) & 0x1F;
switch (rg) { switch (rg) {
case 0: /* SBICNF */ case 0: /* SBICNF */
return 0x00400010; /* 8MB + SBIA Abus code */ return 0x00400010; /* 8MB + SBIA Abus code */
case 1: /* SBICSR */ case 1: /* SBICSR */
return sbi_csr; return sbi_csr;
case 2: /* SBIES (not impl) */ case 2: /* SBIES (not impl) */
case 3: /* SBIDCR (not impl) */ case 3: /* SBIDCR (not impl) */
case 4: /* DMAI CMD (not impl) */ case 4: /* DMAI CMD (not impl) */
case 5: /* DMAI ID (not impl) */ case 5: /* DMAI ID (not impl) */
case 6: /* DMAA CMD (not impl) */ case 6: /* DMAA CMD (not impl) */
case 7: /* DMAA ID (not impl) */ case 7: /* DMAA ID (not impl) */
case 8: /* DMAB CMD (not impl) */ case 8: /* DMAB CMD (not impl) */
case 9: /* DMAB ID (not impl) */ case 9: /* DMAB ID (not impl) */
case 0xa: /* DMAC CMD (not impl) */ case 0xa: /* DMAC CMD (not impl) */
case 0xb: /* DMAC ID (not impl) */ case 0xb: /* DMAC ID (not impl) */
case 0xc: /* SBIS (not impl) */ case 0xc: /* SBIS (not impl) */
return 0; return 0;
case 0xd: /* SBIER */ case 0xd: /* SBIER */
return sbi_er & SBIER_RD; return sbi_er & SBIER_RD;
case 0xe: /* SBITA */ case 0xe: /* SBITA */
return sbi_tmo; return sbi_tmo;
case 0xf: /* SBIFS */ case 0xf: /* SBIFS */
return sbi_fs & SBIFS_RD; return sbi_fs & SBIFS_RD;
case 0x10: /* SBISC */ case 0x10: /* SBISC */
return sbi_sc & SBISC_RD; return sbi_sc & SBISC_RD;
case 0x11: /* SBIMT */ case 0x11: /* SBIMT */
return sbi_mt & SBIMT_RD; return sbi_mt & SBIMT_RD;
default: /* Anything else is not impl */ default: /* Anything else is not impl */
return 0; return 0;
@ -179,31 +179,31 @@ int32 sbia_rd (int32 pa, int32 lnt)
void sbia_wr (int32 pa, int32 val, int32 lnt) void sbia_wr (int32 pa, int32 val, int32 lnt)
{ {
int32 rg = (pa >> 2) & 0x1F; int32 rg = (pa >> 2) & 0x1F;
switch (rg) { switch (rg) {
case 0: /* SBICNF */ case 0: /* SBICNF */
break; break;
case 1: /* SBICSR */ case 1: /* SBICSR */
printf ("sbi_csr wr: %08X\n", val); printf ("sbi_csr wr: %08X\n", val);
sbi_csr = sbi_csr & SBICSR_WR; sbi_csr = sbi_csr & SBICSR_WR;
break; break;
case 2: /* SBIES (not impl) */ case 2: /* SBIES (not impl) */
case 3: /* SBIDCR (not impl) */ case 3: /* SBIDCR (not impl) */
case 4: /* DMAI CMD (not impl) */ case 4: /* DMAI CMD (not impl) */
case 5: /* DMAI ID (not impl) */ case 5: /* DMAI ID (not impl) */
case 6: /* DMAA CMD (not impl) */ case 6: /* DMAA CMD (not impl) */
case 7: /* DMAA ID (not impl) */ case 7: /* DMAA ID (not impl) */
case 8: /* DMAB CMD (not impl) */ case 8: /* DMAB CMD (not impl) */
case 9: /* DMAB ID (not impl) */ case 9: /* DMAB ID (not impl) */
case 0xa: /* DMAC CMD (not impl) */ case 0xa: /* DMAC CMD (not impl) */
case 0xb: /* DMAC ID (not impl) */ case 0xb: /* DMAC ID (not impl) */
case 0xc: /* SBIS (not impl) */ case 0xc: /* SBIS (not impl) */
break; break;
case 0xd: /* SBIER */ case 0xd: /* SBIER */
sbi_er = (sbi_er & ~SBIER_WR) | (val & SBIER_WR); sbi_er = (sbi_er & ~SBIER_WR) | (val & SBIER_WR);
sbi_er = sbi_er & ~(val & SBIER_W1C); sbi_er = sbi_er & ~(val & SBIER_W1C);
if (val & SBIER_TMO) if (val & SBIER_TMO)
@ -215,22 +215,22 @@ void sbia_wr (int32 pa, int32 val, int32 lnt)
else crd_err = 0; else crd_err = 0;
break; break;
case 0xe: /* SBITA */ case 0xe: /* SBITA */
break; break;
case 0xf: /* SBIFS */ case 0xf: /* SBIFS */
sbi_fs = (sbi_fs & ~SBIFS_WR) | (val & SBIFS_WR); sbi_fs = (sbi_fs & ~SBIFS_WR) | (val & SBIFS_WR);
sbi_fs = sbi_fs & ~(val & SBIFS_W1C); sbi_fs = sbi_fs & ~(val & SBIFS_W1C);
break; break;
case 0x10: /* SBISC */ case 0x10: /* SBISC */
sbi_sc = (sbi_sc & ~(SBISC_LOCK|SBISC_WR)) | (val & SBISC_WR); sbi_sc = (sbi_sc & ~(SBISC_LOCK|SBISC_WR)) | (val & SBISC_WR);
break; break;
case 0x11: /* SBIMT */ case 0x11: /* SBIMT */
sbi_mt = (sbi_mt & ~SBIMT_WR) | (val & SBIMT_WR); sbi_mt = (sbi_mt & ~SBIMT_WR) | (val & SBIMT_WR);
break; break;
} }
return; return;
} }

42
VAX/vax860_stddev.c
View file

@ -189,7 +189,7 @@
#define RLDS_ATT (RLDS_HDO+RLDS_BHO+RLDS_LOCK) /* att status */ #define RLDS_ATT (RLDS_HDO+RLDS_BHO+RLDS_LOCK) /* att status */
#define RLDS_UNATT (RLDS_CVO+RLDS_LOAD) /* unatt status */ #define RLDS_UNATT (RLDS_CVO+RLDS_LOAD) /* unatt status */
#define RLDS_ERR (RLDS_WDE+RLDS_HCE+RLDS_STO+RLDS_SPE+RLDS_WGE+ \ #define RLDS_ERR (RLDS_WDE+RLDS_HCE+RLDS_STO+RLDS_SPE+RLDS_WGE+ \
RLDS_VCK+RLDS_DSE) /* errors bits */ RLDS_VCK+RLDS_DSE) /* errors bits */
int32 tti_csr = 0; /* control/status */ int32 tti_csr = 0; /* control/status */
int32 tti_buf = 0; /* buffer */ int32 tti_buf = 0; /* buffer */
@ -526,33 +526,33 @@ cso_csr = cso_csr & ~STXCS_STS;
switch (fnc) { switch (fnc) {
case RLFC_NOP: case RLFC_NOP:
break; break;
case RLFC_CONT: case RLFC_CONT:
rlcs_bcnt = 0; rlcs_bcnt = 0;
case RLFC_STS: case RLFC_STS:
rlcs_state = RL_STATUS; rlcs_state = RL_STATUS;
cso_csr = cso_csr & ~CSR_DONE; /* clear done */ cso_csr = cso_csr & ~CSR_DONE; /* clear done */
sim_activate (&rlcs_unit, rlcs_swait); sim_activate (&rlcs_unit, rlcs_swait);
break; break;
case RLFC_ABORT: case RLFC_ABORT:
rlcs_state = RL_ABORT; rlcs_state = RL_ABORT;
cso_csr = cso_csr & ~CSR_DONE; /* clear done */ cso_csr = cso_csr & ~CSR_DONE; /* clear done */
sim_activate (&rlcs_unit, rlcs_swait); sim_activate (&rlcs_unit, rlcs_swait);
break; break;
case RLFC_WRITE: case RLFC_WRITE:
rlcs_state = RL_WRITE; rlcs_state = RL_WRITE;
cso_csr = cso_csr & ~CSR_DONE; /* clear done */ cso_csr = cso_csr & ~CSR_DONE; /* clear done */
sim_activate (&rlcs_unit, rlcs_swait); sim_activate (&rlcs_unit, rlcs_swait);
break; break;
case RLFC_READ: case RLFC_READ:
rlcs_state = RL_READ; rlcs_state = RL_READ;
cso_csr = cso_csr & ~CSR_DONE; /* clear done */ cso_csr = cso_csr & ~CSR_DONE; /* clear done */
sim_activate (&rlcs_unit, rlcs_swait); sim_activate (&rlcs_unit, rlcs_swait);
break; break;
default: default:
printf ("CS: Unknown Command: %d\n", fnc); printf ("CS: Unknown Command: %d\n", fnc);
@ -1095,7 +1095,7 @@ switch (rlcs_state) {
case RL_IDLE: case RL_IDLE:
return SCPE_IERR; return SCPE_IERR;
case RL_READ: case RL_READ:
if ((cso_csr & CSR_DONE) == 0) { /* buf ready? */ if ((cso_csr & CSR_DONE) == 0) { /* buf ready? */
if (rlcs_bcnt == 0) { /* read in whole block */ if (rlcs_bcnt == 0) { /* read in whole block */
if ((uptr->flags & UNIT_ATT) == 0) { /* Attached? */ if ((uptr->flags & UNIT_ATT) == 0) { /* Attached? */
@ -1127,7 +1127,7 @@ switch (rlcs_state) {
break; break;
} }
sim_activate (uptr, rlcs_swait); /* schedule next */ sim_activate (uptr, rlcs_swait); /* schedule next */
break; break;
case RL_WRITE: case RL_WRITE:
if ((uptr->flags & UNIT_ATT) == 0) { /* Attached? */ if ((uptr->flags & UNIT_ATT) == 0) { /* Attached? */
@ -1156,21 +1156,21 @@ switch (rlcs_state) {
csi_int = 1; csi_int = 1;
break; break;
case RL_ABORT: case RL_ABORT:
if ((cso_csr & CSR_DONE) == 0) { /* buf ready? */ if ((cso_csr & CSR_DONE) == 0) { /* buf ready? */
cso_csr = cso_csr | CSR_DONE | /* aborted */ cso_csr = cso_csr | CSR_DONE | /* aborted */
(RLST_ABORT << STXCS_V_STS); (RLST_ABORT << STXCS_V_STS);
cso_buf = 0; cso_buf = 0;
rlcs_bcnt = 0; rlcs_bcnt = 0;
rlcs_state = RL_IDLE; rlcs_state = RL_IDLE;
if (cso_csr & CSR_IE) if (cso_csr & CSR_IE)
csi_int = 1; csi_int = 1;
break; break;
} }
sim_activate (uptr, rlcs_swait); /* schedule next */ sim_activate (uptr, rlcs_swait); /* schedule next */
break; break;
case RL_STATUS: case RL_STATUS:
if ((cso_csr & CSR_DONE) == 0) { /* buf ready? */ if ((cso_csr & CSR_DONE) == 0) { /* buf ready? */
switch (rlcs_sts_reg) { /* which register? */ switch (rlcs_sts_reg) { /* which register? */
@ -1194,14 +1194,14 @@ switch (rlcs_state) {
} }
cso_csr = cso_csr | CSR_DONE | /* returning status */ cso_csr = cso_csr | CSR_DONE | /* returning status */
(RLST_STS << STXCS_V_STS); (RLST_STS << STXCS_V_STS);
rlcs_state = RL_IDLE; rlcs_state = RL_IDLE;
if (cso_csr & CSR_IE) if (cso_csr & CSR_IE)
csi_int = 1; csi_int = 1;
break; break;
} }
sim_activate (uptr, rlcs_swait); /* schedule next */ sim_activate (uptr, rlcs_swait); /* schedule next */
break; break;
} }
return SCPE_OK; return SCPE_OK;
} }

10
VAX/vax860_syslist.c
View file

@ -72,7 +72,7 @@ DEVICE *sim_devices[] = {
&tmr_dev, &tmr_dev,
&tti_dev, &tti_dev,
&tto_dev, &tto_dev,
&rlcs_dev, &rlcs_dev,
&dz_dev, &dz_dev,
&vh_dev, &vh_dev,
&cr_dev, &cr_dev,
@ -90,10 +90,10 @@ DEVICE *sim_devices[] = {
&tq_dev, &tq_dev,
&xu_dev, &xu_dev,
&xub_dev, &xub_dev,
&dmc_dev[0], &dmc_dev[0],
&dmc_dev[1], &dmc_dev[1],
&dmc_dev[2], &dmc_dev[2],
&dmc_dev[3], &dmc_dev[3],
&dup_dev, &dup_dev,
NULL NULL
}; };

6
VAX/vax_cpu.c
View file

@ -1480,7 +1480,7 @@ for ( ;; ) {
default: default:
RSVD_ADDR_FAULT; /* end case idxspec */ RSVD_ADDR_FAULT; /* end case idxspec */
} }
switch (disp & (DR_ACMASK|DR_SPFLAG|DR_LNMASK)) { /* case acc+lnt */ switch (disp & (DR_ACMASK|DR_SPFLAG|DR_LNMASK)) { /* case acc+lnt */
case VB: case VB:
@ -2954,7 +2954,7 @@ for ( ;; ) {
if (op7 < 0) { if (op7 < 0) {
Read (op8, L_BYTE, WA); Read (op8, L_BYTE, WA);
Read ((op8 + 7) & LMASK, L_BYTE, WA); Read ((op8 + 7) & LMASK, L_BYTE, WA);
} }
if (op5 >= 0) if (op5 >= 0)
R[op5] = temp; R[op5] = temp;
else Write (op6, temp, L_LONG, WA); else Write (op6, temp, L_LONG, WA);
@ -2970,7 +2970,7 @@ for ( ;; ) {
if (op7 < 0) { if (op7 < 0) {
Read (op8, L_BYTE, WA); Read (op8, L_BYTE, WA);
Read ((op8 + 7) & LMASK, L_BYTE, WA); Read ((op8 + 7) & LMASK, L_BYTE, WA);
} }
if (op5 >= 0) if (op5 >= 0)
R[op5] = temp; R[op5] = temp;
else Write (op6, temp, L_LONG, WA); else Write (op6, temp, L_LONG, WA);

2
VAX/vax_io.c
View file

@ -387,7 +387,7 @@ if (lnt < L_LONG) {
int32 t = cqbic_rd (pa); int32 t = cqbic_rd (pa);
nval = ((val & mask) << sc) | (t & ~(mask << sc)); nval = ((val & mask) << sc) | (t & ~(mask << sc));
val = val << sc; val = val << sc;
} }
else nval = val; else nval = val;
switch (rg) { switch (rg) {

2
VAX/vax_sys.c
View file

@ -764,7 +764,7 @@ if ((sw & SWMASK ('A')) || (sw & SWMASK ('C'))) { /* char format? */
for (vp = lnt - 1; vp >= 0; vp--) { for (vp = lnt - 1; vp >= 0; vp--) {
c = (int32) val[vp] & 0x7F; c = (int32) val[vp] & 0x7F;
fprintf (of, (c < 0x20)? "<%02X>": "%c", c); fprintf (of, (c < 0x20)? "<%02X>": "%c", c);
} }
return -(lnt - 1); /* return # chars */ return -(lnt - 1); /* return # chars */
} }

4
VAX/vax_syscm.c
View file

@ -27,7 +27,7 @@
22-May-10 RMS Fixed t_addr printouts for 64b big-endian systems 22-May-10 RMS Fixed t_addr printouts for 64b big-endian systems
(Mark Pizzolato) (Mark Pizzolato)
12-Nov-06 RMS Fixed operand order in EIS instructions (W.F.J. Mueller) 12-Nov-06 RMS Fixed operand order in EIS instructions (W.F.J. Mueller)
27-Sep-05 RMS Fixed warnings compiling with 64b addresses 27-Sep-05 RMS Fixed warnings compiling with 64b addresses
15-Sep-04 RMS Cloned from pdp11_sys.c 15-Sep-04 RMS Cloned from pdp11_sys.c
*/ */
@ -686,6 +686,6 @@ if (*cptr != 0) return SCPE_ARG; /* junk at end? */
for (i = j = 0; i < 3; i++, j = j + 2) { for (i = j = 0; i < 3; i++, j = j + 2) {
bytes[j] = val[i] & BMASK; bytes[j] = val[i] & BMASK;
bytes[j + 1] = (val[i] >> 8) & BMASK; bytes[j + 1] = (val[i] >> 8) & BMASK;
} }
return ((2 * (n1 + n2)) - 1); return ((2 * (n1 + n2)) - 1);
} }

4
VAX/vax_watch.c
View file

@ -222,8 +222,8 @@ t_stat wtc_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr)
{ {
fprintf (st, "Watch Chip (WTC)\n\n"); fprintf (st, "Watch Chip (WTC)\n\n");
fprintf (st, "The WTC simulates the MC146818 watch chip. It recognizes the following options:\n\n"); fprintf (st, "The WTC simulates the MC146818 watch chip. It recognizes the following options:\n\n");
fprintf (st, " SET WTC TIME=STD standard time mode\n"); fprintf (st, " SET WTC TIME=STD standard time mode\n");
fprintf (st, " SET WTC TIME=VMS VMS time mode\n\n"); fprintf (st, " SET WTC TIME=VMS VMS time mode\n\n");
fprintf (st, "When running in standard mode the current year reported by the watch chip is\n"); fprintf (st, "When running in standard mode the current year reported by the watch chip is\n");
fprintf (st, "determined by the date/time of the host system. When running in VMS mode the\n"); fprintf (st, "determined by the date/time of the host system. When running in VMS mode the\n");
fprintf (st, "year is fixed at 1982, which is one of the conditions VMS expects in order to\n"); fprintf (st, "year is fixed at 1982, which is one of the conditions VMS expects in order to\n");

2
sim_defs.h
View file

@ -178,7 +178,7 @@ typedef unsigned long t_uint64;
#define t_uint64 unsigned long long #define t_uint64 unsigned long long
#endif /* end 64b */ #endif /* end 64b */
#ifndef INT64_C #ifndef INT64_C
#define INT64_C(x) x ## LL #define INT64_C(x) x ## LL
#endif #endif
#if defined (USE_INT64) /* 64b data */ #if defined (USE_INT64) /* 64b data */

10
sim_ether.c
View file

@ -1229,11 +1229,11 @@ int pcap_sendpacket(pcap_t* handle, const u_char* msg, int len)
#if defined(_WIN32) || defined(__CYGWIN__) #if defined(_WIN32) || defined(__CYGWIN__)
/* extracted from WinPcap's Packet32.h */ /* extracted from WinPcap's Packet32.h */
struct _PACKET_OID_DATA { struct _PACKET_OID_DATA {
uint32 Oid; ///< OID code. See the Microsoft DDK documentation or the file ntddndis.h uint32 Oid; ///< OID code. See the Microsoft DDK documentation or the file ntddndis.h
///< for a complete list of valid codes. ///< for a complete list of valid codes.
uint32 Length; ///< Length of the data field uint32 Length; ///< Length of the data field
uint8 Data[1]; ///< variable-lenght field that contains the information passed to or received uint8 Data[1]; ///< variable-lenght field that contains the information passed to or received
///< from the adapter. ///< from the adapter.
}; };
typedef struct _PACKET_OID_DATA PACKET_OID_DATA, *PPACKET_OID_DATA; typedef struct _PACKET_OID_DATA PACKET_OID_DATA, *PPACKET_OID_DATA;
typedef void **LPADAPTER; typedef void **LPADAPTER;

8
sim_fio.c
View file

@ -283,10 +283,10 @@ switch (whence) {
break; break;
case SEEK_END: case SEEK_END:
if (_fstati64 (_fileno (st), &statb)) if (_fstati64 (_fileno (st), &statb))
return (-1); return (-1);
fileaddr = statb.st_size + offset; fileaddr = statb.st_size + offset;
break; break;
case SEEK_CUR: case SEEK_CUR:
if (fgetpos (st, &fileaddr)) if (fgetpos (st, &fileaddr))
return (-1); return (-1);

2
sim_rev.h
View file

@ -238,7 +238,7 @@ patch date module(s) and fix(es)
pdp11_io.c: pdp11_io.c:
- fixed Qbus interrupts to treat all IO devices (except clock) as BR4 - fixed Qbus interrupts to treat all IO devices (except clock) as BR4
- fixed order of int_internal (Jordi Guillaumes i Pons) - fixed order of int_internal (Jordi Guillaumes i Pons)
ppd11_rf.c ppd11_rf.c
- fixed bug in updating mem addr extension (Peter Schorn) - fixed bug in updating mem addr extension (Peter Schorn)