PDP11: DH11 device.
This commit is contained in:
Lars Brinkhoff
parent
4daf07bfe2
commit
65410851d5
6 changed files with 366 additions and 3 deletions
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@ -633,6 +633,8 @@ typedef struct pdp_dib DIB;
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#define INT_V_UCB 25
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#define INT_V_CH 26
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#define INT_V_NG 27
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#define INT_V_DHRX 28
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#define INT_V_DHTX 29
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#define INT_V_PIR4 0 /* BR4 */
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#define INT_V_TTI 1
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@ -720,6 +722,8 @@ typedef struct pdp_dib DIB;
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#define INT_TDTX (1u << INT_V_TDTX)
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#define INT_CH (1u << INT_V_CH)
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#define INT_NG (1u << INT_V_NG)
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#define INT_DHRX (1u << INT_V_DHRX)
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#define INT_DHTX (1u << INT_V_DHTX)
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#define INT_INTERNAL7 (INT_PIR7)
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#define INT_INTERNAL6 (INT_PIR6 | INT_CLK)
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@ -762,6 +766,8 @@ typedef struct pdp_dib DIB;
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#define IPL_DUPTX 5
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#define IPL_UCA 5
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#define IPL_NG 5
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#define IPL_DHRX 5
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#define IPL_DHTX 5
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#define IPL_PTR 4
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#define IPL_PTP 4
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#define IPL_TTI 4
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350
PDP11/pdp11_dh.c
Normal file
350
PDP11/pdp11_dh.c
Normal file
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@ -0,0 +1,350 @@
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/* pdp11_dh.c: DH11, asynchronous serial line interface
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Copyright (c) 2022, Lars Brinkhoff
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the names of the authors shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from the authors.
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*/
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#include "pdp11_defs.h"
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#include "sim_tmxr.h"
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t_stat dh_rd(int32 *data, int32 PA, int32 access);
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t_stat dh_wr(int32 data, int32 PA, int32 access);
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t_stat dh_input_svc(UNIT *uptr);
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t_stat dh_output_svc(UNIT *uptr);
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t_stat dh_reset(DEVICE *dptr);
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t_stat dh_attach (UNIT *uptr, CONST char *cptr);
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t_stat dh_detach (UNIT *uptr);
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const char *dh_description (DEVICE *dptr);
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#define DH_LINES 16
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uint16 dh_scr; /* System Control Register */
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uint16 dh_nrcr; /* Next Received Character Register */
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uint16 dh_lpr[DH_LINES]; /* Line Parameter Regiser */
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uint32 dh_car[DH_LINES]; /* Current Address Register */
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uint16 dh_bcr[DH_LINES]; /* Byte Count Register */
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uint16 dh_bar; /* Buffer Active Register */
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uint16 dh_brcr; /* Break Control Register */
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uint16 dh_ssr; /* Silo Status Register */
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uint16 dh_silo[64];
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#define LN (dh_scr & 017)
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/* DHSCR bits */
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#define RIE 0000100
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#define RI 0000200
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#define CNXM 0000400
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#define MAINT 0001000
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#define NXM 0002000
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#define MCLR 0004000
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#define SIE 0010000
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#define OIE 0020000
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#define SI 0040000
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#define TI 0100000
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/* DHNRCR bits */
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#define DPR 0100000
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/* DHLPR bits */
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#define RSPEED 0001700
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#define TSPEED 0036000
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#define HFD 0040000
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#define ECHO 0100000
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TMLN dh_ldsc[DH_LINES] = { { 0 } };
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TMXR dh_desc = { DH_LINES, 0, 0, dh_ldsc };
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#define IOLN_DH 020
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DIB dh_dib = {
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IOBA_AUTO, IOLN_DH, &dh_rd, &dh_wr,
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2, IVCL (DHRX), 0, {NULL}, IOLN_DH
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};
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UNIT dh_unit[] = {
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{ UDATA (&dh_input_svc, UNIT_ATTABLE, 0) },
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{ UDATA (&dh_output_svc, UNIT_DIS, 0) }
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};
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REG dh_reg[] = {
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{ ORDATAD(DHSCR, dh_scr, 16, "System Control Register") },
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{ ORDATAD(DHNRCR, dh_nrcr, 16, "Next Received Character Register") },
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{ BRDATAD(DHLPR, dh_lpr, 8, 16, DH_LINES, "Line Parameter Regiser") },
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{ BRDATAD(DHCAR, dh_car, 8, 18, DH_LINES, "Current Address Register") },
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{ BRDATAD(DHBCR, dh_bcr, 8, 16, DH_LINES, "Byte Count Register") },
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{ ORDATAD(DHBAR, dh_bar, 16, "Buffer Active Register") },
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{ ORDATAD(DHBRCR, dh_brcr, 16, "Break Control Register") },
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{ ORDATAD(DHSSR, dh_ssr, 16, "Silo Status Register") },
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{ BRDATAD(DHSILO, dh_silo, 8, 16, 64, "Silo") },
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{ NULL }
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};
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MTAB dh_mod[] = {
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{ MTAB_XTD|MTAB_VDV|MTAB_VALR, 020, "ADDRESS", "ADDRESS",
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&set_addr, &show_addr, NULL, "Bus address" },
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{ MTAB_XTD|MTAB_VDV|MTAB_VALR, 0, "VECTOR", "VECTOR",
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&set_vec, &show_vec, NULL, "Interrupt vector" },
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{ MTAB_XTD|MTAB_VDV, 0, NULL, "AUTOCONFIGURE",
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&set_addr_flt, NULL, NULL, "Enable autoconfiguration of address & vector" },
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{ UNIT_ATT, UNIT_ATT, "summary", NULL,
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NULL, &tmxr_show_summ, (void *) &dh_desc, "Display a summary of line states" },
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{ MTAB_XTD|MTAB_VDV|MTAB_NMO, 1, "CONNECTIONS", NULL,
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NULL, &tmxr_show_cstat, (void *) &dh_desc, "Display current connections" },
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{ MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, "STATISTICS", NULL,
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NULL, &tmxr_show_cstat, (void *) &dh_desc, "Display multiplexer statistics" },
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{ MTAB_XTD|MTAB_VDV|MTAB_VALR, 1, NULL, "DISCONNECT",
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&tmxr_dscln, NULL, &dh_desc, "Disconnect a specific line" },
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{ 0 } };
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#define DBG_IO 0001
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DEBTAB dh_deb[] = {
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{ "IO", DBG_IO, "trace" },
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{ NULL, 0 }
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};
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DEVICE dh_dev = {
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"DH", dh_unit, dh_reg, dh_mod,
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2, 8, 16, 1, 8, 16,
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NULL, NULL, &dh_reset,
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NULL, &dh_attach, &dh_detach,
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&dh_dib, DEV_DIS | DEV_DISABLE | DEV_UBUS | DEV_DEBUG | DEV_MUX,
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0, dh_deb, NULL, NULL, NULL, NULL, NULL,
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&dh_description
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};
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t_stat
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dh_rd(int32 *data, int32 PA, int32 access)
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{
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t_stat stat = SCPE_OK;
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*data = 0;
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switch (PA & 017) {
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case 000:
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*data = dh_scr;
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sim_debug (DBG_IO, &dh_dev, "READ DHSCR %06o\n", *data);
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break;
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case 002:
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*data = dh_nrcr;
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dh_nrcr = 0;
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dh_scr &= ~RI;
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CLR_INT (DHRX);
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sim_activate_abs (&dh_unit[0], 0);
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sim_debug (DBG_IO, &dh_dev, "READ DHNRCR %06o\n", *data);
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break;
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case 004:
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*data = 0;
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sim_debug (DBG_IO, &dh_dev, "READ DHLPR[%o]\n", LN);
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break;
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case 006:
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*data = dh_car[LN];
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sim_debug (DBG_IO, &dh_dev, "READ DHCAR[%o] %06o\n", LN, *data);
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break;
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case 010:
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*data = dh_bcr[LN];
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sim_debug (DBG_IO, &dh_dev, "READ DHBCR[%o] %06o\n", LN, *data);
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break;
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case 012:
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*data = dh_bar;
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sim_debug (DBG_IO, &dh_dev, "READ DHBAR %06o\n", *data);
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break;
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case 014:
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*data = dh_brcr;
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sim_debug (DBG_IO, &dh_dev, "READ DHBRCR %06o\n", *data);
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break;
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case 016:
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dh_ssr &= ~0300;
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dh_ssr |= (dh_car[LN] >> 10) & 0300;
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*data = dh_ssr;
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sim_debug (DBG_IO, &dh_dev, "READ DHSSR %06o\n", *data);
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break;
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default:
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*data = 0;
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break;
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}
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return stat;
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}
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t_stat
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dh_wr(int32 data, int32 PA, int32 access)
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{
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t_stat stat = SCPE_OK;
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switch (PA & 017) {
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case 000:
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sim_debug (DBG_IO, &dh_dev, "WRITE DHSCR %06o\n", data);
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dh_scr = data;
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if (data & MCLR)
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dh_reset (&dh_dev);
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if (data & CNXM)
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data &= ~NXM;
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if (data & TI) {
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if (dh_scr & OIE)
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SET_INT (DHTX);
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} else {
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if (dh_bar != 0)
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sim_activate_abs (&dh_unit[1], 0);
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CLR_INT (DHTX);
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}
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break;
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case 002:
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sim_debug (DBG_IO, &dh_dev, "WRITE DHNRCR %06o\n", data);
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break;
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case 004:
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sim_debug (DBG_IO, &dh_dev, "WRITE DHLPR[%o] %06o\n", LN, data);
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dh_lpr[LN] = data;
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if (data & RSPEED)
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sim_activate_abs (&dh_unit[0], 0);
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break;
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case 006:
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sim_debug (DBG_IO, &dh_dev, "WRITE DHCAR[%o] %06o\n", LN, data);
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dh_car[LN] = data;
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dh_car[LN] |= ((uint32)dh_scr & 060) << 12;
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break;
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case 010:
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sim_debug (DBG_IO, &dh_dev, "WRITE DHBCR[%o] %06o\n", LN, data);
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dh_bcr[LN] = data;
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if (data == 0)
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sim_cancel (&dh_unit[1]);
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break;
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case 012:
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sim_debug (DBG_IO, &dh_dev, "WRITE DHBAR %06o\n", data);
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dh_bar = data;
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if (dh_bar == 0)
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sim_cancel (&dh_unit[1]);
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else
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sim_activate_abs (&dh_unit[1], 0);
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break;
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case 014:
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sim_debug (DBG_IO, &dh_dev, "WRITE DHBRCR %06o\n", data);
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dh_brcr = data;
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break;
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case 016:
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sim_debug (DBG_IO, &dh_dev, "WRITE DHSSR %06o\n", data);
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dh_ssr &= 077700;
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dh_ssr |= data & 0100077;
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break;
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default:
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break;
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}
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return stat;
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}
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t_stat dh_attach (UNIT *uptr, CONST char *cptr)
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{
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return tmxr_attach (&dh_desc, uptr, cptr);
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}
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t_stat dh_detach (UNIT *uptr)
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{
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return tmxr_detach (&dh_desc, uptr);
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}
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t_stat dh_input_svc(UNIT *uptr)
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{
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int32 ch;
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int i;
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sim_clock_coschedule (uptr, 100);
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i = tmxr_poll_conn (&dh_desc);
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if (i >= 0) {
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dh_ldsc[i].rcve = 1;
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dh_ldsc[i].xmte = 1;
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sim_debug(DBG_IO, &dh_dev, "Connect %d\n", i);
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}
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tmxr_poll_rx (&dh_desc);
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for (i = 0; i < DH_LINES; i++) {
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ch = tmxr_getc_ln (&dh_ldsc[i]);
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if (ch & TMXR_VALID) {
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ch &= (1 << ((dh_lpr[i] & 3) + 5)) - 1;
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dh_nrcr = ch | (i << 8) | DPR;
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dh_scr |= RI;
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if (dh_scr & RIE)
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SET_INT (DHRX);
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sim_debug(DBG_IO, &dh_dev, "Input character %03o line %d\n", ch, i);
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sim_cancel (&dh_unit[0]);
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break;
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}
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}
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return SCPE_OK;
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}
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t_stat dh_output_svc(UNIT *uptr)
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{
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int32 ch;
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int i;
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sim_clock_coschedule (uptr, 100);
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for (i = 0; i < DH_LINES; i++) {
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if ((dh_bar & (1 << i)) == 0)
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continue;
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if (dh_bcr[i] == 0)
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continue;
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ch = RdMemB (dh_car[i]);
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ch &= (1 << ((dh_lpr[i] & 3) + 5)) - 1;
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if (tmxr_putc_ln (&dh_ldsc[i], ch) != SCPE_STALL) {
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sim_debug(DBG_IO, &dh_dev, "Output character %03o line %d\n", ch, i);
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dh_car[i]++;
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dh_car[i] &= 0777777;
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dh_bcr[i]++;
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dh_bcr[i] &= 0177777;
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if (dh_bcr[i] == 0) {
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dh_bar &= ~(1 << i);
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dh_scr |= TI;
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if (dh_bar == 0)
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sim_cancel (uptr);
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if (dh_scr & OIE)
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SET_INT (DHTX);
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}
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}
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}
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tmxr_poll_tx (&dh_desc);
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return SCPE_OK;
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}
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t_stat dh_reset(DEVICE *dptr)
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{
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CLR_INT (DHRX);
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CLR_INT (DHTX);
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sim_cancel (&dh_unit[0]);
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sim_cancel (&dh_unit[1]);
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dh_scr = 0;
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dh_nrcr = 0;
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dh_bar = 0;
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dh_brcr = 0;
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dh_ssr = 0;
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memset (dh_lpr, 0, sizeof dh_lpr);
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memset (dh_car, 0, sizeof dh_car);
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memset (dh_bcr, 0, sizeof dh_bcr);
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return SCPE_OK;
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}
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const char *dh_description (DEVICE *dptr)
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{
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return "DH-11, asynchronous serial line interface";
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}
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@ -745,7 +745,7 @@ AUTO_CON auto_tab[] = {/*c #v am vm fxa fxv */
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016740, 016750, 016760, 016770} }, /* KL11/DL11/DLV11/TU58 - fx CSRs */
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{ { NULL }, 1, 2, 0, 8, { 0 } }, /* DLV11J - fx CSRs */
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{ { NULL }, 1, 2, 8, 8 }, /* DJ11 */
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{ { NULL }, 1, 2, 16, 8 }, /* DH11 */
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{ { "DH" }, 1, 2, 16, 8 }, /* DH11 */
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{ { "VT" }, 1, 4, 0, 8,
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{012000, 012010, 012020, 012030} }, /* VT11/GT40 - fx CSRs */
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{ { "VS60" }, 1, 4, 0, 8,
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@ -87,6 +87,7 @@ extern DEVICE dco_dev;
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extern DEVICE tdc_dev;
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extern DEVICE dz_dev;
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extern DEVICE vh_dev;
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extern DEVICE dh_dev;
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extern DEVICE dt_dev;
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extern DEVICE rc_dev;
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extern DEVICE rf_dev;
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@ -167,6 +168,7 @@ DEVICE *sim_devices[] = {
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&dco_dev,
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&dz_dev,
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&vh_dev,
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&dh_dev,
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&rc_dev,
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&rf_dev,
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&rk_dev,
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@ -227,6 +227,10 @@
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RelativePath="..\PDP11\pdp11_dc.c"
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>
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</File>
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<File
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RelativePath="..\PDP11\pdp11_dh.c"
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>
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</File>
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<File
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RelativePath="..\PDP11\pdp11_dl.c"
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>
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5
makefile
5
makefile
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@ -1440,8 +1440,9 @@ PDP11 = ${PDP11D}/pdp11_fp.c ${PDP11D}/pdp11_cpu.c ${PDP11D}/pdp11_dz.c \
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${PDP11D}/pdp11_ke.c ${PDP11D}/pdp11_dc.c ${PDP11D}/pdp11_dmc.c \
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${PDP11D}/pdp11_kmc.c ${PDP11D}/pdp11_dup.c ${PDP11D}/pdp11_rs.c \
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${PDP11D}/pdp11_vt.c ${PDP11D}/pdp11_td.c ${PDP11D}/pdp11_io_lib.c \
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${PDP11D}/pdp11_rom.c ${PDP11D}/pdp11_ch.c ${DISPLAYL} ${DISPLAYVT} \
|
||||
${PDP11D}/pdp11_ng.c ${PDP11D}/pdp11_daz.c ${DISPLAYNG}
|
||||
${PDP11D}/pdp11_rom.c ${PDP11D}/pdp11_ch.c ${PDP11D}/pdp11_dh.c \
|
||||
${PDP11D}/pdp11_ng.c ${PDP11D}/pdp11_daz.c \
|
||||
${DISPLAYL} ${DISPLAYNG} ${DISPLAYVT}
|
||||
PDP11_OPT = -DVM_PDP11 -I ${PDP11D} ${NETWORK_OPT} ${DISPLAY_OPT}
|
||||
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue