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PDP18B: Latest updates from Bob Supnik

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- Added unix v0 terminal support
- Added 3-cycle databreak set/show entries
- Revised for dynamically allocated memory
- Added support for -u modifier (UC15 and Unix v0)

These changes are to support the Unix v0 bringup and to implement a
"Unix input" mode on the console terminal.  In Unix mode, CR and LF are
swapped (so that a modern terminal can use 'enter' instead of CTRK-J to
create the newline Unix expects), escape is mapped to altmode (175),
upper and lower case are enabled and the parity bit is forced to 1.  This
most closely matches the characteristics of the KSR-37, but there is no
definitive evidence of the terminal that was actually used.
This commit is contained in:
Mark Pizzolato 2016-03-15 09:52:20 -07:00
parent f17c3535da
commit 6595ae52df
13 changed files with 129 additions and 75 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

44
PDP18B/pdp18b_cpu.c
View file

@ -1,6 +1,6 @@
/* pdp18b_cpu.c: 18b PDP CPU simulator
Copyright (c) 1993-2008, Robert M Supnik
Copyright (c) 1993-2016, Robert M Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
@ -25,6 +25,9 @@
cpu PDP-4/7/9/15 central processor
10-Mar-16 RMS Added 3-cycle databreak set/show routines
07-Mar-16 RMS Revised to allocate memory dynamically
28-Mar-15 RMS Revised to use sim_printf
28-Apr-07 RMS Removed clock initialization
26-Dec-06 RMS Fixed boundary test in KT15/XVM (Andrew Warkentin)
30-Oct-06 RMS Added idle and infinite loop detection
@ -330,7 +333,7 @@ typedef struct {
#define ASW_DFLT 017720
#endif
int32 M[MAXMEMSIZE] = { 0 }; /* memory */
int32 *M = NULL; /* memory */
int32 LAC = 0; /* link'AC */
int32 MQ = 0; /* MQ */
int32 PC = 0; /* PC */
@ -1550,7 +1553,7 @@ while (reason == 0) { /* loop until halted */
}
else if (pulse == 004) { /* ISA */
api_enb = (iot_data & SIGN)? 1: 0;
api_req = api_req | ((LAC >> 8) & 017);
api_req = api_req | ((LAC >> 8) & 017); /* swre levels only */
api_act = api_act | (LAC & 0377);
}
break;
@ -1643,7 +1646,7 @@ while (reason == 0) { /* loop until halted */
}
else if (pulse == 004) { /* ISA */
api_enb = (iot_data & SIGN)? 1: 0;
api_req = api_req | ((LAC >> 8) & 017);
api_req = api_req | ((LAC >> 8) & 017); /* swre levels only */
api_act = api_act | (LAC & 0377);
}
else if (pulse == 021) /* ENB */
@ -2096,6 +2099,10 @@ usmd = usmd_buf = usmd_defer = 0;
memm = memm_init;
nexm = prvn = trap_pending = 0;
emir_pending = rest_pending = 0;
if (M == NULL)
M = (int32 *) calloc (MEMSIZE, sizeof (int32));
if (M == NULL)
return SCPE_MEM;
pcq_r = find_reg ("PCQ", NULL, dptr);
if (pcq_r)
pcq_r->qptr = 0;
@ -2251,7 +2258,7 @@ for (i = 0; i < DEV_MAX; i++) { /* clr tables */
}
for (i = 0; i < ((uint32) sizeof (std_dev)); i++) /* std entries */
dev_tab[std_dev[i]] = &bad_dev;
for (i = p = 0; (dptr = sim_devices[i]) != NULL; i++) { /* add devices */
for (i = p = 0; (dptr = sim_devices[i]) != NULL; i++) { /* add devices */
dibp = (DIB *) dptr->ctxt; /* get DIB */
if (dibp && !(dptr->flags & DEV_DIS)) { /* enabled? */
if (dibp->iors) /* if IORS, add */
@ -2260,7 +2267,7 @@ for (i = p = 0; (dptr = sim_devices[i]) != NULL; i++) { /* add devices *
if (dibp->dsp[j]) { /* any dispatch? */
if (dev_tab[dibp->dev + j]) { /* already filled? */
sim_printf ("%s device number conflict at %02o\n",
sim_dname (dptr), dibp->dev + j);
sim_dname (dptr), dibp->dev + j);
return TRUE;
}
dev_tab[dibp->dev + j] = dibp->dsp[j]; /* fill */
@ -2271,6 +2278,31 @@ for (i = p = 0; (dptr = sim_devices[i]) != NULL; i++) { /* add devices *
return FALSE;
}
/* Set in memory 3-cycle databreak register */
t_stat set_3cyc_reg (UNIT *uptr, int32 val, char *cptr, void *desc)
{
t_stat r;
int32 newv;
if (cptr == NULL)
return SCPE_ARG;
newv = (int32) get_uint (cptr, 8, 0777777, &r);
if (r != SCPE_OK)
return SCPE_ARG;
M[val] = newv;
return SCPE_OK;
}
/* Show in-memory 3-cycle databreak register */
t_stat show_3cyc_reg (FILE *st, UNIT *uptr, int32 val, void *desc)
{
fprintf (st, "%s=", (char *) desc);
fprint_val (st, (t_value) M[val], 8, 18, PV_RZRO);
return SCPE_OK;
}
/* Set history */
t_stat cpu_set_hist (UNIT *uptr, int32 val, char *cptr, void *desc)

5
PDP18B/pdp18b_defs.h
View file

@ -23,6 +23,7 @@
used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Robert M Supnik.
10-Mar-16 RMS Added 3-cycle databreak set/show routines
26-Feb-16 RMS Added RB09 to PDP-7 for Unix "v0" and RM09 to PDP-9
13-Sep-15 RMS Added DR15C
18-Apr-12 RMS Added clk_cosched prototype
@ -108,6 +109,7 @@
TC59D magnetic tape
TC15/TU56 DECtape
LT15/LT19 additional Teletypes
DR15C parallel interface to UC15
??Indicates not implemented. The PDP-4 manual refers to a memory
??extension control; there is no documentation on it.
@ -164,7 +166,6 @@
#define MTA 0 /* magtape */
#define TC02 0 /* DECtape */
#define TTY1 16 /* second Teletype(s) */
#define DR 0 /* DR15C */
#define BRMASK 0377400 /* bounds mask */
#define BRMASK_XVM 0777400 /* bounds mask, XVM */
#endif
@ -520,5 +521,7 @@ typedef struct {
t_stat set_devno (UNIT *uptr, int32 val, char *cptr, void *desc);
t_stat show_devno (FILE *st, UNIT *uptr, int32 val, void *desc);
t_stat set_3cyc_reg (UNIT *uptr, int32 val, char *cptr, void *desc);
t_stat show_3cyc_reg (FILE *st, UNIT *uptr, int32 val, void *desc);
#endif

3
PDP18B/pdp18b_drm.c
View file

@ -25,6 +25,7 @@
drm (PDP-4,PDP-7) Type 24 serial drum; (PDP-9) RM09 drum
07-Mar-16 RMS Revised for dynamically allocated memory
26-Feb-16 RMS Added PDP-9 support; set default state to disabled
03-Sep-13 RMS Added explicit void * cast
14-Jan-04 RMS Revised IO device call interface
@ -64,7 +65,7 @@
#define GET_POS(x) ((int) fmod (sim_gtime() / ((double) (x)), \
((double) DRM_NUMWDT)))
extern int32 M[];
extern int32 *M;
extern int32 int_hwre[API_HLVL+1];
extern UNIT cpu_unit;

14
PDP18B/pdp18b_dt.c
View file

@ -1,6 +1,6 @@
/* pdp18b_dt.c: 18b DECtape simulator
Copyright (c) 1993-2015, Robert M Supnik
Copyright (c) 1993-2016, Robert M Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
@ -27,6 +27,8 @@
(PDP-9) TC02/TU55 DECtape
(PDP-15) TC15/TU56 DECtape
10-Mar-16 RMS Added 3-cycle databreak set/show entries
07-Mar-16 RMS Revised for dynamically allocated memory
13-Mar-15 RMS Added APIVEC register
28-Mar-15 RMS Revised to use sim_printf
23-Jun-06 RMS Fixed switch conflict in ATTACH
@ -327,7 +329,7 @@
#define ABS(x) (((x) < 0)? (-(x)): (x))
extern int32 M[];
extern int32 *M;
extern int32 int_hwre[API_HLVL+1];
extern int32 api_vec[API_HLVL][32];
extern UNIT cpu_unit;
@ -406,10 +408,6 @@ REG dt_reg[] = {
{ FLDATA (BEF, dtsb, DTB_V_BEF) },
#endif
{ FLDATA (ERF, dtsb, DTB_V_ERF) },
#if defined (TC02) /* TC02/TC15 */
{ ORDATA (WC, M[DT_WC], 18) },
{ ORDATA (CA, M[DT_CA], 18) },
#endif
{ DRDATA (LTIME, dt_ltime, 31), REG_NZ },
{ DRDATA (DCTIME, dt_dctime, 31), REG_NZ },
{ ORDATA (SUBSTATE, dt_substate, 2) },
@ -434,6 +432,10 @@ MTAB dt_mod[] = {
{ UNIT_8FMT + UNIT_11FMT, 0, "18b", NULL, NULL },
{ UNIT_8FMT + UNIT_11FMT, UNIT_8FMT, "12b", NULL, NULL },
{ UNIT_8FMT + UNIT_11FMT, UNIT_11FMT, "16b", NULL, NULL },
#if defined (TC02)
{ MTAB_XTD|MTAB_VDV|MTAB_NMO, DT_WC, "WC", "WC", &set_3cyc_reg, &show_3cyc_reg, "WC" },
{ MTAB_XTD|MTAB_VDV|MTAB_NMO, DT_CA, "CA", "CA", &set_3cyc_reg, &show_3cyc_reg, "CA" },
#endif
{ MTAB_XTD|MTAB_VDV, 0, "DEVNO", "DEVNO", &set_devno, &show_devno },
{ 0 }
};

5
PDP18B/pdp18b_fpp.c
View file

@ -1,6 +1,6 @@
/* pdp18b_fpp.c: FP15 floating point processor simulator
Copyright (c) 2003-2012, Robert M Supnik
Copyright (c) 2003-2016, Robert M Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
@ -25,6 +25,7 @@
fpp PDP-15 floating point processor
07-Mar-16 RMS Revised for dynamically allocated memory
19-Mar-12 RMS Fixed declaration of pc queue (Mark Pizzolato)
06-Jul-06 RMS Fixed bugs in left shift, multiply
31-Oct-04 RMS Fixed URFST to mask low 9b of fraction
@ -144,7 +145,7 @@ static UFP fma; /* FMA */
static UFP fmb; /* FMB */
static UFP fmq; /* FMQ - hi,lo only */
extern int32 M[MAXMEMSIZE];
extern int32 *M;
#if defined (PDP15)
extern int32 pcq[PCQ_SIZE]; /* PC queue */
#else

9
PDP18B/pdp18b_lp.c
View file

@ -1,6 +1,6 @@
/* pdp18b_lp.c: 18b PDP's line printer simulator
Copyright (c) 1993-2015, Robert M Supnik
Copyright (c) 1993-2016, Robert M Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
@ -28,6 +28,8 @@
lp09 (PDP-9,15) LP09 line printer
lp15 (PDP-15) LP15 line printer
10-Mar-16 RMS Added 3-cycle databreak set/show entry
07-Mar-16 RMS Revised for dynamically allocated memory
13-Sep-15 RMS Added APIVEC register
19-Jan-07 RMS Added UNIT_TEXT flag
11-Jun-06 RMS Made character translation table global scope
@ -666,7 +668,6 @@ return detach_unit (uptr);
/* LP15 line printer */
#define LP15_BSIZE 132 /* line size */
#define LPT_WC 034 /* word count */
#define LPT_CA 035 /* current addr */
/* Status register */
@ -681,7 +682,7 @@ return detach_unit (uptr);
#define STA_EFLGS (STA_ALM | STA_OVF | STA_IHT | STA_ILK)
#define STA_CLR 0003777 /* always clear */
extern int32 M[];
extern int32 *M;
int32 lp15_sta = 0;
int32 lp15_ie = 1;
int32 lp15_stopioe = 0;
@ -714,7 +715,6 @@ UNIT lp15_unit = {
REG lp15_reg[] = {
{ ORDATA (STA, lp15_sta, 18) },
{ ORDATA (CA, M[LPT_CA], 18) },
{ FLDATA (INT, int_hwre[API_LPT], INT_V_LPT) },
{ FLDATA (ENABLE, lp15_ie, 0) },
{ DRDATA (LCNT, lp15_lc, 9) },
@ -730,6 +730,7 @@ REG lp15_reg[] = {
};
MTAB lp15_mod[] = {
{ MTAB_XTD|MTAB_VDV|MTAB_NMO, LPT_CA, "CA", "CA", &set_3cyc_reg, &show_3cyc_reg, "CA" },
{ MTAB_XTD|MTAB_VDV, 0, "DEVNO", "DEVNO", &set_devno, &show_devno },
{ 0 }
};

12
PDP18B/pdp18b_mt.c
View file

@ -1,6 +1,6 @@
/* pdp18b_mt.c: 18b PDP magnetic tape simulator
Copyright (c) 1993-2015, Robert M Supnik
Copyright (c) 1993-2016, Robert M Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
@ -26,6 +26,8 @@
mt (PDP-9) TC59 magtape
(PDP-15) TC59D magtape
10-Mar-16 RMS Added 3-cycle databreak set/show entries
07-Mar-16 RMS Revised for dynamically allocated memory
13-Sep-15 RMS Added APIVEC register
14-Nov-08 RMS Replaced mt_log with standard debug facility
16-Feb-06 RMS Added tape capacity checking
@ -125,7 +127,7 @@
#define STA_DYN (STA_REW | STA_BOT | STA_EOF | STA_EOT)
/* kept in USTAT */
extern int32 M[];
extern int32 *M;
extern int32 int_hwre[API_HLVL+1];
extern int32 api_vec[API_HLVL][32];
extern UNIT cpu_unit;
@ -171,8 +173,6 @@ UNIT mt_unit[] = {
REG mt_reg[] = {
{ ORDATA (STA, mt_sta, 18) },
{ ORDATA (CMD, mt_cu, 18) },
{ ORDATA (WC, M[MT_WC], 18) },
{ ORDATA (CA, M[MT_CA], 18) },
{ FLDATA (INT, int_hwre[API_MTA], INT_V_MTA) },
{ FLDATA (STOP_IOE, mt_stopioe, 0) },
{ DRDATA (TIME, mt_time, 24), PV_LEFT },
@ -189,8 +189,10 @@ MTAB mt_mod[] = {
{ MTUF_WLK, MTUF_WLK, "write locked", "LOCKED", NULL },
{ MTAB_XTD|MTAB_VUN, 0, "FORMAT", "FORMAT",
&sim_tape_set_fmt, &sim_tape_show_fmt, NULL },
{ MTAB_XTD|MTAB_VUN, 0, "CAPACITY", "CAPACITY",
{ MTAB_XTD|MTAB_VUN, 0, "TCAPACITY", "TCAPACITY",
&sim_tape_set_capac, &sim_tape_show_capac, NULL },
{ MTAB_XTD|MTAB_VDV|MTAB_NMO, MT_WC, "WC", "WC", &set_3cyc_reg, &show_3cyc_reg, "WC" },
{ MTAB_XTD|MTAB_VDV|MTAB_NMO, MT_CA, "CA", "CA", &set_3cyc_reg, &show_3cyc_reg, "CA" },
{ MTAB_XTD|MTAB_VDV, 0, "DEVNO", "DEVNO",
&set_devno, &show_devno, NULL },
{ 0 }

5
PDP18B/pdp18b_rb.c
View file

@ -1,6 +1,6 @@
/* pdp18b_rb.c: RB09 fixed head disk simulator
Copyright (c) 2003-2013, Robert M Supnik
Copyright (c) 2003-2016, Robert M Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
@ -25,6 +25,7 @@
rb RB09 fixed head disk
07-Mar-16 RMS Revised for dynamically allocated memory
03-Sep-13 RMS Added explicit void * cast
14-Jan-04 RMS Revised IO device call interface
26-Oct-03 RMS Cleaned up buffer copy code
@ -77,7 +78,7 @@
#define GET_POS(x) ((int) fmod (sim_gtime () / ((double) (x)), \
((double) (RB_NUMSC * RB_NUMWD))))
extern int32 M[];
extern int32 *M;
extern int32 int_hwre[API_HLVL+1];
extern UNIT cpu_unit;

14
PDP18B/pdp18b_rf.c
View file

@ -1,6 +1,6 @@
/* pdp18b_rf.c: fixed head disk simulator
Copyright (c) 1993-2015, Robert M Supnik
Copyright (c) 1993-2016, Robert M Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
@ -26,6 +26,8 @@
rf (PDP-9) RF09/RF09
(PDP-15) RF15/RS09
10-Mar-16 RMS Added 3-cycle databreak set/show entries
07-Mar-16 RMS Revised for dynamically allocated memory
13-Sep-15 RMS Added APIVEC register
03-Sep-13 RMS Added explicit void * cast
04-Oct-06 RMS Fixed bug, DSCD does not clear function register
@ -109,7 +111,7 @@
((double) RF_NUMWD)))
#define RF_BUSY (sim_is_active (&rf_unit))
extern int32 M[];
extern int32 *M;
extern int32 int_hwre[API_HLVL+1];
extern int32 api_vec[API_HLVL][32];
extern UNIT cpu_unit;
@ -149,8 +151,6 @@ UNIT rf_unit = {
REG rf_reg[] = {
{ ORDATA (STA, rf_sta, 18) },
{ ORDATA (DA, rf_da, 22) },
{ ORDATA (WC, M[RF_WC], 18) },
{ ORDATA (CA, M[RF_CA], 18) },
{ ORDATA (BUF, rf_dbuf, 18) },
{ FLDATA (INT, int_hwre[API_RF], INT_V_RF) },
{ BRDATA (WLK, rf_wlk, 8, 16, RF_NUMDK) },
@ -173,6 +173,8 @@ MTAB rf_mod[] = {
{ UNIT_PLAT, (6 << UNIT_V_PLAT), NULL, "7P", &rf_set_size },
{ UNIT_PLAT, (7 << UNIT_V_PLAT), NULL, "8P", &rf_set_size },
{ UNIT_AUTO, UNIT_AUTO, "autosize", "AUTOSIZE", NULL },
{ MTAB_XTD|MTAB_VDV|MTAB_NMO, RF_WC, "WC", "WC", &set_3cyc_reg, &show_3cyc_reg, "WC" },
{ MTAB_XTD|MTAB_VDV|MTAB_NMO, RF_CA, "CA", "CA", &set_3cyc_reg, &show_3cyc_reg, "CA" },
{ MTAB_XTD|MTAB_VDV, 0, "DEVNO", "DEVNO", &set_devno, &show_devno },
{ 0 }
};
@ -314,9 +316,9 @@ return SCPE_OK;
/* Update status */
int32 rf_updsta (int32 new)
int32 rf_updsta (int32 news)
{
rf_sta = (rf_sta | new) & ~(RFS_ERR | RFS_CLR);
rf_sta = (rf_sta | news) & ~(RFS_ERR | RFS_CLR);
if (rf_sta & RFS_EFLGS)
rf_sta = rf_sta | RFS_ERR;
if ((rf_sta & (RFS_ERR | RFS_DON)) && (rf_sta & RFS_IE))

5
PDP18B/pdp18b_rp.c
View file

@ -1,6 +1,6 @@
/* pdp18b_rp.c: RP15/RP02 disk pack simulator
Copyright (c) 1993-2015, Robert M Supnik
Copyright (c) 1993-2016, Robert M Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
@ -25,6 +25,7 @@
rp RP15/RP02 disk pack
07-Mar-16 RMS Revised for dynamically allocated memory
13-Sep-15 RMS Added APIVEC register
14-Jan-04 RMS Revised IO device call interface
06-Feb-03 RMS Revised IOT decoding, fixed bug in initiation
@ -132,7 +133,7 @@
#define RP_MIN 2
#define MAX(x,y) (((x) > (y))? (x): (y))
extern int32 M[];
extern int32 *M;
extern int32 int_hwre[API_HLVL+1], nexm;
extern int32 api_vec[API_HLVL][32];
extern UNIT cpu_unit;

42
PDP18B/pdp18b_stddev.c
View file

@ -1,6 +1,6 @@
/* pdp18b_stddev.c: 18b PDP's standard devices
Copyright (c) 1993-2015, Robert M Supnik
Copyright (c) 1993-2016, Robert M Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
@ -29,6 +29,8 @@
tto teleprinter
clk clock
15-Mar-16 RMS Added unix v0 terminal support
07-Mar-16 RMS Revised for dynamically allocated memory
13-Sep-15 RMS Added APIVEC register to PTR, CLK only
28-Mar-15 RMS Revised to use sim_printf
18-Apr-12 RMS Added clk_cosched routine
@ -86,7 +88,7 @@
#define UNIT_V_PASCII (UNIT_V_UF + 0) /* punch ASCII */
#define UNIT_PASCII (1 << UNIT_V_PASCII)
extern int32 M[];
extern int32 *M;
extern int32 int_hwre[API_HLVL+1], PC, ASW;
extern int32 api_vec[API_HLVL][32];
extern UNIT cpu_unit;
@ -312,7 +314,9 @@ DEVICE ptp_dev = {
#define TTI_MASK ((1 << TTI_WIDTH) - 1)
#define TTUF_V_HDX (TTUF_V_UF + 0) /* half duplex */
#define TTUF_V_UNIX (TTUF_V_UF + 1)
#define TTUF_HDX (1 << TTUF_V_HDX)
#define TTUF_UNIX (1 << TTUF_V_UNIX)
DIB tti_dib = { DEV_TTI, 1, &tti_iors, { &tti } };
@ -335,10 +339,13 @@ REG tti_reg[] = {
MTAB tti_mod[] = {
#if !defined (KSR28)
{ TT_MODE, TT_MODE_KSR, "KSR", "KSR", &tty_set_mode },
{ TT_MODE, TT_MODE_7B, "7b", "7B", &tty_set_mode },
{ TT_MODE, TT_MODE_8B, "8b", "8B", &tty_set_mode },
{ TT_MODE, TT_MODE_7P, "7b", NULL, NULL },
{ TTUF_UNIX|TT_PAR|TT_MODE, TT_MODE_KSR, "KSR", "KSR", &tty_set_mode },
{ TTUF_UNIX|TT_PAR|TT_MODE, TT_MODE_7B, "7b", "7B", &tty_set_mode },
{ TTUF_UNIX|TT_PAR|TT_MODE, TT_MODE_8B, "8b", "8B", &tty_set_mode },
{ TTUF_UNIX|TT_PAR|TT_MODE, TT_MODE_7P, "7b", NULL, NULL },
#if !defined (PDP15)
{ TTUF_UNIX|TT_PAR|TT_MODE, TTUF_UNIX|TT_PAR_MARK|TT_MODE_7B, "Unix v0", "UNIX", &tty_set_mode },
#endif
#endif
{ TTUF_HDX, 0 , "full duplex", "FDX", NULL },
{ TTUF_HDX, TTUF_HDX, "half duplex", "HDX", NULL },
@ -390,10 +397,13 @@ REG tto_reg[] = {
MTAB tto_mod[] = {
#if !defined (KSR28)
{ TT_MODE, TT_MODE_KSR, "KSR", "KSR", &tty_set_mode },
{ TT_MODE, TT_MODE_7B, "7b", "7B", &tty_set_mode },
{ TT_MODE, TT_MODE_8B, "8b", "8B", &tty_set_mode },
{ TT_MODE, TT_MODE_7P, "7p", "7P", &tty_set_mode },
{ TTUF_UNIX|TT_PAR|TT_MODE, TT_MODE_KSR, "KSR", "KSR", &tty_set_mode },
{ TTUF_UNIX|TT_PAR|TT_MODE, TT_MODE_7B, "7b", "7B", &tty_set_mode },
{ TTUF_UNIX|TT_PAR|TT_MODE, TT_MODE_8B, "8b", "8B", &tty_set_mode },
{ TTUF_UNIX|TT_PAR|TT_MODE, TT_MODE_7P, "7p", "7P", &tty_set_mode },
#if !defined (PDP15)
{ TTUF_UNIX|TT_PAR|TT_MODE, TTUF_UNIX|TT_PAR_MARK|TT_MODE_7B, "Unix v0", "UNIX", &tty_set_mode },
#endif
#endif
{ MTAB_XTD|MTAB_VDV, 0, "DEVNO", NULL, NULL, &show_devno },
{ 0 }
@ -1050,6 +1060,14 @@ out = c & 0177; /* mask echo to 7b */
if (c & SCPE_BREAK) /* break? */
c = 0;
else c = sim_tt_inpcvt (c, TT_GET_MODE (uptr->flags) | TTUF_KSR);
if (uptr->flags & TTUF_UNIX) { /* unix v0? */
if (c == 0215) /* cr -> lf */
c = 0212;
else if (c == 0212) /* lf -> cr */
c = 0215;
else if (c == 0233) /* esc -> altmode */
c = 0375;
}
if ((uptr->flags & TTUF_HDX) && !tti_fdpx && out && /* half duplex and */
((out = sim_tt_outcvt (out, TT_GET_MODE (uptr->flags) | TTUF_KSR)) >= 0)) {
sim_putchar (out); /* echo */
@ -1156,7 +1174,7 @@ return SCPE_OK;
t_stat tty_set_mode (UNIT *uptr, int32 val, char *cptr, void *desc)
{
tti_unit.flags = (tti_unit.flags & ~TT_MODE) | val;
tto_unit.flags = (tto_unit.flags & ~TT_MODE) | val;
tti_unit.flags = (tti_unit.flags & ~(TTUF_UNIX|TT_PAR|TT_MODE)) | val;
tto_unit.flags = (tto_unit.flags & ~(TTUF_UNIX|TT_PAR|TT_MODE)) | val;
return SCPE_OK;
}

46
PDP18B/pdp18b_sys.c
View file

@ -23,7 +23,9 @@
used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Robert M Supnik.
26-Feb-15 RMS Added support for -u modifier (UC15 and Unix v0)
07-Mar-16 RMS Revised for dynamically allocated memory
03-Mar-16 RMS Added DR15C support
26-Feb-16 RMS Added support for -u modifier (UC15 and Unix v0)
13-Sep-15 RMS Added DR15C instructions
30-Oct-06 RMS Added infinite loop stop
18-Oct-06 RMS Re-ordered device list
@ -97,16 +99,17 @@ extern DEVICE mt_dev;
extern DEVICE tti1_dev, tto1_dev;
extern UNIT tti1_unit, tto1_unit;
#endif
#if defined (UC15)
extern DEVICE dr15_dev;
#endif
extern UNIT cpu_unit;
extern REG cpu_reg[];
extern int32 M[];
extern int32 *M;
extern int32 memm;
extern int32 PC;
extern const char asc_to_baud[128];
extern const char baud_to_asc[64];
extern const char fio_to_asc[64];
extern t_stat fprint_sym_cm_w (FILE *of, t_addr addr, t_value *val, int32 sw);
extern t_stat parse_sym_cm_w (char *cptr, t_addr addr, t_value *val, int32 sw);
/* SCP data structures and interface routines
@ -172,6 +175,9 @@ DEVICE *sim_devices[] = {
#endif
#if defined (TTY1)
&tti1_dev, &tto1_dev,
#endif
#if defined (UC15)
&dr15_dev,
#endif
NULL
};
@ -505,16 +511,16 @@ static const char *opcode[] = {
"DTCA", "DTRA", "DTXA", "DTLA",
"DTEF", "DTRB", "DTDF",
#endif
#if defined (DR) /* DR15C */
#if defined (TTY1)
"KSF1", "KRB1",
"TSF1", "TCF1", "TLS1", "TCF1!TLS1",
#endif
#if defined (UC15) /* DR15C */
"SIOA", "CIOD", "LIOR",
"RDRS", "LDRS",
"SAPI0", "SAPI1", "SAPI2", "SAPI3",
"CAPI0", "CAPI1", "CAPI2", "CAPI3",
#endif
#if defined (TTY1)
"KSF1", "KRB1",
"TSF1", "TCF1", "TLS1", "TCF1!TLS1",
#endif
#if defined (PDP7)
"ITON", "TTS", "SKP7", "CAF",
"SEM", "EEM", "EMIR", "LEM",
@ -748,9 +754,9 @@ static const int32 opc_val[] = {
0704101+I_NPI, 0704112+I_NPN,
0704001+I_NPI, 0704002+I_NPI, 0704004+I_NPI, 0704006+I_NPI,
#endif
#if defined (DR)
#if defined (UC15)
0706001+I_NPI, 0706002+I_NPI, 0706006+I_NPI,
0706112+I_NPI, 0706122+I_NPI,
0706112+I_NPN, 0706122+I_NPI,
0706101+I_NPI, 0706121+I_NPI, 0706141+I_NPI, 0706161+I_NPI,
0706104+I_NPI, 0706124+I_NPI, 0706144+I_NPI, 0706164+I_NPI,
#endif
@ -957,12 +963,8 @@ if ((sw & SWMASK ('A')) != 0) { /* ASCII? */
fprintf (of, FMTASC (inst & 0177));
return SCPE_OK;
}
#if defined (UC15)
if (dptr->dwidth == 16) /* 16b device? */
return fprint_sym_cm_w (of, addr, val, sw);
#endif
if (dptr->dwidth < 18) /* 18b device? */
if (dptr->dwidth < 18) /* 18b device? */
return SCPE_ARG;
if ((sw & SWMASK ('C')) != 0) { /* character? */
@ -1169,18 +1171,6 @@ if ((sw & SWMASK ('A')) || ((*cptr == '\'') && cptr++)) { /* ASCII char? */
val[0] = (t_value) cptr[0] | 0200;
return SCPE_OK;
}
#if defined (UC15)
if (dptr->dwidth == 16) { /* 16b decode? */
if ((sw & SWMASK ('C')) || ((*cptr == '"') && cptr++)) { /* char string? */
if (cptr[0] == 0) /* must have 1 char */
return SCPE_ARG;
val[0] = (((t_value) cptr[1] & 0377) << 8) |
((t_value) cptr[0] & 0377);
return SCPE_OK;
}
return fparse_sym_cm_w (of, addr, val, uptr, sw);
}
#endif
if (dptr->dwidth < 18) /* 18b decode? */
return SCPE_ARG; /* no, fail */

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