diff --git a/sigma/sigma_bugs.txt b/sigma/sigma_bugs.txt
index ddba4848..e3ca048f 100644
--- a/sigma/sigma_bugs.txt
+++ b/sigma/sigma_bugs.txt
@@ -120,6 +120,7 @@
 114: RAD: device address must include unit identifier everywhere, for interrupt generation.
 115. MT: error handling not consistent.
 116: IO: dangling else in write direct mode 1 code causes incorrect behavior.
+117: CPU: sim_interval is decremented before breakpoint test, which is incorrect.
 
 
 Diagnostic Notes
diff --git a/sigma/sigma_cpu.c b/sigma/sigma_cpu.c
index 71825163..179573bb 100644
--- a/sigma/sigma_cpu.c
+++ b/sigma/sigma_cpu.c
@@ -25,6 +25,8 @@
 
    cpu          central processor
 
+   12-Jul-22    RMS     Fix incorrect decrement on breakpoint (Ken Rector)
+
    The system state for the Sigma CPU is as follows:
 
    RF[0:15][0:31]<0:31> register blocks
@@ -476,6 +478,7 @@ while (reason == 0) {                                   /* loop until stop */
         if (sim_brk_summ &&
             sim_brk_test (PC, SWMASK ('E'))) {          /* breakpoint? */
             reason = STOP_IBKPT;                        /* stop simulation */
+            sim_interval++;                             /* undo decrement */
             break;
             }
         if (PSW_QRX9 && (PC & PSW1_XA))                 /* S9 real ext && ext? */