Added register definitions and logic to allow reasonable SAVE/RESTORE behavior.
This commit is contained in:
Mark Pizzolato
parent
f91256203c
commit
68b5433940
2 changed files with 93 additions and 9 deletions
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@ -173,7 +173,39 @@ MTAB xu_mod[] = {
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};
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REG xua_reg[] = {
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{ NULL } };
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{ GRDATA ( SA0, xua.mac[0], 16, 8, 0), REG_RO|REG_FIT},
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{ GRDATA ( SA1, xua.mac[1], 16, 8, 0), REG_RO|REG_FIT},
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{ GRDATA ( SA2, xua.mac[2], 16, 8, 0), REG_RO|REG_FIT},
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{ GRDATA ( SA3, xua.mac[3], 16, 8, 0), REG_RO|REG_FIT},
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{ GRDATA ( SA4, xua.mac[4], 16, 8, 0), REG_RO|REG_FIT},
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{ GRDATA ( SA5, xua.mac[5], 16, 8, 0), REG_RO|REG_FIT},
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{ GRDATA ( TYPE, xua.type, XU_RDX, 32, 0), REG_FIT },
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{ FLDATA ( INT, xua.irq, 0) },
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{ GRDATA ( IDTMR, xua.idtmr, XU_RDX, 32, 0), REG_HRO},
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{ BRDATA ( SETUP, &xua.setup, XU_RDX, 8, sizeof(xua.setup)), REG_HRO},
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{ BRDATA ( STATS, &xua.stats, XU_RDX, 8, sizeof(xua.stats)), REG_HRO},
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{ GRDATA ( CSR0, xua.pcsr0, XU_RDX, 16, 0), REG_FIT },
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{ GRDATA ( CSR1, xua.pcsr1, XU_RDX, 16, 0), REG_FIT },
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{ GRDATA ( CSR2, xua.pcsr2, XU_RDX, 16, 0), REG_FIT },
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{ GRDATA ( CSR3, xua.pcsr3, XU_RDX, 16, 0), REG_FIT },
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{ GRDATA ( MODE, xua.mode, XU_RDX, 32, 0), REG_FIT },
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{ GRDATA ( PCBB, xua.pcbb, XU_RDX, 32, 0), REG_FIT },
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{ GRDATA ( STAT, xua.stat, XU_RDX, 16, 0), REG_FIT },
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{ GRDATA ( TDRB, xua.tdrb, XU_RDX, 32, 0), REG_FIT },
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{ GRDATA ( TELEN, xua.telen, XU_RDX, 32, 0), REG_FIT },
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{ GRDATA ( TRLEN, xua.trlen, XU_RDX, 32, 0), REG_FIT },
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{ GRDATA ( TXNEXT, xua.txnext, XU_RDX, 32, 0), REG_FIT },
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{ GRDATA ( RDRB, xua.rdrb, XU_RDX, 32, 0), REG_FIT },
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{ GRDATA ( RELEN, xua.relen, XU_RDX, 32, 0), REG_FIT },
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{ GRDATA ( RRLEN, xua.rrlen, XU_RDX, 32, 0), REG_FIT },
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{ GRDATA ( RXNEXT, xua.rxnext, XU_RDX, 32, 0), REG_FIT },
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{ BRDATA ( PCB, xua.pcb, XU_RDX, 16, 4), REG_HRO},
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{ BRDATA ( UDB, xua.udb, XU_RDX, 16, UDBSIZE), REG_HRO},
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{ BRDATA ( RXHDR, xua.rxhdr, XU_RDX, 16, 4), REG_HRO},
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{ BRDATA ( TXHDR, xua.txhdr, XU_RDX, 16, 4), REG_HRO},
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{ GRDATA ( BA, xua_dib.ba, XU_RDX, 32, 0), REG_HRO},
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{ GRDATA ( VECTOR, xua_dib.vec, XU_RDX, 32, 0), REG_HRO},
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{ NULL } };
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DEBTAB xu_debug[] = {
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{"TRACE", DBG_TRC},
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@ -212,7 +244,39 @@ struct xu_device xub = {
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};
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REG xub_reg[] = {
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{ NULL } };
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{ GRDATA ( SA0, xub.mac[0], 16, 8, 0), REG_RO|REG_FIT},
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{ GRDATA ( SA1, xub.mac[1], 16, 8, 0), REG_RO|REG_FIT},
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{ GRDATA ( SA2, xub.mac[2], 16, 8, 0), REG_RO|REG_FIT},
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{ GRDATA ( SA3, xub.mac[3], 16, 8, 0), REG_RO|REG_FIT},
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{ GRDATA ( SA4, xub.mac[4], 16, 8, 0), REG_RO|REG_FIT},
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{ GRDATA ( SA5, xub.mac[5], 16, 8, 0), REG_RO|REG_FIT},
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{ GRDATA ( TYPE, xub.type, XU_RDX, 32, 0), REG_FIT },
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{ FLDATA ( INT, xub.irq, 0) },
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{ GRDATA ( IDTMR, xub.idtmr, XU_RDX, 32, 0), REG_HRO},
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{ BRDATA ( SETUP, &xub.setup, XU_RDX, 8, sizeof(xua.setup)), REG_HRO},
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{ BRDATA ( STATS, &xub.stats, XU_RDX, 8, sizeof(xua.stats)), REG_HRO},
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{ GRDATA ( CSR0, xub.pcsr0, XU_RDX, 16, 0), REG_FIT },
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{ GRDATA ( CSR1, xub.pcsr1, XU_RDX, 16, 0), REG_FIT },
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{ GRDATA ( CSR2, xub.pcsr2, XU_RDX, 16, 0), REG_FIT },
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{ GRDATA ( CSR3, xub.pcsr3, XU_RDX, 16, 0), REG_FIT },
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{ GRDATA ( MODE, xub.mode, XU_RDX, 32, 0), REG_FIT },
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{ GRDATA ( PCBB, xub.pcbb, XU_RDX, 32, 0), REG_FIT },
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{ GRDATA ( STAT, xub.stat, XU_RDX, 16, 0), REG_FIT },
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{ GRDATA ( TDRB, xub.tdrb, XU_RDX, 32, 0), REG_FIT },
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{ GRDATA ( TELEN, xub.telen, XU_RDX, 32, 0), REG_FIT },
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{ GRDATA ( TRLEN, xub.trlen, XU_RDX, 32, 0), REG_FIT },
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{ GRDATA ( TXNEXT, xub.txnext, XU_RDX, 32, 0), REG_FIT },
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{ GRDATA ( RDRB, xub.rdrb, XU_RDX, 32, 0), REG_FIT },
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{ GRDATA ( RELEN, xub.relen, XU_RDX, 32, 0), REG_FIT },
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{ GRDATA ( RRLEN, xub.rrlen, XU_RDX, 32, 0), REG_FIT },
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{ GRDATA ( RXNEXT, xub.rxnext, XU_RDX, 32, 0), REG_FIT },
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{ BRDATA ( PCB, xub.pcb, XU_RDX, 16, 4), REG_HRO},
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{ BRDATA ( UDB, xub.udb, XU_RDX, 16, UDBSIZE), REG_HRO},
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{ BRDATA ( RXHDR, xub.rxhdr, XU_RDX, 16, 4), REG_HRO},
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{ BRDATA ( TXHDR, xub.txhdr, XU_RDX, 16, 4), REG_HRO},
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{ GRDATA ( BA, xub_dib.ba, XU_RDX, 32, 0), REG_HRO},
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{ GRDATA ( VECTOR, xub_dib.vec, XU_RDX, 32, 0), REG_HRO},
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{ NULL } };
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DEVICE xub_dev = {
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"XUB", xub_unit, xub_reg, xu_mod,
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@ -795,6 +859,7 @@ int32 xu_command(CTLR* xu)
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/* get multicast list from host */
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rstatus = Map_ReadB(udbb, mtlen * 6, (uint8*) &xu->var->setup.macs[2]);
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if (rstatus == 0) {
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xu->var->setup.valid = 1;
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xu->var->setup.mac_count = mtlen + 2;
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eth_filter (xu->var->etherface, xu->var->setup.mac_count,
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xu->var->setup.macs, xu->var->setup.multicast,
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@ -1593,15 +1658,34 @@ t_stat xu_attach(UNIT* uptr, char* cptr)
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if (sim_log) fprintf (sim_log, "%s: MAC Address Conflict on LAN for address %s\n", xu->dev->name, buf);
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eth_close(xu->var->etherface);
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free(tptr);
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xu->var->etherface = 0;
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free(xu->var->etherface);
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xu->var->etherface = NULL;
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return SCPE_NOATT;
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}
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uptr->filename = tptr;
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uptr->flags |= UNIT_ATT;
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eth_setcrc(xu->var->etherface, 1); /* enable CRC */
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/* reset the device with the new attach info */
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xu_reset(xu->dev);
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/* init read queue (first time only) */
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status = ethq_init(&xu->var->ReadQ, XU_QUE_MAX);
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if (status != SCPE_OK) {
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eth_close(xu->var->etherface);
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free(tptr);
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free(xu->var->etherface);
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xu->var->etherface = NULL;
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return status;
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}
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if (xu->var->setup.valid) {
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int i, count = 0;
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ETH_MAC zeros = {0, 0, 0, 0, 0, 0};
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ETH_MAC filters[XU_FILTER_MAX + 1];
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for (i = 0; i < XU_FILTER_MAX; i++)
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if (memcmp(zeros, &xu->var->setup.macs[i], sizeof(ETH_MAC)))
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memcpy (filters[count++], xu->var->setup.macs[i], sizeof(ETH_MAC));
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eth_filter (xu->var->etherface, count, filters, xu->var->setup.multicast, xu->var->setup.promiscuous);
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}
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return SCPE_OK;
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}
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@ -53,8 +53,8 @@ extern int32 int_req;
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#elif defined (VM_VAX) /* VAX version */
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#include "vax_defs.h"
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#define XU_RDX 8
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#define XU_WID 16
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#define XU_RDX 16
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#define XU_WID 32
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extern int32 int_req[IPL_HLVL];
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#else /* PDP-11 version */
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@ -75,6 +75,7 @@ extern int32 int_req[IPL_HLVL];
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enum xu_type {XU_T_DEUNA, XU_T_DELUA};
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struct xu_setup {
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int valid; /* is the setup block valid? */
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int promiscuous; /* promiscuous mode enabled */
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int multicast; /* enable all multicast addresses */
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int mac_count; /* number of multicast mac addresses */
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@ -129,7 +130,6 @@ struct xu_device {
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ETH_QUE ReadQ;
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ETH_MAC load_server; /* load server address */
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int idtmr; /* countdown for ID Timer */
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int sectmr; /* countup for one second timer */
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struct xu_setup setup;
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struct xu_stats stats; /* reportable network statistics */
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@ -140,7 +140,7 @@ struct xu_device {
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uint16 pcsr3;
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uint32 mode; /* mode register */
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uint32 pcbb; /* port command block base */
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uint32 stat; /* extended port status */
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uint16 stat; /* extended port status */
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uint32 tdrb; /* transmit desc ring base */
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uint32 telen; /* transmit desc ring entry len */
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