Added calls to sim_register_clock_unit for simulators with clock devices
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115f8608c3
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15 changed files with 15 additions and 0 deletions
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@ -419,6 +419,7 @@ return SCPE_OK;
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t_stat rtc_reset (DEVICE *dptr)
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{
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sim_register_clock_unit (&rtc_unit); /* declare clock unit */
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dev_done = dev_done & ~INT_RTC; /* clear ready */
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sim_cancel (&rtc_unit); /* stop clock */
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return SCPE_OK;
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@ -881,6 +881,7 @@ return SCPE_OK;
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t_stat clk_reset (DEVICE *dptr)
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{
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sim_register_clock_unit (&clk_unit); /* declare clock unit */
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CLR_INT (INT_CLK); /* clear ready, enb */
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CLR_ENB (INT_CLK);
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sim_cancel (&clk_unit); /* deactivate unit */
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@ -126,6 +126,7 @@ return d1;
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t_stat clk_reset (DEVICE *dptr)
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{
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sim_register_clock_unit (&clk_unit); /* declare clock unit */
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chtr_clk = 0;
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if (clk_dev.flags & DEV_DIS)
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sim_cancel (&clk_unit);
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@ -153,6 +153,7 @@ return SCPE_OK;
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t_stat clk_reset (DEVICE *dptr)
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{
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sim_register_clock_unit (&clk_unit); /* declare clock unit */
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clk_sel = 0;
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DEV_CLR_BUSY( INT_CLK ) ;
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DEV_CLR_DONE( INT_CLK ) ;
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@ -118,6 +118,7 @@ t_stat clk_reset (DEVICE *dptr)
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{
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if (clk_dev.flags & DEV_DIS) sim_cancel (&clk_unit); /* disabled? */
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else {
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sim_register_clock_unit (&clk_unit); /* declare clock unit */
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tmxr_poll = sim_rtcn_init (clk_unit.wait, TMR_CLK);
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sim_activate_abs (&clk_unit, tmxr_poll); /* activate unit */
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}
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@ -224,6 +224,7 @@ return;
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t_stat tim_reset (DEVICE *dptr)
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{
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sim_register_clock_unit (&tim_unit); /* declare clock unit */
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tim_period = 0; /* clear timer */
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tim_ttg = 0;
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apr_flg = apr_flg & ~APRF_TIM; /* clear interrupt */
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@ -463,6 +463,7 @@ return clk_dib.vec;
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t_stat clk_reset (DEVICE *dptr)
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{
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sim_register_clock_unit (&clk_unit); /* declare clock unit */
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if (CPUT (HAS_LTCR)) /* reg there? */
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clk_fie = clk_fnxm = 0;
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else clk_fie = clk_fnxm = 1; /* no, BEVENT */
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@ -483,6 +483,7 @@ t_stat clk_reset (DEVICE *dptr)
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{
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int32 t;
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sim_register_clock_unit (&clk_unit); /* declare clock unit */
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CLR_INT (CLK); /* clear flag */
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if (!sim_is_running) { /* RESET (not CAF)? */
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t = sim_rtc_init (clk_unit.wait); /* init calibration */
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@ -157,6 +157,7 @@ t_stat clk_reset (DEVICE *dptr)
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{
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int32 t;
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sim_register_clock_unit (&clk_unit); /* declare clock unit */
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dev_done = dev_done & ~INT_CLK; /* clear done, int */
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int_req = int_req & ~INT_CLK;
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int_enable = int_enable & ~INT_CLK; /* clear enable */
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@ -412,6 +412,7 @@ t_stat clk_reset (DEVICE *dptr)
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{
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int32 t;
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sim_register_clock_unit (&clk_unit); /* declare clock unit */
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clk_csr = 0;
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CLR_INT (CLK);
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t = sim_rtcn_init (clk_unit.wait, TMR_CLK); /* init timer */
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@ -348,6 +348,7 @@ t_stat clk_reset (DEVICE *dptr)
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{
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int32 t;
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sim_register_clock_unit (&clk_unit); /* declare clock unit */
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clk_csr = 0;
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CLR_INT (CLK);
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t = sim_rtcn_init (clk_unit.wait, TMR_CLK); /* init timer */
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@ -858,6 +858,7 @@ return;
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t_stat clk_reset (DEVICE *dptr)
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{
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sim_register_clock_unit (&clk_unit); /* declare clock unit */
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tmr_poll = sim_rtcn_init (clk_unit.wait, TMR_CLK); /* init 100Hz timer */
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sim_activate_abs (&clk_unit, tmr_poll); /* activate 100Hz unit */
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tmxr_poll = tmr_poll * TMXR_MULT; /* set mux poll */
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@ -854,6 +854,7 @@ return;
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t_stat clk_reset (DEVICE *dptr)
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{
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sim_register_clock_unit (&clk_unit); /* declare clock unit */
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tmr_poll = sim_rtcn_init (clk_unit.wait, TMR_CLK); /* init 100Hz timer */
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sim_activate_abs (&clk_unit, tmr_poll); /* activate 100Hz unit */
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tmxr_poll = tmr_poll * TMXR_MULT; /* set mux poll */
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@ -672,6 +672,7 @@ return;
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t_stat clk_reset (DEVICE *dptr)
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{
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sim_register_clock_unit (&clk_unit); /* declare clock unit */
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tmr_poll = sim_rtcn_init (clk_unit.wait, TMR_CLK); /* init 100Hz timer */
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sim_activate (&clk_unit, tmr_poll); /* activate 100Hz unit */
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tmxr_poll = tmr_poll * TMXR_MULT; /* set mux poll */
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@ -809,6 +809,7 @@ return;
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t_stat clk_reset (DEVICE *dptr)
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{
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sim_register_clock_unit (&clk_unit); /* declare clock unit */
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tmr_poll = sim_rtcn_init (clk_unit.wait, TMR_CLK); /* init 100Hz timer */
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sim_activate (&clk_unit, tmr_poll); /* activate 100Hz unit */
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tmxr_poll = tmr_poll * TMXR_MULT; /* set mux poll */
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