From 75901333e541c6607029f13c4e81ff5b95189ad5 Mon Sep 17 00:00:00 2001 From: Mark Pizzolato Date: Thu, 29 Dec 2016 06:05:53 -0800 Subject: [PATCH] VAX780, VAX730, VAX750, VAX8600: Moved the TPS register to the TMR device Clock ticks for these simulatrs are performed by programmatic setup of the interval timer device (TMR) and have nothing to do with the TODR which increments at 100Hz, but doesn't generate ticks to the simulated system. --- VAX/vax730_stddev.c | 4 ++-- VAX/vax750_stddev.c | 4 ++-- VAX/vax780_stddev.c | 4 ++-- VAX/vax860_stddev.c | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/VAX/vax730_stddev.c b/VAX/vax730_stddev.c index eb94eebb..42370719 100644 --- a/VAX/vax730_stddev.c +++ b/VAX/vax730_stddev.c @@ -298,7 +298,6 @@ UNIT clk_unit = { UDATA (NULL, UNIT_IDLE+UNIT_FIX, sizeof(TOY))}; REG clk_reg[] = { { DRDATAD (TIME, clk_unit.wait, 24, "initial poll interval"), REG_NZ + PV_LEFT }, { DRDATAD (POLL, tmr_poll, 24, "calibrated poll interval"), REG_NZ + PV_LEFT + REG_HRO }, - { DRDATAD (TPS, clk_tps, 8, "ticks per second (100)"), REG_NZ + PV_LEFT }, #if defined (SIM_ASYNCH_IO) { DRDATAD (ASYNCH, sim_asynch_enabled, 1, "asynch I/O enabled flag"), PV_LEFT }, { DRDATAD (LATENCY, sim_asynch_latency, 32, "desired asynch interrupt latency"), PV_LEFT }, @@ -323,6 +322,7 @@ REG tmr_reg[] = { { HRDATAD (ICR, tmr_icr, 32, "interval count register") }, { HRDATAD (NICR, tmr_nicr, 32, "next interval count register") }, { FLDATAD (INT, tmr_int, 0, "interrupt request") }, + { DRDATAD (TPS, clk_tps, 8, "ticks per second (100)"), REG_NZ + PV_LEFT }, { HRDATA (INCR, tmr_inc, 32), REG_HIDDEN }, { HRDATA (SAVE, tmr_sav, 32), REG_HIDDEN }, { NULL } @@ -337,7 +337,7 @@ REG tmr_reg[] = { DEBTAB tmr_deb[] = { { "REG", TMR_DB_REG, "Register Access"}, { "TICK", TMR_DB_TICK, "Ticks"}, - { "SCHED", TMR_DB_SCHED, "Ticks"}, + { "SCHED", TMR_DB_SCHED, "Scheduling"}, { "INT", TMR_DB_INT, "Interrupts"}, { "TODR", TMR_DB_TODR, "TODR activities"}, { NULL, 0 } diff --git a/VAX/vax750_stddev.c b/VAX/vax750_stddev.c index 47afa3fd..03e3f75a 100644 --- a/VAX/vax750_stddev.c +++ b/VAX/vax750_stddev.c @@ -291,7 +291,6 @@ UNIT clk_unit = { UDATA (NULL, UNIT_IDLE+UNIT_FIX, sizeof(TOY))}; REG clk_reg[] = { { DRDATAD (TIME, clk_unit.wait, 24, "initial poll interval"), REG_NZ + PV_LEFT }, { DRDATAD (POLL, tmr_poll, 24, "calibrated poll interval"), REG_NZ + PV_LEFT + REG_HRO }, - { DRDATAD (TPS, clk_tps, 8, "ticks per second"), REG_NZ + PV_LEFT }, #if defined (SIM_ASYNCH_IO) { DRDATAD (ASYNCH, sim_asynch_enabled, 1, "asynch I/O enabled flag"), PV_LEFT }, { DRDATAD (LATENCY, sim_asynch_latency, 32, "desired asynch interrupt latency"), PV_LEFT }, @@ -316,6 +315,7 @@ REG tmr_reg[] = { { HRDATAD (ICR, tmr_icr, 32, "interval count register") }, { HRDATAD (NICR, tmr_nicr, 32, "next interval count register") }, { FLDATAD (INT, tmr_int, 0, "interrupt request") }, + { DRDATAD (TPS, clk_tps, 8, "ticks per second"), REG_NZ + PV_LEFT }, { HRDATA (INCR, tmr_inc, 32), REG_HIDDEN }, { HRDATA (SAVE, tmr_sav, 32), REG_HIDDEN }, { NULL } @@ -330,7 +330,7 @@ REG tmr_reg[] = { DEBTAB tmr_deb[] = { { "REG", TMR_DB_REG, "Register Access"}, { "TICK", TMR_DB_TICK, "Ticks"}, - { "SCHED", TMR_DB_SCHED, "Ticks"}, + { "SCHED", TMR_DB_SCHED, "Scheduling"}, { "INT", TMR_DB_INT, "Interrupts"}, { "TODR", TMR_DB_TODR, "TODR activities"}, { NULL, 0 } diff --git a/VAX/vax780_stddev.c b/VAX/vax780_stddev.c index 28cbbf05..53bb9c9f 100644 --- a/VAX/vax780_stddev.c +++ b/VAX/vax780_stddev.c @@ -338,7 +338,6 @@ UNIT clk_unit = { UDATA (NULL, UNIT_FIX, sizeof(TOY))}; REG clk_reg[] = { { DRDATAD (TIME, clk_unit.wait, 24, "initial poll interval"), REG_NZ + PV_LEFT }, { DRDATAD (POLL, tmr_poll, 24, "calibrated poll interval"), REG_NZ + PV_LEFT + REG_HRO }, - { DRDATAD (TPS, clk_tps, 8, "ticks per second"), REG_NZ + PV_LEFT }, #if defined (SIM_ASYNCH_IO) { DRDATAD (ASYNCH, sim_asynch_enabled, 1, "asynch I/O enabled flag"), PV_LEFT }, { DRDATAD (LATENCY, sim_asynch_latency, 32, "desired asynch interrupt latency"), PV_LEFT }, @@ -363,6 +362,7 @@ REG tmr_reg[] = { { HRDATAD (ICR, tmr_icr, 32, "interval count register") }, { HRDATAD (NICR, tmr_nicr, 32, "next interval count register") }, { FLDATAD (INT, tmr_int, 0, "interrupt request") }, + { DRDATAD (TPS, clk_tps, 8, "ticks per second"), REG_NZ + PV_LEFT }, { HRDATA (INCR, tmr_inc, 32), REG_HIDDEN }, { HRDATA (SAVE, tmr_sav, 32), REG_HIDDEN }, { NULL } @@ -377,7 +377,7 @@ REG tmr_reg[] = { DEBTAB tmr_deb[] = { { "REG", TMR_DB_REG, "Register Access"}, { "TICK", TMR_DB_TICK, "Ticks"}, - { "SCHED", TMR_DB_SCHED, "Ticks"}, + { "SCHED", TMR_DB_SCHED, "Scheduling"}, { "INT", TMR_DB_INT, "Interrupts"}, { "TODR", TMR_DB_TODR, "TODR activities"}, { NULL, 0 } diff --git a/VAX/vax860_stddev.c b/VAX/vax860_stddev.c index 20ae179f..0b35f14e 100644 --- a/VAX/vax860_stddev.c +++ b/VAX/vax860_stddev.c @@ -363,7 +363,6 @@ UNIT clk_unit = { UDATA (NULL, UNIT_FIX, sizeof(TOY))}; REG clk_reg[] = { { DRDATAD (TIME, clk_unit.wait, 24, "initial poll interval"), REG_NZ + PV_LEFT }, { DRDATAD (POLL, tmr_poll, 24, "calibrated poll interval"), REG_NZ + PV_LEFT + REG_HRO }, - { DRDATAD (TPS, clk_tps, 8, "ticks per second"), REG_NZ + PV_LEFT }, #if defined (SIM_ASYNCH_IO) { DRDATAD (ASYNCH, sim_asynch_enabled, 1, "asynch I/O enabled flag"), PV_LEFT }, { DRDATAD (LATENCY, sim_asynch_latency, 32, "desired asynch interrupt latency"), PV_LEFT }, @@ -388,6 +387,7 @@ REG tmr_reg[] = { { HRDATAD (ICR, tmr_icr, 32, "interval count register") }, { HRDATAD (NICR, tmr_nicr, 32, "next interval count register") }, { FLDATAD (INT, tmr_int, 0, "interrupt request") }, + { DRDATAD (TPS, clk_tps, 8, "ticks per second"), REG_NZ + PV_LEFT }, { HRDATA (INCR, tmr_inc, 32), REG_HIDDEN }, { HRDATA (SAVE, tmr_sav, 32), REG_HIDDEN }, { NULL } @@ -402,7 +402,7 @@ REG tmr_reg[] = { DEBTAB tmr_deb[] = { { "REG", TMR_DB_REG, "Register Access"}, { "TICK", TMR_DB_TICK, "Ticks"}, - { "SCHED", TMR_DB_SCHED, "Ticks"}, + { "SCHED", TMR_DB_SCHED, "Scheduling"}, { "INT", TMR_DB_INT, "Interrupts"}, { "TODR", TMR_DB_TODR, "TODR activities"}, { NULL, 0 }