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I7000: Updated register definitions.

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Mark Pizzolato 2020-03-02 09:08:13 -05:00 • committed by Richard Cornwell
parent 74d61d2d87
commit 7757ecada3
1 changed files with 37 additions and 26 deletions
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63
I7000/i7080_cpu.c
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@ -246,22 +246,24 @@ UNIT cpu_unit =
REG cpu_reg[] = { REG cpu_reg[] = {
{DRDATAD(IC, IC, 32, "Instruction register")}, {DRDATAD(IC, IC, 32, "Instruction register")},
{"A", &AC, 8, 8, 0, 256, "A Register", NULL, REG_VMIO|REG_CIRC, 0, }, {BRDATAD(ADATA, &AC, 8, 8, sizeof(AC), "All Possible Register Data"), REG_HRO },
{"ASU1", &AC[256], 8, 8, 256, 16, "ASU1 Register", NULL, REG_VMIO|REG_CIRC, 0}, {BRDATAD(A, &AC[0], 8, 8, 256, "A Register"), REG_VMIO|REG_CIRC },
{"ASU2", &AC[256], 8, 8, 256, 16, "ASU2 Register", NULL, REG_VMIO|REG_CIRC, 0}, {BRDATAD(B, &AC[256], 8, 8, 256, "B Register"), REG_VMIO|REG_CIRC },
{"ASU3", &AC[256], 8, 8, 256, 16, "ASU3 Register", NULL, REG_VMIO|REG_CIRC, 0}, {BRDATAD(ASU1, &AC[256], 8, 8, 16, "ASU1 Register"), REG_VMIO|REG_CIRC},
{"ASU4", &AC[256], 8, 8, 256, 16, "ASU4 Register", NULL, REG_VMIO|REG_CIRC, 0}, {BRDATAD(ASU2, &AC[272], 8, 8, 16, "ASU2 Register"), REG_VMIO|REG_CIRC},
{"ASU5", &AC[256], 8, 8, 256, 16, "ASU5 Register", NULL, REG_VMIO|REG_CIRC, 0}, {BRDATAD(ASU3, &AC[288], 8, 8, 16, "ASU3 Register"), REG_VMIO|REG_CIRC},
{"ASU6", &AC[256], 8, 8, 256, 16, "ASU6 Register", NULL, REG_VMIO|REG_CIRC, 0}, {BRDATAD(ASU4, &AC[304], 8, 8, 16, "ASU4 Register"), REG_VMIO|REG_CIRC},
{"ASU7", &AC[256], 8, 8, 256, 16, "ASU7 Register", NULL, REG_VMIO|REG_CIRC, 0}, {BRDATAD(ASU5, &AC[320], 8, 8, 16, "ASU5 Register"), REG_VMIO|REG_CIRC},
{"ASU8", &AC[256], 8, 8, 256, 16, "ASU8 Register", NULL, REG_VMIO|REG_CIRC, 0}, {BRDATAD(ASU6, &AC[336], 8, 8, 16, "ASU6 Register"), REG_VMIO|REG_CIRC},
{"ASU9", &AC[256], 8, 8, 256, 16, "ASU9 Register", NULL, REG_VMIO|REG_CIRC, 0}, {BRDATAD(ASU7, &AC[352], 8, 8, 16, "ASU7 Register"), REG_VMIO|REG_CIRC},
{"ASU10", &AC[256], 8, 8, 256, 16, "ASU10 Register", NULL, REG_VMIO|REG_CIRC, 0}, {BRDATAD(ASU8, &AC[368], 8, 8, 16, "ASU8 Register"), REG_VMIO|REG_CIRC},
{"ASU11", &AC[256], 8, 8, 256, 16, "ASU11 Register", NULL, REG_VMIO|REG_CIRC, 0}, {BRDATAD(ASU9, &AC[384], 8, 8, 16, "ASU9 Register"), REG_VMIO|REG_CIRC},
{"ASU12", &AC[256], 8, 8, 256, 16, "ASU12 Register", NULL, REG_VMIO|REG_CIRC, 0}, {BRDATAD(ASU10, &AC[400], 8, 8, 16, "ASU10 Register"), REG_VMIO|REG_CIRC},
{"ASU13", &AC[256], 8, 8, 256, 16, "ASU13 Register", NULL, REG_VMIO|REG_CIRC, 0}, {BRDATAD(ASU11, &AC[416], 8, 8, 16, "ASU11 Register"), REG_VMIO|REG_CIRC},
{"ASU14", &AC[256], 8, 8, 256, 16, "ASU14 Register", NULL, REG_VMIO|REG_CIRC, 0}, {BRDATAD(ASU12, &AC[432], 8, 8, 16, "ASU12 Register"), REG_VMIO|REG_CIRC},
{"ASU15", &AC[256], 8, 8, 256, 32, "ASU15 Register", NULL, REG_VMIO|REG_CIRC, 0}, {BRDATAD(ASU13, &AC[448], 8, 8, 16, "ASU13 Register"), REG_VMIO|REG_CIRC},
{BRDATAD(ASU14, &AC[464], 8, 8, 16, "ASU14 Register"), REG_VMIO|REG_CIRC},
{BRDATAD(ASU15, &AC[480], 8, 8, 32, "ASU15 Register"), REG_VMIO|REG_CIRC},
{BRDATA(SW, &SW, 2, 6, 1), REG_FIT}, {BRDATA(SW, &SW, 2, 6, 1), REG_FIT},
{FLDATA(SW911, SW, 0), REG_FIT}, {FLDATA(SW911, SW, 0), REG_FIT},
{FLDATA(SW912, SW, 1), REG_FIT}, {FLDATA(SW912, SW, 1), REG_FIT},
@ -3174,6 +3176,7 @@ cpu_reset(DEVICE * dptr)
int i; int i;
int n,p,h; int n,p,h;
static int initialized; static int initialized;
REG *reg;
if (initialized == 0) { if (initialized == 0) {
initialized = 1; initialized = 1;
@ -3193,10 +3196,13 @@ cpu_reset(DEVICE * dptr)
prev_addr[i+512] = 512 + p; prev_addr[i+512] = 512 + p;
next_half[i+512] = 512 + h; next_half[i+512] = 512 + h;
} }
cpu_reg[1].depth = 512; reg = find_reg("A", NULL, dptr);
cpu_reg[2].offset = 512; reg->depth = 512;
cpu_reg[2].depth = 512; reg->offset = 0;
cpu_reg[2].loc = &AC[512]; reg = find_reg("B", NULL, dptr);
reg->offset = 0;
reg->depth = 512;
reg->loc = &AC[512];
} else { } else {
for(i = 0; i < 256; i++) { for(i = 0; i < 256; i++) {
n = next_addr[i] = (i + 1) & 0377; /* A */ n = next_addr[i] = (i + 1) & 0377; /* A */
@ -3218,12 +3224,17 @@ cpu_reset(DEVICE * dptr)
prev_addr[i+1280] = 1280 + p; prev_addr[i+1280] = 1280 + p;
next_half[i+1280] = 1280 + h; next_half[i+1280] = 1280 + h;
} }
cpu_reg[1].depth = 256; reg = find_reg("A", NULL, dptr);
cpu_reg[2].offset = 256; reg->depth = 256; /* A register */
for(i = 0; i < 15; i++) { reg->offset = 0;
cpu_reg[i+2].loc = &AC[256 + 16*i]; reg = find_reg("B", NULL, dptr);
cpu_reg[i+2].depth = 256; reg->depth = 256; /* B register */
} reg->offset = 0;
reg->loc = &AC[256];
/* Set up ASU locations */
reg = find_reg("ASU1", NULL, dptr);
for(i = 0; i < 15; i++)
(reg + i)->loc = &AC[256 + 16*i];
} }
/* Clear io error flags */ /* Clear io error flags */