diff --git a/AltairZ80/i8272.c b/AltairZ80/i8272.c
index 5809034b..d5c9862f 100644
--- a/AltairZ80/i8272.c
+++ b/AltairZ80/i8272.c
@@ -781,12 +781,18 @@ uint8 I8272_Write(const uint32 Addr, uint8 cData)
 
                 if(i8272_info->fdc_phase == EXEC_PHASE) {
                     switch(i8272_info->cmd[0] & 0x1F) {
-                        case I8272_READ_TRACK:          /* intentional fallthrough */
+                        case I8272_READ_TRACK:
                             sim_printf("I8272: " ADDRESS_FORMAT " Read a track (untested.)" NLP, PCX);
                             i8272_info->fdc_sector = 1; /* Read entire track from sector 1...eot */
-                        case I8272_READ_DATA:           /* intentional fallthrough */
-                        case I8272_READ_DELETED_DATA:   /* intentional fallthrough */
+                            /* fall through */
+
+                        case I8272_READ_DATA:
+                            /* fall through */
+                            
+                        case I8272_READ_DELETED_DATA:
                             disk_read = 1;
+                            /* fall through */
+
                         case I8272_WRITE_DATA:
                         case I8272_WRITE_DELETED_DATA:
                             for(;i8272_info->fdc_sector<=i8272_info->fdc_eot;i8272_info->fdc_sector++) {
diff --git a/AltairZ80/m68kdasm.c b/AltairZ80/m68kdasm.c
index c73f413f..90e76db4 100755
--- a/AltairZ80/m68kdasm.c
+++ b/AltairZ80/m68kdasm.c
@@ -3288,7 +3288,8 @@ unsigned int m68k_is_valid_instruction(unsigned int instruction, unsigned int cp
             if(g_instruction_table[instruction] == d68010_moves_32)
                 return 0;
             if(g_instruction_table[instruction] == d68010_rtd)
-                return 0;   /* intentional fallthrough, older models have more invalid instructions */
+                return 0;   /* older models have more invalid instructions */
+            /* fall through */
         case M68K_CPU_TYPE_68010:
             if(g_instruction_table[instruction] == d68020_bcc_32)
                 return 0;
diff --git a/AltairZ80/s100_hdc1001.c b/AltairZ80/s100_hdc1001.c
index ac78d65f..d9432df5 100644
--- a/AltairZ80/s100_hdc1001.c
+++ b/AltairZ80/s100_hdc1001.c
@@ -361,7 +361,8 @@ static uint8 HDC1001_Write(const uint32 Addr, uint8 cData)
 
     switch(Addr & 0x07) {
         case TF_SDH:
-            hdc1001_info->sel_drive = (cData >> 3) & 0x03; /* intentional fallthrough */
+            hdc1001_info->sel_drive = (cData >> 3) & 0x03;
+            /* fall through */
         case TF_DATA:
         case TF_ERROR:
         case TF_SECNT:
diff --git a/AltairZ80/s100_ss1.c b/AltairZ80/s100_ss1.c
index 032b80a8..74f13b6f 100644
--- a/AltairZ80/s100_ss1.c
+++ b/AltairZ80/s100_ss1.c
@@ -304,7 +304,8 @@ static uint8 SS1_Read(const uint32 Addr)
 
     switch(Addr & 0x0F) {
         case SS1_S8259_L:
-            sel_pic = SLAVE_PIC;    /* intentional fallthrough */
+            sel_pic = SLAVE_PIC;
+            /* fall through */
         case SS1_M8259_L:
             if((ss1_pic[sel_pic].OCW3 & 0x03) == 0x03) {
                 cData = ss1_pic[sel_pic].ISR;
@@ -319,7 +320,8 @@ static uint8 SS1_Read(const uint32 Addr)
             }
             break;
         case SS1_S8259_H:
-            sel_pic = SLAVE_PIC;    /* intentional fallthrough */
+            sel_pic = SLAVE_PIC;
+            /* fall through */
         case SS1_M8259_H:
             cData = ss1_pic[sel_pic].IMR;
             sim_debug(PIC_MSG, &ss1_dev, "SS1: " ADDRESS_FORMAT
@@ -457,7 +459,8 @@ static uint8 SS1_Write(const uint32 Addr, uint8 cData)
             }
             break;
         case SS1_S8259_H:
-            sel_pic = SLAVE_PIC;    /* intentional fallthrough */
+            sel_pic = SLAVE_PIC;
+            /* fall through */
         case SS1_M8259_H:
             if(ss1_pic[sel_pic].config_cnt == 0) {
                 sim_debug(PIC_MSG, &ss1_dev, "SS1: " ADDRESS_FORMAT " WR: %s PIC IMR=0x%02x.\n", PCX, (sel_pic ? "Slave " : "Master"), cData);