folkert/simh-testsetgenerator
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions 1

Added device help and register descriptions

Browse source
This commit is contained in:
Mark Pizzolato 2013-02-04 13:52:59 -08:00
parent ad4d5be6ab
commit 7bd01a5873
7 changed files with 340 additions and 118 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

131
PDP11/pdp11_dc.c
View file

@ -140,6 +140,8 @@ void dco_clr_int (int32 ln);
void dco_set_int (int32 ln); void dco_set_int (int32 ln);
int32 dco_iack (void); int32 dco_iack (void);
void dcx_reset_ln (int32 ln); void dcx_reset_ln (int32 ln);
t_stat dcx_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr);
char *dcx_description (DEVICE *dptr);
/* DCI data structures /* DCI data structures
@ -158,9 +160,9 @@ DIB dci_dib = {
UNIT dci_unit = { UDATA (&dci_svc, 0, 0), KBD_POLL_WAIT }; UNIT dci_unit = { UDATA (&dci_svc, 0, 0), KBD_POLL_WAIT };
REG dci_reg[] = { REG dci_reg[] = {
{ BRDATA (BUF, dci_buf, DEV_RDX, 8, DCX_LINES) }, { BRDATAD (BUF, dci_buf, DEV_RDX, 8, DCX_LINES, "input control/stats register") },
{ BRDATA (CSR, dci_csr, DEV_RDX, 16, DCX_LINES) }, { BRDATAD (CSR, dci_csr, DEV_RDX, 16, DCX_LINES, "input buffer") },
{ GRDATA (IREQ, dci_ireq, DEV_RDX, DCX_LINES, 0) }, { GRDATAD (IREQ, dci_ireq, DEV_RDX, DCX_LINES, 0, "interrupt requests") },
{ DRDATA (LINES, dcx_desc.lines, 6), REG_HRO }, { DRDATA (LINES, dcx_desc.lines, 6), REG_HRO },
{ GRDATA (DEVADDR, dci_dib.ba, DEV_RDX, 32, 0), REG_HRO }, { GRDATA (DEVADDR, dci_dib.ba, DEV_RDX, 32, 0), REG_HRO },
{ GRDATA (DEVIOLN, dci_dib.lnt, DEV_RDX, 32, 0), REG_HRO }, { GRDATA (DEVIOLN, dci_dib.lnt, DEV_RDX, 32, 0), REG_HRO },
@ -169,22 +171,20 @@ REG dci_reg[] = {
}; };
MTAB dci_mod[] = { MTAB dci_mod[] = {
{ MTAB_XTD | MTAB_VDV, 1, NULL, "DISCONNECT", { MTAB_XTD|MTAB_VDV|MTAB_VALR, 1, NULL, "DISCONNECT",
&tmxr_dscln, NULL, &dcx_desc }, &tmxr_dscln, NULL, &dcx_desc, "Disconnect a specific line" },
{ UNIT_ATT, UNIT_ATT, "summary", NULL, { UNIT_ATT, UNIT_ATT, "summary", NULL,
NULL, &tmxr_show_summ, (void *) &dcx_desc }, NULL, &tmxr_show_summ, (void *) &dcx_desc, "Display a summary of line states" },
{ MTAB_XTD | MTAB_VDV | MTAB_NMO, 1, "CONNECTIONS", NULL, { MTAB_XTD|MTAB_VDV|MTAB_NMO, 1, "CONNECTIONS", NULL,
NULL, &tmxr_show_cstat, (void *) &dcx_desc }, NULL, &tmxr_show_cstat, (void *) &dcx_desc, "Display current connections" },
{ MTAB_XTD | MTAB_VDV | MTAB_NMO, 0, "STATISTICS", NULL, { MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, "STATISTICS", NULL,
NULL, &tmxr_show_cstat, (void *) &dcx_desc }, NULL, &tmxr_show_cstat, (void *) &dcx_desc, "Display multiplexer statistics" },
{ MTAB_XTD|MTAB_VDV, 010, "ADDRESS", NULL, { MTAB_XTD|MTAB_VDV|MTAB_VALR, 010, "ADDRESS", "ADDRESS",
&set_addr, &show_addr, NULL }, &set_addr, &show_addr, NULL, "Bus address" },
{ MTAB_XTD | MTAB_VDV, 0, NULL, "AUTOCONFIGURE", { MTAB_XTD|MTAB_VDV|MTAB_VALR, 1, "VECTOR", "VECTOR",
&set_addr_flt, NULL, NULL }, &set_vec, &show_vec_mux, (void *) &dcx_desc, "Interrupt vector" },
{ MTAB_XTD|MTAB_VDV, 1, "VECTOR", NULL, { MTAB_XTD|MTAB_VDV|MTAB_VALR, 0, "LINES", "LINES=n",
&set_vec, &show_vec_mux, (void *) &dcx_desc }, &dcx_set_lines, &tmxr_show_lines, (void *) &dcx_desc, "Display number of lines" },
{ MTAB_XTD | MTAB_VDV, 0, "LINES", "LINES",
&dcx_set_lines, &tmxr_show_lines, (void *) &dcx_desc },
{ 0 } { 0 }
}; };
@ -193,7 +193,11 @@ DEVICE dci_dev = {
1, 10, 31, 1, 8, 8, 1, 10, 31, 1, 8, 8,
NULL, NULL, &dcx_reset, NULL, NULL, &dcx_reset,
NULL, &dcx_attach, &dcx_detach, NULL, &dcx_attach, &dcx_detach,
&dci_dib, DEV_UBUS | DEV_QBUS | DEV_DISABLE | DEV_DIS | DEV_MUX &dci_dib, DEV_UBUS | DEV_QBUS | DEV_DISABLE | DEV_DIS | DEV_MUX,
0, NULL, NULL, NULL,
&dcx_help, NULL, /* help and attach_help routines */
(void *)&dcx_desc, /* help context variable */
&dcx_description /* description routine */
}; };
/* DCO data structures /* DCO data structures
@ -223,30 +227,30 @@ UNIT dco_unit[] = {
}; };
REG dco_reg[] = { REG dco_reg[] = {
{ BRDATA (BUF, dco_buf, DEV_RDX, 8, DCX_LINES) }, { BRDATAD (BUF, dco_buf, DEV_RDX, 8, DCX_LINES, "control/stats register") },
{ BRDATA (CSR, dco_csr, DEV_RDX, 16, DCX_LINES) }, { BRDATAD (CSR, dco_csr, DEV_RDX, 16, DCX_LINES, "buffer") },
{ GRDATA (IREQ, dco_ireq, DEV_RDX, DCX_LINES, 0) }, { GRDATAD (IREQ, dco_ireq, DEV_RDX, DCX_LINES, 0, "interrupt requests") },
{ URDATA (TIME, dco_unit[0].wait, 10, 31, 0, { URDATAD (TIME, dco_unit[0].wait, 10, 31, 0,
DCX_LINES, PV_LEFT) }, DCX_LINES, PV_LEFT, "time from I/O initiation to interrupt") },
{ NULL } { NULL }
}; };
MTAB dco_mod[] = { MTAB dco_mod[] = {
{ TT_MODE, TT_MODE_UC, "UC", "UC", NULL }, { TT_MODE, TT_MODE_UC, "UC", "UC", NULL, NULL, NULL, "lower case converted to upper, high bit cleared" },
{ TT_MODE, TT_MODE_7B, "7b", "7B", NULL }, { TT_MODE, TT_MODE_7B, "7b", "7B", NULL, NULL, NULL, "7 bit mode" },
{ TT_MODE, TT_MODE_8B, "8b", "8B", NULL }, { TT_MODE, TT_MODE_8B, "8b", "8B", NULL, NULL, NULL, "8 bit mode" },
{ TT_MODE, TT_MODE_7P, "7p", "7P", NULL }, { TT_MODE, TT_MODE_7P, "7p", "7P", NULL, NULL, NULL, "7 bit mode - non printing suppressed" },
{ DCX_OPAR+DCX_EPAR, 0, "no parity", "NOPARITY", NULL }, { DCX_OPAR+DCX_EPAR, 0, "no parity", "NOPARITY", NULL },
{ DCX_OPAR+DCX_EPAR, DCX_OPAR, "odd parity", "ODDPARITY", NULL }, { DCX_OPAR+DCX_EPAR, DCX_OPAR, "odd parity", "ODDPARITY", NULL },
{ DCX_OPAR+DCX_EPAR, DCX_EPAR, "even parity", "EVENPARITY", NULL }, { DCX_OPAR+DCX_EPAR, DCX_EPAR, "even parity", "EVENPARITY", NULL },
{ DCX_MDM, 0, "no dataset", "NODATASET", NULL }, { DCX_MDM, 0, "no dataset", "NODATASET", NULL },
{ DCX_MDM, DCX_MDM, "dataset", "DATASET", NULL }, { DCX_MDM, DCX_MDM, "dataset", "DATASET", NULL },
{ MTAB_XTD|MTAB_VUN, 0, NULL, "DISCONNECT", { MTAB_XTD|MTAB_VUN, 1, NULL, "DISCONNECT",
&tmxr_dscln, NULL, &dcx_desc }, &tmxr_dscln, NULL, &dcx_desc, "Disconnect a specific line" },
{ MTAB_XTD|MTAB_VUN|MTAB_NC, 0, "LOG", "LOG", { MTAB_XTD|MTAB_VUN|MTAB_NC, 0, NULL, "LOG=file",
&tmxr_set_log, &tmxr_show_log, &dcx_desc }, &tmxr_set_log, tmxr_show_log, &dcx_desc, "Display logging for designated line" },
{ MTAB_XTD|MTAB_VUN|MTAB_NC, 0, NULL, "NOLOG", { MTAB_XTD|MTAB_VUN, 0, NULL, "NOLOG",
&tmxr_set_nolog, NULL, &dcx_desc }, &tmxr_set_nolog, NULL, &dcx_desc, "Disable logging on designated line" },
{ 0 } { 0 }
}; };
@ -255,7 +259,11 @@ DEVICE dco_dev = {
DCX_LINES, 10, 31, 1, 8, 8, DCX_LINES, 10, 31, 1, 8, 8,
NULL, NULL, &dcx_reset, NULL, NULL, &dcx_reset,
NULL, NULL, NULL, NULL, NULL, NULL,
NULL, DEV_UBUS | DEV_DISABLE | DEV_DIS NULL, DEV_UBUS | DEV_DISABLE | DEV_DIS,
0, NULL, NULL, NULL,
&dcx_help, NULL, /* help and attach_help routines */
(void *)&dcx_desc, /* help context variable */
&dcx_description /* description routine */
}; };
/* Terminal input routines */ /* Terminal input routines */
@ -614,3 +622,56 @@ dcx_desc.lines = newln;
dci_dib.lnt = newln * 010; /* upd IO page lnt */ dci_dib.lnt = newln * 010; /* upd IO page lnt */
return auto_config (dci_dev.name, newln); /* auto config */ return auto_config (dci_dev.name, newln); /* auto config */
} }
t_stat dcx_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr)
{
fprintf (st, "DC11 Additional Terminal Interfaces (DCI/DCO)\n\n");
fprintf (st, "For very early system programs, the PDP-11 simulator supports up to sixteen\n");
fprintf (st, "additional DC11 terminal interfaces. The additional terminals consist of two\n");
fprintf (st, "independent devices, DCI and DCO. The entire set is modeled as a terminal\n");
fprintf (st, "multiplexer, with DCI as the master controller. The additional terminals\n");
fprintf (st, "perform input and output through Telnet sessions connected to a user-specified\n");
fprintf (st, "port. The number of lines is specified with a SET command:\n\n");
fprintf (st, " sim> SET DCI LINES=n set number of additional lines to n [1-16]\n\n");
fprintf (st, "The ATTACH command specifies the port to be used:\n\n");
tmxr_attach_help (st, dptr, uptr, flag, cptr);
fprintf (st, "The additional terminals can be set to one of four modes: UC, 7P, 7B, or 8B.\n\n");
fprintf (st, " mode input characters output characters\n\n");
fprintf (st, " UC lower case converted lower case converted to upper case,\n");
fprintf (st, " to upper case, high-order bit cleared,\n");
fprintf (st, " high-order bit cleared non-printing characters suppressed\n");
fprintf (st, " 7P high-order bit cleared high-order bit cleared,\n");
fprintf (st, " non-printing characters suppressed\n");
fprintf (st, " 7B high-order bit cleared high-order bit cleared\n");
fprintf (st, " 8B no changes no changes\n\n");
fprintf (st, "The default mode is 7P. In addition, each line can be configured to\n");
fprintf (st, "behave as though it was attached to a dataset, or hardwired to a terminal:\n\n");
fprintf (st, " sim> SET DCOn DATASET simulate attachment to a dataset (modem)\n");
fprintf (st, " sim> SET DCOn NODATASET simulate direct attachment to a terminal\n\n");
fprintf (st, "Finally, each line supports output logging. The SET DCOn LOG command enables\n");
fprintf (st, "logging on a line:\n\n");
fprintf (st, " sim> SET DCOn LOG=filename log output of line n to filename\n\n");
fprintf (st, "The SET DCOn NOLOG command disables logging and closes the open log file,\n");
fprintf (st, "if any.\n\n");
fprintf (st, "Once DCI is attached and the simulator is running, the terminals listen for\n");
fprintf (st, "connections on the specified port. They assume that the incoming connections\n");
fprintf (st, "are Telnet connections. The connections remain open until disconnected either\n");
fprintf (st, "by the Telnet client, a SET DCI DISCONNECT command, or a DETACH DCI command.\n\n");
fprintf (st, "Other special commands:\n\n");
fprintf (st, " sim> SHOW DCI CONNECTIONS show current connections\n");
fprintf (st, " sim> SHOW DCI STATISTICS show statistics for active connections\n");
fprintf (st, " sim> SET DCOn DISCONNECT disconnects the specified line.\n\n");
fprintf (st, "The input device (DCI) implements these registers:\n\n");
fprint_reg_help (st, &dci_dev);
fprintf (st, "\nThe output device (DCO) implements these registers:\n\n");
fprint_reg_help (st, &dco_dev);
fprintf (st, "\nThe additional terminals do not support save and restore. All open connections\n");
fprintf (st, "are lost when the simulator shuts down or DCI is detached.\n");
return SCPE_OK;
}
char *dcx_description (DEVICE *dptr)
{
return (dptr == &dci_dev) ? "DC11 asynchronous line interface - receiver"
: "DC11 asynchronous line interface - transmitter";
}

33
PDP11/pdp11_rc.c
View file

@ -171,6 +171,7 @@ static t_stat rc_reset (DEVICE *);
static t_stat rc_attach (UNIT *, char *); static t_stat rc_attach (UNIT *, char *);
static t_stat rc_set_size (UNIT *, int32, char *, void *); static t_stat rc_set_size (UNIT *, int32, char *, void *);
static uint32 update_rccs (uint32, uint32); static uint32 update_rccs (uint32, uint32);
static char *rc_description (DEVICE *dptr);
/* RC11 data structures /* RC11 data structures
@ -216,15 +217,20 @@ static const REG rc_reg[] = {
}; };
static const MTAB rc_mod[] = { static const MTAB rc_mod[] = {
{ UNIT_PLAT, (0 << UNIT_V_PLAT), NULL, "1P", &rc_set_size }, { UNIT_PLAT, (0 << UNIT_V_PLAT), NULL, "1P",
{ UNIT_PLAT, (1 << UNIT_V_PLAT), NULL, "2P", &rc_set_size }, &rc_set_size, NULL, NULL, "Set to 1 platter device" },
{ UNIT_PLAT, (2 << UNIT_V_PLAT), NULL, "3P", &rc_set_size }, { UNIT_PLAT, (1 << UNIT_V_PLAT), NULL, "2P",
{ UNIT_PLAT, (3 << UNIT_V_PLAT), NULL, "4P", &rc_set_size }, &rc_set_size, NULL, NULL, "Set to 2 platter device" },
{ UNIT_AUTO, UNIT_AUTO, "autosize", "AUTOSIZE", NULL }, { UNIT_PLAT, (2 << UNIT_V_PLAT), NULL, "3P",
{ MTAB_XTD|MTAB_VDV, 020, "ADDRESS", "ADDRESS", &rc_set_size, NULL, NULL, "Set to 3 platter device" },
&set_addr, &show_addr, NULL }, { UNIT_PLAT, (3 << UNIT_V_PLAT), NULL, "4P",
{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", "VECTOR", &rc_set_size, NULL, NULL, "Set to 4 platter device" },
&set_vec, &show_vec, NULL }, { UNIT_AUTO, UNIT_AUTO, "autosize", "AUTOSIZE",
NULL, NULL, NULL, "set platters based on file size at ATTACH" },
{ MTAB_XTD|MTAB_VDV|MTAB_VALR, 0020, "ADDRESS", "ADDRESS",
&set_addr, &show_addr, NULL, "Bus address" },
{ MTAB_XTD|MTAB_VDV|MTAB_VALR, 0, "VECTOR", "VECTOR",
&set_vec, &show_vec, NULL, "Interrupt vector" },
{ 0 } { 0 }
}; };
@ -238,7 +244,9 @@ DEVICE rc_dev = {
&rc_attach, /* attach */ &rc_attach, /* attach */
NULL, /* detach */ NULL, /* detach */
&rc_dib, &rc_dib,
DEV_DISABLE | DEV_DIS | DEV_UBUS | DEV_DEBUG DEV_DISABLE | DEV_DIS | DEV_UBUS | DEV_DEBUG, 0,
NULL, NULL, NULL, NULL, NULL, NULL,
&rc_description
}; };
/* I/O dispatch routine, I/O addresses 17777440 - 17777456 */ /* I/O dispatch routine, I/O addresses 17777440 - 17777456 */
@ -582,3 +590,8 @@ static t_stat rc_set_size (UNIT *uptr, int32 val, char *cptr, void *desc)
uptr->flags = uptr->flags & ~UNIT_AUTO; uptr->flags = uptr->flags & ~UNIT_AUTO;
return (SCPE_OK); return (SCPE_OK);
} }
char *rc_description (DEVICE *dptr)
{
return "RC11/RS64 fixed head disk controller";
}

56
PDP11/pdp11_rl.c
View file

@ -260,6 +260,7 @@ t_stat rl_show_dstate (FILE *, UNIT *, int32, void *);
t_stat rl_set_ctrl (UNIT *uptr, int32 val, char *cptr, void *desc); t_stat rl_set_ctrl (UNIT *uptr, int32 val, char *cptr, void *desc);
#endif #endif
t_stat rl_show_ctrl (FILE *st, UNIT *uptr, int32 val, void *desc); t_stat rl_show_ctrl (FILE *st, UNIT *uptr, int32 val, void *desc);
t_stat rl_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr);
char *rl_description (DEVICE *dptr); char *rl_description (DEVICE *dptr);
/* RL11 data structures /* RL11 data structures
@ -288,22 +289,22 @@ static UNIT rl_unit[] = {
}; };
static const REG rl_reg[] = { static const REG rl_reg[] = {
{ GRDATA (RLCS, rlcs, DEV_RDX, 16, 0) }, { GRDATAD (RLCS, rlcs, DEV_RDX, 16, 0, "control/status") },
{ GRDATA (RLDA, rlda, DEV_RDX, 16, 0) }, { GRDATAD (RLDA, rlda, DEV_RDX, 16, 0, "disk address") },
{ GRDATA (RLBA, rlba, DEV_RDX, 16, 0) }, { GRDATAD (RLBA, rlba, DEV_RDX, 16, 0, "memory address") },
{ GRDATA (RLBAE, rlbae, DEV_RDX, 6, 0) }, { GRDATAD (RLBAE, rlbae, DEV_RDX, 6, 0, "memory address extension (RLV12)") },
{ GRDATA (RLMP, rlmp, DEV_RDX, 16, 0) }, { GRDATAD (RLMP, rlmp, DEV_RDX, 16, 0, "multipurpose register queue") },
{ GRDATA (RLMP1, rlmp1, DEV_RDX, 16, 0) }, { GRDATAD (RLMP1, rlmp1, DEV_RDX, 16, 0, "multipurpose register queue") },
{ GRDATA (RLMP2, rlmp2, DEV_RDX, 16, 0) }, { GRDATAD (RLMP2, rlmp2, DEV_RDX, 16, 0, "multipurpose register queue") },
{ FLDATA (INT, IREQ (RL), INT_V_RL) }, { FLDATAD (INT, IREQ (RL), INT_V_RL, "interrupt pending flag") },
{ FLDATA (ERR, rlcs, CSR_V_ERR) }, { FLDATAD (ERR, rlcs, CSR_V_ERR, "error flag (CSR<15>)") },
{ FLDATA (DONE, rlcs, CSR_V_DONE) }, { FLDATAD (DONE, rlcs, CSR_V_DONE, "device done flag (CSR<7>)") },
{ FLDATA (IE, rlcs, CSR_V_IE) }, { FLDATAD (IE, rlcs, CSR_V_IE, "interrupt enable flag (CSR<6>)") },
{ DRDATA (STIME, rl_swait, 24), PV_LEFT }, { DRDATAD (STIME, rl_swait, 24, "seek time, per cylinder"), PV_LEFT },
{ DRDATA (RTIME, rl_rwait, 24), PV_LEFT }, { DRDATAD (RTIME, rl_rwait, 24, "rotational delay"), PV_LEFT },
{ URDATA (CAPAC, rl_unit[0].capac, 10, T_ADDR_W, 0, { URDATA (CAPAC, rl_unit[0].capac, 10, T_ADDR_W, 0,
RL_NUMDR, PV_LEFT + REG_HRO) }, RL_NUMDR, PV_LEFT + REG_HRO) },
{ FLDATA (STOP_IOE, rl_stopioe, 0) }, { FLDATAD (STOP_IOE, rl_stopioe, 0, "stop on I/O error flag") },
{ GRDATA (DEVADDR, rl_dib.ba, DEV_RDX, 32, 0), REG_HRO }, { GRDATA (DEVADDR, rl_dib.ba, DEV_RDX, 32, 0), REG_HRO },
{ GRDATA (DEVVEC, rl_dib.vec, DEV_RDX, 16, 0), REG_HRO }, { GRDATA (DEVVEC, rl_dib.vec, DEV_RDX, 16, 0), REG_HRO },
{ NULL } { NULL }
@ -368,7 +369,7 @@ DEVICE rl_dev = {
NULL, NULL, &rl_reset, NULL, NULL, &rl_reset,
&rl_boot, &rl_attach, &rl_detach, &rl_boot, &rl_attach, &rl_detach,
&rl_dib, DEV_DISABLE | DEV_UBUS | DEV_QBUS | DEV_DEBUG, 0, &rl_dib, DEV_DISABLE | DEV_UBUS | DEV_QBUS | DEV_DEBUG, 0,
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, &rl_help, NULL, NULL,
&rl_description &rl_description
}; };
@ -1231,9 +1232,32 @@ return SCPE_NOFNC;
#endif #endif
t_stat rl_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr)
{
fprintf (st, "RL11/RL01/RL02 Cartridge Disk\n\n");
fprintf (st, "RL11 options include the ability to set units write enabled or write locked,\n");
fprintf (st, "to set the drive type to RL01, RL02, or autosize, and to write a DEC standard\n");
fprintf (st, "044 compliant bad block table on the last track:\n\n");
fprint_set_help (st, dptr);
fprint_show_help (st, dptr);
fprintf (st, "\nThe type options can be used only when a unit is not attached to a file. The\n");
fprintf (st, "bad block option can be used only when a unit is attached to a file.\n");
#if defined (VM_PDP11)
fprintf (st, "The RL device supports the BOOT command.\n");
#endif
fprintf (st, "\nThe RX211 implements these registers:\n\n");
fprint_reg_help (st, dptr);
fprintf (st, "\nError handling is as follows:\n\n");
fprintf (st, " error STOP_IOE processed as\n");
fprintf (st, " not attached 1 report error and stop\n");
fprintf (st, " 0 disk not ready\n\n");
fprintf (st, " end of file x assume rest of disk is zero\n");
fprintf (st, " OS I/O error x report error and stop\n");
return SCPE_OK;
}
char *rl_description (DEVICE *dptr) char *rl_description (DEVICE *dptr)
{ {
return (UNIBUS) ? "RL11/RL01(2) cartridge disk controller" : return (UNIBUS) ? "RL11/RL01(2) cartridge disk controller" :
"RLV12/RL01(2) cartridge disk controller"; "RLV12/RL01(2) cartridge disk controller";
} }

64
PDP11/pdp11_ry.c
View file

@ -164,6 +164,7 @@ t_stat ry_boot (int32 unitno, DEVICE *dptr);
void ry_done (int32 esr_flags, int32 new_ecode); void ry_done (int32 esr_flags, int32 new_ecode);
t_stat ry_set_size (UNIT *uptr, int32 val, char *cptr, void *desc); t_stat ry_set_size (UNIT *uptr, int32 val, char *cptr, void *desc);
t_stat ry_attach (UNIT *uptr, char *cptr); t_stat ry_attach (UNIT *uptr, char *cptr);
t_stat ry_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr);
char *ry_description (DEVICE *dptr); char *ry_description (DEVICE *dptr);
@ -190,25 +191,25 @@ UNIT ry_unit[] = {
}; };
REG ry_reg[] = { REG ry_reg[] = {
{ GRDATA (RYCS, ry_csr, DEV_RDX, 16, 0) }, { GRDATAD (RYCS, ry_csr, DEV_RDX, 16, 0, "status") },
{ GRDATA (RYBA, ry_ba, DEV_RDX, 16, 0) }, { GRDATAD (RYBA, ry_ba, DEV_RDX, 16, 0, "buffer address") },
{ GRDATA (RYWC, ry_wc, DEV_RDX, 8, 0) }, { GRDATAD (RYWC, ry_wc, DEV_RDX, 8, 0, "word count") },
{ GRDATA (RYDB, ry_dbr, DEV_RDX, 16, 0) }, { GRDATAD (RYDB, ry_dbr, DEV_RDX, 16, 0, "data buffer") },
{ GRDATA (RYES, ry_esr, DEV_RDX, 12, 0) }, { GRDATAD (RYES, ry_esr, DEV_RDX, 12, 0, "error status") },
{ GRDATA (RYERR, ry_ecode, DEV_RDX, 8, 0) }, { GRDATAD (RYERR, ry_ecode, DEV_RDX, 8, 0, "error code") },
{ GRDATA (RYTA, ry_track, DEV_RDX, 8, 0) }, { GRDATAD (RYTA, ry_track, DEV_RDX, 8, 0, "current track") },
{ GRDATA (RYSA, ry_sector, DEV_RDX, 8, 0) }, { GRDATAD (RYSA, ry_sector, DEV_RDX, 8, 0, "current sector") },
{ DRDATA (STAPTR, ry_state, 4), REG_RO }, { DRDATAD (STAPTR, ry_state, 4, "controller state"), REG_RO },
{ FLDATA (INT, IREQ (RY), INT_V_RY) }, { FLDATAD (INT, IREQ (RY), INT_V_RY, "interrupt pending flag") },
{ FLDATA (ERR, ry_csr, RYCS_V_ERR) }, { FLDATAD (ERR, ry_csr, RYCS_V_ERR, "error flag") },
{ FLDATA (TR, ry_csr, RYCS_V_TR) }, { FLDATAD (TR, ry_csr, RYCS_V_TR, "transfer ready flag ") },
{ FLDATA (IE, ry_csr, RYCS_V_IE) }, { FLDATAD (IE, ry_csr, RYCS_V_IE, "interrupt enable flag ") },
{ FLDATA (DONE, ry_csr, RYCS_V_DONE) }, { FLDATAD (DONE, ry_csr, RYCS_V_DONE, "device done flag") },
{ DRDATA (CTIME, ry_cwait, 24), PV_LEFT }, { DRDATAD (CTIME, ry_cwait, 24, "command completion time"), PV_LEFT },
{ DRDATA (STIME, ry_swait, 24), PV_LEFT }, { DRDATAD (STIME, ry_swait, 24, "seek time, per track"), PV_LEFT },
{ DRDATA (XTIME, ry_xwait, 24), PV_LEFT }, { DRDATAD (XTIME, ry_xwait, 24, "transfer ready delay"), PV_LEFT },
{ BRDATA (SBUF, rx2xb, 8, 8, RY_NUMBY) }, { BRDATAD (SBUF, rx2xb, 8, 8, RY_NUMBY, "sector buffer array") },
{ FLDATA (STOP_IOE, ry_stopioe, 0) }, { FLDATAD (STOP_IOE, ry_stopioe, 0, "stop on I/O error") },
{ URDATA (CAPAC, ry_unit[0].capac, 10, T_ADDR_W, 0, { URDATA (CAPAC, ry_unit[0].capac, 10, T_ADDR_W, 0,
RX_NUMDR, REG_HRO | PV_LEFT) }, RX_NUMDR, REG_HRO | PV_LEFT) },
{ GRDATA (DEVADDR, ry_dib.ba, DEV_RDX, 32, 0), REG_HRO }, { GRDATA (DEVADDR, ry_dib.ba, DEV_RDX, 32, 0), REG_HRO },
@ -254,7 +255,7 @@ DEVICE ry_dev = {
NULL, NULL, &ry_reset, NULL, NULL, &ry_reset,
&ry_boot, &ry_attach, NULL, &ry_boot, &ry_attach, NULL,
&ry_dib, DEV_DISABLE | DEV_DISI | DEV_UBUS | DEV_Q18, 0, &ry_dib, DEV_DISABLE | DEV_DISI | DEV_UBUS | DEV_Q18, 0,
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, &ry_help, NULL, NULL,
&ry_description &ry_description
}; };
@ -712,6 +713,29 @@ return SCPE_NOFNC;
#endif #endif
t_stat ry_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr)
{
fprintf (st, "RX211/RX02 Floppy Disk\n\n");
fprintf (st, "RX211 options include the ability to set units write enabled or write locked,\n");
fprintf (st, "single or double density, or autosized:\n\n");
fprint_set_help (st, dptr);
fprint_show_help (st, dptr);
fprintf (st, "\n");
#if defined (VM_PDP11)
fprintf (st, "The RX211 supports the BOOT command.\n\n");
#endif
fprintf (st, "The RX211 is disabled in a Qbus system with more than 256KB of memory.\n\n");
fprintf (st, "The RX211 implements these registers:\n\n");
fprint_reg_help (st, dptr);
fprintf (st, "\nError handling is as follows:\n\n");
fprintf (st, " error STOP_IOE processed as\n");
fprintf (st, " not attached 1 report error and stop\n");
fprintf (st, " 0 disk not ready\n\n");
fprintf (st, "RX02 data files are buffered in memory; therefore, end of file and OS I/O\n");
fprintf (st, "errors cannot occur.\n");
return SCPE_OK;
}
char *ry_description (DEVICE *dptr) char *ry_description (DEVICE *dptr)
{ {
return (UNIBUS) ? "RX211 floppy disk controller" : return (UNIBUS) ? "RX211 floppy disk controller" :

66
PDP11/pdp11_tu.c
View file

@ -248,6 +248,7 @@ t_stat tu_detach (UNIT *uptr);
t_stat tu_boot (int32 unitno, DEVICE *dptr); t_stat tu_boot (int32 unitno, DEVICE *dptr);
t_stat tu_set_fmtr (UNIT *uptr, int32 val, char *cptr, void *desc); t_stat tu_set_fmtr (UNIT *uptr, int32 val, char *cptr, void *desc);
t_stat tu_show_fmtr (FILE *st, UNIT *uptr, int32 val, void *desc); t_stat tu_show_fmtr (FILE *st, UNIT *uptr, int32 val, void *desc);
t_stat tu_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr);
char *tu_description (DEVICE *dptr); char *tu_description (DEVICE *dptr);
t_stat tu_go (int32 drv); t_stat tu_go (int32 drv);
int32 tu_abort (void); int32 tu_abort (void);
@ -278,32 +279,32 @@ UNIT tu_unit[] = {
}; };
REG tu_reg[] = { REG tu_reg[] = {
{ GRDATA (CS1, tucs1, DEV_RDX, 6, 0) }, { GRDATAD (CS1, tucs1, DEV_RDX, 6, 0, "current operation") },
{ GRDATA (FC, tufc, DEV_RDX, 16, 0) }, { GRDATAD (FC, tufc, DEV_RDX, 16, 0, "frame count") },
{ GRDATA (FS, tufs, DEV_RDX, 16, 0) }, { GRDATAD (FS, tufs, DEV_RDX, 16, 0, "formatter status") },
{ GRDATA (ER, tuer, DEV_RDX, 16, 0) }, { GRDATAD (ER, tuer, DEV_RDX, 16, 0, "formatter errors") },
{ GRDATA (CC, tucc, DEV_RDX, 16, 0) }, { GRDATAD (CC, tucc, DEV_RDX, 16, 0, "check character") },
{ GRDATA (MR, tumr, DEV_RDX, 16, 0) }, { GRDATAD (MR, tumr, DEV_RDX, 16, 0, "maintenance register") },
{ GRDATA (TC, tutc, DEV_RDX, 16, 0) }, { GRDATAD (TC, tutc, DEV_RDX, 16, 0, "tape control register") },
{ FLDATA (STOP_IOE, tu_stopioe, 0) }, { FLDATAD (STOP_IOE, tu_stopioe, 0, "stop on I/O error flag") },
{ DRDATA (TIME, tu_time, 24), PV_LEFT }, { DRDATAD (TIME, tu_time, 24, "operation execution time"), PV_LEFT },
{ URDATA (UST, tu_unit[0].USTAT, DEV_RDX, 17, 0, TU_NUMDR, 0) }, { URDATAD (UST, tu_unit[0].USTAT, DEV_RDX, 17, 0, TU_NUMDR, 0, "unit status") },
{ URDATA (POS, tu_unit[0].pos, 10, T_ADDR_W, 0, { URDATAD (POS, tu_unit[0].pos, 10, T_ADDR_W, 0,
TU_NUMDR, PV_LEFT | REG_RO) }, TU_NUMDR, PV_LEFT | REG_RO, "position") },
{ NULL } { NULL }
}; };
MTAB tu_mod[] = { MTAB tu_mod[] = {
{ MTAB_XTD|MTAB_VDV, 0, "MASSBUS", "MASSBUS", NULL, &mba_show_num }, { MTAB_XTD|MTAB_VDV, 0, "MASSBUS", NULL,
NULL, &mba_show_num, NULL, "Display Massbus number" },
#if defined (VM_PDP11) #if defined (VM_PDP11)
{ MTAB_XTD|MTAB_VDV, 0, "FORMATTER", "TM02", { MTAB_XTD|MTAB_VDV, 0, "FORMATTER", "TM02",
&tu_set_fmtr, &tu_show_fmtr, NULL, "Set controller type to TM02" }, &tu_set_fmtr, NULL , NULL, "Set formatter/controller type to TM02" },
{ MTAB_XTD|MTAB_VDV, 1, NULL, "TM03", { MTAB_XTD|MTAB_VDV, 1, NULL, "TM03",
&tu_set_fmtr, NULL, NULL, "Set controller type to TM03" }, &tu_set_fmtr, NULL, NULL, "Set formatter/controller type to TM03" },
#else
{ MTAB_XTD|MTAB_VDV, 0, "FORMATTER", NULL,
NULL, &tu_show_fmtr, NULL, "Display controller type" },
#endif #endif
{ MTAB_XTD|MTAB_VDV, 0, "FORMATTER", NULL,
NULL, &tu_show_fmtr, NULL, "Display formatter/controller type" },
{ MTUF_WLK, 0, "write enabled", "WRITEENABLED", { MTUF_WLK, 0, "write enabled", "WRITEENABLED",
NULL, NULL, NULL, "Write enable tape drive" }, NULL, NULL, NULL, "Write enable tape drive" },
{ MTUF_WLK, MTUF_WLK, "write locked", "LOCKED", { MTUF_WLK, MTUF_WLK, "write locked", "LOCKED",
@ -317,7 +318,9 @@ MTAB tu_mod[] = {
{ MTAB_XTD|MTAB_VUN|MTAB_VALR, 0, "FORMAT", "FORMAT", { MTAB_XTD|MTAB_VUN|MTAB_VALR, 0, "FORMAT", "FORMAT",
&sim_tape_set_fmt, &sim_tape_show_fmt, NULL, "Set/Display tape format (SIMH, E11, TPC, P7B)" }, &sim_tape_set_fmt, &sim_tape_show_fmt, NULL, "Set/Display tape format (SIMH, E11, TPC, P7B)" },
{ MTAB_XTD|MTAB_VUN|MTAB_VALR, 0, "CAPACITY", "CAPACITY", { MTAB_XTD|MTAB_VUN|MTAB_VALR, 0, "CAPACITY", "CAPACITY",
&sim_tape_set_capac, &sim_tape_show_capac, NULL, "Set/Display capacity" }, &sim_tape_set_capac, &sim_tape_show_capac, NULL, "Set unit n capacity to arg MB (0 = unlimited)" },
{ MTAB_XTD|MTAB_VUN|MTAB_NMO, 0, "CAPACITY", NULL,
NULL, &sim_tape_show_capac, NULL, "Set/Display capacity" },
{ 0 } { 0 }
}; };
@ -327,7 +330,7 @@ DEVICE tu_dev = {
NULL, NULL, &tu_reset, NULL, NULL, &tu_reset,
&tu_boot, &tu_attach, &tu_detach, &tu_boot, &tu_attach, &tu_detach,
&tu_dib, DEV_MBUS|DEV_UBUS|DEV_QBUS|DEV_DEBUG|DEV_DISABLE|DEV_DIS_INIT|DEV_TM03|DEV_TAPE, &tu_dib, DEV_MBUS|DEV_UBUS|DEV_QBUS|DEV_DEBUG|DEV_DISABLE|DEV_DIS_INIT|DEV_TM03|DEV_TAPE,
0, NULL, NULL, NULL, NULL, NULL, NULL, 0, NULL, NULL, NULL, &tu_help, NULL, NULL,
&tu_description &tu_description
}; };
@ -1062,6 +1065,29 @@ return SCPE_NOFNC;
#endif #endif
t_stat tu_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr)
{
fprintf (st, "TM02/TM03/TE16/TU45/TU77 Magnetic Tapes\n\n");
fprintf (st, "The TU controller implements the Massbus family of 800/1600bpi magnetic tape\n");
fprintf (st, "drives. TU options include the ability to select the formatter type (TM02\n");
fprintf (st, "or TM03), to set the drive type to one of three drives (TE16, TU45, or TU77),\n");
fprintf (st, "and to set the drives write enabled or write locked.\n\n");
fprint_set_help (st, dptr);
fprintf (st, "\nMagnetic tape units can be set to a specific reel capacity in MB, or to\n");
fprintf (st, "unlimited capacity:\n\n");
#if defined (VM_PDP11)
fprintf (st, "The TU controller supports the BOOT command.\n");
#endif
fprintf (st, "\nThe TU controller implements the following registers:\n\n");
fprint_reg_help (st, dptr);
fprintf (st, "\nError handling is as follows:\n\n");
fprintf (st, " error processed as\n");
fprintf (st, " not attached tape not ready; if STOP_IOE, stop\n");
fprintf (st, " end of file bad tape\n");
fprintf (st, " OS I/O error parity error; if STOP_IOE, stop\n");
return SCPE_OK;
}
char *tu_description (DEVICE *dptr) char *tu_description (DEVICE *dptr)
{ {
return "TM03 tape formatter"; return "TM03 tape formatter";

56
PDP11/pdp11_xq.c
View file

@ -296,6 +296,7 @@ void xq_setint (CTLR* xq);
void xq_clrint (CTLR* xq); void xq_clrint (CTLR* xq);
int32 xq_int (void); int32 xq_int (void);
void xq_csr_set_clr(CTLR* xq, uint16 set_bits, uint16 clear_bits); void xq_csr_set_clr(CTLR* xq, uint16 set_bits, uint16 clear_bits);
t_stat xq_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr);
char *xq_description (DEVICE *dptr); char *xq_description (DEVICE *dptr);
struct xq_device xqa = { struct xq_device xqa = {
@ -455,7 +456,7 @@ MTAB xq_mod[] = {
{ MTAB_XTD|MTAB_VDV|MTAB_VALR, 0, "POLL", "POLL={DEFAULT|DISABLED|4..2500|DELAY=nnn}", { MTAB_XTD|MTAB_VDV|MTAB_VALR, 0, "POLL", "POLL={DEFAULT|DISABLED|4..2500|DELAY=nnn}",
&xq_set_poll, &xq_show_poll, NULL, "Display the current polling mode" }, &xq_set_poll, &xq_show_poll, NULL, "Display the current polling mode" },
#else #else
{ MTAB_XTD | MTAB_VDV, 0, "POLL", "POLL={DEFAULT|DISABLED|4..2500}", { MTAB_XTD|MTAB_VDV, 0, "POLL", "POLL={DEFAULT|DISABLED|4..2500}",
&xq_set_poll, &xq_show_poll, NULL, "Display the current polling mode" }, &xq_set_poll, &xq_show_poll, NULL, "Display the current polling mode" },
#endif #endif
{ MTAB_XTD|MTAB_VDV|MTAB_NMO|MTAB_VALR, 0, "SANITY", "SANITY={ON|OFF}", { MTAB_XTD|MTAB_VDV|MTAB_NMO|MTAB_VALR, 0, "SANITY", "SANITY={ON|OFF}",
@ -485,7 +486,7 @@ DEVICE xq_dev = {
&xq_ex, &xq_dep, &xq_reset, &xq_ex, &xq_dep, &xq_reset,
NULL, &xq_attach, &xq_detach, NULL, &xq_attach, &xq_detach,
&xqa_dib, DEV_DISABLE | DEV_QBUS | DEV_DEBUG | DEV_ETHER, &xqa_dib, DEV_DISABLE | DEV_QBUS | DEV_DEBUG | DEV_ETHER,
0, xq_debug, NULL, NULL, NULL, NULL, NULL, 0, xq_debug, NULL, NULL, &xq_help, NULL, NULL,
&xq_description &xq_description
}; };
@ -2977,7 +2978,56 @@ void xq_debug_turbo_setup(CTLR* xq)
xq->dev->name, xq->var->init.tdra_h, xq->var->init.tdra_l); xq->dev->name, xq->var->init.tdra_h, xq->var->init.tdra_l);
} }
t_stat xq_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr)
{
fprintf (st, "DELQA-T/DELQA/DEQNA Qbus Ethernet Controllers\n\n");
fprintf (st, "The simulator implements two DELQA-T/DELQA/DEQNA Qbus Ethernet controllers\n");
fprintf (st, "(XQ, XQB). Initially, XQ is enabled, and XQB is disabled. Options allow\n");
fprintf (st, "control of the MAC address, the controller type, and the sanity timer.\n\n");
fprint_set_help (st, dptr);
fprintf (st, "\nConfigured options and controller state can be displayed with:\n\n");
fprint_show_help (st, dptr);
fprintf (st, "\nMAC address octets must be delimited by dashes, colons or periods.\n");
fprintf (st, "The controller defaults to 08-00-2B-AA-BB-CC, which should be sufficient if\n");
fprintf (st, "there is only one SIMH DELQA-T/DELQA/DEQNA controller on your LAN. Two cards\n");
fprintf (st, "with the same MAC address will see each other's packets, resulting in a serious\n");
fprintf (st, "mess.\n\n");
fprintf (st, "The DELQA-T type/mode is better and faster but may not be usable by older or\n");
fprintf (st, "non-DEC OS's. Also, be aware that DEQNA mode is not supported on many most\n");
fprintf (st, "recent OS's. The DEQNA-LOCK mode of the DELQA card is emulated by setting the\n");
fprintf (st, "controller to DEQNA -- there is no need for a separate mode. DEQNA-LOCK mode\n");
fprintf (st, "behaves exactly like a DEQNA, except for the operation of the VAR and MOP\n");
fprintf (st, "processing.\n\n");
fprintf (st, "The SANITY command change or display the INITIALIZATION sanity timer (DEQNA\n");
fprintf (st, "jumper W3/DELQA switch S4). The INITIALIZATION sanity timer has a default\n");
fprintf (st, "timeout of 4 minutes, and cannot be turned off, just reset. The normal sanity\n");
fprintf (st, "timer can be set by operating system software regardless of the state of this\n");
fprintf (st, "switch. Note that only the DEQNA (or the DELQA in DEQNA-LOCK mode (=DEQNA))\n");
fprintf (st, "supports the sanity timer -- it is ignored by a DELQA in Normal mode, which\n");
fprintf (st, "uses switch S4 for a different purpose.\n\n");
#if defined(USE_READER_THREAD) && defined(SIM_ASYNCH_IO)
fprintf (st, "The POLL command change or display the service polling timer. Scheduled\n");
fprintf (st, "service polling is unnecessary and inefficient when asynchronous I/O is\n");
fprintf (st, "available, therefore the default setting is disabled.\n");
#else /* !(defined(USE_READER_THREAD) && defined(SIM_ASYNCH_IO)) */
fprintf (st, "The POLL command change or display the service polling timer. The polling\n");
fprintf (st, "timer is calibrated to run the service thread on each simulated system clock\n");
fprintf (st, "tick. This should be sufficient for most situations, however if desired more\n");
fprintf (st, "frequent polling can be specified. Polling too frequent can seriously impact\n");
fprintf (st, "the simulator's ability to execute instructions efficiently.\n");
#endif /* defined(USE_READER_THREAD) && defined(SIM_ASYNCH_IO) */
fprintf (st, "\nTo access the network, the simulated Ethernet controller must be attached to a\n");
fprintf (st, "real Ethernet interface.\n\n");
eth_attach_help(st, dptr, uptr, flag, cptr);
fprintf (st, "One final note: because of its asynchronous nature, the XQ controller is not\n");
fprintf (st, "limited to the network speed of the real DELQA-T/DELQA/DEQNA controllers, nor\n");
fprintf (st, "the 10Mbit/sec of a standard Ethernet. Attach it to a Fast Ethernet (100\n");
fprintf (st, "Mbit/sec) card, and \"Feel the Power!\" :-)\n");
return SCPE_OK;
}
char *xq_description (DEVICE *dptr) char *xq_description (DEVICE *dptr)
{ {
return "DELQA/DEQNA Ethernet controller"; return (dptr == &xq_dev) ? "DELQA/DEQNA Ethernet controller"
: "Second DELQA/DEQNA Ethernet controller";
} }

30
PDP11/pdp11_xu.c
View file

@ -128,6 +128,7 @@ void xu_process_receive(CTLR* xu);
void xu_dump_rxring(CTLR* xu); void xu_dump_rxring(CTLR* xu);
void xu_dump_txring(CTLR* xu); void xu_dump_txring(CTLR* xu);
t_stat xu_show_filters (FILE* st, UNIT* uptr, int32 val, void* desc); t_stat xu_show_filters (FILE* st, UNIT* uptr, int32 val, void* desc);
t_stat xu_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr);
char *xu_description (DEVICE *dptr); char *xu_description (DEVICE *dptr);
#define IOLN_XU 010 #define IOLN_XU 010
@ -168,9 +169,9 @@ MTAB xu_mod[] = {
{ MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, "STATS", "STATS", { MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, "STATS", "STATS",
&xu_set_stats, &xu_show_stats, NULL, "Display or reset statistics" }, &xu_set_stats, &xu_show_stats, NULL, "Display or reset statistics" },
{ MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, "FILTERS", NULL, { MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, "FILTERS", NULL,
NULL, &xu_show_filters, NULL, "Display address filters" }, NULL, &xu_show_filters, NULL, "Display MAC addresses which will be received" },
{ MTAB_XTD|MTAB_VDV, 0, "TYPE", "TYPE={DEUNA|DELUA}", { MTAB_XTD|MTAB_VDV, 0, "TYPE", "TYPE={DEUNA|DELUA}",
&xu_set_type, &xu_show_type, NULL }, &xu_set_type, &xu_show_type, NULL, "Display the controller type" },
{ 0 }, { 0 },
}; };
@ -226,7 +227,7 @@ DEVICE xu_dev = {
&xu_ex, &xu_dep, &xu_reset, &xu_ex, &xu_dep, &xu_reset,
NULL, &xu_attach, &xu_detach, NULL, &xu_attach, &xu_detach,
&xua_dib, DEV_DISABLE | DEV_DIS | DEV_UBUS | DEV_DEBUG | DEV_ETHER, &xua_dib, DEV_DISABLE | DEV_DIS | DEV_UBUS | DEV_DEBUG | DEV_ETHER,
0, xu_debug, NULL, NULL, NULL, NULL, NULL, 0, xu_debug, NULL, NULL, &xu_help, NULL, NULL,
&xu_description &xu_description
}; };
@ -1791,6 +1792,29 @@ void xu_dump_txring (CTLR* xu)
} }
} }
t_stat xu_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr)
{
fprintf (st, "DELUA/DEUNA Unibus Ethernet Controllers (XU, XUB)\n\n");
fprintf (st, "The simulator implements two DELUA/DEUNA Unibus Ethernet controllers (XU, XUB).\n");
fprintf (st, "Initially, both XU and XQB are disabled. Options allow control of the MAC\n");
fprintf (st, "address and the controller type.\n\n");
fprint_set_help (st, dptr);
fprintf (st, "\nConfigured options and controller state can be displayed with:\n\n");
fprint_show_help (st, dptr);
fprintf (st, "\nMAC address octets must be delimited by dashes, colons or periods.\n");
fprintf (st, "The controller defaults to 08-00-2B-CC-DD-EE, which should be sufficient if\n");
fprintf (st, "there is only one SIMH DEUNA/DELUA controller on your LAN. Two cards with the\n");
fprintf (st, "same MAC address will see each other's packets, resulting in a serious mess.\n\n");
fprintf (st, "To access the network, the simulated Ethernet controller must be attached to a\n");
fprintf (st, "real Ethernet interface.\n\n");
eth_attach_help(st, dptr, uptr, flag, cptr);
fprintf (st, "One final note: because of its asynchronous nature, the XU controller is not\n");
fprintf (st, "limited to the ~1.5Mbit/sec of the real DEUNA/DELUA controllers, nor the\n");
fprintf (st, "10Mbit/sec of a standard Ethernet. Attach it to a Fast Ethernet (100 Mbit/sec)\n");
fprintf (st, "card, and \"Feel the Power!\" :-)\n");
return SCPE_OK;
}
char *xu_description (DEVICE *dptr) char *xu_description (DEVICE *dptr)
{ {
return "DEUNA/DELUA Ethernet controller"; return "DEUNA/DELUA Ethernet controller";