diff --git a/PDP10/pdp10_defs.h b/PDP10/pdp10_defs.h
index d076dbd9..ed54818d 100644
--- a/PDP10/pdp10_defs.h
+++ b/PDP10/pdp10_defs.h
@@ -624,11 +624,9 @@ typedef struct pdp_dib DIB;
 #define DEV_V_UBUS      (DEV_V_UF + 0)                  /* Unibus */
 #define DEV_V_QBUS      (DEV_V_UF + 1)                  /* Qbus */
 #define DEV_V_Q18       (DEV_V_UF + 2)                  /* Qbus, mem <= 256KB */
-#define DEV_V_FLTA      (DEV_V_UF + 3)                  /* float addr */
 #define DEV_UBUS        (1u << DEV_V_UBUS)
 #define DEV_QBUS        (1u << DEV_V_QBUS)
 #define DEV_Q18         (1u << DEV_V_Q18)
-#define DEV_FLTA        (1u << DEV_V_FLTA)
 
 #define UNIBUS          TRUE                            /* 18b only */
 
@@ -672,6 +670,7 @@ typedef struct pdp_dib DIB;
 #define IOLN_PTR        004
 #define IOBA_PTP        (IO_UBA3 + 017554)              /* PC11 punch */
 #define IOLN_PTP        004
+#define IOBA_AUTO       0                               /* Set by Auto Configure */
 
 /* Common Unibus CSR flags */
 
@@ -747,6 +746,7 @@ typedef struct pdp_dib DIB;
 #define VEC_DZRX        0340
 #define VEC_DZTX        0344
 #define VEC_LP20        0754
+#define VEC_AUTO        0                               /* Set by Auto Configure */
 
 #define IVCL(dv)        (INT_V_##dv)
 #define IREQ(dv)        int_req
diff --git a/PDP10/pdp10_ksio.c b/PDP10/pdp10_ksio.c
index e71f773c..6832de06 100644
--- a/PDP10/pdp10_ksio.c
+++ b/PDP10/pdp10_ksio.c
@@ -904,10 +904,50 @@ for (i = 0; dib_tab[i] != NULL; i++) {                  /* print table */
 return SCPE_OK;
 }
 
-/* Stub auto-configure */
+/* 
+    Autoconfiguration - Not really just configure fixed addresses on KS10
+*/
 
-t_stat auto_config (char *name, int32 num)
+typedef struct {
+    char        *dnam;
+    uint32      fixa[1];
+    uint32      fixv[1];
+    } AUTO_CON;
+
+AUTO_CON auto_tab[] = {/*c  #v  am vm  fxa   fxv */
+    { { "DZ" },    {IOBA_DZ},   {VEC_DZRX} },           /* DZ11 - fx CSR, fx VEC */
+    { { "CR" },    {IOBA_CR},   {VEC_CR} },             /* CR11 - fx CSR, fx VEC */
+    { { "RY" },    {IOBA_RY},   {VEC_RY} },             /* RX211/RXV21/RX02 - fx CSR, no VEC */
+    { { "PTR" },   {IOBA_PTR},  {VEC_PTR} },            /* PC11 reader - fx CSR, no VEC */
+    { { "PTP" },   {IOBA_PTP},  {VEC_PTP} },            /* PC11 punch - fx CSR, no VEC */
+    { { "LP20" },  {IOBA_LP20}, {VEC_LP20} },           /* LP20 - fx CSR, no VEC */
+    { { "TU" },    {IOBA_TU},   {VEC_TU} },             /* RH11/tape - fx CSR, no VEC */
+    { { "RP" },    {IOBA_RP},   {VEC_RP} },             /* RH11/disk - fx CSR, no VEC */
+    { { NULL } }                                        /* end table */
+};
+
+t_stat auto_config (char *name, int32 nctrl)
 {
+AUTO_CON *autp;
+DEVICE *dptr;
+DIB *dibp;
+
+if (name == NULL)
+    return SCPE_IERR;
+if (nctrl < 0)
+    return SCPE_ARG;
+for (autp = auto_tab; autp->dnam; autp++) {
+    dptr = find_dev (autp->dnam);                   /* find ctrl */
+    if ((dptr == NULL) ||                           /* enabled? */
+        (dptr->flags & DEV_DIS) ||
+        (strcmp (name, autp->dnam)))
+        continue;
+    dibp = (DIB *) dptr->ctxt;                      /* get DIB */
+    if (dibp == NULL)                               /* not there??? */
+        return SCPE_IERR;
+    dibp->ba = autp->fixa[0];
+    dibp->vec = autp->fixv[0];
+    }
 return SCPE_OK;
 }
 
diff --git a/PDP11/pdp11_cr.c b/PDP11/pdp11_cr.c
index 521f3edd..ce583169 100644
--- a/PDP11/pdp11_cr.c
+++ b/PDP11/pdp11_cr.c
@@ -345,8 +345,10 @@ t_stat cr_show_trans (FILE *, UNIT *, int32, void *);
    cr_dev   CR device descriptor
 */
 
-static DIB cr_dib = { IOBA_CR, IOLN_CR, &cr_rd, &cr_wr,
-        1, IVCL (CR), VEC_CR, { NULL } };
+#define IOLN_CR         010
+
+static DIB cr_dib = { IOBA_AUTO, IOLN_CR, &cr_rd, &cr_wr,
+        1, IVCL (CR), VEC_AUTO, { NULL } };
 
 static UNIT cr_unit = {
     UDATA (&cr_svc,
@@ -1085,7 +1087,7 @@ t_stat cr_reset (   DEVICE  *dptr    )
     CLR_INT (CR);
     /* TBD: flush current card */
     /* init uptr->wait ? */
-    return (SCPE_OK);
+    return auto_config (dptr->name, 1);
 }
 
 /*
diff --git a/PDP11/pdp11_dc.c b/PDP11/pdp11_dc.c
index 99eecf2d..58d2f0b4 100644
--- a/PDP11/pdp11_dc.c
+++ b/PDP11/pdp11_dc.c
@@ -148,9 +148,11 @@ void dcx_reset_ln (int32 ln);
    dci_reg      DCI register list
 */
 
+#define IOLN_DC         010
+
 DIB dci_dib = {
-    IOBA_DC, IOLN_DC, &dcx_rd, &dcx_wr,
-    2, IVCL (DCI), VEC_DCI, { &dci_iack, &dco_iack }
+    IOBA_AUTO, IOLN_DC * DCX_LINES, &dcx_rd, &dcx_wr,
+    2, IVCL (DCI), VEC_AUTO, { &dci_iack, &dco_iack }
     };
 
 UNIT dci_unit = { UDATA (&dci_svc, 0, 0), KBD_POLL_WAIT };
@@ -191,7 +193,7 @@ DEVICE dci_dev = {
     1, 10, 31, 1, 8, 8,
     NULL, NULL, &dcx_reset,
     NULL, &dcx_attach, &dcx_detach,
-    &dci_dib, DEV_FLTA | DEV_UBUS | DEV_QBUS | DEV_DISABLE | DEV_DIS
+    &dci_dib, DEV_UBUS | DEV_QBUS | DEV_DISABLE | DEV_DIS
     };
 
 /* DCO data structures
diff --git a/PDP11/pdp11_defs.h b/PDP11/pdp11_defs.h
index bfa0e01b..79d5214e 100644
--- a/PDP11/pdp11_defs.h
+++ b/PDP11/pdp11_defs.h
@@ -488,13 +488,11 @@ typedef struct {
 #define DEV_V_UBUS      (DEV_V_UF + 0)                  /* Unibus */
 #define DEV_V_QBUS      (DEV_V_UF + 1)                  /* Qbus */
 #define DEV_V_Q18       (DEV_V_UF + 2)                  /* Qbus with <= 256KB */
-#define DEV_V_FLTA      (DEV_V_UF + 3)                  /* flt addr */
-#define DEV_V_MBUS      (DEV_V_UF + 4)                  /* Massbus */
-#define DEV_V_FFUF      (DEV_V_UF + 5)                  /* first free flag */
+#define DEV_V_MBUS      (DEV_V_UF + 3)                  /* Massbus */
+#define DEV_V_FFUF      (DEV_V_UF + 4)                  /* first free flag */
 #define DEV_UBUS        (1u << DEV_V_UBUS)
 #define DEV_QBUS        (1u << DEV_V_QBUS)
 #define DEV_Q18         (1u << DEV_V_Q18)
-#define DEV_FLTA        (1u << DEV_V_FLTA)
 #define DEV_MBUS        (1u << DEV_V_MBUS)
 
 #define DEV_RDX         8                               /* default device radix */
@@ -516,26 +514,45 @@ struct pdp_dib {
 
 typedef struct pdp_dib DIB;
 
-/* I/O page layout - XUB, RQB,RQC,RQD float based on number of DZ's */
+/* Unibus I/O page layout - see pdp11_ui_lib.c for address layout details
+   Massbus devices (RP, TU) do not appear in the Unibus IO page */
 
+#define IOBA_AUTO       (0)                             /* Assigned by Auto Configure */
 #define IOBA_FLOAT      (0)                             /* Assigned by Auto Configure */
 
-#define IOBA_DZ         (IOPAGEBASE + 000100)           /* DZ11 */
-#define IOLN_DZ         010
-#define IOBA_XUB        (IOPAGEBASE + 000330 + (020 * (DZ_MUXES / 2)))
-#define IOLN_XUB        010
-#define IOBA_RQB        (IOPAGEBASE + 000334 + (020 * (DZ_MUXES / 2)))
-#define IOLN_RQB        004
-#define IOBA_RQC        (IOPAGEBASE + IOBA_RQB + IOLN_RQB)
-#define IOLN_RQC        004
-#define IOBA_RQD        (IOPAGEBASE + IOBA_RQC + IOLN_RQC)
-#define IOLN_RQD        004
+/* Processor registers which have I/O page addresses
+ */
+
+#define IOBA_CTL        (IOPAGEBASE + 017520)           /* board ctrl */
+#define IOLN_CTL        010
 #define IOBA_UBM        (IOPAGEBASE + 010200)           /* Unibus map */
 #define IOLN_UBM        (UBM_LNT_LW * sizeof (int32))
-#define	IOBA_KG         (IOPAGEBASE + 010700)           /* KG11-A */
-#define	IOLN_KG         006
-#define IOBA_RQ         (IOPAGEBASE + 012150)           /* RQDX3 */
-#define IOLN_RQ         004
+#define IOBA_MMR3       (IOPAGEBASE + 012516)           /* MMR3 */
+#define IOLN_MMR3       002
+#define IOBA_TTI        (IOPAGEBASE + 017560)           /* DL11 rcv */
+#define IOLN_TTI        004
+#define IOBA_TTO        (IOPAGEBASE + 017564)           /* DL11 xmt */
+#define IOLN_TTO        004
+#define IOBA_SR         (IOPAGEBASE + 017570)           /* SR */
+#define IOLN_SR         002
+#define IOBA_MMR012     (IOPAGEBASE + 017572)           /* MMR0-2 */
+#define IOLN_MMR012     006
+#define IOBA_GPR        (IOPAGEBASE + 017700)           /* GPR's */
+#define IOLN_GPR        010
+#define IOBA_UCTL       (IOPAGEBASE + 017730)           /* UBA ctrl */
+#define IOLN_UCTL       010
+#define IOBA_CPU        (IOPAGEBASE + 017740)           /* CPU reg */
+#define IOLN_CPU        036
+#define IOBA_PSW        (IOPAGEBASE + 017776)           /* PSW */
+#define IOLN_PSW        002
+#define IOBA_UIPDR      (IOPAGEBASE + 017600)           /* user APR's */
+#define IOLN_UIPDR      020
+#define IOBA_UDPDR      (IOPAGEBASE + 017620)
+#define IOLN_UDPDR      020
+#define IOBA_UIPAR      (IOPAGEBASE + 017640)
+#define IOLN_UIPAR      020
+#define IOBA_UDPAR      (IOPAGEBASE + 017660)
+#define IOLN_UDPAR      020
 #define IOBA_SUP        (IOPAGEBASE + 012200)           /* supervisor APR's */
 #define IOLN_SUP        0100
 #define IOBA_KIPDR      (IOPAGEBASE + 012300)           /* kernel APR's */
@@ -546,88 +563,6 @@ typedef struct pdp_dib DIB;
 #define IOLN_KIPAR      020
 #define IOBA_KDPAR      (IOPAGEBASE + 012360)
 #define IOLN_KDPAR      020
-#define IOBA_TU         (IOPAGEBASE + 012440)           /* TU */
-#define IOLN_TU         040
-#define IOBA_MMR3       (IOPAGEBASE + 012516)           /* MMR3 */
-#define IOLN_MMR3       002
-#define IOBA_TM         (IOPAGEBASE + 012520)           /* TM11 */
-#define IOLN_TM         014
-#define IOBA_TS         (IOPAGEBASE + 012520)           /* TS11 */
-#define IOLN_TS         004
-#define IOBA_PCLK       (IOPAGEBASE + 012540)           /* KW11P */
-#define IOLN_PCLK       006
-#define IOBA_DC         (IOPAGEBASE + 014000)           /* DC11 */
-#define IOLN_DC         (DCX_LINES * 010)
-#define IOBA_RL         (IOPAGEBASE + 014400)           /* RL11 */
-#define IOLN_RL         012
-#define IOBA_XQ         (IOPAGEBASE + 014440)           /* DEQNA/DELQA */
-#define IOLN_XQ         020
-#define IOBA_XQB        (IOPAGEBASE + 014460)           /* 2nd DEQNA/DELQA */
-#define IOLN_XQB        020
-#define IOBA_TQ         (IOPAGEBASE + 014500)           /* TMSCP */
-#define IOLN_TQ         004
-#define IOBA_XU         (IOPAGEBASE + 014510)           /* DEUNA/DELUA */
-#define IOLN_XU         010
-#define IOBA_DL         (IOPAGEBASE + 016500)           /* extra KL11/DL11 */
-#define IOLN_DL         (DLX_LINES * 010)
-#define IOBA_RP         (IOPAGEBASE + 016700)           /* RP/RM */
-#define IOLN_RP         054
-#define IOBA_CR         (IOPAGEBASE + 017160)           /* CD/CR/CM */
-#define IOLN_CR         010
-#define IOBA_RX         (IOPAGEBASE + 017170)           /* RX11 */
-#define IOLN_RX         004
-#define IOBA_RY         (IOPAGEBASE + 017170)           /* RY11 */
-#define IOLN_RY         004
-#define IOBA_KE         (IOPAGEBASE + 017300)           /* KE11-A */
-#define IOLN_KE         020
-#define IOBA_TC         (IOPAGEBASE + 017340)           /* TC11 */
-#define IOLN_TC         012
-#define IOBA_QDSS       (IOPAGEBASE + 017400)           /* QDSS */
-#define IOLN_QDSS       002
-#define IOBA_RK         (IOPAGEBASE + 017400)           /* RK11 */
-#define IOLN_RK         020
-#define IOBA_RC         (IOPAGEBASE + 017440)           /* RC11/RS64 */
-#define IOLN_RC         020
-#define IOBA_HK         (IOPAGEBASE + 017440)           /* RK611 */
-#define IOLN_HK         040
-#define IOBA_RF         (IOPAGEBASE + 017460)           /* RF11 */
-#define IOLN_RF         020
-#define IOBA_TA         (IOPAGEBASE + 017500)           /* TA11 */
-#define IOLN_TA         004
-#define IOBA_LPT        (IOPAGEBASE + 017514)           /* LP11 */
-#define IOLN_LPT        004
-#define IOBA_CTL        (IOPAGEBASE + 017520)           /* board ctrl */
-#define IOLN_CTL        010
-#define IOBA_CLK        (IOPAGEBASE + 017546)           /* KW11L */
-#define IOLN_CLK        002
-#define IOBA_PTR        (IOPAGEBASE + 017550)           /* PC11 reader */
-#define IOLN_PTR        004
-#define IOBA_PTP        (IOPAGEBASE + 017554)           /* PC11 punch */
-#define IOLN_PTP        004
-#define IOBA_TTI        (IOPAGEBASE + 017560)           /* DL11 rcv */
-#define IOLN_TTI        004
-#define IOBA_TTO        (IOPAGEBASE + 017564)           /* DL11 xmt */
-#define IOLN_TTO        004
-#define IOBA_SR         (IOPAGEBASE + 017570)           /* SR */
-#define IOLN_SR         002
-#define IOBA_MMR012     (IOPAGEBASE + 017572)           /* MMR0-2 */
-#define IOLN_MMR012     006
-#define IOBA_UIPDR      (IOPAGEBASE + 017600)           /* user APR's */
-#define IOLN_UIPDR      020
-#define IOBA_UDPDR      (IOPAGEBASE + 017620)
-#define IOLN_UDPDR      020
-#define IOBA_UIPAR      (IOPAGEBASE + 017640)
-#define IOLN_UIPAR      020
-#define IOBA_UDPAR      (IOPAGEBASE + 017660)
-#define IOLN_UDPAR      020
-#define IOBA_GPR        (IOPAGEBASE + 017700)           /* GPR's */
-#define IOLN_GPR        010
-#define IOBA_UCTL       (IOPAGEBASE + 017730)           /* UBA ctrl */
-#define IOLN_UCTL       010
-#define IOBA_CPU        (IOPAGEBASE + 017740)           /* CPU reg */
-#define IOLN_CPU        036
-#define IOBA_PSW        (IOPAGEBASE + 017776)           /* PSW */
-#define IOLN_PSW        002
 
 /* Interrupt assignments; within each level, priority is right to left
    PIRQn has the highest priority with a level and is always bit <0>
@@ -780,41 +715,15 @@ typedef struct pdp_dib DIB;
 
 /* Device vectors */
 
+#define VEC_AUTO        (0)                             /* Assigned by Auto Configure */
 #define VEC_FLOAT       (0)                             /* Assigned by Auto Configure */
 
 #define VEC_Q           0000                            /* vector base */
+
+/* Processor specific internal fixed vectors */
 #define VEC_PIRQ        0240
 #define VEC_TTI         0060
 #define VEC_TTO         0064
-#define VEC_PTR         0070
-#define VEC_PTP         0074
-#define VEC_CLK         0100
-#define VEC_PCLK        0104
-#define VEC_XQ          0120
-#define VEC_XU          0120
-#define VEC_RQ          0154
-#define VEC_RL          0160
-#define VEC_LPT         0200
-#define VEC_RF          0204
-#define VEC_HK          0210
-#define VEC_RC          0210
-#define VEC_RK          0220
-#define VEC_DTA         0214
-#define VEC_TM          0224
-#define VEC_TS          0224
-#define VEC_TU          0224
-#define VEC_CR          0230
-#define VEC_RP          0254
-#define VEC_TQ          0260
-#define VEC_TA          0260
-#define VEC_RX          0264
-#define VEC_RY          0264
-#define VEC_DLI         0300
-#define VEC_DLO         0304
-#define VEC_DCI         0300
-#define VEC_DCO         0304
-#define VEC_DZRX        0300
-#define VEC_DZTX        0304
 
 /* Interrupt macros */
 
diff --git a/PDP11/pdp11_dl.c b/PDP11/pdp11_dl.c
index 9b264667..57393883 100644
--- a/PDP11/pdp11_dl.c
+++ b/PDP11/pdp11_dl.c
@@ -114,9 +114,11 @@ void dlx_reset_ln (int32 ln);
    dli_reg      DLI register list
 */
 
+#define IOLN_DL         010
+
 DIB dli_dib = {
-    IOBA_DL, IOLN_DL, &dlx_rd, &dlx_wr,
-    2, IVCL (DLI), VEC_DLI, { &dli_iack, &dlo_iack }
+    IOBA_AUTO, IOLN_DL * DLX_LINES, &dlx_rd, &dlx_wr,
+    2, IVCL (DLI), VEC_AUTO, { &dli_iack, &dlo_iack }
     };
 
 UNIT dli_unit = { UDATA (&dli_svc, 0, 0), KBD_POLL_WAIT };
@@ -158,7 +160,7 @@ DEVICE dli_dev = {
     1, 10, 31, 1, 8, 8,
     NULL, NULL, &dlx_reset,
     NULL, &dlx_attach, &dlx_detach,
-    &dli_dib, DEV_FLTA | DEV_UBUS | DEV_QBUS | DEV_DISABLE | DEV_DIS
+    &dli_dib, DEV_UBUS | DEV_QBUS | DEV_DISABLE | DEV_DIS
     };
 
 /* DLO data structures
diff --git a/PDP11/pdp11_dmc.c b/PDP11/pdp11_dmc.c
index e8c7467a..4707bd88 100644
--- a/PDP11/pdp11_dmc.c
+++ b/PDP11/pdp11_dmc.c
@@ -381,16 +381,16 @@ DEVICE dmc_dev[] =
 {
     { "DMC0", &dmc_unit[0], dmca_reg, dmc_mod, DMC_UNITSPERDEVICE, DMC_RDX, 8, 1, DMC_RDX, 8,
     NULL,NULL,&dmc_reset,NULL,&dmc_attach,&dmc_detach,
-    &dmc_dib[0], DEV_FLTA | DEV_DISABLE | DEV_DIS | DEV_UBUS | DEV_NET | DEV_DEBUG, 0, dmc_debug },
+    &dmc_dib[0], DEV_DISABLE | DEV_DIS | DEV_UBUS | DEV_NET | DEV_DEBUG, 0, dmc_debug },
     { "DMC1", &dmc_unit[1], dmcb_reg, dmc_mod, DMC_UNITSPERDEVICE, DMC_RDX, 8, 1, DMC_RDX, 8,
     NULL,NULL,&dmc_reset,NULL,&dmc_attach,&dmc_detach,
-    &dmc_dib[1], DEV_FLTA | DEV_DISABLE | DEV_DIS | DEV_UBUS | DEV_NET | DEV_DEBUG, 0, dmc_debug },
+    &dmc_dib[1], DEV_DISABLE | DEV_DIS | DEV_UBUS | DEV_NET | DEV_DEBUG, 0, dmc_debug },
     { "DMC2", &dmc_unit[2], dmcc_reg, dmc_mod, DMC_UNITSPERDEVICE, DMC_RDX, 8, 1, DMC_RDX, 8,
     NULL,NULL,&dmc_reset,NULL,&dmc_attach,&dmc_detach,
-    &dmc_dib[2], DEV_FLTA | DEV_DISABLE | DEV_DIS | DEV_UBUS | DEV_NET | DEV_DEBUG, 0, dmc_debug },
+    &dmc_dib[2], DEV_DISABLE | DEV_DIS | DEV_UBUS | DEV_NET | DEV_DEBUG, 0, dmc_debug },
     { "DMC3", &dmc_unit[3], dmcd_reg, dmc_mod, DMC_UNITSPERDEVICE, DMC_RDX, 8, 1, DMC_RDX, 8,
     NULL,NULL,&dmc_reset,NULL,&dmc_attach,&dmc_detach,
-    &dmc_dib[3], DEV_FLTA | DEV_DISABLE | DEV_DIS | DEV_UBUS | DEV_NET | DEV_DEBUG, 0, dmc_debug }
+    &dmc_dib[3], DEV_DISABLE | DEV_DIS | DEV_UBUS | DEV_NET | DEV_DEBUG, 0, dmc_debug }
 };
 
 #ifdef DMP
@@ -398,7 +398,7 @@ DEVICE dmp_dev[] =
 {
     { "DMP", &dmp_unit[0], dmp_reg, dmc_mod, DMP_UNITSPERDEVICE, DMC_RDX, 8, 1, DMC_RDX, 8,
     NULL,NULL,&dmc_reset,NULL,&dmc_attach,&dmc_detach,
-    &dmp_dib[0], DEV_FLTA | DEV_DISABLE | DEV_DIS | DEV_UBUS | DEV_NET | DEV_DEBUG, 0, dmc_debug }
+    &dmp_dib[0], DEV_DISABLE | DEV_DIS | DEV_UBUS | DEV_NET | DEV_DEBUG, 0, dmc_debug }
 };
 #endif
 
diff --git a/PDP11/pdp11_dz.c b/PDP11/pdp11_dz.c
index 313cb456..efdecf26 100644
--- a/PDP11/pdp11_dz.c
+++ b/PDP11/pdp11_dz.c
@@ -229,9 +229,11 @@ t_stat dz_show_log (FILE *st, UNIT *uptr, int32 val, void *desc);
    dz_reg       DZ register list
 */
 
+#define IOLN_DZ         010
+
 DIB dz_dib = {
-    IOBA_DZ, IOLN_DZ * DZ_MUXES, &dz_rd, &dz_wr,
-    2, IVCL (DZRX), VEC_DZRX, { &dz_rxinta, &dz_txinta }
+    IOBA_AUTO, IOLN_DZ * DZ_MUXES, &dz_rd, &dz_wr,
+    2, IVCL (DZRX), VEC_AUTO, { &dz_rxinta, &dz_txinta }
     };
 
 UNIT dz_unit = { UDATA (&dz_svc, UNIT_IDLE|UNIT_ATTABLE|DZ_8B_DFLT, 0) };
@@ -289,7 +291,7 @@ DEVICE dz_dev = {
     1, DEV_RDX, 8, 1, DEV_RDX, 8,
     &tmxr_ex, &tmxr_dep, &dz_reset,
     NULL, &dz_attach, &dz_detach,
-    &dz_dib, DEV_FLTA | DEV_DISABLE | DEV_UBUS | DEV_QBUS | DEV_DEBUG,
+    &dz_dib, DEV_DISABLE | DEV_UBUS | DEV_QBUS | DEV_DEBUG,
     0, dz_debug
     };
 
diff --git a/PDP11/pdp11_hk.c b/PDP11/pdp11_hk.c
index 0b57cb2c..ca62cd82 100644
--- a/PDP11/pdp11_hk.c
+++ b/PDP11/pdp11_hk.c
@@ -575,9 +575,11 @@ t_stat hk_set_bad (UNIT *uptr, int32 val, char *cptr, void *desc);
    hk_mod       HK modifier list
 */
 
+#define IOLN_HK         040
+
 DIB hk_dib = {
-    IOBA_HK, IOLN_HK, &hk_rd, &hk_wr,
-    1, IVCL (HK), VEC_HK, { NULL }
+    IOBA_AUTO, IOLN_HK, &hk_rd, &hk_wr,
+    1, IVCL (HK), VEC_AUTO, { NULL }
     };
 
 UNIT hk_unit[] = {
diff --git a/PDP11/pdp11_io_lib.c b/PDP11/pdp11_io_lib.c
index aff5487b..1936622d 100644
--- a/PDP11/pdp11_io_lib.c
+++ b/PDP11/pdp11_io_lib.c
@@ -48,7 +48,7 @@ extern t_stat build_dib_tab (void);
 
 static DIB *iodibp[IOPAGESIZE >> 1];
 
-#define AUTO_MAXC       4
+#define AUTO_MAXC       32              /* Maximum number of controllers */
 #define AUTO_CSRBASE    0010
 #define AUTO_CSRMAX    04000
 #define AUTO_VECBASE    0300
@@ -98,7 +98,6 @@ if ((newba <= IOPAGEBASE) ||                            /* > IO page base? */
     (newba % ((uint32) val)))                           /* check modulus */
     return SCPE_ARG;
 dibp->ba = newba;                                       /* store */
-dptr->flags = dptr->flags & ~DEV_FLTA;                  /* not floating */
 autcon_enb = 0;                                         /* autoconfig off */
 return SCPE_OK;
 }
@@ -142,7 +141,6 @@ if (uptr == NULL)
 dptr = find_dev_from_unit (uptr);
 if (dptr == NULL)
     return SCPE_IERR;
-dptr->flags = dptr->flags | DEV_FLTA;                   /* floating */
 return auto_config (NULL, 0);                           /* autoconfigure */
 }
 
@@ -171,7 +169,6 @@ if ((r != SCPE_OK) || (newvec == VEC_Q) ||
     (newvec & ((dibp->vnum > 1)? 07: 03)))
     return SCPE_ARG;
 dibp->vec = newvec;
-dptr->flags = dptr->flags & ~DEV_FLTA;                  /* not floating */
 autcon_enb = 0;                                         /* autoconfig off */
 return SCPE_OK;
 }
@@ -319,7 +316,7 @@ for (i = 0, dibp = NULL; i < (IOPAGESIZE >> 1); i++) {  /* loop thru entries */
         fprintf (st, " - ");
         fprint_val (st, (t_value) dibp->ba + dibp->lnt - 1, DEV_RDX, 32, PV_LEFT);
         fprintf (st, "%c\t%s\n",                        /* print block entry */
-            (dptr && (dptr->flags & DEV_FLTA))? '*': ' ',
+            (dibp->ba < IOPAGEBASE + AUTO_CSRBASE + AUTO_CSRMAX)? '*': ' ',
             dptr? sim_dname (dptr): "CPU");
         }                                               /* end if */
     }                                                   /* end for i */
@@ -328,16 +325,19 @@ return SCPE_OK;
 
 /* Autoconfiguration
 
-   The table reflects the MicroVAX 3900 microcode, with one addition - the
+   The table reflects the MicroVAX 3900 microcode, with one field addition - the
    number of controllers field handles devices where multiple instances
    are simulated through a single DEVICE structure (e.g., DZ, VH).
 
-   A minus number of vectors indicates a field that should be calculated
-   but not placed in the DIB (RQ, TQ dynamic vectors) */
+   The table has been reviewed, extended and updated to reflect the contents of
+   the auto configure table in VMS sysgen (V5.5-2)
+
+   A minus number of vectors indicates a field that should be calculated
+   but not placed in the DIB (RQ, TQ dynamic vectors)
+
+   An amod value of 0 indicates that all addresses are FIXED
+   An vmod value of 0 indicates that all vectors are FIXED */
 
-#define AUTO_MAXC       4
-#define AUTO_CSRBASE    0010
-#define AUTO_VECBASE    0300
 
 typedef struct {
     char        *dnam[AUTO_MAXC];
@@ -349,18 +349,101 @@ typedef struct {
     uint32      fixv[AUTO_MAXC];
     } AUTO_CON;
 
-/* An amod value of 0 implies that all addresses are FIXED */
-/* An vmod value of 0 implies that all vectors are FIXED */
 AUTO_CON auto_tab[] = {/*c  #v  am vm  fxa   fxv */
-    { { "DCI" }, DCX_LINES,  2,  0, 8, { 0 } },         /* DC11 - fx CSRs */
-    { { "DLI" }, DLX_LINES,  2,  0, 8, { 0 } },         /* KL11/DL11/DLV11 - fx CSRs */
+    { { "QBA" },         1,  0,  0, 0, 
+        {017500} },                                     /* doorbell - fx CSR, no VEC */
+    { { "MCTL" },        1,  0,  0, 0, 
+        {012100} },                                     /* MSV11-P - fx CSR, no VEC */
+    { { "KE" },          1,  0,  0, 0, 
+        {017300} },                                     /* KE11-A - fx CSR, no VEC */
+    { { "KG" },          1,  0,  0, 0, 
+        {010700} },                                     /* KG11-A - fx CSR, no VEC */
+    { { "RHA", "RHB" },  1,  1,  0, 0, 
+        {016700, 012440}, {0254, 0224} },               /* RH11/RH70 - fx CSR, fx VEC */
+    { { "CLK" },         1,  0,  0, 0, 
+        {017546}, {0100} },                             /* KW11L - fx CSR, fx VEC */
+    { { "PTR" },         1,  1,  0, 0, 
+        {017550}, {0070} },                             /* PC11 reader - fx CSR, fx VEC */
+    { { "PTP" },         1,  1,  0, 0, 
+        {017554}, {0074} },                             /* PC11 punch - fx CSR, fx VEC */
+    { { "RK" },          1,  1,  0, 0, 
+        {017400}, {0220} },                             /* RK11 - fx CSR, fx VEC */
+    { { "TM" },          1,  1,  0, 0, 
+        {012520}, {0224} },                             /* TM11 - fx CSR, fx VEC */
+    { { "RC" },          1,  1,  0, 0, 
+        {017440}, {0210} },                             /* RC11 - fx CSR, fx VEC */
+    { { "RF" },          1,  1,  0, 0, 
+        {017460}, {0204} },                             /* RF11 - fx CSR, fx VEC */
+    { { "CR" },          1,  1,  0, 0, 
+        {017160}, {0230} },                             /* CR11 - fx CSR, fx VEC */
+    { { "HK" },          1,  1,  0, 0, 
+        {017440}, {0210} },                             /* RK611 - fx CSR, fx VEC */
+    { { "LPT" },         1,  1,  0, 0, 
+        {017514, 004004, 004014, 004024, 004034}, 
+        {0200,     0170,   0174,   0270,   0274} },     /* LP11 - fx CSR, fx VEC */
+    { { "RB" },          1,  1,  0, 0, 
+        {015606}, {0250} },                             /* RB730 - fx CSR, fx VEC */
+    { { "RL" },          1,  1,  0, 0, 
+        {014400}, {0160} },                             /* RL11 - fx CSR, fx VEC */
+    { { "RL" },          1,  1,  0, 0, 
+        {014400}, {0160} },                             /* RL11 - fx CSR, fx VEC */
+    { { "DCI" }, DCX_LINES,  2,  0, 8, 
+        {014000, 014010, 014020, 014030, 
+         014040, 014050, 014060, 014070, 
+         014100, 014110, 014120, 014130, 
+         014140, 014150, 014160, 014170, 
+         014200, 014210, 014220, 014230, 
+         014240, 014250, 014260, 014270,
+         014300, 014310, 014320, 014330, 
+         014340, 014350, 014360, 014370} },             /* DC11 - fx CSRs */
+    { { NULL },          1,  2,  0, 8, 
+        {016500, 016510, 016520, 016530, 
+         016540, 016550, 016560, 016570,
+         016600, 016610, 016620, 016630,
+         016640, 016650, 016660, 016670} },             /* TU58 - fx CSRs */
+    { { NULL },          1,  1,  0, 4, 
+        {015200, 015210, 015220, 015230, 
+         015240, 015250, 015260, 015270,
+         015300, 015310, 015320, 015330,
+         015340, 015350, 015360, 015370} },             /* DN11 - fx CSRs */
+    { { NULL },          1,  1,  0, 4, 
+        {010500, 010510, 010520, 010530, 
+         010540, 010550, 010560, 010570, 
+         010600, 010610, 010620, 010630, 
+         010640, 010650, 010660, 010670} },             /* DM11B - fx CSRs */
+    { { NULL },          1,  2,  0, 8, 
+        {007600, 007570, 007560, 007550, 
+         007540, 007530, 007520, 007510,
+         007500, 007470, 007460, 007450,
+         007440, 007430, 007420, 007410} },             /* DR11C - fx CSRs */
+    { { NULL },          1,  1,  0, 8, 
+        {012600, 012604, 012610, 012614, 
+         012620, 012624, 012620, 012624} },             /* PR611 - fx CSRs */
+    { { NULL },          1,  1,  0, 8, 
+        {017420, 017422, 017424, 017426, 
+         017430, 017432, 017434, 017436} },             /* DT11 - fx CSRs */
+    { { NULL },          1,  2,  0, 8,
+      {016200, 016240} },                               /* DX11 */
+    { { "DLI" }, DLX_LINES,  2,  0, 8, 
+        {016500, 016510, 016520, 016530,
+         016540, 016550, 016560, 016570,
+         016600, 016610, 016620, 016630,
+         016740, 016750, 016760, 016770} },             /* KL11/DL11/DLV11 - fx CSRs */
     { { NULL },          1,  2,  0, 8, { 0 } },         /* DLV11J - fx CSRs */
     { { NULL },          1,  2,  8, 8 },                /* DJ11 */
     { { NULL },          1,  2, 16, 8 },                /* DH11 */
+    { { NULL },          1,  4,  0, 8,
+      {012000, 012010, 012020, 012030} },               /* GT40 */
+    { { NULL },          1,  2,  0, 8,
+      {010400} },                                       /* LPS11 */
     { { NULL },          1,  2,  8, 8 },                /* DQ11 */
+    { { NULL },          1,  2,  0, 8,
+      {012400} },                                       /* KW11W */
     { { NULL },          1,  2,  8, 8 },                /* DU11 */
     { { NULL },          1,  2,  8, 8 },                /* DUP11 */
-    { { NULL },         10,  2,  8, 8 },                /* LK11A */
+    { { NULL },          1,  3,  0, 8,
+      {015000, 015040, 015100, 015140, }},              /* DV11 */
+    { { NULL },          1,  2,  8, 8 },                /* LK11A */
     { { "DMC0", "DMC1", "DMC2", "DMC3" }, 
                          1,  2,  8, 8 },                /* DMC11 */
     { { "DZ" },   DZ_MUXES,  2,  8, 8 },                /* DZ11 */
@@ -369,54 +452,97 @@ AUTO_CON auto_tab[] = {/*c  #v  am vm  fxa   fxv */
     { { NULL },          1,  2,  8, 8 },                /* VMV21 */
     { { NULL },          1,  2, 16, 8 },                /* VMV31 */
     { { NULL },          1,  2,  8, 8 },                /* DWR70 */
-    { { "RL", "RLB" },   1,  1,  8, 4, 
-        {IOBA_RL}, {VEC_RL} },                          /* RL11 */
-    { { "TS", "TSB", "TSC", "TSD" }, 
+    { { "RL", "RLB"},    1,  1,  8, 4, 
+        {014400}, {0160} },                             /* RL11 */
+    { { "TS", "TSB", "TSC", "TSD"}, 
                          1,  1,  0, 4,                  /* TS11 */
-        {IOBA_TS, IOBA_TS + 4, IOBA_TS + 8, IOBA_TS + 12},
-        {VEC_TS} },
-    { { NULL },          1,  2, 16, 8 },                /* LPA11K */
+        {012520, 012524, 012530, 012534},
+        {0224} },
+    { { NULL },          1,  2, 16, 8,
+        {010460} },                                     /* LPA11K */
     { { NULL },          1,  2,  8, 8 },                /* KW11C */
     { { NULL },          1,  1,  8, 8 },                /* reserved */
     { { "RX", "RY" },    1,  1,  8, 4, 
-        {IOBA_RX} , {VEC_RX} },                         /* RX11/RX211 */
+        {017170} , {0264} },                            /* RX11/RX211 */
     { { NULL },          1,  1,  8, 4 },                /* DR11W */
     { { NULL },          1,  1,  8, 4, 
-        { 0, 0 }, { 0 } },                              /* DR11B - fx CSRs,vec */
+        {012410, 012410}, {0124} },                     /* DR11B - fx CSRs,vec */
     { { "DMP" },         1,  2,  8, 8 },                /* DMP11 */
     { { NULL },          1,  2,  8, 8 },                /* DPV11 */
-    { { NULL },          1,  2, 8, 8 },                 /* ISB11 */
+    { { NULL },          1,  2,  8, 8 },                /* ISB11 */
     { { NULL },          1,  2, 16, 8 },                /* DMV11 */
     { { "XU", "XUB" },   1,  1,  8, 4, 
-        {IOBA_XU}, {VEC_XU} },                          /* DEUNA */
-    { { "XQ", "XQB" },   1,  1,  0, 4,                  /* DEQNA */
-        {IOBA_XQ,IOBA_XQB}, {VEC_XQ} },
+        {014510}, {0120} },                             /* DEUNA */
+    { { "XQ", "XQB" },   1, -1,  0, 4,
+        {014440, 014460, 014520, 014540}, {0120} },     /* DEQNA */
     { { "RQ", "RQB", "RQC", "RQD" }, 
                          1, -1,  4, 4,                  /* RQDX3 */
-        {IOBA_RQ}, {VEC_RQ} },
+        {012150}, {0154} },
     { { NULL },          1,  8, 32, 4 },                /* DMF32 */
-    { { NULL },          1,  2, 16, 8 },                /* KMS11 */
+    { { NULL },          1,  3, 16, 8 },                /* KMS11 */
+    { { NULL },          1,  2,  0, 8,
+        {004200, 004240, 004300, 004340} },             /* PLC11 */
     { { NULL },          1,  1, 16, 4 },                /* VS100 */
     { { "TQ", "TQB" },   1, -1,  4, 4, 
-        {IOBA_TQ}, {VEC_TQ} },                          /* TQK50 */
+        {014500}, {0260} },                             /* TQK50 */
     { { NULL },          1,  2, 16, 8 },                /* KMV11 */
+    { { NULL },          1,  2,  0, 8,
+        {004400, 004440, 004500, 004540} },             /* KTC32 */
+    { { NULL },          1,  2,  0, 8,
+        {004100} },                                     /* IEQ11 */
     { { "VH" },   VH_MUXES,  2, 16, 8 },                /* DHU11/DHQ11 */
     { { NULL },          1,  6, 32, 4 },                /* DMZ32 */
     { { NULL },          1,  6, 32, 4 },                /* CP132 */
-    { { NULL },          1,  2, 64, 8, { 0 } },         /* QVSS - fx CSR */
+    { { NULL },          1,  1,  0, 0,
+        {017340}, {0214} },                             /* TC11 */
+    { { NULL },          1,  2, 64, 8, 
+        {017200} },                                     /* QVSS - fx CSR */
     { { NULL },          1,  1,  8, 4 },                /* VS31 */
-    { { NULL },          1,  1,  0, 4, { 0 } },         /* LNV11 - fx CSR */
+    { { NULL },          1,  1,  0, 4,
+        {016200} },                                     /* LNV11 - fx CSR */
     { { NULL },          1,  1, 16, 4 },                /* LNV21/QPSS */
-    { { NULL },          1,  1,  8, 4, { 0 } },         /* QTA - fx CSR */
+    { { NULL },          1,  1,  8, 4, 
+        {012570} },                                     /* QTA - fx CSR */
     { { NULL },          1,  1,  8, 4 },                /* DSV11 */
     { { NULL },          1,  2,  8, 8 },                /* CSAM */
     { { NULL },          1,  2,  8, 8 },                /* ADV11C */
-    { { NULL },          1,  0,  8, 0 },                /* AAV11C */
-    { { NULL },          1,  2,  8, 8, { 0 }, { 0 } },  /* AXV11C - fx CSR,vec */
-    { { NULL },          1,  2,  4, 8, { 0 } },         /* KWV11C - fx CSR */
-    { { NULL },          1,  2,  8, 8, { 0 } },         /* ADV11D - fx CSR */
-    { { NULL },          1,  2,  8, 8, { 0 } },         /* AAV11D - fx CSR */
-    { { "QDSS" },        1,  3,  0, 16, {IOBA_QDSS} },  /* QDSS - fx CSR */
+    { { NULL },          1,  0,  8, 8, 
+        {010440} },                                     /* AAV11/AAV11C */
+    { { NULL },          1,  2,  8, 8, 
+        {016400}, {0140} },                             /* AXV11C - fx CSR,vec */
+    { { NULL },          1,  2,  4, 8, 
+        {010420} },                                     /* KWV11C - fx CSR */
+    { { NULL },          1,  2,  8, 8, 
+        {016410} },                                     /* ADV11D - fx CSR */
+    { { NULL },          1,  2,  8, 8, 
+        {016420} },                                     /* AAV11D - fx CSR */
+    { { "QDSS" },        1,  3,  0, 16,
+        {017400, 017402, 017404, 017406, 
+         017410, 017412, 017414, 017416} },             /* VCB02 - QDSS - fx CSR */
+    { { NULL },          1, 16,  0, 4, 
+        {004160, 004140, 004120} },                     /* DRV11J - fx CSR */
+    { { NULL },          1,  2, 16, 8 },                /* DRQ3B */
+    { { NULL },          1,  1,  8, 4 },                /* VSV24 */
+    { { NULL },          1,  1,  8, 4 },                /* VSV21 */
+    { { NULL },          1,  1,  8, 4 },                /* IBQ01 */
+    { { NULL },          1,  1,  8, 8 },                /* IDV11A */
+    { { NULL },          1,  0,  8, 8 },                /* IDV11B */
+    { { NULL },          1,  0,  8, 8 },                /* IDV11C */
+    { { NULL },          1,  1,  8, 8 },                /* IDV11D */
+    { { NULL },          1,  2,  8, 8 },                /* IAV11A */
+    { { NULL },          1,  0,  8, 8 },                /* IAV11B */
+    { { NULL },          1,  2,  8, 8 },                /* MIRA */
+    { { NULL },          1,  2, 16, 8 },                /* IEQ11 */
+    { { NULL },          1,  2, 32, 8 },                /* ADQ32 */
+    { { NULL },          1,  2,  8, 8 },                /* DTC04, DECvoice */
+    { { NULL },          1,  1, 32, 4 },                /* DESNA */
+    { { NULL },          1,  2,  4, 8 },                /* IGQ11 */
+    { { NULL },          1,  2, 32, 8 },                /* KMV1F */
+    { { NULL },          1,  1,  8, 4 },                /* DIV32 */
+    { { NULL },          1,  2,  4, 8 },                /* DTCN5, DECvoice */
+    { { NULL },          1,  2,  4, 8 },                /* DTC05, DECvoice */
+    { { NULL },          1,  2,  8, 8 },                /* KWV32 (DSV11) */
+    { { NULL },          1,  1, 64, 4 },                /* QZA */
     { { NULL }, -1 }                                    /* end table */
 };
 
@@ -427,6 +553,7 @@ uint32 vec = VEC_Q + AUTO_VECBASE;
 AUTO_CON *autp;
 DEVICE *dptr;
 DIB *dibp;
+t_bool auto_fixed = TRUE;
 uint32 j, k, vmask, amask;
 
 if (autcon_enb == 0)                                    /* enabled? */
@@ -448,28 +575,27 @@ for (autp = auto_tab; autp->numc >= 0; autp++) {        /* loop thru table */
         }
     for (j = k = 0; (j < AUTO_MAXC) && autp->dnam[j]; j++) {
         if (autp->dnam[j] == NULL)                      /* no device? */
-            continue;
+            break;
         dptr = find_dev (autp->dnam[j]);                /* find ctrl */
         if ((dptr == NULL) ||                           /* enabled, floating? */
-            (dptr->flags & DEV_DIS) ||
-            !(dptr->flags & DEV_FLTA))
+            (dptr->flags & DEV_DIS))
             continue;
         dibp = (DIB *) dptr->ctxt;                      /* get DIB */
         if (dibp == NULL)                               /* not there??? */
             return SCPE_IERR;
-        if (autp->amod) {                               /* dyn csr needed? */
+        if (auto_fixed || (autp->amod)) {               /* dyn csr needed? */
             if (autp->fixa[k])                          /* fixed csr avail? */
-                dibp->ba = autp->fixa[k];               /* use it */
+                dibp->ba = IOPAGEBASE + autp->fixa[k];  /* use it */
             else {                                      /* no fixed left */
                 dibp->ba = csr;                         /* set CSR */
                 csr += (autp->numc * autp->amod);       /* next CSR */
                 }                                       /* end else */
             }                                           /* end if dyn csr */
-        if (autp->numv && autp->vmod) {                 /* dyn vec needed? */
+        if (autp->numv && (autp->vmod || auto_fixed)) { /* dyn vec needed? */
             uint32 numv = abs (autp->numv);             /* get num vec */
             if (autp->fixv[k]) {                        /* fixed vec avail? */
                 if (autp->numv > 0)
-                    dibp->vec = autp->fixv[k];          /* use it */
+                    dibp->vec = VEC_Q + autp->fixv[k];  /* use it */
                 }
             else {                                      /* no fixed left */
                 vmask = autp->vmod - 1;
diff --git a/PDP11/pdp11_ke.c b/PDP11/pdp11_ke.c
index c82ddeef..d2c91058 100644
--- a/PDP11/pdp11_ke.c
+++ b/PDP11/pdp11_ke.c
@@ -71,7 +71,9 @@ t_stat ke_wr (int32 data, int32 PA, int32 access);
 t_stat ke_reset (DEVICE *dptr);
 uint32 ke_set_SR (void);
 
-DIB ke_dib = { IOBA_KE, IOLN_KE, &ke_rd, &ke_wr, 0 };
+#define IOLN_KE         020
+
+DIB ke_dib = { IOBA_AUTO, IOLN_KE, &ke_rd, &ke_wr, 0 };
 
 UNIT ke_unit = {
 	UDATA (NULL, UNIT_DISABLE, 0)
@@ -344,5 +346,5 @@ ke_SR = 0;
 ke_SC = 0;
 ke_AC = 0;
 ke_MQ = 0;
-return SCPE_OK;
+return auto_config(0, 0);
 }
diff --git a/PDP11/pdp11_kg.c b/PDP11/pdp11_kg.c
index 6597250f..b037388d 100644
--- a/PDP11/pdp11_kg.c
+++ b/PDP11/pdp11_kg.c
@@ -195,8 +195,10 @@ static t_stat set_units (UNIT *, int32, char *, void *);
    kg_dev       KG device descriptor
 */
 
+#define IOLN_KG         006
+
 static DIB kg_dib = {
-    IOBA_KG,
+    IOBA_AUTO,
     (IOLN_KG + 2) * KG_UNITS,
     &kg_rd,
     &kg_wr,
@@ -406,7 +408,7 @@ static t_stat kg_reset (DEVICE *dptr)
         kg_unit[i].BCC = 0;
         kg_unit[i].PULSCNT = 0;
     }
-    return (SCPE_OK);
+    return auto_config(0, 0);
 }
 
 static void cycleOneBit (int unit)
diff --git a/PDP11/pdp11_lp.c b/PDP11/pdp11_lp.c
index c535daed..74d0ff98 100644
--- a/PDP11/pdp11_lp.c
+++ b/PDP11/pdp11_lp.c
@@ -71,9 +71,11 @@ t_stat lpt_detach (UNIT *uptr);
    lpt_reg      LPT register list
 */
 
+#define IOLN_LPT        004
+
 DIB lpt_dib = {
-    IOBA_LPT, IOLN_LPT, &lpt_rd, &lpt_wr,
-    1, IVCL (LPT), VEC_LPT, { NULL }
+    IOBA_AUTO, IOLN_LPT, &lpt_rd, &lpt_wr,
+    1, IVCL (LPT), VEC_AUTO, { NULL }
     };
 
 UNIT lpt_unit = {
diff --git a/PDP11/pdp11_pclk.c b/PDP11/pdp11_pclk.c
index f83f5e83..0984b1d3 100644
--- a/PDP11/pdp11_pclk.c
+++ b/PDP11/pdp11_pclk.c
@@ -151,9 +151,11 @@ void pclk_tick (void);
    pclk_reg     PCLK register list
 */
 
+#define IOLN_PCLK       006
+
 DIB pclk_dib = {
-    IOBA_PCLK, IOLN_PCLK, &pclk_rd, &pclk_wr,
-    1, IVCL (PCLK), VEC_PCLK, { NULL }
+    IOBA_AUTO, IOLN_PCLK, &pclk_rd, &pclk_wr,
+    1, IVCL (PCLK), VEC_AUTO, { NULL }
     };
 
 UNIT pclk_unit = { UDATA (&pclk_svc, UNIT_IDLE, 0) };
@@ -304,7 +306,7 @@ pclk_ctr = 0;
 CLR_INT (PCLK);                                         /* clear int */
 sim_cancel (&pclk_unit);                                /* cancel */
 pclk_unit.wait = xtim[0];                               /* reset delay */
-return SCPE_OK;
+return auto_config (0, 0);
 }
 
 /* Set line frequency */
diff --git a/PDP11/pdp11_pt.c b/PDP11/pdp11_pt.c
index 62a6d46d..ba4f480c 100644
--- a/PDP11/pdp11_pt.c
+++ b/PDP11/pdp11_pt.c
@@ -79,9 +79,11 @@ t_stat ptp_detach (UNIT *uptr);
    ptr_reg      PTR register list
 */
 
+#define IOLN_PTR        004
+
 DIB ptr_dib = {
-    IOBA_PTR, IOLN_PTR, &ptr_rd, &ptr_wr,
-    1, IVCL (PTR), VEC_PTR, { NULL }
+    IOBA_AUTO, IOLN_PTR, &ptr_rd, &ptr_wr,
+    1, IVCL (PTR), VEC_AUTO, { NULL }
     };
 
 UNIT ptr_unit = {
@@ -127,9 +129,11 @@ DEVICE ptr_dev = {
    ptp_reg      PTP register list
 */
 
+#define IOLN_PTP        004
+
 DIB ptp_dib = {
-    IOBA_PTP, IOLN_PTP, &ptp_rd, &ptp_wr,
-    1, IVCL (PTP), VEC_PTP, { NULL }
+    IOBA_AUTO, IOLN_PTP, &ptp_rd, &ptp_wr,
+    1, IVCL (PTP), VEC_AUTO, { NULL }
     };
 
 UNIT ptp_unit = {
@@ -249,7 +253,7 @@ if ((ptr_unit.flags & UNIT_ATT) == 0)
     ptr_csr = ptr_csr | CSR_ERR;
 CLR_INT (PTR);
 sim_cancel (&ptr_unit);
-return SCPE_OK;
+return auto_config (dptr->name, 1);
 }
 
 t_stat ptr_attach (UNIT *uptr, char *cptr)
@@ -344,7 +348,7 @@ if ((ptp_unit.flags & UNIT_ATT) == 0)
     ptp_csr = ptp_csr | CSR_ERR;
 CLR_INT (PTP);
 sim_cancel (&ptp_unit);                                 /* deactivate unit */
-return SCPE_OK;
+return auto_config (dptr->name, 1);
 }
 
 t_stat ptp_attach (UNIT *uptr, char *cptr)
diff --git a/PDP11/pdp11_rc.c b/PDP11/pdp11_rc.c
index f0bab9ba..448a668a 100644
--- a/PDP11/pdp11_rc.c
+++ b/PDP11/pdp11_rc.c
@@ -180,12 +180,14 @@ static uint32 update_rccs (uint32, uint32);
    rc_reg       RC register list
 */
 
+#define IOLN_RC         020
+
 static DIB rc_dib = {
-    IOBA_RC,
+    IOBA_AUTO,
     IOLN_RC,
     &rc_rd,
     &rc_wr,
-    1, IVCL (RC), VEC_RC, { NULL }
+    1, IVCL (RC), VEC_AUTO, { NULL }
 };
 
 static UNIT rc_unit = {
@@ -549,7 +551,7 @@ static t_stat rc_reset (DEVICE *dptr)
     rc_db = 0;
     CLR_INT (RC);
     sim_cancel (&rc_unit);
-    return (SCPE_OK);
+    return auto_config(0, 0);
 }
 
 /* Attach routine */
diff --git a/PDP11/pdp11_rf.c b/PDP11/pdp11_rf.c
index 6af0f800..6fb62525 100644
--- a/PDP11/pdp11_rf.c
+++ b/PDP11/pdp11_rf.c
@@ -142,9 +142,11 @@ uint32 update_rfcs (uint32 newcs, uint32 newdae);
    rf_reg       RF register list
 */
 
+#define IOLN_RF         020
+
 DIB rf_dib = {
-    IOBA_RF, IOLN_RF, &rf_rd, &rf_wr,
-    1, IVCL (RF), VEC_RF, {NULL}
+    IOBA_AUTO, IOLN_RF, &rf_rd, &rf_wr,
+    1, IVCL (RF), VEC_AUTO, {NULL}
     };
 
 
@@ -428,7 +430,7 @@ rf_wc = 0;
 rf_maint = 0;
 CLR_INT (RF);
 sim_cancel (&rf_unit);
-return SCPE_OK;
+return auto_config (0, 0);
 }
 
 /* Bootstrap routine */
diff --git a/PDP11/pdp11_rh.c b/PDP11/pdp11_rh.c
index efc7c043..263f16fd 100644
--- a/PDP11/pdp11_rh.c
+++ b/PDP11/pdp11_rh.c
@@ -206,9 +206,11 @@ static int32 mba_mapofs[(MBA_OFSMASK + 1) >> 1] = {
    mbax_reg     RHx register list
 */
 
+#define IOLN_RP         054
+
 DIB mba0_dib = {
-    IOBA_RP, IOLN_RP, &mba_rd, &mba_wr,
-    1, IVCL (RP), VEC_RP, { &mba0_inta }
+    IOBA_AUTO, IOLN_RP, &mba_rd, &mba_wr,
+    1, IVCL (RP), VEC_AUTO, { &mba0_inta }
     };
 
 UNIT mba0_unit = { UDATA (NULL, 0, 0) };
@@ -239,9 +241,11 @@ MTAB mba0_mod[] = {
     { 0 }
     };
 
+#define IOLN_TU         040
+
 DIB mba1_dib = {
-    IOBA_TU, IOLN_TU, &mba_rd, &mba_wr,
-    1, IVCL (TU), VEC_TU, { &mba1_inta }
+    IOBA_AUTO, IOLN_TU, &mba_rd, &mba_wr,
+    1, IVCL (TU), VEC_AUTO, { &mba1_inta }
     };
 
 UNIT mba1_unit = { UDATA (NULL, 0, 0) };
@@ -776,7 +780,7 @@ massbus[mb].iff = 0;
 mba_clr_int (mb);
 if (mbabort[mb])
     mbabort[mb] ();
-return SCPE_OK;
+return auto_config (0, 0);
 }
 
 /* Enable/disable Massbus adapter */
diff --git a/PDP11/pdp11_rk.c b/PDP11/pdp11_rk.c
index cb27b06d..af865465 100644
--- a/PDP11/pdp11_rk.c
+++ b/PDP11/pdp11_rk.c
@@ -212,9 +212,11 @@ t_stat rk_boot (int32 unitno, DEVICE *dptr);
    rk_mod       RK modifier list
 */
 
+#define IOLN_RK         020
+
 DIB rk_dib = {
-    IOBA_RK, IOLN_RK, &rk_rd, &rk_wr,
-    1, IVCL (RK), VEC_RK, { &rk_inta }
+    IOBA_AUTO, IOLN_RK, &rk_rd, &rk_wr,
+    1, IVCL (RK), VEC_AUTO, { &rk_inta }
     };
 
 UNIT rk_unit[] = {
@@ -707,7 +709,7 @@ if (rkxb == NULL)
     rkxb = (uint16 *) calloc (RK_MAXFR, sizeof (uint16));
 if (rkxb == NULL)
     return SCPE_MEM;
-return SCPE_OK;
+return auto_config (0, 0);
 }
 
 /* Device bootstrap */
diff --git a/PDP11/pdp11_rl.c b/PDP11/pdp11_rl.c
index 146eeadb..ff435b55 100644
--- a/PDP11/pdp11_rl.c
+++ b/PDP11/pdp11_rl.c
@@ -270,9 +270,11 @@ t_stat rl_show_ctrl (FILE *st, UNIT *uptr, int32 val, void *desc);
    rl_mod   RL modifier list
 */
 
+#define IOLN_RL         012
+
 static DIB rl_dib = {
-    IOBA_RL, IOLN_RL, &rl_rd, &rl_wr,
-    1, IVCL (RL), VEC_RL, { NULL } };
+    IOBA_AUTO, IOLN_RL, &rl_rd, &rl_wr,
+    1, IVCL (RL), VEC_AUTO, { NULL } };
 
 static UNIT rl_unit[] = {
     { UDATA (&rl_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+
diff --git a/PDP11/pdp11_rq.c b/PDP11/pdp11_rq.c
index 66e27737..f5b1d0f6 100644
--- a/PDP11/pdp11_rq.c
+++ b/PDP11/pdp11_rq.c
@@ -854,8 +854,10 @@ int32 rq_inta (void);
 
 MSC rq_ctx = { 0 };
 
+#define IOLN_RQ         004
+
 DIB rq_dib = {
-    IOBA_RQ, IOLN_RQ, &rq_rd, &rq_wr,
+    IOBA_AUTO, IOLN_RQ, &rq_rd, &rq_wr,
     1, IVCL (RQ), 0, { &rq_inta }
     };
 
@@ -1006,7 +1008,7 @@ DEVICE rq_dev = {
     RQ_NUMDR + 2, DEV_RDX, T_ADDR_W, 2, DEV_RDX, 16,
     NULL, NULL, &rq_reset,
     &rq_boot, &rq_attach, &rq_detach,
-    &rq_dib, DEV_FLTA | DEV_DISABLE | DEV_UBUS | DEV_QBUS | DEV_DEBUG,
+    &rq_dib, DEV_DISABLE | DEV_UBUS | DEV_QBUS | DEV_DEBUG,
     0, rq_debug
     };
 
@@ -1021,7 +1023,7 @@ DEVICE rq_dev = {
 MSC rqb_ctx = { 1 };
 
 DIB rqb_dib = {
-    IOBA_RQB, IOLN_RQB, &rq_rd, &rq_wr,
+    IOBA_FLOAT, IOLN_RQ, &rq_rd, &rq_wr,
     1, IVCL (RQ), 0, { &rq_inta }
     };
 
@@ -1078,7 +1080,7 @@ DEVICE rqb_dev = {
     RQ_NUMDR + 2, DEV_RDX, T_ADDR_W, 2, DEV_RDX, 16,
     NULL, NULL, &rq_reset,
     &rq_boot, &rq_attach, &rq_detach,
-    &rqb_dib, DEV_FLTA | DEV_DISABLE | DEV_DIS | DEV_UBUS | DEV_QBUS | DEV_DEBUG,
+    &rqb_dib, DEV_DISABLE | DEV_DIS | DEV_UBUS | DEV_QBUS | DEV_DEBUG,
     0, rq_debug
     };
 
@@ -1093,7 +1095,7 @@ DEVICE rqb_dev = {
 MSC rqc_ctx = { 2 };
 
 DIB rqc_dib = {
-    IOBA_RQC, IOLN_RQC, &rq_rd, &rq_wr,
+    IOBA_FLOAT, IOLN_RQ, &rq_rd, &rq_wr,
     1, IVCL (RQ), 0, { &rq_inta }
     };
 
@@ -1150,7 +1152,7 @@ DEVICE rqc_dev = {
     RQ_NUMDR + 2, DEV_RDX, T_ADDR_W, 2, DEV_RDX, 16,
     NULL, NULL, &rq_reset,
     &rq_boot, &rq_attach, &rq_detach,
-    &rqc_dib, DEV_FLTA | DEV_DISABLE | DEV_DIS | DEV_UBUS | DEV_QBUS | DEV_DEBUG,
+    &rqc_dib, DEV_DISABLE | DEV_DIS | DEV_UBUS | DEV_QBUS | DEV_DEBUG,
     0, rq_debug
     };
 
@@ -1165,7 +1167,7 @@ DEVICE rqc_dev = {
 MSC rqd_ctx = { 3 };
 
 DIB rqd_dib = {
-    IOBA_RQD, IOLN_RQD, &rq_rd, &rq_wr,
+    IOBA_FLOAT, IOLN_RQ, &rq_rd, &rq_wr,
     1, IVCL (RQ), 0, { &rq_inta }
     };
 
@@ -1222,7 +1224,7 @@ DEVICE rqd_dev = {
     RQ_NUMDR + 2, DEV_RDX, T_ADDR_W, 2, DEV_RDX, 16,
     NULL, NULL, &rq_reset,
     &rq_boot, &rq_attach, &rq_detach,
-    &rqd_dib, DEV_FLTA | DEV_DISABLE | DEV_DIS | DEV_UBUS | DEV_QBUS | DEV_DEBUG,
+    &rqd_dib, DEV_DISABLE | DEV_DIS | DEV_UBUS | DEV_QBUS | DEV_DEBUG,
     0, rq_debug
     };
 
diff --git a/PDP11/pdp11_rx.c b/PDP11/pdp11_rx.c
index 9112e8b4..8d599578 100644
--- a/PDP11/pdp11_rx.c
+++ b/PDP11/pdp11_rx.c
@@ -140,9 +140,11 @@ void rx_done (int32 esr_flags, int32 new_ecode);
    rx_mod       RX modifier list
 */
 
+#define IOLN_RX         004
+
 DIB rx_dib = {
-    IOBA_RX, IOLN_RX, &rx_rd, &rx_wr,
-    1, IVCL (RX), VEC_RX, { NULL }
+    IOBA_AUTO, IOLN_RX, &rx_rd, &rx_wr,
+    1, IVCL (RX), VEC_AUTO, { NULL }
     };
 
 UNIT rx_unit[] = {
@@ -200,7 +202,7 @@ DEVICE rx_dev = {
     RX_NUMDR, 8, 20, 1, 8, 8,
     NULL, NULL, &rx_reset,
     &rx_boot, NULL, NULL,
-    &rx_dib, DEV_FLTA | DEV_DISABLE | DEV_UBUS | DEV_QBUS
+    &rx_dib, DEV_DISABLE | DEV_UBUS | DEV_QBUS
     };
 
 /* I/O dispatch routine, I/O addresses 17777170 - 17777172
diff --git a/PDP11/pdp11_ry.c b/PDP11/pdp11_ry.c
index 2cf63568..c98cdefe 100644
--- a/PDP11/pdp11_ry.c
+++ b/PDP11/pdp11_ry.c
@@ -173,9 +173,11 @@ t_stat ry_attach (UNIT *uptr, char *cptr);
    ry_mod       RY modifier list
 */
 
+#define IOLN_RY         004
+
 DIB ry_dib = {
-    IOBA_RY, IOLN_RY, &ry_rd, &ry_wr,
-    1, IVCL (RY), VEC_RY, { NULL }
+    IOBA_AUTO, IOLN_RY, &ry_rd, &ry_wr,
+    1, IVCL (RY), VEC_AUTO, { NULL }
     };
 
 UNIT ry_unit[] = {
@@ -244,7 +246,7 @@ DEVICE ry_dev = {
     RX_NUMDR, DEV_RDX, 20, 1, DEV_RDX, 8,
     NULL, NULL, &ry_reset,
     &ry_boot, &ry_attach, NULL,
-    &ry_dib, DEV_FLTA | DEV_DISABLE | DEV_DISI | DEV_UBUS | DEV_Q18
+    &ry_dib, DEV_DISABLE | DEV_DISI | DEV_UBUS | DEV_Q18
     };
 
 /* I/O dispatch routine, I/O addresses 17777170 - 17777172
@@ -577,7 +579,7 @@ else if (ry_unit[0].flags & UNIT_BUF)  {                /* attached? */
     sim_activate (&ry_unit[0], ry_swait * abs (1 - ry_unit[0].TRACK));
     }
 else ry_done (RYES_ID, 0010);                           /* no, error */
-return auto_config (0, 0);                              /* run autoconfig */
+return auto_config (dptr->name, 1);                     /* run autoconfig */
 }
 
 /* Attach routine */
diff --git a/PDP11/pdp11_stddev.c b/PDP11/pdp11_stddev.c
index 8166a285..733d0d45 100644
--- a/PDP11/pdp11_stddev.c
+++ b/PDP11/pdp11_stddev.c
@@ -199,9 +199,11 @@ DEVICE tto_dev = {
    clk_reg      CLK register list
 */
 
+#define IOLN_CLK        002
+
 DIB clk_dib = {
-    IOBA_CLK, IOLN_CLK, &clk_rd, &clk_wr,
-    1, IVCL (CLK), VEC_CLK, { &clk_inta }
+    IOBA_AUTO, IOLN_CLK, &clk_rd, &clk_wr,
+    1, IVCL (CLK), VEC_AUTO, { &clk_inta }
     };
 
 UNIT clk_unit = { UDATA (&clk_svc, UNIT_IDLE, 0), CLK_DELAY };
diff --git a/PDP11/pdp11_ta.c b/PDP11/pdp11_ta.c
index f777eff9..507e8a1e 100644
--- a/PDP11/pdp11_ta.c
+++ b/PDP11/pdp11_ta.c
@@ -145,9 +145,11 @@ uint32 ta_crc (uint8 *buf, uint32 cnt);
    ta_mod       TA modifier list
 */
 
+#define IOLN_TA         004
+
 DIB ta_dib = {
-    IOBA_TA, IOLN_TA, &ta_rd, &ta_wr,
-    1, IVCL (TA), VEC_TA, { NULL }
+    IOBA_AUTO, IOLN_TA, &ta_rd, &ta_wr,
+    1, IVCL (TA), VEC_AUTO, { NULL }
     };
 
 UNIT ta_unit[] = {
@@ -580,7 +582,7 @@ if (ta_xb == NULL)
     ta_xb = (uint8 *) calloc (TA_MAXFR + 2, sizeof (uint8));
 if (ta_xb == NULL)
     return SCPE_MEM;
-return SCPE_OK;
+return auto_config (0, 0);
 }
 
 /* Attach routine */
diff --git a/PDP11/pdp11_tc.c b/PDP11/pdp11_tc.c
index 4fc1fd19..4ca42485 100644
--- a/PDP11/pdp11_tc.c
+++ b/PDP11/pdp11_tc.c
@@ -318,9 +318,11 @@ extern int32 sim_is_running;
    dt_mod       DT modifier list
 */
 
+#define IOLN_TC         012
+
 DIB dt_dib = {
-    IOBA_TC, IOLN_TC, &dt_rd, &dt_wr,
-    1, IVCL (DTA), VEC_DTA, { NULL }
+    IOBA_AUTO, IOLN_TC, &dt_rd, &dt_wr,
+    1, IVCL (DTA), VEC_AUTO, { NULL }
     };
 
 UNIT dt_unit[] = {
@@ -1130,7 +1132,7 @@ for (i = 0; i < DT_NUMDR; i++) {                        /* stop all activity */
 tcst =  tcwc = tcba = tcdt = 0;                         /* clear reg */
 tccm = CSR_DONE;
 CLR_INT (DTA);                                          /* clear int req */
-return SCPE_OK;
+return auto_config (0, 0);
 }
 
 /* Device bootstrap */
diff --git a/PDP11/pdp11_tm.c b/PDP11/pdp11_tm.c
index 55a4ef3a..2a08b8f8 100644
--- a/PDP11/pdp11_tm.c
+++ b/PDP11/pdp11_tm.c
@@ -188,9 +188,11 @@ t_stat tm_vlock (UNIT *uptr, int32 val, char *cptr, void *desc);
    tm_mod       MT modifier list
 */
 
+#define IOLN_TM         014
+
 DIB tm_dib = {
-    IOBA_TM, IOLN_TM, &tm_rd, &tm_wr,
-    1, IVCL (TM), VEC_TM, { NULL }
+    IOBA_AUTO, IOLN_TM, &tm_rd, &tm_wr,
+    1, IVCL (TM), VEC_AUTO, { NULL }
     };
 
 UNIT tm_unit[] = {
@@ -596,7 +598,7 @@ if (tmxb == NULL)
     tmxb = (uint8 *) calloc (MT_MAXFR, sizeof (uint8));
 if (tmxb == NULL)
     return SCPE_MEM;
-return SCPE_OK;
+return auto_config (0, 0);
 }
 
 /* Attach routine */
diff --git a/PDP11/pdp11_tq.c b/PDP11/pdp11_tq.c
index 50a0ead3..2dc0605e 100644
--- a/PDP11/pdp11_tq.c
+++ b/PDP11/pdp11_tq.c
@@ -414,8 +414,10 @@ UNIT *tq_getucb (uint32 lu);
    tq_mod       TQ modifier list
 */
 
+#define IOLN_TQ         004
+
 DIB tq_dib = {
-    IOBA_TQ, IOLN_TQ, &tq_rd, &tq_wr,
+    IOBA_AUTO, IOLN_TQ, &tq_rd, &tq_wr,
     1, IVCL (TQ), 0, { &tq_inta }
     };
 
diff --git a/PDP11/pdp11_ts.c b/PDP11/pdp11_ts.c
index e9326eeb..0f86e24e 100644
--- a/PDP11/pdp11_ts.c
+++ b/PDP11/pdp11_ts.c
@@ -306,9 +306,11 @@ int32 ts_map_status (t_stat st);
    ts_mod       TS modifier list
 */
 
+#define IOLN_TS         004
+
 DIB ts_dib = {
-    IOBA_TS, IOLN_TS, &ts_rd, &ts_wr,
-    1, IVCL (TS), VEC_TS, { NULL }
+    IOBA_AUTO, IOLN_TS, &ts_rd, &ts_wr,
+    1, IVCL (TS), VEC_AUTO, { NULL }
     };
 
 UNIT ts_unit = { UDATA (&ts_svc, UNIT_ATTABLE + UNIT_ROABLE + UNIT_DISABLE, 0) };
@@ -1055,7 +1057,7 @@ if (tsxb == NULL)
     tsxb = (uint8 *) calloc (MT_MAXFR, sizeof (uint8));
 if (tsxb == NULL)
     return SCPE_MEM;
-return SCPE_OK;
+return auto_config (0, 0);
 }
 
 /* Attach */
diff --git a/PDP11/pdp11_tu.c b/PDP11/pdp11_tu.c
index ce827ea9..9a746c7e 100644
--- a/PDP11/pdp11_tu.c
+++ b/PDP11/pdp11_tu.c
@@ -933,7 +933,7 @@ if (wbuf == NULL)
     wbuf = (uint16 *) calloc ((MT_MAXFR + 4) >> 1, sizeof (uint16));
 if (wbuf == NULL)
     return SCPE_MEM;
-return SCPE_OK;
+return auto_config(0, 0);
 }
 
 /* Attach routine */
diff --git a/PDP11/pdp11_vh.c b/PDP11/pdp11_vh.c
index c193cbe0..2fa14719 100644
--- a/PDP11/pdp11_vh.c
+++ b/PDP11/pdp11_vh.c
@@ -341,6 +341,7 @@ static t_stat vh_set_nolog (UNIT *uptr, int32 val, char *cptr, void *desc);
 static t_stat vh_show_log (FILE *st, UNIT *uptr, int32 val, void *desc);
 
 /* SIMH I/O Structures */
+
 #define IOLN_VH         020
 
 static DIB vh_dib = {
@@ -425,7 +426,7 @@ DEVICE vh_dev = {
     &vh_attach,     /* attach routine */
     &vh_detach,     /* detach routine */
     (void *)&vh_dib,/* context */
-    DEV_FLTA | DEV_DISABLE | DEV_DIS | DEV_QBUS | DEV_UBUS | DEV_DEBUG,    /* flags */
+    DEV_DISABLE | DEV_DIS | DEV_QBUS | DEV_UBUS | DEV_DEBUG,    /* flags */
     0, vh_debug
 };
 
diff --git a/PDP11/pdp11_xq.c b/PDP11/pdp11_xq.c
index ae147377..07965109 100644
--- a/PDP11/pdp11_xq.c
+++ b/PDP11/pdp11_xq.c
@@ -324,7 +324,10 @@ struct xq_device    xqb = {
   };
 
 /* SIMH device structures */
-DIB xqa_dib = { IOBA_XQ, IOLN_XQ, &xq_rd, &xq_wr,
+
+#define IOLN_XQ         020
+
+DIB xqa_dib = { IOBA_AUTO, IOLN_XQ, &xq_rd, &xq_wr,
 		1, IVCL (XQ), 0, { &xq_int } };
 
 UNIT xqa_unit[] = {
@@ -380,7 +383,7 @@ REG xqa_reg[] = {
   { NULL },
 };
 
-DIB xqb_dib = { IOBA_XQB, IOLN_XQB, &xq_rd, &xq_wr,
+DIB xqb_dib = { IOBA_AUTO, IOLN_XQ, &xq_rd, &xq_wr,
 		1, IVCL (XQ), 0, { &xq_int } };
 
 UNIT xqb_unit[] = {
@@ -484,7 +487,7 @@ DEVICE xq_dev = {
   2, XQ_RDX, 11, 1, XQ_RDX, 16,
   &xq_ex, &xq_dep, &xq_reset,
   NULL, &xq_attach, &xq_detach,
-  &xqa_dib, DEV_FLTA | DEV_DISABLE | DEV_QBUS | DEV_DEBUG,
+  &xqa_dib, DEV_DISABLE | DEV_QBUS | DEV_DEBUG,
   0, xq_debug
 };
 
@@ -493,7 +496,7 @@ DEVICE xqb_dev = {
   2, XQ_RDX, 11, 1, XQ_RDX, 16,
   &xq_ex, &xq_dep, &xq_reset,
   NULL, &xq_attach, &xq_detach,
-  &xqb_dib, DEV_FLTA | DEV_DISABLE | DEV_DIS | DEV_QBUS | DEV_DEBUG,
+  &xqb_dib, DEV_DISABLE | DEV_DIS | DEV_QBUS | DEV_DEBUG,
   0, xq_debug
 };
 
diff --git a/PDP11/pdp11_xu.c b/PDP11/pdp11_xu.c
index 0a7b54d2..7d873dbe 100644
--- a/PDP11/pdp11_xu.c
+++ b/PDP11/pdp11_xu.c
@@ -129,8 +129,10 @@ void xu_dump_rxring(CTLR* xu);
 void xu_dump_txring(CTLR* xu);
 t_stat xu_show_filters (FILE* st, UNIT* uptr, int32 val, void* desc);
 
-DIB xua_dib = { IOBA_XU, IOLN_XU, &xu_rd, &xu_wr,
-1, IVCL (XU), VEC_XU, {&xu_int} };
+#define IOLN_XU        010
+
+DIB xua_dib = { IOBA_AUTO, IOLN_XU, &xu_rd, &xu_wr,
+1, IVCL (XU), VEC_AUTO, {&xu_int} };
 
 UNIT xua_unit[] = {
  { UDATA (&xu_svc, UNIT_IDLE|UNIT_ATTABLE|UNIT_DISABLE, 0) },     /* receive timer */
@@ -190,15 +192,13 @@ DEVICE xu_dev = {
 	2, XU_RDX, 8, 1, XU_RDX, 8,
 	&xu_ex, &xu_dep, &xu_reset,
 	NULL, &xu_attach, &xu_detach,
-	&xua_dib, DEV_FLTA | DEV_DISABLE | DEV_DIS | DEV_UBUS | DEV_DEBUG,
+	&xua_dib, DEV_DISABLE | DEV_DIS | DEV_UBUS | DEV_DEBUG,
   0, xu_debug
   };
 
+#define IOLN_XU         010
 
-/* XUB does not exist in the PDP10 simulation */
-#if defined(IOBA_XUB)
-
-DIB xub_dib = { IOBA_XUB, IOLN_XUB, &xu_rd, &xu_wr,
+DIB xub_dib = { IOBA_FLOAT, IOLN_XU, &xu_rd, &xu_wr,
 		1, IVCL (XU), 0, { &xu_int } };
 
 UNIT xub_unit[] = {
@@ -220,7 +220,7 @@ DEVICE xub_dev = {
   1, XU_RDX, 8, 1, XU_RDX, 8,
   &xu_ex, &xu_dep, &xu_reset,
   NULL, &xu_attach, &xu_detach,
-  &xub_dib, DEV_FLTA | DEV_DISABLE | DEV_DIS | DEV_UBUS | DEV_DEBUG,
+  &xub_dib, DEV_DISABLE | DEV_DIS | DEV_UBUS | DEV_DEBUG,
   0, xu_debug
 };
 
@@ -229,12 +229,6 @@ CTLR xu_ctrl[] = {
    {&xu_dev,  xua_unit, &xua_dib, &xua}       /* XUA controller */
   ,{&xub_dev, xub_unit, &xub_dib, &xub}       /* XUB controller */
 };
-#else /* IOBA_XUB */
-#define XU_MAX_CONTROLLERS 1
-CTLR xu_ctrl[] = {
-   {&xu_dev,  xua_unit, &xua_dib, &xua}       /* XUA controller */
-}; 
-#endif /* IOBA_XUB */
 
 /*============================================================================*/
 
diff --git a/VAX/vax610_defs.h b/VAX/vax610_defs.h
index d90b9f83..b03c3e46 100644
--- a/VAX/vax610_defs.h
+++ b/VAX/vax610_defs.h
@@ -163,11 +163,9 @@
 #define DEV_V_UBUS      (DEV_V_UF + 0)                  /* Unibus */
 #define DEV_V_QBUS      (DEV_V_UF + 1)                  /* Qbus */
 #define DEV_V_Q18       (DEV_V_UF + 2)                  /* Qbus, mem <= 256KB */
-#define DEV_V_FLTA      (DEV_V_UF + 3)                  /* flt addr */
 #define DEV_UBUS        (1u << DEV_V_UBUS)
 #define DEV_QBUS        (1u << DEV_V_QBUS)
 #define DEV_Q18         (1u << DEV_V_Q18)
-#define DEV_FLTA        (1u << DEV_V_FLTA)
 
 #define UNIBUS          FALSE                           /* 22b only */
 
@@ -188,54 +186,11 @@ typedef struct {
     int32               (*ack[VEC_DEVMAX])(void);       /* ack routine */
     } DIB;
 
-/* I/O page layout - RQB,RQC,RQD float based on number of DZ's */
+/* Qbus I/O page layout - see pdp11_ui_lib.c for address layout details */
 
+#define IOBA_AUTO       (0)                             /* Assigned by Auto Configure */
 #define IOBA_FLOAT      (0)                             /* Assigned by Auto Configure */
 
-#define IOBA_DZ         (IOPAGEBASE + 000100)           /* DZ11 */
-#define IOLN_DZ         010
-#define IOBA_RQB        (IOPAGEBASE + 000334 +  (020 * (DZ_MUXES / 2)))
-#define IOLN_RQB        004
-#define IOBA_RQC        (IOPAGEBASE + IOBA_RQB + IOLN_RQB)
-#define IOLN_RQC        004
-#define IOBA_RQD        (IOPAGEBASE + IOBA_RQC + IOLN_RQC)
-#define IOLN_RQD        004
-#define IOBA_MEM        (IOPAGEBASE + 012100)           /* MSV11-P */
-#define IOLN_MEM        040
-#define IOBA_RQ         (IOPAGEBASE + 012150)           /* RQDX3 */
-#define IOLN_RQ         004
-#define IOBA_TS         (IOPAGEBASE + 012520)           /* TS11 */
-#define IOLN_TS         004
-#define IOBA_RL         (IOPAGEBASE + 014400)           /* RL11 */
-#define IOLN_RL         012
-#define IOBA_XQ         (IOPAGEBASE + 014440)           /* DEQNA/DELQA */
-#define IOLN_XQ         020
-#define IOBA_XQB        (IOPAGEBASE + 014460)           /* 2nd DEQNA/DELQA */
-#define IOLN_XQB        020
-#define IOBA_TQ         (IOPAGEBASE + 014500)           /* TMSCP */
-#define IOLN_TQ         004
-#define IOBA_XU         (IOPAGEBASE + 014510)           /* DEUNA/DELUA */
-#define IOLN_XU         010
-#define IOBA_RP         (IOPAGEBASE + 016700)           /* RP/RM */
-#define IOLN_RP         054
-#define IOBA_CR         (IOPAGEBASE + 017160)           /* CD/CR/CM */
-#define IOLN_CR         010
-#define IOBA_RX         (IOPAGEBASE + 017170)           /* RXV11 */
-#define IOLN_RX         004
-#define IOBA_RY         (IOPAGEBASE + 017170)           /* RXV21 */
-#define IOLN_RY         004
-#define IOBA_QVSS       (IOPAGEBASE + 017200)           /* QVSS */
-#define IOLN_QVSS       0100
-#define IOBA_QDSS       (IOPAGEBASE + 017400)           /* QDSS */
-#define IOLN_QDSS       002
-#define IOBA_DBL        (IOPAGEBASE + 017500)           /* doorbell */
-#define IOLN_DBL        002
-#define IOBA_LPT        (IOPAGEBASE + 017514)           /* LP11 */
-#define IOLN_LPT        004
-#define IOBA_PTR        (IOPAGEBASE + 017550)           /* PC11 reader */
-#define IOLN_PTR        004
-#define IOBA_PTP        (IOPAGEBASE + 017554)           /* PC11 punch */
-#define IOLN_PTP        004
 
 /* The KA610 maintains 4 separate hardware IPL levels, IPL 17 to IPL 14;
    however, DEC Qbus controllers all interrupt on IPL 14
@@ -331,26 +286,11 @@ typedef struct {
 
 /* Device vectors */
 
+#define VEC_AUTO        (0)                             /* Assigned by Auto Configure */
 #define VEC_FLOAT       (0)                             /* Assigned by Auto Configure */
 
 #define VEC_QBUS        1                               /* Qbus system */
 #define VEC_Q           0x200                           /* Qbus vector offset */
-#define VEC_PTR         (VEC_Q + 0070)
-#define VEC_PTP         (VEC_Q + 0074)
-#define VEC_XQ          (VEC_Q + 0120)
-#define VEC_XU          (VEC_Q + 0120)
-#define VEC_RQ          (VEC_Q + 0154)
-#define VEC_RL          (VEC_Q + 0160)
-#define VEC_LPT         (VEC_Q + 0200)
-#define VEC_TS          (VEC_Q + 0224)
-#define VEC_CR          (VEC_Q + 0230)
-#define VEC_TQ          (VEC_Q + 0260)
-#define VEC_RX          (VEC_Q + 0264)
-#define VEC_RY          (VEC_Q + 0264)
-#define VEC_DZRX        (VEC_Q + 0300)
-#define VEC_DZTX        (VEC_Q + 0304)
-#define VEC_VHRX        (VEC_Q + 0310)   
-#define VEC_VHTX        (VEC_Q + 0314)
 
 /* Interrupt macros */
 
diff --git a/VAX/vax610_io.c b/VAX/vax610_io.c
index 97b53f3d..4cded759 100644
--- a/VAX/vax610_io.c
+++ b/VAX/vax610_io.c
@@ -71,7 +71,7 @@ MTAB qba_mod[] = {
     };
 
 DEVICE qba_dev = {
-    "QBA", &qba_unit, qba_reg, qba_mod,
+    "QBUS", &qba_unit, qba_reg, qba_mod,
     1, 16, 4, 2, 16, 16,
     NULL, NULL, &qba_reset,
     NULL, NULL, NULL,
diff --git a/VAX/vax610_mem.c b/VAX/vax610_mem.c
index 2275f0ba..b00b6c4d 100644
--- a/VAX/vax610_mem.c
+++ b/VAX/vax610_mem.c
@@ -52,8 +52,10 @@ t_stat mctl_reset (DEVICE *dptr);
    mctl_mod       MCTL modifier list
 */
 
+#define IOLN_MEM        040
+
 DIB mctl_dib = {
-    IOBA_MEM, IOLN_MEM, &mctl_rd, &mctl_wr,
+    IOBA_AUTO, IOLN_MEM, &mctl_rd, &mctl_wr,
     1, 0, 0, { NULL }
     };
 
diff --git a/VAX/vax630_defs.h b/VAX/vax630_defs.h
index 9e91fa1a..0f9e0aee 100644
--- a/VAX/vax630_defs.h
+++ b/VAX/vax630_defs.h
@@ -208,11 +208,9 @@
 #define DEV_V_UBUS      (DEV_V_UF + 0)                  /* Unibus */
 #define DEV_V_QBUS      (DEV_V_UF + 1)                  /* Qbus */
 #define DEV_V_Q18       (DEV_V_UF + 2)                  /* Qbus, mem <= 256KB */
-#define DEV_V_FLTA      (DEV_V_UF + 3)                  /* flt addr */
 #define DEV_UBUS        (1u << DEV_V_UBUS)
 #define DEV_QBUS        (1u << DEV_V_QBUS)
 #define DEV_Q18         (1u << DEV_V_Q18)
-#define DEV_FLTA        (1u << DEV_V_FLTA)
 
 #define UNIBUS          FALSE                           /* 22b only */
 
@@ -233,52 +231,11 @@ typedef struct {
     int32               (*ack[VEC_DEVMAX])(void);       /* ack routine */
     } DIB;
 
-/* I/O page layout - RQB,RQC,RQD float based on number of DZ's */
+/* Qbus I/O page layout - see pdp11_ui_lib.c for address layout details */
 
+#define IOBA_AUTO       (0)                             /* Assigned by Auto Configure */
 #define IOBA_FLOAT      (0)                             /* Assigned by Auto Configure */
 
-#define IOBA_DZ         (IOPAGEBASE + 000100)           /* DZ11 */
-#define IOLN_DZ         010
-#define IOBA_RQB        (IOPAGEBASE + 000334 +  (020 * (DZ_MUXES / 2)))
-#define IOLN_RQB        004
-#define IOBA_RQC        (IOPAGEBASE + IOBA_RQB + IOLN_RQB)
-#define IOLN_RQC        004
-#define IOBA_RQD        (IOPAGEBASE + IOBA_RQC + IOLN_RQC)
-#define IOLN_RQD        004
-#define IOBA_RQ         (IOPAGEBASE + 012150)           /* RQDX3 */
-#define IOLN_RQ         004
-#define IOBA_TS         (IOPAGEBASE + 012520)           /* TS11 */
-#define IOLN_TS         004
-#define IOBA_RL         (IOPAGEBASE + 014400)           /* RL11 */
-#define IOLN_RL         012
-#define IOBA_XQ         (IOPAGEBASE + 014440)           /* DEQNA/DELQA */
-#define IOLN_XQ         020
-#define IOBA_XQB        (IOPAGEBASE + 014460)           /* 2nd DEQNA/DELQA */
-#define IOLN_XQB        020
-#define IOBA_TQ         (IOPAGEBASE + 014500)           /* TMSCP */
-#define IOLN_TQ         004
-#define IOBA_XU         (IOPAGEBASE + 014510)           /* DEUNA/DELUA */
-#define IOLN_XU         010
-#define IOBA_RP         (IOPAGEBASE + 016700)           /* RP/RM */
-#define IOLN_RP         054
-#define IOBA_CR         (IOPAGEBASE + 017160)           /* CD/CR/CM */
-#define IOLN_CR         010
-#define IOBA_RX         (IOPAGEBASE + 017170)           /* RXV11 */
-#define IOLN_RX         004
-#define IOBA_RY         (IOPAGEBASE + 017170)           /* RXV21 */
-#define IOLN_RY         004
-#define IOBA_QVSS       (IOPAGEBASE + 017200)           /* QVSS */
-#define IOLN_QVSS       0100
-#define IOBA_QDSS       (IOPAGEBASE + 017400)           /* QDSS */
-#define IOLN_QDSS       002
-#define IOBA_DBL        (IOPAGEBASE + 017500)           /* doorbell */
-#define IOLN_DBL        002
-#define IOBA_LPT        (IOPAGEBASE + 017514)           /* LP11 */
-#define IOLN_LPT        004
-#define IOBA_PTR        (IOPAGEBASE + 017550)           /* PC11 reader */
-#define IOLN_PTR        004
-#define IOBA_PTP        (IOPAGEBASE + 017554)           /* PC11 punch */
-#define IOLN_PTP        004
 
 /* The KA620/KA630 maintains 4 separate hardware IPL levels, IPL 17 to IPL 14;
    however, DEC Qbus controllers all interrupt on IPL 14
@@ -380,26 +337,11 @@ typedef struct {
 
 /* Device vectors */
 
+#define VEC_AUTO        (0)                             /* Assigned by Auto Configure */
 #define VEC_FLOAT       (0)                             /* Assigned by Auto Configure */
 
 #define VEC_QBUS        1                               /* Qbus system */
 #define VEC_Q           0x200                           /* Qbus vector offset */
-#define VEC_PTR         (VEC_Q + 0070)
-#define VEC_PTP         (VEC_Q + 0074)
-#define VEC_XQ          (VEC_Q + 0120)
-#define VEC_XU          (VEC_Q + 0120)
-#define VEC_RQ          (VEC_Q + 0154)
-#define VEC_RL          (VEC_Q + 0160)
-#define VEC_LPT         (VEC_Q + 0200)
-#define VEC_TS          (VEC_Q + 0224)
-#define VEC_CR          (VEC_Q + 0230)
-#define VEC_TQ          (VEC_Q + 0260)
-#define VEC_RX          (VEC_Q + 0264)
-#define VEC_RY          (VEC_Q + 0264)
-#define VEC_DZRX        (VEC_Q + 0300)
-#define VEC_DZTX        (VEC_Q + 0304)
-#define VEC_VHRX        (VEC_Q + 0310)   
-#define VEC_VHTX        (VEC_Q + 0314)
 
 /* Interrupt macros */
 
diff --git a/VAX/vax630_io.c b/VAX/vax630_io.c
index 8fa0ef9a..f8656a9e 100644
--- a/VAX/vax630_io.c
+++ b/VAX/vax630_io.c
@@ -89,7 +89,9 @@ t_stat qba_show_virt (FILE *of, UNIT *uptr, int32 val, void *desc);
    qba_reg      QBA register list
 */
 
-DIB qba_dib = { IOBA_DBL, IOLN_DBL, &dbl_rd, &dbl_wr, 0 };
+#define IOLN_DBL        002
+
+DIB qba_dib = { IOBA_AUTO, IOLN_DBL, &dbl_rd, &dbl_wr, 0 };
 
 UNIT qba_unit = { UDATA (NULL, 0, 0) };
 
diff --git a/VAX/vax730_defs.h b/VAX/vax730_defs.h
index 46905c0d..6e60bf5e 100644
--- a/VAX/vax730_defs.h
+++ b/VAX/vax730_defs.h
@@ -201,11 +201,9 @@
 
 #define DEV_V_UBUS      (DEV_V_UF + 0)                  /* Unibus */
 #define DEV_V_NEXUS     (DEV_V_UF + 1)                  /* Nexus */
-#define DEV_V_FLTA      (DEV_V_UF + 2)                  /* flt addr */
-#define DEV_V_FFUF      (DEV_V_UF + 3)                  /* first free flag */
+#define DEV_V_FFUF      (DEV_V_UF + 2)                  /* first free flag */
 #define DEV_UBUS        (1u << DEV_V_UBUS)
 #define DEV_NEXUS       (1u << DEV_V_NEXUS)
-#define DEV_FLTA        (1u << DEV_V_FLTA)
 #define DEV_QBUS        (0)
 #define DEV_Q18         (0)
 
@@ -232,53 +230,11 @@ typedef struct {
     int32               (*ack[VEC_DEVMAX])(void);       /* ack routine */
     } DIB;
 
-/* Unibus I/O page layout - XUB,RQB,RQC,RQD float based on number of DZ's */
+/* Unibus I/O page layout - see pdp11_ui_lib.c for address layout details */
 
+#define IOBA_AUTO       (0)                             /* Assigned by Auto Configure */
 #define IOBA_FLOAT      (0)                             /* Assigned by Auto Configure */
 
-#define IOBA_DZ         (IOPAGEBASE + 000100)           /* DZ11 */
-#define IOLN_DZ         010
-#define IOBA_XUB        (IOPAGEBASE + 000330 + (020 * (DZ_MUXES / 2)))
-#define IOLN_XUB        010
-#define IOBA_RQB        (IOPAGEBASE + 000334 +  (020 * (DZ_MUXES / 2)))
-#define IOLN_RQB        004
-#define IOBA_RQC        (IOPAGEBASE + IOBA_RQB + IOLN_RQB)
-#define IOLN_RQC        004
-#define IOBA_RQD        (IOPAGEBASE + IOBA_RQC + IOLN_RQC)
-#define IOLN_RQD        004
-#define IOBA_RQ         (IOPAGEBASE + 012150)           /* UDA50 */
-#define IOLN_RQ         004
-#define IOBA_TS         (IOPAGEBASE + 012520)           /* TS11 */
-#define IOLN_TS         004
-#define IOBA_RL         (IOPAGEBASE + 014400)           /* RL11 */
-#define IOLN_RL         012
-#define IOBA_XQ         (IOPAGEBASE + 014440)           /* DEQNA/DELQA */
-#define IOLN_XQ         020
-#define IOBA_XQB        (IOPAGEBASE + 014460)           /* 2nd DEQNA/DELQA */
-#define IOLN_XQB        020
-#define IOBA_TQ         (IOPAGEBASE + 014500)           /* TMSCP */
-#define IOLN_TQ         004
-#define IOBA_XU         (IOPAGEBASE + 014510)           /* DEUNA/DELUA */
-#define IOLN_XU         010
-#define IOBA_RB         (IOPAGEBASE + 015606)           /* RB730 */
-#define IOLN_RB         002
-#define IOBA_CR         (IOPAGEBASE + 017160)           /* CD/CR/CM */
-#define IOLN_CR         010
-#define IOBA_RX         (IOPAGEBASE + 017170)           /* RX11 */
-#define IOLN_RX         004
-#define IOBA_RY         (IOPAGEBASE + 017170)           /* RXV21 */
-#define IOLN_RY         004
-#define IOBA_QDSS       (IOPAGEBASE + 017400)           /* QDSS */
-#define IOLN_QDSS       002
-#define IOBA_HK         (IOPAGEBASE + 017440)           /* RK611 */
-#define IOLN_HK         040
-#define IOBA_LPT        (IOPAGEBASE + 017514)           /* LP11 */
-#define IOLN_LPT        004
-#define IOBA_PTR        (IOPAGEBASE + 017550)           /* PC11 reader */
-#define IOLN_PTR        004
-#define IOBA_PTP        (IOPAGEBASE + 017554)           /* PC11 punch */
-#define IOLN_PTP        004
-
 /* Interrupt assignments; within each level, priority is right to left */
 
 #define INT_V_DZRX      0                               /* BR5 */
@@ -341,26 +297,11 @@ typedef struct {
 
 /* Device vectors */
 
+#define VEC_AUTO        (0)                             /* Assigned by Auto Configure */
 #define VEC_FLOAT       (0)                             /* Assigned by Auto Configure */
 
 #define VEC_QBUS        0
 #define VEC_Q           0x200
-#define VEC_PTR         (VEC_Q + 0070)
-#define VEC_PTP         (VEC_Q + 0074)
-#define VEC_XQ          (VEC_Q + 0120)
-#define VEC_XU          (VEC_Q + 0120)
-#define VEC_RQ          (VEC_Q + 0154)
-#define VEC_RL          (VEC_Q + 0160)
-#define VEC_LPT         (VEC_Q + 0200)
-#define VEC_HK          (VEC_Q + 0210)
-#define VEC_TS          (VEC_Q + 0224)
-#define VEC_CR          (VEC_Q + 0230)
-#define VEC_RB          (VEC_Q + 0250)
-#define VEC_TQ          (VEC_Q + 0260)
-#define VEC_RX          (VEC_Q + 0264)
-#define VEC_RY          (VEC_Q + 0264)
-#define VEC_DZRX        (VEC_Q + 0300)
-#define VEC_DZTX        (VEC_Q + 0304)
 
 /* Interrupt macros */
 
diff --git a/VAX/vax730_rb.c b/VAX/vax730_rb.c
index 66dd8826..2400d640 100644
--- a/VAX/vax730_rb.c
+++ b/VAX/vax730_rb.c
@@ -228,9 +228,11 @@ t_stat rb_set_bad (UNIT *uptr, int32 val, char *cptr, void *desc);
    rb_mod       RB modifier list
 */
 
+#define IOLN_RB         002
+
 DIB rb_dib = {
-    IOBA_RB, IOLN_RB, &rb_rd16, &rb_wr16,
-    1, IVCL (RB), VEC_RB, { NULL } };
+    IOBA_AUTO, IOLN_RB, &rb_rd16, &rb_wr16,
+    1, IVCL (RB), VEC_AUTO, { NULL } };
 
 UNIT rb_unit[] = {
     { UDATA (&rb_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+
diff --git a/VAX/vax730_sys.c b/VAX/vax730_sys.c
index 36c6fa1b..dfeddbba 100644
--- a/VAX/vax730_sys.c
+++ b/VAX/vax730_sys.c
@@ -530,8 +530,10 @@ else if (*regptr != 0)
 for (i = 0; boot_tab[i].name != NULL; i++) {
     if (strcmp (dptr->name, boot_tab[i].name) == 0) {
         R[0] = boot_tab[i].code;
-        if (boot_tab[i].code == BOOT_RB)                /* vector set by console for RB730 */
-            R[0] = R[0] | ((VEC_RB - VEC_Q) << 16);
+        if (boot_tab[i].code == BOOT_RB) {              /* vector set by console for RB730 */
+            extern DIB rb_dib;
+            R[0] = R[0] | ((rb_dib.vec - VEC_Q) << 16);
+            }
         R[1] = TR_UBA;
         R[2] = boot_tab[i].let | (ba & UBADDRMASK);
         R[3] = unitno;
diff --git a/VAX/vax750_defs.h b/VAX/vax750_defs.h
index b186b78b..07b0b8ec 100644
--- a/VAX/vax750_defs.h
+++ b/VAX/vax750_defs.h
@@ -228,14 +228,12 @@
 #define DEV_V_UBUS      (DEV_V_UF + 0)                  /* Unibus */
 #define DEV_V_MBUS      (DEV_V_UF + 1)                  /* Massbus */
 #define DEV_V_NEXUS     (DEV_V_UF + 2)                  /* Nexus */
-#define DEV_V_FLTA      (DEV_V_UF + 3)                  /* flt addr */
-#define DEV_V_CI        (DEV_V_UF + 4)                  /* CI */
-#define DEV_V_FFUF      (DEV_V_UF + 5)                  /* first free flag */
+#define DEV_V_CI        (DEV_V_UF + 3)                  /* CI */
+#define DEV_V_FFUF      (DEV_V_UF + 4)                  /* first free flag */
 #define DEV_UBUS        (1u << DEV_V_UBUS)
 #define DEV_MBUS        (1u << DEV_V_MBUS)
 #define DEV_NEXUS       (1u << DEV_V_NEXUS)
 #define DEV_CI          (1u << DEV_V_CI)
-#define DEV_FLTA        (1u << DEV_V_FLTA)
 #define DEV_QBUS        (0)
 #define DEV_Q18         (0)
 
@@ -267,51 +265,12 @@ typedef struct {
     int32               (*ack[VEC_DEVMAX])(void);       /* ack routine */
     } DIB;
 
-/* Unibus I/O page layout - XUB,RQB,RQC,RQD float based on number of DZ's
+/* Unibus I/O page layout - see pdp11_ui_lib.c for address layout details
    Massbus devices (RP, TU) do not appear in the Unibus IO page */
 
+#define IOBA_AUTO       (0)                             /* Assigned by Auto Configure */
 #define IOBA_FLOAT      (0)                             /* Assigned by Auto Configure */
 
-#define IOBA_DZ         (IOPAGEBASE + 000100)           /* DZ11 */
-#define IOLN_DZ         010
-#define IOBA_XUB        (IOPAGEBASE + 000330 + (020 * (DZ_MUXES / 2)))
-#define IOLN_XUB        010
-#define IOBA_RQB        (IOPAGEBASE + 000334 +  (020 * (DZ_MUXES / 2)))
-#define IOLN_RQB        004
-#define IOBA_RQC        (IOPAGEBASE + IOBA_RQB + IOLN_RQB)
-#define IOLN_RQC        004
-#define IOBA_RQD        (IOPAGEBASE + IOBA_RQC + IOLN_RQC)
-#define IOLN_RQD        004
-#define IOBA_RQ         (IOPAGEBASE + 012150)           /* UDA50 */
-#define IOLN_RQ         004
-#define IOBA_TS         (IOPAGEBASE + 012520)           /* TS11 */
-#define IOLN_TS         004
-#define IOBA_RL         (IOPAGEBASE + 014400)           /* RL11 */
-#define IOLN_RL         012
-#define IOBA_XQ         (IOPAGEBASE + 014440)           /* DEQNA/DELQA */
-#define IOLN_XQ         020
-#define IOBA_XQB        (IOPAGEBASE + 014460)           /* 2nd DEQNA/DELQA */
-#define IOLN_XQB        020
-#define IOBA_TQ         (IOPAGEBASE + 014500)           /* TMSCP */
-#define IOLN_TQ         004
-#define IOBA_XU         (IOPAGEBASE + 014510)           /* DEUNA/DELUA */
-#define IOLN_XU         010
-#define IOBA_CR         (IOPAGEBASE + 017160)           /* CD/CR/CM */
-#define IOLN_CR         010
-#define IOBA_RX         (IOPAGEBASE + 017170)           /* RX11 */
-#define IOLN_RX         004
-#define IOBA_RY         (IOPAGEBASE + 017170)           /* RXV21 */
-#define IOLN_RY         004
-#define IOBA_QDSS       (IOPAGEBASE + 017400)           /* QDSS */
-#define IOLN_QDSS       002
-#define IOBA_HK         (IOPAGEBASE + 017440)           /* RK611 */
-#define IOLN_HK         040
-#define IOBA_LPT        (IOPAGEBASE + 017514)           /* LP11 */
-#define IOLN_LPT        004
-#define IOBA_PTR        (IOPAGEBASE + 017550)           /* PC11 reader */
-#define IOLN_PTR        004
-#define IOBA_PTP        (IOPAGEBASE + 017554)           /* PC11 punch */
-#define IOLN_PTP        004
 
 /* Interrupt assignments; within each level, priority is right to left */
 
@@ -372,25 +331,11 @@ typedef struct {
 
 /* Device vectors */
 
+#define VEC_AUTO        (0)                             /* Assigned by Auto Configure */
 #define VEC_FLOAT       (0)                             /* Assigned by Auto Configure */
 
 #define VEC_QBUS        0
 #define VEC_Q           0x200
-#define VEC_PTR         (VEC_Q + 0070)
-#define VEC_PTP         (VEC_Q + 0074)
-#define VEC_XQ          (VEC_Q + 0120)
-#define VEC_XU          (VEC_Q + 0120)
-#define VEC_RQ          (VEC_Q + 0154)
-#define VEC_RL          (VEC_Q + 0160)
-#define VEC_LPT         (VEC_Q + 0200)
-#define VEC_HK          (VEC_Q + 0210)
-#define VEC_TS          (VEC_Q + 0224)
-#define VEC_CR          (VEC_Q + 0230)
-#define VEC_TQ          (VEC_Q + 0260)
-#define VEC_RX          (VEC_Q + 0264)
-#define VEC_RY          (VEC_Q + 0264)
-#define VEC_DZRX        (VEC_Q + 0300)
-#define VEC_DZTX        (VEC_Q + 0304)
 
 /* Interrupt macros */
 
diff --git a/VAX/vax780_defs.h b/VAX/vax780_defs.h
index 8305a58c..1f38cb8e 100644
--- a/VAX/vax780_defs.h
+++ b/VAX/vax780_defs.h
@@ -237,12 +237,10 @@
 #define DEV_V_UBUS      (DEV_V_UF + 0)                  /* Unibus */
 #define DEV_V_MBUS      (DEV_V_UF + 1)                  /* Massbus */
 #define DEV_V_NEXUS     (DEV_V_UF + 2)                  /* Nexus */
-#define DEV_V_FLTA      (DEV_V_UF + 3)                  /* flt addr */
-#define DEV_V_FFUF      (DEV_V_UF + 4)                  /* first free flag */
+#define DEV_V_FFUF      (DEV_V_UF + 3)                  /* first free flag */
 #define DEV_UBUS        (1u << DEV_V_UBUS)
 #define DEV_MBUS        (1u << DEV_V_MBUS)
 #define DEV_NEXUS       (1u << DEV_V_NEXUS)
-#define DEV_FLTA        (1u << DEV_V_FLTA)
 #define DEV_QBUS        (0)
 #define DEV_Q18         (0)
 
@@ -274,51 +272,12 @@ typedef struct {
     int32               (*ack[VEC_DEVMAX])(void);       /* ack routine */
     } DIB;
 
-/* Unibus I/O page layout - XUB,RQB,RQC,RQD float based on number of DZ's
+/* Unibus I/O page layout - see pdp11_ui_lib.c for address layout details
    Massbus devices (RP, TU) do not appear in the Unibus IO page */
 
+#define IOBA_AUTO       (0)                             /* Assigned by Auto Configure */
 #define IOBA_FLOAT      (0)                             /* Assigned by Auto Configure */
 
-#define IOBA_DZ         (IOPAGEBASE + 000100)           /* DZ11 */
-#define IOLN_DZ         010
-#define IOBA_XUB        (IOPAGEBASE + 000330 + (020 * (DZ_MUXES / 2)))
-#define IOLN_XUB        010
-#define IOBA_RQB        (IOPAGEBASE + 000334 +  (020 * (DZ_MUXES / 2)))
-#define IOLN_RQB        004
-#define IOBA_RQC        (IOPAGEBASE + IOBA_RQB + IOLN_RQB)
-#define IOLN_RQC        004
-#define IOBA_RQD        (IOPAGEBASE + IOBA_RQC + IOLN_RQC)
-#define IOLN_RQD        004
-#define IOBA_RQ         (IOPAGEBASE + 012150)           /* UDA50 */
-#define IOLN_RQ         004
-#define IOBA_TS         (IOPAGEBASE + 012520)           /* TS11 */
-#define IOLN_TS         004
-#define IOBA_RL         (IOPAGEBASE + 014400)           /* RL11 */
-#define IOLN_RL         012
-#define IOBA_XQ         (IOPAGEBASE + 014440)           /* DEQNA/DELQA */
-#define IOLN_XQ         020
-#define IOBA_XQB        (IOPAGEBASE + 014460)           /* 2nd DEQNA/DELQA */
-#define IOLN_XQB        020
-#define IOBA_TQ         (IOPAGEBASE + 014500)           /* TMSCP */
-#define IOLN_TQ         004
-#define IOBA_XU         (IOPAGEBASE + 014510)           /* DEUNA/DELUA */
-#define IOLN_XU         010
-#define IOBA_CR         (IOPAGEBASE + 017160)           /* CD/CR/CM */
-#define IOLN_CR         010
-#define IOBA_RX         (IOPAGEBASE + 017170)           /* RX11 */
-#define IOLN_RX         004
-#define IOBA_RY         (IOPAGEBASE + 017170)           /* RXV21 */
-#define IOLN_RY         004
-#define IOBA_QDSS       (IOPAGEBASE + 017400)           /* QDSS */
-#define IOLN_QDSS       002
-#define IOBA_HK         (IOPAGEBASE + 017440)           /* RK611 */
-#define IOLN_HK         040
-#define IOBA_LPT        (IOPAGEBASE + 017514)           /* LP11 */
-#define IOLN_LPT        004
-#define IOBA_PTR        (IOPAGEBASE + 017550)           /* PC11 reader */
-#define IOLN_PTR        004
-#define IOBA_PTP        (IOPAGEBASE + 017554)           /* PC11 punch */
-#define IOLN_PTP        004
 
 /* Interrupt assignments; within each level, priority is right to left */
 
@@ -379,25 +338,11 @@ typedef struct {
 
 /* Device vectors */
 
+#define VEC_AUTO        (0)                             /* Assigned by Auto Configure */
 #define VEC_FLOAT       (0)                             /* Assigned by Auto Configure */
 
 #define VEC_QBUS        0
 #define VEC_Q           0000
-#define VEC_PTR         0070
-#define VEC_PTP         0074
-#define VEC_XQ          0120
-#define VEC_XU          0120
-#define VEC_RQ          0154
-#define VEC_RL          0160
-#define VEC_LPT         0200
-#define VEC_HK          0210
-#define VEC_TS          0224
-#define VEC_CR          0230
-#define VEC_TQ          0260
-#define VEC_RX          0264
-#define VEC_RY          0264
-#define VEC_DZRX        0300
-#define VEC_DZTX        0304
 
 /* Interrupt macros */
 
diff --git a/VAX/vax780_stddev.c b/VAX/vax780_stddev.c
index a3bf1669..ce18fc44 100644
--- a/VAX/vax780_stddev.c
+++ b/VAX/vax780_stddev.c
@@ -390,7 +390,7 @@ MTAB fl_mod[] = {
     };
 
 DEVICE fl_dev = {
-    "RX", &fl_unit, fl_reg, fl_mod,
+    "RXC", &fl_unit, fl_reg, fl_mod,
     1, DEV_RDX, 20, 1, DEV_RDX, 8,
     NULL, NULL, &fl_reset,
     NULL, NULL, NULL,
diff --git a/VAX/vax_cpu.c b/VAX/vax_cpu.c
index 8327513b..ddb18481 100644
--- a/VAX/vax_cpu.c
+++ b/VAX/vax_cpu.c
@@ -3141,8 +3141,8 @@ PSL = PSL_IS | PSL_IPL1F;
 SISR = 0;
 ASTLVL = 4;
 mapen = 0;
-FLUSH_ISTR;                                             /* init I-stream */
-if (M == NULL) {                                        /* first time init? */
+FLUSH_ISTR;                             /* init I-stream */
+if (M == NULL) {                        /* first time init? */
     sim_brk_types = sim_brk_dflt = SWMASK ('E');
     pcq_r = find_reg ("PCQ", NULL, dptr);
     if (pcq_r == NULL)
@@ -3151,6 +3151,7 @@ if (M == NULL) {                                        /* first time init? */
     M = (uint32 *) calloc (((uint32) MEMSIZE) >> 2, sizeof (uint32));
     if (M == NULL)
         return SCPE_MEM;
+    auto_config(NULL, 0);               /* do an initial auto configure */
     }
 return build_dib_tab ();
 }
diff --git a/VAX/vax_io.c b/VAX/vax_io.c
index 95b46073..32c78a75 100644
--- a/VAX/vax_io.c
+++ b/VAX/vax_io.c
@@ -143,7 +143,9 @@ t_stat qba_show_virt (FILE *of, UNIT *uptr, int32 val, void *desc);
    qba_reg      QBA register list
 */
 
-DIB qba_dib = { IOBA_DBL, IOLN_DBL, &dbl_rd, &dbl_wr, 0 };
+#define IOLN_DBL        002
+
+DIB qba_dib = { IOBA_AUTO, IOLN_DBL, &dbl_rd, &dbl_wr, 0 };
 
 UNIT qba_unit = { UDATA (NULL, 0, 0) };
 
diff --git a/VAX/vaxmod_defs.h b/VAX/vaxmod_defs.h
index 3e56d146..61c99010 100644
--- a/VAX/vaxmod_defs.h
+++ b/VAX/vaxmod_defs.h
@@ -258,11 +258,9 @@
 #define DEV_V_UBUS      (DEV_V_UF + 0)                  /* Unibus */
 #define DEV_V_QBUS      (DEV_V_UF + 1)                  /* Qbus */
 #define DEV_V_Q18       (DEV_V_UF + 2)                  /* Qbus, mem <= 256KB */
-#define DEV_V_FLTA      (DEV_V_UF + 3)                  /* flt addr */
 #define DEV_UBUS        (1u << DEV_V_UBUS)
 #define DEV_QBUS        (1u << DEV_V_QBUS)
 #define DEV_Q18         (1u << DEV_V_Q18)
-#define DEV_FLTA        (1u << DEV_V_FLTA)
 
 #define UNIBUS          FALSE                           /* 22b only */
 
@@ -283,52 +281,11 @@ typedef struct {
     int32               (*ack[VEC_DEVMAX])(void);       /* ack routine */
     } DIB;
 
-/* I/O page layout - RQB,RQC,RQD float based on number of DZ's */
+/* Qbus I/O page layout - see pdp11_ui_lib.c for address layout details */
 
+#define IOBA_AUTO       (0)                             /* Assigned by Auto Configure */
 #define IOBA_FLOAT      (0)                             /* Assigned by Auto Configure */
 
-#define IOBA_DZ         (IOPAGEBASE + 000100)           /* DZ11 */
-#define IOLN_DZ         010
-#define IOBA_RQB        (IOPAGEBASE + 000334 +  (020 * (DZ_MUXES / 2)))
-#define IOLN_RQB        004
-#define IOBA_RQC        (IOPAGEBASE + IOBA_RQB + IOLN_RQB)
-#define IOLN_RQC        004
-#define IOBA_RQD        (IOPAGEBASE + IOBA_RQC + IOLN_RQC)
-#define IOLN_RQD        004
-#define IOBA_RQ         (IOPAGEBASE + 012150)           /* RQDX3 */
-#define IOLN_RQ         004
-#define IOBA_TS         (IOPAGEBASE + 012520)           /* TS11 */
-#define IOLN_TS         004
-#define IOBA_RL         (IOPAGEBASE + 014400)           /* RL11 */
-#define IOLN_RL         012
-#define IOBA_XQ         (IOPAGEBASE + 014440)           /* DEQNA/DELQA */
-#define IOLN_XQ         020
-#define IOBA_XQB        (IOPAGEBASE + 014460)           /* 2nd DEQNA/DELQA */
-#define IOLN_XQB        020
-#define IOBA_TQ         (IOPAGEBASE + 014500)           /* TMSCP */
-#define IOLN_TQ         004
-#define IOBA_XU         (IOPAGEBASE + 014510)           /* DEUNA/DELUA */
-#define IOLN_XU         010
-#define IOBA_RP         (IOPAGEBASE + 016700)           /* RP/RM */
-#define IOLN_RP         054
-#define IOBA_CR         (IOPAGEBASE + 017160)           /* CD/CR/CM */
-#define IOLN_CR         010
-#define IOBA_RX         (IOPAGEBASE + 017170)           /* RXV11 */
-#define IOLN_RX         004
-#define IOBA_RY         (IOPAGEBASE + 017170)           /* RXV21 */
-#define IOLN_RY         004
-#define IOBA_QDSS       (IOPAGEBASE + 017400)           /* QDSS */
-#define IOLN_QDSS       002
-#define IOBA_DBL        (IOPAGEBASE + 017500)           /* doorbell */
-#define IOLN_DBL        002
-#define IOBA_LPT        (IOPAGEBASE + 017514)           /* LP11 */
-#define IOLN_LPT        004
-#define IOBA_PTR        (IOPAGEBASE + 017550)           /* PC11 reader */
-#define IOLN_PTR        004
-#define IOBA_PTP        (IOPAGEBASE + 017554)           /* PC11 punch */
-#define IOLN_PTP        004
-#define IOBA_DMC        (IOPAGEBASE + 017060)           /* DMC11 */
-#define IOLN_DMC        010
 
 /* The KA65x maintains 4 separate hardware IPL levels, IPL 17 to IPL 14;
    however, DEC Qbus controllers all interrupt on IPL 14
@@ -427,28 +384,11 @@ typedef struct {
 
 /* Device vectors */
 
+#define VEC_AUTO        (0)                             /* Assigned by Auto Configure */
 #define VEC_FLOAT       (0)                             /* Assigned by Auto Configure */
 
 #define VEC_QBUS        1                               /* Qbus system */
 #define VEC_Q           0x200                           /* Qbus vector offset */
-#define VEC_PTR         (VEC_Q + 0070)
-#define VEC_PTP         (VEC_Q + 0074)
-#define VEC_XQ          (VEC_Q + 0120)
-#define VEC_XU          (VEC_Q + 0120)
-#define VEC_RQ          (VEC_Q + 0154)
-#define VEC_RL          (VEC_Q + 0160)
-#define VEC_LPT         (VEC_Q + 0200)
-#define VEC_TS          (VEC_Q + 0224)
-#define VEC_CR          (VEC_Q + 0230)
-#define VEC_TQ          (VEC_Q + 0260)
-#define VEC_RX          (VEC_Q + 0264)
-#define VEC_RY          (VEC_Q + 0264)
-#define VEC_DZRX        (VEC_Q + 0300)
-#define VEC_DZTX        (VEC_Q + 0304)
-#define VEC_VHRX        (VEC_Q + 0310)   
-#define VEC_VHTX        (VEC_Q + 0314)
-#define VEC_DMCRX       (VEC_Q + 0310)
-#define VEC_DMCTX       (VEC_Q + 0314)
 
 /* Interrupt macros */
 
diff --git a/doc/simh_vmio.doc b/doc/simh_vmio.doc
index 4dc78bae..cb6ba9fd 100644
Binary files a/doc/simh_vmio.doc and b/doc/simh_vmio.doc differ
diff --git a/doc/vax780_doc.doc b/doc/vax780_doc.doc
index 8f21180a..e5e0753b 100644
Binary files a/doc/vax780_doc.doc and b/doc/vax780_doc.doc differ