PDQ-3: Compiler suggested warning cleanup (gcc & Visual C++) from Holger Veit
This commit is contained in:
Mark Pizzolato
parent
5b288b0d98
commit
7c1f909752
7 changed files with 119 additions and 94 deletions
129
PDQ-3/pdq3_cpu.c
129
PDQ-3/pdq3_cpu.c
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@ -41,10 +41,11 @@
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20131110 hv A really hard one: INT 3 (RCV CONSOLE) incremented waiter sema, because
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interrupt changed reg_intpending within a WAIT. Need to latch interrupt before
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execution and process afterwards
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20141003 hv compiler suggested warnings (vc++2013, gcc)
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*/
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#include "pdq3_defs.h"
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#include <math.h>
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/* some simulator publics */
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t_stat cpu_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw);
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@ -140,14 +141,14 @@ REG cpu_reg[] = {
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{ NULL }
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};
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MTAB cpu_mod[] = {
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{ UNIT_MSIZE, 0, NULL, "32K", &cpu_set_size, NULL },
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{ UNIT_MSIZE, 1, NULL, "64K", &cpu_set_size, NULL },
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{ UNIT_PASEXC, UNIT_PASEXC, "halt on EXC", "EXC", &cpu_set_flag, NULL },
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{ UNIT_PASEXC, 0, "no EXC", NULL, NULL, NULL },
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{ MTAB_XTD|MTAB_VDV, UNIT_PASEXC, NULL, "NOEXC", &cpu_set_noflag, NULL },
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{ MTAB_XTD|MTAB_VDV, 0, "IOBASE", "IOBASE", NULL, &show_iobase },
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{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", "VECTOR", NULL, &show_iovec },
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{ MTAB_XTD|MTAB_VDV, 0, "PRIO", "PRIO", NULL, &show_ioprio },
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{ UNIT_MSIZE, 0, NULL, "32K", &cpu_set_size, NULL },
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{ UNIT_MSIZE, 1, NULL, "64K", &cpu_set_size, NULL },
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{ UNIT_PASEXC, UNIT_PASEXC, "halt on EXC", "EXC", &cpu_set_flag, NULL },
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{ UNIT_PASEXC, 0, "no EXC", NULL, NULL, NULL },
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{ MTAB_XTD|MTAB_VDV, UNIT_PASEXC, NULL, "NOEXC", &cpu_set_noflag, NULL },
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{ MTAB_XTD|MTAB_VDV, 0, "IOBASE", "IOBASE", NULL, &show_iobase },
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{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", "VECTOR", NULL, &show_iovec },
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{ MTAB_XTD|MTAB_VDV, 0, "PRIO", "PRIO", NULL, &show_ioprio },
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{ 0 }
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};
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@ -323,7 +324,7 @@ t_stat cpu_boot(int32 unitnum, DEVICE *dptr) {
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cpu_setRegs(ctp, ssv, rq);
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} else {
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/* autoload the 1st track into meory at reg_dmabase */
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if ((rc = fdc_dev.boot(0, &fdc_dev)) != SCPE_OK) return rc;
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if ((rc = fdc_boot(0, &fdc_dev)) != SCPE_OK) return rc;
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}
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return SCPE_OK;
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}
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@ -495,8 +496,6 @@ void cpu_assertInt(int level, t_bool tf) {
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}
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t_stat cpu_raiseInt(int level) {
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uint16 vector = int_vectors[level];
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if (level > 15) {
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printf("Implementation error: raiseInt with level>15! Need fix\n");
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exit(1);
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@ -562,10 +561,10 @@ static t_stat cpu_processInt() {
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* instruction interpreter
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************************************************************************************/
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static uint16 UB() {
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static uint8 UB() {
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uint16 val;
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ReadB(reg_segb, reg_ipc++, &val, DBG_CPU_FETCH);
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return val;
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return val & 0xff;
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}
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static uint16 W() {
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uint16 high, data;
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@ -610,10 +609,10 @@ static void Putb(t_addr base, t_addr idx, uint16 val) {
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WriteB(base, idx, val, DBG_CPU_WRITE);
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}
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static uint16 Getb(t_addr addr,t_addr idx) {
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static uint8 Getb(t_addr addr,t_addr idx) {
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uint16 val;
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ReadB(addr, idx, &val, DBG_CPU_READ);
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return val;
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return val & 0xff;
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}
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static uint16 TraverseMSstat(uint16 db) {
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@ -699,9 +698,9 @@ static uint16 GetSIB(uint8 segno) {
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}
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/* do a CXG instruction into segment SEGNO to procedure procno */
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static float DoCXG(uint16 segno, uint16 procno) {
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static void DoCXG(uint8 segno, uint8 procno) {
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uint16 ptbl;
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uint16 osegno = GetSegno(); /* obtain segment of caller to be set into MSCW */
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uint8 osegno = (uint8)GetSegno(); /* obtain segment of caller to be set into MSCW */
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uint16 osegb = reg_segb;
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// printf("CXG: seg=%d proc=%d, osegno=%d\n",segno,procno,osegno);
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@ -710,7 +709,7 @@ static float DoCXG(uint16 segno, uint16 procno) {
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// printf("CXG: ptbl=%x, reg_segb=%x\n",ptbl,reg_segb);
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reg_ipc = createMSCW(ptbl, procno, reg_bp, osegno, osegb); /* call new segment */
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return 63.2;
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sim_interval -= 63; /* actually 63.2 */
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}
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static t_stat Raise(uint16 err) {
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@ -729,7 +728,7 @@ static t_stat Raise(uint16 err) {
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/* call OS trap handler
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* Note: if an exception occurs in boot loader (CHK instruction for CPU serial),
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* this goes to nirvana because HALTUNIT is not yet linked correctly */
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sim_interval -= DoCXG(2,2);
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DoCXG(2,2);
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return SCPE_OK;
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}
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@ -791,7 +790,7 @@ static t_stat taskswitch6() {
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uint16 vector, sem;
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int level;
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t_stat rc = SCPE_OK;
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int kbdc;
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// int kbdc;
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sim_debug(DBG_CPU_CONC2, &cpu_dev, DBG_PCFORMAT0 "Taskswitch6: ctp=$%04x rq=$%04x\n",DBG_PC, reg_ctp, reg_rq);
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while (reg_rq == NIL) { /* no task ready to run? */
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@ -804,15 +803,19 @@ static t_stat taskswitch6() {
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sim_debug(DBG_CPU_CONC3, &cpu_dev, DBG_PCFORMAT0 "Taskswitch6: SIGNAL sem=$%04x\n",DBG_PC, sem);
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rc = DoSIGNAL(sem);
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return rc;
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} else {
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} else {
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#if 0
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kbdc = sim_poll_kbd(); /* check keyboard */
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if (kbdc == SCPE_STOP) return kbdc; /* handle CTRL-E */
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/* process timer */
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if (sim_interval <= 0) {
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if ((rc = sim_process_event()))
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if ((rc = sim_process_event()) != SCPE_OK)
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return rc;
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}
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sim_interval -= 3.6; /* NOP cycle */
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sim_interval -= 4; /* actually 3.6, NOP cycle */
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#else
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sim_idle(TMR_IDLE, TRUE);
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#endif
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}
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}
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@ -861,7 +864,7 @@ static t_stat DoSIGNAL(uint16 sem) {
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sim_debug(DBG_CPU_CONC3, &cpu_dev, DBG_PCFORMAT0 "SIGNAL: reg_rq=$%x, reg_ctp=$%x\n", DBG_PC, reg_rq, reg_ctp);
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if (reg_ctp == NIL) { /* no current task (marker for int processing */
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sim_interval -= 134.8; /* consume time */
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sim_interval -= 135; /* actually 134.8, consume time */
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return taskswitch6(); /* and switch task */
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}
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if (Getb(reg_ctp+OFFB_PRIOR,0) < Getb(qtask+OFFB_PRIOR,0)) { /* is qtask higher prio than current task? */
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@ -870,7 +873,7 @@ static t_stat DoSIGNAL(uint16 sem) {
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} else {
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/* else: nothing is waiting on this semaphore, discard argument, and continue */
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reg_sp++;
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sim_interval -= 52.0;
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sim_interval -= 52; /* correct: 52.0 */
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}
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return rc;
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}
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@ -879,18 +882,18 @@ static t_stat DoSIGNAL(uint16 sem) {
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sim_debug(DBG_CPU_CONC2, &cpu_dev, DBG_PCFORMAT0 "SIGNAL: Sem=$%x(count=%d): increment\n",DBG_PC, sem, count);
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Put(sem+OFF_SEMCOUNT,count+1);
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if (reg_ctp == NIL) { /* if no active task, get one from ready queue */
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sim_interval -= 134.8;
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sim_interval -= 135; /* actually 134.8 */
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return taskswitch6();
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}
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reg_sp++;
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sim_interval -= 18.0;
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sim_interval -= 18; /* correct: 18.0 */
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return rc;
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}
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static float DoWAIT(uint16 sem) {
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static t_stat DoWAIT(uint16 sem) {
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uint16 qhead;
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uint16 wqaddr = sem + OFF_SEMWAITQ;
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t_stat rc = SCPE_OK;
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t_stat rc;
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uint16 count = Get(sem + OFF_SEMCOUNT); /* get count of semaphore */
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sim_debug(DBG_CPU_CONC, &cpu_dev, DBG_PCFORMAT1 "WAIT: Sem=$%04x(count=%d)\n",DBG_PC,sem, count);
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@ -902,33 +905,35 @@ static float DoWAIT(uint16 sem) {
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// sim_debug(DBG_CPU_CONC3, &cpu_dev, DBG_PCFORMAT0 "WAIT: new qhead=%x\n",DBG_PC, qhead);
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rc = taskswitch5(); /* save context in TIB, and switch to new task from ready queue */
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sim_interval -= 90.8;
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sim_interval -= 91; /* actually 90.8 */
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sim_debug(DBG_CPU_CONC2, &cpu_dev, DBG_PCFORMAT0 "WAIT: DONE, switch to newTIB=$%04x\n",DBG_PC, reg_ctp);
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return rc;
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} else {
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sim_debug(DBG_CPU_CONC2, &cpu_dev, DBG_PCFORMAT0 "WAIT: Sem=$%04x(count=%d): decrement\n", DBG_PC, sem, count);
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Put(sem+OFF_SEMCOUNT,count-1);
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}
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sim_interval -= 11.6;
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sim_interval -= 12; /* actually 11.6 */
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sim_debug(DBG_CPU_CONC2, &cpu_dev, DBG_PCFORMAT0 "WAIT: DONE, continue\n",DBG_PC);
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return rc;
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return SCPE_OK;
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}
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static uint16 HiByte(uint16 reg) {
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static uint8 HiByte(uint16 reg) {
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return (reg>>8) & 0xff;
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}
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static uint16 LoByte(uint16 reg) {
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static uint8 LoByte(uint16 reg) {
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return reg & 0xff;
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}
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static t_stat DoInstr(void) {
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t_stat rc = SCPE_OK;
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uint16 opcode, ub1, db, b, ub2, src, dst, inx, len0, len1, hi,lo;
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uint16 t1, t2, t3, t4, t5, min1, max1, ptbl, procno, osegb;
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uint16 opcode, db, b, src, dst, inx, len0, len1, hi,lo;
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uint16 t1, t2, t3, t4, t5, min1, max1, ptbl, osegb;
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int16 ts1, ts2, w;
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uint8 segno, osegno;
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float tf1, tf2, cyc = 0.0;
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uint8 ub1, ub2;
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uint8 segno, osegno, procno;
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float tf1, tf2;
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double cyc = 0.0;
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int i;
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/* set PCX: current instr in progress */
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@ -1069,7 +1074,7 @@ static t_stat DoInstr(void) {
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cyc = 12.0;
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break;
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case 0xc8: /* STB */
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ub1 = Pop(); /* index */ b = Pop(); /* byteaddr */
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ub1 = Pop() & 0xff; /* index */ b = Pop(); /* byteaddr */
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Putb(Pop(), b, ub1);
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cyc = 13.6;
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break;
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@ -1092,7 +1097,7 @@ static t_stat DoInstr(void) {
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cyc = 9.6;
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break;
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case 0xd7: /* IXA */
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t1 = Pop(); Push(Pop() + t1*B());
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b = B(); t1 = Pop(); Push(Pop() + t1*b);
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cyc = 9.6 + b/16384.*46.4;
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break;
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case 0xd8: /* IXP */
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@ -1214,15 +1219,15 @@ static t_stat DoInstr(void) {
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case 0xbe: /* TNC */
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tf1 = PopF();
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PushS((int16)tf1);
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cyc = tf1 ? (abs(tf1)<0.5 ? 15.6 : 37.4) : 12.4; /* approximate */
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cyc = tf1 ? (fabs(tf1)<0.5 ? 15.6 : 37.4) : 12.4; /* approximate */
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break;
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case 0xbf: /* RND */
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tf1 = PopF();
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PushS((int16)(tf1+0.5));
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cyc = tf1 ? (abs(tf1)<0.5 ? 15.6 : 37.4) : 12.4; /* approximate */
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cyc = tf1 ? (fabs(tf1)<0.5 ? 15.6 : 37.4) : 12.4; /* approximate */
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break;
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case 0xe3: /* ABR */
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PushF(abs(PopF()));
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PushF((float)fabs(PopF()));
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cyc = 5.2;
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break;
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case 0xe4: /* NGR */
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@ -1545,7 +1550,7 @@ static t_stat DoInstr(void) {
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break;
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case 0x94: /* CXG */
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ub1 = UB(); ub2 = UB();
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cyc = DoCXG(ub1, ub2);
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DoCXG(ub1, ub2);
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break;
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case 0x95: /* CXI */
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segno = UB(); db = DB(); procno = UB();
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@ -1596,7 +1601,7 @@ static t_stat DoInstr(void) {
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break;
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case 0xdf: /* WAIT */
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t1 = Pop();
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rc = DoWAIT(t1); break;
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DoWAIT(t1); break;
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case 0x9d: /* LPR */
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w = Tos();
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cyc = 0.0;
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@ -1630,12 +1635,12 @@ static t_stat DoInstr(void) {
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} else if (w >= 1) {
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cyc = 54.8;
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switch (w) {
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case OFF_SP: reg_sp = t1; break;
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case OFF_MP: reg_mp = t1; break;
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case OFF_BP: reg_bp = t1; break;
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case OFF_IPC: reg_ipc = t1; break;
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case OFF_SEGB: reg_segb = t1; break;
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default: Put(reg_ctp + w, t1); break;
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case OFF_SP: reg_sp = t1; break;
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case OFF_MP: reg_mp = t1; break;
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case OFF_BP: reg_bp = t1; break;
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case OFF_IPC: reg_ipc = t1; break;
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case OFF_SEGB: reg_segb = t1; break;
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default: Put(reg_ctp + w, t1); break;
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}
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}
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if (w >= -1)
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@ -1676,6 +1681,11 @@ static t_stat DoInstr(void) {
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t_stat sim_instr(void)
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{
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t_stat rc = SCPE_OK;
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/* mandatory idling */
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sim_rtcn_init(TMR_IDLECNT, TMR_IDLE);
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sim_set_idle(&cpu_unit, 10, NULL, NULL);
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while (rc == SCPE_OK) {
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/* set PCX of instruction in progress */
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@ -1683,7 +1693,7 @@ t_stat sim_instr(void)
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/* process timer */
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if (sim_interval <= 0) {
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if ((rc = sim_process_event()))
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if ((rc = sim_process_event()) != SCPE_OK)
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break;
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}
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@ -1697,10 +1707,15 @@ t_stat sim_instr(void)
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* handle time by NOP cycles
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*/
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if (reg_ctp != NIL) {
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if ((rc = DoInstr())) break;
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} else {
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if ((rc = DoInstr()) != SCPE_OK) break;
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}
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else {
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#if 0
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/* waste time by doing a NOP */
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sim_interval -= 3.6;
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sim_interval -= 4; /* actually 3.6 */
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#else
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sim_idle(TMR_IDLE, TRUE);
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#endif
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}
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/* process interrupts
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@ -1710,7 +1725,7 @@ t_stat sim_instr(void)
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if (cpu_isIntEnabled()) {
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reg_intpending |= reg_intlatch;
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if (reg_intpending) {
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if ((rc = cpu_processInt())) {
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if ((rc = cpu_processInt()) != SCPE_OK) {
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printf("processint returns %d\n",rc); fflush(stdout);
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break;
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}
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@ -27,7 +27,8 @@
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20130421 hv initial version
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20130928 hv fix problem with callstack when S_Start_P patches MSCW
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20131012 hv view calltree returned incorrect segment of caller
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*/
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20141003 hv compiler suggested warnings (vc++2013, gcc)
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*/
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#include "pdq3_defs.h"
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static uint8 *opdebug = NULL;
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@ -225,10 +226,11 @@ typedef struct _seginfo {
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SEGINFO* seghash[SEGHASHSIZE];
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#define SEGHASHFUNC(i) (i % SEGHASHSIZE)
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void dbg_segtrackinit() {
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t_stat dbg_segtrackinit() {
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int i;
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for (i=0; i<SEGHASHSIZE; i++)
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seghash[i] = NULL;
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return SCPE_OK;
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}
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static SEGINFO* new_seginfo(SEGINFO* next, uint16 base) {
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@ -274,10 +276,11 @@ typedef struct _aliases {
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#define ALIASHASHSIZE 97
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static ALIASES* aliases[ALIASHASHSIZE];
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static void dbg_initaliases() {
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static t_stat dbg_aliasesinit() {
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int i;
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for (i=0; i<ALIASHASHSIZE; i++)
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aliases[i] = NULL;
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return SCPE_OK;
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}
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static int aliashash(const char* key) {
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@ -293,7 +296,7 @@ static ALIASES* find_alias(const char* key, int* idx) {
|
|||
char gbuf[CBUFSIZE], gbuf2[CBUFSIZE];
|
||||
|
||||
get_glyph(key, gbuf, 0);
|
||||
*idx = aliashash(key);
|
||||
*idx = aliashash(gbuf);
|
||||
a = aliases[*idx];
|
||||
if (a) get_glyph(a->key, gbuf2, 0);
|
||||
while (a && strcmp(gbuf2,gbuf)) {
|
||||
|
|
@ -416,12 +419,12 @@ t_stat dbg_calltree(FILE* fd) {
|
|||
}
|
||||
|
||||
fprintf(fd,"Calltree:\nCurrently in %s at %04x:%04x\n",
|
||||
find_procname(p), reg_segb, reg_ipc);
|
||||
find_procname(p), reg_segb, reg_ipc);
|
||||
lastp = p;
|
||||
p = p->next;
|
||||
while (p) {
|
||||
fprintf(fd," at %04x:%04x called by %s (%04x:%04x)\n",
|
||||
lastp->segb, lastp->instipc, find_procname(p), p->segb, p->instipc);
|
||||
lastp->segb, lastp->instipc, find_procname(p), p->segb, p->instipc);
|
||||
lastp = p;
|
||||
p = p->next;
|
||||
}
|
||||
|
|
@ -435,6 +438,8 @@ t_stat dbg_calltree(FILE* fd) {
|
|||
t_stat dbg_init() {
|
||||
dbg_opdbginit();
|
||||
dbg_segtrackinit();
|
||||
dbg_aliasesinit();
|
||||
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -25,6 +25,7 @@
|
|||
in this Software without prior written authorization from Robert M Supnik and Holger Veit.
|
||||
|
||||
20131103 hv INT_CONR/CONT assignments incorrect in docs, must be swapped
|
||||
20141003 hv recommended warnings from VC++ and gcc added
|
||||
*/
|
||||
#ifndef _PDQ3_DEFS_H_
|
||||
#define _PDQ3_DEFS_H_ 0
|
||||
|
|
@ -191,7 +192,12 @@
|
|||
#define DBG_PC2 reg_segb,reg_ipc
|
||||
|
||||
/* calibration timers */
|
||||
#define TMR_CONPOLL 0
|
||||
#define TMR_CONPOLL 1
|
||||
|
||||
/* IDLE timer. This is supposed to run at 100 Hz; the CPU runs at
|
||||
* 1.25MHz, i.e. the interval is 12500. */
|
||||
#define TMR_IDLE 0
|
||||
#define TMR_IDLECNT 12500
|
||||
|
||||
/* console sio data rates */
|
||||
#define CON_POLLUNIT 0
|
||||
|
|
@ -371,6 +377,7 @@ extern t_stat fprint_sym_m (FILE *of, t_addr addr, t_value *val, UNIT *uptr, int
|
|||
extern t_stat con_read(t_addr ioaddr, uint16 *data);
|
||||
extern t_stat con_write(t_addr ioaddr, uint16 data);
|
||||
extern t_stat con_binit();
|
||||
extern t_stat fdc_boot(int32 unitnum, DEVICE *dptr);
|
||||
extern t_stat fdc_read(t_addr ioaddr, uint16 *data);
|
||||
extern t_stat fdc_write(t_addr ioaddr, uint16 data);
|
||||
extern t_stat fdc_autoload();
|
||||
|
|
|
|||
|
|
@ -23,6 +23,9 @@
|
|||
Except as contained in this notice, the names of Robert M Supnik and Holger Veit
|
||||
shall not be used in advertising or otherwise to promote the sale, use or other dealings
|
||||
in this Software without prior written authorization from Robert M Supnik and Holger Veit.
|
||||
|
||||
2013xxxx hv initial version
|
||||
20141003 hv compiler suggested warnings (vc++2013, gcc)
|
||||
*/
|
||||
#include "pdq3_defs.h"
|
||||
#include "sim_imd.h"
|
||||
|
|
@ -158,7 +161,6 @@ extern UNIT cpu_unit;
|
|||
|
||||
/* forwards */
|
||||
t_stat fdc_svc (UNIT *uptr);
|
||||
t_stat fdc_boot(int32 unitnum, DEVICE *dptr);
|
||||
t_stat fdc_reset (DEVICE *uptr);
|
||||
t_stat fdc_attach(UNIT *uptr, char *cptr);
|
||||
t_stat fdc_detach(UNIT *uptr);
|
||||
|
|
@ -263,7 +265,7 @@ DEVICE fdc_dev = {
|
|||
|
||||
/* boot unit - not available through BOOT FDC cmd, use BOOT CPU instead */
|
||||
t_stat fdc_boot(int32 unitnum, DEVICE *dptr) {
|
||||
if (unitnum < 0 || ((uint32)unitnum > dptr->numunits))
|
||||
if (unitnum < 0 || (uint32)unitnum > dptr->numunits)
|
||||
return SCPE_NXUN;
|
||||
// printf("BOOT FDC%d\n",unitnum);
|
||||
return fdc_autoload(unitnum);
|
||||
|
|
@ -427,10 +429,9 @@ static t_bool dma_abort(t_bool fromfinish) {
|
|||
sim_debug(DBG_FD_DMA, & fdc_dev, DBG_PCFORMAT2 "AUTOLOAD finished by end-of-track (DMA aborted)\n", DBG_PC);
|
||||
cpu_finishAutoload();
|
||||
dma_isautoload = FALSE;
|
||||
} else
|
||||
if (!fromfinish) {
|
||||
sim_debug(DBG_FD_DMA, & fdc_dev, DBG_PCFORMAT2 "Aborted transfer\n", DBG_PC);
|
||||
}
|
||||
} else if (!fromfinish) {
|
||||
sim_debug(DBG_FD_DMA, & fdc_dev, DBG_PCFORMAT2 "Aborted transfer\n", DBG_PC);
|
||||
}
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
|
|
@ -522,7 +523,7 @@ static t_bool dma_transfer_from_ram(uint8 *buf, int bufsize) {
|
|||
dma_interrupt(DMA_CTRL_TOIE);
|
||||
return FALSE; /* write fault */
|
||||
}
|
||||
buf[i] = data;
|
||||
buf[i] = data & 0xff;
|
||||
_reg_dma_cnt++;
|
||||
if (_reg_dma_cnt == 0) /* all data done? */
|
||||
break;
|
||||
|
|
@ -930,7 +931,7 @@ static t_stat fdc_docmd(uint16 data) {
|
|||
}
|
||||
|
||||
void dma_docmd(uint16 data) {
|
||||
reg_dma_ctrl = data;
|
||||
reg_dma_ctrl = data & 0xff;
|
||||
reg_dma_status &= 0x8f;
|
||||
reg_dma_status |= (reg_dma_ctrl & 0x70);
|
||||
|
||||
|
|
@ -941,11 +942,9 @@ void dma_docmd(uint16 data) {
|
|||
/* setup FDC/DMA to read first track into low memory */
|
||||
t_stat fdc_autoload(int unitnum) {
|
||||
int unitbit = 1 << unitnum;
|
||||
|
||||
sim_debug(DBG_FD_CMD, &fdc_dev, DBG_PCFORMAT2 "Autoload Unit=%d\n", DBG_PC, unitnum);
|
||||
dma_isautoload = TRUE;
|
||||
|
||||
|
||||
/* note: this is partly in microcode/ROM. The DMA cntrlr itself does not set the
|
||||
* FDC register for multi_read */
|
||||
fdc_reset(&fdc_dev);
|
||||
|
|
@ -996,22 +995,22 @@ t_stat fdc_write(t_addr ioaddr, uint16 data) {
|
|||
reg_dma_status = data & 0x8f;
|
||||
break;
|
||||
case 0x0a: /* count low */
|
||||
reg_dma_cntl = data;
|
||||
reg_dma_cntl = data & 0xff;
|
||||
break;
|
||||
case 0x0b: /* count high */
|
||||
reg_dma_cnth = data;
|
||||
reg_dma_cnth = data & 0xff;
|
||||
break;
|
||||
case 0x0c: /* addr low */
|
||||
reg_dma_addrl = data;
|
||||
reg_dma_addrl = data & 0xff;
|
||||
break;
|
||||
case 0x0d: /* addr high */
|
||||
reg_dma_addrh = data;
|
||||
reg_dma_addrh = data & 0xff;
|
||||
break;
|
||||
case 0x0e: /* addr ext */
|
||||
reg_dma_addre = data & 0x03;
|
||||
break;
|
||||
case 0x0f: /* ID register */
|
||||
reg_dma_id = data;
|
||||
reg_dma_id = data & 0xff;
|
||||
break;
|
||||
}
|
||||
_reg_dma_cnt = (reg_dma_cnth << 8) | reg_dma_cntl;
|
||||
|
|
@ -1148,7 +1147,7 @@ t_stat pdq3_diskCreate(FILE *fileref, char *ctlr_comment) {
|
|||
}
|
||||
|
||||
t_stat pdq3_diskFormat(DISK_INFO *myDisk) {
|
||||
uint8 i;
|
||||
uint8 i = 0;
|
||||
uint8 sector_map[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26};
|
||||
uint32 flags;
|
||||
|
||||
|
|
@ -1156,7 +1155,7 @@ t_stat pdq3_diskFormat(DISK_INFO *myDisk) {
|
|||
|
||||
/* format first track as 26 sectors with 128 bytes */
|
||||
if((trackWrite(myDisk, 0, 0, 26, 128, sector_map, IMD_MODE_500K_FM, 0xE5, &flags)) != 0) {
|
||||
printf("PDQ3_IMD: Error formatting track 0\n");
|
||||
printf("PDQ3_IMD: Error formatting track %d\n", i);
|
||||
return SCPE_IOERR;
|
||||
}
|
||||
putchar('.');
|
||||
|
|
|
|||
|
|
@ -113,7 +113,6 @@ t_stat set_iobase(UNIT *uptr, int32 val, char *cptr, void *desc) {
|
|||
DEVICE* dptr;
|
||||
DEVCTXT* ctxt;
|
||||
IOINFO* ioi;
|
||||
t_bool first = TRUE;
|
||||
if (!cptr) return SCPE_ARG;
|
||||
if (!uptr) return SCPE_IERR;
|
||||
if ((dptr = find_dev_from_unit(uptr)) == 0) return SCPE_IERR;
|
||||
|
|
@ -130,7 +129,6 @@ t_stat set_iovec(UNIT *uptr, int32 val, char *cptr, void *desc) {
|
|||
DEVICE* dptr;
|
||||
DEVCTXT* ctxt;
|
||||
IOINFO* ioi;
|
||||
t_bool first = TRUE;
|
||||
if (!cptr) return SCPE_ARG;
|
||||
if (!uptr) return SCPE_IERR;
|
||||
if ((dptr = find_dev_from_unit(uptr)) == 0) return SCPE_IERR;
|
||||
|
|
@ -166,7 +164,6 @@ t_stat set_ioprio(UNIT *uptr, int32 val, char *cptr, void *desc) {
|
|||
DEVICE* dptr;
|
||||
DEVCTXT* ctxt;
|
||||
IOINFO* ioi;
|
||||
t_bool first = TRUE;
|
||||
if (!cptr) return SCPE_ARG;
|
||||
if (!uptr) return SCPE_IERR;
|
||||
if ((dptr = find_dev_from_unit(uptr)) == 0) return SCPE_IERR;
|
||||
|
|
|
|||
|
|
@ -25,9 +25,11 @@
|
|||
other dealings in this Software without prior written authorization from
|
||||
Robert M Supnik and Holger Veit.
|
||||
|
||||
2013xxxx hv initial version
|
||||
20130902 hv added telnet multiplexer code
|
||||
20131020 hv fixed CON interrupt handling
|
||||
20131103 hv connect CON_ATTACH logic with DSR, so that DSR is set if tcp connect
|
||||
20141003 hv compiler suggested warnings (vc++2013, gcc)
|
||||
*/
|
||||
#include "pdq3_defs.h"
|
||||
#include <ctype.h>
|
||||
|
|
@ -348,6 +350,8 @@ static int set_parity(int c, int odd)
|
|||
if (!odd) c ^= 0x80;
|
||||
return c;
|
||||
}
|
||||
#if 0
|
||||
// currently unused
|
||||
static int get_parity(int c, int even)
|
||||
{
|
||||
int i, p = 0;
|
||||
|
|
@ -356,6 +360,7 @@ static int get_parity(int c, int even)
|
|||
if (even) p ^= 1;
|
||||
return p;
|
||||
}
|
||||
#endif
|
||||
|
||||
// functions from memory handler to read and write a char
|
||||
// note: the usart is connected to inverted data lines,
|
||||
|
|
@ -372,7 +377,7 @@ t_stat con_write(t_addr ioaddr, uint16 data) {
|
|||
data = (~data) & 0xff;
|
||||
switch (ioaddr & 0x0003) {
|
||||
case 0: /* CTRL1 */
|
||||
con_ctrl1 = data;
|
||||
con_ctrl1 = data & 0xff;
|
||||
if (!RCVENABLED()) { /* disable receiver */
|
||||
clrbit(con_status,CONS_FE|CONS_PE|CONS_OE|CONS_DR);
|
||||
sim_cancel(poll);
|
||||
|
|
@ -391,7 +396,7 @@ t_stat con_write(t_addr ioaddr, uint16 data) {
|
|||
}
|
||||
break;
|
||||
case 1:
|
||||
con_ctrl2 = data;
|
||||
con_ctrl2 = data & 0xff;
|
||||
break;
|
||||
case 2:
|
||||
// ignore this here - DLE register
|
||||
|
|
@ -406,7 +411,7 @@ t_stat con_write(t_addr ioaddr, uint16 data) {
|
|||
break;
|
||||
case CONC2_CLEN8: data &= 0xff; break;
|
||||
}
|
||||
con_xmit = data;
|
||||
con_xmit = data & 0xff;
|
||||
term->buf = data;
|
||||
clrbit(con_status,CONS_THRE);
|
||||
if (XMITENABLED())
|
||||
|
|
|
|||
|
|
@ -28,18 +28,17 @@
|
|||
20130907 hv added VIEWSEG command
|
||||
20130925 hv added CALL and NAME command
|
||||
20130927 hv wrong disassembly of LDC instr
|
||||
20141003 hv compiler suggested warnings (vc++2013, gcc)
|
||||
*/
|
||||
#include "pdq3_defs.h"
|
||||
#include <ctype.h>
|
||||
|
||||
static int disass(t_addr addr);
|
||||
t_stat parse_sym_m (char *cptr, t_value *val, int32 sw);
|
||||
void pdq3_vm_init (void);
|
||||
static t_stat pdq3_cmd_exstack(int32 arg, char *buf);
|
||||
static t_stat pdq3_cmd_exmscw(int32 arg, char *buf);
|
||||
static t_stat pdq3_cmd_extib(int32 arg, char *buf);
|
||||
static t_stat pdq3_cmd_exseg(int32 arg, char *buf);
|
||||
static t_stat pdq3_cmd_calcea(int32 arg, char *buf);
|
||||
static t_stat pdq3_cmd_calltree(int32 arg, char *buf);
|
||||
static t_stat pdq3_cmd_namealias(int32 arg, char *buf);
|
||||
|
||||
|
|
@ -52,7 +51,6 @@ extern REG cpu_reg[];
|
|||
extern uint16 M[];
|
||||
extern uint16 reg_pc;
|
||||
|
||||
|
||||
/* SCP data structures and interface routines
|
||||
sim_name simulator name string
|
||||
sim_PC pointer to saved PC register descriptor
|
||||
|
|
@ -541,7 +539,6 @@ t_stat fprint_sym (FILE *of, t_addr addr, t_value *val,
|
|||
T_FLCVT t;
|
||||
int ch;
|
||||
|
||||
t_bool hexdec = (sw & SWMASK('H')) ? TRUE : FALSE;
|
||||
if (sw & SWMASK('M') && !ADDR_ISWORD(addr)) {
|
||||
return fprint_sym_m(of, addr, val, uptr, sw);
|
||||
}
|
||||
|
|
@ -570,11 +567,11 @@ t_stat fprint_sym (FILE *of, t_addr addr, t_value *val,
|
|||
if (ADDR_ISWORD(addr)) {
|
||||
fprint_val(of, val[0], cpu_dev.dradix, 16, PV_RZRO);
|
||||
off = ADDR_OFF(addr);
|
||||
if (off > (reg_bp+MSCW_SZ-1))
|
||||
if (off > (t_addr)(reg_bp+MSCW_SZ-1))
|
||||
fprintf(of," (GLOBAL+%d)", off - reg_bp - MSCW_SZ + 1);
|
||||
else if (off >= reg_mp && off <= (reg_mp+OFFB_MSSEG))
|
||||
else if (off >= reg_mp && off <= (t_addr)(reg_mp+OFFB_MSSEG))
|
||||
fprintf(of," (MP+%d)", off - reg_mp);
|
||||
else if (off > (reg_mp+MSCW_SZ-1))
|
||||
else if (off > (t_addr)(reg_mp+MSCW_SZ-1))
|
||||
fprintf(of," (LOCAL+%d)", off - reg_mp - MSCW_SZ + 1);
|
||||
else if (off >= reg_sp && off < reg_spupr)
|
||||
fprintf(of," (SP+%d)", off - reg_sp);
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue