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PDQ-3: Compiler suggested warning cleanup (gcc & Visual C++) from Holger Veit

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This commit is contained in:
Mark Pizzolato 2014-10-04 12:37:45 -07:00
parent 5b288b0d98
commit 7c1f909752
7 changed files with 119 additions and 94 deletions
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127
PDQ-3/pdq3_cpu.c
View file

@ -41,10 +41,11 @@
20131110 hv A really hard one: INT 3 (RCV CONSOLE) incremented waiter sema, because 20131110 hv A really hard one: INT 3 (RCV CONSOLE) incremented waiter sema, because
interrupt changed reg_intpending within a WAIT. Need to latch interrupt before interrupt changed reg_intpending within a WAIT. Need to latch interrupt before
execution and process afterwards execution and process afterwards
20141003 hv compiler suggested warnings (vc++2013, gcc)
*/ */
#include "pdq3_defs.h" #include "pdq3_defs.h"
#include <math.h>
/* some simulator publics */ /* some simulator publics */
t_stat cpu_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw); t_stat cpu_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw);
@ -140,14 +141,14 @@ REG cpu_reg[] = {
{ NULL } { NULL }
}; };
MTAB cpu_mod[] = { MTAB cpu_mod[] = {
{ UNIT_MSIZE, 0, NULL, "32K", &cpu_set_size, NULL }, { UNIT_MSIZE, 0, NULL, "32K", &cpu_set_size, NULL },
{ UNIT_MSIZE, 1, NULL, "64K", &cpu_set_size, NULL }, { UNIT_MSIZE, 1, NULL, "64K", &cpu_set_size, NULL },
{ UNIT_PASEXC, UNIT_PASEXC, "halt on EXC", "EXC", &cpu_set_flag, NULL }, { UNIT_PASEXC, UNIT_PASEXC, "halt on EXC", "EXC", &cpu_set_flag, NULL },
{ UNIT_PASEXC, 0, "no EXC", NULL, NULL, NULL }, { UNIT_PASEXC, 0, "no EXC", NULL, NULL, NULL },
{ MTAB_XTD|MTAB_VDV, UNIT_PASEXC, NULL, "NOEXC", &cpu_set_noflag, NULL }, { MTAB_XTD|MTAB_VDV, UNIT_PASEXC, NULL, "NOEXC", &cpu_set_noflag, NULL },
{ MTAB_XTD|MTAB_VDV, 0, "IOBASE", "IOBASE", NULL, &show_iobase }, { MTAB_XTD|MTAB_VDV, 0, "IOBASE", "IOBASE", NULL, &show_iobase },
{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", "VECTOR", NULL, &show_iovec }, { MTAB_XTD|MTAB_VDV, 0, "VECTOR", "VECTOR", NULL, &show_iovec },
{ MTAB_XTD|MTAB_VDV, 0, "PRIO", "PRIO", NULL, &show_ioprio }, { MTAB_XTD|MTAB_VDV, 0, "PRIO", "PRIO", NULL, &show_ioprio },
{ 0 } { 0 }
}; };
@ -323,7 +324,7 @@ t_stat cpu_boot(int32 unitnum, DEVICE *dptr) {
cpu_setRegs(ctp, ssv, rq); cpu_setRegs(ctp, ssv, rq);
} else { } else {
/* autoload the 1st track into meory at reg_dmabase */ /* autoload the 1st track into meory at reg_dmabase */
if ((rc = fdc_dev.boot(0, &fdc_dev)) != SCPE_OK) return rc; if ((rc = fdc_boot(0, &fdc_dev)) != SCPE_OK) return rc;
} }
return SCPE_OK; return SCPE_OK;
} }
@ -495,8 +496,6 @@ void cpu_assertInt(int level, t_bool tf) {
} }
t_stat cpu_raiseInt(int level) { t_stat cpu_raiseInt(int level) {
uint16 vector = int_vectors[level];
if (level > 15) { if (level > 15) {
printf("Implementation error: raiseInt with level>15! Need fix\n"); printf("Implementation error: raiseInt with level>15! Need fix\n");
exit(1); exit(1);
@ -562,10 +561,10 @@ static t_stat cpu_processInt() {
* instruction interpreter * instruction interpreter
************************************************************************************/ ************************************************************************************/
static uint16 UB() { static uint8 UB() {
uint16 val; uint16 val;
ReadB(reg_segb, reg_ipc++, &val, DBG_CPU_FETCH); ReadB(reg_segb, reg_ipc++, &val, DBG_CPU_FETCH);
return val; return val & 0xff;
} }
static uint16 W() { static uint16 W() {
uint16 high, data; uint16 high, data;
@ -610,10 +609,10 @@ static void Putb(t_addr base, t_addr idx, uint16 val) {
WriteB(base, idx, val, DBG_CPU_WRITE); WriteB(base, idx, val, DBG_CPU_WRITE);
} }
static uint16 Getb(t_addr addr,t_addr idx) { static uint8 Getb(t_addr addr,t_addr idx) {
uint16 val; uint16 val;
ReadB(addr, idx, &val, DBG_CPU_READ); ReadB(addr, idx, &val, DBG_CPU_READ);
return val; return val & 0xff;
} }
static uint16 TraverseMSstat(uint16 db) { static uint16 TraverseMSstat(uint16 db) {
@ -699,9 +698,9 @@ static uint16 GetSIB(uint8 segno) {
} }
/* do a CXG instruction into segment SEGNO to procedure procno */ /* do a CXG instruction into segment SEGNO to procedure procno */
static float DoCXG(uint16 segno, uint16 procno) { static void DoCXG(uint8 segno, uint8 procno) {
uint16 ptbl; uint16 ptbl;
uint16 osegno = GetSegno(); /* obtain segment of caller to be set into MSCW */ uint8 osegno = (uint8)GetSegno(); /* obtain segment of caller to be set into MSCW */
uint16 osegb = reg_segb; uint16 osegb = reg_segb;
// printf("CXG: seg=%d proc=%d, osegno=%d\n",segno,procno,osegno); // printf("CXG: seg=%d proc=%d, osegno=%d\n",segno,procno,osegno);
@ -710,7 +709,7 @@ static float DoCXG(uint16 segno, uint16 procno) {
// printf("CXG: ptbl=%x, reg_segb=%x\n",ptbl,reg_segb); // printf("CXG: ptbl=%x, reg_segb=%x\n",ptbl,reg_segb);
reg_ipc = createMSCW(ptbl, procno, reg_bp, osegno, osegb); /* call new segment */ reg_ipc = createMSCW(ptbl, procno, reg_bp, osegno, osegb); /* call new segment */
return 63.2; sim_interval -= 63; /* actually 63.2 */
} }
static t_stat Raise(uint16 err) { static t_stat Raise(uint16 err) {
@ -729,7 +728,7 @@ static t_stat Raise(uint16 err) {
/* call OS trap handler /* call OS trap handler
* Note: if an exception occurs in boot loader (CHK instruction for CPU serial), * Note: if an exception occurs in boot loader (CHK instruction for CPU serial),
* this goes to nirvana because HALTUNIT is not yet linked correctly */ * this goes to nirvana because HALTUNIT is not yet linked correctly */
sim_interval -= DoCXG(2,2); DoCXG(2,2);
return SCPE_OK; return SCPE_OK;
} }
@ -791,7 +790,7 @@ static t_stat taskswitch6() {
uint16 vector, sem; uint16 vector, sem;
int level; int level;
t_stat rc = SCPE_OK; t_stat rc = SCPE_OK;
int kbdc; // int kbdc;
sim_debug(DBG_CPU_CONC2, &cpu_dev, DBG_PCFORMAT0 "Taskswitch6: ctp=$%04x rq=$%04x\n",DBG_PC, reg_ctp, reg_rq); sim_debug(DBG_CPU_CONC2, &cpu_dev, DBG_PCFORMAT0 "Taskswitch6: ctp=$%04x rq=$%04x\n",DBG_PC, reg_ctp, reg_rq);
while (reg_rq == NIL) { /* no task ready to run? */ while (reg_rq == NIL) { /* no task ready to run? */
@ -805,14 +804,18 @@ static t_stat taskswitch6() {
rc = DoSIGNAL(sem); rc = DoSIGNAL(sem);
return rc; return rc;
} else { } else {
#if 0
kbdc = sim_poll_kbd(); /* check keyboard */ kbdc = sim_poll_kbd(); /* check keyboard */
if (kbdc == SCPE_STOP) return kbdc; /* handle CTRL-E */ if (kbdc == SCPE_STOP) return kbdc; /* handle CTRL-E */
/* process timer */ /* process timer */
if (sim_interval <= 0) { if (sim_interval <= 0) {
if ((rc = sim_process_event())) if ((rc = sim_process_event()) != SCPE_OK)
return rc; return rc;
} }
sim_interval -= 3.6; /* NOP cycle */ sim_interval -= 4; /* actually 3.6, NOP cycle */
#else
sim_idle(TMR_IDLE, TRUE);
#endif
} }
} }
@ -861,7 +864,7 @@ static t_stat DoSIGNAL(uint16 sem) {
sim_debug(DBG_CPU_CONC3, &cpu_dev, DBG_PCFORMAT0 "SIGNAL: reg_rq=$%x, reg_ctp=$%x\n", DBG_PC, reg_rq, reg_ctp); sim_debug(DBG_CPU_CONC3, &cpu_dev, DBG_PCFORMAT0 "SIGNAL: reg_rq=$%x, reg_ctp=$%x\n", DBG_PC, reg_rq, reg_ctp);
if (reg_ctp == NIL) { /* no current task (marker for int processing */ if (reg_ctp == NIL) { /* no current task (marker for int processing */
sim_interval -= 134.8; /* consume time */ sim_interval -= 135; /* actually 134.8, consume time */
return taskswitch6(); /* and switch task */ return taskswitch6(); /* and switch task */
} }
if (Getb(reg_ctp+OFFB_PRIOR,0) < Getb(qtask+OFFB_PRIOR,0)) { /* is qtask higher prio than current task? */ if (Getb(reg_ctp+OFFB_PRIOR,0) < Getb(qtask+OFFB_PRIOR,0)) { /* is qtask higher prio than current task? */
@ -870,7 +873,7 @@ static t_stat DoSIGNAL(uint16 sem) {
} else { } else {
/* else: nothing is waiting on this semaphore, discard argument, and continue */ /* else: nothing is waiting on this semaphore, discard argument, and continue */
reg_sp++; reg_sp++;
sim_interval -= 52.0; sim_interval -= 52; /* correct: 52.0 */
} }
return rc; return rc;
} }
@ -879,18 +882,18 @@ static t_stat DoSIGNAL(uint16 sem) {
sim_debug(DBG_CPU_CONC2, &cpu_dev, DBG_PCFORMAT0 "SIGNAL: Sem=$%x(count=%d): increment\n",DBG_PC, sem, count); sim_debug(DBG_CPU_CONC2, &cpu_dev, DBG_PCFORMAT0 "SIGNAL: Sem=$%x(count=%d): increment\n",DBG_PC, sem, count);
Put(sem+OFF_SEMCOUNT,count+1); Put(sem+OFF_SEMCOUNT,count+1);
if (reg_ctp == NIL) { /* if no active task, get one from ready queue */ if (reg_ctp == NIL) { /* if no active task, get one from ready queue */
sim_interval -= 134.8; sim_interval -= 135; /* actually 134.8 */
return taskswitch6(); return taskswitch6();
} }
reg_sp++; reg_sp++;
sim_interval -= 18.0; sim_interval -= 18; /* correct: 18.0 */
return rc; return rc;
} }
static float DoWAIT(uint16 sem) { static t_stat DoWAIT(uint16 sem) {
uint16 qhead; uint16 qhead;
uint16 wqaddr = sem + OFF_SEMWAITQ; uint16 wqaddr = sem + OFF_SEMWAITQ;
t_stat rc = SCPE_OK; t_stat rc;
uint16 count = Get(sem + OFF_SEMCOUNT); /* get count of semaphore */ uint16 count = Get(sem + OFF_SEMCOUNT); /* get count of semaphore */
sim_debug(DBG_CPU_CONC, &cpu_dev, DBG_PCFORMAT1 "WAIT: Sem=$%04x(count=%d)\n",DBG_PC,sem, count); sim_debug(DBG_CPU_CONC, &cpu_dev, DBG_PCFORMAT1 "WAIT: Sem=$%04x(count=%d)\n",DBG_PC,sem, count);
@ -902,33 +905,35 @@ static float DoWAIT(uint16 sem) {
// sim_debug(DBG_CPU_CONC3, &cpu_dev, DBG_PCFORMAT0 "WAIT: new qhead=%x\n",DBG_PC, qhead); // sim_debug(DBG_CPU_CONC3, &cpu_dev, DBG_PCFORMAT0 "WAIT: new qhead=%x\n",DBG_PC, qhead);
rc = taskswitch5(); /* save context in TIB, and switch to new task from ready queue */ rc = taskswitch5(); /* save context in TIB, and switch to new task from ready queue */
sim_interval -= 90.8; sim_interval -= 91; /* actually 90.8 */
sim_debug(DBG_CPU_CONC2, &cpu_dev, DBG_PCFORMAT0 "WAIT: DONE, switch to newTIB=$%04x\n",DBG_PC, reg_ctp); sim_debug(DBG_CPU_CONC2, &cpu_dev, DBG_PCFORMAT0 "WAIT: DONE, switch to newTIB=$%04x\n",DBG_PC, reg_ctp);
return rc; return rc;
} else { } else {
sim_debug(DBG_CPU_CONC2, &cpu_dev, DBG_PCFORMAT0 "WAIT: Sem=$%04x(count=%d): decrement\n", DBG_PC, sem, count); sim_debug(DBG_CPU_CONC2, &cpu_dev, DBG_PCFORMAT0 "WAIT: Sem=$%04x(count=%d): decrement\n", DBG_PC, sem, count);
Put(sem+OFF_SEMCOUNT,count-1); Put(sem+OFF_SEMCOUNT,count-1);
} }
sim_interval -= 11.6; sim_interval -= 12; /* actually 11.6 */
sim_debug(DBG_CPU_CONC2, &cpu_dev, DBG_PCFORMAT0 "WAIT: DONE, continue\n",DBG_PC); sim_debug(DBG_CPU_CONC2, &cpu_dev, DBG_PCFORMAT0 "WAIT: DONE, continue\n",DBG_PC);
return rc; return SCPE_OK;
} }
static uint16 HiByte(uint16 reg) { static uint8 HiByte(uint16 reg) {
return (reg>>8) & 0xff; return (reg>>8) & 0xff;
} }
static uint16 LoByte(uint16 reg) { static uint8 LoByte(uint16 reg) {
return reg & 0xff; return reg & 0xff;
} }
static t_stat DoInstr(void) { static t_stat DoInstr(void) {
t_stat rc = SCPE_OK; t_stat rc = SCPE_OK;
uint16 opcode, ub1, db, b, ub2, src, dst, inx, len0, len1, hi,lo; uint16 opcode, db, b, src, dst, inx, len0, len1, hi,lo;
uint16 t1, t2, t3, t4, t5, min1, max1, ptbl, procno, osegb; uint16 t1, t2, t3, t4, t5, min1, max1, ptbl, osegb;
int16 ts1, ts2, w; int16 ts1, ts2, w;
uint8 segno, osegno; uint8 ub1, ub2;
float tf1, tf2, cyc = 0.0; uint8 segno, osegno, procno;
float tf1, tf2;
double cyc = 0.0;
int i; int i;
/* set PCX: current instr in progress */ /* set PCX: current instr in progress */
@ -1069,7 +1074,7 @@ static t_stat DoInstr(void) {
cyc = 12.0; cyc = 12.0;
break; break;
case 0xc8: /* STB */ case 0xc8: /* STB */
ub1 = Pop(); /* index */ b = Pop(); /* byteaddr */ ub1 = Pop() & 0xff; /* index */ b = Pop(); /* byteaddr */
Putb(Pop(), b, ub1); Putb(Pop(), b, ub1);
cyc = 13.6; cyc = 13.6;
break; break;
@ -1092,7 +1097,7 @@ static t_stat DoInstr(void) {
cyc = 9.6; cyc = 9.6;
break; break;
case 0xd7: /* IXA */ case 0xd7: /* IXA */
t1 = Pop(); Push(Pop() + t1*B()); b = B(); t1 = Pop(); Push(Pop() + t1*b);
cyc = 9.6 + b/16384.*46.4; cyc = 9.6 + b/16384.*46.4;
break; break;
case 0xd8: /* IXP */ case 0xd8: /* IXP */
@ -1214,15 +1219,15 @@ static t_stat DoInstr(void) {
case 0xbe: /* TNC */ case 0xbe: /* TNC */
tf1 = PopF(); tf1 = PopF();
PushS((int16)tf1); PushS((int16)tf1);
cyc = tf1 ? (abs(tf1)<0.5 ? 15.6 : 37.4) : 12.4; /* approximate */ cyc = tf1 ? (fabs(tf1)<0.5 ? 15.6 : 37.4) : 12.4; /* approximate */
break; break;
case 0xbf: /* RND */ case 0xbf: /* RND */
tf1 = PopF(); tf1 = PopF();
PushS((int16)(tf1+0.5)); PushS((int16)(tf1+0.5));
cyc = tf1 ? (abs(tf1)<0.5 ? 15.6 : 37.4) : 12.4; /* approximate */ cyc = tf1 ? (fabs(tf1)<0.5 ? 15.6 : 37.4) : 12.4; /* approximate */
break; break;
case 0xe3: /* ABR */ case 0xe3: /* ABR */
PushF(abs(PopF())); PushF((float)fabs(PopF()));
cyc = 5.2; cyc = 5.2;
break; break;
case 0xe4: /* NGR */ case 0xe4: /* NGR */
@ -1545,7 +1550,7 @@ static t_stat DoInstr(void) {
break; break;
case 0x94: /* CXG */ case 0x94: /* CXG */
ub1 = UB(); ub2 = UB(); ub1 = UB(); ub2 = UB();
cyc = DoCXG(ub1, ub2); DoCXG(ub1, ub2);
break; break;
case 0x95: /* CXI */ case 0x95: /* CXI */
segno = UB(); db = DB(); procno = UB(); segno = UB(); db = DB(); procno = UB();
@ -1596,7 +1601,7 @@ static t_stat DoInstr(void) {
break; break;
case 0xdf: /* WAIT */ case 0xdf: /* WAIT */
t1 = Pop(); t1 = Pop();
rc = DoWAIT(t1); break; DoWAIT(t1); break;
case 0x9d: /* LPR */ case 0x9d: /* LPR */
w = Tos(); w = Tos();
cyc = 0.0; cyc = 0.0;
@ -1630,12 +1635,12 @@ static t_stat DoInstr(void) {
} else if (w >= 1) { } else if (w >= 1) {
cyc = 54.8; cyc = 54.8;
switch (w) { switch (w) {
case OFF_SP: reg_sp = t1; break; case OFF_SP: reg_sp = t1; break;
case OFF_MP: reg_mp = t1; break; case OFF_MP: reg_mp = t1; break;
case OFF_BP: reg_bp = t1; break; case OFF_BP: reg_bp = t1; break;
case OFF_IPC: reg_ipc = t1; break; case OFF_IPC: reg_ipc = t1; break;
case OFF_SEGB: reg_segb = t1; break; case OFF_SEGB: reg_segb = t1; break;
default: Put(reg_ctp + w, t1); break; default: Put(reg_ctp + w, t1); break;
} }
} }
if (w >= -1) if (w >= -1)
@ -1676,6 +1681,11 @@ static t_stat DoInstr(void) {
t_stat sim_instr(void) t_stat sim_instr(void)
{ {
t_stat rc = SCPE_OK; t_stat rc = SCPE_OK;
/* mandatory idling */
sim_rtcn_init(TMR_IDLECNT, TMR_IDLE);
sim_set_idle(&cpu_unit, 10, NULL, NULL);
while (rc == SCPE_OK) { while (rc == SCPE_OK) {
/* set PCX of instruction in progress */ /* set PCX of instruction in progress */
@ -1683,7 +1693,7 @@ t_stat sim_instr(void)
/* process timer */ /* process timer */
if (sim_interval <= 0) { if (sim_interval <= 0) {
if ((rc = sim_process_event())) if ((rc = sim_process_event()) != SCPE_OK)
break; break;
} }
@ -1697,10 +1707,15 @@ t_stat sim_instr(void)
* handle time by NOP cycles * handle time by NOP cycles
*/ */
if (reg_ctp != NIL) { if (reg_ctp != NIL) {
if ((rc = DoInstr())) break; if ((rc = DoInstr()) != SCPE_OK) break;
} else { }
else {
#if 0
/* waste time by doing a NOP */ /* waste time by doing a NOP */
sim_interval -= 3.6; sim_interval -= 4; /* actually 3.6 */
#else
sim_idle(TMR_IDLE, TRUE);
#endif
} }
/* process interrupts /* process interrupts
@ -1710,7 +1725,7 @@ t_stat sim_instr(void)
if (cpu_isIntEnabled()) { if (cpu_isIntEnabled()) {
reg_intpending |= reg_intlatch; reg_intpending |= reg_intlatch;
if (reg_intpending) { if (reg_intpending) {
if ((rc = cpu_processInt())) { if ((rc = cpu_processInt()) != SCPE_OK) {
printf("processint returns %d\n",rc); fflush(stdout); printf("processint returns %d\n",rc); fflush(stdout);
break; break;
} }

17
PDQ-3/pdq3_debug.c
View file

@ -27,7 +27,8 @@
20130421 hv initial version 20130421 hv initial version
20130928 hv fix problem with callstack when S_Start_P patches MSCW 20130928 hv fix problem with callstack when S_Start_P patches MSCW
20131012 hv view calltree returned incorrect segment of caller 20131012 hv view calltree returned incorrect segment of caller
*/ 20141003 hv compiler suggested warnings (vc++2013, gcc)
*/
#include "pdq3_defs.h" #include "pdq3_defs.h"
static uint8 *opdebug = NULL; static uint8 *opdebug = NULL;
@ -225,10 +226,11 @@ typedef struct _seginfo {
SEGINFO* seghash[SEGHASHSIZE]; SEGINFO* seghash[SEGHASHSIZE];
#define SEGHASHFUNC(i) (i % SEGHASHSIZE) #define SEGHASHFUNC(i) (i % SEGHASHSIZE)
void dbg_segtrackinit() { t_stat dbg_segtrackinit() {
int i; int i;
for (i=0; i<SEGHASHSIZE; i++) for (i=0; i<SEGHASHSIZE; i++)
seghash[i] = NULL; seghash[i] = NULL;
return SCPE_OK;
} }
static SEGINFO* new_seginfo(SEGINFO* next, uint16 base) { static SEGINFO* new_seginfo(SEGINFO* next, uint16 base) {
@ -274,10 +276,11 @@ typedef struct _aliases {
#define ALIASHASHSIZE 97 #define ALIASHASHSIZE 97
static ALIASES* aliases[ALIASHASHSIZE]; static ALIASES* aliases[ALIASHASHSIZE];
static void dbg_initaliases() { static t_stat dbg_aliasesinit() {
int i; int i;
for (i=0; i<ALIASHASHSIZE; i++) for (i=0; i<ALIASHASHSIZE; i++)
aliases[i] = NULL; aliases[i] = NULL;
return SCPE_OK;
} }
static int aliashash(const char* key) { static int aliashash(const char* key) {
@ -293,7 +296,7 @@ static ALIASES* find_alias(const char* key, int* idx) {
char gbuf[CBUFSIZE], gbuf2[CBUFSIZE]; char gbuf[CBUFSIZE], gbuf2[CBUFSIZE];
get_glyph(key, gbuf, 0); get_glyph(key, gbuf, 0);
*idx = aliashash(key); *idx = aliashash(gbuf);
a = aliases[*idx]; a = aliases[*idx];
if (a) get_glyph(a->key, gbuf2, 0); if (a) get_glyph(a->key, gbuf2, 0);
while (a && strcmp(gbuf2,gbuf)) { while (a && strcmp(gbuf2,gbuf)) {
@ -416,12 +419,12 @@ t_stat dbg_calltree(FILE* fd) {
} }
fprintf(fd,"Calltree:\nCurrently in %s at %04x:%04x\n", fprintf(fd,"Calltree:\nCurrently in %s at %04x:%04x\n",
find_procname(p), reg_segb, reg_ipc); find_procname(p), reg_segb, reg_ipc);
lastp = p; lastp = p;
p = p->next; p = p->next;
while (p) { while (p) {
fprintf(fd," at %04x:%04x called by %s (%04x:%04x)\n", fprintf(fd," at %04x:%04x called by %s (%04x:%04x)\n",
lastp->segb, lastp->instipc, find_procname(p), p->segb, p->instipc); lastp->segb, lastp->instipc, find_procname(p), p->segb, p->instipc);
lastp = p; lastp = p;
p = p->next; p = p->next;
} }
@ -435,6 +438,8 @@ t_stat dbg_calltree(FILE* fd) {
t_stat dbg_init() { t_stat dbg_init() {
dbg_opdbginit(); dbg_opdbginit();
dbg_segtrackinit(); dbg_segtrackinit();
dbg_aliasesinit();
return SCPE_OK; return SCPE_OK;
} }

9
PDQ-3/pdq3_defs.h
View file

@ -25,6 +25,7 @@
in this Software without prior written authorization from Robert M Supnik and Holger Veit. in this Software without prior written authorization from Robert M Supnik and Holger Veit.
20131103 hv INT_CONR/CONT assignments incorrect in docs, must be swapped 20131103 hv INT_CONR/CONT assignments incorrect in docs, must be swapped
20141003 hv recommended warnings from VC++ and gcc added
*/ */
#ifndef _PDQ3_DEFS_H_ #ifndef _PDQ3_DEFS_H_
#define _PDQ3_DEFS_H_ 0 #define _PDQ3_DEFS_H_ 0
@ -191,7 +192,12 @@
#define DBG_PC2 reg_segb,reg_ipc #define DBG_PC2 reg_segb,reg_ipc
/* calibration timers */ /* calibration timers */
#define TMR_CONPOLL 0 #define TMR_CONPOLL 1
/* IDLE timer. This is supposed to run at 100 Hz; the CPU runs at
* 1.25MHz, i.e. the interval is 12500. */
#define TMR_IDLE 0
#define TMR_IDLECNT 12500
/* console sio data rates */ /* console sio data rates */
#define CON_POLLUNIT 0 #define CON_POLLUNIT 0
@ -371,6 +377,7 @@ extern t_stat fprint_sym_m (FILE *of, t_addr addr, t_value *val, UNIT *uptr, int
extern t_stat con_read(t_addr ioaddr, uint16 *data); extern t_stat con_read(t_addr ioaddr, uint16 *data);
extern t_stat con_write(t_addr ioaddr, uint16 data); extern t_stat con_write(t_addr ioaddr, uint16 data);
extern t_stat con_binit(); extern t_stat con_binit();
extern t_stat fdc_boot(int32 unitnum, DEVICE *dptr);
extern t_stat fdc_read(t_addr ioaddr, uint16 *data); extern t_stat fdc_read(t_addr ioaddr, uint16 *data);
extern t_stat fdc_write(t_addr ioaddr, uint16 data); extern t_stat fdc_write(t_addr ioaddr, uint16 data);
extern t_stat fdc_autoload(); extern t_stat fdc_autoload();

33
PDQ-3/pdq3_fdc.c
View file

@ -23,6 +23,9 @@
Except as contained in this notice, the names of Robert M Supnik and Holger Veit Except as contained in this notice, the names of Robert M Supnik and Holger Veit
shall not be used in advertising or otherwise to promote the sale, use or other dealings shall not be used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Robert M Supnik and Holger Veit. in this Software without prior written authorization from Robert M Supnik and Holger Veit.
2013xxxx hv initial version
20141003 hv compiler suggested warnings (vc++2013, gcc)
*/ */
#include "pdq3_defs.h" #include "pdq3_defs.h"
#include "sim_imd.h" #include "sim_imd.h"
@ -158,7 +161,6 @@ extern UNIT cpu_unit;
/* forwards */ /* forwards */
t_stat fdc_svc (UNIT *uptr); t_stat fdc_svc (UNIT *uptr);
t_stat fdc_boot(int32 unitnum, DEVICE *dptr);
t_stat fdc_reset (DEVICE *uptr); t_stat fdc_reset (DEVICE *uptr);
t_stat fdc_attach(UNIT *uptr, char *cptr); t_stat fdc_attach(UNIT *uptr, char *cptr);
t_stat fdc_detach(UNIT *uptr); t_stat fdc_detach(UNIT *uptr);
@ -263,7 +265,7 @@ DEVICE fdc_dev = {
/* boot unit - not available through BOOT FDC cmd, use BOOT CPU instead */ /* boot unit - not available through BOOT FDC cmd, use BOOT CPU instead */
t_stat fdc_boot(int32 unitnum, DEVICE *dptr) { t_stat fdc_boot(int32 unitnum, DEVICE *dptr) {
if (unitnum < 0 || ((uint32)unitnum > dptr->numunits)) if (unitnum < 0 || (uint32)unitnum > dptr->numunits)
return SCPE_NXUN; return SCPE_NXUN;
// printf("BOOT FDC%d\n",unitnum); // printf("BOOT FDC%d\n",unitnum);
return fdc_autoload(unitnum); return fdc_autoload(unitnum);
@ -427,10 +429,9 @@ static t_bool dma_abort(t_bool fromfinish) {
sim_debug(DBG_FD_DMA, & fdc_dev, DBG_PCFORMAT2 "AUTOLOAD finished by end-of-track (DMA aborted)\n", DBG_PC); sim_debug(DBG_FD_DMA, & fdc_dev, DBG_PCFORMAT2 "AUTOLOAD finished by end-of-track (DMA aborted)\n", DBG_PC);
cpu_finishAutoload(); cpu_finishAutoload();
dma_isautoload = FALSE; dma_isautoload = FALSE;
} else } else if (!fromfinish) {
if (!fromfinish) { sim_debug(DBG_FD_DMA, & fdc_dev, DBG_PCFORMAT2 "Aborted transfer\n", DBG_PC);
sim_debug(DBG_FD_DMA, & fdc_dev, DBG_PCFORMAT2 "Aborted transfer\n", DBG_PC); }
}
return FALSE; return FALSE;
} }
@ -522,7 +523,7 @@ static t_bool dma_transfer_from_ram(uint8 *buf, int bufsize) {
dma_interrupt(DMA_CTRL_TOIE); dma_interrupt(DMA_CTRL_TOIE);
return FALSE; /* write fault */ return FALSE; /* write fault */
} }
buf[i] = data; buf[i] = data & 0xff;
_reg_dma_cnt++; _reg_dma_cnt++;
if (_reg_dma_cnt == 0) /* all data done? */ if (_reg_dma_cnt == 0) /* all data done? */
break; break;
@ -930,7 +931,7 @@ static t_stat fdc_docmd(uint16 data) {
} }
void dma_docmd(uint16 data) { void dma_docmd(uint16 data) {
reg_dma_ctrl = data; reg_dma_ctrl = data & 0xff;
reg_dma_status &= 0x8f; reg_dma_status &= 0x8f;
reg_dma_status |= (reg_dma_ctrl & 0x70); reg_dma_status |= (reg_dma_ctrl & 0x70);
@ -941,11 +942,9 @@ void dma_docmd(uint16 data) {
/* setup FDC/DMA to read first track into low memory */ /* setup FDC/DMA to read first track into low memory */
t_stat fdc_autoload(int unitnum) { t_stat fdc_autoload(int unitnum) {
int unitbit = 1 << unitnum; int unitbit = 1 << unitnum;
sim_debug(DBG_FD_CMD, &fdc_dev, DBG_PCFORMAT2 "Autoload Unit=%d\n", DBG_PC, unitnum); sim_debug(DBG_FD_CMD, &fdc_dev, DBG_PCFORMAT2 "Autoload Unit=%d\n", DBG_PC, unitnum);
dma_isautoload = TRUE; dma_isautoload = TRUE;
/* note: this is partly in microcode/ROM. The DMA cntrlr itself does not set the /* note: this is partly in microcode/ROM. The DMA cntrlr itself does not set the
* FDC register for multi_read */ * FDC register for multi_read */
fdc_reset(&fdc_dev); fdc_reset(&fdc_dev);
@ -996,22 +995,22 @@ t_stat fdc_write(t_addr ioaddr, uint16 data) {
reg_dma_status = data & 0x8f; reg_dma_status = data & 0x8f;
break; break;
case 0x0a: /* count low */ case 0x0a: /* count low */
reg_dma_cntl = data; reg_dma_cntl = data & 0xff;
break; break;
case 0x0b: /* count high */ case 0x0b: /* count high */
reg_dma_cnth = data; reg_dma_cnth = data & 0xff;
break; break;
case 0x0c: /* addr low */ case 0x0c: /* addr low */
reg_dma_addrl = data; reg_dma_addrl = data & 0xff;
break; break;
case 0x0d: /* addr high */ case 0x0d: /* addr high */
reg_dma_addrh = data; reg_dma_addrh = data & 0xff;
break; break;
case 0x0e: /* addr ext */ case 0x0e: /* addr ext */
reg_dma_addre = data & 0x03; reg_dma_addre = data & 0x03;
break; break;
case 0x0f: /* ID register */ case 0x0f: /* ID register */
reg_dma_id = data; reg_dma_id = data & 0xff;
break; break;
} }
_reg_dma_cnt = (reg_dma_cnth << 8) | reg_dma_cntl; _reg_dma_cnt = (reg_dma_cnth << 8) | reg_dma_cntl;
@ -1148,7 +1147,7 @@ t_stat pdq3_diskCreate(FILE *fileref, char *ctlr_comment) {
} }
t_stat pdq3_diskFormat(DISK_INFO *myDisk) { t_stat pdq3_diskFormat(DISK_INFO *myDisk) {
uint8 i; uint8 i = 0;
uint8 sector_map[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26}; uint8 sector_map[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26};
uint32 flags; uint32 flags;
@ -1156,7 +1155,7 @@ t_stat pdq3_diskFormat(DISK_INFO *myDisk) {
/* format first track as 26 sectors with 128 bytes */ /* format first track as 26 sectors with 128 bytes */
if((trackWrite(myDisk, 0, 0, 26, 128, sector_map, IMD_MODE_500K_FM, 0xE5, &flags)) != 0) { if((trackWrite(myDisk, 0, 0, 26, 128, sector_map, IMD_MODE_500K_FM, 0xE5, &flags)) != 0) {
printf("PDQ3_IMD: Error formatting track 0\n"); printf("PDQ3_IMD: Error formatting track %d\n", i);
return SCPE_IOERR; return SCPE_IOERR;
} }
putchar('.'); putchar('.');

3
PDQ-3/pdq3_mem.c
View file

@ -113,7 +113,6 @@ t_stat set_iobase(UNIT *uptr, int32 val, char *cptr, void *desc) {
DEVICE* dptr; DEVICE* dptr;
DEVCTXT* ctxt; DEVCTXT* ctxt;
IOINFO* ioi; IOINFO* ioi;
t_bool first = TRUE;
if (!cptr) return SCPE_ARG; if (!cptr) return SCPE_ARG;
if (!uptr) return SCPE_IERR; if (!uptr) return SCPE_IERR;
if ((dptr = find_dev_from_unit(uptr)) == 0) return SCPE_IERR; if ((dptr = find_dev_from_unit(uptr)) == 0) return SCPE_IERR;
@ -130,7 +129,6 @@ t_stat set_iovec(UNIT *uptr, int32 val, char *cptr, void *desc) {
DEVICE* dptr; DEVICE* dptr;
DEVCTXT* ctxt; DEVCTXT* ctxt;
IOINFO* ioi; IOINFO* ioi;
t_bool first = TRUE;
if (!cptr) return SCPE_ARG; if (!cptr) return SCPE_ARG;
if (!uptr) return SCPE_IERR; if (!uptr) return SCPE_IERR;
if ((dptr = find_dev_from_unit(uptr)) == 0) return SCPE_IERR; if ((dptr = find_dev_from_unit(uptr)) == 0) return SCPE_IERR;
@ -166,7 +164,6 @@ t_stat set_ioprio(UNIT *uptr, int32 val, char *cptr, void *desc) {
DEVICE* dptr; DEVICE* dptr;
DEVCTXT* ctxt; DEVCTXT* ctxt;
IOINFO* ioi; IOINFO* ioi;
t_bool first = TRUE;
if (!cptr) return SCPE_ARG; if (!cptr) return SCPE_ARG;
if (!uptr) return SCPE_IERR; if (!uptr) return SCPE_IERR;
if ((dptr = find_dev_from_unit(uptr)) == 0) return SCPE_IERR; if ((dptr = find_dev_from_unit(uptr)) == 0) return SCPE_IERR;

11
PDQ-3/pdq3_stddev.c
View file

@ -25,9 +25,11 @@
other dealings in this Software without prior written authorization from other dealings in this Software without prior written authorization from
Robert M Supnik and Holger Veit. Robert M Supnik and Holger Veit.
2013xxxx hv initial version
20130902 hv added telnet multiplexer code 20130902 hv added telnet multiplexer code
20131020 hv fixed CON interrupt handling 20131020 hv fixed CON interrupt handling
20131103 hv connect CON_ATTACH logic with DSR, so that DSR is set if tcp connect 20131103 hv connect CON_ATTACH logic with DSR, so that DSR is set if tcp connect
20141003 hv compiler suggested warnings (vc++2013, gcc)
*/ */
#include "pdq3_defs.h" #include "pdq3_defs.h"
#include <ctype.h> #include <ctype.h>
@ -348,6 +350,8 @@ static int set_parity(int c, int odd)
if (!odd) c ^= 0x80; if (!odd) c ^= 0x80;
return c; return c;
} }
#if 0
// currently unused
static int get_parity(int c, int even) static int get_parity(int c, int even)
{ {
int i, p = 0; int i, p = 0;
@ -356,6 +360,7 @@ static int get_parity(int c, int even)
if (even) p ^= 1; if (even) p ^= 1;
return p; return p;
} }
#endif
// functions from memory handler to read and write a char // functions from memory handler to read and write a char
// note: the usart is connected to inverted data lines, // note: the usart is connected to inverted data lines,
@ -372,7 +377,7 @@ t_stat con_write(t_addr ioaddr, uint16 data) {
data = (~data) & 0xff; data = (~data) & 0xff;
switch (ioaddr & 0x0003) { switch (ioaddr & 0x0003) {
case 0: /* CTRL1 */ case 0: /* CTRL1 */
con_ctrl1 = data; con_ctrl1 = data & 0xff;
if (!RCVENABLED()) { /* disable receiver */ if (!RCVENABLED()) { /* disable receiver */
clrbit(con_status,CONS_FE|CONS_PE|CONS_OE|CONS_DR); clrbit(con_status,CONS_FE|CONS_PE|CONS_OE|CONS_DR);
sim_cancel(poll); sim_cancel(poll);
@ -391,7 +396,7 @@ t_stat con_write(t_addr ioaddr, uint16 data) {
} }
break; break;
case 1: case 1:
con_ctrl2 = data; con_ctrl2 = data & 0xff;
break; break;
case 2: case 2:
// ignore this here - DLE register // ignore this here - DLE register
@ -406,7 +411,7 @@ t_stat con_write(t_addr ioaddr, uint16 data) {
break; break;
case CONC2_CLEN8: data &= 0xff; break; case CONC2_CLEN8: data &= 0xff; break;
} }
con_xmit = data; con_xmit = data & 0xff;
term->buf = data; term->buf = data;
clrbit(con_status,CONS_THRE); clrbit(con_status,CONS_THRE);
if (XMITENABLED()) if (XMITENABLED())

11
PDQ-3/pdq3_sys.c
View file

@ -28,18 +28,17 @@
20130907 hv added VIEWSEG command 20130907 hv added VIEWSEG command
20130925 hv added CALL and NAME command 20130925 hv added CALL and NAME command
20130927 hv wrong disassembly of LDC instr 20130927 hv wrong disassembly of LDC instr
20141003 hv compiler suggested warnings (vc++2013, gcc)
*/ */
#include "pdq3_defs.h" #include "pdq3_defs.h"
#include <ctype.h> #include <ctype.h>
static int disass(t_addr addr);
t_stat parse_sym_m (char *cptr, t_value *val, int32 sw); t_stat parse_sym_m (char *cptr, t_value *val, int32 sw);
void pdq3_vm_init (void); void pdq3_vm_init (void);
static t_stat pdq3_cmd_exstack(int32 arg, char *buf); static t_stat pdq3_cmd_exstack(int32 arg, char *buf);
static t_stat pdq3_cmd_exmscw(int32 arg, char *buf); static t_stat pdq3_cmd_exmscw(int32 arg, char *buf);
static t_stat pdq3_cmd_extib(int32 arg, char *buf); static t_stat pdq3_cmd_extib(int32 arg, char *buf);
static t_stat pdq3_cmd_exseg(int32 arg, char *buf); static t_stat pdq3_cmd_exseg(int32 arg, char *buf);
static t_stat pdq3_cmd_calcea(int32 arg, char *buf);
static t_stat pdq3_cmd_calltree(int32 arg, char *buf); static t_stat pdq3_cmd_calltree(int32 arg, char *buf);
static t_stat pdq3_cmd_namealias(int32 arg, char *buf); static t_stat pdq3_cmd_namealias(int32 arg, char *buf);
@ -52,7 +51,6 @@ extern REG cpu_reg[];
extern uint16 M[]; extern uint16 M[];
extern uint16 reg_pc; extern uint16 reg_pc;
/* SCP data structures and interface routines /* SCP data structures and interface routines
sim_name simulator name string sim_name simulator name string
sim_PC pointer to saved PC register descriptor sim_PC pointer to saved PC register descriptor
@ -541,7 +539,6 @@ t_stat fprint_sym (FILE *of, t_addr addr, t_value *val,
T_FLCVT t; T_FLCVT t;
int ch; int ch;
t_bool hexdec = (sw & SWMASK('H')) ? TRUE : FALSE;
if (sw & SWMASK('M') && !ADDR_ISWORD(addr)) { if (sw & SWMASK('M') && !ADDR_ISWORD(addr)) {
return fprint_sym_m(of, addr, val, uptr, sw); return fprint_sym_m(of, addr, val, uptr, sw);
} }
@ -570,11 +567,11 @@ t_stat fprint_sym (FILE *of, t_addr addr, t_value *val,
if (ADDR_ISWORD(addr)) { if (ADDR_ISWORD(addr)) {
fprint_val(of, val[0], cpu_dev.dradix, 16, PV_RZRO); fprint_val(of, val[0], cpu_dev.dradix, 16, PV_RZRO);
off = ADDR_OFF(addr); off = ADDR_OFF(addr);
if (off > (reg_bp+MSCW_SZ-1)) if (off > (t_addr)(reg_bp+MSCW_SZ-1))
fprintf(of," (GLOBAL+%d)", off - reg_bp - MSCW_SZ + 1); fprintf(of," (GLOBAL+%d)", off - reg_bp - MSCW_SZ + 1);
else if (off >= reg_mp && off <= (reg_mp+OFFB_MSSEG)) else if (off >= reg_mp && off <= (t_addr)(reg_mp+OFFB_MSSEG))
fprintf(of," (MP+%d)", off - reg_mp); fprintf(of," (MP+%d)", off - reg_mp);
else if (off > (reg_mp+MSCW_SZ-1)) else if (off > (t_addr)(reg_mp+MSCW_SZ-1))
fprintf(of," (LOCAL+%d)", off - reg_mp - MSCW_SZ + 1); fprintf(of," (LOCAL+%d)", off - reg_mp - MSCW_SZ + 1);
else if (off >= reg_sp && off < reg_spupr) else if (off >= reg_sp && off < reg_spupr)
fprintf(of," (SP+%d)", off - reg_sp); fprintf(of," (SP+%d)", off - reg_sp);