pdp11_xu - SELFTEST needs to report the READY state otherwise VMS 3.7 gets fatal controller error - Update from Rob Jarratt
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@ -62,6 +62,7 @@
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Modification history:
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Modification history:
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25-Jan-13 RJ SELFTEST needs to report the READY state otherwise VMS 3.7 gets fatal controller error
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12-Jan-11 DTH Added SHOW XU FILTERS modifier
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12-Jan-11 DTH Added SHOW XU FILTERS modifier
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11-Jan-11 DTH Corrected SELFTEST command, enabling use by VMS 3.7, VMS 4.7, and Ultrix 1.1
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11-Jan-11 DTH Corrected SELFTEST command, enabling use by VMS 3.7, VMS 4.7, and Ultrix 1.1
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09-Dec-10 MP Added address conflict check during attach.
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09-Dec-10 MP Added address conflict check during attach.
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@ -1456,6 +1457,9 @@ void xu_port_command (CTLR* xu)
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controller's progress through the diagnostic testing.
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controller's progress through the diagnostic testing.
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*/
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*/
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xu->var->pcsr0 |= PCSR0_DNI;
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xu->var->pcsr0 |= PCSR0_DNI;
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xu->var->pcsr0 &= ~PCSR0_USCI;
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xu->var->pcsr0 &= ~PCSR0_FATL;
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xu->var->pcsr1 = STATE_READY;
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break;
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break;
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case CMD_START: /* START */
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case CMD_START: /* START */
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@ -28,6 +28,7 @@
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Modification history:
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Modification history:
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25-Jan-13 RJ SELFTEST needs to report the READY state otherwise VMS 3.7 gets fatal controller error
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23-Jan-08 MP Added debugging support to display packet headers and packet data
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23-Jan-08 MP Added debugging support to display packet headers and packet data
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08-Dec-05 DTH Added load_server, increased UDBSIZE for system ID parameters
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08-Dec-05 DTH Added load_server, increased UDBSIZE for system ID parameters
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07-Jul-05 RMS Removed extraneous externs
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07-Jul-05 RMS Removed extraneous externs
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@ -173,6 +174,7 @@ typedef struct xu_controller CTLR;
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#define PCSR0_TXI 0010000 /* <12> Transmit Interrupt */
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#define PCSR0_TXI 0010000 /* <12> Transmit Interrupt */
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#define PCSR0_DNI 0004000 /* <11> Done Interrupt */
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#define PCSR0_DNI 0004000 /* <11> Done Interrupt */
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#define PCSR0_RCBI 0002000 /* <10> Recv Buffer Unavail Intr */
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#define PCSR0_RCBI 0002000 /* <10> Recv Buffer Unavail Intr */
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#define PCSR0_FATL 0001000 /* <09> Fatal Internal Error */
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#define PCSR0_USCI 0000400 /* <08> Unsolicited State Chg Inter */
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#define PCSR0_USCI 0000400 /* <08> Unsolicited State Chg Inter */
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#define PCSR0_INTR 0000200 /* <07> Interrupt Summary */
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#define PCSR0_INTR 0000200 /* <07> Interrupt Summary */
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#define PCSR0_INTE 0000100 /* <06> Interrupt Enable */
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#define PCSR0_INTE 0000100 /* <06> Interrupt Enable */
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