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ISYS8010: Removed remaining tabs (converted to spaces).

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Bill Beech 2015-04-28 14:14:38 -07:00 • committed by Mark Pizzolato
parent f36a8de70d
commit 7e3a32fc06
7 changed files with 195 additions and 195 deletions
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278
isys8010/common/i8259.c
View file

@ -27,8 +27,8 @@
24 Jan 13 - Original file. 24 Jan 13 - Original file.
*/ */
#include "system_defs.h" /* system header in system dir */ #include "system_defs.h" /* system header in system dir */
#define i8259_DEV 2 /* number of devices */ #define i8259_DEV 2 /* number of devices */
/* function prototypes */ /* function prototypes */
@ -119,67 +119,67 @@ int32 i8259a0(int32 io, int32 data)
int32 bit; int32 bit;
if (io == 0) { /* read data port */ if (io == 0) { /* read data port */
if ((i8259_ocw3[0] & 0x03) == 0x02) if ((i8259_ocw3[0] & 0x03) == 0x02)
return (i8259_unit[0].u3); /* IRR */ return (i8259_unit[0].u3); /* IRR */
if ((i8259_ocw3[0] & 0x03) == 0x03) if ((i8259_ocw3[0] & 0x03) == 0x03)
return (i8259_unit[0].u4); /* ISR */ return (i8259_unit[0].u4); /* ISR */
} else { /* write data port */ } else { /* write data port */
if (data & 0x10) { if (data & 0x10) {
icw_num0 = 1; icw_num0 = 1;
} }
if (icw_num0 == 1) { if (icw_num0 == 1) {
i8259_icw1[0] = data; /* ICW1 */ i8259_icw1[0] = data; /* ICW1 */
i8259_unit[0].u5 = 0x00; /* clear IMR */ i8259_unit[0].u5 = 0x00; /* clear IMR */
i8259_ocw3[0] = 0x02; /* clear OCW3, Sel IRR */ i8259_ocw3[0] = 0x02; /* clear OCW3, Sel IRR */
} else { } else {
switch (data & 0x18) { switch (data & 0x18) {
case 0: /* OCW2 */ case 0: /* OCW2 */
i8259_ocw2[0] = data; i8259_ocw2[0] = data;
break; break;
case 8: /* OCW3 */ case 8: /* OCW3 */
i8259_ocw3[0] = data; i8259_ocw3[0] = data;
break; break;
default: default:
printf("8259b-0: OCW Error %02X\n", data); printf("8259b-0: OCW Error %02X\n", data);
break; break;
} }
} }
printf("8259a-0: data = %02X\n", data); printf("8259a-0: data = %02X\n", data);
icw_num0++; /* step ICW number */ icw_num0++; /* step ICW number */
} }
i8259_dump(0); i8259_dump(0);
return 0; return 0;
} }
int32 i8259b0(int32 io, int32 data) int32 i8259b0(int32 io, int32 data)
{ {
if (io == 0) { /* read data port */ if (io == 0) { /* read data port */
return (i8259_unit[0].u5); /* IMR */ return (i8259_unit[0].u5); /* IMR */
} else { /* write data port */ } else { /* write data port */
if (icw_num0 >= 2 && icw_num0 < 5) { /* ICW mode */ if (icw_num0 >= 2 && icw_num0 < 5) { /* ICW mode */
switch (icw_num0) { switch (icw_num0) {
case 2: /* ICW2 */ case 2: /* ICW2 */
i8259_icw2[0] = data; i8259_icw2[0] = data;
break; break;
case 3: /* ICW3 */ case 3: /* ICW3 */
i8259_icw3[0] = data; i8259_icw3[0] = data;
break; break;
case 4: /* ICW4 */ case 4: /* ICW4 */
if (i8259_icw1[0] & 0x01) if (i8259_icw1[0] & 0x01)
i8259_icw4[0] = data; i8259_icw4[0] = data;
else else
printf("8259b-0: ICW4 not enabled - data=%02X\n", data); printf("8259b-0: ICW4 not enabled - data=%02X\n", data);
break; break;
default: default:
printf("8259b-0: ICW Error %02X\n", data); printf("8259b-0: ICW Error %02X\n", data);
break; break;
} }
icw_num0++; icw_num0++;
} else { } else {
i8259_ocw1[0] = data; /* OCW0 */ i8259_ocw1[0] = data; /* OCW0 */
} }
} }
i8259_dump(0); i8259_dump(0);
return 0; return 0;
} }
@ -188,116 +188,116 @@ int32 i8259a1(int32 io, int32 data)
int32 bit; int32 bit;
if (io == 0) { /* read data port */ if (io == 0) { /* read data port */
if ((i8259_ocw3[1] & 0x03) == 0x02) if ((i8259_ocw3[1] & 0x03) == 0x02)
return (i8259_unit[1].u3); /* IRR */ return (i8259_unit[1].u3); /* IRR */
if ((i8259_ocw3[1] & 0x03) == 0x03) if ((i8259_ocw3[1] & 0x03) == 0x03)
return (i8259_unit[1].u4); /* ISR */ return (i8259_unit[1].u4); /* ISR */
} else { /* write data port */ } else { /* write data port */
if (data & 0x10) { if (data & 0x10) {
icw_num1 = 1; icw_num1 = 1;
} }
if (icw_num1 == 1) { if (icw_num1 == 1) {
i8259_icw1[1] = data; /* ICW1 */ i8259_icw1[1] = data; /* ICW1 */
i8259_unit[1].u5 = 0x00; /* clear IMR */ i8259_unit[1].u5 = 0x00; /* clear IMR */
i8259_ocw3[1] = 0x02; /* clear OCW3, Sel IRR */ i8259_ocw3[1] = 0x02; /* clear OCW3, Sel IRR */
} else { } else {
switch (data & 0x18) { switch (data & 0x18) {
case 0: /* OCW2 */ case 0: /* OCW2 */
i8259_ocw2[1] = data; i8259_ocw2[1] = data;
break; break;
case 8: /* OCW3 */ case 8: /* OCW3 */
i8259_ocw3[1] = data; i8259_ocw3[1] = data;
break; break;
default: default:
printf("8259b-1: OCW Error %02X\n", data); printf("8259b-1: OCW Error %02X\n", data);
break; break;
} }
} }
printf("8259a-1: data = %02X\n", data); printf("8259a-1: data = %02X\n", data);
icw_num1++; /* step ICW number */ icw_num1++; /* step ICW number */
} }
i8259_dump(1); i8259_dump(1);
return 0; return 0;
} }
int32 i8259b1(int32 io, int32 data) int32 i8259b1(int32 io, int32 data)
{ {
if (io == 0) { /* read data port */ if (io == 0) { /* read data port */
return (i8259_unit[1].u5); /* IMR */ return (i8259_unit[1].u5); /* IMR */
} else { /* write data port */ } else { /* write data port */
if (icw_num1 >= 2 && icw_num1 < 5) { /* ICW mode */ if (icw_num1 >= 2 && icw_num1 < 5) { /* ICW mode */
switch (icw_num1) { switch (icw_num1) {
case 2: /* ICW2 */ case 2: /* ICW2 */
i8259_icw2[1] = data; i8259_icw2[1] = data;
break; break;
case 3: /* ICW3 */ case 3: /* ICW3 */
i8259_icw3[1] = data; i8259_icw3[1] = data;
break; break;
case 4: /* ICW4 */ case 4: /* ICW4 */
if (i8259_icw1[1] & 0x01) if (i8259_icw1[1] & 0x01)
i8259_icw4[1] = data; i8259_icw4[1] = data;
else else
printf("8259b-1: ICW4 not enabled - data=%02X\n", data); printf("8259b-1: ICW4 not enabled - data=%02X\n", data);
break; break;
default: default:
printf("8259b-1: ICW Error %02X\n", data); printf("8259b-1: ICW Error %02X\n", data);
break; break;
} }
icw_num1++; icw_num1++;
} else { } else {
i8259_ocw1[1] = data; /* OCW0 */ i8259_ocw1[1] = data; /* OCW0 */
} }
} }
i8259_dump(1); i8259_dump(1);
return 0; return 0;
} }
void i8259_dump(int32 dev) void i8259_dump(int32 dev)
{ {
printf("Device %d\n", dev); printf("Device %d\n", dev);
printf(" IRR = %02X\n", i8259_unit[dev].u3); printf(" IRR = %02X\n", i8259_unit[dev].u3);
printf(" ISR = %02X\n", i8259_unit[dev].u4); printf(" ISR = %02X\n", i8259_unit[dev].u4);
printf(" IMR = %02X\n", i8259_unit[dev].u5); printf(" IMR = %02X\n", i8259_unit[dev].u5);
printf(" ICW1 = %02X\n", i8259_icw1[dev]); printf(" ICW1 = %02X\n", i8259_icw1[dev]);
printf(" ICW2 = %02X\n", i8259_icw2[dev]); printf(" ICW2 = %02X\n", i8259_icw2[dev]);
printf(" ICW3 = %02X\n", i8259_icw3[dev]); printf(" ICW3 = %02X\n", i8259_icw3[dev]);
printf(" ICW4 = %02X\n", i8259_icw4[dev]); printf(" ICW4 = %02X\n", i8259_icw4[dev]);
printf(" OCW1 = %02X\n", i8259_ocw1[dev]); printf(" OCW1 = %02X\n", i8259_ocw1[dev]);
printf(" OCW2 = %02X\n", i8259_ocw2[dev]); printf(" OCW2 = %02X\n", i8259_ocw2[dev]);
printf(" OCW3 = %02X\n", i8259_ocw3[dev]); printf(" OCW3 = %02X\n", i8259_ocw3[dev]);
} }
/* Reset routine */ /* Reset routine */
t_stat i8259_reset (DEVICE *dptr, int32 base) t_stat i8259_reset (DEVICE *dptr, int32 base)
{ {
switch (i8259_cnt) { switch (i8259_cnt) {
case 0: case 0:
reg_dev(i8259a0, base); reg_dev(i8259a0, base);
reg_dev(i8259b0, base + 1); reg_dev(i8259b0, base + 1);
reg_dev(i8259a0, base + 2); reg_dev(i8259a0, base + 2);
reg_dev(i8259b0, base + 3); reg_dev(i8259b0, base + 3);
i8259_unit[0].u3 = 0x00; /* IRR */ i8259_unit[0].u3 = 0x00; /* IRR */
i8259_unit[0].u4 = 0x00; /* ISR */ i8259_unit[0].u4 = 0x00; /* ISR */
i8259_unit[0].u5 = 0x00; /* IMR */ i8259_unit[0].u5 = 0x00; /* IMR */
printf(" 8259-0: Reset\n"); printf(" 8259-0: Reset\n");
break; break;
case 1: case 1:
reg_dev(i8259a1, base); reg_dev(i8259a1, base);
reg_dev(i8259b1, base + 1); reg_dev(i8259b1, base + 1);
reg_dev(i8259a1, base + 2); reg_dev(i8259a1, base + 2);
reg_dev(i8259b1, base + 3); reg_dev(i8259b1, base + 3);
i8259_unit[1].u3 = 0x00; /* IRR */ i8259_unit[1].u3 = 0x00; /* IRR */
i8259_unit[1].u4 = 0x00; /* ISR */ i8259_unit[1].u4 = 0x00; /* ISR */
i8259_unit[1].u5 = 0x00; /* IMR */ i8259_unit[1].u5 = 0x00; /* IMR */
printf(" 8259-1: Reset\n"); printf(" 8259-1: Reset\n");
break; break;
default: default:
printf(" 8259: Bad device\n"); printf(" 8259: Bad device\n");
break; break;
} }
printf(" 8259-%d: Registered at %02X\n", i8259_cnt, base); printf(" 8259-%d: Registered at %02X\n", i8259_cnt, base);
i8259_cnt++; i8259_cnt++;
return SCPE_OK; return SCPE_OK;
} }

8
isys8010/common/iSBC80-10.c
View file

@ -37,16 +37,16 @@
#include "system_defs.h" #include "system_defs.h"
/* set the base I/O address for the first 8255 */ /* set the base I/O address for the first 8255 */
#define I8255_BASE_0 0xE4 #define I8255_BASE_0 0xE4
/* set the base I/O address for the second 8255 */ /* set the base I/O address for the second 8255 */
#define I8255_BASE_1 0xE8 #define I8255_BASE_1 0xE8
/* set the base I/O address for the 8251 */ /* set the base I/O address for the 8251 */
#define I8251_BASE 0xEC #define I8251_BASE 0xEC
/* set the base and size for the EPROM on the iSBC 80/10 */ /* set the base and size for the EPROM on the iSBC 80/10 */
#define ROM_SIZE 0x1000 #define ROM_SIZE 0x1000
/* set the base and size for the RAM on the iSBC 80/10 */ /* set the base and size for the RAM on the iSBC 80/10 */
#define RAM_BASE 0x3C00 #define RAM_BASE 0x3C00

20
isys8010/common/iSBC80-20.c
View file

@ -32,16 +32,16 @@
#include "system_defs.h" #include "system_defs.h"
/* set the base I/O address for the 8259 */ /* set the base I/O address for the 8259 */
#define I8259_BASE 0xD8 #define I8259_BASE 0xD8
/* set the base I/O address for the first 8255 */ /* set the base I/O address for the first 8255 */
#define I8255_BASE_0 0xE4 #define I8255_BASE_0 0xE4
/* set the base I/O address for the second 8255 */ /* set the base I/O address for the second 8255 */
#define I8255_BASE_1 0xE8 #define I8255_BASE_1 0xE8
/* set the base I/O address for the 8251 */ /* set the base I/O address for the 8251 */
#define I8251_BASE 0xEC #define I8251_BASE 0xEC
/* set the base and size for the EPROM on the iSBC 80/20 */ /* set the base and size for the EPROM on the iSBC 80/20 */
#define ROM_SIZE 0x1000 #define ROM_SIZE 0x1000
@ -86,12 +86,12 @@ t_stat SBC_reset (DEVICE *dptr)
{ {
printf("Initializing iSBC-80/20\n"); printf("Initializing iSBC-80/20\n");
i8080_reset(NULL); i8080_reset(NULL);
i8259_reset(NULL, I8259_BASE); i8259_reset(NULL, I8259_BASE);
i8255_reset(NULL, I8255_BASE_0); i8255_reset(NULL, I8255_BASE_0);
i8255_reset(NULL, I8255_BASE_1); i8255_reset(NULL, I8255_BASE_1);
i8251_reset(NULL, I8251_BASE); i8251_reset(NULL, I8251_BASE);
EPROM_reset(NULL, ROM_SIZE); EPROM_reset(NULL, ROM_SIZE);
RAM_reset(NULL, RAM_BASE, RAM_SIZE); RAM_reset(NULL, RAM_BASE, RAM_SIZE);
return SCPE_OK; return SCPE_OK;
} }

20
isys8010/common/iSBC80-30.c
View file

@ -32,16 +32,16 @@
#include "system_defs.h" #include "system_defs.h"
/* set the base I/O address for the 8259 */ /* set the base I/O address for the 8259 */
#define I8259_BASE 0xD8 #define I8259_BASE 0xD8
/* set the base I/O address for the first 8255 */ /* set the base I/O address for the first 8255 */
#define I8255_BASE_0 0xE4 #define I8255_BASE_0 0xE4
/* set the base I/O address for the second 8255 */ /* set the base I/O address for the second 8255 */
#define I8255_BASE_1 0xE8 #define I8255_BASE_1 0xE8
/* set the base I/O address for the 8251 */ /* set the base I/O address for the 8251 */
#define I8251_BASE 0xEC #define I8251_BASE 0xEC
/* set the base and size for the EPROM on the iSBC 80/20 */ /* set the base and size for the EPROM on the iSBC 80/20 */
#define ROM_SIZE 0x1000 #define ROM_SIZE 0x1000
@ -86,12 +86,12 @@ t_stat SBC_reset (DEVICE *dptr)
{ {
printf("Initializing iSBC-80/20\n"); printf("Initializing iSBC-80/20\n");
i8080_reset(NULL); i8080_reset(NULL);
i8259_reset(NULL, I8259_BASE); i8259_reset(NULL, I8259_BASE);
i8255_reset(NULL, I8255_BASE_0); i8255_reset(NULL, I8255_BASE_0);
i8255_reset(NULL, I8255_BASE_1); i8255_reset(NULL, I8255_BASE_1);
i8251_reset(NULL, I8251_BASE); i8251_reset(NULL, I8251_BASE);
EPROM_reset(NULL, ROM_SIZE); EPROM_reset(NULL, ROM_SIZE);
RAM_reset(NULL, RAM_BASE, RAM_SIZE); RAM_reset(NULL, RAM_BASE, RAM_SIZE);
return SCPE_OK; return SCPE_OK;
} }

32
isys8010/common/ijedec.c
View file

@ -96,16 +96,16 @@
#define JEDEC_NUM 4 #define JEDEC_NUM 4
#define UNIT_V_DMODE (UNIT_V_UF) /* data bus mode */ #define UNIT_V_DMODE (UNIT_V_UF) /* data bus mode */
#define UNIT_DMODE (1 << UNIT_V_DMODE) #define UNIT_DMODE (1 << UNIT_V_DMODE)
#define UNIT_V_MSIZE (UNIT_V_UF+1) /* Memory Size */ #define UNIT_V_MSIZE (UNIT_V_UF+1) /* Memory Size */
#define UNIT_MSIZE (1 << UNIT_V_MSIZE) #define UNIT_MSIZE (1 << UNIT_V_MSIZE)
#define UNIT_NONE 0 /* No device */ #define UNIT_NONE 0 /* No device */
#define UNIT_8KROM 1 /* 8KB ROM */ #define UNIT_8KROM 1 /* 8KB ROM */
#define UNIT_16KROM 2 /* 16KB ROM */ #define UNIT_16KROM 2 /* 16KB ROM */
#define UNIT_32KROM 3 /* 32KB ROM */ #define UNIT_32KROM 3 /* 32KB ROM */
#define UNIT_8KRAM 4 /* 8KB RAM */ #define UNIT_8KRAM 4 /* 8KB RAM */
#define UNIT_32KRAM 5 /* 32KB RAM */ #define UNIT_32KRAM 5 /* 32KB RAM */
#define RAM 0x00000001 #define RAM 0x00000001
#define D16BIT 0x00000002 #define D16BIT 0x00000002
@ -239,9 +239,9 @@ t_stat JEDEC_set_size (UNIT *uptr, int32 val, char *cptr, void *desc)
uptr->capac = 0; uptr->capac = 0;
uptr->u5 &= ~RAM; /* ROM */ uptr->u5 &= ~RAM; /* ROM */
if (uptr->u6 == JEDEC_NUM - 1) {/* top unit ? */ if (uptr->u6 == JEDEC_NUM - 1) {/* top unit ? */
uptr->u3 = 0; /* base address */ uptr->u3 = 0; /* base address */
printf("JEDEC site size set to 8KB\n"); printf("JEDEC site size set to 8KB\n");
for (i = 0; i < JEDEC_NUM-1; i++) { /* clear all units but last unit */ for (i = 0; i < JEDEC_NUM-1; i++) { /* clear all units but last unit */
uptr1 = JEDEC_dev.units + i; uptr1 = JEDEC_dev.units + i;
uptr1->capac = 0; uptr1->capac = 0;
} }
@ -255,7 +255,7 @@ t_stat JEDEC_set_size (UNIT *uptr, int32 val, char *cptr, void *desc)
if (uptr->u6 == JEDEC_NUM - 1) {/* top unit ? */ if (uptr->u6 == JEDEC_NUM - 1) {/* top unit ? */
uptr->u3 = basadr + (uptr->capac * uptr->u6); /* base address */ uptr->u3 = basadr + (uptr->capac * uptr->u6); /* base address */
printf("JEDEC site size set to 8KB\n"); printf("JEDEC site size set to 8KB\n");
for (i = 0; i < JEDEC_NUM-1; i++) { /* clear all units but last unit */ for (i = 0; i < JEDEC_NUM-1; i++) { /* clear all units but last unit */
uptr1 = JEDEC_dev.units + i; uptr1 = JEDEC_dev.units + i;
uptr1->capac = 0; uptr1->capac = 0;
} }
@ -274,7 +274,7 @@ t_stat JEDEC_set_size (UNIT *uptr, int32 val, char *cptr, void *desc)
if (uptr->u6 == JEDEC_NUM - 1) {/* top unit ? */ if (uptr->u6 == JEDEC_NUM - 1) {/* top unit ? */
uptr->u3 = basadr + (uptr->capac * uptr->u6); /* base address */ uptr->u3 = basadr + (uptr->capac * uptr->u6); /* base address */
printf("JEDEC site size set to 16KB\n"); printf("JEDEC site size set to 16KB\n");
for (i = 0; i < JEDEC_NUM-1; i++) { /* clear all units but last unit */ for (i = 0; i < JEDEC_NUM-1; i++) { /* clear all units but last unit */
uptr1 = JEDEC_dev.units + i; uptr1 = JEDEC_dev.units + i;
uptr1->capac = 0; uptr1->capac = 0;
} }
@ -312,9 +312,9 @@ t_stat JEDEC_set_size (UNIT *uptr, int32 val, char *cptr, void *desc)
if (uptr1->capac != uptr->capac) { if (uptr1->capac != uptr->capac) {
uptr->capac = 0; uptr->capac = 0;
printf("JEDEC site size precludes use of this device\n"); printf("JEDEC site size precludes use of this device\n");
} else { } else {
uptr->u5 |= RAM; /* RAM */ uptr->u5 |= RAM; /* RAM */
} }
} }
break; break;
case UNIT_32KRAM: case UNIT_32KRAM:
@ -325,9 +325,9 @@ t_stat JEDEC_set_size (UNIT *uptr, int32 val, char *cptr, void *desc)
if (uptr1->capac != uptr->capac) { if (uptr1->capac != uptr->capac) {
uptr->capac = 0; uptr->capac = 0;
printf("JEDEC site size precludes use of this device\n"); printf("JEDEC site size precludes use of this device\n");
} else { } else {
uptr->u5 |= RAM; /* RAM */ uptr->u5 |= RAM; /* RAM */
} }
} }
break; break;
default: default:
@ -335,7 +335,7 @@ t_stat JEDEC_set_size (UNIT *uptr, int32 val, char *cptr, void *desc)
printf("\tJEDEC_set_size: Error\n"); printf("\tJEDEC_set_size: Error\n");
return SCPE_ARG; return SCPE_ARG;
} }
if (JEDEC_buf[uptr->u6]) { /* any change requires a new buffer */ if (JEDEC_buf[uptr->u6]) { /* any change requires a new buffer */
free (JEDEC_buf[uptr->u6]); free (JEDEC_buf[uptr->u6]);
JEDEC_buf[uptr->u6] = NULL; JEDEC_buf[uptr->u6] = NULL;
} }

24
isys8010/common/iram16.c
View file

@ -36,10 +36,10 @@
#include "multibus_defs.h" #include "multibus_defs.h"
#define UNIT_V_RSIZE (UNIT_V_UF) /* RAM Size */ #define UNIT_V_RSIZE (UNIT_V_UF) /* RAM Size */
#define UNIT_RSIZE (0x1 << UNIT_V_RSIZE) #define UNIT_RSIZE (0x1 << UNIT_V_RSIZE)
#define UNIT_NONE (0) /* No unit */ #define UNIT_NONE (0) /* No unit */
#define UNIT_16K (1) /* 16KB */ #define UNIT_16K (1) /* 16KB */
/* function prototypes */ /* function prototypes */
@ -84,7 +84,7 @@ DEVICE RAM_dev = {
NULL, //deposit NULL, //deposit
&RAM_reset, //reset &RAM_reset, //reset
NULL, //boot NULL, //boot
NULL, //attach NULL, //attach
NULL, //detach NULL, //detach
NULL, //ctxt NULL, //ctxt
DEV_DEBUG, //flags DEV_DEBUG, //flags
@ -96,7 +96,7 @@ DEVICE RAM_dev = {
/* global variables */ /* global variables */
uint8 *RAM_buf = NULL; /* RAM buffer pointer */ uint8 *RAM_buf = NULL; /* RAM buffer pointer */
/* RAM functions */ /* RAM functions */
@ -111,16 +111,16 @@ t_stat RAM_set_size (UNIT *uptr, int32 val, char *cptr, void *desc)
printf("RAM_set_size: Size error\n"); printf("RAM_set_size: Size error\n");
return SCPE_ARG; return SCPE_ARG;
} }
RAM_unit.capac = 0x4000 * val; /* set size */ RAM_unit.capac = 0x4000 * val; /* set size */
RAM_unit.u3 = 0x0000; /* base is 0 */ RAM_unit.u3 = 0x0000; /* base is 0 */
RAM_unit.u4 = val; /* save val */ RAM_unit.u4 = val; /* save val */
if (RAM_buf) { /* if changed, allocate new buffer */ if (RAM_buf) { /* if changed, allocate new buffer */
free (RAM_buf); free (RAM_buf);
RAM_buf = NULL; RAM_buf = NULL;
} }
if (RAM_dev.dctrl & DEBUG_flow) if (RAM_dev.dctrl & DEBUG_flow)
printf("RAM_set_size: Done\n"); printf("RAM_set_size: Done\n");
return (RAM_reset (NULL)); /* force reset after reconfig */ return (RAM_reset (NULL)); /* force reset after reconfig */
} }
/* RAM reset */ /* RAM reset */
@ -132,7 +132,7 @@ t_stat RAM_reset (DEVICE *dptr)
if (RAM_dev.dctrl & DEBUG_flow) if (RAM_dev.dctrl & DEBUG_flow)
printf("RAM_reset: \n"); printf("RAM_reset: \n");
if (RAM_unit.capac == 0) { /* if undefined */ if (RAM_unit.capac == 0) { /* if undefined */
printf(" RAM: defaulted for 16KB\n"); printf(" RAM: defaulted for 16KB\n");
printf(" \"set RAM 16KB\"\n"); printf(" \"set RAM 16KB\"\n");
RAM_unit.capac = 0x4000; RAM_unit.capac = 0x4000;
@ -142,7 +142,7 @@ t_stat RAM_reset (DEVICE *dptr)
printf(" RAM: Initializing [%04X-%04XH]\n", printf(" RAM: Initializing [%04X-%04XH]\n",
RAM_unit.u3, RAM_unit.u3,
RAM_unit.u3 + RAM_unit.capac - 1); RAM_unit.u3 + RAM_unit.capac - 1);
if (RAM_buf == NULL) { /* no buffer allocated */ if (RAM_buf == NULL) { /* no buffer allocated */
RAM_buf = malloc(RAM_unit.capac); RAM_buf = malloc(RAM_unit.capac);
if (RAM_buf == NULL) { if (RAM_buf == NULL) {
if (RAM_dev.dctrl & DEBUG_flow) if (RAM_dev.dctrl & DEBUG_flow)

8
isys8010/common/mds-800.c
View file

@ -32,16 +32,16 @@
#include "system_defs.h" #include "system_defs.h"
/* set the base I/O address for the first 8255 */ /* set the base I/O address for the first 8255 */
#define I8255_BASE_0 0xE4 #define I8255_BASE_0 0xE4
/* set the base I/O address for the second 8255 */ /* set the base I/O address for the second 8255 */
#define I8255_BASE_1 0xE8 #define I8255_BASE_1 0xE8
/* set the base I/O address for the 8251 */ /* set the base I/O address for the 8251 */
#define I8251_BASE 0xEC #define I8251_BASE 0xEC
/* set the base and size for the EPROM on the iSBC 80/10 */ /* set the base and size for the EPROM on the iSBC 80/10 */
#define ROM_SIZE 0x1000 #define ROM_SIZE 0x1000
/* set the base and size for the RAM on the iSBC 80/10 */ /* set the base and size for the RAM on the iSBC 80/10 */
#define RAM_BASE 0x3C00 #define RAM_BASE 0x3C00