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I7000: Update register definitions for checking

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This commit is contained in:
Mark Pizzolato 2020-03-07 19:56:55 -08:00
parent f2435c91f4
commit 7ee3af8b9d
2 changed files with 20 additions and 20 deletions
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2
I7000/i7010_cpu.c
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@ -194,7 +194,7 @@ REG cpu_reg[] = {
{DRDATAD(G, caddr[2], 18, "Channel 2 address"), REG_FIT}, {DRDATAD(G, caddr[2], 18, "Channel 2 address"), REG_FIT},
{DRDATAD(H, caddr[3], 18, "Channel 3 address"), REG_FIT}, {DRDATAD(H, caddr[3], 18, "Channel 3 address"), REG_FIT},
{FLDATAD(ASTRISK, astmode, 1, "Asterix Mode"), REG_FIT}, {FLDATAD(ASTRISK, astmode, 1, "Asterix Mode"), REG_FIT},
{BRDATAD(SW, &SW, 2, 7, 1, "Sense Switch register"), REG_FIT}, {BINRDATAD(SW, SW, 7, "Sense Switch register"), REG_FIT},
{FLDATAD(SW1, SW, 0, "Sense Switch 0"), REG_FIT}, {FLDATAD(SW1, SW, 0, "Sense Switch 0"), REG_FIT},
{FLDATAD(SW2, SW, 1, "Sense Switch 1"), REG_FIT}, {FLDATAD(SW2, SW, 1, "Sense Switch 1"), REG_FIT},
{FLDATAD(SW3, SW, 2, "Sense Switch 2"), REG_FIT}, {FLDATAD(SW3, SW, 2, "Sense Switch 2"), REG_FIT},

38
I7000/i7080_cpu.c
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@ -246,25 +246,25 @@ UNIT cpu_unit =
REG cpu_reg[] = { REG cpu_reg[] = {
{DRDATAD(IC, IC, 32, "Instruction register")}, {DRDATAD(IC, IC, 32, "Instruction register")},
{BRDATAD(ADATA, &AC, 8, 8, sizeof(AC), "All Possible Register Data"), REG_HRO }, {SAVEDATA(ADATA, AC) },
{BRDATAD(A, &AC[0], 8, 8, 256, "A Register"), REG_VMIO|REG_CIRC }, {VBRDATAD(A, AC[0], 8, 8, 256, "A Register"), REG_VMIO|REG_CIRC },
{BRDATAD(B, &AC[256], 8, 8, 256, "B Register"), REG_VMIO|REG_CIRC }, {VBRDATAD(B, AC[256], 8, 8, 256, "B Register"), REG_VMIO|REG_CIRC },
{BRDATAD(ASU1, &AC[256], 8, 8, 16, "ASU1 Register"), REG_VMIO|REG_CIRC}, {VBRDATAD(ASU1, AC[256], 8, 8, 16, "ASU1 Register"), REG_VMIO|REG_CIRC},
{BRDATAD(ASU2, &AC[272], 8, 8, 16, "ASU2 Register"), REG_VMIO|REG_CIRC}, {VBRDATAD(ASU2, AC[272], 8, 8, 16, "ASU2 Register"), REG_VMIO|REG_CIRC},
{BRDATAD(ASU3, &AC[288], 8, 8, 16, "ASU3 Register"), REG_VMIO|REG_CIRC}, {VBRDATAD(ASU3, AC[288], 8, 8, 16, "ASU3 Register"), REG_VMIO|REG_CIRC},
{BRDATAD(ASU4, &AC[304], 8, 8, 16, "ASU4 Register"), REG_VMIO|REG_CIRC}, {VBRDATAD(ASU4, AC[304], 8, 8, 16, "ASU4 Register"), REG_VMIO|REG_CIRC},
{BRDATAD(ASU5, &AC[320], 8, 8, 16, "ASU5 Register"), REG_VMIO|REG_CIRC}, {VBRDATAD(ASU5, AC[320], 8, 8, 16, "ASU5 Register"), REG_VMIO|REG_CIRC},
{BRDATAD(ASU6, &AC[336], 8, 8, 16, "ASU6 Register"), REG_VMIO|REG_CIRC}, {VBRDATAD(ASU6, AC[336], 8, 8, 16, "ASU6 Register"), REG_VMIO|REG_CIRC},
{BRDATAD(ASU7, &AC[352], 8, 8, 16, "ASU7 Register"), REG_VMIO|REG_CIRC}, {VBRDATAD(ASU7, AC[352], 8, 8, 16, "ASU7 Register"), REG_VMIO|REG_CIRC},
{BRDATAD(ASU8, &AC[368], 8, 8, 16, "ASU8 Register"), REG_VMIO|REG_CIRC}, {VBRDATAD(ASU8, AC[368], 8, 8, 16, "ASU8 Register"), REG_VMIO|REG_CIRC},
{BRDATAD(ASU9, &AC[384], 8, 8, 16, "ASU9 Register"), REG_VMIO|REG_CIRC}, {VBRDATAD(ASU9, AC[384], 8, 8, 16, "ASU9 Register"), REG_VMIO|REG_CIRC},
{BRDATAD(ASU10, &AC[400], 8, 8, 16, "ASU10 Register"), REG_VMIO|REG_CIRC}, {VBRDATAD(ASU10, AC[400], 8, 8, 16, "ASU10 Register"), REG_VMIO|REG_CIRC},
{BRDATAD(ASU11, &AC[416], 8, 8, 16, "ASU11 Register"), REG_VMIO|REG_CIRC}, {VBRDATAD(ASU11, AC[416], 8, 8, 16, "ASU11 Register"), REG_VMIO|REG_CIRC},
{BRDATAD(ASU12, &AC[432], 8, 8, 16, "ASU12 Register"), REG_VMIO|REG_CIRC}, {VBRDATAD(ASU12, AC[432], 8, 8, 16, "ASU12 Register"), REG_VMIO|REG_CIRC},
{BRDATAD(ASU13, &AC[448], 8, 8, 16, "ASU13 Register"), REG_VMIO|REG_CIRC}, {VBRDATAD(ASU13, AC[448], 8, 8, 16, "ASU13 Register"), REG_VMIO|REG_CIRC},
{BRDATAD(ASU14, &AC[464], 8, 8, 16, "ASU14 Register"), REG_VMIO|REG_CIRC}, {VBRDATAD(ASU14, AC[464], 8, 8, 16, "ASU14 Register"), REG_VMIO|REG_CIRC},
{BRDATAD(ASU15, &AC[480], 8, 8, 32, "ASU15 Register"), REG_VMIO|REG_CIRC}, {VBRDATAD(ASU15, AC[480], 8, 8, 32, "ASU15 Register"), REG_VMIO|REG_CIRC},
{BRDATA(SW, &SW, 2, 6, 1), REG_FIT}, {BINRDATA(SW, SW, 6), REG_FIT},
{FLDATA(SW911, SW, 0), REG_FIT}, {FLDATA(SW911, SW, 0), REG_FIT},
{FLDATA(SW912, SW, 1), REG_FIT}, {FLDATA(SW912, SW, 1), REG_FIT},
{FLDATA(SW913, SW, 2), REG_FIT}, {FLDATA(SW913, SW, 2), REG_FIT},