ALTAIRZ80: Add "SET CPU HISTORY" and "SHOW CPU HISTORY" for 8080/Z80
This commit is contained in:
Patrick Linstruth
parent
7082e212ea
commit
807005553b
1 changed files with 197 additions and 1 deletions
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@ -41,6 +41,8 @@
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#define PCQ_MASK (PCQ_SIZE - 1)
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#define PCQ_MASK (PCQ_SIZE - 1)
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#define PCQ_ENTRY(PC) if (pcq[pcq_p] != (PC)) { pcq[pcq_p = (pcq_p - 1) & PCQ_MASK] = (PC); }
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#define PCQ_ENTRY(PC) if (pcq[pcq_p] != (PC)) { pcq[pcq_p = (pcq_p - 1) & PCQ_MASK] = (PC); }
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#define INST_MAX_BYTES 4 /* instruction max bytes */
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#define FLAG_C 1
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#define FLAG_C 1
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#define FLAG_N 2
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#define FLAG_N 2
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#define FLAG_P 4
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#define FLAG_P 4
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@ -50,6 +52,7 @@
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#define SETFLAG(f,c) AF = (c) ? AF | FLAG_ ## f : AF & ~FLAG_ ## f
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#define SETFLAG(f,c) AF = (c) ? AF | FLAG_ ## f : AF & ~FLAG_ ## f
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#define TSTFLAG(f) ((AF & FLAG_ ## f) != 0)
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#define TSTFLAG(f) ((AF & FLAG_ ## f) != 0)
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#define TSTFLAG2(a, f) ((a & FLAG_ ## f) != 0)
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#define LOW_DIGIT(x) ((x) & 0xf)
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#define LOW_DIGIT(x) ((x) & 0xf)
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#define HIGH_DIGIT(x) (((x) >> 4) & 0xf)
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#define HIGH_DIGIT(x) (((x) >> 4) & 0xf)
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@ -158,6 +161,8 @@ static t_stat cpu_set_ramtype (UNIT *uptr, int32 value, CONST char *cptr,
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static t_stat cpu_set_chiptype (UNIT *uptr, int32 value, CONST char *cptr, void *desc);
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static t_stat cpu_set_chiptype (UNIT *uptr, int32 value, CONST char *cptr, void *desc);
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static t_stat cpu_set_size (UNIT *uptr, int32 value, CONST char *cptr, void *desc);
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static t_stat cpu_set_size (UNIT *uptr, int32 value, CONST char *cptr, void *desc);
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static t_stat cpu_set_memory (UNIT *uptr, int32 value, CONST char *cptr, void *desc);
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static t_stat cpu_set_memory (UNIT *uptr, int32 value, CONST char *cptr, void *desc);
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static t_stat cpu_set_hist (UNIT *uptr, int32 val, CONST char *cptr, void *desc);
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static t_stat cpu_show_hist (FILE *st, UNIT *uptr, int32 val, CONST void *desc);
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static t_stat cpu_clear_command (UNIT *uptr, int32 value, CONST char *cptr, void *desc);
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static t_stat cpu_clear_command (UNIT *uptr, int32 value, CONST char *cptr, void *desc);
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static void cpu_clear(void);
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static void cpu_clear(void);
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static t_stat cpu_show (FILE *st, UNIT *uptr, int32 val, CONST void *desc);
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static t_stat cpu_show (FILE *st, UNIT *uptr, int32 val, CONST void *desc);
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@ -246,6 +251,30 @@ static uint16 pcq[PCQ_SIZE] = { 0 }; /* PC queue
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static int32 pcq_p = 0; /* PC queue ptr */
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static int32 pcq_p = 0; /* PC queue ptr */
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static REG *pcq_r = NULL; /* PC queue reg ptr */
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static REG *pcq_r = NULL; /* PC queue reg ptr */
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#define HIST_MIN 16
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#define HIST_MAX 8192
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typedef struct {
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uint8 valid;
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uint16 af;
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uint16 bc;
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uint16 de;
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uint16 hl;
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t_addr pc;
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t_addr sp;
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uint16 af1;
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uint16 bc1;
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uint16 de1;
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uint16 hl1;
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uint16 ix;
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uint16 iy;
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t_value op[INST_MAX_BYTES];
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} insthist_t;
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static uint32 hst_p = 0; /* history pointer */
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static uint32 hst_lnt = 0; /* history length */
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static insthist_t *hst = NULL; /* instruction history */
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uint32 m68k_registers[M68K_REG_CPU_TYPE + 1]; /* M68K CPU registers */
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uint32 m68k_registers[M68K_REG_CPU_TYPE + 1]; /* M68K CPU registers */
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@ -523,6 +552,8 @@ static MTAB cpu_mod[] = {
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NULL, NULL, "Sets the RAM size to 60KB for 8080 / Z80 / 8086" },
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NULL, NULL, "Sets the RAM size to 60KB for 8080 / Z80 / 8086" },
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{ MTAB_VDV, 64, NULL, "64KB", &cpu_set_size,
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{ MTAB_VDV, 64, NULL, "64KB", &cpu_set_size,
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NULL, NULL, "Sets the RAM size to 64KB for 8080 / Z80 / 8086" },
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NULL, NULL, "Sets the RAM size to 64KB for 8080 / Z80 / 8086" },
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{ MTAB_XTD|MTAB_VDV|MTAB_NMO|MTAB_VALO|MTAB_SHP, 0, "HISTORY", "HISTORY", &cpu_set_hist, &cpu_show_hist,
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NULL, "CPU instruction history buffer"},
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{ 0 }
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{ 0 }
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};
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};
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@ -2047,6 +2078,7 @@ static t_stat sim_instr_mmu (void) {
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extern int32 keyboardInterrupt;
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extern int32 keyboardInterrupt;
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extern uint32 keyboardInterruptHandler;
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extern uint32 keyboardInterruptHandler;
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int32 reason = SCPE_OK;
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int32 reason = SCPE_OK;
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int i;
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register uint32 specialProcessing;
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register uint32 specialProcessing;
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register uint32 AF;
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register uint32 AF;
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register uint32 BC;
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register uint32 BC;
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@ -6128,8 +6160,34 @@ static t_stat sim_instr_mmu (void) {
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PC = 0x38;
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PC = 0x38;
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}
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}
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sim_interval--;
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/*
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** Save in instruction history ring buffer?
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*/
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if (hst_lnt && ((chiptype == CHIP_TYPE_8080) || (chiptype == CHIP_TYPE_Z80))) {
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hst[hst_p].valid = 1;
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hst[hst_p].pc = PCX;
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hst[hst_p].sp = SP;
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hst[hst_p].af = AF;
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hst[hst_p].bc = BC;
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hst[hst_p].de = DE;
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hst[hst_p].hl = HL;
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hst[hst_p].af1 = AF1_S;
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hst[hst_p].bc1 = BC1_S;
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hst[hst_p].de1 = DE1_S;
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hst[hst_p].hl1 = HL1_S;
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hst[hst_p].ix = IX;
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hst[hst_p].iy = IY;
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for (i=0; i < INST_MAX_BYTES; i++) {
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hst[hst_p].op[i] = GetBYTE(PCX+i);
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}
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if (++hst_p == hst_lnt) {
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hst_p = 0;
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}
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}
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sim_interval--;
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}
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}
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/* It we stopped processing instructions because of a switch to the other
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/* It we stopped processing instructions because of a switch to the other
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@ -6794,6 +6852,144 @@ static t_stat cpu_set_memory(UNIT *uptr, int32 value, CONST char *cptr, void *de
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return SCPE_ARG;
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return SCPE_ARG;
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}
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}
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static t_stat cpu_set_hist(UNIT *uptr, int32 val, CONST char *cptr, void *desc) {
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uint32 i, lnt;
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t_stat r;
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if ((chiptype != CHIP_TYPE_8080) && (chiptype != CHIP_TYPE_Z80)) {
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sim_printf("History not supported for chiptype: %s\n",
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(chiptype < NUM_CHIP_TYPE) ? cpu_mod[chiptype].mstring : "????");
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return SCPE_NOFNC;
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}
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/*
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** If cptr is NULL, reset ring buffer ("SET HISTORY")
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*/
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if (cptr == NULL) {
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if (hst==NULL) {
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sim_printf("History buffer not enabled.\n");
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return SCPE_NOFNC;
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}
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for (i = 0; i < hst_lnt; i++) {
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hst[i].valid = 0;
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}
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hst_p = 0;
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return SCPE_OK;
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}
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/*
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** Enable/Resize ring buffer ("SET HISTORY=<n>")
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*/
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lnt = (uint32) get_uint (cptr, 10, HIST_MAX, &r);
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if ((r != SCPE_OK) || (lnt && (lnt < HIST_MIN))) {
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sim_printf("History buffer minimum/maximum size: %d/%d\n", HIST_MIN, HIST_MAX);
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return SCPE_ARG;
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}
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/*
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** Delete old history buffer
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*/
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if (hst!=NULL) {
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free (hst);
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hst_lnt = 0;
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hst = NULL;
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}
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hst_p = 0;
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/*
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** If a length was specified, allocate new buffer ("SET HISTORY=<n>" where n>0)
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*/
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if (lnt) {
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hst = (insthist_t *) calloc (lnt, sizeof (insthist_t));
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if (hst == NULL) {
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return SCPE_MEM;
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}
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hst_lnt = lnt;
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}
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return SCPE_OK;
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}
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t_stat cpu_show_hist (FILE *st, UNIT *uptr, int32 val, CONST void *desc)
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{
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int32 k, di, lnt;
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CONST char *cptr = (CONST char *) desc;
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t_stat r;
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insthist_t *h;
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if ((chiptype != CHIP_TYPE_8080) && (chiptype != CHIP_TYPE_Z80)) {
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sim_printf("History not supported for chiptype: %s\n",
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(chiptype < NUM_CHIP_TYPE) ? cpu_mod[chiptype].mstring : "????");
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return SCPE_NOFNC;
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}
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if (hst_lnt == 0) {
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return SCPE_NOFNC; /* enabled? */
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}
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if (cptr) {
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lnt = (int32) get_uint (cptr, 10, hst_lnt, &r);
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if ((r != SCPE_OK) || (lnt == 0)) {
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return SCPE_ARG;
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}
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}
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else {
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lnt = hst_lnt;
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}
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di = hst_p - lnt;
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if (di < 0) di = di + hst_lnt;
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for (k = 0; k < lnt; k++) {
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h = &hst[(di++) % hst_lnt];
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if (h->valid) { /* valid entry? */
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if (chiptype == CHIP_TYPE_8080) {
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/*
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** Use DDT output:
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** CfZfMfEfIf A=bb B=dddd D=dddd H=dddd S=dddd P=dddd inst
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*/
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fprintf(st, "CPU: C%dZ%dM%dE%dI%d A=%02X B=%04X D=%04X H=%04X S=%04X P=%04X ",
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TSTFLAG2(h->af, C),
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TSTFLAG2(h->af, Z),
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TSTFLAG2(h->af, S),
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TSTFLAG2(h->af, P),
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TSTFLAG2(h->af, H),
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HIGH_REGISTER(h->af), h->bc, h->de, h->hl, h->sp, h->pc);
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fprint_sym (st, h->pc, h->op, &cpu_unit, SWMASK ('M'));
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fprintf(st, "\n");
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}
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else { /* Z80 */
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/*
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** Use DDT/Z output:
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*/
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fprintf(st, "CPU: C%dZ%dS%dP%dH%dN%d A =%02X BC =%04X DE =%04X HL =%04X S =%04X P =%04X ",
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TSTFLAG2(h->af, C),
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TSTFLAG2(h->af, Z),
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TSTFLAG2(h->af, S),
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TSTFLAG2(h->af, P),
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TSTFLAG2(h->af, H),
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TSTFLAG2(h->af, N),
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HIGH_REGISTER(h->af), h->bc, h->de, h->hl, h->sp, h->pc);
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fprint_sym (st, h->pc, h->op, &cpu_unit, SWMASK ('M'));
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fprintf(st, "\n");
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fprintf(st, " A'=%02X BC'=%04X DE'=%04X HL'=%04X IX=%04X IY=%04X ",
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HIGH_REGISTER(h->af1), h->bc1, h->de1, h->hl1, h->ix, h->iy);
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fprintf(st, "\n");
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}
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}
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}
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return SCPE_OK;
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}
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t_value altairz80_pc_value (void) {
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t_value altairz80_pc_value (void) {
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return (t_value)PCX;
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return (t_value)PCX;
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}
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}
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