Fix VAX 8600 memory controller attribute descriptions to properly reflect the board size and slots.
Fixed value of 8600/8650 SID register ECO and PLANT fields. Added SHOW CPU MEMORY command to display memory board configuration
This commit is contained in:
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2f85000dbc
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8116b7571d
3 changed files with 106 additions and 21 deletions
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@ -88,6 +88,7 @@ struct boot_dev {
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uint32 nexus_req[NEXUS_HLVL]; /* nexus int req */
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uint32 nexus_req[NEXUS_HLVL]; /* nexus int req */
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uint32 pamloc = 0;
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uint32 pamloc = 0;
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uint32 pamm[1024]; /* Contents of physical memory space */
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uint32 cswp = 0;
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uint32 cswp = 0;
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uint32 ehsr = 0;
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uint32 ehsr = 0;
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uint32 mdctl = 0;
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uint32 mdctl = 0;
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@ -127,6 +128,7 @@ char *abus_description (DEVICE *dptr);
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t_stat vax860_boot (int32 flag, char *ptr);
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t_stat vax860_boot (int32 flag, char *ptr);
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t_stat vax860_boot_parse (int32 flag, char *ptr);
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t_stat vax860_boot_parse (int32 flag, char *ptr);
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t_stat cpu_boot (int32 unitno, DEVICE *dptr);
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t_stat cpu_boot (int32 unitno, DEVICE *dptr);
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void init_pamm (void);
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extern t_stat (*nexusR[NEXUS_NUM])(int32 *dat, int32 ad, int32 md);
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extern t_stat (*nexusR[NEXUS_NUM])(int32 *dat, int32 ad, int32 md);
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extern t_stat (*nexusW[NEXUS_NUM])(int32 dat, int32 ad, int32 md);
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extern t_stat (*nexusW[NEXUS_NUM])(int32 dat, int32 ad, int32 md);
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@ -170,6 +172,13 @@ extern t_stat sbi_wr (int32 pa, int32 val, int32 lnt);
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UNIT abus_unit = { UDATA (NULL, 0, 0) };
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UNIT abus_unit = { UDATA (NULL, 0, 0) };
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REG abus_reg[] = {
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REG abus_reg[] = {
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{ GRDATA (PAMLOC, pamloc, 16, 32, 0) },
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{ GRDATA (CSWP, cswp, 16, 32, 0) },
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{ GRDATA (EHSR, ehsr, 16, 32, 0) },
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{ GRDATA (MDCTL, mdctl, 16, 32, 0) },
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{ GRDATA (MODEL, sys_model, 16, 32, 0) },
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{ BRDATA (NEXUS_REQ, nexus_req, 16, 32, NEXUS_HLVL) },
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{ BRDATA (PAMM, pamm, 16, 32, 1024) },
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{ NULL }
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{ NULL }
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};
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};
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@ -182,6 +191,84 @@ DEVICE abus_dev = {
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&abus_description
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&abus_description
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};
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};
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/*
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The 8600/8650 systems can have a max to 260MB of memory.
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There are three different memory boards that exists: 4MB, 16MB, and 64MB.
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In addition, you can mix different boards.
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The rule is to put large boards first, and smaller boards later.
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The 16MB and 64MB boards are stacked and thus take up two backplane slots
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in the backplane, while the 4MB board only takes up one slot.
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There are 8 slots in the memory backplane. You start by putting boards in
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slot 0, going to slot 7. The boards taking up two slots actually use slot n,
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while covering slot n-1. That means that the board in slot 0 does not cover
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up any other slot.
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If you are using 16MB boards, the max memory is 68MB.
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Slot 0,2,4 and 6 will have 16MB boards. And then you can place a 4MB board in slot 7.
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Same story with the 64MB boards.
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*/
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void init_pamm()
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{
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int32 addr = 0;
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int32 mem = (int32)(MEMSIZE >> 20);
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int32 slot = 0;
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int32 size = 0;
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int32 i;
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for (i=0; i<1024; i++)
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pamm[i] = PAMM_NXM;
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for (;mem > 0; ) {
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if (mem >= 64)
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size = 64;
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else {
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if (mem >= 16)
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size = 16;
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else
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size = 4;
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}
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if ((size > 4) && (slot > 0))
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slot++;
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if (slot < 8) {
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for (i=0; i<size; i++)
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pamm[addr++] = slot;
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}
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slot++;
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mem -= size;
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}
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pamm[512] = PAMM_IOA0;
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}
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t_stat cpu_show_memory (FILE* st, UNIT* uptr, int32 val, void* desc)
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{
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int32 i, size, addr;
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int32 last_slot = pamm[0];
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for (i=size=addr=0; i<1024; i++) {
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if (last_slot != pamm[i]) {
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switch (last_slot) {
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case PAMM_NXM:
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break;
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case PAMM_IOA0:
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case PAMM_IOA1:
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case PAMM_IOA2:
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case PAMM_IOA3:
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fprintf (st, "I/O Adapter %d, %2dMB Board, Address: %08X\n", last_slot-PAMM_IOA0, size, addr);
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break;
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default:
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fprintf (st, "Slot:%2d - %2dMB Board, Address: %08X\n", last_slot, size, addr);
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break;
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}
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addr += (size << 20);
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size = 0;
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last_slot = pamm[i];
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}
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++size;
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}
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return SCPE_OK;
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}
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/* Special boot command, overrides regular boot */
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/* Special boot command, overrides regular boot */
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CTAB vax860_cmd[] = {
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CTAB vax860_cmd[] = {
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@ -345,21 +432,13 @@ switch (rg) {
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case MT_SID: /* SID */
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case MT_SID: /* SID */
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if (sys_model)
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if (sys_model)
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val = VAX860_SID | VAX865_TYP | VAX860_PLANT | VAX860_SN;
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val = VAX860_SID | VAX865_TYP | VAX860_ECO | VAX860_PLANT | VAX860_SN;
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else
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else
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val = VAX860_SID | VAX860_TYP | VAX860_PLANT | VAX860_SN;
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val = VAX860_SID | VAX860_TYP | VAX860_ECO | VAX860_PLANT | VAX860_SN;
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break;
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break;
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case MT_PAMACC: /* PAMACC */
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case MT_PAMACC: /* PAMACC */
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if (ADDR_IS_REG (pamloc))
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val = pamm[pamloc >> 20];
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val = PAMM_IOA0; /* SBIA */
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else if (ADDR_IS_MEM (pamloc)) {
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if (MEMSIZE < MAXMEMSIZE)
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val = (pamloc >> 23); /* 4MB Boards */
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else
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val = (pamloc >> 25); /* 16MB Boards */
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}
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else val = PAMM_NXM; /* NXM */
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val = val | (pamloc & PAMACC_ADDR);
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val = val | (pamloc & PAMACC_ADDR);
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break;
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break;
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@ -691,6 +770,7 @@ return SCPE_OK;
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t_stat abus_reset (DEVICE *dptr)
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t_stat abus_reset (DEVICE *dptr)
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{
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{
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sim_vm_cmd = vax860_cmd;
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sim_vm_cmd = vax860_cmd;
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init_pamm ();
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return SCPE_OK;
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return SCPE_OK;
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}
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}
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@ -85,8 +85,8 @@
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#define VAX860_SID (4 << 24) /* system ID */
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#define VAX860_SID (4 << 24) /* system ID */
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#define VAX860_TYP (0 << 23) /* sys type: 8600 */
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#define VAX860_TYP (0 << 23) /* sys type: 8600 */
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#define VAX865_TYP (1 << 23) /* sys type: 8650 */
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#define VAX865_TYP (1 << 23) /* sys type: 8650 */
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#define VAX860_ECO (7 << 19) /* ucode revision */
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#define VAX860_ECO (7 << 16) /* ucode revision */
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#define VAX860_PLANT (0 << 12) /* plant (Salem NH) */
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#define VAX860_PLANT (0 << 12) /* plant (say we're simh/undefined) */
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#define VAX860_SN (1234)
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#define VAX860_SN (1234)
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#define CON_HLTPIN 0x0200 /* external CPU halt */
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#define CON_HLTPIN 0x0200 /* external CPU halt */
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#define CON_HLTINS 0x0600 /* HALT instruction */
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#define CON_HLTINS 0x0600 /* HALT instruction */
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@ -183,14 +183,18 @@
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#define INITMEMSIZE (1 << MAXMEMWIDTH) /* initial memory size */
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#define INITMEMSIZE (1 << MAXMEMWIDTH) /* initial memory size */
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#define MEMSIZE (cpu_unit.capac)
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#define MEMSIZE (cpu_unit.capac)
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#define ADDR_IS_MEM(x) (((uint32) (x)) < MEMSIZE)
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#define ADDR_IS_MEM(x) (((uint32) (x)) < MEMSIZE)
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#define MEM_MODIFIERS { UNIT_MSIZE, (1u << 23), NULL, "8M", &cpu_set_size, NULL, NULL, "Set Memory to 8M bytes" }, \
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#define MEM_MODIFIERS { UNIT_MSIZE, (1u << 23), NULL, "8M", &cpu_set_size, NULL, NULL, "Set Memory to 8M bytes" }, \
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{ UNIT_MSIZE, (1u << 24), NULL, "16M", &cpu_set_size, NULL, NULL, "Set Memory to 16M bytes" }, \
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{ UNIT_MSIZE, (1u << 24), NULL, "16M", &cpu_set_size, NULL, NULL, "Set Memory to 16M bytes" }, \
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{ UNIT_MSIZE, (1u << 25), NULL, "32M", &cpu_set_size, NULL, NULL, "Set Memory to 32M bytes" }, \
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{ UNIT_MSIZE, (1u << 25), NULL, "32M", &cpu_set_size, NULL, NULL, "Set Memory to 32M bytes" }, \
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{ UNIT_MSIZE, (1u << 25) + (1u << 24), NULL, "48M", &cpu_set_size, NULL, NULL, "Set Memory to 48M bytes" }, \
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{ UNIT_MSIZE, (1u << 25) + (1u << 24), NULL, "48M", &cpu_set_size, NULL, NULL, "Set Memory to 48M bytes" }, \
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{ UNIT_MSIZE, (1u << 26), NULL, "64M", &cpu_set_size, NULL, NULL, "Set Memory to 64M bytes" }, \
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{ UNIT_MSIZE, (1u << 26), NULL, "64M", &cpu_set_size, NULL, NULL, "Set Memory to 64M bytes" }, \
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{ UNIT_MSIZE, (1u << 27), NULL, "128M", &cpu_set_size, NULL, NULL, "Set Memory to 128M bytes" }, \
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{ UNIT_MSIZE, (1u << 26) + (1u << 22), NULL, "68M", &cpu_set_size, NULL, NULL, "Set Memory to 68M bytes" }, \
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{ UNIT_MSIZE, (1u << 28), NULL, "256M", &cpu_set_size, NULL, NULL, "Set Memory to 256M bytes" }, \
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{ UNIT_MSIZE, (1u << 27), NULL, "128M", &cpu_set_size, NULL, NULL, "Set Memory to 128M bytes" }, \
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{ UNIT_MSIZE, (1u << 28) + (1u << 22), NULL, "260M", &cpu_set_size, NULL, NULL, "Set Memory to 260M bytes" }
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{ UNIT_MSIZE, (1u << 28), NULL, "256M", &cpu_set_size, NULL, NULL, "Set Memory to 256M bytes" }, \
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{ UNIT_MSIZE, (1u << 28) + (1u << 22), NULL, "260M", &cpu_set_size, NULL, NULL, "Set Memory to 260M bytes" }, \
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{ MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, "MEMORY", NULL, NULL, &cpu_show_memory, NULL, "Display memory configuration" }
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extern t_stat cpu_show_memory (FILE* st, UNIT* uptr, int32 val, void* desc);
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#define CPU_MODEL_MODIFIERS \
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#define CPU_MODEL_MODIFIERS \
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{ MTAB_XTD|MTAB_VDV, 0, "MODEL", "MODEL=8600|8650", \
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{ MTAB_XTD|MTAB_VDV, 0, "MODEL", "MODEL=8600|8650", \
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&cpu_set_model, &cpu_show_model, NULL, "Set/Display processor model" }
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&cpu_set_model, &cpu_show_model, NULL, "Set/Display processor model" }
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@ -3249,6 +3249,7 @@ for (i = 0; i < clim; i = i + 4)
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free (M);
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free (M);
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M = nM;
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M = nM;
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MEMSIZE = uval;
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MEMSIZE = uval;
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reset_all (0);
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return SCPE_OK;
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return SCPE_OK;
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}
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}
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