From 814ce9ea2a51c93310987f6dbf012ff8f8335b69 Mon Sep 17 00:00:00 2001 From: Seth Morabito Date: Wed, 26 Feb 2020 17:27:11 -0800 Subject: [PATCH] 3b2: Fix incorrect register width Several registers in the TIMERS device were described as being 16 bits wide, when they are in fact 8 bits wide. --- 3B2/3b2_sysdev.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/3B2/3b2_sysdev.c b/3B2/3b2_sysdev.c index eb2d9a7a..9f0a93e2 100644 --- a/3B2/3b2_sysdev.c +++ b/3B2/3b2_sysdev.c @@ -425,11 +425,11 @@ UNIT *timer_clk_unit = &timer_unit[1]; REG timer_reg[] = { { HRDATAD(DIVA, TIMERS[0].divider, 16, "Divider A") }, - { HRDATAD(STA, TIMERS[0].mode, 16, "Mode A") }, + { HRDATAD(STA, TIMERS[0].mode, 8, "Mode A") }, { HRDATAD(DIVB, TIMERS[1].divider, 16, "Divider B") }, - { HRDATAD(STB, TIMERS[1].mode, 16, "Mode B") }, + { HRDATAD(STB, TIMERS[1].mode, 8, "Mode B") }, { HRDATAD(DIVC, TIMERS[2].divider, 16, "Divider C") }, - { HRDATAD(STC, TIMERS[2].mode, 16, "Mode C") }, + { HRDATAD(STC, TIMERS[2].mode, 8, "Mode C") }, { NULL } };