diff --git a/.gitignore b/.gitignore index 4014582e..d958df61 100644 --- a/.gitignore +++ b/.gitignore @@ -1,3 +1,4 @@ +.git-commit-id #ignore thumbnails created by windows Thumbs.db #Ignore files built by Visual Studio @@ -41,3 +42,4 @@ ipch/ Visual Studio Projects/* + diff --git a/0readmeAsynchIO.txt b/0readmeAsynchIO.txt index b8fa50a6..f4113403 100644 --- a/0readmeAsynchIO.txt +++ b/0readmeAsynchIO.txt @@ -155,7 +155,10 @@ The pdp11_rq.c module has been refactored to leverage the asynch I/O features of the sim_disk library. The impact to this code to adopt the asynch I/O paradigm was quite minimal. The pdp11_rp.c module has also been refactored to leverage the asynch I/O -features of the sim_disk library. +features of the sim_disk library. The impact to this code to adopt the +asynch I/O paradigm was also quite minimal. After conversion a latent +bug in the VAX Massbus adapter implementation was illuminated due to the +more realistic delays to perform I/O operations. The pdp11_tq.c module has been refactored to leverage the asynch I/O features of the sim_tape library. The impact to this code to adopt the asynch I/O paradigm was very significant. This was due to the two facts: @@ -195,15 +198,8 @@ particular device emulation which isn't capable of asynch operation, or it can be defined globally on the compile command line for the simulator. Alternatively, if a specific Multiplexer device doesn't function correctly under the multiplexer asynchronous environment and it will never be -revised to operate correctly, it may set the TMUF_NOASYNCH bit in its -unit flags field. - -Console I/O can operate asynchronously if the simulator notifies the -tmxr/console subsystem which device unit is used by the simulator to poll -for console input. This is done by including sim_tmxr.h in the source -module which contains the console input device definition and calling -tmxr_set_console_input_unit(). tmxr_set_console_input_unit would usually -be called in a device reset routine. +revised to operate correctly, it may statically set the TMUF_NOASYNCH bit +in its unit flags field. Some devices will need a small amount of extra coding to leverage the Multiplexer Asynch I/O capabilties. Devices which require extra coding @@ -215,7 +211,17 @@ have one or more of the following characteristics: The extra coding required for proper operation is to call tmxr_set_line_unit() to associate the appropriate input polling unit to -the respective multiplexer line. +the respective multiplexer line (ONLY if input polling is done by a unit +different than the unit specified when the MUX was attached). If output +polling is done on a different unit, then tmxr_set_line_output_unit() +should be called to describe that fact. + +Console I/O can operate asynchronously if the simulator notifies the +tmxr/console subsystem which device unit is used by the simulator to poll +for console input and output units. This is done by including sim_tmxr.h +in the source module which contains the console input device definition +and calling tmxr_set_console_units(). tmxr_set_console_units would usually +be called in a device reset routine. sim_tmxr consumers: - Altair Z80 SIO devices = 1, units = 1, lines = 4, flagbits = 8, Untested Asynch @@ -288,7 +294,8 @@ happen under a combination of conditions: 2) the multiplexor device is NOT attached, and thus is not being managed by the asynchronous multiplexer support 3) the multiplexer device schedules polling (co-scheduled) when not - attached (such polling will never produce anything input). + attached (such polling will never produce any input, so this is probably + a bug). In prior simh versions support for clock co-scheduling was implmented separately by each simulator, and usually was expressed by code of the form: sim_activate (uptr, clk_cosched (tmxr_poll)); diff --git a/0readme_39.txt b/0readme_39.txt index e5b3509e..1dfc5fa6 100644 --- a/0readme_39.txt +++ b/0readme_39.txt @@ -34,25 +34,25 @@ components and build network capable simulators if they are available. 1.1.4 PDP11 and VAX (Mark Pizzolato) - - Added DELQA-Plus device. + - added DELQA-Plus device 1.1.5 IA64 VMS Ethernet Support - - Identified compiler version issues and added IA64 support (Matt Burke) + - identified compiler version issues and added IA64 support (Matt Burke) -1.1.6 Visual Studio Projects (Mark Pizzolato) 2. Bugs Fixed Please see the revision history on http://simh.trailing-edge.com or in the source module sim_rev.h. + 3. Status Report -This is the last release of SimH for which I will be sole editor. After this +This is the last release of SimH for which I will be lead editor. After this release, the source is moving to a public repository: - +https://github.com/markpizz/simh under the general editorship of Dave Hittner and Mark Pizzolato. The status of the individual simulators is as follows: @@ -113,7 +113,7 @@ Stable and working; runs available software. 3.13 IBM 1620 -Hand debug only. No software for it has been found or tested. +Hand debug only. No software for it has been found or tested. 3.14 IBM 7094 @@ -126,7 +126,7 @@ Stable and working, but not really supported. Runs available software. 3.16 IBM 1130 -Stable and working; runs available software. Supported and edited by +Stable and working; runs available software. Supported and edited by Brian Knittel. 3.17 HP 2100/1000 @@ -140,7 +140,7 @@ Stable and working; runs available software. 3.19 GRI-909/99 -Hand debug only. No software for it has been found or tested. +Hand debug only. No software for it has been found or tested. 3.20 SDS-940 @@ -168,10 +168,23 @@ Bill Beech 3.25 Sigma 32b Incomplete; more work is needed on the peripherals for accuracy. +Included in the beta simulators package. 3.26 Alpha -Incomplete; essentially just an EV-5 (21164) chip emulator. +Incomplete; essentially just an EV-5 (21164) chip emulator. Included +in the beta simulators package. + +3.27 SAGE + +Incomplete. Included in the beta simulators package. + +3.28 SC1 + +Internal simulator for SiCortex supercomputer; intended as an example +of implementing an SMP system in the current SimH structure. Included +in the beta simulators package. + 4. Suggestions for Future Work @@ -198,4 +211,3 @@ Incomplete; essentially just an EV-5 (21164) chip emulator. - Data General MV8000 (if a hobbyist license can be obtained for AOS) - Alpha simulator - HP 3000 (16b) simulator with MPE - diff --git a/0readme_ethernet.txt b/0readme_ethernet.txt index 841079e2..eaa2709f 100644 --- a/0readme_ethernet.txt +++ b/0readme_ethernet.txt @@ -156,9 +156,9 @@ Note 2: Root access will likely be needed to configure or start the vde Note 3: Simulators running using VDE networking can run without root privilege. -Linux (Ubuntu 10.04): +Linux (Ubuntu 11.10): apt-get install make - apt-get install libvdeplug-dev + apt-get install libvdeplug2-dev apt-get install vde2 vde_switch -s /tmp/switch1 -tap tap0 -m 666 @@ -207,7 +207,7 @@ Building on Windows: The contents of the windows-build directory can be downloaded from: - https://github.com/downloads/markpizz/simh/windows-build.zip + https://github.com/downloads/simh/simh/windows-build.zip There are Windows batch files provided to initiate compiles using the MinGW diff --git a/ALTAIR/altair_cpu.c b/ALTAIR/altair_cpu.c index 196893c4..74a62635 100644 --- a/ALTAIR/altair_cpu.c +++ b/ALTAIR/altair_cpu.c @@ -107,9 +107,6 @@ int32 chip = 0; /* 0 = 8080 chip, 1 = z8 int32 PCX; /* External view of PC */ -extern int32 sim_int_char; -extern uint32 sim_brk_types, sim_brk_dflt, sim_brk_summ;/* breakpoint info */ - /* function prototypes */ t_stat cpu_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw); @@ -300,9 +297,8 @@ DEVICE cpu_dev = { NULL, NULL, NULL }; -int32 sim_instr (void) +t_stat sim_instr (void) { - extern int32 sim_interval; int32 PC, IR, OP, DAR, reason, hi, lo, carry, i; PC = saved_PC & ADDRMASK; /* load local PC */ @@ -366,7 +362,7 @@ int32 sim_instr (void) if ((OP & 0xCF) == 0x01) { /* LXI */ DAR = M[PC] & 0x00ff; PC++; - DAR = DAR | (M[PC] <<8) & 0xFF00;; + DAR = DAR | ((M[PC] <<8) & 0xFF00); putpair((OP >> 4) & 0x03, DAR); PC++; continue; diff --git a/ALTAIR/altair_sys.c b/ALTAIR/altair_sys.c index fa32695a..0453f8f7 100644 --- a/ALTAIR/altair_sys.c +++ b/ALTAIR/altair_sys.c @@ -153,7 +153,7 @@ int32 oplen[256] = { load starts at the current value of the PC. */ -int32 sim_load (FILE *fileref, char *cptr, char *fnam, int flag) +t_stat sim_load (FILE *fileref, char *cptr, char *fnam, int flag) { int32 i, addr = 0, cnt = 0; @@ -180,7 +180,7 @@ return (SCPE_OK); status = error code */ -int32 fprint_sym (FILE *of, int32 addr, uint32 *val, +t_stat fprint_sym (FILE *of, t_addr addr, t_value *val, UNIT *uptr, int32 sw) { int32 cflag, c1, c2, inst, adr; @@ -229,7 +229,7 @@ return -(oplen[inst] - 1); status = error status */ -int32 parse_sym (char *cptr, int32 addr, UNIT *uptr, uint32 *val, int32 sw) +t_stat parse_sym (char *cptr, t_addr addr, UNIT *uptr, t_value *val, int32 sw) { int32 cflag, i = 0, j, r; char gbuf[CBUFSIZE]; diff --git a/AltairZ80/altairz80_cpu.c b/AltairZ80/altairz80_cpu.c index e645b7c3..dc4c0d46 100644 --- a/AltairZ80/altairz80_cpu.c +++ b/AltairZ80/altairz80_cpu.c @@ -128,7 +128,6 @@ } \ } -extern int32 sim_int_char; extern int32 sio0s (const int32 port, const int32 io, const int32 data); extern int32 sio0d (const int32 port, const int32 io, const int32 data); extern int32 sio1s (const int32 port, const int32 io, const int32 data); @@ -147,8 +146,6 @@ extern void do_SIMH_sleep(void); extern void prepareMemoryAccessMessage(const t_addr loc); extern void prepareInstructionMessage(const t_addr loc, const uint32 op); -extern FILE *sim_deb; - extern t_stat sim_instr_nommu(void); extern uint8 MOPT[MAXBANKSIZE]; extern t_stat sim_instr_8086(void); @@ -194,7 +191,6 @@ void setBankSelect(const int32 b); uint32 getClockFrequency(void); void setClockFrequency(const uint32 Value); uint32 getCommon(void); -t_stat sim_load(FILE *fileref, char *cptr, char *fnam, int32 flag); uint32 sim_map_resource(uint32 baseaddr, uint32 size, uint32 resource_type, int32 (*routine)(const int32, const int32, const int32), uint8 unmap); @@ -1882,15 +1878,12 @@ void setClockFrequency(const uint32 Value) { } static t_stat sim_instr_mmu (void) { - extern int32 sim_interval; extern t_bool sim_brk_pend[SIM_BKPT_N_SPC]; extern int32 timerInterrupt; extern int32 timerInterruptHandler; extern int32 keyboardInterrupt; extern uint32 keyboardInterruptHandler; - extern uint32 sim_os_msec(void); extern const t_bool rtc_avail; - extern uint32 sim_brk_summ; int32 reason = SCPE_OK; register uint32 specialProcessing; register uint32 AF; @@ -6287,7 +6280,6 @@ static t_stat sim_instr_mmu (void) { /* reset routine */ static t_stat cpu_reset(DEVICE *dptr) { - extern uint32 sim_brk_types, sim_brk_dflt; /* breakpoint info */ int32 i; AF_S = AF1_S = 0; BC_S = DE_S = HL_S = 0; @@ -6817,7 +6809,7 @@ void (*sim_vm_init) (void) = &altairz80_init; #define PLURAL(x) (x), (x) == 1 ? "" : "s" -t_stat sim_load(FILE *fileref, char *cptr, char *fnam, int32 flag) { +t_stat sim_load(FILE *fileref, char *cptr, char *fnam, int flag) { int32 i; uint32 addr, cnt = 0, org, pagesModified = 0, makeROM = FALSE; t_addr j, lo, hi; diff --git a/AltairZ80/altairz80_cpu_nommu.c b/AltairZ80/altairz80_cpu_nommu.c index a390ca4b..552ac1d9 100644 --- a/AltairZ80/altairz80_cpu_nommu.c +++ b/AltairZ80/altairz80_cpu_nommu.c @@ -985,8 +985,6 @@ static uint16 GET_WORD(register uint32 a) { INOUTFLAGS((HIGH_REGISTER(BC) & 0xa8) | ((HIGH_REGISTER(BC) == 0) << 6), x) t_stat sim_instr_nommu(void) { - extern int32 sim_interval; - extern uint32 sim_brk_summ; int32 reason = SCPE_OK; register uint32 AF; register uint32 BC; diff --git a/AltairZ80/altairz80_net.c b/AltairZ80/altairz80_net.c index fa5e5103..f6d71ffe 100644 --- a/AltairZ80/altairz80_net.c +++ b/AltairZ80/altairz80_net.c @@ -150,36 +150,33 @@ static t_stat net_reset(DEVICE *dptr) { } static t_stat net_attach(UNIT *uptr, char *cptr) { - uint32 i, ipa, ipp; - t_stat r = get_ipaddr(cptr, &ipa, &ipp); + uint32 i; + char host[CBUFSIZE], port[CBUFSIZE]; + t_stat r; + + r = sim_parse_addr (cptr, host, sizeof(host), "localhost", port, sizeof(port), "3000", NULL); if (r != SCPE_OK) return SCPE_ARG; - if (ipa == 0) - ipa = 0x7F000001; /* localhost = 127.0.0.1 */ - if (ipp == 0) - ipp = 3000; - net_unit.u3 = ipp; - net_unit.u4 = ipa; net_reset(&net_dev); for (i = 0; i <= MAX_CONNECTIONS; i++) serviceDescriptor[i].ioSocket = 0; if (net_unit.flags & UNIT_SERVER) { net_unit.wait = NET_INIT_POLL_SERVER; - serviceDescriptor[1].masterSocket = sim_master_sock(ipp); + serviceDescriptor[1].masterSocket = sim_master_sock(cptr, NULL); if (serviceDescriptor[1].masterSocket == INVALID_SOCKET) return SCPE_IOERR; } else { net_unit.wait = NET_INIT_POLL_CLIENT; - serviceDescriptor[0].ioSocket = sim_connect_sock(ipa, ipp); + serviceDescriptor[0].ioSocket = sim_connect_sock(cptr, "localhost", "3000"); if (serviceDescriptor[0].ioSocket == INVALID_SOCKET) return SCPE_IOERR; } net_unit.flags |= UNIT_ATT; - net_unit.filename = (char *) calloc(CBUFSIZE, sizeof (char)); /* alloc name buf */ + net_unit.filename = (char *) calloc(1, strlen(cptr)+1); /* alloc name buf */ if (net_unit.filename == NULL) return SCPE_MEM; - strncpy(net_unit.filename, cptr, CBUFSIZE); /* save name */ + strcpy(net_unit.filename, cptr); /* save name */ return SCPE_OK; } @@ -216,7 +213,7 @@ static t_stat net_svc(UNIT *uptr) { } } else if (serviceDescriptor[0].ioSocket == 0) { - serviceDescriptor[0].ioSocket = sim_connect_sock(net_unit.u4, net_unit.u3); + serviceDescriptor[0].ioSocket = sim_connect_sock(net_unit.filename, "localhost", "3000"); if (serviceDescriptor[0].ioSocket == INVALID_SOCKET) return SCPE_IOERR; printf("\rWaiting for server ... Type g (possibly twice) when ready" NLP); diff --git a/AltairZ80/altairz80_sio.c b/AltairZ80/altairz80_sio.c index fb76b774..10283178 100644 --- a/AltairZ80/altairz80_sio.c +++ b/AltairZ80/altairz80_sio.c @@ -166,12 +166,9 @@ extern void setClockFrequency(const uint32 Value); extern int32 chiptype; extern const t_bool rtc_avail; extern uint32 PCX; -extern int32 sim_switches; -extern int32 sim_quiet; extern int32 SR; extern UNIT cpu_unit; extern volatile int32 stop_cpu; -extern int32 sim_interval; /* Debug Flags */ static DEBTAB generic_dt[] = { @@ -324,7 +321,7 @@ DEVICE sio_dev = { 1, 10, 31, 1, 8, 8, NULL, NULL, &sio_reset, NULL, &sio_attach, &sio_detach, - NULL, DEV_DEBUG, 0, + NULL, DEV_DEBUG | DEV_MUX, 0, generic_dt, NULL, "Serial Input Output SIO" }; diff --git a/AltairZ80/i86_decode.c b/AltairZ80/i86_decode.c index 2b15e27f..afa7c2d0 100644 --- a/AltairZ80/i86_decode.c +++ b/AltairZ80/i86_decode.c @@ -41,9 +41,7 @@ extern int32 SPX_S; /* SP register (8086) */ extern int32 IP_S; /* IP register (8086) */ extern int32 FLAGS_S; /* flags register (8086) */ extern int32 PCX_S; /* PC register (8086), 20 bit */ -extern int32 sim_interval; extern uint32 PCX; /* external view of PC */ -extern uint32 sim_brk_summ; extern UNIT cpu_unit; void i86_intr_raise(PC_ENV *m,uint8 intrnum); diff --git a/GRI/gri_cpu.c b/GRI/gri_cpu.c index e173f306..ca08fc59 100644 --- a/GRI/gri_cpu.c +++ b/GRI/gri_cpu.c @@ -187,10 +187,6 @@ int16 scq[SCQ_SIZE] = { 0 }; /* PC queue */ int32 scq_p = 0; /* PC queue ptr */ REG *scq_r = NULL; /* PC queue reg ptr */ -extern int32 sim_interval; -extern int32 sim_int_char; -extern uint32 sim_brk_types, sim_brk_dflt, sim_brk_summ; /* breakpoint info */ - t_stat cpu_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw); t_stat cpu_dep (t_value val, t_addr addr, UNIT *uptr, int32 sw); t_stat cpu_reset (DEVICE *dptr); diff --git a/GRI/gri_stddev.c b/GRI/gri_stddev.c index 53a3b13d..c07cacdc 100644 --- a/GRI/gri_stddev.c +++ b/GRI/gri_stddev.c @@ -39,6 +39,7 @@ */ #include "gri_defs.h" +#include "sim_tmxr.h" #include uint32 hsr_stopioe = 1, hsp_stopioe = 1; @@ -277,6 +278,7 @@ return SCPE_OK; t_stat tti_reset (DEVICE *dptr) { +tmxr_set_console_units (&tti_unit, &tto_unit); tti_unit.buf = 0; /* clear buffer */ dev_done = dev_done & ~INT_TTI; /* clear ready */ sim_activate (&tti_unit, tti_unit.wait); /* activate unit */ diff --git a/GRI/gri_sys.c b/GRI/gri_sys.c index 42e793d2..c20ab10b 100644 --- a/GRI/gri_sys.c +++ b/GRI/gri_sys.c @@ -37,7 +37,6 @@ extern DEVICE hsr_dev, hsp_dev; extern DEVICE rtc_dev; extern REG cpu_reg[]; extern uint16 M[]; -extern int32 sim_switches; void fprint_addr (FILE *of, uint32 val, uint32 mod, uint32 dst); diff --git a/H316/h316_cpu.c b/H316/h316_cpu.c index d09a0654..52110867 100644 --- a/H316/h316_cpu.c +++ b/H316/h316_cpu.c @@ -276,12 +276,6 @@ int32 hst_p = 0; /* history pointer */ int32 hst_lnt = 0; /* history length */ InstHistory *hst = NULL; /* instruction history */ -extern int32 sim_int_char; -extern int32 sim_interval; -extern uint32 sim_brk_types, sim_brk_dflt, sim_brk_summ; /* breakpoint info */ -extern FILE *sim_log; -extern DEVICE *sim_devices[]; - t_bool devtab_init (void); int32 dmaio (int32 inst, int32 fnc, int32 dat, int32 dev); int32 undio (int32 inst, int32 fnc, int32 dat, int32 dev); @@ -296,9 +290,6 @@ t_stat cpu_show_dma (FILE *st, UNIT *uptr, int32 val, void *desc); t_stat cpu_set_nchan (UNIT *uptr, int32 val, char *cptr, void *desc); t_stat cpu_show_nchan (FILE *st, UNIT *uptr, int32 val, void *desc); -extern t_stat fprint_sym (FILE *of, t_addr addr, t_value *val, - UNIT *uptr, int32 sw); - /* CPU data structures cpu_dev CPU device descriptor @@ -1592,8 +1583,6 @@ char *cptr = (char *) desc; t_value sim_eval; t_stat r; InstHistory *h; -extern t_stat fprint_sym (FILE *ofile, t_addr addr, t_value *val, - UNIT *uptr, int32 sw); static uint8 has_opnd[16] = { 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1 }; diff --git a/H316/h316_dp.c b/H316/h316_dp.c index 533c3a86..056a9b1f 100644 --- a/H316/h316_dp.c +++ b/H316/h316_dp.c @@ -220,7 +220,6 @@ extern int32 dev_int, dev_enb; extern uint32 chan_req; extern int32 stop_inst; extern uint32 dma_ad[DMA_MAX]; -extern int32 sim_switches; uint32 dp_cw1 = 0; /* cmd word 1 */ uint32 dp_cw2 = 0; /* cmd word 2 */ diff --git a/H316/h316_stddev.c b/H316/h316_stddev.c index beb3585c..32005811 100644 --- a/H316/h316_stddev.c +++ b/H316/h316_stddev.c @@ -68,6 +68,7 @@ */ #include "h316_defs.h" +#include "sim_tmxr.h" #include #define UNIT_V_ASC (TTUF_V_UF + 0) /* ASCII */ @@ -88,7 +89,6 @@ extern int32 PC; extern int32 stop_inst; extern int32 C, dp, ext, extoff_pending, sc; extern int32 dev_int, dev_enb; -extern int32 sim_switches; extern UNIT cpu_unit; uint32 ptr_motion = 0; /* read motion */ @@ -534,6 +534,7 @@ return SCPE_OK; t_stat ptp_reset (DEVICE *dptr) { +tmxr_set_console_units (&tty_unit[TTR], &tty_unit[TTO]); CLR_INT (INT_PTP); /* clear ready, enb */ CLR_ENB (INT_PTP); ptp_power = 0; /* power off */ diff --git a/H316/h316_sys.c b/H316/h316_sys.c index c9b6e54e..905c8470 100644 --- a/H316/h316_sys.c +++ b/H316/h316_sys.c @@ -43,7 +43,6 @@ extern DEVICE fhd_dev; extern DEVICE mt_dev; extern REG cpu_reg[]; extern uint16 M[]; -extern int32 sim_switches; /* SCP data structures and interface routines diff --git a/HP2100/hp2100_baci.c b/HP2100/hp2100_baci.c index 878a6eff..ef2f6392 100644 --- a/HP2100/hp2100_baci.c +++ b/HP2100/hp2100_baci.c @@ -26,6 +26,7 @@ BACI 12966A BACI card 10-Feb-12 JDB Deprecated DEVNO in favor of SC + Removed DEV_NET to allow restoration of listening port 28-Mar-11 JDB Tidied up signal handling 26-Oct-10 JDB Changed I/O signal handler for revised signal model 25-Nov-08 JDB Revised for new multiplexer library SHOW routines @@ -502,11 +503,14 @@ DEVICE baci_dev = { &baci_attach, /* attach routine */ &baci_detach, /* detach routine */ &baci_dib, /* device information block */ - DEV_DEBUG | DEV_DISABLE, /* device flags */ + DEV_DEBUG | DEV_DISABLE | DEV_MUX, /* device flags */ 0, /* debug control flags */ baci_deb, /* debug flag name table */ NULL, /* memory size change routine */ - NULL }; /* logical device name */ + NULL, /* logical device name */ + NULL, /* help routine */ + NULL, /* help attach routine*/ + (void*)&baci_desc }; /* help context */ /* I/O signal handler. @@ -1157,11 +1161,11 @@ if (baci_edsiw & (baci_status ^ baci_dsrw) & IN_MODEM) /* device interrupt? */ baci_status = baci_status | IN_DEVINT; /* set flag */ if ((baci_status & IN_STDIRQ) || /* standard interrupt? */ - (!(baci_icw & OUT_DCPC) && /* or under program control */ - (baci_status & IN_FIFOIRQ)) || /* and FIFO interrupt? */ - ((IO_MODE == RECV) && /* or receiving */ + !(baci_icw & OUT_DCPC) && /* or under program control */ + (baci_status & IN_FIFOIRQ) || /* and FIFO interrupt? */ + (IO_MODE == RECV) && /* or receiving */ (baci_edsiw & OUT_ENCM) && /* and char mode */ - (baci_fget != baci_fput))) { /* and FIFO not empty? */ + (baci_fget != baci_fput)) { /* and FIFO not empty? */ if (baci.lockout) { /* interrupt lockout? */ if (DEBUG_PRI (baci_dev, DEB_CMDS)) @@ -1185,8 +1189,8 @@ if ((baci_status & IN_STDIRQ) || /* standard interrupt? * } if ((baci_icw & OUT_DCPC) && /* DCPC enabled? */ - (((IO_MODE == XMIT) && (baci_fcount < 128)) || /* and xmit and room in FIFO */ - ((IO_MODE == RECV) && (baci_fcount > 0)))) { /* or recv and data in FIFO? */ + ((IO_MODE == XMIT) && (baci_fcount < 128) || /* and xmit and room in FIFO */ + (IO_MODE == RECV) && (baci_fcount > 0))) { /* or recv and data in FIFO? */ if (baci.lockout) { /* interrupt lockout? */ if (DEBUG_PRI (baci_dev, DEB_CMDS)) @@ -1472,9 +1476,9 @@ if (baci_uart_clk > 0) { /* transfer in progress? if ((IO_MODE == XMIT) && /* transmit mode? */ ((baci_uart_clk == 0) || /* and end of character? */ - ((baci_uart_clk == 8) && /* or last stop bit */ - (baci_cfcw & OUT_STBITS) && /* and extra stop bit requested */ - ((baci_cfcw & OUT_CHARSIZE) == 0)))) { /* and 1.5 stop bits used? */ + (baci_uart_clk == 8) && /* or last stop bit */ + (baci_cfcw & OUT_STBITS) && /* and extra stop bit requested */ + ((baci_cfcw & OUT_CHARSIZE) == 0))) { /* and 1.5 stop bits used? */ baci_uart_clk = 0; /* clear clock count */ diff --git a/HP2100/hp2100_bugfixes.txt b/HP2100/hp2100_bugfixes.txt index 80793696..040e3b58 100644 --- a/HP2100/hp2100_bugfixes.txt +++ b/HP2100/hp2100_bugfixes.txt @@ -1,6 +1,6 @@ HP 2100 SIMULATOR BUG FIX WRITEUPS ================================== - Last update: 2012-03-25 + Last update: 2012-12-28 1. PROBLEM: Booting from magnetic tape reports "HALT instruction, P: 77756 @@ -6280,3 +6280,114 @@ (hp2100_mt.c). STATUS: Fixed in version 3.9-0. + + + +247. PROBLEM: The ICD disc read end-of-track delay is not optimal. + + VERSION: 3.9-0 + + OBSERVATION: To avoid End of Cylinder errors when reading the last sector + of a track, the ICD controller must delay more than the usual intersector + time to allow the OS driver to send an Untalk if a read is to be + terminated. Currently, the longer delay is used if an end-of-cylinder + condition is present. However, the delay is needed only if the resulting + seek attempt would cause an error if the read is continued; the normal + delay should be used if the seek is permitted and would succeed. + + Also, if the host does send an Untalk during this time, the longer delay + should be cancelled, and command termination should be scheduled for + immediate processing. + + CAUSE: Suboptimal implementation. + + RESOLUTION: Modify "end_read" (hp_disclib.c) to use the longer time only + if the seek would fail, and modify "complete_read" (hp2100_di_da.c) to + cancel the intersector delay and schedule the completion phase immediately. + + STATUS: Fixed in version 4.0-0. + + + +248. PROBLEM: Calling a VMA routine from a non-VMA program does not MP abort. + + VERSION: 3.9-0 + + OBSERVATION: If a virtual memory routine, such as .LBP, is called from a + non-VMA program, it should be aborted with a memory protect error. + Instead, a dynamic mapping error occurs instead: + + ASMB,R + NAM MAPPR + EXT EXEC,.LBP + START CLA + CLB + JSB .LBP + NOP + JSB EXEC + DEF *+2 + DEF *+1 + DEC 6 + END START + + DM VIOL = 160377 + DM INST = 105257 + ABE 0 0 0 + XYO 0 0 0 + DM MAPPR 2014 + MAPPR ABORTED + + CAUSE: The page mapping routine, "cpu_vma_mapte", returns TRUE if the page + table is set up and valid and FALSE if not. If a program is not a VMA + program, then it has no page table, but "cpu_vma_mapte" is returning TRUE + erroneously. That results in a DM error when the invalid page entry is + used. + + The microcode explicitly tests for a non-VMA program, i.e., one with no ID + extension, and generates an MP error in this case. + + RESOLUTION: Modify "cpu_vma_mapte" (hp2100_cpu5.c) to return FALSE if + called for a non-VMA program. + + STATUS: Fixed in version 4.0-0. + + + +249. PROBLEM: RESTORing a previously SAVEd session fails if the 12792C + multiplexer is attached. + + VERSION: 3.9-0 + + OBSERVATION: If the MPX device has a listening port attached when a + session is saved, attempting to restore that session results in a "Unit not + attachable" error. + + CAUSE: The MPX attach routine only allows attachment to unit 0, i.e., + ATTACH MPX , but the actual attachment is made to the Telnet poll + unit (unit 9). As SAVE finds the port attached to unit 9, RESTORE attempts + to reattach it to unit 9. + + RESOLUTION: Modify "mpx_attach" (hp2100_mpx.c) to allow attachment to unit + 9 only during a RESTORE. + + STATUS: Fixed in version 4.0-0. + + + +250. PROBLEM: DEASSIGNing the TBG device generates a debug warning. + + VERSION: 3.9-0 + + OBSERVATION: When running the simulator under a debugger, entering the + command DEASSIGN TBG prints "warning: Invalid Address specified to + RtlFreeHeap." + + CAUSE: The TBG logical name is specified statically in the DEVICE + structure, but "deassign_device" calls "free" on the pointer. The + developer's manual does not state that the logical name must be dynamically + allocated, but deassigning assumes that it was. + + RESOLUTION: Modify "clk_reset" (hp2100_stddev.c) to allocate the logical + name during a power-on reset. + + STATUS: Fixed in version 4.0-0. diff --git a/HP2100/hp2100_cpu.c b/HP2100/hp2100_cpu.c index 5fba8699..d40c1ad2 100644 --- a/HP2100/hp2100_cpu.c +++ b/HP2100/hp2100_cpu.c @@ -29,6 +29,7 @@ DMA1,DMA2 12607B/12578A/12895A direct memory access controller DCPC1,DCPC2 12897B dual channel port controller + 09-May-12 JDB Separated assignments from conditional expressions 13-Jan-12 JDB Minor speedup in "is_mapped" Added casts to cpu_mod, dmasio, dmapio, cpu_reset, dma_reset 07-Apr-11 JDB Fixed I/O return status bug for DMA cycles @@ -560,14 +561,7 @@ uint16 dms_map[MAP_NUM * MAP_LNT] = { 0 }; /* dms maps */ /* External data */ -extern int32 sim_interval; -extern int32 sim_int_char; -extern int32 sim_brk_char; -extern int32 sim_del_char; -extern uint32 sim_brk_types, sim_brk_dflt, sim_brk_summ; /* breakpoint info */ -extern DEVICE *sim_devices[]; extern char halt_msg[]; -extern t_bool sim_idle_enab; extern DIB clk_dib; /* CLK DIB for idle check */ /* CPU local routines */ @@ -1054,7 +1048,8 @@ for (i = OPTDEV; i <= MAXDEV; i++) /* default optional devi dtab [PWR] = &pwrf_dib; /* for now, powerfail is always present */ -for (i = 0; (dptr = sim_devices [i]); i++) { /* loop thru dev */ +for (i = 0; sim_devices [i] != NULL; i++) { /* loop thru dev */ + dptr = sim_devices [i]; dibptr = (DIB *) dptr->ctxt; /* get DIB */ if (dibptr && !(dptr->flags & DEV_DIS)) { /* handler exists and device is enabled? */ @@ -1464,17 +1459,17 @@ while (reason == SCPE_OK) { /* loop until halted */ */ if ((sim_idle_enab) && (intrq == 0)) /* idle enabled w/o pending irq? */ - if ((((PC == err_PC) || /* RTE through RTE-IVB */ - ((PC == (err_PC - 1)) && /* RTE-6/VM */ - ((ReadW (PC) & I_MRG) == I_ISZ))) && /* RTE jump target */ - (mp_fence == CLEAR) && (M [xeqt] == 0) && /* RTE idle indications */ - (M [tbg] == clk_dib.select_code)) || /* RTE verification */ + if (((PC == err_PC) || /* RTE through RTE-IVB */ + ((PC == (err_PC - 1)) && /* RTE-6/VM */ + ((ReadW (PC) & I_MRG) == I_ISZ))) && /* RTE jump target */ + (mp_fence == CLEAR) && (M [xeqt] == 0) && /* RTE idle indications */ + (M [tbg] == clk_dib.select_code) || /* RTE verification */ - ((PC == (err_PC - 3)) && /* DOS through DOS-III */ - (ReadW (PC) == I_STF) && /* DOS jump target */ - (AR == 0177777) && (BR == 0177777) && /* DOS idle indication */ - (M [m64] == 0177700) && /* DOS verification */ - (M [p64] == 0000100))) /* DOS verification */ + (PC == (err_PC - 3)) && /* DOS through DOS-III */ + (ReadW (PC) == I_STF) && /* DOS jump target */ + (AR == 0177777) && (BR == 0177777) && /* DOS idle indication */ + (M [m64] == 0177700) && /* DOS verification */ + (M [p64] == 0000100)) /* DOS verification */ sim_idle (TMR_POLL, FALSE); /* idle the simulator */ break; @@ -3351,7 +3346,7 @@ t_stat status; uint32 ioresult; IOCYCLE signals; -if ((bytes && !even) || (dma [ch].cw3 != DMASK)) { /* normal cycle? */ +if (bytes && !even || dma [ch].cw3 != DMASK) { /* normal cycle? */ if (input) /* input cycle? */ signals = ioIOI | ioCLF; /* assert IOI and CLF */ else /* output cycle */ @@ -3609,30 +3604,32 @@ DEVICE *dptr; DIB *dibptr; uint32 i, j, k; t_bool is_conflict = FALSE; -uint32 conflicts[MAXDEV + 1] = { 0 }; +uint32 conflicts [MAXDEV + 1] = { 0 }; -for (i = 0; (dptr = sim_devices[i]); i++) { +for (i = 0; sim_devices [i] != NULL; i++) { + dptr = sim_devices [i]; dibptr = (DIB *) dptr->ctxt; if (dibptr && !(dptr->flags & DEV_DIS)) - if (++conflicts[dibptr->select_code] > 1) + if (++conflicts [dibptr->select_code] > 1) is_conflict = TRUE; } if (is_conflict) { sim_ttcmd(); for (i = 0; i <= MAXDEV; i++) { - if (conflicts[i] > 1) { - k = conflicts[i]; + if (conflicts [i] > 1) { + k = conflicts [i]; printf ("Select code %o conflict:", i); if (sim_log) fprintf (sim_log, "Select code %o conflict:", i); - for (j = 0; (dptr = sim_devices[j]); j++) { + for (j = 0; sim_devices [j] != NULL; j++) { + dptr = sim_devices [j]; dibptr = (DIB *) dptr->ctxt; - if (dibptr && !(dptr->flags & DEV_DIS) && (i == dibptr->select_code)) { - if (k < conflicts[i]) { + if (dibptr && !(dptr->flags & DEV_DIS) && i == dibptr->select_code) { + if (k < conflicts [i]) { printf (" and"); if (sim_log) diff --git a/HP2100/hp2100_cpu0.c b/HP2100/hp2100_cpu0.c index f2506c97..a7769901 100644 --- a/HP2100/hp2100_cpu0.c +++ b/HP2100/hp2100_cpu0.c @@ -1,6 +1,6 @@ /* hp2100_cpu0.c: HP 1000 user microcode and unimplemented instruction set stubs - Copyright (c) 2006-2010, J. David Bryan + Copyright (c) 2006-2012, J. David Bryan Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), @@ -25,6 +25,7 @@ CPU0 User microcode and unimplemented firmware options + 09-May-12 JDB Separated assignments from conditional expressions 04-Nov-10 JDB Removed DS note regarding PIF card (is now implemented) 18-Sep-08 JDB .FLUN and self-tests for VIS and SIGNAL are NOP if not present 11-Sep-08 JDB Moved microcode function prototypes to hp2100_cpu1.h @@ -129,9 +130,11 @@ uint32 entry; entry = IR & 017; /* mask to entry point */ -if (op_ds[entry] != OP_N) - if ((reason = cpu_ops (op_ds[entry], op, intrq))) /* get instruction operands */ - return reason; +if (op_ds [entry] != OP_N) { + reason = cpu_ops (op_ds[entry], op, intrq); /* get instruction operands */ + if (reason != SCPE_OK) /* did the evaluation fail? */ + return reason; /* return the reason for failure */ + } switch (entry) { /* decode IR<3:0> */ @@ -191,23 +194,23 @@ switch (IR) { switch ((IR >> 4) & 037) { /* decode IR<8:4> */ -/* case 000: *//* 105000-105017 */ -/* return cpu_user_00 (IR, intrq); *//* uncomment to handle instruction */ +/* case 000: ** 105000-105017 */ +/* return cpu_user_00 (IR, intrq); ** uncomment to handle instruction */ -/* case 001: *//* 105020-105037 */ -/* return cpu_user_01 (IR, intrq); *//* uncomment to handle instruction */ +/* case 001: ** 105020-105037 */ +/* return cpu_user_01 (IR, intrq); ** uncomment to handle instruction */ -/* case 0nn: *//* other cases as needed */ -/* return cpu_user_nn (IR, intrq); *//* uncomment to handle instruction */ +/* case 0nn: ** other cases as needed */ +/* return cpu_user_nn (IR, intrq); ** uncomment to handle instruction */ case 020: /* 10x400-10x417 */ return cpu_user_20 (IR, intrq); /* call sample dispatcher */ -/* case 021: *//* 10x420-10x437 */ -/* return cpu_user_21 (IR, intrq); *//* uncomment to handle instruction */ +/* case 021: ** 10x420-10x437 */ +/* return cpu_user_21 (IR, intrq); ** uncomment to handle instruction */ -/* case 0nn: *//* other cases as needed */ -/* return cpu_user_nn (IR, intrq); *//* uncomment to handle instruction */ +/* case 0nn: ** other cases as needed */ +/* return cpu_user_nn (IR, intrq); ** uncomment to handle instruction */ default: /* others undefined */ reason = stop_inst; @@ -243,20 +246,22 @@ uint32 entry; entry = IR & 017; /* mask to entry point */ -if (op_user_20 [entry] != OP_N) - if ((reason = cpu_ops (op_user_20 [entry], op, intrq))) /* get instruction operands */ - return reason; +if (op_user_20 [entry] != OP_N) { + reason = cpu_ops (op_user_20 [entry], op, intrq); /* get instruction operands */ + if (reason != SCPE_OK) /* did the evaluation fail? */ + return reason; /* return the reason for failure */ + } switch (entry) { /* decode IR<4:0> */ case 000: /* 10x400 */ -/* break; *//* uncomment to handle instruction */ +/* break; ** uncomment to handle instruction */ case 001: /* 10x401 */ -/* break; *//* uncomment to handle instruction */ +/* break; ** uncomment to handle instruction */ -/* case 0nn: *//* other cases as needed */ -/* break; *//* uncomment to handle instruction */ +/* case 0nn: ** other cases as needed */ +/* break; ** uncomment to handle instruction */ default: /* others undefined */ reason = stop_inst; diff --git a/HP2100/hp2100_cpu1.c b/HP2100/hp2100_cpu1.c index 338d1ba9..0096e6e6 100644 --- a/HP2100/hp2100_cpu1.c +++ b/HP2100/hp2100_cpu1.c @@ -1,6 +1,6 @@ /* hp2100_cpu1.c: HP 2100/1000 EAU simulator and UIG dispatcher - Copyright (c) 2005-2008, Robert M. Supnik + Copyright (c) 2005-2012, Robert M. Supnik Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), @@ -25,6 +25,7 @@ CPU1 Extended arithmetic and optional microcode dispatchers + 09-May-12 JDB Separated assignments from conditional expressions 11-Sep-08 JDB Moved microcode function prototypes to hp2100_cpu1.h 05-Sep-08 JDB Moved option-present tests to UIG dispatchers Call "user microcode" dispatcher for unclaimed UIG instructions @@ -245,14 +246,15 @@ switch ((IR >> 8) & 0377) { /* decode IR<15:8> */ case 010: /* MPY 100200 (OP_K) */ MPY: - if ((reason = cpu_ops (OP_K, op, intrq))) /* get operand */ - break; - sop1 = SEXT (AR); /* sext AR */ - sop2 = SEXT (op[0].word); /* sext mem */ - sop1 = sop1 * sop2; /* signed mpy */ - BR = (sop1 >> 16) & DMASK; /* to BR'AR */ - AR = sop1 & DMASK; - O = 0; /* no overflow */ + reason = cpu_ops (OP_K, op, intrq); /* get operand */ + if (reason == SCPE_OK) { /* successful eval? */ + sop1 = SEXT (AR); /* sext AR */ + sop2 = SEXT (op[0].word); /* sext mem */ + sop1 = sop1 * sop2; /* signed mpy */ + BR = (sop1 >> 16) & DMASK; /* to BR'AR */ + AR = sop1 & DMASK; + O = 0; /* no overflow */ + } break; default: /* others undefined */ @@ -262,9 +264,11 @@ switch ((IR >> 8) & 0377) { /* decode IR<15:8> */ break; case 0201: /* DIV 100400 (OP_K) */ - if ((reason = cpu_ops (OP_K, op, intrq))) /* get operand */ + reason = cpu_ops (OP_K, op, intrq); /* get operand */ + if (reason != SCPE_OK) /* eval failed? */ break; - if ((rs = qs = BR & SIGN)) { /* save divd sign, neg? */ + rs = qs = BR & SIGN; /* save divd sign */ + if (rs) { /* neg? */ AR = (~AR + 1) & DMASK; /* make B'A pos */ BR = (~BR + (AR == 0)) & DMASK; /* make divd pos */ } @@ -317,17 +321,19 @@ switch ((IR >> 8) & 0377) { /* decode IR<15:8> */ break; case 0210: /* DLD 104200 (OP_D) */ - if ((reason = cpu_ops (OP_D, op, intrq))) /* get operand */ - break; - AR = (op[0].dword >> 16) & DMASK; /* load AR */ - BR = op[0].dword & DMASK; /* load BR */ + reason = cpu_ops (OP_D, op, intrq); /* get operand */ + if (reason == SCPE_OK) { /* successful eval? */ + AR = (op[0].dword >> 16) & DMASK; /* load AR */ + BR = op[0].dword & DMASK; /* load BR */ + } break; case 0211: /* DST 104400 (OP_A) */ - if ((reason = cpu_ops (OP_A, op, intrq))) /* get operand */ - break; - WriteW (op[0].word, AR); /* store AR */ - WriteW ((op[0].word + 1) & VAMASK, BR); /* store BR */ + reason = cpu_ops (OP_A, op, intrq); /* get operand */ + if (reason == SCPE_OK) { /* successful eval? */ + WriteW (op[0].word, AR); /* store AR */ + WriteW ((op[0].word + 1) & VAMASK, BR); /* store BR */ + } break; default: /* should never get here */ @@ -733,9 +739,11 @@ uint32 i, MA; for (i = 0; i < OP_N_F; i++) { flags = pattern & OP_M_FLAGS; /* get operand pattern */ - if (flags >= OP_ADR) /* address operand? */ - if ((reason = resolve (ReadW (PC), &MA, irq))) /* resolve indirects */ + if (flags >= OP_ADR) { /* address operand? */ + reason = resolve (ReadW (PC), &MA, irq); /* resolve indirects */ + if (reason != SCPE_OK) /* resolution failed? */ return reason; + } switch (flags) { case OP_NUL: /* null operand */ diff --git a/HP2100/hp2100_cpu2.c b/HP2100/hp2100_cpu2.c index 464452ae..a55cf656 100644 --- a/HP2100/hp2100_cpu2.c +++ b/HP2100/hp2100_cpu2.c @@ -1,6 +1,6 @@ /* hp2100_cpu2.c: HP 2100/1000 FP/DMS/EIG/IOP instructions - Copyright (c) 2005-2008, Robert M. Supnik + Copyright (c) 2005-2012, Robert M. Supnik Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), @@ -26,6 +26,7 @@ CPU2 Floating-point, dynamic mapping, extended, and I/O processor instructions + 09-May-12 JDB Separated assignments from conditional expressions 11-Sep-08 JDB Moved microcode function prototypes to hp2100_cpu1.h 05-Sep-08 JDB Removed option-present tests (now in UIG dispatchers) 05-Aug-08 JDB Updated mp_dms_jmp calling sequence @@ -243,9 +244,12 @@ uint32 i, t, mapi, mapj; absel = (IR & I_AB)? 1: 0; /* get A/B select */ entry = IR & 037; /* mask to entry point */ -if (op_dms[entry] != OP_N) - if ((reason = cpu_ops (op_dms[entry], op, intrq))) /* get instruction operands */ - return reason; +if (op_dms [entry] != OP_N) { + reason = cpu_ops (op_dms [entry], op, intrq); /* get instruction operands */ + + if (reason != SCPE_OK) /* evaluation failed? */ + return reason; /* return reason for failure */ + } switch (entry) { /* decode IR<3:0> */ @@ -609,9 +613,12 @@ int32 sop1, sop2; absel = (IR & I_AB)? 1: 0; /* get A/B select */ entry = IR & 037; /* mask to entry point */ -if (op_eig[entry] != OP_N) - if ((reason = cpu_ops (op_eig[entry], op, intrq))) /* get instruction operands */ - return reason; +if (op_eig [entry] != OP_N) { + reason = cpu_ops (op_eig [entry], op, intrq); /* get instruction operands */ + + if (reason != SCPE_OK) /* evaluation failed? */ + return reason; /* return reason for failure */ + } switch (entry) { /* decode IR<4:0> */ @@ -988,9 +995,12 @@ else if (entry <= 057) /* IR = 10x440-457? */ entry = entry - 060; /* offset 10x460-477 */ -if (op_iop[entry] != OP_N) - if ((reason = cpu_ops (op_iop[entry], op, intrq))) /* get instruction operands */ - return reason; +if (op_iop [entry] != OP_N) { + reason = cpu_ops (op_iop [entry], op, intrq); /* get instruction operands */ + + if (reason != SCPE_OK) /* evaluation failed? */ + return reason; /* return reason for failure */ + } switch (entry) { /* decode IR<5:0> */ diff --git a/HP2100/hp2100_cpu3.c b/HP2100/hp2100_cpu3.c index 036a3d82..3e201aea 100644 --- a/HP2100/hp2100_cpu3.c +++ b/HP2100/hp2100_cpu3.c @@ -25,6 +25,7 @@ CPU3 Fast FORTRAN and Double Integer instructions + 09-May-12 JDB Separated assignments from conditional expressions 11-Sep-08 JDB Moved microcode function prototypes to hp2100_cpu1.h 05-Sep-08 JDB Removed option-present tests (now in UIG dispatchers) 05-Aug-08 JDB Updated mp_dms_jmp calling sequence @@ -185,17 +186,23 @@ int32 i; entry = IR & 037; /* mask to entry point */ if (UNIT_CPU_MODEL != UNIT_1000_F) { /* 2100/M/E-Series? */ - if (op_ffp_e[entry] != OP_N) - if ((reason = cpu_ops (op_ffp_e[entry], op, intrq)))/* get instruction operands */ - return reason; + if (op_ffp_e [entry] != OP_N) { + reason = cpu_ops (op_ffp_e [entry], op, intrq); /* get instruction operands */ + + if (reason != SCPE_OK) /* evaluation failed? */ + return reason; /* return reason for failure */ + } } #if defined (HAVE_INT64) /* int64 support available */ else { /* F-Series */ - if (op_ffp_f[entry] != OP_N) - if ((reason = cpu_ops (op_ffp_f[entry], op, intrq)))/* get instruction operands */ - return reason; + if (op_ffp_f [entry] != OP_N) { + reason = cpu_ops (op_ffp_f [entry], op, intrq); /* get instruction operands */ + + if (reason != SCPE_OK) /* evaluation failed? */ + return reason; /* return reason for failure */ + } switch (entry) { /* decode IR<4:0> */ @@ -417,7 +424,8 @@ switch (entry) { /* decode IR<4:0> */ sa = op[0].word - 1; da = ReadW (sa); /* get jump target */ - if ((reason = resolve (da, &MA, intrq))) { /* resolve indirects */ + reason = resolve (da, &MA, intrq); /* resolve indirects */ + if (reason != SCPE_OK) { /* resolution failed? */ PC = err_PC; /* irq restarts instruction */ break; } @@ -435,7 +443,8 @@ switch (entry) { /* decode IR<4:0> */ op[1].word = op[1].word + /* compute element offset */ (op[2].word - 1) * op[3].word; else { /* 3-dim access */ - if ((reason = cpu_ops (OP_KK, op2, intrq))) {/* get 1st, 2nd ranges */ + reason = cpu_ops (OP_KK, op2, intrq); /* get 1st, 2nd ranges */ + if (reason != SCPE_OK) { /* evaluation failed? */ PC = err_PC; /* irq restarts instruction */ break; } @@ -461,7 +470,8 @@ switch (entry) { /* decode IR<4:0> */ for (j = 0; j < sc; j++) { MA = ReadW (sa++); /* get addr of actual */ - if ((reason = resolve (MA, &MA, intrq))) { /* resolve indirect */ + reason = resolve (MA, &MA, intrq); /* resolve indirect */ + if (reason != SCPE_OK) { /* resolution failed? */ PC = err_PC; /* irq restarts instruction */ break; } @@ -643,9 +653,11 @@ t_stat reason = SCPE_OK; entry = IR & 017; /* mask to entry point */ -if (op_dbi[entry] != OP_N) - if ((reason = cpu_ops (op_dbi[entry], op, intrq))) /* get instruction operands */ - return reason; +if (op_dbi[entry] != OP_N) { + reason = cpu_ops (op_dbi [entry], op, intrq); /* get instruction operands */ + if (reason != SCPE_OK) /* evaluation failed? */ + return reason; /* return reason for failure */ + } switch (entry) { /* decode IR<3:0> */ diff --git a/HP2100/hp2100_cpu4.c b/HP2100/hp2100_cpu4.c index 2f8cba77..ea294664 100644 --- a/HP2100/hp2100_cpu4.c +++ b/HP2100/hp2100_cpu4.c @@ -25,6 +25,7 @@ CPU4 Floating Point Processor and Scientific Instruction Set + 09-May-12 JDB Separated assignments from conditional expressions 06-Feb-12 JDB Added OPSIZE casts to fp_accum calls in .FPWR/.TPWR 11-Sep-08 JDB Moved microcode function prototypes to hp2100_cpu1.h 05-Sep-08 JDB Removed option-present tests (now in UIG dispatchers) @@ -260,9 +261,12 @@ else entry = opcode & 0177; /* map to <6:0> */ -if (op_fpp[entry] != OP_N) - if ((reason = cpu_ops (op_fpp[entry], op, intrq))) /* get instruction operands */ - return reason; +if (op_fpp [entry] != OP_N) { + reason = cpu_ops (op_fpp [entry], op, intrq); /* get instruction operands */ + + if (reason != SCPE_OK) /* evaluation failed? */ + return reason; /* return reason for failure */ + } switch (entry) { /* decode IR<6:0> */ case 0000: /* FAD 105000 (OP_RF) */ @@ -599,9 +603,12 @@ static const OP t_one = { { 0040000, 0000000, 0000000, 0000002 } }; /* DEY 1. entry = IR & 017; /* mask to entry point */ -if (op_sis[entry] != OP_N) - if ((reason = cpu_ops (op_sis[entry], op, intrq))) /* get instruction operands */ - return reason; +if (op_sis [entry] != OP_N) { + reason = cpu_ops (op_sis [entry], op, intrq); /* get instruction operands */ + + if (reason != SCPE_OK) /* evaluation failed? */ + return reason; /* return reason for failure */ + } switch (entry) { /* decode IR<3:0> */ diff --git a/HP2100/hp2100_cpu5.c b/HP2100/hp2100_cpu5.c index 3e70d92d..5a72e75a 100644 --- a/HP2100/hp2100_cpu5.c +++ b/HP2100/hp2100_cpu5.c @@ -26,6 +26,8 @@ CPU5 RTE-6/VM and RTE-IV firmware option instructions + 17-Dec-12 JDB Fixed cpu_vma_mapte to return FALSE if not a VMA program + 09-May-12 JDB Separated assignments from conditional expressions 23-Mar-12 JDB Added sign extension for dim count in "cpu_ema_resolve" 28-Dec-11 JDB Eliminated unused variable in "cpu_ema_vset" 11-Sep-08 JDB Moved microcode function prototypes to hp2100_cpu1.h @@ -332,8 +334,13 @@ uint32 dispatch = ReadIO(vswp,UMAP) & 01777; /* get fresh dispatch flag * t_bool swapflag = TRUE; if (dispatch == 0) { /* not yet set */ - idext = ReadIO(idx,UMAP); /* go into IDsegment extent */ - if (idext != 0) { /* is ema/vma program? */ + idext = ReadIO(idx,UMAP); /* go into ID segment extent */ + if (idext == 0) { /* is ema/vma program? */ + swapflag = FALSE; /* no, so mark PTE as invalid */ + *ptepg = (uint32) -1; /* and return an invalid page number */ + } + + else { /* is an EMA/VMA program */ dispatch = ReadWA(idext+1) & 01777; /* get 1st ema page: new vswp */ WriteIO(vswp,dispatch,UMAP); /* move into $VSWP */ idext2 = ReadWA(idext+2); /* get swap bit */ @@ -346,7 +353,7 @@ if (dispatch) { /* some page is defined */ *ptepg = dispatch; /* return PTEPG# for later */ } -return swapflag; /* true for swap bit set */ +return swapflag; /* true for valid PTE */ } /* .LBP @@ -649,9 +656,11 @@ t_bool debug = DEBUG_PRI (cpu_dev, DEB_VMA); entry = IR & 017; /* mask to entry point */ pattern = op_vma[entry]; /* get operand pattern */ -if (pattern != OP_N) - if ((reason = cpu_ops (pattern, op, intrq))) /* get instruction operands */ - return reason; +if (pattern != OP_N) { + reason = cpu_ops (pattern, op, intrq); /* get instruction operands */ + if (reason != SCPE_OK) /* evaluation failed? */ + return reason; /* return reason for failure */ + } if (debug) { /* debugging? */ fprintf (sim_deb, ">>CPU VMA: IR = %06o (", IR); /* print preamble and IR */ @@ -1360,9 +1369,11 @@ t_bool debug = DEBUG_PRI (cpu_dev, DEB_EMA); entry = IR & 017; /* mask to entry point */ pattern = op_ema[entry]; /* get operand pattern */ -if (pattern != OP_N) - if ((reason = cpu_ops (pattern, op, intrq))) /* get instruction operands */ - return reason; +if (pattern != OP_N) { + reason = cpu_ops (pattern, op, intrq); /* get instruction operands */ + if (reason != SCPE_OK) /* evaluation failed? */ + return reason; /* return reason for failure */ + } if (debug) { /* debugging? */ fprintf (sim_deb, ">>CPU EMA: PC = %06o, IR = %06o (", err_PC,IR); /* print preamble and IR */ diff --git a/HP2100/hp2100_cpu6.c b/HP2100/hp2100_cpu6.c index 4baa952f..b3dc34aa 100644 --- a/HP2100/hp2100_cpu6.c +++ b/HP2100/hp2100_cpu6.c @@ -1,6 +1,6 @@ /* hp2100_cpu6.c: HP 1000 RTE-6/VM OS instructions - Copyright (c) 2006-2010, J. David Bryan + Copyright (c) 2006-2012, J. David Bryan Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), @@ -25,6 +25,7 @@ CPU6 RTE-6/VM OS instructions + 09-May-12 JDB Separated assignments from conditional expressions 29-Oct-10 JDB DMA channels renamed from 0,1 to 1,2 to match documentation 18-Sep-08 JDB Corrected .SIP debug formatting 11-Sep-08 JDB Moved microcode function prototypes to hp2100_cpu1.h @@ -393,11 +394,14 @@ static t_bool tbg_tick = FALSE; /* set if processing TBG entry = IR & 017; /* mask to entry point */ pattern = op_os[entry]; /* get operand pattern */ -if (pattern != OP_N) - if ((reason = cpu_ops (pattern, op, intrq))) /* get instruction operands */ - return reason; +if (pattern != OP_N) { + reason = cpu_ops (pattern, op, intrq); /* get instruction operands */ -tbg_tick = tbg_tick || ((IR == 0105357) && iotrap); /* set TBG interrupting flag */ + if (reason != SCPE_OK) /* evaluation failed? */ + return reason; /* return reason for failure */ + } + +tbg_tick = tbg_tick || (IR == 0105357) && iotrap; /* set TBG interrupting flag */ debug_print = (DEBUG_PRI (cpu_dev, DEB_OS) && !tbg_tick) || (DEBUG_PRI (cpu_dev, DEB_OSTBG) && tbg_tick); @@ -544,7 +548,9 @@ switch (entry) { /* decode IR<3:0> */ for (i = 0; i < count; i++) { ma = ReadW (PC); /* get operand address */ - if ((reason = resolve (ma, &ma, intrq))) { /* resolve indirect */ + reason = resolve (ma, &ma, intrq); /* resolve indirect */ + + if (reason != SCPE_OK) { /* resolution failed? */ PC = err_PC; /* IRQ restarts instruction */ break; } @@ -620,8 +626,8 @@ switch (entry) { /* decode IR<3:0> */ while ((AR != 0) && ((AR & SIGN) == 0)) { /* end of list or bad list? */ key = ReadW ((AR + op[1].word) & VAMASK); /* get key value */ - if (((E == 0) && (key == op[0].word)) || /* for E = 0, key = arg? */ - ((E != 0) && (key > op[0].word))) /* for E = 1, key > arg? */ + if ((E == 0) && (key == op[0].word) || /* for E = 0, key = arg? */ + (E != 0) && (key > op[0].word)) /* for E = 1, key > arg? */ break; /* search is done */ BR = AR; /* B = last link */ @@ -710,8 +716,10 @@ switch (entry) { /* decode IR<3:0> */ ma = ReadW (sa); /* get addr of actual */ sa = (sa + 1) & VAMASK; /* increment address */ - if ((reason = resolve (ma, &ma, intrq))) { /* resolve indirect */ - PC = err_PC; /* irq restarts instruction */ + reason = resolve (ma, &ma, intrq); /* resolve indirect */ + + if (reason != SCPE_OK) { /* resolution failed? */ + PC = err_PC; /* irq restarts instruction */ break; } diff --git a/HP2100/hp2100_cpu7.c b/HP2100/hp2100_cpu7.c index cf3f2c76..84fb1163 100644 --- a/HP2100/hp2100_cpu7.c +++ b/HP2100/hp2100_cpu7.c @@ -26,6 +26,7 @@ CPU7 Vector Instruction Set and SIGNAL firmware + 09-May-12 JDB Separated assignments from conditional expressions 06-Feb-12 JDB Corrected "opsize" parameter type in vis_abs 11-Sep-08 JDB Moved microcode function prototypes to hp2100_cpu1.h 05-Sep-08 JDB Removed option-present tests (now in UIG dispatchers) @@ -383,16 +384,18 @@ if (entry==0) { /* retrieve sub opcode subcode = AR; /* for reentry */ PC = (PC + 1) & VAMASK; /* bump to real argument list */ pattern = (subcode & 0400) ? OP_AAKAKK : OP_AKAKAKK; /* scalar or vector operation */ -} + } -if (pattern != OP_N) +if (pattern != OP_N) { if (op_ftnret[entry]) { /* most VIS instrs ignore RTN addr */ ret = ReadOp(PC, in_s); rtn = rtn1 = ret.word; /* but save it just in case */ PC = (PC + 1) & VAMASK; /* move to next argument */ + } + reason = cpu_ops (pattern, op, intrq); /* get instruction operands */ + if (reason != SCPE_OK) /* evaluation failed? */ + return reason; /* return reason for failure */ } - if ((reason = cpu_ops (pattern, op, intrq))) /* get instruction operands */ - return reason; if (debug) { /* debugging? */ fprintf (sim_deb, ">>CPU VIS: IR = %06o/%06o (", /* print preamble and IR */ @@ -652,9 +655,11 @@ t_bool debug = DEBUG_PRI (cpu_dev, DEB_SIG); entry = IR & 017; /* mask to entry point */ -if (op_signal[entry] != OP_N) - if ((reason = cpu_ops (op_signal[entry], op, intrq)))/* get instruction operands */ - return reason; +if (op_signal [entry] != OP_N) { + reason = cpu_ops (op_signal [entry], op, intrq); /* get instruction operands */ + if (reason != SCPE_OK) /* evaluation failed? */ + return reason; /* return reason for failure */ + } if (debug) { /* debugging? */ fprintf (sim_deb, ">>CPU SIG: IR = %06o (", IR); /* print preamble and IR */ diff --git a/HP2100/hp2100_defs.h b/HP2100/hp2100_defs.h index 3118e2d1..2f65fe9d 100644 --- a/HP2100/hp2100_defs.h +++ b/HP2100/hp2100_defs.h @@ -23,6 +23,8 @@ be used in advertising or otherwise to promote the sale, use or other dealings in this Software without prior written authorization from Robert M Supnik. + 14-Dec-12 JDB Added "-Wbitwise-op-parentheses" to the suppression pragmas + 12-May-12 JDB Added pragmas to suppress logical operator precedence warnings 10-Feb-12 JDB Added hp_setsc, hp_showsc functions to support SC modifier 28-Mar-11 JDB Tidied up signal handling 29-Oct-10 JDB DMA channels renamed from 0,1 to 1,2 to match documentation @@ -72,6 +74,16 @@ #include "sim_defs.h" /* simulator defns */ +/* Required to quell clang precedence warnings */ + +#if defined (__GNUC__) +#pragma GCC diagnostic ignored "-Wunknown-pragmas" +#pragma GCC diagnostic ignored "-Wpragmas" +#pragma GCC diagnostic ignored "-Wlogical-op-parentheses" +#pragma GCC diagnostic ignored "-Wbitwise-op-parentheses" +#endif + + /* Simulator stop and notification codes */ #define STOP_RSRV 1 /* must be 1 */ @@ -455,7 +467,6 @@ extern void hp_enbdis_pair (DEVICE *ccp, DEVICE *dcp); /* System functions */ -extern t_stat fprint_sym (FILE *ofile, t_addr addr, t_value *val, UNIT *uptr, int32 sw); extern const char *fmt_char (uint8 ch); extern t_stat hp_setsc (UNIT *uptr, int32 val, char *cptr, void *desc); extern t_stat hp_showsc (FILE *st, UNIT *uptr, int32 val, void *desc); diff --git a/HP2100/hp2100_di.c b/HP2100/hp2100_di.c index 2238d356..98cc4ef0 100644 --- a/HP2100/hp2100_di.c +++ b/HP2100/hp2100_di.c @@ -1466,10 +1466,10 @@ if (assert != deny) /* was there any change previous_state = di_card->srq; /* save the current SRQ state */ -if (((di_card->cntl_register & CNTL_LSTN) && /* if the card is a listener */ - (di_card->status_register & STAT_IRL)) || /* and the input register is loaded, */ - ((di_card->cntl_register & CNTL_TALK) && /* or the card is a talker */ - ! FIFO_FULL)) /* and the FIFO is not full */ +if (di_card->cntl_register & CNTL_LSTN /* if the card is a listener */ + && di_card->status_register & STAT_IRL /* and the input register is loaded, */ + || di_card->cntl_register & CNTL_TALK /* or the card is a talker */ + && ! FIFO_FULL) /* and the FIFO is not full */ di_card->srq = SET; /* then request a DCPC cycle */ else di_card->srq = CLEAR; /* otherwise, DCPC service is not needed */ @@ -1481,21 +1481,21 @@ if (DEBUG_PRJ (dptrs [card], DEB_CMDS) dptrs [card]->name, di_card->srq == SET ? "set" : "cleared"); -if (((di_card->status_register & STAT_IRL) && /* is the input register loaded */ - (di_card->cntl_register & CNTL_IRL)) || /* and notification is wanted? */ - ((di_card->status_register & STAT_LBO) && /* or is the last byte out */ - (di_card->cntl_register & CNTL_LBO)) || /* and notification is wanted? */ - ((di_card->eor == SET) && /* or was the end of record seen */ - !(di_card->status_register & STAT_IRL)) || /* and the input register was unloaded? */ - ((di_card->bus_cntl & BUS_SRQ) && /* or is SRQ asserted on the bus */ - (di_card->cntl_register & CNTL_SRQ) && /* and notification is wanted */ - (di_card->cntl_register & CNTL_CIC)) || /* and the card is not controller? */ - (!SW8_SYSCTL && /* or is the card not the system controller */ - (di_card->bus_cntl & BUS_REN) && /* and REN is asserted on the bus */ - (di_card->cntl_register & CNTL_REN)) || /* and notification is wanted? */ - (!SW8_SYSCTL && /* or is the card not the system controller */ - (di_card->status_register & STAT_IFC) && /* and IFC is asserted on the bus */ - (di_card->cntl_register & CNTL_IFC))) { /* and notification is wanted? */ +if (di_card->status_register & STAT_IRL /* is the input register loaded */ + && di_card->cntl_register & CNTL_IRL /* and notification is wanted? */ + || di_card->status_register & STAT_LBO /* or is the last byte out */ + && di_card->cntl_register & CNTL_LBO /* and notification is wanted? */ + || di_card->eor == SET /* or was the end of record seen */ + && !(di_card->status_register & STAT_IRL) /* and the input register was unloaded? */ + || di_card->bus_cntl & BUS_SRQ /* or is SRQ asserted on the bus */ + && di_card->cntl_register & CNTL_SRQ /* and notification is wanted */ + && di_card->cntl_register & CNTL_CIC /* and the card is not controller? */ + || !SW8_SYSCTL /* or is the card not the system controller */ + && di_card->bus_cntl & BUS_REN /* and REN is asserted on the bus */ + && di_card->cntl_register & CNTL_REN /* and notification is wanted? */ + || !SW8_SYSCTL /* or is the card not the system controller */ + && di_card->status_register & STAT_IFC /* and IFC is asserted on the bus */ + && di_card->cntl_register & CNTL_IFC) { /* and notification is wanted? */ if (DEBUG_PRJ (dptrs [card], DEB_CMDS)) fprintf (sim_deb, ">>%s cmds: Flag set\n", diff --git a/HP2100/hp2100_di_da.c b/HP2100/hp2100_di_da.c index eea57d72..a3d73fdd 100644 --- a/HP2100/hp2100_di_da.c +++ b/HP2100/hp2100_di_da.c @@ -25,6 +25,8 @@ DA 12821A Disc Interface with Amigo disc drives + 24-Oct-12 JDB Changed CNTLR_OPCODE to title case to avoid name clash + 07-May-12 JDB Cancel the intersector delay if an untalk is received 29-Mar-12 JDB First release 04-Nov-11 JDB Created DA device @@ -756,7 +758,7 @@ switch (if_state [unit]) { /* dispatch the inte case disc_command: /* execute a disc command */ result = dl_service_drive (cvptr, uptr); /* service the disc unit */ - if (cvptr->opcode == clear) /* is this a Clear command? */ + if (cvptr->opcode == Clear) /* is this a Clear command? */ if_dsj [unit] = 2; /* indicate that the self test is complete */ if (cvptr->state != cntlr_busy) { /* has the controller stopped? */ @@ -856,7 +858,7 @@ switch (if_state [unit]) { /* dispatch the inte if (cvptr->length == 0 || cvptr->eod == SET) { /* is the data phase complete? */ uptr->PHASE = end_phase; /* set the end phase */ - if (cvptr->opcode == request_status) /* is it a Request Status command? */ + if (cvptr->opcode == Request_Status) /* is it a Request Status command? */ if_dsj [unit] = 0; /* clear the DSJ value */ if_state [unit] = command_exec; /* set to execute the command */ @@ -980,7 +982,7 @@ if (result == SCPE_IERR && DEBUG_PRI (da_dev, DEB_RWSC)) { /* did an internal e if (if_state [unit] == idle) { /* is the command now complete? */ if (if_command [unit] == disc_command) { /* did a disc command complete? */ - if (cvptr->opcode != end) /* yes; if the command was not End, */ + if (cvptr->opcode != End) /* yes; if the command was not End, */ di_poll_response (da, unit, SET); /* then enable PPR */ if (DEBUG_PRI (da_dev, DEB_RWSC)) @@ -1266,7 +1268,7 @@ result = dl_load_unload (&icd_cntlr [unit], uptr, load); /* load or unload th if (result == SCPE_OK && ! load) { /* was the unload successful? */ icd_cntlr [unit].status = drive_attention; /* set Drive Attention status */ - if (uptr->OP == end) /* is the controller in idle state 2? */ + if (uptr->OP == End) /* is the controller in idle state 2? */ di_poll_response (da, unit, SET); /* enable PPR */ } @@ -1594,10 +1596,10 @@ if (di [da].bus_cntl & BUS_ATN) { /* is it a bus comma da_unit [unit].wait = icd_cntlr [unit].cmd_time; /* these are always scheduled and */ initiated = TRUE; /* logged as initiated */ - if (((if_state [unit] == read_wait) && /* if we're waiting for a send data secondary */ - (message_address != 0x00)) || /* but it's not there */ - ((if_state [unit] == status_wait) && /* or a send status secondary, */ - (message_address != 0x08))) /* but it's not there */ + if (if_state [unit] == read_wait /* if we're waiting for a send data secondary */ + && message_address != 0x00 /* but it's not there */ + || if_state [unit] == status_wait /* or a send status secondary, */ + && message_address != 0x08) /* but it's not there */ abort_command (unit, io_program_error, /* then abort the pending command */ idle); /* and process the new command */ @@ -1962,6 +1964,11 @@ return; 2. There is no need to test if we are processing a disc command, as the controller would not be busy otherwise. + + 3. If an auto-seek will be needed to continue the read, but the seek will + fail, then an extra delay is inserted before the service call to start + the next sector. Once an Untalk is received, this delay is no longer + needed, so it is cancelled before rescheduling the service routine. */ static void complete_read (uint32 unit) @@ -1974,7 +1981,9 @@ if ((if_state [unit] == command_exec /* is a command exec if_state [unit] = command_exec; /* set to execute */ da_unit [unit].PHASE = end_phase; /* the completion phase */ - da_unit [unit].wait = icd_cntlr [unit].data_time; /* ensure that the controller will finish */ + + sim_cancel (&da_unit [unit]); /* cancel the EOT delay */ + da_unit [unit].wait = icd_cntlr [unit].data_time; /* reschedule for completion */ } return; diff --git a/HP2100/hp2100_dp.c b/HP2100/hp2100_dp.c index c6877dca..40614207 100644 --- a/HP2100/hp2100_dp.c +++ b/HP2100/hp2100_dp.c @@ -26,6 +26,8 @@ DP 12557A 2871 disk subsystem 13210A 7900 disk subsystem + 18-Dec-12 MP Now calls sim_activate_time to get remaining seek time + 09-May-12 JDB Separated assignments from conditional expressions 10-Feb-12 JDB Deprecated DEVNO in favor of SC Added CNTLR_TYPE cast to dp_settype 28-Mar-11 JDB Tidied up signal handling @@ -190,7 +192,7 @@ #define STA_PROT 0002000 /* protected (13210) */ #define STA_SKI 0001000 /* incomplete NI (u) */ #define STA_SKE 0000400 /* seek error */ -/* 0000200 *//* unused */ +/* 0000200 (unused) */ #define STA_NRDY 0000100 /* not ready (d) */ #define STA_EOC 0000040 /* end of cylinder */ #define STA_AER 0000020 /* addr error */ @@ -694,7 +696,8 @@ void dp_goc (int32 fnc, int32 drv, int32 time) { int32 t; -if ((t = sim_is_active (&dpc_unit[drv]))) { /* still seeking? */ +t = sim_activate_time (&dpc_unit[drv]); +if (t) { /* still seeking? */ sim_cancel (&dpc_unit[drv]); /* stop seek */ dpc_sta[drv] = dpc_sta[drv] & ~STA_BSY; /* clear busy */ time = time + t; /* include seek time */ @@ -906,10 +909,13 @@ switch (uptr->FNC) { /* case function */ dpc_rarh = dpc_rarh ^ 1; /* incr head */ dpc_eoc = ((dpc_rarh & 1) == 0); /* calc eoc */ } - if ((err = fseek (uptr->fileref, da * sizeof (int16), - SEEK_SET))) break; + err = fseek (uptr->fileref, da * sizeof (int16), SEEK_SET); + if (err) /* error? */ + break; fxread (dpxb, sizeof (int16), DP_NUMWD, uptr->fileref); - if ((err = ferror (uptr->fileref))) break; + err = ferror (uptr->fileref); + if (err) /* error? */ + break; } dpd_ibuf = dpxb[dp_ptr++]; /* get word */ if (dp_ptr >= DP_NUMWD) { /* end of sector? */ @@ -953,10 +959,13 @@ switch (uptr->FNC) { /* case function */ dpc_rarh = dpc_rarh ^ 1; /* incr head */ dpc_eoc = ((dpc_rarh & 1) == 0); /* calc eoc */ } - if ((err = fseek (uptr->fileref, da * sizeof (int16), - SEEK_SET))) break; + err = fseek (uptr->fileref, da * sizeof (int16), SEEK_SET); + if (err) /* error? */ + break; fxwrite (dpxb, sizeof (int16), DP_NUMWD, uptr->fileref); - if ((err = ferror (uptr->fileref))) break; /* error? */ + err = ferror (uptr->fileref); + if (err) /* error? */ + break; dp_ptr = 0; /* next sector */ } if (dpd.command && dpd_xfer) /* dch on, xfer? */ diff --git a/HP2100/hp2100_dq.c b/HP2100/hp2100_dq.c index 24b8f303..11feafb7 100644 --- a/HP2100/hp2100_dq.c +++ b/HP2100/hp2100_dq.c @@ -26,6 +26,8 @@ DQ 12565A 2883 disk system + 18-Dec-12 MP Now calls sim_activate_time to get remaining seek time + 09-May-12 JDB Separated assignments from conditional expressions 10-Feb-12 JDB Deprecated DEVNO in favor of SC 28-Mar-11 JDB Tidied up signal handling 26-Oct-10 JDB Changed I/O signal handler for revised signal model @@ -100,7 +102,7 @@ #define CW_V_FNC 12 /* function */ #define CW_M_FNC 017 #define CW_GETFNC(x) (((x) >> CW_V_FNC) & CW_M_FNC) -/* 000 *//* unused */ +/* 000 (unused) */ #define FNC_STA 001 /* status check */ #define FNC_RCL 002 /* recalibrate */ #define FNC_SEEK 003 /* seek */ @@ -530,7 +532,9 @@ void dq_goc (int32 fnc, int32 drv, int32 time) { int32 t; -if ((t = sim_is_active (&dqc_unit[drv]))) { /* still seeking? */ +t = sim_activate_time (&dqc_unit[drv]); + +if (t) { /* still seeking? */ sim_cancel (&dqc_unit[drv]); /* cancel */ time = time + t; /* include seek time */ } @@ -740,10 +744,13 @@ switch (uptr->FNC) { /* case function */ dqc_rars = (dqc_rars + 1) % DQ_NUMSC; /* incr sector */ if (dqc_rars == 0) /* wrap? incr head */ dqc_uhed[drv] = dqc_rarh = dqc_rarh + 1; - if ((err = fseek (uptr->fileref, da * sizeof (int16), - SEEK_SET))) break; + err = fseek (uptr->fileref, da * sizeof (int16), SEEK_SET); + if (err) + break; fxread (dqxb, sizeof (int16), DQ_NUMWD, uptr->fileref); - if ((err = ferror (uptr->fileref))) break; + err = ferror (uptr->fileref); + if (err) + break; } dqd_ibuf = dqxb[dq_ptr++]; /* get word */ if (dq_ptr >= DQ_NUMWD) { /* end of sector? */ @@ -786,10 +793,13 @@ switch (uptr->FNC) { /* case function */ dqc_rars = (dqc_rars + 1) % DQ_NUMSC; /* incr sector */ if (dqc_rars == 0) /* wrap? incr head */ dqc_uhed[drv] = dqc_rarh = dqc_rarh + 1; - if ((err = fseek (uptr->fileref, da * sizeof (int16), - SEEK_SET))) return TRUE; + err = fseek (uptr->fileref, da * sizeof (int16), SEEK_SET); + if (err) + break; fxwrite (dqxb, sizeof (int16), DQ_NUMWD, uptr->fileref); - if ((err = ferror (uptr->fileref))) break; + err = ferror (uptr->fileref); + if (err) + break; dq_ptr = 0; } if (dqd.command && dqd_xfer) { /* dch on, xfer? */ diff --git a/HP2100/hp2100_ds.c b/HP2100/hp2100_ds.c index 29df4589..f42a7c8c 100644 --- a/HP2100/hp2100_ds.c +++ b/HP2100/hp2100_ds.c @@ -26,6 +26,7 @@ DS 13037D/13175D disc controller/interface + 24-Oct-12 JDB Changed CNTLR_OPCODE to title case to avoid name clash 29-Mar-12 JDB Rewritten to use the MAC/ICD disc controller library ioIOO now notifies controller service of parameter output 14-Feb-12 JDB Corrected SRQ generation and FIFO under/overrun detection @@ -705,10 +706,10 @@ result = dl_service_drive (&mac_cntlr, uptr); /* service the drive */ if ((CNTLR_PHASE) uptr->PHASE == data_phase) /* is the drive in the data phase? */ switch ((CNTLR_OPCODE) uptr->OP) { /* dispatch the current operation */ - case read: /* read operations */ - case read_full_sector: - case read_with_offset: - case read_without_verify: + case Read: /* read operations */ + case Read_Full_Sector: + case Read_With_Offset: + case Read_Without_Verify: if (mac_cntlr.length == 0 || ds.edt == SET) { /* is the data phase complete? */ mac_cntlr.eod = ds.edt; /* set EOD if DCPC is done */ uptr->PHASE = end_phase; /* set the end phase */ @@ -729,9 +730,9 @@ if ((CNTLR_PHASE) uptr->PHASE == data_phase) /* is the drive in the d break; - case write: /* write operations */ - case write_full_sector: - case initialize: + case Write: /* write operations */ + case Write_Full_Sector: + case Initialize: if (entry_phase == start_phase) { /* is this the phase transition? */ ds.srq = SET; /* start the DCPC transfer */ ds_io (&ds_dib, ioSIR, 0); /* and recalculate the interrupts */ @@ -850,19 +851,19 @@ switch ((CNTLR_PHASE) uptr->PHASE) { /* dispatch the current case end_phase: /* start and end on the same phase */ switch (opcode) { /* dispatch the current operation */ - case request_status: - case request_sector_address: - case address_record: - case request_syndrome: - case load_tio_register: - case request_disc_address: - case end: + case Request_Status: + case Request_Sector_Address: + case Address_Record: + case Request_Syndrome: + case Load_TIO_Register: + case Request_Disc_Address: + case End: break; /* complete the operation without setting the flag */ - case clear: - case set_file_mask: - case wakeup: + case Clear: + case Set_File_Mask: + case Wakeup: ds_io (&ds_dib, ioENF, 0); /* complete the operation and set the flag */ break; @@ -877,11 +878,11 @@ switch ((CNTLR_PHASE) uptr->PHASE) { /* dispatch the current case data_phase: switch (opcode) { /* dispatch the current operation */ - case seek: /* operations that accept parameters */ - case verify: - case address_record: - case read_with_offset: - case load_tio_register: + case Seek: /* operations that accept parameters */ + case Verify: + case Address_Record: + case Read_With_Offset: + case Load_TIO_Register: buffer [mac_cntlr.index++] = fifo_unload (); /* unload the next word from the FIFO */ mac_cntlr.length--; /* count it */ @@ -891,7 +892,7 @@ switch ((CNTLR_PHASE) uptr->PHASE) { /* dispatch the current else { /* all parameters have been received */ uptr->PHASE = end_phase; /* set the end phase */ - if (opcode == read_with_offset) /* a Read With Offset command sets the flag */ + if (opcode == Read_With_Offset) /* a Read With Offset command sets the flag */ ds_io (&ds_dib, ioENF, 0); /* to indicate that offsetting is complete */ start_command (); /* the command is now ready to execute */ @@ -899,10 +900,10 @@ switch ((CNTLR_PHASE) uptr->PHASE) { /* dispatch the current break; - case request_status: /* operations that supply parameters */ - case request_sector_address: - case request_syndrome: - case request_disc_address: + case Request_Status: /* operations that supply parameters */ + case Request_Sector_Address: + case Request_Syndrome: + case Request_Disc_Address: if (mac_cntlr.length) { /* are there more words to return? */ fifo_load (buffer [mac_cntlr.index++]); /* load the next word into the FIFO */ mac_cntlr.length--; /* count it */ @@ -1258,7 +1259,7 @@ unit = GET_S1UNIT (mac_cntlr.spd_unit); /* get the (prepared) un if (unit <= DL_MAXDRIVE) /* is the unit number valid? */ drive_command = (CNTLR_OPCODE) ds_unit [unit].OP; /* get the opcode from the unit that will be used */ else /* the unit is invalid, so the command will not start */ - drive_command = end; /* but the compiler doesn't know this! */ + drive_command = End; /* but the compiler doesn't know this! */ uptr = dl_start_command (&mac_cntlr, ds_unit, DL_MAXDRIVE); /* ask the controller to start the command */ diff --git a/HP2100/hp2100_ipl.c b/HP2100/hp2100_ipl.c index a01b4881..5a5c8cad 100644 --- a/HP2100/hp2100_ipl.c +++ b/HP2100/hp2100_ipl.c @@ -25,6 +25,8 @@ IPLI, IPLO 12875A interprocessor link + 25-Oct-12 JDB Removed DEV_NET to allow restoration of listening ports + 09-May-12 JDB Separated assignments from conditional expressions 10-Feb-12 JDB Deprecated DEVNO in favor of SC Added CARD_INDEX casts to dib.card_index 07-Apr-11 JDB A failed STC may now be retried @@ -187,7 +189,7 @@ DEVICE ipli_dev = { 1, 10, 31, 1, 16, 16, &tmxr_ex, &tmxr_dep, &ipl_reset, &ipl_boot, &ipl_attach, &ipl_detach, - &ipli_dib, DEV_NET | DEV_DISABLE | DEV_DIS | DEV_DEBUG, + &ipli_dib, DEV_DISABLE | DEV_DIS | DEV_DEBUG, 0, ipl_deb, NULL, NULL }; @@ -216,7 +218,7 @@ DEVICE iplo_dev = { 1, 10, 31, 1, 16, 16, &tmxr_ex, &tmxr_dep, &ipl_reset, &ipl_boot, &ipl_attach, &ipl_detach, - &iplo_dib, DEV_NET | DEV_DISABLE | DEV_DIS | DEV_DEBUG, + &iplo_dib, DEV_DISABLE | DEV_DIS | DEV_DEBUG, 0, ipl_deb, NULL, NULL }; @@ -569,61 +571,62 @@ return SCPE_OK; t_stat ipl_attach (UNIT *uptr, char *cptr) { SOCKET newsock; -uint32 i, t, ipa, ipp, oldf; -char *tptr; +uint32 i, t, oldf; +char host[CBUFSIZE], port[CBUFSIZE], hostport[2*CBUFSIZE+3]; +char *tptr = NULL; t_stat r; -r = get_ipaddr (cptr, &ipa, &ipp); -if ((r != SCPE_OK) || (ipp == 0)) - return SCPE_ARG; oldf = uptr->flags; if (oldf & UNIT_ATT) ipl_detach (uptr); if ((sim_switches & SWMASK ('C')) || ((sim_switches & SIM_SW_REST) && (oldf & UNIT_ACTV))) { - if (ipa == 0) - ipa = 0x7F000001; - newsock = sim_connect_sock (ipa, ipp); + r = sim_parse_addr (cptr, host, sizeof(host), "localhost", port, sizeof(port), NULL, NULL); + if ((r != SCPE_OK) || (port[0] == '\0')) + return SCPE_ARG; + sprintf(hostport, "%s%s%s%s%s", strchr(host, ':') ? "[" : "", host, strchr(host, ':') ? "]" : "", host[0] ? ":" : "", port); + newsock = sim_connect_sock (hostport, NULL, NULL); if (newsock == INVALID_SOCKET) return SCPE_IOERR; - printf ("Connecting to IP address %d.%d.%d.%d, port %d\n", - (ipa >> 24) & 0xff, (ipa >> 16) & 0xff, - (ipa >> 8) & 0xff, ipa & 0xff, ipp); + printf ("Connecting to %s\n", hostport); if (sim_log) fprintf (sim_log, - "Connecting to IP address %d.%d.%d.%d, port %d\n", - (ipa >> 24) & 0xff, (ipa >> 16) & 0xff, - (ipa >> 8) & 0xff, ipa & 0xff, ipp); + "Connecting to %s\n", hostport); uptr->flags = uptr->flags | UNIT_ACTV; uptr->LSOCKET = 0; uptr->DSOCKET = newsock; } else { - if (ipa != 0) + r = sim_parse_addr (cptr, host, sizeof(host), NULL, port, sizeof(port), NULL, NULL); + if (r != SCPE_OK) return SCPE_ARG; - newsock = sim_master_sock (ipp); + sprintf(hostport, "%s%s%s%s%s", strchr(host, ':') ? "[" : "", host, strchr(host, ':') ? "]" : "", host[0] ? ":" : "", port); + newsock = sim_master_sock (hostport, &r); + if (r != SCPE_OK) + return r; if (newsock == INVALID_SOCKET) return SCPE_IOERR; - printf ("Listening on port %d\n", ipp); + printf ("Listening on port %s\n", hostport); if (sim_log) - fprintf (sim_log, "Listening on port %d\n", ipp); + fprintf (sim_log, "Listening on port %s\n", hostport); uptr->flags = uptr->flags & ~UNIT_ACTV; uptr->LSOCKET = newsock; uptr->DSOCKET = 0; } uptr->IBUF = uptr->OBUF = 0; uptr->flags = (uptr->flags | UNIT_ATT) & ~(UNIT_ESTB | UNIT_HOLD); -tptr = (char *) malloc (strlen (cptr) + 1); /* get string buf */ +tptr = (char *) malloc (strlen (hostport) + 1); /* get string buf */ if (tptr == NULL) { /* no memory? */ ipl_detach (uptr); /* close sockets */ return SCPE_MEM; } -strcpy (tptr, cptr); /* copy ipaddr:port */ +strcpy (tptr, hostport); /* copy ipaddr:port */ uptr->filename = tptr; /* save */ sim_activate (uptr, POLL_FIRST); /* activate first poll "immediately" */ if (sim_switches & SWMASK ('W')) { /* wait? */ for (i = 0; i < 30; i++) { /* check for 30 sec */ - if ((t = ipl_check_conn (uptr))) /* established? */ + t = ipl_check_conn (uptr); + if (t) /* established? */ break; if ((i % 10) == 0) /* status every 10 sec */ printf ("Waiting for connnection\n"); diff --git a/HP2100/hp2100_mpx.c b/HP2100/hp2100_mpx.c index b61572dd..786f58a4 100644 --- a/HP2100/hp2100_mpx.c +++ b/HP2100/hp2100_mpx.c @@ -25,7 +25,9 @@ MPX 12792C 8-channel multiplexer card + 28-Dec-12 JDB Allow direct attach to the poll unit only when restoring 10-Feb-12 JDB Deprecated DEVNO in favor of SC + Removed DEV_NET to allow restoration of listening port 28-Mar-11 JDB Tidied up signal handling 26-Oct-10 JDB Changed I/O signal handler for revised signal model 25-Nov-08 JDB Revised for new multiplexer library SHOW routines @@ -743,11 +745,14 @@ DEVICE mpx_dev = { &mpx_attach, /* attach routine */ &mpx_detach, /* detach routine */ &mpx_dib, /* device information block */ - DEV_DEBUG | DEV_DISABLE, /* device flags */ + DEV_DEBUG | DEV_DISABLE | DEV_MUX, /* device flags */ 0, /* debug control flags */ mpx_deb, /* debug flag name table */ NULL, /* memory size change routine */ - NULL }; /* logical device name */ + NULL, /* logical device name */ + NULL, /* help routine */ + NULL, /* help attach routine*/ + (void*)&mpx_desc }; /* help context */ /* I/O signal handler. @@ -1926,8 +1931,8 @@ if (fast_binary_read) { /* fast binary read else { /* normal service */ tmxr_poll_tx (&mpx_desc); /* output any accumulated characters */ - if (((buf_avail (iowrite, port) < 2) && /* more to transmit? */ - !(mpx_flags [port] & (FL_WAITACK | FL_XOFF))) || /* and transmission not suspended */ + if ((buf_avail (iowrite, port) < 2) && /* more to transmit? */ + !(mpx_flags [port] & (FL_WAITACK | FL_XOFF)) || /* and transmission not suspended */ tmxr_rqln (&mpx_ldsc [port])) /* or more to receive? */ sim_activate (uptr, uptr->wait); /* reschedule service */ else @@ -2057,6 +2062,9 @@ return SCPE_OK; unit is not allowed, so we first enable the unit, then attach it, then disable it again. Attachment is reported by the "mpx_status" routine below. + A direct attach to the poll unit is only allowed when restoring a previously + saved session. + The Telnet poll service routine is synchronized with the other input polling devices in the simulator to facilitate idling. */ @@ -2065,16 +2073,17 @@ t_stat mpx_attach (UNIT *uptr, char *cptr) { t_stat status = SCPE_OK; -if (uptr != mpx_unit) /* not unit 0? */ - return SCPE_NOATT; /* can't attach */ +if (uptr != mpx_unit /* not unit 0? */ + && (uptr != &mpx_poll || !(sim_switches & SIM_SW_REST))) /* and not restoring the poll unit? */ + return SCPE_NOATT; /* can't attach */ -mpx_poll.flags = mpx_poll.flags & ~UNIT_DIS; /* enable unit */ -status = tmxr_attach (&mpx_desc, &mpx_poll, cptr); /* attach to socket */ -mpx_poll.flags = mpx_poll.flags | UNIT_DIS; /* disable unit */ +mpx_poll.flags = mpx_poll.flags & ~UNIT_DIS; /* enable unit */ +status = tmxr_attach (&mpx_desc, &mpx_poll, cptr); /* attach to socket */ +mpx_poll.flags = mpx_poll.flags | UNIT_DIS; /* disable unit */ if (status == SCPE_OK) { - mpx_poll.wait = POLL_FIRST; /* set up poll */ - sim_activate (&mpx_poll, mpx_poll.wait); /* start poll immediately */ + mpx_poll.wait = POLL_FIRST; /* set up poll */ + sim_activate (&mpx_poll, mpx_poll.wait); /* start poll immediately */ } return status; } diff --git a/HP2100/hp2100_ms.c b/HP2100/hp2100_ms.c index bc24f172..ba160875 100644 --- a/HP2100/hp2100_ms.c +++ b/HP2100/hp2100_ms.c @@ -26,6 +26,7 @@ MS 13181A 7970B 800bpi nine track magnetic tape 13183A 7970E 1600bpi nine track magnetic tape + 09-May-12 JDB Separated assignments from conditional expressions 10-Feb-12 JDB Deprecated DEVNO in favor of SC Added CNTLR_TYPE cast to ms_settype 28-Mar-11 JDB Tidied up signal handling @@ -374,7 +375,7 @@ DEVICE msc_dev = { MS_NUMDR, 10, 31, 1, 8, 8, NULL, NULL, &msc_reset, &msc_boot, &msc_attach, &msc_detach, - &msc_dib, DEV_DISABLE | DEV_DEBUG, + &msc_dib, DEV_DISABLE | DEV_DEBUG | DEV_TAPE, 0, msc_deb, NULL, NULL }; @@ -737,7 +738,8 @@ switch (uptr->FNC) { /* case on function */ fprintf (sim_deb, ">>MSC svc: Unit %d wrote initial gap\n", unum); - if ((st = ms_write_gap (uptr))) { /* write initial gap; error? */ + st = ms_write_gap (uptr); /* write initial gap*/ + if (st != MTSE_OK) { /* error? */ r = ms_map_err (uptr, st); /* map error */ break; /* terminate operation */ } @@ -747,13 +749,15 @@ switch (uptr->FNC) { /* case on function */ fprintf (sim_deb, ">>MSC svc: Unit %d wrote file mark\n", unum); - if ((st = sim_tape_wrtmk (uptr))) /* write tmk, err? */ + st = sim_tape_wrtmk (uptr); /* write tmk */ + if (st != MTSE_OK) /* error? */ r = ms_map_err (uptr, st); /* map error */ msc_sta = STA_EOF; /* set EOF status */ break; case FNC_FSR: /* space forward */ - if ((st = sim_tape_sprecf (uptr, &tbc))) /* space rec fwd, err? */ + st = sim_tape_sprecf (uptr, &tbc); /* space rec fwd */ + if (st != MTSE_OK) /* error? */ r = ms_map_err (uptr, st); /* map error */ if (tbc & 1) msc_sta = msc_sta | STA_ODD; @@ -761,7 +765,8 @@ switch (uptr->FNC) { /* case on function */ break; case FNC_BSR: /* space reverse */ - if ((st = sim_tape_sprecr (uptr, &tbc))) /* space rec rev, err? */ + st = sim_tape_sprecr (uptr, &tbc); /* space rec rev*/ + if (st != MTSE_OK) /* error? */ r = ms_map_err (uptr, st); /* map error */ if (tbc & 1) msc_sta = msc_sta | STA_ODD; @@ -831,7 +836,8 @@ switch (uptr->FNC) { /* case on function */ fprintf (sim_deb, ">>MSC svc: Unit %d wrote initial gap\n", unum); - if ((st = ms_write_gap (uptr))) { /* write initial gap; error? */ + st = ms_write_gap (uptr); /* write initial gap */ + if (st != MTSE_OK) { /* error? */ r = ms_map_err (uptr, st); /* map error */ break; /* terminate operation */ } @@ -855,7 +861,8 @@ switch (uptr->FNC) { /* case on function */ fprintf (sim_deb, ">>MSC svc: Unit %d wrote %d word record\n", unum, ms_ptr / 2); - if ((st = sim_tape_wrrecf (uptr, msxb, ms_ptr))) { /* write, err? */ + st = sim_tape_wrrecf (uptr, msxb, ms_ptr); /* write */ + if (st != MTSE_OK) { r = ms_map_err (uptr, st); /* map error */ break; } @@ -894,7 +901,9 @@ t_stat st; uint32 gap_len = ms_ctype ? GAP_13183 : GAP_13181; /* establish gap length */ uint32 tape_bpi = ms_ctype ? BPI_13183 : BPI_13181; /* establish nominal bpi */ -if ((st = sim_tape_wrgap (uptr, gap_len, tape_bpi))) /* write gap */ +st = sim_tape_wrgap (uptr, gap_len, tape_bpi); /* write gap */ + +if (st != MTSE_OK) return ms_map_err (uptr, st); /* map error if failure */ else return SCPE_OK; @@ -974,7 +983,9 @@ for (i = 0; i < MS_NUMDR; i++) { /* look for write in pro fprintf (sim_deb, ">>MSC rws: Unit %d wrote %d word partial record\n", i, ms_ptr / 2); - if ((st = sim_tape_wrrecf (uptr, msxb, ms_ptr | MTR_ERF))) + st = sim_tape_wrrecf (uptr, msxb, ms_ptr | MTR_ERF); + + if (st != MTSE_OK) ms_map_err (uptr, st); /* discard any error */ ms_ptr = 0; /* clear partial */ diff --git a/HP2100/hp2100_mt.c b/HP2100/hp2100_mt.c index ecdfbf80..f8fa9fd6 100644 --- a/HP2100/hp2100_mt.c +++ b/HP2100/hp2100_mt.c @@ -25,6 +25,7 @@ MT 12559A 3030 nine track magnetic tape + 09-May-12 JDB Separated assignments from conditional expressions 25-Mar-12 JDB Removed redundant MTAB_VUN from "format" MTAB entry 10-Feb-12 JDB Deprecated DEVNO in favor of SC 28-Mar-11 JDB Tidied up signal handling @@ -233,7 +234,7 @@ DEVICE mtc_dev = { 1, 10, 31, 1, 8, 8, NULL, NULL, &mt_reset, NULL, &mtc_attach, &mtc_detach, - &mtc_dib, DEV_DISABLE | DEV_DIS + &mtc_dib, DEV_DISABLE | DEV_DIS | DEV_TAPE }; @@ -495,7 +496,8 @@ switch (mtc_fnc) { /* case on function */ return sim_tape_detach (uptr); /* don't set cch flg */ case FNC_WFM: /* write file mark */ - if ((st = sim_tape_wrtmk (uptr))) /* write tmk, err? */ + st = sim_tape_wrtmk (uptr); /* write tmk */ + if (st != MTSE_OK) /* error? */ r = mt_map_err (uptr, st); /* map error */ mtc_sta = STA_EOF; /* set EOF status */ break; @@ -504,12 +506,14 @@ switch (mtc_fnc) { /* case on function */ break; case FNC_FSR: /* space forward */ - if ((st = sim_tape_sprecf (uptr, &tbc))) /* space rec fwd, err? */ + st = sim_tape_sprecf (uptr, &tbc); /* space rec fwd */ + if (st != MTSE_OK) /* error? */ r = mt_map_err (uptr, st); /* map error */ break; case FNC_BSR: /* space reverse */ - if ((st = sim_tape_sprecr (uptr, &tbc))) /* space rec rev, err? */ + st = sim_tape_sprecr (uptr, &tbc); /* space rec rev */ + if (st != MTSE_OK) /* error? */ r = mt_map_err (uptr, st); /* map error */ break; @@ -558,7 +562,8 @@ switch (mtc_fnc) { /* case on function */ return SCPE_OK; } if (mt_ptr) { /* write buffer */ - if ((st = sim_tape_wrrecf (uptr, mtxb, mt_ptr))) { /* write, err? */ + st = sim_tape_wrrecf (uptr, mtxb, mt_ptr); /* write */ + if (st != MTSE_OK) { /* error? */ r = mt_map_err (uptr, st); /* map error */ break; /* done */ } @@ -627,7 +632,8 @@ t_stat st; if (sim_is_active (&mtc_unit) && /* write in prog? */ (mtc_fnc == FNC_WC) && (mt_ptr > 0)) { /* yes, bad rec */ - if ((st = sim_tape_wrrecf (&mtc_unit, mtxb, mt_ptr | MTR_ERF))) + st = sim_tape_wrrecf (&mtc_unit, mtxb, mt_ptr | MTR_ERF); + if (st != MTSE_OK) mt_map_err (&mtc_unit, st); } diff --git a/HP2100/hp2100_mux.c b/HP2100/hp2100_mux.c index f341a51d..6d13cec8 100644 --- a/HP2100/hp2100_mux.c +++ b/HP2100/hp2100_mux.c @@ -26,6 +26,7 @@ MUX,MUXL,MUXM 12920A terminal multiplexor 10-Feb-12 JDB Deprecated DEVNO in favor of SC + Removed DEV_NET to allow restoration of listening port 28-Mar-11 JDB Tidied up signal handling 26-Oct-10 JDB Changed I/O signal handler for revised signal model 25-Nov-08 JDB Revised for new multiplexer library SHOW routines @@ -437,7 +438,10 @@ DEVICE muxl_dev = { 0, /* debug control flags */ NULL, /* debug flag name table */ NULL, /* memory size change routine */ - NULL }; /* logical device name */ + NULL, /* logical device name */ + NULL, /* help routine */ + NULL, /* help attach routine*/ + NULL }; /* help context */ /* MUXU data structures @@ -511,11 +515,14 @@ DEVICE muxu_dev = { &mux_attach, /* attach routine */ &mux_detach, /* detach routine */ &muxu_dib, /* device information block */ - DEV_DISABLE | DEV_DEBUG, /* device flags */ + DEV_DISABLE | DEV_DEBUG | DEV_MUX, /* device flags */ 0, /* debug control flags */ muxu_deb, /* debug flag name table */ NULL, /* memory size change routine */ - NULL }; /* logical device name */ + NULL, /* logical device name */ + NULL, /* help routine */ + NULL, /* help attach routine*/ + (void*)&mux_desc }; /* help context */ /* MUXC data structures. @@ -574,7 +581,10 @@ DEVICE muxc_dev = { 0, /* debug control flags */ NULL, /* debug flag name table */ NULL, /* memory size change routine */ - NULL }; /* logical device name */ + NULL, /* logical device name */ + NULL, /* help routine */ + NULL, /* help attach routine*/ + NULL }; /* help context */ /* Lower data card I/O signal handler. diff --git a/HP2100/hp2100_stddev.c b/HP2100/hp2100_stddev.c index 9664be58..217c1a89 100644 --- a/HP2100/hp2100_stddev.c +++ b/HP2100/hp2100_stddev.c @@ -26,8 +26,11 @@ PTR 12597A-002 paper tape reader interface PTP 12597A-005 paper tape punch interface TTY 12531C buffered teleprinter interface - CLK 12539C time base generator + TBG 12539C time base generator + 28-Dec-12 JDB Allocate the TBG logical name during power-on reset + 18-Dec-12 MP Now calls sim_activate_time to get remaining poll time + 09-May-12 JDB Separated assignments from conditional expressions 12-Feb-12 JDB Add TBG as a logical name for the CLK device 10-Feb-12 JDB Deprecated DEVNO in favor of SC 28-Mar-11 JDB Tidied up signal handling @@ -96,7 +99,7 @@ idle time. The console poll is guaranteed to run, as the TTY device cannot be disabled. - The clock (time base generator) autocalibrates. If the CLK is set to a ten + The clock (time base generator) autocalibrates. If the TBG is set to a ten millisecond period (e.g., as under RTE), it is synchronized to the console poll. Otherwise (e.g., as under DOS or TSB, which use 100 millisecond periods), it runs asynchronously. If the specified clock frequency is below @@ -391,7 +394,7 @@ DEVICE clk_dev = { NULL, NULL, &clk_reset, NULL, NULL, NULL, &clk_dib, DEV_DISABLE, - 0, NULL, NULL, "TBG" + 0, NULL, NULL, NULL }; @@ -942,7 +945,9 @@ t_stat r; if (tty_mode & TM_PRI) { /* printing? */ c = sim_tt_outcvt (c, TT_GET_MODE (tty_unit[TTO].flags)); if (c >= 0) { /* valid? */ - if ((r = sim_putchar_s (c))) return r; /* output char */ + r = sim_putchar_s (c); /* output char */ + if (r != SCPE_OK) + return r; tty_unit[TTO].pos = tty_unit[TTO].pos + 1; } } @@ -1018,7 +1023,7 @@ int32 sync_poll (POLLMODE poll_mode) int32 poll_time; if (poll_mode == INITIAL) { - poll_time = sim_is_active (&tty_unit[TTI]); + poll_time = sim_activate_time (&tty_unit[TTI]); if (poll_time) return poll_time; @@ -1114,7 +1119,7 @@ while (working_set) { if ((clk_unit.flags & UNIT_DIAG) == 0) /* calibrated? */ if (clk_select == 2) /* 10 msec. interval? */ - clk_tick = sync_poll (INITIAL); /* sync poll */ + clk_tick = sync_poll (INITIAL); /* sync poll */ else sim_rtcn_init (clk_tick, TMR_CLK); /* initialize timer */ @@ -1187,6 +1192,9 @@ if (sim_switches & SWMASK ('P')) { /* initialization reset? clk_error = 0; /* clear error */ clk_select = 0; /* clear select */ clk_ctr = 0; /* clear counter */ + + if (clk_dev.lname == NULL) /* logical name unassigned? */ + clk_dev.lname = strdup ("TBG"); /* allocate and initialize the name */ } IOPRESET (&clk_dib); /* PRESET device (does not use PON) */ diff --git a/HP2100/hp2100_sys.c b/HP2100/hp2100_sys.c index e47687c0..c8681731 100644 --- a/HP2100/hp2100_sys.c +++ b/HP2100/hp2100_sys.c @@ -23,6 +23,7 @@ used in advertising or otherwise to promote the sale, use or other dealings in this Software without prior written authorization from Robert M Supnik. + 09-May-12 JDB Quieted warnings for assignments in conditional expressions 10-Feb-12 JDB Deprecated DEVNO in favor of SC Added hp_setsc, hp_showsc functions to support SC modifier 15-Dec-11 JDB Added DA and dummy DC devices diff --git a/HP2100/hp_disclib.c b/HP2100/hp_disclib.c index 7f69af4c..2a0d3ce2 100644 --- a/HP2100/hp_disclib.c +++ b/HP2100/hp_disclib.c @@ -24,7 +24,10 @@ used in advertising or otherwise to promote the sale, use or other dealings in this Software without prior written authorization from the authors. - 28-Mar-12 JDB First release + 20-Dec-12 JDB sim_is_active() now returns t_bool + 24-Oct-12 JDB Changed CNTLR_OPCODE to title case to avoid name clash + 07-May-12 JDB Corrected end-of-track delay time logic + 02-May-12 JDB First release 09-Nov-11 JDB Created disc controller common library from DS simulator References: @@ -593,8 +596,8 @@ set_timer (cvptr, CLEAR); /* stop the command wait opcode = GET_OPCODE (cvptr->buffer [0]); /* get the opcode from the command */ -if (opcode > last_opcode) /* is the opcode invalid? */ - props = &cmd_props [invalid_opcode]; /* undefined commands clear prior status */ +if (opcode > Last_Opcode) /* is the opcode invalid? */ + props = &cmd_props [Invalid_Opcode]; /* undefined commands clear prior status */ else /* the opcode is potentially valid */ props = &cmd_props [opcode]; /* get the command properties */ @@ -761,8 +764,8 @@ else { /* for an ICD controller uptr = units + unit_limit; /* and we use the indicated unit */ } -if ((props->unit_check && !uptr) || /* if the unit number is checked and is invalid */ - (props->seek_wait && (drive_status (uptr) & DL_S2STOPS))) { /* or if we're waiting for an offline drive */ +if (props->unit_check && !uptr /* if the unit number is checked and is invalid */ + || props->seek_wait && (drive_status (uptr) & DL_S2STOPS)) { /* or if we're waiting for an offline drive */ dl_end_command (cvptr, status_2_error); /* then the command ends with a Status-2 error */ uptr = NULL; /* prevent the command from starting */ } @@ -771,7 +774,7 @@ else if (uptr) { /* otherwise, we have a uptr->wait = cvptr->cmd_time; /* most commands use the command delay */ if (props->unit_access) { /* does the command access the unit? */ - is_seeking = sim_is_active (uptr) != 0; /* see if the unit is busy */ + is_seeking = sim_is_active (uptr); /* see if the unit is busy */ if (is_seeking) /* if a seek is in progress, */ uptr->wait = 0; /* set for no unit activation */ @@ -793,7 +796,7 @@ cvptr->eod = CLEAR; /* clear the end of data switch (cvptr->opcode) { /* dispatch the command */ - case cold_load_read: + case Cold_Load_Read: cvptr->cylinder = 0; /* set the cylinder address to 0 */ cvptr->head = GET_CHEAD (cvptr->buffer [0]); /* set the head */ cvptr->sector = GET_CSECT (cvptr->buffer [0]); /* and sector from the command */ @@ -801,7 +804,7 @@ switch (cvptr->opcode) { /* dispatch the command if (is_seeking) { /* if a seek is in progress, */ uptr->STAT |= DL_S2SC; /* a Seek Check occurs */ cvptr->file_mask = DL_FSPEN; /* enable sparing */ - uptr->OP = read; /* start the read on the seek completion */ + uptr->OP = Read; /* start the read on the seek completion */ uptr->PHASE = start_phase; /* and reset the command phase */ return uptr; /* to allow the seek to complete normally */ } @@ -812,7 +815,7 @@ switch (cvptr->opcode) { /* dispatch the command break; - case seek: + case Seek: cvptr->cylinder = cvptr->buffer [1]; /* get the supplied cylinder */ cvptr->head = GET_HEAD (cvptr->buffer [2]); /* and head */ cvptr->sector = GET_SECTOR (cvptr->buffer [2]); /* and sector addresses */ @@ -826,7 +829,7 @@ switch (cvptr->opcode) { /* dispatch the command break; - case request_status: + case Request_Status: cvptr->buffer [0] = /* set the Status-1 value */ cvptr->spd_unit | SET_S1STAT (cvptr->status); /* into the buffer */ @@ -853,12 +856,12 @@ switch (cvptr->opcode) { /* dispatch the command break; - case request_disc_address: + case Request_Disc_Address: set_address (cvptr, 0); /* return the CHS values in buffer 0-1 */ break; - case request_sector_address: + case Request_Sector_Address: if (unit > unit_limit) /* if the unit number is invalid */ rptr = NULL; /* it does not correspond to a unit */ else /* otherwise, the unit is valid */ @@ -871,7 +874,7 @@ switch (cvptr->opcode) { /* dispatch the command break; - case request_syndrome: + case Request_Syndrome: cvptr->buffer [0] = /* return the Status-1 value in buffer 0 */ cvptr->spd_unit | SET_S1STAT (cvptr->status); @@ -884,7 +887,7 @@ switch (cvptr->opcode) { /* dispatch the command break; - case address_record: + case Address_Record: cvptr->cylinder = cvptr->buffer [1]; /* get the supplied cylinder */ cvptr->head = GET_HEAD (cvptr->buffer [2]); /* and head */ cvptr->sector = GET_SECTOR (cvptr->buffer [2]); /* and sector addresses */ @@ -892,7 +895,7 @@ switch (cvptr->opcode) { /* dispatch the command break; - case set_file_mask: + case Set_File_Mask: cvptr->file_mask = GET_FMASK (cvptr->buffer [0]); /* get the supplied file mask */ if (cvptr->type == MAC) /* if this is a MAC controller, */ @@ -900,14 +903,14 @@ switch (cvptr->opcode) { /* dispatch the command break; - case initialize: + case Initialize: if (uptr) /* if the unit is valid, */ cvptr->spd_unit |= /* merge the SPD flags */ SET_S1SPD (GET_SPD (cvptr->buffer [0])); /* from the command word */ break; - case verify: + case Verify: cvptr->verify_count = cvptr->buffer [1]; /* get the supplied sector count */ break; @@ -1077,35 +1080,35 @@ switch ((CNTLR_PHASE) uptr->PHASE) { /* dispatch the phase */ case start_phase: switch (opcode) { /* dispatch the current operation */ - case recalibrate: - case seek: + case Recalibrate: + case Seek: if (start_seek (cvptr, uptr, opcode, end_phase) /* start the seek; if it succeeded, */ && (cvptr->type == MAC)) /* and this a MAC controller, */ dl_idle_controller (cvptr); /* then go idle until it completes */ break; - case cold_load_read: - if (start_seek (cvptr, uptr, read, start_phase)) /* start the seek; did it succeed? */ + case Cold_Load_Read: + if (start_seek (cvptr, uptr, Read, start_phase)) /* start the seek; did it succeed? */ cvptr->file_mask = DL_FSPEN; /* set sparing enabled now */ break; - case read: - case read_with_offset: - case read_without_verify: + case Read: + case Read_With_Offset: + case Read_Without_Verify: cvptr->length = DL_WPSEC; /* transfer just the data */ result = start_read (cvptr, uptr); /* start the sector read */ break; - case read_full_sector: + case Read_Full_Sector: cvptr->length = DL_WPFSEC; /* transfer the header/data/trailer */ result = start_read (cvptr, uptr); /* start the sector read */ break; - case verify: + case Verify: cvptr->length = 0; /* no data transfer needed */ result = start_read (cvptr, uptr); /* start the sector read */ @@ -1117,29 +1120,29 @@ switch ((CNTLR_PHASE) uptr->PHASE) { /* dispatch the phase */ break; - case write: - case initialize: + case Write: + case Initialize: cvptr->length = DL_WPSEC; /* transfer just the data */ start_write (cvptr, uptr); /* start the sector write */ break; - case write_full_sector: + case Write_Full_Sector: cvptr->length = DL_WPFSEC; /* transfer the header/data/trailer */ start_write (cvptr, uptr); /* start the sector write */ break; - case request_status: - case request_sector_address: - case clear: - case address_record: - case request_syndrome: - case set_file_mask: - case load_tio_register: - case request_disc_address: - case end: - case wakeup: + case Request_Status: + case Request_Sector_Address: + case Clear: + case Address_Record: + case Request_Syndrome: + case Set_File_Mask: + case Load_TIO_Register: + case Request_Disc_Address: + case End: + case Wakeup: dl_service_controller (cvptr, uptr); /* the controller service handles these */ break; @@ -1153,13 +1156,13 @@ switch ((CNTLR_PHASE) uptr->PHASE) { /* dispatch the phase */ case data_phase: switch (opcode) { /* dispatch the current operation */ - case read: - case read_full_sector: - case read_with_offset: - case read_without_verify: - case write: - case write_full_sector: - case initialize: + case Read: + case Read_Full_Sector: + case Read_With_Offset: + case Read_Without_Verify: + case Write: + case Write_Full_Sector: + case Initialize: break; /* data transfers are handled by the caller */ @@ -1173,8 +1176,8 @@ switch ((CNTLR_PHASE) uptr->PHASE) { /* dispatch the phase */ case end_phase: switch (opcode) { /* dispatch the operation command */ - case recalibrate: - case seek: + case Recalibrate: + case Seek: if (cvptr->type == ICD) /* is this an ICD controller? */ dl_end_command (cvptr, drive_attention); /* seeks end with Drive Attention status */ else /* if not an ICD controller, */ @@ -1182,22 +1185,22 @@ switch ((CNTLR_PHASE) uptr->PHASE) { /* dispatch the phase */ break; - case read: - case read_full_sector: - case read_with_offset: + case Read: + case Read_Full_Sector: + case Read_With_Offset: end_read (cvptr, uptr); /* end the sector read */ break; - case read_without_verify: + case Read_Without_Verify: if (cvptr->sector == 0) /* have we reached the end of the track? */ - uptr->OP = read; /* begin verifying the next time */ + uptr->OP = Read; /* begin verifying the next time */ end_read (cvptr, uptr); /* end the sector read */ break; - case verify: + case Verify: cvptr->verify_count = /* decrement the count */ (cvptr->verify_count - 1) & DMASK; /* modulo 65536 */ @@ -1208,16 +1211,16 @@ switch ((CNTLR_PHASE) uptr->PHASE) { /* dispatch the phase */ break; - case write: - case write_full_sector: - case initialize: + case Write: + case Write_Full_Sector: + case Initialize: result = end_write (cvptr, uptr); /* end the sector write */ break; - case request_status: - case request_sector_address: - case request_disc_address: + case Request_Status: + case Request_Sector_Address: + case Request_Disc_Address: dl_service_controller (cvptr, uptr); /* the controller service handles these */ break; @@ -1277,33 +1280,33 @@ switch ((CNTLR_PHASE) uptr->PHASE) { /* dispatch the phase */ case start_phase: case end_phase: switch (opcode) { /* dispatch the current operation */ - case request_status: + case Request_Status: dl_end_command (cvptr, cvptr->status); /* the command completes with no status change */ break; - case clear: + case Clear: dl_clear_controller (cvptr, uptr, soft_clear); /* clear the controller */ dl_end_command (cvptr, normal_completion); /* the command is complete */ break; - case request_sector_address: - case address_record: - case request_syndrome: - case set_file_mask: - case load_tio_register: - case request_disc_address: + case Request_Sector_Address: + case Address_Record: + case Request_Syndrome: + case Set_File_Mask: + case Load_TIO_Register: + case Request_Disc_Address: dl_end_command (cvptr, normal_completion); /* the command is complete */ break; - case end: + case End: dl_idle_controller (cvptr); /* the command completes with the controller idle */ break; - case wakeup: + case Wakeup: dl_end_command (cvptr, unit_available); /* the command completes with Unit Available status */ break; @@ -1318,11 +1321,11 @@ switch ((CNTLR_PHASE) uptr->PHASE) { /* dispatch the phase */ case data_phase: switch (opcode) { /* dispatch the current operation */ - case seek: - case verify: - case address_record: - case read_with_offset: - case load_tio_register: + case Seek: + case Verify: + case Address_Record: + case Read_With_Offset: + case Load_TIO_Register: if (cvptr->length > 1) /* at least one more parameter to input? */ set_timer (cvptr, SET); /* restart the timer for the next parameter */ else /* this is the last one */ @@ -1330,10 +1333,10 @@ switch ((CNTLR_PHASE) uptr->PHASE) { /* dispatch the phase */ break; - case request_status: - case request_sector_address: - case request_syndrome: - case request_disc_address: + case Request_Status: + case Request_Sector_Address: + case Request_Syndrome: + case Request_Disc_Address: if (cvptr->length > 0) /* at least one more to parameter output? */ set_timer (cvptr, SET); /* restart the timer for the next parameter */ else /* this is the last one */ @@ -1504,8 +1507,8 @@ for (unit = 0; unit < unit_count; unit++) { /* loop through the unit if (!(uptr->flags & UNIT_DIS)) { /* is the unit enabled? */ if (clear_type == hard_clear /* a hard clear cancels */ - && uptr->OP != seek /* only if not seeking */ - && uptr->OP != recalibrate) /* or recalibrating */ + && uptr->OP != Seek /* only if not seeking */ + && uptr->OP != Recalibrate) /* or recalibrating */ sim_cancel (uptr); /* cancel the service */ uptr->STAT &= ~DL_S2CPS; /* do "Controller Preset" for the unit */ @@ -1596,7 +1599,7 @@ return SCPE_OK; CNTLR_CLASS dl_classify (CNTLR_VARS cntlr) { if (cntlr.type <= last_type /* if the controller type is legal */ - && cntlr.opcode <= last_opcode /* and the opcode is legal */ + && cntlr.opcode <= Last_Opcode /* and the opcode is legal */ && cmd_props [cntlr.opcode].valid [cntlr.type]) /* and is defined for this controller, */ return cmd_props [cntlr.opcode].classification; /* then return the command classification */ else /* the type or opcode is illegal */ @@ -1614,7 +1617,7 @@ else /* the type or opcode is const char *dl_opcode_name (CNTLR_TYPE controller, CNTLR_OPCODE opcode) { if (controller <= last_type /* if the controller type is legal */ - && opcode <= last_opcode /* and the opcode is legal */ + && opcode <= Last_Opcode /* and the opcode is legal */ && cmd_props [opcode].valid [controller]) /* and is defined for this controller, */ return opcode_name [opcode]; /* then return the opcode name */ else /* the type or opcode is illegal, */ @@ -1775,7 +1778,7 @@ if (cvptr->eod == SET) { /* is the end of data in return SCPE_OK; } -if (opcode == read_full_sector) { /* are we starting a Read Full Sector command? */ +if (opcode == Read_Full_Sector) { /* are we starting a Read Full Sector command? */ if (cvptr->type == ICD) /* is this an ICD controller? */ cvptr->buffer [0] = 0100377; /* ICD does not support ECC */ else @@ -1788,7 +1791,7 @@ if (opcode == read_full_sector) { /* are we starting a Rea else { /* it's another read command */ offset = 0; /* data starts at the beginning */ - verify = (opcode != read_without_verify); /* set for address verification unless it's a RWV */ + verify = (opcode != Read_Without_Verify); /* set for address verification unless it's a RWV */ } if (! position_sector (cvptr, uptr, verify)) /* position the sector */ @@ -1817,28 +1820,61 @@ return SCPE_OK; /* the read was successf On entry, the end-of-data flag is checked. If it is set, the current read is completed. Otherwise, the command phase is reset to start the next sector, - and the disc service is scheduled to allow for the intersector delay. + and the disc service is set to allow for the intersector delay. Implementation notes: - 1. The intersector time is required to allow the ICD interface to set the - end-of-data flag before the next sector begins. The CPU must have enough - time to receive the last byte of the current sector and then unaddress - the disc controller before the first byte of the next sector is sent. If - the time is not long enough, the sector address will be incremented twice - (e.g., a 128-word read of sector 0 will terminate with sector 2 as the - next sector instead of sector 1). + 1. The CPU indicates the end of a read data transfer to an ICD controller by + untalking the drive. The untalk is done by the driver as soon as the + DCPC completion interrupt is processed. However, the time from the final + DCPC transfer through driver entry to the point where the untalk is + asserted on the bus varies from 80 instructions (RTE-6/VM with OS + microcode and the buffer in the system map) to 152 instructions (RTE-IVB + with the buffer in the user map). The untalk must occur before the start + of the next sector, or the drive will begin the data transfer. + + Normally, this is not a problem, as the driver clears the FIFO of any + received data after DCPC completion. However, if the read terminates + after the last sector of a track, and accessing the next sector would + require an intervening seek, and the file mask disables auto-seeking or + an enabled seek would move the positioner beyond the drive limits, then + the controller will indicate an End of Cylinder error if the untalk does + not arrive before the seek is initiated. + + The RTE driver (DVA32) and various utilities that manage the disc + directly (e.g., SWTCH) do not appear to account for these bogus errors, + so the ICD controller hardware must avoid them in some unknown manner. + We work around the issue by extending the intersector delay to allow time + for a potential untalk whenever the next access would otherwise fail. + + Note that this issue does not occur with writes because DCPC completion + asserts EOI concurrently with the final data byte to terminate the + command. */ static void end_read (CVPTR cvptr, UNIT *uptr) { +uint32 limit; + if (cvptr->eod == SET) /* is the end of data indicated? */ dl_end_command (cvptr, normal_completion); /* complete the command */ else { /* reading continues */ uptr->PHASE = start_phase; /* reset to the start phase */ uptr->wait = cvptr->sector_time; /* delay for the intersector time */ + + if (cvptr->eoc == SET && cvptr->type == ICD) { /* seek will be required and controller is ICD? */ + if (!(cvptr->file_mask & DL_FAUTSK)) /* if auto-seek is disabled */ + limit = cvptr->cylinder; /* then the limit is the current cylinder */ + else if (cvptr->file_mask & DL_FDECR) /* else if enabled and decremental seek */ + limit = 0; /* then the limit is cylinder 0 */ + else /* else the enabled limit is the last cylinder */ + limit = drive_props [GET_MODEL (uptr->flags)].cylinders; + + if (cvptr->cylinder == limit) /* is positioner at the limit? */ + uptr->wait = cvptr->eot_time; /* seek will fail; delay to allow CPU to untalk */ + } } return; @@ -1877,10 +1913,10 @@ return; static void start_write (CVPTR cvptr, UNIT *uptr) { -const t_bool verify = (CNTLR_OPCODE) uptr->OP == write; /* only Write verifies the sector address */ +const t_bool verify = (CNTLR_OPCODE) uptr->OP == Write; /* only Write verifies the sector address */ -if ((uptr->flags & UNIT_WPROT) || /* is the unit write protected, */ - (!verify && !(uptr->flags & UNIT_FMT))) /* or is formatting required but not enabled? */ +if ((uptr->flags & UNIT_WPROT) /* is the unit write protected, */ + || !verify && !(uptr->flags & UNIT_FMT)) /* or is formatting required but not enabled? */ dl_end_command (cvptr, status_2_error); /* terminate the write with an error */ else if (position_sector (cvptr, uptr, verify)) { /* writing is permitted; position the sector */ @@ -1925,7 +1961,7 @@ static t_stat end_write (CVPTR cvptr, UNIT *uptr) uint32 count; uint16 pad; const CNTLR_OPCODE opcode = (CNTLR_OPCODE) uptr->OP; -const uint32 offset = (opcode == write_full_sector ? 3 : 0); +const uint32 offset = (opcode == Write_Full_Sector ? 3 : 0); if (uptr->flags & UNIT_UNLOAD) { /* if the drive is not ready, */ dl_end_command (cvptr, access_not_ready); /* terminate the command with an error */ @@ -1964,12 +2000,12 @@ return SCPE_OK; /* Position the disc image file at the current sector. - The image file is positioned at the byte address corresponding to the - controller's current cylinder, head, and sector address. Positioning may - involve an auto-seek if a prior read or write addressed the final sector in a - cylinder. If a seek is initiated or an error is detected, the routine - returns FALSE to indicate that the positioning was not performed. If the - file was positioned, the routine returns TRUE. + The image file is positioned at the byte address corresponding to the drive's + current cylinder and the controller's current head and sector addresses. + Positioning may involve an auto-seek if a prior read or write addressed the + final sector of a cylinder. If a seek is initiated or an error is detected, + the routine returns FALSE to indicate that the positioning was not performed. + If the file was positioned, the routine returns TRUE. On entry, if the controller's end-of-cylinder flag is set, a prior read or write addressed the final sector in the current cylinder. If the file mask @@ -1983,21 +2019,23 @@ return SCPE_OK; seek completion and the command state unchanged. When the service is reentered, the read or write will continue on the new cylinder. - If the EOC flag was not set, the drive position is checked against the - controller position. If they are different (as may occur with an Address - Record command that specified a different location than the last Seek - command), a seek is started to the correct cylinder, and the routine returns - with the disc service scheduled for seek completion as above. + If the EOC flag was not set, the drive's position is checked against the + controller's position if address verification is requested. If they are + different (as may occur with an Address Record command that specified a + different location than the last Seek command), a seek is started to the + correct cylinder, and the routine returns with the disc service scheduled for + seek completion as above. - If the drive and controller positions agree, the controller CHS address is - validated against the drive limits. If they are invalid, Seek Check status - is set, and the command is terminated with an error. + If the drive and controller positions agree or verification is not requested, + the CHS addresses are validated against the drive limits. If they are + invalid, Seek Check status is set, and the command is terminated with an + error. - If the address is valid, the drive is checked to ensure that it is ready for - positioning. If it is, the the byte offset in the image file is calculated - from the CHS address, and the file is positioned. The disc service is - scheduled to begin the data transfer, and the routine returns TRUE to - indicate that the file position was set. + If the addresses are valid, the drive is checked to ensure that it is ready + for positioning. If it is, the the byte offset in the image file is + calculated from the CHS address, and the file is positioned. The disc + service is scheduled to begin the data transfer, and the routine returns TRUE + to indicate that the file position was set. Implementation notes: @@ -2164,7 +2202,7 @@ if (uptr->flags & UNIT_UNLOAD) { /* are the heads unloade return FALSE; /* as the drive was not ready */ } -if ((CNTLR_OPCODE) uptr->OP == recalibrate) /* is the unit recalibrating? */ +if ((CNTLR_OPCODE) uptr->OP == Recalibrate) /* is the unit recalibrating? */ target_cylinder = 0; /* seek to cylinder 0 and don't reset the EOC flag */ else { /* it's a Seek command or an auto-seek request */ diff --git a/HP2100/hp_disclib.h b/HP2100/hp_disclib.h index 315fc6ec..fb5d6ef8 100644 --- a/HP2100/hp_disclib.h +++ b/HP2100/hp_disclib.h @@ -24,7 +24,9 @@ used in advertising or otherwise to promote the sale, use or other dealings in this Software without prior written authorization from the authors. - 30-Mar-12 JDB First release + 24-Oct-12 JDB Changed CNTLR_OPCODE to title case to avoid name clash + 07-May-12 JDB Added end-of-track delay time as a controller variable + 02-May-12 JDB First release 09-Nov-11 JDB Created disc controller common library from DS simulator @@ -53,6 +55,7 @@ /* Default controller times */ +#define DL_EOT_TIME 160 /* end-of-track delay time */ #define DL_SEEK_TIME 100 /* seek delay time (per cylinder) */ #define DL_SECTOR_TIME 27 /* intersector delay time */ #define DL_CMD_TIME 3 /* command start delay time */ @@ -204,29 +207,29 @@ typedef enum { /* Controller opcodes */ typedef enum { - cold_load_read = 000, - recalibrate = 001, - seek = 002, - request_status = 003, - request_sector_address = 004, - read = 005, - read_full_sector = 006, - verify = 007, - write = 010, - write_full_sector = 011, - clear = 012, - initialize = 013, - address_record = 014, - request_syndrome = 015, - read_with_offset = 016, - set_file_mask = 017, - invalid_opcode = 020, - read_without_verify = 022, - load_tio_register = 023, - request_disc_address = 024, - end = 025, - wakeup = 026, - last_opcode = wakeup /* last valid opcode */ + Cold_Load_Read = 000, + Recalibrate = 001, + Seek = 002, + Request_Status = 003, + Request_Sector_Address = 004, + Read = 005, + Read_Full_Sector = 006, + Verify = 007, + Write = 010, + Write_Full_Sector = 011, + Clear = 012, + Initialize = 013, + Address_Record = 014, + Request_Syndrome = 015, + Read_With_Offset = 016, + Set_File_Mask = 017, + Invalid_Opcode = 020, + Read_Without_Verify = 022, + Load_TIO_Register = 023, + Request_Disc_Address = 024, + End = 025, + Wakeup = 026, + Last_Opcode = Wakeup /* last valid opcode */ } CNTLR_OPCODE; #define DL_OPCODE_MASK 037 @@ -330,6 +333,7 @@ typedef struct { uint32 index; /* data buffer current index */ uint32 length; /* data buffer valid length */ UNIT *aux; /* MAC auxiliary units (controller and timer) */ + int32 eot_time; /* end-of-track read delay time */ int32 seek_time; /* per-cylinder seek delay time */ int32 sector_time; /* intersector delay time */ int32 cmd_time; /* command response time */ @@ -350,11 +354,11 @@ typedef CNTLR_VARS *CVPTR; /* pointer to controller */ #define CNTLR_INIT(ctype,bufptr,auxptr) \ - (ctype), cntlr_idle, end, normal_completion, \ + (ctype), cntlr_idle, End, normal_completion, \ CLEAR, CLEAR, \ 0, 0, 0, 0, 0, 0, 0, 0, \ (bufptr), 0, 0, (auxptr), \ - DL_SEEK_TIME, DL_SECTOR_TIME, \ + DL_EOT_TIME, DL_SEEK_TIME, DL_SECTOR_TIME, \ DL_CMD_TIME, DL_DATA_TIME, DL_WAIT_TIME diff --git a/I1401/i1401_cd.c b/I1401/i1401_cd.c index 7bd64b70..255dccd5 100644 --- a/I1401/i1401_cd.c +++ b/I1401/i1401_cd.c @@ -398,7 +398,7 @@ static const unsigned char boot_rom[] = { t_stat cdr_boot (int32 unitno, DEVICE *dptr) { -int32 i; +size_t i; extern int32 saved_IS; for (i = 0; i < CDR_WIDTH; i++) /* clear buffer */ diff --git a/I1401/i1401_cpu.c b/I1401/i1401_cpu.c index fdc787bd..61aaf155 100644 --- a/I1401/i1401_cpu.c +++ b/I1401/i1401_cpu.c @@ -197,11 +197,8 @@ int32 hst_lnt = 0; /* history length */ InstHistory *hst = NULL; /* instruction history */ t_bool conv_old = 0; /* old conversions */ -extern int32 sim_int_char; extern int32 sim_emax; extern t_value *sim_eval; -extern FILE *sim_deb; -extern uint32 sim_brk_types, sim_brk_dflt, sim_brk_summ; /* breakpoint info */ t_stat cpu_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw); t_stat cpu_dep (t_value val, t_addr addr, UNIT *uptr, int32 sw); @@ -229,8 +226,6 @@ extern t_stat inq_io (int32 flag, int32 mod); extern t_stat mt_io (int32 unit, int32 flag, int32 mod); extern t_stat dp_io (int32 fnc, int32 flag, int32 mod); extern t_stat mt_func (int32 unit, int32 flag, int32 mod); -extern t_stat sim_activate (UNIT *uptr, int32 delay); -extern t_stat fprint_sym (FILE *of, t_addr addr, t_value *val, UNIT *uptr, int32 sw); /* CPU data structures @@ -1904,8 +1899,6 @@ char *cptr = (char *) desc; t_value sim_eval[MAX_L + 1]; t_stat r; InstHistory *h; -extern t_stat fprint_sym (FILE *ofile, t_addr addr, t_value *val, - UNIT *uptr, int32 sw); if (hst_lnt == 0) /* enabled? */ return SCPE_NOFNC; diff --git a/I1401/i1401_mt.c b/I1401/i1401_mt.c index df7b8574..57a7f436 100644 --- a/I1401/i1401_mt.c +++ b/I1401/i1401_mt.c @@ -113,7 +113,6 @@ extern uint8 M[]; /* memory */ extern int32 ind[64]; extern int32 BS, iochk; extern UNIT cpu_unit; -extern FILE *sim_deb; t_stat mt_reset (DEVICE *dptr); t_stat mt_boot (int32 unitno, DEVICE *dptr); @@ -469,7 +468,6 @@ return SCPE_OK; t_stat mt_boot (int32 unitno, DEVICE *dptr) { extern int32 saved_IS; -extern int32 sim_switches; if ((sim_switches & SWMASK ('N')) == 0) /* unless -n */ sim_tape_rewind (&mt_unit[unitno]); /* force rewind */ diff --git a/I1620/i1620_cpu.c b/I1620/i1620_cpu.c index 49b02106..5ef99843 100644 --- a/I1620/i1620_cpu.c +++ b/I1620/i1620_cpu.c @@ -131,11 +131,6 @@ int32 hst_lnt = 0; /* history length */ InstHistory *hst = NULL; /* instruction history */ uint8 ind[NUM_IND] = { 0 }; /* indicators */ -extern int32 sim_int_char; -extern int32 sim_interval; -extern uint32 sim_brk_types, sim_brk_dflt, sim_brk_summ; /* breakpoint info */ -extern FILE *sim_log; - t_stat cpu_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw); t_stat cpu_dep (t_value val, t_addr addr, UNIT *uptr, int32 sw); t_stat cpu_reset (DEVICE *dptr); diff --git a/I1620/i1620_pt.c b/I1620/i1620_pt.c index 42a1ac63..88323ade 100644 --- a/I1620/i1620_pt.c +++ b/I1620/i1620_pt.c @@ -348,7 +348,7 @@ return SCPE_OK; /* Bootstrap routine */ -const static uint8 boot_rom[] = { +static const uint8 boot_rom[] = { 4, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* NOP */ 3, 6, 0, 0, 0, 3, 1, 0, 0, 3, 0, 0, /* RNPT 31 */ 2, 5, 0, 0, 0, 7, 1, 0, 0, 0, 0, 0, /* TD 71,loc */ @@ -363,7 +363,7 @@ const static uint8 boot_rom[] = { t_stat ptr_boot (int32 unitno, DEVICE *dptr) { -int32 i; +size_t i; extern uint32 saved_PC; for (i = 0; i < BOOT_LEN; i++) diff --git a/I7094/i7094_cd.c b/I7094/i7094_cd.c index cbdcf458..d0ad6870 100644 --- a/I7094/i7094_cd.c +++ b/I7094/i7094_cd.c @@ -88,7 +88,6 @@ t_stat cd_attach (UNIT *uptr, char *cptr); t_stat cd_set_mode (UNIT *uptr, int32 val, char *cptr, void *desc); char colbin_to_bcd (uint32 cb); -extern int32 sim_switches; extern uint32 PC; extern uint32 ind_ioc; extern char bcd_to_ascii_a[64]; diff --git a/I7094/i7094_com.c b/I7094/i7094_com.c index 8f0d4e7c..cacb10ee 100644 --- a/I7094/i7094_com.c +++ b/I7094/i7094_com.c @@ -183,10 +183,10 @@ uint32 com_chob_v = 0; /* valid flag */ t_uint64 com_buf[COM_BUFSIZ]; /* channel buffer */ LISTHD com_free; /* free list */ uint32 com_not_ret[COM_TLINES] = { 0 }; /* chars not returned */ -LISTHD com_inpq[COM_TLINES] = { 0 }; /* input queues */ -LISTHD com_outq[COM_TLINES] = { 0 }; /* output queues */ +LISTHD com_inpq[COM_TLINES] = { {0} }; /* input queues */ +LISTHD com_outq[COM_TLINES] = { {0} }; /* output queues */ LISTENT com_pkt[COM_PKTSIZ]; /* character packets */ -TMLN com_ldsc[COM_MLINES] = { 0 }; /* line descriptors */ +TMLN com_ldsc[COM_MLINES] = { {0} }; /* line descriptors */ TMXR com_desc = { COM_MLINES, 0, 0, com_ldsc }; /* mux descriptor */ /* Even parity truth table */ @@ -348,7 +348,7 @@ DEVICE com_dev = { 3, 10, 31, 1, 16, 8, &tmxr_ex, &tmxr_dep, &com_reset, NULL, &com_attach, &com_detach, - &com_dib, DEV_NET | DEV_DIS + &com_dib, DEV_MUX | DEV_DIS }; /* COML data structures diff --git a/I7094/i7094_cpu.c b/I7094/i7094_cpu.c index 4dbd5882..54d51429 100644 --- a/I7094/i7094_cpu.c +++ b/I7094/i7094_cpu.c @@ -211,11 +211,6 @@ extern uint32 ch_sta[NUM_CHAN]; extern uint32 ch_flags[NUM_CHAN]; extern DEVICE mt_dev[NUM_CHAN]; extern DEVICE ch_dev[NUM_CHAN]; -extern FILE *sim_deb; -extern int32 sim_int_char; -extern int32 sim_interval; -extern int32 sim_switches; -extern uint32 sim_brk_types, sim_brk_dflt, sim_brk_summ; /* breakpoint info */ /* Forward and external declarations */ @@ -2406,8 +2401,6 @@ t_stat cpu_fprint_one_inst (FILE *st, uint32 pc, uint32 rpt, uint32 ea, { int32 ch; t_value sim_eval; -extern t_stat fprint_sym (FILE *ofile, t_addr addr, t_value *val, - UNIT *uptr, int32 sw); sim_eval = ir; if (pc & HIST_PC) { /* instruction? */ diff --git a/I7094/i7094_io.c b/I7094/i7094_io.c index 391debfa..dae1d2b0 100644 --- a/I7094/i7094_io.c +++ b/I7094/i7094_io.c @@ -88,7 +88,6 @@ extern DEVICE mt_dev[NUM_CHAN]; extern DEVICE drm_dev; extern DEVICE dsk_dev; extern DEVICE com_dev; -extern uint32 sim_brk_summ; t_stat ch_reset (DEVICE *dptr); t_stat ch6_svc (UNIT *uptr); @@ -111,7 +110,6 @@ t_stat ch9_wr_getw (uint32 ch); void ch9_eval_int (uint32 ch, uint32 iflags); DEVICE *ch_map_flags (uint32 ch, int32 fl); -extern CTAB *sim_vm_cmd; extern t_stat ch_bkpt (uint32 ch, uint32 clc); const uint32 col_masks[12] = { /* row 9,8,..,0,11,12 */ diff --git a/I7094/i7094_mt.c b/I7094/i7094_mt.c index dddf2531..86c22bab 100644 --- a/I7094/i7094_mt.c +++ b/I7094/i7094_mt.c @@ -72,7 +72,6 @@ static const char *tape_stat[] = { extern uint32 PC; extern uint32 cpu_model; extern uint32 ind_ioc; -extern FILE *sim_deb; extern const char *sel_name[]; t_stat mt_chsel (uint32 ch, uint32 sel, uint32 unit); @@ -368,7 +367,7 @@ DEVICE mt_dev[NUM_CHAN] = { MT_NUMDR + 1, 10, 31, 1, 8, 8, NULL, NULL, &mt_reset, &mt_boot, &mt_attach, &sim_tape_detach, - &mt_dib, DEV_DEBUG + &mt_dib, DEV_DEBUG | DEV_TAPE }, { "MTB", mtb_unit, mtb_reg, mt_mod, diff --git a/Ibm1130/ibm1130_cpu.c b/Ibm1130/ibm1130_cpu.c index d35bbcbd..9910f586 100644 --- a/Ibm1130/ibm1130_cpu.c +++ b/Ibm1130/ibm1130_cpu.c @@ -222,9 +222,7 @@ t_stat cpu_set_type (UNIT *uptr, int32 value, char *cptr, void *desc); void calc_ints (void); extern t_stat ts_wr (int32 data, int32 addr, int32 access); -extern t_stat detach_cmd (int32 flags, char *cptr); extern UNIT cr_unit; -extern int32 sim_switches; #ifdef ENABLE_BACKTRACE static void archive_backtrace(char *inst); @@ -466,8 +464,6 @@ static char *xio_funcs[] = { t_stat sim_instr (void) { - extern int32 sim_interval; - extern UNIT *sim_clock_queue; int32 i, eaddr, INDIR, IR, F, DSPLC, word2, oldval, newval, src, src2, dst, abit, xbit; int32 iocc_addr, iocc_op, iocc_dev, iocc_func, iocc_mod; char msg[50]; @@ -516,7 +512,7 @@ t_stat sim_instr (void) #endif /* ifdef GUI_SUPPORT */ if (sim_interval <= 0) { /* any events timed out? */ - if (sim_clock_queue != NULL) { + if (sim_clock_queue != QUEUE_LIST_END) { if ((status = sim_process_event()) != 0) reason = simh_status_to_stopcode(status); @@ -768,7 +764,7 @@ t_stat sim_instr (void) CCC--; } C = (CCC != 0); - WriteIndex(TAG, ReadIndex(TAG) & 0xFF00 | CCC); /* put 6 bits back into low byte of index register */ + WriteIndex(TAG, (ReadIndex(TAG) & 0xFF00) | CCC); /* put 6 bits back into low byte of index register */ break; } /* if TAG == 0, fall through and treat like normal shift SLT */ @@ -814,8 +810,8 @@ t_stat sim_instr (void) while (CCC > 0) { xbit = (ACC & 0x0001) << 15; abit = (ACC & 0x8000); - ACC = (ACC >> 1) & 0x7FFF | abit; - EXT = (EXT >> 1) & 0x7FFF | xbit; + ACC = ((ACC >> 1) & 0x7FFF) | abit; + EXT = ((EXT >> 1) & 0x7FFF) | xbit; CCC--; } break; @@ -824,8 +820,8 @@ t_stat sim_instr (void) while (CCC > 0) { abit = (EXT & 0x0001) << 15; xbit = (ACC & 0x0001) << 15; - ACC = (ACC >> 1) & 0x7FFF | abit; - EXT = (EXT >> 1) & 0x7FFF | xbit; + ACC = ((ACC >> 1) & 0x7FFF) | abit; + EXT = ((EXT >> 1) & 0x7FFF) | xbit; CCC--; } break; diff --git a/Ibm1130/ibm1130_cr.c b/Ibm1130/ibm1130_cr.c index cc01d941..df9c19b3 100644 --- a/Ibm1130/ibm1130_cr.c +++ b/Ibm1130/ibm1130_cr.c @@ -349,7 +349,6 @@ way to solve the problem, the other is to keep DSW up-to-date all the time). #define ENABLE_PHYSICAL_CARD_READER_SUPPORT -extern int32 sim_switches; extern UNIT cpu_unit; static t_stat cr_svc (UNIT *uptr); diff --git a/Ibm1130/ibm1130_disk.c b/Ibm1130/ibm1130_disk.c index 4b776470..f74cbcc6 100644 --- a/Ibm1130/ibm1130_disk.c +++ b/Ibm1130/ibm1130_disk.c @@ -39,8 +39,6 @@ commands may NOT be accurate. This should probably be fixed. #define TRACE_DMS_IO /* define to enable debug of DMS phase IO */ #ifdef TRACE_DMS_IO -extern int32 sim_switches; -extern int32 sim_quiet; static int trace_dms = 0; static void tracesector (int iswrite, int nwords, int addr, int sector); static t_stat where_cmd (int32 flag, char *ptr); diff --git a/Ibm1130/ibm1130_gui.c b/Ibm1130/ibm1130_gui.c index 765c2214..0e32e3e5 100644 --- a/Ibm1130/ibm1130_gui.c +++ b/Ibm1130/ibm1130_gui.c @@ -93,8 +93,8 @@ DEVICE console_dev = { /* reset for the "console" display device */ extern char *read_line (char *cptr, int size, FILE *stream); -extern FILE *sim_log; extern DEVICE *find_unit (char *cptr, UNIT **uptr); +extern char *sim_prompt; extern UNIT cr_unit; /* pointers to 1442 and 1132 (1403) printers */ extern UNIT prt_unit; @@ -1648,8 +1648,8 @@ void remark_cmd (char *remark) if (sim_log) fprintf(sim_log, "%s\n", remark); if (scp_reading) { - printf("sim> "); - if (sim_log) fprintf(sim_log, "sim> "); + printf("%s", sim_prompt); + if (sim_log) fprintf(sim_log, "%s", sim_prompt); } } diff --git a/Ibm1130/ibm1130_plot.c b/Ibm1130/ibm1130_plot.c index 02344a3c..efa14401 100644 --- a/Ibm1130/ibm1130_plot.c +++ b/Ibm1130/ibm1130_plot.c @@ -93,7 +93,6 @@ static void update_pen(void); /* will ensure pen action is correct static t_stat plot_validate_change (UNIT *uptr, int32 val, char * ptr, void *desc); /* when set command issued */ static void process_cmd(void); /* does actual drawing for plotter */ -extern int32 sim_switches; /* switches set on simh command */ static int16 plot_dsw = 0; /* device status word */ static int16 plot_cmd = 0; /* the command to process */ static int32 plot_wait = 1000; /* plotter movement wait */ diff --git a/Ibm1130/ibm1130_prt.c b/Ibm1130/ibm1130_prt.c index 90103b8f..21aaa140 100644 --- a/Ibm1130/ibm1130_prt.c +++ b/Ibm1130/ibm1130_prt.c @@ -202,8 +202,6 @@ cccgi[] = { #include "ibm1130_prtwheel.h" -extern int32 sim_switches; - /* cc_format_1132 and cc_format_1403 - turn cctape bits into proper format for DSW or status read */ static int cc_format_1132 (int bits) diff --git a/Ibm1130/ibm1130_sca.c b/Ibm1130/ibm1130_sca.c index b0e8e293..e9927185 100644 --- a/Ibm1130/ibm1130_sca.c +++ b/Ibm1130/ibm1130_sca.c @@ -85,9 +85,6 @@ #include "ibm1130_defs.h" #include "sim_sock.h" /* include path must include main simh directory */ #include -#ifndef INADDR_NONE -#define INADDR_NONE ((unsigned long)-1) -#endif #define DEBUG_SCA_FLUSH 0x0001 /* debugging options */ #define DEBUG_SCA_TRANSMIT 0x0002 @@ -106,7 +103,7 @@ /* #define DEBUG_SCA (DEBUG_SCA_TIMERS|DEBUG_SCA_FLUSH|DEBUG_SCA_TRANSMIT|DEBUG_SCA_CHECK_INDATA|DEBUG_SCA_RECEIVE_SYNC|DEBUG_SCA_RECEIVE_DATA|DEBUG_SCA_XIO_INITR|DEBUG_SCA_XIO_INITW) */ #define DEBUG_SCA (DEBUG_SCA_TIMERS|DEBUG_SCA_FLUSH|DEBUG_SCA_CHECK_INDATA|DEBUG_SCA_XIO_INITR|DEBUG_SCA_XIO_INITW) -#define SCA_DEFAULT_PORT 2703 /* default socket, This is the number of the IBM 360's BSC device */ +#define SCA_DEFAULT_PORT "2703" /* default socket, This is the number of the IBM 360's BSC device */ #define MAX_SYNS 100 /* number of consecutive syn's after which we stop buffering them */ @@ -164,7 +161,7 @@ static uint32 sca_state = SCA_STATE_IDLE; static uint8 sichar = 0; /* sync/idle character */ static uint8 rcvd_char = 0; /* most recently received character */ static uint8 sca_frame = 8; -static uint16 sca_port = SCA_DEFAULT_PORT; /* listening port number */ +static char sca_port[CBUFSIZE]; /* listening port */ static int32 sca_keepalive = 0; /* keepalive SYN packet period in msec, default = 0 (disabled) */ static SCA_TIMER_STATE sca_timer_state[3]; /* current timer state */ static int sca_timer_endtime[3]; /* clocktime when timeout is to occur if state is RUNNING */ @@ -205,8 +202,6 @@ static int sca_rcvptr = 0; /* index of next byte to take from rcvbuf * #define UNIT_AUTOANSWER (1u << UNIT_V_AUTOANSWER) #define UNIT_LISTEN (1u << UNIT_V_LISTEN) -extern int sim_switches; /* variable that gets bits set for -x switches on command lines */ - t_stat sca_set_baud (UNIT *uptr, int32 value, char *cptr, void *desc); UNIT sca_unit = { /* default settings */ @@ -221,7 +216,7 @@ REG sca_reg[] = { /* DEVICE STATE/SETTABLE PARAMETERS: */ { DRDATA (SCASTATE, sca_state, 32), PV_LEFT }, /* current state */ { DRDATA (CTIME, sca_cwait, 32), PV_LEFT }, /* inter-character wait */ { DRDATA (ITIME, sca_iwait, 32), PV_LEFT }, /* idle wait (polling interval for socket connects) */ - { DRDATA (SCASOCKET, sca_port, 16), PV_LEFT }, /* listening port number */ + { BRDATA (SCASOCKET, sca_port, 8, 8, sizeof(sca_port)) }, /* listening port number */ { DRDATA (KEEPALIVE, sca_keepalive, 32), PV_LEFT }, /* keepalive packet period in msec */ { NULL } }; @@ -317,7 +312,7 @@ static void sca_socket_error (void) free(sca_unit.filename); if (sca_unit.flags & UNIT_LISTEN) { - sprintf(name, "(Listening on port %d)", sca_port); + sprintf(name, "(Listening on port %s)", sca_port); sca_unit.filename = mstring(name); printf("%s\n", name); } @@ -454,99 +449,75 @@ static t_stat sca_reset (DEVICE *dptr) static t_stat sca_attach (UNIT *uptr, char *cptr) { + char host[CBUFSIZE], port[CBUFSIZE]; t_bool do_listen; - char *colon; - uint32 ipaddr; - int32 port; - struct hostent *he; - char name[256]; - static SOCKET sdummy = INVALID_SOCKET; - fd_set wr_set, err_set; + char name[CBUFSIZE]; + t_stat r; do_listen = sim_switches & SWMASK('L'); /* -l means listen mode */ if (sca_unit.flags & UNIT_ATT) /* if already attached, detach */ detach_unit(&sca_unit); - if (do_listen) { /* if listen mode, string specifies socket number (only; otherwise it's a dummy argument) */ - if (isdigit(*cptr)) { /* if digits specified, extract port number */ - port = atoi(cptr); - if (port <= 0 || port > 65535) - return SCPE_ARG; - else - sca_port = port; - } + if (do_listen) { /* if listen mode, string specifies port number (only; otherwise it's a dummy argument) */ + r = sim_parse_addr (cptr, host, sizeof(host), NULL, port, sizeof(port), SCA_DEFAULT_PORT, NULL); + if (r != SCPE_OK) + return r; + if ((0 == strcmp(port, cptr)) && (0 == strcmp(port, "dummy"))) + strcpy(port, SCA_DEFAULT_PORT); + + sprintf(sca_port, "%s%s%s:%s", strchr(host, ':') ? "[" : "", host, strchr(host, ':') ? "]" : "", port); + /* else if nondigits specified, ignore... but the command has to have something there otherwise the core scp */ /* attach_cmd() routine complains "too few arguments". */ - if ((sca_lsock = sim_master_sock(sca_port)) == INVALID_SOCKET) + sca_lsock = sim_master_sock(sca_port, &r); + if (r != SCPE_OK) + return r; + if (sca_lsock == INVALID_SOCKET) return SCPE_OPENERR; SETBIT(sca_unit.flags, UNIT_LISTEN); /* note that we are listening, not yet connected */ - sprintf(name, "(Listening on port %d)", sca_port); - sca_unit.filename = mstring(name); - printf("%s\n", name); + sprintf(name, "(Listening on port %s)", sca_port); + sca_unit.filename = mstring(name); + printf("%s\n", sca_unit.filename); } else { - while (*cptr && *cptr <= ' ') + while (*cptr && *cptr <= ' ') cptr++; if (! *cptr) return SCPE_2FARG; - if ((colon = strchr(cptr, ':')) != NULL) { - *colon++ = '\0'; /* clip hostname at colon */ + r = sim_parse_addr (cptr, host, sizeof(host), NULL, port, sizeof(port), SCA_DEFAULT_PORT, NULL); + if (r != SCPE_OK) + return r; + if ((0 == strcmp(cptr, port)) && (0 == strcmp(host, ""))) { + strcpy(host, port); + strcpy(port, SCA_DEFAULT_PORT); + } - port = atoi(colon); /* extract port number that follows it */ - if (port <= 0 || port > 65535) - return SCPE_ARG; - else - sca_port = port; - } + sprintf(sca_port, "%s%s%s:%s", strchr(host, ':') ? "[" : "", host, strchr(host, ':') ? "]" : "", port); - if (sdummy == INVALID_SOCKET) - if ((sdummy = sim_create_sock()) == INVALID_SOCKET) /* create and keep a socket, to force initialization */ - return SCPE_IERR; /* of socket library (e.g on Win32 call WSAStartup), else gethostbyname fails */ - - if (get_ipaddr(cptr, &ipaddr, NULL) != SCPE_OK) { /* try to parse hostname as dotted decimal nnn.nnn.nnn.nnn */ - if ((he = gethostbyname(cptr)) == NULL) /* if not decimal, look up name through DNS */ - return SCPE_OPENERR; - - if ((ipaddr = * (unsigned long *) he->h_addr_list[0]) == INADDR_NONE) - return SCPE_OPENERR; - - ipaddr = ntohl(ipaddr); /* convert to host byte order; gethostbyname() gives us network order */ - } - - if ((sca_sock = sim_connect_sock(ipaddr, sca_port)) == INVALID_SOCKET) + if ((sca_sock = sim_connect_sock(sca_port, NULL, NULL)) == INVALID_SOCKET) return SCPE_OPENERR; /* sim_connect_sock() sets socket to nonblocking before initiating the connect, so * the connect is pending when it returns. For outgoing connections, the attach command should wait - * until the connection succeeds or fails. We use "accept" to wait and find out which way it goes... + * until the connection succeeds or fails. We use "sim_check_conn" to wait and find out which way it goes... */ - FD_ZERO(&wr_set); /* we are only interested in info for sca_sock */ - FD_ZERO(&err_set); - FD_SET(sca_sock, &wr_set); - FD_SET(sca_sock, &err_set); + while (0 == sim_check_conn(sca_sock, 0))/* wait for connection to complete or fail */ + sim_os_ms_sleep(1000); - select(3, NULL, &wr_set, &err_set, NULL); /* wait for connection to complete or fail */ - - if (FD_ISSET(sca_sock, &wr_set)) { /* sca_sock appears in "writable" set -- connect completed */ - sprintf(name, "%s:%d", cptr, sca_port); + if (1 == sim_check_conn(sca_sock, 0)) { /* sca_sock appears in "writable" set -- connect completed */ + sprintf(name, "%s%s%s:%s", strchr(host, ':') ? "[" : "", host, strchr(host, ':') ? "]" : "", port); sca_unit.filename = mstring(name); SETBIT(sca_dsw, SCA_DSW_READY); } - else if (FD_ISSET(sca_sock, &err_set)) { /* sca_sock appears in "error" set -- connect failed */ - sim_close_sock(sca_sock, TRUE); - sca_sock = INVALID_SOCKET; - return SCPE_OPENERR; - } - else { /* if we get here my assumption about how select works is wrong */ - printf("SCA_SOCK NOT FOUND IN WR_SET -OR- ERR_SET, CODING IN IBM1130_SCA IS WRONG\n"); + else { /* sca_sock appears in "error" set -- connect failed */ sim_close_sock(sca_sock, TRUE); sca_sock = INVALID_SOCKET; return SCPE_OPENERR; @@ -610,22 +581,17 @@ static t_stat sca_detach (UNIT *uptr) static void sca_check_connect (void) { - uint32 ipaddr; - char name[100]; + char *connectaddress; - if ((sca_sock = sim_accept_conn(sca_lsock, &ipaddr)) == INVALID_SOCKET) + if ((sca_sock = sim_accept_conn(sca_lsock, &connectaddress)) == INVALID_SOCKET) return; - ipaddr = htonl(ipaddr); /* convert to network order so we can print it */ - - sprintf(name, "%d.%d.%d.%d", ipaddr & 0xFF, (ipaddr >> 8) & 0xFF, (ipaddr >> 16) & 0xFF, (ipaddr >> 24) & 0xFF); - - printf("(SCA connection from %s)\n", name); + printf("(SCA connection from %s)\n", connectaddress); if (sca_unit.filename != NULL) free(sca_unit.filename); - sca_unit.filename = mstring(name); + sca_unit.filename = connectaddress; SETBIT(sca_dsw, SCA_DSW_READY); /* indicate active connection */ diff --git a/Ibm1130/ibm1130_stddev.c b/Ibm1130/ibm1130_stddev.c index d71d45b4..b6d15034 100644 --- a/Ibm1130/ibm1130_stddev.c +++ b/Ibm1130/ibm1130_stddev.c @@ -112,7 +112,6 @@ typedef struct tag_os_map { /* os_map = overstrike mapping */ unsigned char inlist[MAX_OS_CHARS]; /* inlist = overstruck ASCII characters, sorted. NOT NULL TERMINATED */ } OS_MAP; -extern UNIT *sim_clock_queue; extern int cgi; static int32 tti_dsw = 0; /* device status words */ @@ -152,10 +151,6 @@ static char * handle_map_input_definition(char **pc); static char * handle_map_output_definition(char **pc); static char * handle_map_overstrike_definition(char **pc); -extern t_stat sim_poll_kbd(void); -extern t_stat sim_wait_kbd(void); -extern t_stat sim_putchar(int32 out); - #define UNIT_V_CSET (UNIT_V_UF + 0) /* user flag: character set */ #define UNIT_V_LOCKED (UNIT_V_UF + 2) /* user flag: keyboard locked */ #define UNIT_V_ANSI (UNIT_V_UF + 3) @@ -340,7 +335,7 @@ t_stat emit_conout_character (int ch) return map_conout_character(ch); } -static void Beep (void) /* notify user keyboard was locked or key was bad */ +static void SendBeep (void) /* notify user keyboard was locked or key was bad */ { sim_putchar(7); } @@ -356,7 +351,7 @@ static t_stat tti_svc (UNIT *uptr) /* otherwise, so ^E can interrupt the simulator, */ sim_activate(&tti_unit, tti_unit.wait); /* always continue polling keyboard */ - assert(sim_clock_queue != NULL); + assert(sim_clock_queue != QUEUE_LIST_END); temp = sim_poll_kbd(); @@ -395,7 +390,7 @@ static t_stat tti_svc (UNIT *uptr) } if ((tti_unit.flags & KEYBOARD_LOCKED) || ! (tti_dsw & TT_DSW_KEYBOARD_BUSY)) { - Beep(); + SendBeep(); return SCPE_OK; } @@ -403,7 +398,7 @@ static t_stat tti_svc (UNIT *uptr) temp = ascii_to_conin[temp]; if (temp == 0) { /* ignore invalid characters */ - Beep(); + SendBeep(); calc_ints(); return SCPE_OK; } diff --git a/Interdata/id16_cpu.c b/Interdata/id16_cpu.c index 9add9292..bfcc6d45 100644 --- a/Interdata/id16_cpu.c +++ b/Interdata/id16_cpu.c @@ -223,11 +223,6 @@ InstHistory *hst = NULL; /* instruction history * struct BlockIO blk_io; /* block I/O status */ uint32 (*dev_tab[DEVNO])(uint32 dev, uint32 op, uint32 datout) = { NULL }; -extern int32 sim_interval; -extern int32 sim_int_char; -extern uint32 sim_brk_types, sim_brk_dflt, sim_brk_summ; /* breakpoint info */ -extern t_bool sim_idle_enab; - uint32 ReadB (uint32 loc); uint32 ReadH (uint32 loc); void WriteB (uint32 loc, uint32 val); @@ -651,7 +646,6 @@ while (reason == 0) { /* loop until halted */ if (PSW & PSW_WAIT) { /* wait state? */ sim_idle (TMR_LFC, TRUE); /* idling */ - else sim_interval = sim_interval - 1; /* no, count cycle */ continue; } @@ -2010,8 +2004,6 @@ char *cptr = (char *) desc; t_value sim_eval[2]; t_stat r; InstHistory *h; -extern t_stat fprint_sym (FILE *ofile, t_addr addr, t_value *val, - UNIT *uptr, int32 sw); if (hst_lnt == 0) /* enabled? */ return SCPE_NOFNC; diff --git a/Interdata/id32_cpu.c b/Interdata/id32_cpu.c index 386e1630..c1d89b10 100644 --- a/Interdata/id32_cpu.c +++ b/Interdata/id32_cpu.c @@ -222,7 +222,7 @@ uint32 GREG[16 * NRSETS] = { 0 }; /* general registers */ uint32 *M = NULL; /* memory */ uint32 *R = &GREG[0]; /* working reg set */ uint32 F[8] = { 0 }; /* sp fp registers */ -dpr_t D[8] = { 0 }; /* dp fp registers */ +dpr_t D[8] = { {0} }; /* dp fp registers */ uint32 PSW = 0; /* processor status word */ uint32 PC = 0; /* program counter */ uint32 oPC = 0; /* PC at inst start */ @@ -253,12 +253,6 @@ jmp_buf save_env; /* abort handler */ struct BlockIO blk_io; /* block I/O status */ uint32 (*dev_tab[DEVNO])(uint32 dev, uint32 op, uint32 datout) = { NULL }; -extern int32 sim_interval; -extern int32 sim_int_char; -extern uint32 sim_brk_types, sim_brk_dflt, sim_brk_summ; /* breakpoint info */ -extern t_bool sim_idle_enab; -extern FILE *sim_deb; - uint32 ReadB (uint32 loc, uint32 rel); uint32 ReadH (uint32 loc, uint32 rel); void WriteB (uint32 loc, uint32 val, uint32 rel); @@ -715,7 +709,6 @@ while (reason == 0) { /* loop until halted */ if (PSW & PSW_WAIT) { /* wait state? */ sim_idle (TMR_LFC, TRUE); /* idling */ - else sim_interval = sim_interval - 1; /* no, count cycle */ continue; } @@ -2399,8 +2392,6 @@ char *cptr = (char *) desc; t_value sim_eval[3]; t_stat r; InstHistory *h; -extern t_stat fprint_sym (FILE *ofile, t_addr addr, t_value *val, - UNIT *uptr, int32 sw); if (hst_lnt == 0) /* enabled? */ return SCPE_NOFNC; diff --git a/Interdata/id32_dboot.c b/Interdata/id32_dboot.c index 40ee4167..133f59e2 100644 --- a/Interdata/id32_dboot.c +++ b/Interdata/id32_dboot.c @@ -288,7 +288,6 @@ t_stat id_dboot (int32 u, DEVICE *dptr) { extern DIB ttp_dib, sch_dib; extern uint32 PC; -extern int32 sim_switches; uint32 i, typ, ctlno, off, add, cap, sch_dev; UNIT *uptr; diff --git a/Interdata/id_dp.c b/Interdata/id_dp.c index cf3f82c2..de31cfbf 100644 --- a/Interdata/id_dp.c +++ b/Interdata/id_dp.c @@ -139,7 +139,6 @@ static struct drvtyp drv_tab[] = { }; extern uint32 int_req[INTSZ], int_enb[INTSZ]; -extern FILE *sim_deb; uint8 dpxb[DP_NUMBY]; /* xfer buffer */ uint32 dp_bptr = 0; /* buffer ptr */ diff --git a/Interdata/id_fd.c b/Interdata/id_fd.c index a016436c..079d05ef 100644 --- a/Interdata/id_fd.c +++ b/Interdata/id_fd.c @@ -115,7 +115,7 @@ uint32 fd_cmd = 0; /* command */ uint32 fd_db = 0; /* data buffer */ uint32 fd_bptr = 0; /* buffer pointer */ uint8 fdxb[FD_NUMBY] = { 0 }; /* sector buffer */ -uint8 fd_es[FD_NUMDR][ES_SIZE] = { 0 }; /* ext status */ +uint8 fd_es[FD_NUMDR][ES_SIZE] = { {0} }; /* ext status */ uint32 fd_lrn = 0; /* log rec # */ uint32 fd_wdv = 0; /* wd valid */ uint32 fd_stopioe = 1; /* stop on error */ diff --git a/Interdata/id_io.c b/Interdata/id_io.c index 4ba20a23..6a326b08 100644 --- a/Interdata/id_io.c +++ b/Interdata/id_io.c @@ -66,8 +66,6 @@ extern uint32 int_req[INTSZ], int_enb[INTSZ]; extern uint32 (*dev_tab[DEVNO])(uint32 dev, uint32 op, uint32 datout); extern uint32 pawidth; extern UNIT cpu_unit; -extern FILE *sim_log; -extern DEVICE *sim_devices[]; uint32 sch_max = 2; /* sch count */ uint32 sch_sa[SCH_NUMCH] = { 0 }; /* start addr */ diff --git a/Interdata/id_mt.c b/Interdata/id_mt.c index f71a5f18..f9209d82 100644 --- a/Interdata/id_mt.c +++ b/Interdata/id_mt.c @@ -168,7 +168,7 @@ DEVICE mt_dev = { MT_NUMDR, 10, 31, 1, 16, 8, NULL, NULL, &mt_reset, &mt_boot, &mt_attach, &mt_detach, - &mt_dib, DEV_DISABLE + &mt_dib, DEV_DISABLE | DEV_TAPE }; /* Magtape: IO routine */ diff --git a/Interdata/id_pas.c b/Interdata/id_pas.c index 3e2d105a..8b007f57 100644 --- a/Interdata/id_pas.c +++ b/Interdata/id_pas.c @@ -103,7 +103,7 @@ uint8 pas_xarm[PAS_LINES]; /* xmt int armed */ uint8 pas_rchp[PAS_LINES]; /* rcvr chr pend */ uint8 pas_tplte[PAS_LINES * 2 + 1]; /* template */ -TMLN pas_ldsc[PAS_LINES] = { 0 }; /* line descriptors */ +TMLN pas_ldsc[PAS_LINES] = { {0} }; /* line descriptors */ TMXR pas_desc = { 8, 0, 0, pas_ldsc }; /* mux descriptor */ #define PAS_ENAB pas_desc.lines @@ -165,7 +165,7 @@ DEVICE pas_dev = { 1, 10, 31, 1, 16, 8, &tmxr_ex, &tmxr_dep, &pas_reset, NULL, &pas_attach, &pas_detach, - &pas_dib, DEV_NET | DEV_DISABLE + &pas_dib, DEV_MUX | DEV_DISABLE }; /* PASL data structures diff --git a/Interdata/id_ttp.c b/Interdata/id_ttp.c index 660fd469..eb9fd393 100644 --- a/Interdata/id_ttp.c +++ b/Interdata/id_ttp.c @@ -130,7 +130,7 @@ DEVICE ttp_dev = { uint32 ttp (uint32 dev, uint32 op, uint32 dat) { int32 xmt = dev & 1; -int32 t, old_cmd; +int32 t; switch (op) { /* case IO op */ @@ -160,7 +160,6 @@ switch (op) { /* case IO op */ return t; case IO_OC: /* command */ - old_cmd = ttp_cmd; /* old cmd */ if (dat & CMD_TYP) { /* type 1? */ ttp_cmd = (ttp_cmd & 0xFF) | (dat << 8); if (ttp_cmd & CMD_WRT) /* write? */ diff --git a/Interdata/id_uvc.c b/Interdata/id_uvc.c index 7ccc070a..0d1d9451 100644 --- a/Interdata/id_uvc.c +++ b/Interdata/id_uvc.c @@ -358,7 +358,7 @@ int32 lfc_cosched (int32 wait) { int32 t; -t = sim_is_active (&lfc_unit); +t = sim_activate_time (&lfc_unit); return (t? t - 1: wait); } diff --git a/LGP/lgp_cpu.c b/LGP/lgp_cpu.c index 27f2746c..083625a0 100644 --- a/LGP/lgp_cpu.c +++ b/LGP/lgp_cpu.c @@ -147,9 +147,6 @@ int16 pcq[PCQ_SIZE] = { 0 }; /* PC queue */ int32 pcq_p = 0; /* PC queue ptr */ REG *pcq_r = NULL; /* PC queue reg ptr */ -extern int32 sim_interval; -extern int32 sim_int_char; -extern uint32 sim_brk_types, sim_brk_dflt, sim_brk_summ; /* breakpoint info */ extern int32 sim_step; t_stat cpu_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw); diff --git a/LGP/lgp_stddev.c b/LGP/lgp_stddev.c index f86ac096..dad514c0 100644 --- a/LGP/lgp_stddev.c +++ b/LGP/lgp_stddev.c @@ -48,7 +48,6 @@ extern uint32 A; extern uint32 inp_strt, inp_done; extern uint32 out_strt, out_done; extern UNIT cpu_unit; -extern int32 sim_switches; t_stat tti_svc (UNIT *uptr); t_stat ttr_svc (UNIT *uptr); diff --git a/LGP/lgp_sys.c b/LGP/lgp_sys.c index 083a3025..acac5b08 100644 --- a/LGP/lgp_sys.c +++ b/LGP/lgp_sys.c @@ -40,12 +40,8 @@ extern REG cpu_reg[]; extern uint32 M[]; extern uint32 PC; extern uint32 ts_flag; -extern int32 sim_switches; extern int32 flex_to_ascii[128], ascii_to_flex[128]; -extern void (*sim_vm_fprint_addr) (FILE *st, DEVICE *dptr, t_addr addr); -extern t_addr (*sim_vm_parse_addr) (DEVICE *dptr, char *cptr, char **tptr); - /* SCP data structures and interface routines sim_name simulator name string diff --git a/NOVA/eclipse_cpu.c b/NOVA/eclipse_cpu.c index c855cc55..0532da3b 100644 --- a/NOVA/eclipse_cpu.c +++ b/NOVA/eclipse_cpu.c @@ -495,9 +495,6 @@ FILE *Trace; t_stat reason; -extern int32 sim_int_char; -extern uint32 sim_brk_types, sim_brk_dflt, sim_brk_summ; /* breakpoint info */ -extern DEVICE *sim_devices[]; t_stat cpu_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw); t_stat cpu_dep (t_value val, t_addr addr, UNIT *uptr, int32 sw); @@ -516,9 +513,6 @@ int32 PutMap(int32 addr, int32 data); int32 Debug_Entry(int32 PC, int32 inst, int32 inst2, int32 AC0, int32 AC1, int32 AC2, int32 AC3, int32 flags); t_stat build_devtab (void); -extern t_stat fprint_sym (FILE *of, t_addr addr, t_value *val, - UNIT *uptr, int32 sw); - /* CPU data structures cpu_dev CPU device descriptor @@ -699,7 +693,6 @@ DEVICE pit_dev = { t_stat sim_instr (void) { -extern int32 sim_interval; register int32 PC, IR, i, t, MA, j, k, tac; register uint32 mddata, uAC0, uAC1, uAC2, uAC3; int16 sAC0, sAC1, sAC2; diff --git a/NOVA/eclipse_tt.c b/NOVA/eclipse_tt.c index ab3489dd..49c350d7 100644 --- a/NOVA/eclipse_tt.c +++ b/NOVA/eclipse_tt.c @@ -35,6 +35,7 @@ */ #include "nova_defs.h" +#include "sim_tmxr.h" #define UNIT_V_DASHER (UNIT_V_UF + 0) /* Dasher mode */ #define UNIT_DASHER (1 << UNIT_V_DASHER) @@ -192,6 +193,7 @@ void translate_in() t_stat tti_reset (DEVICE *dptr) { +tmxr_set_console_units (&tti_unit, &tto_unit); tti_unit.buf = 0; dev_busy = dev_busy & ~INT_TTI; /* clear busy */ dev_done = dev_done & ~INT_TTI; /* clear done, int */ diff --git a/NOVA/nova_cpu.c b/NOVA/nova_cpu.c index a1caf573..ab2fc108 100644 --- a/NOVA/nova_cpu.c +++ b/NOVA/nova_cpu.c @@ -330,14 +330,6 @@ char * devBitNames( int32 flags, char * ptr, char * sepStr ) ; void mask_out (int32 mask); -extern int32 sim_interval; -extern int32 sim_int_char; -extern uint32 sim_brk_types, sim_brk_dflt, sim_brk_summ; /* breakpoint info */ -extern DEVICE * sim_devices[]; -extern t_stat fprint_sym(FILE *ofile, t_addr addr, t_value *val, UNIT *uptr, int32 sw); - - - /* CPU data structures cpu_dev CPU device descriptor diff --git a/NOVA/nova_dkp.c b/NOVA/nova_dkp.c index c027022f..f5126f28 100644 --- a/NOVA/nova_dkp.c +++ b/NOVA/nova_dkp.c @@ -25,6 +25,7 @@ dkp moving head disk + 27-Apr-12 RMS Changed ??? string digraphs to ?, per C rules 04-Jul-04 BKR device name changed to DG's DKP from DEC's DP, DEV_SET/CLR/INTR macro use started, fixed 'P' pulse code and secret quirks, @@ -706,7 +707,7 @@ if ( DKP_TRACE(1) ) "write" : ((uptr->FUNC == FCCY_SEEK) ? "seek" - : "" + : "" ) ) ), @@ -871,7 +872,7 @@ do { "read" : ((uptr->FUNC == FCCY_WRITE) ? "write" - : "") + : "") ), (unsigned) (uptr->CYL), (unsigned) (GET_SURF(dkp_ussc, dtype)), diff --git a/NOVA/nova_mta.c b/NOVA/nova_mta.c index 25a9ec1e..42d16873 100644 --- a/NOVA/nova_mta.c +++ b/NOVA/nova_mta.c @@ -236,7 +236,7 @@ DEVICE mta_dev = { MTA_NUMDR, 10, 31, 1, 8, 8, NULL, NULL, &mta_reset, &mta_boot, &mta_attach, &mta_detach, - &mta_dib, DEV_DISABLE + &mta_dib, DEV_DISABLE | DEV_TAPE }; /* IOT routine */ diff --git a/NOVA/nova_qty.c b/NOVA/nova_qty.c index 215ac3fe..8e1e07a4 100644 --- a/NOVA/nova_qty.c +++ b/NOVA/nova_qty.c @@ -105,8 +105,6 @@ extern int32 int_req, dev_busy, dev_done, dev_disable ; -extern int32 sim_switches ; -extern FILE * sim_log ; extern int32 tmxr_poll ; /* calibrated delay */ t_stat qty_setnl ( UNIT * uptr, int32 val, char * cptr, void * desc ) ; @@ -193,7 +191,7 @@ DEVICE qty_dev = 1, 10, 31, 1, 8, 8, NULL, NULL, &qty_reset, NULL, &qty_attach, &qty_detach, - &qty_dib, (DEV_DISABLE | DEV_DIS | DEV_NET) + &qty_dib, (DEV_DISABLE | DEV_DIS | DEV_MUX) }; #define DG_RETURN( status, data ) (int32)(((status) << IOT_V_REASON) | ((data) & 0x0FFFF) ) @@ -222,7 +220,7 @@ DEVICE qty_dev = #define QTY_LINE_RX_CHAR( line ) (qty_status[ (line) ] & QTY_S_DMASK) #define QTY_UNIT_ACTIVE( unitp ) ( (unitp)->conn ) -#define QTY_LINE_BITS( line, bits ) qty_status[ (line) ] & bits +#define QTY_LINE_BITS( line, bits ) (qty_status[ (line) ] & bits) #define QTY_LINE_SET_BIT( line, bit ) qty_status[ (line) ] |= (bit) ; #define QTY_LINE_CLEAR_BIT( line, bit ) qty_status[ (line) ] &= ~(bit) ; diff --git a/NOVA/nova_sys.c b/NOVA/nova_sys.c index 36a4cf22..104b992c 100644 --- a/NOVA/nova_sys.c +++ b/NOVA/nova_sys.c @@ -79,9 +79,6 @@ extern int32 MapStat; #endif -extern int32 sim_switches; - - /* SCP data structures sim_name simulator name string diff --git a/NOVA/nova_tt.c b/NOVA/nova_tt.c index 59491d5c..8d5abff3 100644 --- a/NOVA/nova_tt.c +++ b/NOVA/nova_tt.c @@ -49,6 +49,7 @@ */ #include "nova_defs.h" +#include "sim_tmxr.h" #define UNIT_V_DASHER (UNIT_V_UF + 0) /* Dasher mode */ #define UNIT_DASHER (1 << UNIT_V_DASHER) @@ -186,6 +187,7 @@ return SCPE_OK; t_stat tti_reset (DEVICE *dptr) { +tmxr_set_console_units (&tti_unit, &tto_unit); tti_unit.buf = 0; /* */ DEV_CLR_BUSY( INT_TTI ) ; DEV_CLR_DONE( INT_TTI ) ; diff --git a/NOVA/nova_tt1.c b/NOVA/nova_tt1.c index cffad5e9..5cb969b8 100644 --- a/NOVA/nova_tt1.c +++ b/NOVA/nova_tt1.c @@ -108,7 +108,7 @@ DEVICE tti1_dev = { 1, 10, 31, 1, 8, 8, &tmxr_ex, &tmxr_dep, &tti1_reset, NULL, &tti1_attach, &tti1_detach, - &tti1_dib, DEV_NET | DEV_DISABLE + &tti1_dib, DEV_MUX | DEV_DISABLE }; /* TTO1 data structures @@ -148,7 +148,7 @@ DEVICE tto1_dev = { 1, 10, 31, 1, 8, 8, NULL, NULL, &tto1_reset, NULL, NULL, NULL, - &tto1_dib, DEV_DISABLE + &tto1_dib, DEV_DISABLE | DEV_MUX }; /* Terminal input: IOT routine */ diff --git a/PDP1/pdp1_clk.c b/PDP1/pdp1_clk.c index 9e3914fd..acc32533 100644 --- a/PDP1/pdp1_clk.c +++ b/PDP1/pdp1_clk.c @@ -89,7 +89,7 @@ int32 used, incr; if (clk_dev.flags & DEV_DIS) /* disabled? */ return (stop_inst << IOT_V_REASON) | dat; /* illegal inst */ -used = tmxr_poll - (sim_is_active (&clk_unit) - 1); +used = tmxr_poll - (sim_activate_time (&clk_unit) - 1); incr = (used * CLK_CNTS) / tmxr_poll; return clk_cntr + incr; } diff --git a/PDP1/pdp1_cpu.c b/PDP1/pdp1_cpu.c index d52a6a31..a58174ec 100644 --- a/PDP1/pdp1_cpu.c +++ b/PDP1/pdp1_cpu.c @@ -335,10 +335,6 @@ int32 hst_p = 0; /* history pointer */ int32 hst_lnt = 0; /* history length */ InstHistory *hst = NULL; /* inst history */ -extern UNIT *sim_clock_queue; -extern int32 sim_int_char; -extern uint32 sim_brk_types, sim_brk_dflt, sim_brk_summ; /* breakpoint info */ - t_stat cpu_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw); t_stat cpu_dep (t_value val, t_addr addr, UNIT *uptr, int32 sw); t_stat cpu_reset (DEVICE *dptr); @@ -503,7 +499,6 @@ DEVICE cpu_dev = { t_stat sim_instr (void) { -extern int32 sim_interval; int32 IR, op, i, t, xct_count; int32 sign, signd, v, sbs_lvl, byno; int32 dev, pulse, io_data, sc, skip; @@ -1656,8 +1651,6 @@ char *cptr = (char *) desc; t_stat r; t_value sim_eval; InstHistory *h; -extern t_stat fprint_sym (FILE *ofile, t_addr addr, t_value *val, - UNIT *uptr, int32 sw); if (hst_lnt == 0) /* enabled? */ return SCPE_NOFNC; diff --git a/PDP1/pdp1_dcs.c b/PDP1/pdp1_dcs.c index 93c9eefc..068c1440 100644 --- a/PDP1/pdp1_dcs.c +++ b/PDP1/pdp1_dcs.c @@ -48,7 +48,7 @@ uint8 dcs_buf[DCS_LINES]; /* line bufffers */ extern int32 iosta, stop_inst; extern int32 tmxr_poll; -TMLN dcs_ldsc[DCS_LINES] = { 0 }; /* line descriptors */ +TMLN dcs_ldsc[DCS_LINES] = { {0} }; /* line descriptors */ TMXR dcs_desc = { DCS_LINES, 0, 0, dcs_ldsc }; /* mux descriptor */ t_stat dcsi_svc (UNIT *uptr); @@ -101,7 +101,7 @@ DEVICE dcs_dev = { 1, 10, 31, 1, 8, 8, &tmxr_ex, &tmxr_dep, &dcs_reset, NULL, &dcs_attach, &dcs_detach, - NULL, DEV_NET | DEV_DISABLE | DEV_DIS + NULL, DEV_MUX | DEV_DISABLE | DEV_DIS }; /* DCSL data structures @@ -172,7 +172,7 @@ DEVICE dcsl_dev = { DCS_LINES, 10, 31, 1, 8, 8, NULL, NULL, &dcs_reset, NULL, NULL, NULL, - NULL, DEV_DIS + NULL, DEV_DIS | DEV_MUX }; /* DCS IOT routine */ diff --git a/PDP1/pdp1_dt.c b/PDP1/pdp1_dt.c index 2c902f62..3083a76a 100644 --- a/PDP1/pdp1_dt.c +++ b/PDP1/pdp1_dt.c @@ -250,9 +250,6 @@ extern int32 M[]; extern int32 stop_inst; extern UNIT cpu_unit; -extern int32 sim_switches; -extern int32 sim_is_running; -extern FILE *sim_deb; int32 dtsa = 0; /* status A */ int32 dtsb = 0; /* status B */ diff --git a/PDP1/pdp1_stddev.c b/PDP1/pdp1_stddev.c index 1d1586dc..da86e10c 100644 --- a/PDP1/pdp1_stddev.c +++ b/PDP1/pdp1_stddev.c @@ -51,6 +51,7 @@ */ #include "pdp1_defs.h" +#include "sim_tmxr.h" #define FIODEC_STOP 013 /* stop code */ #define FIODEC_UC 074 @@ -624,6 +625,7 @@ return SCPE_OK; t_stat tty_reset (DEVICE *dptr) { +tmxr_set_console_units (&tti_unit, &tto_unit); tty_buf = 0; /* clear buffer */ tty_uc = 0; /* clear case */ tti_hold = 0; /* clear hold buf */ diff --git a/PDP1/pdp1_sys.c b/PDP1/pdp1_sys.c index d8985cd9..210d01c0 100644 --- a/PDP1/pdp1_sys.c +++ b/PDP1/pdp1_sys.c @@ -65,7 +65,6 @@ extern int32 M[]; extern int32 PC; extern int32 ascii_to_fiodec[], fiodec_to_ascii[]; extern int32 sc_map[]; -extern int32 sim_switches; /* SCP data structures and interface routines diff --git a/PDP10/pdp10_cpu.c b/PDP10/pdp10_cpu.c index 37cf218b..94850a2d 100644 --- a/PDP10/pdp10_cpu.c +++ b/PDP10/pdp10_cpu.c @@ -198,10 +198,6 @@ int32 hst_p = 0; /* history pointer */ int32 hst_lnt = 0; /* history length */ InstHistory *hst = NULL; /* instruction history */ -extern int32 sim_int_char; -extern int32 sim_interval; -extern uint32 sim_brk_types, sim_brk_dflt, sim_brk_summ; /* breakpoint info */ - /* Forward and external declarations */ t_stat cpu_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw); @@ -2393,8 +2389,6 @@ char *cptr = (char *) desc; t_stat r; t_value sim_eval; InstHistory *h; -extern t_stat fprint_sym (FILE *ofile, t_addr addr, t_value *val, - UNIT *uptr, int32 sw); if (hst_lnt == 0) /* enabled? */ return SCPE_NOFNC; diff --git a/PDP10/pdp10_defs.h b/PDP10/pdp10_defs.h index d076dbd9..03834b2c 100644 --- a/PDP10/pdp10_defs.h +++ b/PDP10/pdp10_defs.h @@ -624,11 +624,9 @@ typedef struct pdp_dib DIB; #define DEV_V_UBUS (DEV_V_UF + 0) /* Unibus */ #define DEV_V_QBUS (DEV_V_UF + 1) /* Qbus */ #define DEV_V_Q18 (DEV_V_UF + 2) /* Qbus, mem <= 256KB */ -#define DEV_V_FLTA (DEV_V_UF + 3) /* float addr */ #define DEV_UBUS (1u << DEV_V_UBUS) #define DEV_QBUS (1u << DEV_V_QBUS) #define DEV_Q18 (1u << DEV_V_Q18) -#define DEV_FLTA (1u << DEV_V_FLTA) #define UNIBUS TRUE /* 18b only */ @@ -636,7 +634,7 @@ typedef struct pdp_dib DIB; /* I/O page layout */ -#define IOPAGEBASE 0760000 /* I/O page base */ +#define IOPAGEBASE (IO_UBA3 + 0760000) /* I/O page base */ #define IOBA_UBMAP 0763000 #define IOBA_UBMAP1 (IO_UBA1 + IOBA_UBMAP) /* Unibus 1 map */ @@ -672,6 +670,7 @@ typedef struct pdp_dib DIB; #define IOLN_PTR 004 #define IOBA_PTP (IO_UBA3 + 017554) /* PC11 punch */ #define IOLN_PTP 004 +#define IOBA_AUTO 0 /* Set by Auto Configure */ /* Common Unibus CSR flags */ @@ -697,6 +696,8 @@ typedef struct pdp_dib DIB; #define INT_V_RP 6 /* RH11/RP,RM drives */ #define INT_V_TU 7 /* RH11/TM03/TU45 */ +#define INT_V_DMCRX 13 +#define INT_V_DMCTX 14 #define INT_V_XU 15 /* DEUNA/DELUA */ #define INT_V_DZRX 16 /* DZ11 */ #define INT_V_DZTX 17 @@ -708,6 +709,8 @@ typedef struct pdp_dib DIB; #define INT_RP (1u << INT_V_RP) #define INT_TU (1u << INT_V_TU) +#define INT_DMCRX (1u << INT_V_DMCRX) +#define INT_DMCTX (1u << INT_V_DMCTX) #define INT_XU (1u << INT_V_XU) #define INT_DZRX (1u << INT_V_DZRX) #define INT_DZTX (1u << INT_V_DZTX) @@ -719,6 +722,8 @@ typedef struct pdp_dib DIB; #define IPL_RP 6 /* int levels */ #define IPL_TU 6 +#define IPL_DMCRX 5 +#define IPL_DMCTX 5 #define IPL_XU 5 #define IPL_DZRX 5 #define IPL_DZTX 5 @@ -747,6 +752,7 @@ typedef struct pdp_dib DIB; #define VEC_DZRX 0340 #define VEC_DZTX 0344 #define VEC_LP20 0754 +#define VEC_AUTO 0 /* Set by Auto Configure */ #define IVCL(dv) (INT_V_##dv) #define IREQ(dv) int_req @@ -768,8 +774,6 @@ t_stat show_vec (FILE *st, UNIT *uptr, int32 val, void *desc); t_stat show_vec_mux (FILE *st, UNIT *uptr, int32 val, void *desc); t_stat auto_config (char *name, int32 num); -int32 clk_cosched (int32 wait); - /* Global data */ extern t_bool sim_idle_enab; diff --git a/PDP10/pdp10_fe.c b/PDP10/pdp10_fe.c index 97cbb20d..80d4a436 100644 --- a/PDP10/pdp10_fe.c +++ b/PDP10/pdp10_fe.c @@ -39,6 +39,7 @@ */ #include "pdp10_defs.h" +#include "sim_tmxr.h" #define UNIT_DUMMY (1 << UNIT_V_UF) extern d10 *M; @@ -143,8 +144,7 @@ t_stat fei_svc (UNIT *uptr) { int32 temp; -sim_activate (uptr, KBD_WAIT (uptr->wait, clk_cosched (tmxr_poll))); - /* continue poll */ +sim_clock_coschedule (uptr, tmxr_poll); /* continue poll */ if ((temp = sim_poll_kbd ()) < SCPE_KFLAG) /* no char or error? */ return temp; if (temp & SCPE_BREAK) /* ignore break */ @@ -160,6 +160,7 @@ return SCPE_OK; t_stat fe_reset (DEVICE *dptr) { +tmxr_set_console_units (&fe_unit[0], &fe_unit[1]); fei_unit.buf = feo_unit.buf = 0; M[FE_CTYIN] = M[FE_CTYOUT] = 0; apr_flg = apr_flg & ~(APRF_ITC | APRF_CON); diff --git a/PDP10/pdp10_ksio.c b/PDP10/pdp10_ksio.c index e71f773c..c270f191 100644 --- a/PDP10/pdp10_ksio.c +++ b/PDP10/pdp10_ksio.c @@ -74,6 +74,11 @@ #include "sim_sock.h" #include "sim_tmxr.h" +#define AUTO_MAXC 32 /* Maximum number of controllers */ +#define AUTO_CSRBASE 0010 +#define AUTO_CSRMAX 04000 +#define AUTO_VECBASE 0300 + #define XBA_MBZ 0400000 /* ba mbz */ #define eaRB (ea & ~1) #define GETBYTE(ea,x) ((((ea) & 1)? (x) >> 8: (x)) & 0377) @@ -92,6 +97,9 @@ int32 ubcs[UBANUM] = { 0 }; /* status registers */ int32 ubmap[UBANUM][UMAP_MEMSIZE] = { 0 }; /* Unibus maps */ int32 int_req = 0; /* interrupt requests */ +int32 autcon_enb = 1; /* auto configure enabled */ + + /* Map IO controller numbers to Unibus adapters: -1 = non-existent */ static int iocmap[IO_N_UBA] = { /* map I/O ext to UBA # */ @@ -112,9 +120,7 @@ extern d10 pager_word; extern int32 flags; extern const int32 pi_l2bit[8]; extern UNIT cpu_unit; -extern FILE *sim_log; extern jmp_buf save_env; -extern DEVICE *sim_devices[]; extern int32 pi_eval (void); extern int32 rp_inta (void); @@ -698,6 +704,7 @@ if (GET_IOUBA (newba) != GET_IOUBA (dibp->ba)) if (newba % ((uint32) val)) /* check modulus */ return SCPE_ARG; dibp->ba = newba; /* store */ +autcon_enb = 0; /* autoconfig off */ return SCPE_OK; } @@ -714,11 +721,16 @@ dptr = find_dev_from_unit (uptr); if (dptr == NULL) return SCPE_IERR; dibp = (DIB *) dptr->ctxt; -if ((dibp == NULL) || (dibp->ba <= IOPAGEBASE)) +if (dibp == NULL) + return SCPE_IERR; +if (((dibp->ba>>IO_V_UBA) != 1) && + ((dibp->ba>>IO_V_UBA) != 3)) return SCPE_IERR; fprintf (st, "address=%07o", dibp->ba); if (dibp->lnt > 1) fprintf (st, "-%07o", dibp->ba + dibp->lnt - 1); +if ((dibp->ba & ((1 << IO_V_UBA) - 1)) < AUTO_CSRBASE + AUTO_CSRMAX) + fprintf (st, "*"); return SCPE_OK; } @@ -747,6 +759,7 @@ if ((r != SCPE_OK) || (newvec == VEC_Q) || (newvec & ((dibp->vnum > 1)? 07: 03))) return SCPE_ARG; dibp->vec = newvec; +autcon_enb = 0; /* autoconfig off */ return SCPE_OK; } @@ -777,6 +790,8 @@ else { if (numvec > 1) fprintf (st, "-%o", vec + (4 * (numvec - 1))); } +if (vec >= AUTO_VECBASE) + fprintf (st, "*"); return SCPE_OK; } @@ -904,16 +919,318 @@ for (i = 0; dib_tab[i] != NULL; i++) { /* print table */ return SCPE_OK; } -/* Stub auto-configure */ +/* Autoconfiguration -t_stat auto_config (char *name, int32 num) + The table reflects the MicroVAX 3900 microcode, with one field addition - the + number of controllers field handles devices where multiple instances + are simulated through a single DEVICE structure (e.g., DZ, VH, DL, DC). + + The table has been reviewed, extended and updated to reflect the contents of + the auto configure table in VMS sysgen (V5.5-2) + + A minus number of vectors indicates a field that should be calculated + but not placed in the DIB (RQ, TQ dynamic vectors) + + An amod value of 0 indicates that all addresses are FIXED + An vmod value of 0 indicates that all vectors are FIXED */ + + +typedef struct { + char *dnam[AUTO_MAXC]; + int32 numc; + int32 numv; + uint32 amod; + uint32 vmod; + uint32 fixa[AUTO_MAXC]; + uint32 fixv[AUTO_MAXC]; + } AUTO_CON; + +AUTO_CON auto_tab[] = {/*c #v am vm fxa fxv */ + { { "QBA" }, 1, 0, 0, 0, + {017500} }, /* doorbell - fx CSR, no VEC */ + { { "MCTL" }, 1, 0, 0, 0, + {012100} }, /* MSV11-P - fx CSR, no VEC */ + { { "KE" }, 1, 0, 0, 0, + {017300} }, /* KE11-A - fx CSR, no VEC */ + { { "KG" }, 1, 0, 0, 0, + {010700} }, /* KG11-A - fx CSR, no VEC */ + { { "RHA", "RHB" }, 1, 1, 0, 0, + {016700, 012440}, {0254, 0224} }, /* RH11/RH70 - fx CSR, fx VEC */ + { { "CLK" }, 1, 1, 0, 0, + {017546}, {0100} }, /* KW11L - fx CSR, fx VEC */ + { { "PCLK" }, 1, 1, 0, 0, + {012540}, {0104} }, /* KW11P - fx CSR, fx VEC */ + { { "PTR" }, 1, 1, 0, 0, + {017550}, {0070} }, /* PC11 reader - fx CSR, fx VEC */ + { { "PTP" }, 1, 1, 0, 0, + {017554}, {0074} }, /* PC11 punch - fx CSR, fx VEC */ + { { "RK" }, 1, 1, 0, 0, + {017400}, {0220} }, /* RK11 - fx CSR, fx VEC */ + { { "TM" }, 1, 1, 0, 0, + {012520}, {0224} }, /* TM11 - fx CSR, fx VEC */ + { { "RC" }, 1, 1, 0, 0, + {017440}, {0210} }, /* RC11 - fx CSR, fx VEC */ + { { "RF" }, 1, 1, 0, 0, + {017460}, {0204} }, /* RF11 - fx CSR, fx VEC */ + { { "CR" }, 1, 1, 0, 0, + {017160}, {0230} }, /* CR11 - fx CSR, fx VEC */ + { { "HK" }, 1, 1, 0, 0, + {017440}, {0210} }, /* RK611 - fx CSR, fx VEC */ + { { "LPT" }, 1, 1, 0, 0, + {017514, 004004, 004014, 004024, 004034}, + {0200, 0170, 0174, 0270, 0274} }, /* LP11 - fx CSR, fx VEC */ + { { "RB" }, 1, 1, 0, 0, + {015606}, {0250} }, /* RB730 - fx CSR, fx VEC */ + { { "RL" }, 1, 1, 0, 0, + {014400}, {0160} }, /* RL11 - fx CSR, fx VEC */ + { { "RL" }, 1, 1, 0, 0, + {014400}, {0160} }, /* RL11 - fx CSR, fx VEC */ + { { "DCI" }, 1, 2, 0, 8, + {014000, 014010, 014020, 014030, + 014040, 014050, 014060, 014070, + 014100, 014110, 014120, 014130, + 014140, 014150, 014160, 014170, + 014200, 014210, 014220, 014230, + 014240, 014250, 014260, 014270, + 014300, 014310, 014320, 014330, + 014340, 014350, 014360, 014370} }, /* DC11 - fx CSRs */ + { { NULL }, 1, 2, 0, 8, + {016500, 016510, 016520, 016530, + 016540, 016550, 016560, 016570, + 016600, 016610, 016620, 016630, + 016640, 016650, 016660, 016670} }, /* TU58 - fx CSRs */ + { { NULL }, 1, 1, 0, 4, + {015200, 015210, 015220, 015230, + 015240, 015250, 015260, 015270, + 015300, 015310, 015320, 015330, + 015340, 015350, 015360, 015370} }, /* DN11 - fx CSRs */ + { { NULL }, 1, 1, 0, 4, + {010500, 010510, 010520, 010530, + 010540, 010550, 010560, 010570, + 010600, 010610, 010620, 010630, + 010640, 010650, 010660, 010670} }, /* DM11B - fx CSRs */ + { { NULL }, 1, 2, 0, 8, + {007600, 007570, 007560, 007550, + 007540, 007530, 007520, 007510, + 007500, 007470, 007460, 007450, + 007440, 007430, 007420, 007410} }, /* DR11C - fx CSRs */ + { { NULL }, 1, 1, 0, 8, + {012600, 012604, 012610, 012614, + 012620, 012624, 012620, 012624} }, /* PR611 - fx CSRs */ + { { NULL }, 1, 1, 0, 8, + {017420, 017422, 017424, 017426, + 017430, 017432, 017434, 017436} }, /* DT11 - fx CSRs */ + { { NULL }, 1, 2, 0, 8, + {016200, 016240} }, /* DX11 */ + { { "DLI" }, 1, 2, 0, 8, + {016500, 016510, 016520, 016530, + 016540, 016550, 016560, 016570, + 016600, 016610, 016620, 016630, + 016740, 016750, 016760, 016770} }, /* KL11/DL11/DLV11 - fx CSRs */ + { { NULL }, 1, 2, 0, 8, { 0 } }, /* DLV11J - fx CSRs */ + { { NULL }, 1, 2, 8, 8 }, /* DJ11 */ + { { NULL }, 1, 2, 16, 8 }, /* DH11 */ + { { NULL }, 1, 4, 0, 8, + {012000, 012010, 012020, 012030} }, /* GT40 */ + { { NULL }, 1, 2, 0, 8, + {010400} }, /* LPS11 */ + { { NULL }, 1, 2, 8, 8 }, /* DQ11 */ + { { NULL }, 1, 2, 0, 8, + {012400} }, /* KW11W */ + { { NULL }, 1, 2, 8, 8 }, /* DU11 */ + { { NULL }, 1, 2, 8, 8 }, /* DUP11 */ + { { NULL }, 1, 3, 0, 8, + {015000, 015040, 015100, 015140, }}, /* DV11 */ + { { NULL }, 1, 2, 8, 8 }, /* LK11A */ + { { "DMC0", "DMC1", "DMC2", "DMC3" }, + 1, 2, 8, 8 }, /* DMC11 */ + { { "DZ" }, 1, 2, 8, 8 }, /* DZ11 */ + { { NULL }, 1, 2, 8, 8 }, /* KMC11 */ + { { NULL }, 1, 2, 8, 8 }, /* LPP11 */ + { { NULL }, 1, 2, 8, 8 }, /* VMV21 */ + { { NULL }, 1, 2, 16, 8 }, /* VMV31 */ + { { NULL }, 1, 2, 8, 8 }, /* DWR70 */ + { { "RL", "RLB"}, 1, 1, 8, 4, + {014400}, {0160} }, /* RL11 */ + { { "TS", "TSB", "TSC", "TSD"}, + 1, 1, 0, 4, /* TS11 */ + {012520, 012524, 012530, 012534}, + {0224} }, + { { NULL }, 1, 2, 16, 8, + {010460} }, /* LPA11K */ + { { NULL }, 1, 2, 8, 8 }, /* KW11C */ + { { NULL }, 1, 1, 8, 8 }, /* reserved */ + { { "RX", "RY" }, 1, 1, 8, 4, + {017170} , {0264} }, /* RX11/RX211 */ + { { NULL }, 1, 1, 8, 4 }, /* DR11W */ + { { NULL }, 1, 1, 8, 4, + {012410, 012410}, {0124} }, /* DR11B - fx CSRs,vec */ + { { "DMP" }, 1, 2, 8, 8 }, /* DMP11 */ + { { NULL }, 1, 2, 8, 8 }, /* DPV11 */ + { { NULL }, 1, 2, 8, 8 }, /* ISB11 */ + { { NULL }, 1, 2, 16, 8 }, /* DMV11 */ + { { "XU", "XUB" }, 1, 1, 8, 4, + {014510}, {0120} }, /* DEUNA */ + { { "XQ", "XQB" }, 1, -1, 0, 4, + {014440, 014460, 014520, 014540}, {0120} }, /* DEQNA */ + { { "RQ", "RQB", "RQC", "RQD" }, + 1, -1, 4, 4, /* RQDX3 */ + {012150}, {0154} }, + { { NULL }, 1, 8, 32, 4 }, /* DMF32 */ + { { NULL }, 1, 3, 16, 8 }, /* KMS11 */ + { { NULL }, 1, 2, 0, 8, + {004200, 004240, 004300, 004340} }, /* PLC11 */ + { { NULL }, 1, 1, 16, 4 }, /* VS100 */ + { { "TQ", "TQB" }, 1, -1, 4, 4, + {014500}, {0260} }, /* TQK50 */ + { { NULL }, 1, 2, 16, 8 }, /* KMV11 */ + { { NULL }, 1, 2, 0, 8, + {004400, 004440, 004500, 004540} }, /* KTC32 */ + { { NULL }, 1, 2, 0, 8, + {004100} }, /* IEQ11 */ + { { "VH" }, 1, 2, 16, 8 }, /* DHU11/DHQ11 */ + { { NULL }, 1, 6, 32, 4 }, /* DMZ32 */ + { { NULL }, 1, 6, 32, 4 }, /* CP132 */ + { { "TC" }, 1, 1, 0, 0, + {017340}, {0214} }, /* TC11 */ + { { "TA" }, 1, 1, 0, 0, + {017500}, {0260} }, /* TA11 */ + { { NULL }, 1, 2, 64, 8, + {017200} }, /* QVSS - fx CSR */ + { { NULL }, 1, 1, 8, 4 }, /* VS31 */ + { { NULL }, 1, 1, 0, 4, + {016200} }, /* LNV11 - fx CSR */ + { { NULL }, 1, 1, 16, 4 }, /* LNV21/QPSS */ + { { NULL }, 1, 1, 8, 4, + {012570} }, /* QTA - fx CSR */ + { { NULL }, 1, 1, 8, 4 }, /* DSV11 */ + { { NULL }, 1, 2, 8, 8 }, /* CSAM */ + { { NULL }, 1, 2, 8, 8 }, /* ADV11C */ + { { NULL }, 1, 0, 8, 8, + {010440} }, /* AAV11/AAV11C */ + { { NULL }, 1, 2, 8, 8, + {016400}, {0140} }, /* AXV11C - fx CSR,vec */ + { { NULL }, 1, 2, 4, 8, + {010420} }, /* KWV11C - fx CSR */ + { { NULL }, 1, 2, 8, 8, + {016410} }, /* ADV11D - fx CSR */ + { { NULL }, 1, 2, 8, 8, + {016420} }, /* AAV11D - fx CSR */ + { { "QDSS" }, 1, 3, 0, 16, + {017400, 017402, 017404, 017406, + 017410, 017412, 017414, 017416} }, /* VCB02 - QDSS - fx CSR */ + { { NULL }, 1, 16, 0, 4, + {004160, 004140, 004120} }, /* DRV11J - fx CSR */ + { { NULL }, 1, 2, 16, 8 }, /* DRQ3B */ + { { NULL }, 1, 1, 8, 4 }, /* VSV24 */ + { { NULL }, 1, 1, 8, 4 }, /* VSV21 */ + { { NULL }, 1, 1, 8, 4 }, /* IBQ01 */ + { { NULL }, 1, 1, 8, 8 }, /* IDV11A */ + { { NULL }, 1, 0, 8, 8 }, /* IDV11B */ + { { NULL }, 1, 0, 8, 8 }, /* IDV11C */ + { { NULL }, 1, 1, 8, 8 }, /* IDV11D */ + { { NULL }, 1, 2, 8, 8 }, /* IAV11A */ + { { NULL }, 1, 0, 8, 8 }, /* IAV11B */ + { { NULL }, 1, 2, 8, 8 }, /* MIRA */ + { { NULL }, 1, 2, 16, 8 }, /* IEQ11 */ + { { NULL }, 1, 2, 32, 8 }, /* ADQ32 */ + { { NULL }, 1, 2, 8, 8 }, /* DTC04, DECvoice */ + { { NULL }, 1, 1, 32, 4 }, /* DESNA */ + { { NULL }, 1, 2, 4, 8 }, /* IGQ11 */ + { { NULL }, 1, 2, 32, 8 }, /* KMV1F */ + { { NULL }, 1, 1, 8, 4 }, /* DIV32 */ + { { NULL }, 1, 2, 4, 8 }, /* DTCN5, DECvoice */ + { { NULL }, 1, 2, 4, 8 }, /* DTC05, DECvoice */ + { { NULL }, 1, 2, 8, 8 }, /* KWV32 (DSV11) */ + { { NULL }, 1, 1, 64, 4 }, /* QZA */ + { { NULL }, -1 } /* end table */ +}; + +#if !defined(DEV_NEXUS) +#if defined(DEV_MBUS) +#define DEV_NEXUS DEV_MBUS +#else +#define DEV_NEXUS 0 +#endif +#endif +t_stat auto_config (char *name, int32 nctrl) { +uint32 csr = IOPAGEBASE + AUTO_CSRBASE; +uint32 vec = VEC_Q + AUTO_VECBASE; +AUTO_CON *autp; +DEVICE *dptr; +DIB *dibp; +uint32 j, vmask, amask; + +if (autcon_enb == 0) /* enabled? */ + return SCPE_OK; +if (name) { /* updating? */ + if (nctrl < 0) + return SCPE_ARG; + for (autp = auto_tab; autp->numc >= 0; autp++) { + for (j = 0; (j < AUTO_MAXC) && autp->dnam[j]; j++) { + if (strcmp (name, autp->dnam[j]) == 0) + autp->numc = nctrl; + } + } + } +for (autp = auto_tab; autp->numc >= 0; autp++) { /* loop thru table */ + if (autp->amod) { /* floating csr? */ + amask = autp->amod - 1; + csr = (csr + amask) & ~amask; /* align csr */ + } + for (j = 0; (j < AUTO_MAXC) && autp->dnam[j]; j++) { + if (autp->dnam[j] == NULL) /* no device? */ + break; + dptr = find_dev (autp->dnam[j]); /* find ctrl */ + if ((dptr == NULL) || /* enabled, not nexus? */ + (dptr->flags & DEV_DIS) || + (dptr->flags & DEV_NEXUS) ) + continue; + dibp = (DIB *) dptr->ctxt; /* get DIB */ + if (dibp == NULL) /* not there??? */ + return SCPE_IERR; + if (autp->fixa[j]) /* fixed csr avail? */ + dibp->ba = IOPAGEBASE + autp->fixa[j]; /* use it */ + else { /* no fixed left */ + dibp->ba = csr; /* set CSR */ + csr += (autp->numc * autp->amod); /* next CSR */ + } /* end else */ + if (autp->numv) { /* vec needed? */ + if (autp->fixv[j]) { /* fixed vec avail? */ + if (autp->numv > 0) + dibp->vec = VEC_Q + autp->fixv[j]; /* use it */ + } + else { /* no fixed left */ + uint32 numv = abs (autp->numv); /* get num vec */ + vmask = autp->vmod - 1; + vec = (vec + vmask) & ~vmask; /* align vector */ + if (autp->numv > 0) + dibp->vec = vec; /* set vector */ + vec += (autp->numc * numv * 4); + } /* end else */ + } /* end vec needed */ + } /* end for j */ + if (autp->amod) /* flt CSR? gap */ + csr = csr + 2; + } /* end for i */ return SCPE_OK; } -/* Stub floating address */ + +/* Set address floating */ t_stat set_addr_flt (UNIT *uptr, int32 val, char *cptr, void *desc) { -return SCPE_OK; +DEVICE *dptr; + +if (cptr != NULL) + return SCPE_ARG; +if (uptr == NULL) + return SCPE_IERR; +dptr = find_dev_from_unit (uptr); +if (dptr == NULL) + return SCPE_IERR; +return auto_config (NULL, 0); /* autoconfigure */ } + diff --git a/PDP10/pdp10_rp.c b/PDP10/pdp10_rp.c index a5997728..14a7a45a 100644 --- a/PDP10/pdp10_rp.c +++ b/PDP10/pdp10_rp.c @@ -1167,7 +1167,8 @@ if (sim_is_active (uptr)) { /* unit active? */ if (uptr->FUNC >= FNC_WCHK) /* data transfer? */ rpcs1 = rpcs1 | CS1_DONE | CS1_TRE; /* set done, err */ } -update_rpcs (CS1_SC, drv); /* request intr */ +if (!sim_is_running) /* from console? */ + update_rpcs (CS1_SC, drv); /* request intr */ return detach_unit (uptr); } @@ -1284,7 +1285,7 @@ static const d10 boot_rom_its[] = { t_stat rp_boot (int32 unitno, DEVICE *dptr) { -int32 i; +size_t i; extern a10 saved_PC; M[FE_UNIT] = unitno & CS2_M_UNIT; diff --git a/PDP10/pdp10_sys.c b/PDP10/pdp10_sys.c index 24ec2d48..12a4b664 100644 --- a/PDP10/pdp10_sys.c +++ b/PDP10/pdp10_sys.c @@ -338,7 +338,6 @@ t_stat sim_load (FILE *fileref, char *cptr, char *fnam, int flag) { d10 data; int32 wc, fmt; -extern int32 sim_switches; fmt = 0; /* no fmt */ if (sim_switches & SWMASK ('R')) /* -r? */ diff --git a/PDP10/pdp10_tim.c b/PDP10/pdp10_tim.c index c15cd503..b9bbdfc1 100644 --- a/PDP10/pdp10_tim.c +++ b/PDP10/pdp10_tim.c @@ -154,7 +154,7 @@ tempbase[1] = tim_base[1]; if (tim_mult != TIM_MULT_T20) { /* interpolate? */ int32 used; d10 incr; - used = tmr_poll - (sim_is_active (&tim_unit) - 1); + used = tmr_poll - (sim_activate_time (&tim_unit) - 1); incr = (d10) (((double) used * TIM_HW_FREQ) / ((double) tmr_poll * (double) clk_tps)); tim_incr_base (tempbase, incr); @@ -211,18 +211,6 @@ else if (t20_idlelock && PROB (100 - tim_t20_prob)) return SCPE_OK; } -/* Clock coscheduling routine */ - -int32 clk_cosched (int32 wait) -{ -int32 t; - -if (tim_mult == TIM_MULT_T20) - return wait; -t = sim_is_active (&tim_unit); -return (t? t - 1: wait); -} - void tim_incr_base (d10 *base, d10 incr) { base[1] = base[1] + incr; /* add on incr */ diff --git a/PDP10/pdp10_tu.c b/PDP10/pdp10_tu.c index 6be277b8..d24f57ca 100644 --- a/PDP10/pdp10_tu.c +++ b/PDP10/pdp10_tu.c @@ -297,8 +297,6 @@ extern int32 int_req; extern int32 ubmap[UBANUM][UMAP_MEMSIZE]; /* Unibus map */ extern int32 ubcs[UBANUM]; extern UNIT cpu_unit; -extern int32 sim_switches; -extern FILE *sim_deb; int32 tucs1 = 0; /* control/status 1 */ int32 tuwc = 0; /* word count */ @@ -415,7 +413,7 @@ DEVICE tu_dev = { TU_NUMDR, 10, 31, 1, 8, 8, NULL, NULL, &tu_reset, &tu_boot, &tu_attach, &tu_detach, - &tu_dib, DEV_UBUS | DEV_DEBUG + &tu_dib, DEV_UBUS | DEV_DEBUG | DEV_TAPE }; /* I/O dispatch routine, I/O addresses 17772440 - 17772472 */ @@ -1015,7 +1013,7 @@ return; void update_tucs (int32 flag, int32 drv) { -int32 act = sim_is_active (&tu_unit[drv]); +int32 act = sim_activate_time (&tu_unit[drv]); if ((flag & ~tucs1) & CS1_DONE) /* DONE 0 to 1? */ tuiff = (tucs1 & CS1_IE)? 1: 0; /* CSTB INTR <- IE */ @@ -1273,7 +1271,7 @@ static const d10 boot_rom_its[] = { t_stat tu_boot (int32 unitno, DEVICE *dptr) { -int32 i; +size_t i; extern a10 saved_PC; M[FE_UNIT] = 0; diff --git a/PDP11/pdp11_cis.c b/PDP11/pdp11_cis.c index 9f78f1bd..16ba673e 100644 --- a/PDP11/pdp11_cis.c +++ b/PDP11/pdp11_cis.c @@ -170,14 +170,12 @@ typedef struct { uint32 val[DSTRLNT]; } DSTR; -static DSTR Dstr0 = { 0, 0, 0, 0, 0 }; +static DSTR Dstr0 = { 0, {0, 0, 0, 0} }; extern int32 isenable, dsenable; extern int32 N, Z, V, C, fpd, ipl; extern int32 R[8], trap_req; -extern int32 sim_interval; extern uint32 cpu_type; -extern FILE *sim_deb; int32 ReadDstr (int32 *dscr, DSTR *dec, int32 flag); void WriteDstr (int32 *dscr, DSTR *dec, int32 flag); @@ -321,14 +319,12 @@ static int32 overbin[128] = { /* Overpunch to ASCII table: indexed by sign and digit */ static int32 binover[2][16] = { - '{', 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', - '0', '0', '0', '0', '0', '0', - '}', 'J', 'K', 'L', 'M', 'N', 'O', 'P', 'Q', 'R', - '0', '0', '0', '0', '0', '0' + {'{', 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', + '0', '0', '0', '0', '0', '0'}, + {'}', 'J', 'K', 'L', 'M', 'N', 'O', 'P', 'Q', 'R', + '0', '0', '0', '0', '0', '0'} }; -static unsigned char movbuf[65536]; - /* CIS emulator */ t_stat cis11 (int32 IR) @@ -342,7 +338,7 @@ uint32 nc, digit, result; t_stat st; static DSTR accum, src1, src2, dst; static DSTR mptable[10]; -static DSTR Dstr1 = { 0, 0x10, 0, 0, 0 }; +static DSTR Dstr1 = { 0, {0x10, 0, 0, 0} }; old_PC = (PC - 2) & 0177777; /* original PC */ op = IR & 0177; /* IR <6:0> */ diff --git a/PDP11/pdp11_cpu.c b/PDP11/pdp11_cpu.c index cc63549f..96049f30 100644 --- a/PDP11/pdp11_cpu.c +++ b/PDP11/pdp11_cpu.c @@ -25,6 +25,7 @@ cpu PDP-11 CPU + 29-Apr-12 RMS Fixed compiler warning (Mark Pizzolato) 19-Mar-12 RMS Fixed declaration of sim_switches (Mark Pizzolato) 29-Dec-08 RMS Fixed failure to clear cpu_bme on RESET (Walter Mueller) 22-Apr-08 RMS Fixed MMR0 treatment in RESET (Walter Mueller) @@ -255,7 +256,7 @@ typedef struct { extern FILE *sim_log; uint16 *M = NULL; /* memory */ -int32 REGFILE[6][2] = { 0 }; /* R0-R5, two sets */ +int32 REGFILE[6][2] = { {0} }; /* R0-R5, two sets */ int32 STACKFILE[4] = { 0 }; /* SP, four modes */ int32 saved_PC = 0; /* program counter */ int32 R[8] = { 0 }; /* working registers */ @@ -272,7 +273,7 @@ int32 trap_req = 0; /* trap requests */ int32 int_req[IPL_HLVL] = { 0 }; /* interrupt requests */ int32 PIRQ = 0; /* programmed int req */ int32 STKLIM = 0; /* stack limit */ -fpac_t FR[6] = { 0 }; /* fp accumulators */ +fpac_t FR[6] = { {0} }; /* fp accumulators */ int32 FPS = 0; /* fp status */ int32 FEC = 0; /* fp exception code */ int32 FEA = 0; /* fp exception addr */ @@ -303,12 +304,6 @@ int32 dsmask[4] = { MMR3_KDS, MMR3_SDS, 0, MMR3_UDS }; /* dspace enables */ t_addr cpu_memsize = INIMEMSIZE; /* last mem addr */ extern int32 CPUERR, MAINT; -extern int32 sim_interval; -extern int32 sim_int_char; -extern int32 sim_switches; -extern uint32 sim_brk_types, sim_brk_dflt, sim_brk_summ; /* breakpoint info */ -extern t_bool sim_idle_enab; -extern DEVICE *sim_devices[]; extern CPUTAB cpu_tab[]; /* Function declarations */ @@ -605,6 +600,7 @@ MTAB cpu_mod[] = { { UNIT_MSIZE, 524288, NULL, "512K", &cpu_set_size}, { UNIT_MSIZE, 786432, NULL, "768K", &cpu_set_size}, { UNIT_MSIZE, 1048576, NULL, "1024K", &cpu_set_size}, + { UNIT_MSIZE, 1572864, NULL, "1536K", &cpu_set_size}, { UNIT_MSIZE, 2097152, NULL, "2048K", &cpu_set_size}, { UNIT_MSIZE, 3145728, NULL, "3072K", &cpu_set_size}, { UNIT_MSIZE, 4186112, NULL, "4096K", &cpu_set_size}, @@ -1245,7 +1241,7 @@ while (reason == 0) { else dst = R[dstspec]; } else { - i = ((cm == pm) && (cm == MD_USR))? calc_ds (pm): calc_is (pm); + i = ((cm == pm) && (cm == MD_USR))? (int32)calc_ds (pm): (int32)calc_is (pm); dst = ReadW ((GeteaW (dstspec) & 0177777) | i); } N = GET_SIGN_W (dst); @@ -3115,8 +3111,6 @@ char *cptr = (char *) desc; t_value sim_eval[HIST_ILNT]; t_stat r; InstHistory *h; -extern t_stat fprint_sym (FILE *ofile, t_addr addr, t_value *val, - UNIT *uptr, int32 sw); if (hst_lnt == 0) /* enabled? */ return SCPE_NOFNC; diff --git a/PDP11/pdp11_cpumod.c b/PDP11/pdp11_cpumod.c index faf5a2b2..57d3c252 100644 --- a/PDP11/pdp11_cpumod.c +++ b/PDP11/pdp11_cpumod.c @@ -84,13 +84,11 @@ static int32 clk_tps_map[4] = { 60, 60, 50, 800 }; extern uint16 *M; extern int32 R[8]; -extern DEVICE cpu_dev, *sim_devices[]; +extern DEVICE cpu_dev; extern UNIT cpu_unit; -extern FILE *sim_log; extern int32 STKLIM, PIRQ; extern uint32 cpu_model, cpu_type, cpu_opt; extern int32 clk_fie, clk_fnxm, clk_tps, clk_default; -extern int32 sim_switches; t_stat CPU24_rd (int32 *data, int32 addr, int32 access); t_stat CPU24_wr (int32 data, int32 addr, int32 access); @@ -1159,7 +1157,7 @@ if ((mc != 0) && !get_yn ("Really truncate memory [N]?", FALSE)) nM = (uint16 *) calloc (val >> 1, sizeof (uint16)); if (nM == NULL) return SCPE_MEM; -clim = (((t_addr) val) < MEMSIZE)? val: MEMSIZE; +clim = (((t_addr) val) < MEMSIZE)? (uint32)val: MEMSIZE; for (i = 0; i < clim; i = i + 2) nM[i >> 1] = M[i >> 1]; free (M); diff --git a/PDP11/pdp11_cr.c b/PDP11/pdp11_cr.c index 521f3edd..175c35b3 100644 --- a/PDP11/pdp11_cr.c +++ b/PDP11/pdp11_cr.c @@ -186,8 +186,6 @@ extern int32 int_req[IPL_HLVL]; #define DFLT_CPM 285 #endif -extern FILE *sim_deb; /* sim_console.c */ - /* create a int32 constant from four characters */ #define I4C(a,b,c,d) (((a) << 24) | ((b) << 16) | ((c) << 8) | (d)) #define I4C_CBN I4C ('C','B','N',' ') @@ -345,8 +343,10 @@ t_stat cr_show_trans (FILE *, UNIT *, int32, void *); cr_dev CR device descriptor */ -static DIB cr_dib = { IOBA_CR, IOLN_CR, &cr_rd, &cr_wr, - 1, IVCL (CR), VEC_CR, { NULL } }; +#define IOLN_CR 010 + +static DIB cr_dib = { IOBA_AUTO, IOLN_CR, &cr_rd, &cr_wr, + 1, IVCL (CR), VEC_AUTO, { NULL } }; static UNIT cr_unit = { UDATA (&cr_svc, @@ -1085,7 +1085,7 @@ t_stat cr_reset ( DEVICE *dptr ) CLR_INT (CR); /* TBD: flush current card */ /* init uptr->wait ? */ - return (SCPE_OK); + return auto_config (dptr->name, 1); } /* @@ -1100,7 +1100,6 @@ t_stat cr_attach ( UNIT *uptr, char *cptr ) { t_stat reason; - extern int32 sim_switches; if (sim_switches & ~MASK) return (SCPE_INVSW); diff --git a/PDP11/pdp11_dc.c b/PDP11/pdp11_dc.c index 1c653fe8..392bc9c7 100644 --- a/PDP11/pdp11_dc.c +++ b/PDP11/pdp11_dc.c @@ -86,7 +86,7 @@ uint32 dci_ireq = 0; uint16 dco_csr[DCX_LINES] = { 0 }; /* control/status */ uint8 dco_buf[DCX_LINES] = { 0 }; uint32 dco_ireq = 0; -TMLN dcx_ldsc[DCX_LINES] = { 0 }; /* line descriptors */ +TMLN dcx_ldsc[DCX_LINES] = { {0} }; /* line descriptors */ TMXR dcx_desc = { DCX_LINES, 0, 0, dcx_ldsc }; /* mux descriptor */ static const uint8 odd_par[] = { @@ -148,9 +148,11 @@ void dcx_reset_ln (int32 ln); dci_reg DCI register list */ +#define IOLN_DC 010 + DIB dci_dib = { - IOBA_DC, IOLN_DC, &dcx_rd, &dcx_wr, - 2, IVCL (DCI), VEC_DCI, { &dci_iack, &dco_iack } + IOBA_AUTO, IOLN_DC * DCX_LINES, &dcx_rd, &dcx_wr, + 2, IVCL (DCI), VEC_AUTO, { &dci_iack, &dco_iack } }; UNIT dci_unit = { UDATA (&dci_svc, 0, 0), KBD_POLL_WAIT }; @@ -191,7 +193,7 @@ DEVICE dci_dev = { 1, 10, 31, 1, 8, 8, NULL, NULL, &dcx_reset, NULL, &dcx_attach, &dcx_detach, - &dci_dib, DEV_FLTA | DEV_UBUS | DEV_QBUS | DEV_DISABLE | DEV_DIS + &dci_dib, DEV_UBUS | DEV_QBUS | DEV_DISABLE | DEV_DIS | DEV_MUX }; /* DCO data structures @@ -368,7 +370,7 @@ int32 ln, c, temp; if ((uptr->flags & UNIT_ATT) == 0) /* attached? */ return SCPE_OK; -sim_activate (uptr, clk_cosched (tmxr_poll)); /* continue poll */ +sim_clock_coschedule (uptr, tmxr_poll); /* continue poll */ ln = tmxr_poll_conn (&dcx_desc); /* look for connect */ if (ln >= 0) { /* got one? */ dcx_ldsc[ln].rcve = 1; /* set rcv enb */ diff --git a/PDP11/pdp11_defs.h b/PDP11/pdp11_defs.h index 8f2d07ab..3c12824f 100644 --- a/PDP11/pdp11_defs.h +++ b/PDP11/pdp11_defs.h @@ -175,6 +175,7 @@ #define CPUT(x) ((cpu_type & (x)) != 0) #define CPUO(x) ((cpu_opt & (x)) != 0) #define UNIBUS (cpu_opt & BUS_U) +extern uint32 cpu_model, cpu_type, cpu_opt; /* Feature sets @@ -488,13 +489,11 @@ typedef struct { #define DEV_V_UBUS (DEV_V_UF + 0) /* Unibus */ #define DEV_V_QBUS (DEV_V_UF + 1) /* Qbus */ #define DEV_V_Q18 (DEV_V_UF + 2) /* Qbus with <= 256KB */ -#define DEV_V_FLTA (DEV_V_UF + 3) /* flt addr */ -#define DEV_V_MBUS (DEV_V_UF + 4) /* Massbus */ -#define DEV_V_FFUF (DEV_V_UF + 5) /* first free flag */ +#define DEV_V_MBUS (DEV_V_UF + 3) /* Massbus */ +#define DEV_V_FFUF (DEV_V_UF + 4) /* first free flag */ #define DEV_UBUS (1u << DEV_V_UBUS) #define DEV_QBUS (1u << DEV_V_QBUS) #define DEV_Q18 (1u << DEV_V_Q18) -#define DEV_FLTA (1u << DEV_V_FLTA) #define DEV_MBUS (1u << DEV_V_MBUS) #define DEV_RDX 8 /* default device radix */ @@ -516,26 +515,44 @@ struct pdp_dib { typedef struct pdp_dib DIB; -/* I/O page layout - XUB, RQB,RQC,RQD float based on number of DZ's */ +/* Unibus I/O page layout - see pdp11_ui_lib.c for address layout details + Massbus devices (RP, TU) do not appear in the Unibus IO page */ -#define IOBA_DZ (IOPAGEBASE + 000100) /* DZ11 */ -#define IOLN_DZ 010 -#define IOBA_XUB (IOPAGEBASE + 000330 + (020 * (DZ_MUXES / 2))) -#define IOLN_XUB 010 -#define IOBA_RQB (IOPAGEBASE + 000334 + (020 * (DZ_MUXES / 2))) -#define IOLN_RQB 004 -#define IOBA_RQC (IOPAGEBASE + IOBA_RQB + IOLN_RQB) -#define IOLN_RQC 004 -#define IOBA_RQD (IOPAGEBASE + IOBA_RQC + IOLN_RQC) -#define IOLN_RQD 004 -#define IOBA_VH (IOPAGEBASE + 000440) /* DHQ11 */ -#define IOLN_VH 020 +#define IOBA_AUTO (0) /* Assigned by Auto Configure */ + +/* Processor registers which have I/O page addresses + */ + +#define IOBA_CTL (IOPAGEBASE + 017520) /* board ctrl */ +#define IOLN_CTL 010 #define IOBA_UBM (IOPAGEBASE + 010200) /* Unibus map */ #define IOLN_UBM (UBM_LNT_LW * sizeof (int32)) -#define IOBA_KG (IOPAGEBASE + 010700) /* KG11-A */ -#define IOLN_KG 006 -#define IOBA_RQ (IOPAGEBASE + 012150) /* RQDX3 */ -#define IOLN_RQ 004 +#define IOBA_MMR3 (IOPAGEBASE + 012516) /* MMR3 */ +#define IOLN_MMR3 002 +#define IOBA_TTI (IOPAGEBASE + 017560) /* DL11 rcv */ +#define IOLN_TTI 004 +#define IOBA_TTO (IOPAGEBASE + 017564) /* DL11 xmt */ +#define IOLN_TTO 004 +#define IOBA_SR (IOPAGEBASE + 017570) /* SR */ +#define IOLN_SR 002 +#define IOBA_MMR012 (IOPAGEBASE + 017572) /* MMR0-2 */ +#define IOLN_MMR012 006 +#define IOBA_GPR (IOPAGEBASE + 017700) /* GPR's */ +#define IOLN_GPR 010 +#define IOBA_UCTL (IOPAGEBASE + 017730) /* UBA ctrl */ +#define IOLN_UCTL 010 +#define IOBA_CPU (IOPAGEBASE + 017740) /* CPU reg */ +#define IOLN_CPU 036 +#define IOBA_PSW (IOPAGEBASE + 017776) /* PSW */ +#define IOLN_PSW 002 +#define IOBA_UIPDR (IOPAGEBASE + 017600) /* user APR's */ +#define IOLN_UIPDR 020 +#define IOBA_UDPDR (IOPAGEBASE + 017620) +#define IOLN_UDPDR 020 +#define IOBA_UIPAR (IOPAGEBASE + 017640) +#define IOLN_UIPAR 020 +#define IOBA_UDPAR (IOPAGEBASE + 017660) +#define IOLN_UDPAR 020 #define IOBA_SUP (IOPAGEBASE + 012200) /* supervisor APR's */ #define IOLN_SUP 0100 #define IOBA_KIPDR (IOPAGEBASE + 012300) /* kernel APR's */ @@ -546,88 +563,6 @@ typedef struct pdp_dib DIB; #define IOLN_KIPAR 020 #define IOBA_KDPAR (IOPAGEBASE + 012360) #define IOLN_KDPAR 020 -#define IOBA_TU (IOPAGEBASE + 012440) /* TU */ -#define IOLN_TU 040 -#define IOBA_MMR3 (IOPAGEBASE + 012516) /* MMR3 */ -#define IOLN_MMR3 002 -#define IOBA_TM (IOPAGEBASE + 012520) /* TM11 */ -#define IOLN_TM 014 -#define IOBA_TS (IOPAGEBASE + 012520) /* TS11 */ -#define IOLN_TS 004 -#define IOBA_PCLK (IOPAGEBASE + 012540) /* KW11P */ -#define IOLN_PCLK 006 -#define IOBA_DC (IOPAGEBASE + 014000) /* DC11 */ -#define IOLN_DC (DCX_LINES * 010) -#define IOBA_RL (IOPAGEBASE + 014400) /* RL11 */ -#define IOLN_RL 012 -#define IOBA_XQ (IOPAGEBASE + 014440) /* DEQNA/DELQA */ -#define IOLN_XQ 020 -#define IOBA_XQB (IOPAGEBASE + 014460) /* 2nd DEQNA/DELQA */ -#define IOLN_XQB 020 -#define IOBA_TQ (IOPAGEBASE + 014500) /* TMSCP */ -#define IOLN_TQ 004 -#define IOBA_XU (IOPAGEBASE + 014510) /* DEUNA/DELUA */ -#define IOLN_XU 010 -#define IOBA_DL (IOPAGEBASE + 016500) /* extra KL11/DL11 */ -#define IOLN_DL (DLX_LINES * 010) -#define IOBA_RP (IOPAGEBASE + 016700) /* RP/RM */ -#define IOLN_RP 054 -#define IOBA_CR (IOPAGEBASE + 017160) /* CD/CR/CM */ -#define IOLN_CR 010 -#define IOBA_RX (IOPAGEBASE + 017170) /* RX11 */ -#define IOLN_RX 004 -#define IOBA_RY (IOPAGEBASE + 017170) /* RY11 */ -#define IOLN_RY 004 -#define IOBA_KE (IOPAGEBASE + 017300) /* KE11-A */ -#define IOLN_KE 020 -#define IOBA_TC (IOPAGEBASE + 017340) /* TC11 */ -#define IOLN_TC 012 -#define IOBA_QDSS (IOPAGEBASE + 017400) /* QDSS */ -#define IOLN_QDSS 002 -#define IOBA_RK (IOPAGEBASE + 017400) /* RK11 */ -#define IOLN_RK 020 -#define IOBA_RC (IOPAGEBASE + 017440) /* RC11/RS64 */ -#define IOLN_RC 020 -#define IOBA_HK (IOPAGEBASE + 017440) /* RK611 */ -#define IOLN_HK 040 -#define IOBA_RF (IOPAGEBASE + 017460) /* RF11 */ -#define IOLN_RF 020 -#define IOBA_TA (IOPAGEBASE + 017500) /* TA11 */ -#define IOLN_TA 004 -#define IOBA_LPT (IOPAGEBASE + 017514) /* LP11 */ -#define IOLN_LPT 004 -#define IOBA_CTL (IOPAGEBASE + 017520) /* board ctrl */ -#define IOLN_CTL 010 -#define IOBA_CLK (IOPAGEBASE + 017546) /* KW11L */ -#define IOLN_CLK 002 -#define IOBA_PTR (IOPAGEBASE + 017550) /* PC11 reader */ -#define IOLN_PTR 004 -#define IOBA_PTP (IOPAGEBASE + 017554) /* PC11 punch */ -#define IOLN_PTP 004 -#define IOBA_TTI (IOPAGEBASE + 017560) /* DL11 rcv */ -#define IOLN_TTI 004 -#define IOBA_TTO (IOPAGEBASE + 017564) /* DL11 xmt */ -#define IOLN_TTO 004 -#define IOBA_SR (IOPAGEBASE + 017570) /* SR */ -#define IOLN_SR 002 -#define IOBA_MMR012 (IOPAGEBASE + 017572) /* MMR0-2 */ -#define IOLN_MMR012 006 -#define IOBA_UIPDR (IOPAGEBASE + 017600) /* user APR's */ -#define IOLN_UIPDR 020 -#define IOBA_UDPDR (IOPAGEBASE + 017620) -#define IOLN_UDPDR 020 -#define IOBA_UIPAR (IOPAGEBASE + 017640) -#define IOLN_UIPAR 020 -#define IOBA_UDPAR (IOPAGEBASE + 017660) -#define IOLN_UDPAR 020 -#define IOBA_GPR (IOPAGEBASE + 017700) /* GPR's */ -#define IOLN_GPR 010 -#define IOBA_UCTL (IOPAGEBASE + 017730) /* UBA ctrl */ -#define IOLN_UCTL 010 -#define IOBA_CPU (IOPAGEBASE + 017740) /* CPU reg */ -#define IOLN_CPU 036 -#define IOBA_PSW (IOPAGEBASE + 017776) /* PSW */ -#define IOLN_PSW 002 /* Interrupt assignments; within each level, priority is right to left PIRQn has the highest priority with a level and is always bit <0> @@ -662,6 +597,8 @@ typedef struct pdp_dib DIB; #define INT_V_TU 15 #define INT_V_RF 16 #define INT_V_RC 17 +#define INT_V_DMCRX 18 +#define INT_V_DMCTX 19 #define INT_V_PIR4 0 /* BR4 */ #define INT_V_TTI 1 @@ -705,6 +642,8 @@ typedef struct pdp_dib DIB; #define INT_TU (1u << INT_V_TU) #define INT_RF (1u << INT_V_RF) #define INT_RC (1u << INT_V_RC) +#define INT_DMCRX (1u << INT_V_DMCRX) +#define INT_DMCTX (1u << INT_V_DMCTX) #define INT_PIR4 (1u << INT_V_PIR4) #define INT_TTI (1u << INT_V_TTI) #define INT_TTO (1u << INT_V_TTO) @@ -751,6 +690,8 @@ typedef struct pdp_dib DIB; #define IPL_TU 5 #define IPL_RF 5 #define IPL_RC 5 +#define IPL_DMCRX 5 +#define IPL_DMCTX 5 #define IPL_PTR 4 #define IPL_PTP 4 #define IPL_TTI 4 @@ -774,41 +715,15 @@ typedef struct pdp_dib DIB; /* Device vectors */ +#define VEC_AUTO (0) /* Assigned by Auto Configure */ +#define VEC_FLOAT (0) /* Assigned by Auto Configure */ + #define VEC_Q 0000 /* vector base */ + +/* Processor specific internal fixed vectors */ #define VEC_PIRQ 0240 #define VEC_TTI 0060 #define VEC_TTO 0064 -#define VEC_PTR 0070 -#define VEC_PTP 0074 -#define VEC_CLK 0100 -#define VEC_PCLK 0104 -#define VEC_XQ 0120 -#define VEC_XU 0120 -#define VEC_RQ 0154 -#define VEC_RL 0160 -#define VEC_LPT 0200 -#define VEC_RF 0204 -#define VEC_HK 0210 -#define VEC_RC 0210 -#define VEC_RK 0220 -#define VEC_DTA 0214 -#define VEC_TM 0224 -#define VEC_TS 0224 -#define VEC_TU 0224 -#define VEC_CR 0230 -#define VEC_RP 0254 -#define VEC_TQ 0260 -#define VEC_TA 0260 -#define VEC_RX 0264 -#define VEC_RY 0264 -#define VEC_DLI 0300 -#define VEC_DLO 0304 -#define VEC_DCI 0300 -#define VEC_DCO 0304 -#define VEC_DZRX 0300 -#define VEC_DZTX 0304 -#define VEC_VHRX 0310 -#define VEC_VHTX 0314 /* Interrupt macros */ @@ -854,8 +769,6 @@ void mba_set_don (uint32 mbus); void mba_set_enbdis (uint32 mb, t_bool dis); t_stat mba_show_num (FILE *st, UNIT *uptr, int32 val, void *desc); -int32 clk_cosched (int32 wait); - #include "pdp11_io_lib.h" #endif diff --git a/PDP11/pdp11_dl.c b/PDP11/pdp11_dl.c index ec8cc9ab..6adaf578 100644 --- a/PDP11/pdp11_dl.c +++ b/PDP11/pdp11_dl.c @@ -87,7 +87,7 @@ uint32 dli_ireq[2] = { 0, 0}; uint16 dlo_csr[DLX_LINES] = { 0 }; /* control/status */ uint8 dlo_buf[DLX_LINES] = { 0 }; uint32 dlo_ireq = 0; -TMLN dlx_ldsc[DLX_LINES] = { 0 }; /* line descriptors */ +TMLN dlx_ldsc[DLX_LINES] = { {0} }; /* line descriptors */ TMXR dlx_desc = { DLX_LINES, 0, 0, dlx_ldsc }; /* mux descriptor */ t_stat dlx_rd (int32 *data, int32 PA, int32 access); @@ -114,9 +114,11 @@ void dlx_reset_ln (int32 ln); dli_reg DLI register list */ +#define IOLN_DL 010 + DIB dli_dib = { - IOBA_DL, IOLN_DL, &dlx_rd, &dlx_wr, - 2, IVCL (DLI), VEC_DLI, { &dli_iack, &dlo_iack } + IOBA_AUTO, IOLN_DL * DLX_LINES, &dlx_rd, &dlx_wr, + 2, IVCL (DLI), VEC_AUTO, { &dli_iack, &dlo_iack } }; UNIT dli_unit = { UDATA (&dli_svc, 0, 0), KBD_POLL_WAIT }; @@ -158,7 +160,7 @@ DEVICE dli_dev = { 1, 10, 31, 1, 8, 8, NULL, NULL, &dlx_reset, NULL, &dlx_attach, &dlx_detach, - &dli_dib, DEV_FLTA | DEV_UBUS | DEV_QBUS | DEV_DISABLE | DEV_DIS + &dli_dib, DEV_UBUS | DEV_QBUS | DEV_DISABLE | DEV_DIS }; /* DLO data structures @@ -217,7 +219,7 @@ DEVICE dlo_dev = { DLX_LINES, 10, 31, 1, 8, 8, NULL, NULL, &dlx_reset, NULL, NULL, NULL, - NULL, DEV_UBUS | DEV_QBUS | DEV_DISABLE | DEV_DIS + NULL, DEV_UBUS | DEV_QBUS | DEV_DISABLE | DEV_DIS | DEV_MUX }; /* Terminal input routines */ @@ -331,7 +333,7 @@ int32 ln, c, temp; if ((uptr->flags & UNIT_ATT) == 0) /* attached? */ return SCPE_OK; -sim_activate (uptr, clk_cosched (tmxr_poll)); /* continue poll */ +sim_clock_coschedule (uptr, tmxr_poll); /* continue poll */ ln = tmxr_poll_conn (&dlx_desc); /* look for connect */ if (ln >= 0) { /* got one? rcv enb */ dlx_ldsc[ln].rcve = 1; diff --git a/PDP11/pdp11_dmc.c b/PDP11/pdp11_dmc.c new file mode 100644 index 00000000..ada43d0d --- /dev/null +++ b/PDP11/pdp11_dmc.c @@ -0,0 +1,2266 @@ +/* pdp11_dmc.c: DMC11 Emulation + ------------------------------------------------------------------------------ + + Copyright (c) 2011, Robert M. A. Jarratt + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHOR BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name of the author shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from the author. + + ------------------------------------------------------------------------------ + + +I/O is done through sockets so that the remote system can be on the same host machine. The device starts polling for +incoming connections when it receives its first read buffer. The device opens the connection for writing when it receives +the first write buffer. + +Transmit and receive buffers are added to their respective queues and the polling method in dmc_svc() checks for input +and sends any output. + +On the wire the format is a 2-byte block length followed by that number of bytes. Some of the diagnostics expect to receive +the same number of bytes in a buffer as were sent by the other end. Using sockets without a block length can cause the +buffers to coalesce and then the buffer lengths in the diagnostics fail. The block length is always sent in network byte +order. + +Tested with two diagnostics. To run the diagnostics set the default directory to SYS$MAINTENANCE, run ESSAA and then +configure it for the DMC-11 with the following commands: + +The above commands can be put into a COM file in SYS$MAINTENANCE (works on VMS 3.0 but not 4.6, not sure why). + +ATT DW780 SBI DW0 3 4 +ATT DMC11 DW0 XMA0 760070 300 5 +SELECT XMA0 +(if putting these into a COM file to be executed by ESSAA add a "DS> " prefix) + + +The first is EVDCA which takes no parameters. Invoke it with the command R EVDCA. This diagnostic uses the DMC-11 loopback +functionality and the transmit port is not used when LU LOOP is enabled. Seems to work only under later versions of VMS +such as 4.6, does not work on 3.0. + +The second is EVDMC, invoke this with the command R EVDMC. For this I used the following commands inside the diagnostic: + +RUN MODE=TRAN on one machine +RUN MODE=REC on the other (unless the one instance is configured with the ports looping back). + +You can add /PASS=n to the above commands to get the diagnostic to send and receive more buffers. + +The other test was to configure DECnet on VMS 4.6 and do SET HOST. +*/ + +// TODO: Avoid need for manifests and newest runtime, compile with 2003 +// TODO: Investigate line number and set parameters at the unit level (?) +// TODO: Multipoint. In this case perhaps don't need transmit port, allow all lines to connect to port on control node. +// TODO: Show active connections like DZ does, for multipoint. +// TODO: Test MOP. +// TODO: Implement actual DDCMP protocol and run over UDP. +// TODO: Allow NCP SHOW COUNTERS to work (think this is the base address thing). Since fixing how I get the addresses this should work now. + +#include +#include + +#include "pdp11_dmc.h" + +#define POLL 1000 +#define TRACE_BYTES_PER_LINE 16 + +struct csrs { + uint16 sel0; + uint16 sel2; + uint16 sel4; + uint16 sel6; +}; + +typedef struct csrs CSRS; + +typedef enum +{ + Initialised, /* after MASTER CLEAR */ + Running /* after any transmit or receive buffer has been supplied */ +} ControllerState; + +typedef enum +{ + Idle, + InputTransfer, + OutputTransfer +} TransferState; + +typedef enum +{ + Available, /* when empty or partially filled on read */ + ContainsData, + TransferInProgress +} BufferState; + +typedef struct +{ + int32 isPrimary; + SOCKET socket; // socket used bidirectionally + int receive_readable; + char *receive_port; + int transmit_writeable; + char peer[CBUFSIZE]; + int transmit_is_loopback; /* if true the transmit socket is the loopback to the receive */ + int32 speed; /* bits per second in each direction, 0 for no limit */ + int last_second; + int bytes_sent_in_last_second; + int bytes_received_in_last_second; + time_t last_connect_attempt; +} LINE; + +/* A partially filled buffer (during a read from the socket) will have block_len_bytes_read = 1 or actual_bytes_transferred < actual_block_len */ +typedef struct buffer +{ + uint32 address; /* unibus address of the buffer */ + uint16 count; /* size of the buffer passed to the device by the driver */ + uint16 actual_block_len; /* actual length of the received block */ + uint8 *transfer_buffer; /* the buffer into which data is received or from which it is transmitted*/ + int block_len_bytes_read; /* the number of bytes read so far for the block length */ + int actual_bytes_transferred; /* the number of bytes from the actual block that have been read or written so far*/ + struct buffer *next; /* next buffer in the queue */ + BufferState state; /* state of this buffer */ + int is_loopback; /* loopback was requested when this buffer was queued */ +} BUFFER; + +typedef struct +{ + char * name; + BUFFER queue[BUFFER_QUEUE_SIZE]; + int head; + int tail; + int count; + struct dmc_controller *controller; /* back pointer to the containing controller */ +} BUFFER_QUEUE; + +typedef struct +{ + int started; + clock_t start_time; + clock_t cumulative_time; +} TIMER; + +typedef struct +{ + TIMER between_polls_timer; + TIMER poll_timer; + uint32 poll_count; + +} UNIT_STATS; + +typedef enum +{ + DMC, + DMR, + DMP +} DEVTYPE; + +struct dmc_controller { + CSRS *csrs; + DEVICE *device; + ControllerState state; + TransferState transfer_state; /* current transfer state (type of transfer) */ + int transfer_type; + int transfer_in_io; // remembers IN I/O setting at start of input transfer as host changes it during transfer! + LINE *line; + BUFFER_QUEUE *receive_queue; + BUFFER_QUEUE *transmit_queue; + UNIT_STATS *stats; + SOCKET master_socket; + int32 connect_poll_interval; + DEVTYPE dev_type; + uint32 rxi; + uint32 txi; + uint32 buffers_received_from_net; + uint32 buffers_transmitted_to_net; + uint32 receive_buffer_output_transfers_completed; + uint32 transmit_buffer_output_transfers_completed; + uint32 receive_buffer_input_transfers_completed; + uint32 transmit_buffer_input_transfers_completed; +}; + +typedef struct dmc_controller CTLR; + +t_stat dmc_rd(int32* data, int32 PA, int32 access); +t_stat dmc_wr(int32 data, int32 PA, int32 access); +t_stat dmc_svc(UNIT * uptr); +t_stat dmc_reset (DEVICE * dptr); +t_stat dmc_attach (UNIT * uptr, char * cptr); +int dmc_isattached(CTLR *controller); +t_stat dmc_detach (UNIT * uptr); +int32 dmc_rxint (void); +int32 dmc_txint (void); +t_stat dmc_setpeer (UNIT* uptr, int32 val, char* cptr, void* desc); +t_stat dmc_showpeer (FILE* st, UNIT* uptr, int32 val, void* desc); +t_stat dmc_setspeed (UNIT* uptr, int32 val, char* cptr, void* desc); +t_stat dmc_showspeed (FILE* st, UNIT* uptr, int32 val, void* desc); +t_stat dmc_settype (UNIT* uptr, int32 val, char* cptr, void* desc); +t_stat dmc_showtype (FILE* st, UNIT* uptr, int32 val, void* desc); +t_stat dmc_setstats (UNIT* uptr, int32 val, char* cptr, void* desc); +t_stat dmc_showstats (FILE* st, UNIT* uptr, int32 val, void* desc); +t_stat dmc_setconnectpoll (UNIT* uptr, int32 val, char* cptr, void* desc); +t_stat dmc_showconnectpoll (FILE* st, UNIT* uptr, int32 val, void* desc); +t_stat dmc_setlinemode (UNIT* uptr, int32 val, char* cptr, void* desc); +t_stat dmc_showlinemode (FILE* st, UNIT* uptr, int32 val, void* desc); +int dmc_is_dmc(CTLR *controller); +int dmc_is_rqi_set(CTLR *controller); +int dmc_is_rdyi_set(CTLR *controller); +int dmc_is_iei_set(CTLR *controller); +int dmc_is_ieo_set(CTLR *controller); +void dmc_process_command(CTLR *controller); +int dmc_buffer_fill_receive_buffers(CTLR *controller); +void dmc_start_transfer_receive_buffer(CTLR *controller); +int dmc_buffer_send_transmit_buffers(CTLR *controller); +void dmc_buffer_queue_init(CTLR *controller, BUFFER_QUEUE *q, char *name); +void dmc_buffer_queue_init_all(CTLR *controller); +BUFFER *dmc_buffer_queue_head(BUFFER_QUEUE *q); +int dmc_buffer_queue_full(BUFFER_QUEUE *q); +void dmc_buffer_queue_get_stats(BUFFER_QUEUE *q, int *available, int *contains_data, int *transfer_in_progress); +void dmc_start_transfer_transmit_buffer(CTLR *controller); +void dmc_error_and_close_socket(CTLR *controller, char *format); +void dmc_close_socket(CTLR *controller, char *reason); +void dmc_close_receive(CTLR *controller, char *reason, char *from); +void dmc_close_transmit(CTLR *controller, char *reason); +int dmc_get_socket(CTLR *controller, int forRead); +int dmc_get_receive_socket(CTLR *controller, int forRead); +int dmc_get_transmit_socket(CTLR *controller, int is_loopback, int forRead); +void dmc_line_update_speed_stats(LINE *line); + +DEBTAB dmc_debug[] = { + {"TRACE", DBG_TRC}, + {"WARN", DBG_WRN}, + {"REG", DBG_REG}, + {"INFO", DBG_INF}, + {"DATA", DBG_DAT}, + {"DATASUM",DBG_DTS}, + {"SOCKET", DBG_SOK}, + {"CONNECT", DBG_CON}, + {0} +}; + +UNIT dmc0_unit = { UDATA (&dmc_svc, UNIT_IDLE|UNIT_ATTABLE|UNIT_DISABLE, 0) }; +UNIT dmc1_unit = { UDATA (&dmc_svc, UNIT_IDLE|UNIT_ATTABLE|UNIT_DISABLE, 0) }; +UNIT dmc2_unit = { UDATA (&dmc_svc, UNIT_IDLE|UNIT_ATTABLE|UNIT_DISABLE, 0) }; +UNIT dmc3_unit = { UDATA (&dmc_svc, UNIT_IDLE|UNIT_ATTABLE|UNIT_DISABLE, 0) }; + +UNIT dmpa_unit = { UDATA (&dmc_svc, UNIT_IDLE|UNIT_ATTABLE|UNIT_DISABLE, 0) }; + +CSRS dmc_csrs[DMC_NUMDEVICE]; + +CSRS dmp_csrs[DMP_NUMDEVICE]; + +LINE dmc_line[DMC_NUMDEVICE] = +{ + { 0, INVALID_SOCKET }, + { 0, INVALID_SOCKET }, + { 0, INVALID_SOCKET }, + { 0, INVALID_SOCKET } +}; + +BUFFER_QUEUE dmc_receive_queues[DMC_NUMDEVICE]; +BUFFER_QUEUE dmc_transmit_queues[DMC_NUMDEVICE]; + +LINE dmp_line[DMP_NUMDEVICE] = +{ + { 0, INVALID_SOCKET } +}; + +BUFFER_QUEUE dmp_receive_queues[DMP_NUMDEVICE]; +BUFFER_QUEUE dmp_transmit_queues[DMP_NUMDEVICE]; + +UNIT_STATS dmc_stats[DMC_NUMDEVICE]; +UNIT_STATS dmp_stats[DMP_NUMDEVICE]; + +REG dmca_reg[] = { + { HRDATA (SEL0, dmc_csrs[0].sel0, 16) }, + { HRDATA (SEL2, dmc_csrs[0].sel2, 16) }, + { HRDATA (SEL4, dmc_csrs[0].sel4, 16) }, + { HRDATA (SEL6, dmc_csrs[0].sel6, 16) }, + { GRDATA (BSEL0, dmc_csrs[0].sel0, DEV_RDX, 8, 0) }, + { GRDATA (BSEL1, dmc_csrs[0].sel0, DEV_RDX, 8, 8) }, + { GRDATA (BSEL2, dmc_csrs[0].sel2, DEV_RDX, 8, 0) }, + { GRDATA (BSEL3, dmc_csrs[0].sel2, DEV_RDX, 8, 8) }, + { GRDATA (BSEL4, dmc_csrs[0].sel4, DEV_RDX, 8, 0) }, + { GRDATA (BSEL5, dmc_csrs[0].sel4, DEV_RDX, 8, 8) }, + { GRDATA (BSEL6, dmc_csrs[0].sel6, DEV_RDX, 8, 0) }, + { GRDATA (BSEL7, dmc_csrs[0].sel6, DEV_RDX, 8, 8) }, + { BRDATA (PEER, dmc_line[0].peer, 16, 8, sizeof(dmc_line[0].peer)), REG_HRO}, + { HRDATA (MODE, dmc_line[0].isPrimary, 32), REG_HRO }, + { HRDATA (SPEED, dmc_line[0].speed, 32), REG_HRO }, + { NULL } }; + +REG dmcb_reg[] = { + { HRDATA (SEL0, dmc_csrs[1].sel0, 16) }, + { HRDATA (SEL2, dmc_csrs[1].sel2, 16) }, + { HRDATA (SEL4, dmc_csrs[1].sel4, 16) }, + { HRDATA (SEL6, dmc_csrs[1].sel6, 16) }, + { GRDATA (BSEL0, dmc_csrs[1].sel0, DEV_RDX, 8, 0) }, + { GRDATA (BSEL1, dmc_csrs[1].sel0, DEV_RDX, 8, 8) }, + { GRDATA (BSEL2, dmc_csrs[1].sel2, DEV_RDX, 8, 0) }, + { GRDATA (BSEL3, dmc_csrs[1].sel2, DEV_RDX, 8, 8) }, + { GRDATA (BSEL4, dmc_csrs[1].sel4, DEV_RDX, 8, 0) }, + { GRDATA (BSEL5, dmc_csrs[1].sel4, DEV_RDX, 8, 8) }, + { GRDATA (BSEL6, dmc_csrs[1].sel6, DEV_RDX, 8, 0) }, + { GRDATA (BSEL7, dmc_csrs[1].sel6, DEV_RDX, 8, 8) }, + { BRDATA (PEER, dmc_line[1].peer, 16, 8, sizeof(dmc_line[1].peer)), REG_HRO}, + { HRDATA (MODE, dmc_line[1].isPrimary, 32), REG_HRO }, + { HRDATA (SPEED, dmc_line[1].speed, 32), REG_HRO }, + { NULL } }; + +REG dmcc_reg[] = { + { HRDATA (SEL0, dmc_csrs[2].sel0, 16) }, + { HRDATA (SEL2, dmc_csrs[2].sel2, 16) }, + { HRDATA (SEL4, dmc_csrs[2].sel4, 16) }, + { HRDATA (SEL6, dmc_csrs[2].sel6, 16) }, + { GRDATA (BSEL0, dmc_csrs[2].sel0, DEV_RDX, 8, 0) }, + { GRDATA (BSEL1, dmc_csrs[2].sel0, DEV_RDX, 8, 8) }, + { GRDATA (BSEL2, dmc_csrs[2].sel2, DEV_RDX, 8, 0) }, + { GRDATA (BSEL3, dmc_csrs[2].sel2, DEV_RDX, 8, 8) }, + { GRDATA (BSEL4, dmc_csrs[2].sel4, DEV_RDX, 8, 0) }, + { GRDATA (BSEL5, dmc_csrs[2].sel4, DEV_RDX, 8, 8) }, + { GRDATA (BSEL6, dmc_csrs[2].sel6, DEV_RDX, 8, 0) }, + { GRDATA (BSEL7, dmc_csrs[2].sel6, DEV_RDX, 8, 8) }, + { BRDATA (PEER, dmc_line[2].peer, 16, 8, sizeof(dmc_line[2].peer)), REG_HRO}, + { HRDATA (MODE, dmc_line[2].isPrimary, 32), REG_HRO }, + { HRDATA (SPEED, dmc_line[2].speed, 32), REG_HRO }, + { NULL } }; + +REG dmcd_reg[] = { + { HRDATA (SEL0, dmc_csrs[3].sel0, 16) }, + { HRDATA (SEL2, dmc_csrs[3].sel2, 16) }, + { HRDATA (SEL4, dmc_csrs[3].sel4, 16) }, + { HRDATA (SEL6, dmc_csrs[3].sel6, 16) }, + { GRDATA (BSEL0, dmc_csrs[3].sel0, DEV_RDX, 8, 0) }, + { GRDATA (BSEL1, dmc_csrs[3].sel0, DEV_RDX, 8, 8) }, + { GRDATA (BSEL2, dmc_csrs[3].sel2, DEV_RDX, 8, 0) }, + { GRDATA (BSEL3, dmc_csrs[3].sel2, DEV_RDX, 8, 8) }, + { GRDATA (BSEL4, dmc_csrs[3].sel4, DEV_RDX, 8, 0) }, + { GRDATA (BSEL5, dmc_csrs[3].sel4, DEV_RDX, 8, 8) }, + { GRDATA (BSEL6, dmc_csrs[3].sel6, DEV_RDX, 8, 0) }, + { GRDATA (BSEL7, dmc_csrs[3].sel6, DEV_RDX, 8, 8) }, + { BRDATA (PEER, dmc_line[3].peer, 16, 8, sizeof(dmc_line[3].peer)), REG_HRO}, + { HRDATA (MODE, dmc_line[3].isPrimary, 32), REG_HRO }, + { HRDATA (SPEED, dmc_line[3].speed, 32), REG_HRO }, + { NULL } }; + +REG dmp_reg[] = { + { HRDATA (SEL0, dmc_csrs[3].sel0, 16) }, + { HRDATA (SEL2, dmc_csrs[3].sel2, 16) }, + { HRDATA (SEL4, dmc_csrs[3].sel4, 16) }, + { HRDATA (SEL6, dmc_csrs[3].sel6, 16) }, + { GRDATA (BSEL0, dmc_csrs[3].sel0, DEV_RDX, 8, 0) }, + { GRDATA (BSEL1, dmc_csrs[3].sel0, DEV_RDX, 8, 8) }, + { GRDATA (BSEL2, dmc_csrs[3].sel2, DEV_RDX, 8, 0) }, + { GRDATA (BSEL3, dmc_csrs[3].sel2, DEV_RDX, 8, 8) }, + { GRDATA (BSEL4, dmc_csrs[3].sel4, DEV_RDX, 8, 0) }, + { GRDATA (BSEL5, dmc_csrs[3].sel4, DEV_RDX, 8, 8) }, + { GRDATA (BSEL6, dmc_csrs[3].sel6, DEV_RDX, 8, 0) }, + { GRDATA (BSEL7, dmc_csrs[3].sel6, DEV_RDX, 8, 8) }, + { BRDATA (PEER, dmp_line[0].peer, 16, 8, sizeof(dmp_line[0].peer)), REG_HRO}, + { HRDATA (MODE, dmp_line[0].isPrimary, 32), REG_HRO }, + { HRDATA (SPEED, dmp_line[0].speed, 32), REG_HRO }, + { NULL } }; + +MTAB dmc_mod[] = { + { MTAB_XTD | MTAB_VDV, 0, "PEER", "PEER=address:port" ,&dmc_setpeer, &dmc_showpeer, NULL }, + { MTAB_XTD | MTAB_VDV, 0, "SPEED", "SPEED=bits/sec (0=unrestricted)" ,&dmc_setspeed, &dmc_showspeed, NULL }, +#ifdef DMP + { MTAB_XTD | MTAB_VDV, 0, "TYPE", "TYPE" ,&dmc_settype, &dmc_showtype, NULL }, +#endif + { MTAB_XTD | MTAB_VDV, 0, "LINEMODE", "LINEMODE={PRIMARY|SECONDARY}" ,&dmc_setlinemode, &dmc_showlinemode, NULL }, + { MTAB_XTD | MTAB_VDV | MTAB_NMO, 0, "STATS", "STATS" ,&dmc_setstats, &dmc_showstats, NULL }, + { MTAB_XTD | MTAB_VDV, 0, "CONNECTPOLL", "CONNECTPOLL=seconds" ,&dmc_setconnectpoll, &dmc_showconnectpoll, NULL }, + { MTAB_XTD | MTAB_VDV, 006, "ADDRESS", "ADDRESS", &set_addr, &show_addr, NULL }, + { MTAB_XTD |MTAB_VDV, 0, "VECTOR", "VECTOR", &set_vec, &show_vec, NULL }, + { 0 }, +}; + +#define IOLN_DMC 010 +DIB dmc0_dib = { IOBA_AUTO, IOLN_DMC, &dmc_rd, &dmc_wr, 2, IVCL (DMCRX), VEC_AUTO, {&dmc_rxint, &dmc_txint} }; +DIB dmc1_dib = { IOBA_AUTO, IOLN_DMC, &dmc_rd, &dmc_wr, 2, IVCL (DMCRX), VEC_AUTO, {&dmc_rxint, &dmc_txint} }; +DIB dmc2_dib = { IOBA_AUTO, IOLN_DMC, &dmc_rd, &dmc_wr, 2, IVCL (DMCRX), VEC_AUTO, {&dmc_rxint, &dmc_txint} }; +DIB dmc3_dib = { IOBA_AUTO, IOLN_DMC, &dmc_rd, &dmc_wr, 2, IVCL (DMCRX), VEC_AUTO, {&dmc_rxint, &dmc_txint} }; + +#define IOLN_DMP 010 + +DIB dmp_dib = { IOBA_AUTO, IOLN_DMP, &dmc_rd, &dmc_wr, 2, IVCL (DMCRX), VEC_AUTO, {&dmc_rxint, &dmc_txint }}; + +DEVICE dmc_dev[] = +{ + { "DMC0", &dmc0_unit, dmca_reg, dmc_mod, DMC_UNITSPERDEVICE, DMC_RDX, 8, 1, DMC_RDX, 8, + NULL,NULL,&dmc_reset,NULL,&dmc_attach,&dmc_detach, + &dmc0_dib, DEV_DISABLE | DEV_DIS | DEV_UBUS | DEV_DEBUG, 0, dmc_debug }, + { "DMC1", &dmc1_unit, dmcb_reg, dmc_mod, DMC_UNITSPERDEVICE, DMC_RDX, 8, 1, DMC_RDX, 8, + NULL,NULL,&dmc_reset,NULL,&dmc_attach,&dmc_detach, + &dmc1_dib, DEV_DISABLE | DEV_DIS | DEV_UBUS | DEV_DEBUG, 0, dmc_debug }, + { "DMC2", &dmc2_unit, dmcc_reg, dmc_mod, DMC_UNITSPERDEVICE, DMC_RDX, 8, 1, DMC_RDX, 8, + NULL,NULL,&dmc_reset,NULL,&dmc_attach,&dmc_detach, + &dmc2_dib, DEV_DISABLE | DEV_DIS | DEV_UBUS | DEV_DEBUG, 0, dmc_debug }, + { "DMC3", &dmc3_unit, dmcd_reg, dmc_mod, DMC_UNITSPERDEVICE, DMC_RDX, 8, 1, DMC_RDX, 8, + NULL,NULL,&dmc_reset,NULL,&dmc_attach,&dmc_detach, + &dmc3_dib, DEV_DISABLE | DEV_DIS | DEV_UBUS | DEV_DEBUG, 0, dmc_debug } +}; + +#ifdef DMP +DEVICE dmp_dev[] = +{ + { "DMP", &dmp_unit, dmp_reg, dmc_mod, DMP_UNITSPERDEVICE, DMC_RDX, 8, 1, DMC_RDX, 8, + NULL,NULL,&dmc_reset,NULL,&dmc_attach,&dmc_detach, + &dmp_dib, DEV_DISABLE | DEV_DIS | DEV_UBUS | DEV_DEBUG, 0, dmc_debug } +}; +#endif + +CTLR dmc_ctrls[] = +{ + { &dmc_csrs[0], &dmc_dev[0], Initialised, Idle, 0, 0, &dmc_line[0], &dmc_receive_queues[0], &dmc_transmit_queues[0], &dmc_stats[0], INVALID_SOCKET, 30, DMC }, + { &dmc_csrs[1], &dmc_dev[1], Initialised, Idle, 0, 0, &dmc_line[1], &dmc_receive_queues[1], &dmc_transmit_queues[1], &dmc_stats[1], INVALID_SOCKET, 30, DMC }, + { &dmc_csrs[2], &dmc_dev[2], Initialised, Idle, 0, 0, &dmc_line[2], &dmc_receive_queues[2], &dmc_transmit_queues[2], &dmc_stats[2], INVALID_SOCKET, 30, DMC }, + { &dmc_csrs[3], &dmc_dev[3], Initialised, Idle, 0, 0, &dmc_line[3], &dmc_receive_queues[3], &dmc_transmit_queues[3], &dmc_stats[3], INVALID_SOCKET, 30, DMC }, +#ifdef DMP + { &dmp_csrs[0], &dmp_dev[0], Initialised, Idle, 0, 0, &dmp_line[0], &dmp_receive_queues[0], &dmp_transmit_queues[0], &dmp_stats[0], INVALID_SOCKET, -1, 30, DMP } +#endif +}; + +extern int32 tmxr_poll; /* calibrated delay */ + +void dmc_reset_unit_stats(UNIT_STATS *s) +{ + s->between_polls_timer.started = FALSE; + s->poll_timer.started = FALSE; + s->poll_count = 0; +} + +int dmc_timer_started(TIMER *t) +{ + return t->started; +} + +void dmc_timer_start(TIMER *t) +{ + t->start_time = clock(); + t->cumulative_time = 0; + t->started = TRUE; +} + +void dmc_timer_stop(TIMER *t) +{ + clock_t end_time = clock(); + t->cumulative_time += end_time - t->start_time; +} + +void dmc_timer_resume(TIMER *t) +{ + t->start_time = clock(); +} + +double dmc_timer_cumulative_seconds(TIMER *t) +{ + return (double)t->cumulative_time/CLOCKS_PER_SEC; +} + +int dmc_is_dmc(CTLR *controller) +{ + return controller->dev_type != DMP; +} + +CTLR *dmc_get_controller_from_unit(UNIT *unit) +{ + int i; + CTLR *ans = NULL; + for (i = 0; i < DMC_NUMDEVICE + DMP_NUMDEVICE; i++) + { + if (dmc_ctrls[i].device->units == unit) + { + ans = &dmc_ctrls[i]; + break; + } + } + + return ans; +} + +CTLR* dmc_get_controller_from_address(uint32 address) +{ + int i; + for (i=0; ictxt; + if ((address >= dib->ba) && (address < (dib->ba + dib->lnt))) + return &dmc_ctrls[i]; + } + /* not found */ + return 0; +} + +CTLR *dmc_get_controller_from_device(DEVICE *device) +{ + int i; + CTLR *ans = NULL; + for (i = 0; i < DMC_NUMDEVICE + DMP_NUMDEVICE; i++) + { + if (dmc_ctrls[i].device == device) + { + ans = &dmc_ctrls[i]; + break; + } + } + + return ans; +} + +t_stat dmc_showpeer (FILE* st, UNIT* uptr, int32 val, void* desc) +{ + CTLR *controller = dmc_get_controller_from_unit(uptr); + if (controller->line->peer[0]) + { + fprintf(st, "peer=%s", controller->line->peer); + } + + return SCPE_OK; +} + +t_stat dmc_setpeer (UNIT* uptr, int32 val, char* cptr, void* desc) +{ + t_stat status = SCPE_OK; + char host[CBUFSIZE], port[CBUFSIZE]; + CTLR *controller = dmc_get_controller_from_unit(uptr); + + if (!cptr) return SCPE_IERR; + if (uptr->flags & UNIT_ATT) return SCPE_ALATT; + status = sim_parse_addr (cptr, host, sizeof(host), NULL, port, sizeof(port), NULL, NULL); + if (status != SCPE_OK) + return status; + if (host[0] == '\0') + return SCPE_ARG; + strncpy(controller->line->peer, cptr, sizeof(controller->line->peer)-1); + + return status; +} + +t_stat dmc_showspeed (FILE* st, UNIT* uptr, int32 val, void* desc) +{ + CTLR *controller = dmc_get_controller_from_unit(uptr); + if (controller->line->speed > 0) + { + fprintf(st, "speed=%d bits/sec", controller->line->speed); + } + else + { + fprintf(st, "speed=0 (unrestricted)"); + } + + return SCPE_OK; +} + +t_stat dmc_setspeed (UNIT* uptr, int32 val, char* cptr, void* desc) +{ + t_stat status = SCPE_OK; + CTLR *controller = dmc_get_controller_from_unit(uptr); + + if (!cptr) return SCPE_IERR; + if (uptr->flags & UNIT_ATT) return SCPE_ALATT; + if (sscanf(cptr, "%d", &controller->line->speed) != 1) + { + status = SCPE_ARG; + } + + return status; +} + +t_stat dmc_showtype (FILE* st, UNIT* uptr, int32 val, void* desc) +{ + CTLR *controller = dmc_get_controller_from_unit(uptr); + switch (controller->dev_type) + { + case DMC: + { + fprintf(st, "type=DMC"); + break; + } + case DMR: + { + fprintf(st, "type=DMR"); + break; + } + case DMP: + { + fprintf(st, "type=DMP"); + break; + } + default: + { + fprintf(st, "type=???"); + break; + } + } + return SCPE_OK; +} + +t_stat dmc_settype (UNIT* uptr, int32 val, char* cptr, void* desc) +{ + char buf[80]; + t_stat status = SCPE_OK; + CTLR *controller = dmc_get_controller_from_unit(uptr); + + if (!cptr) return SCPE_IERR; + if (uptr->flags & UNIT_ATT) return SCPE_ALATT; + if (sscanf(cptr, "%s", buf) != 1) + { + status = SCPE_ARG; + } + else + { + if (strcmp(buf,"DMC")==0) + { + controller->dev_type = DMC; + } + else if (strcmp(buf,"DMR")==0) + { + controller->dev_type = DMR; + } + else if (strcmp(buf,"DMP")==0) + { + controller->dev_type = DMP; + } + else + { + status = SCPE_ARG; + } + } + + return status; +} + +t_stat dmc_showstats (FILE* st, UNIT* uptr, int32 val, void* desc) +{ + CTLR *controller = dmc_get_controller_from_unit(uptr); + TIMER *poll_timer = &controller->stats->poll_timer; + TIMER *between_polls_timer = &controller->stats->between_polls_timer; + uint32 poll_count = controller->stats->poll_count; + + if (dmc_timer_started(between_polls_timer) && poll_count > 0) + { + fprintf(st, "Average time between polls=%f (sec)\n", dmc_timer_cumulative_seconds(between_polls_timer)/poll_count); + } + else + { + fprintf(st, "Average time between polls=n/a\n"); + } + + if (dmc_timer_started(poll_timer) && poll_count > 0) + { + fprintf(st, "Average time within poll=%f (sec)\n", dmc_timer_cumulative_seconds(poll_timer)/poll_count); + } + else + { + fprintf(st, "Average time within poll=n/a\n"); + } + + fprintf(st, "Buffers received from the network=%d\n", controller->buffers_received_from_net); + fprintf(st, "Buffers sent to the network=%d\n", controller->buffers_transmitted_to_net); + fprintf(st, "Output transfers completed for receive buffers=%d\n", controller->receive_buffer_output_transfers_completed); + fprintf(st, "Output transfers completed for transmit buffers=%d\n", controller->transmit_buffer_output_transfers_completed); + fprintf(st, "Input transfers completed for receive buffers=%d\n", controller->receive_buffer_input_transfers_completed); + fprintf(st, "Input transfers completed for transmit buffers=%d\n", controller->transmit_buffer_input_transfers_completed); + + return SCPE_OK; +} + +t_stat dmc_setstats (UNIT* uptr, int32 val, char* cptr, void* desc) +{ + t_stat status = SCPE_OK; + CTLR *controller = dmc_get_controller_from_unit(uptr); + + dmc_reset_unit_stats(controller->stats); + + controller->receive_buffer_output_transfers_completed = 0; + controller->transmit_buffer_output_transfers_completed = 0; + controller->receive_buffer_input_transfers_completed = 0; + controller->transmit_buffer_input_transfers_completed = 0; + + printf("Statistics reset\n" ); + + return status; +} + +t_stat dmc_showconnectpoll (FILE* st, UNIT* uptr, int32 val, void* desc) +{ + CTLR *controller = dmc_get_controller_from_unit(uptr); + fprintf(st, "connectpoll=%d", controller->connect_poll_interval); + return SCPE_OK; +} + +t_stat dmc_setconnectpoll (UNIT* uptr, int32 val, char* cptr, void* desc) +{ + t_stat status = SCPE_OK; + CTLR *controller = dmc_get_controller_from_unit(uptr); + + if (!cptr) return SCPE_IERR; + if (sscanf(cptr, "%d", &controller->connect_poll_interval) != 1) + { + status = SCPE_ARG; + } + + return status; +} + +t_stat dmc_showlinemode (FILE* st, UNIT* uptr, int32 val, void* desc) +{ + CTLR *controller = dmc_get_controller_from_unit(uptr); + fprintf(st, "linemode=%s", controller->line->isPrimary? "PRIMARY" : "SECONDARY"); + return SCPE_OK; +} + +t_stat dmc_setlinemode (UNIT* uptr, int32 val, char* cptr, void* desc) +{ + t_stat status = SCPE_OK; + CTLR *controller = dmc_get_controller_from_unit(uptr); + + if (!cptr) return SCPE_IERR; + if (uptr->flags & UNIT_ATT) return SCPE_ALATT; + + if (MATCH_CMD(cptr, "PRIMARY") == 0) + { + controller->line->isPrimary = 1; + } + else if (MATCH_CMD(cptr, "SECONDARY") == 0) + { + controller->line->isPrimary = 0; + } + else + { + status = SCPE_ARG; + } + + return status; +} + +void dmc_setrxint(CTLR *controller) +{ + controller->rxi = 1; + SET_INT(DMCRX); +} + +void dmc_clrrxint(CTLR *controller) +{ + controller->rxi = 0; + CLR_INT(DMCRX); +} + +void dmc_settxint(CTLR *controller) +{ + controller->txi = 1; + SET_INT(DMCTX); +} + +void dmc_clrtxint(CTLR *controller) +{ + controller->txi = 0; + CLR_INT(DMCTX); +} + +int dmc_getsel(int addr) +{ + return (addr >> 1) & 03; +} + +uint16 dmc_bitfld(int data, int start_bit, int length) +{ + uint16 ans = data >> start_bit; + uint32 mask = (1 << (length))-1; + ans &= mask; + return ans; +} + +void dmc_dumpregsel0(CTLR *controller, int trace_level, char * prefix, uint16 data) +{ + char *type_str = ""; + uint16 type = dmc_bitfld(data, SEL0_TYPEI_BIT, 2); + + if (dmc_is_dmc(controller)) + { + if (dmc_is_rqi_set(controller)) + { + if (type==TYPE_BACCI) + type_str = "BA/CC I"; + else if (type==TYPE_CNTLI) + type_str = "CNTL I"; + else if (type==TYPE_BASEI) + type_str = "BASE I"; + else + type_str = "?????"; + } + + sim_debug( + trace_level, + controller->device, + "%s SEL0 (0x%04x) %s%s%s%s%s%s%s%s\n", + prefix, + data, + dmc_bitfld(data, SEL0_RUN_BIT, 1) ? "RUN " : "", + dmc_bitfld(data, SEL0_MCLR_BIT, 1) ? "MCLR " : "", + dmc_bitfld(data, SEL0_LU_LOOP_BIT, 1) ? "LU LOOP " : "", + dmc_bitfld(data, SEL0_RDI_BIT, 1) ? "RDI " : "", + dmc_bitfld(data, SEL0_DMC_IEI_BIT, 1) ? "IEI " : "", + dmc_bitfld(data, SEL0_DMC_RQI_BIT, 1) ? "RQI " : "", + dmc_bitfld(data, SEL0_IN_IO_BIT, 1) ? "IN I/O " : "", + type_str + ); + } + else + { + sim_debug( + trace_level, + controller->device, + "%s SEL0 (0x%04x) %s%s%s%s%s%s\n", + prefix, + data, + dmc_bitfld(data, SEL0_RUN_BIT, 1) ? "RUN " : "", + dmc_bitfld(data, SEL0_MCLR_BIT, 1) ? "MCLR " : "", + dmc_bitfld(data, SEL0_LU_LOOP_BIT, 1) ? "LU LOOP " : "", + dmc_bitfld(data, SEL0_DMP_RQI_BIT, 1) ? "RQI " : "", + dmc_bitfld(data, SEL0_DMP_IEO_BIT, 1) ? "IEO " : "", + dmc_bitfld(data, SEL0_DMP_IEI_BIT, 1) ? "IEI " : "" + ); + } +} + +void dmc_dumpregsel2(CTLR *controller, int trace_level, char *prefix, uint16 data) +{ + char *type_str = ""; + uint16 type = dmc_bitfld(data, SEL2_TYPEO_BIT, 2); + + if (type==TYPE_BACCO) + type_str = "BA/CC O"; + else if (type==TYPE_CNTLO) + type_str = "CNTL O"; + else + type_str = "?????"; + + sim_debug( + trace_level, + controller->device, + "%s SEL2 (0x%04x) PRIO=%d LINE=%d %s%s%s%s\n", + prefix, + data, + dmc_bitfld(data, SEL2_PRIO_BIT, SEL2_PRIO_BIT_LENGTH), + dmc_bitfld(data, SEL2_LINE_BIT, SEL2_LINE_BIT_LENGTH), + dmc_bitfld(data, SEL2_RDO_BIT, 1) ? "RDO " : "", + dmc_bitfld(data, SEL2_IEO_BIT, 1) ? "IEO " : "", + dmc_bitfld(data, SEL2_OUT_IO_BIT, 1) ? "OUT I/O " : "", + type_str + ); +} + +void dmc_dumpregsel4(CTLR *controller, int trace_level, char *prefix, uint16 data) +{ + sim_debug(trace_level, controller->device, "%s SEL4 (0x%04x)\n", prefix, data); +} + +void dmc_dumpregsel6(CTLR *controller, int trace_level, char *prefix, uint16 data) +{ + sim_debug( + trace_level, + controller->device, + "%s SEL6 (0x%04x) %s\n", + prefix, + data, + dmc_bitfld(data, SEL6_LOST_DATA_BIT, 1) ? "LOST_DATA " : ""); +} + +uint16 dmc_getreg(CTLR *controller, int reg, int ext) +{ + uint16 ans = 0; + switch (dmc_getsel(reg)) + { + case 00: + ans = controller->csrs->sel0; + if (ext) dmc_dumpregsel0(controller, DBG_REG, "Getting", ans); + break; + case 01: + ans = controller->csrs->sel2; + if (ext) dmc_dumpregsel2(controller, DBG_REG, "Getting", ans); + break; + case 02: + ans = controller->csrs->sel4; + if (ext) dmc_dumpregsel4(controller, DBG_REG, "Getting", ans); + break; + case 03: + ans = controller->csrs->sel6; + if (ext) dmc_dumpregsel6(controller, DBG_REG, "Getting", ans); + break; + default: + { + sim_debug(DBG_WRN, controller->device, "dmc_getreg(). Invalid register %d", reg); + } + } + + return ans; +} + +void dmc_setreg(CTLR *controller, int reg, uint16 data, int ext) +{ + char *trace = (ext) ? "Writing" : "Setting"; + switch (dmc_getsel(reg)) + { + case 00: + dmc_dumpregsel0(controller, DBG_REG, trace, data); + controller->csrs->sel0 = data; + break; + case 01: + dmc_dumpregsel2(controller, DBG_REG, trace, data); + controller->csrs->sel2 = data; + break; + case 02: + dmc_dumpregsel4(controller, DBG_REG, trace, data); + controller->csrs->sel4 = data; + break; + case 03: + dmc_dumpregsel6(controller, DBG_REG, trace, data); + controller->csrs->sel6 = data; + break; + default: + { + sim_debug(DBG_WRN, controller->device, "dmc_setreg(). Invalid register %d", reg); + } + } +} + +int dmc_is_master_clear_set(CTLR *controller) +{ + return controller->csrs->sel0 & MASTER_CLEAR_MASK; +} + +int dmc_is_lu_loop_set(CTLR *controller) +{ + return controller->csrs->sel0 & LU_LOOP_MASK; +} + +int dmc_is_rqi_set(CTLR *controller) +{ + int ans = 0; + if (dmc_is_dmc(controller)) + { + ans = controller->csrs->sel0 & DMC_RQI_MASK; + } + else + { + ans = controller->csrs->sel0 & DMP_RQI_MASK; + } + return ans; +} + +int dmc_is_rdyi_set(CTLR *controller) +{ + int ans = 0; + if (dmc_is_dmc(controller)) + { + ans = controller->csrs->sel0 & DMC_RDYI_MASK; + } + else + { + ans = controller->csrs->sel2 & DMP_RDYI_MASK; + } + return ans; +} + +int dmc_is_iei_set(CTLR *controller) +{ + int ans = 0; + if (dmc_is_dmc(controller)) + { + ans = controller->csrs->sel0 & DMC_IEI_MASK; + } + else + { + ans = controller->csrs->sel0 & DMP_IEI_MASK; + } + + return ans; +} +int dmc_is_ieo_set(CTLR *controller) +{ + int ans = 0; + if (dmc_is_dmc(controller)) + { + ans = controller->csrs->sel2 & DMC_IEO_MASK; + } + else + { + ans = controller->csrs->sel0 & DMP_IEO_MASK; + } + + return ans; +} +int dmc_is_in_io_set(CTLR *controller) +{ + int ans = 0; + if (dmc_is_dmc(controller)) + { + ans = controller->csrs->sel0 & DMC_IN_IO_MASK; + } + else + { + ans = !controller->csrs->sel2 & DMP_IN_IO_MASK; + } + + return ans; +} +int dmc_is_out_io_set(CTLR *controller) +{ + int ans = controller->csrs->sel2 & OUT_IO_MASK; + return ans; +} + +int dmc_is_rdyo_set(CTLR *controller) +{ + return controller->csrs->sel2 & DMC_RDYO_MASK; +} + +void dmc_set_rdyi(CTLR *controller) +{ + if (dmc_is_dmc(controller)) + { + dmc_setreg(controller, 0, controller->csrs->sel0 | DMC_RDYI_MASK, 0); + } + else + { + dmc_setreg(controller, 2, controller->csrs->sel2 | DMP_RDYI_MASK, 0); + } + + if (dmc_is_iei_set(controller)) + { + dmc_setrxint(controller); + } +} + +void dmc_clear_rdyi(CTLR *controller) +{ + if (dmc_is_dmc(controller)) + { + dmc_setreg(controller, 0, controller->csrs->sel0 & ~DMC_RDYI_MASK, 0); + } + else + { + dmc_setreg(controller, 2, controller->csrs->sel2 & ~DMP_RDYI_MASK, 0); + } +} + +void dmc_set_rdyo(CTLR *controller) +{ + dmc_setreg(controller, 2, controller->csrs->sel2 | DMC_RDYO_MASK, 0); + + if (dmc_is_ieo_set(controller)) + { + dmc_settxint(controller); + } +} + +void dmc_set_lost_data(CTLR *controller) +{ + dmc_setreg(controller, 6, controller->csrs->sel6 | LOST_DATA_MASK, 0); +} + +void dmc_clear_master_clear(CTLR *controller) +{ + dmc_setreg(controller, 0, controller->csrs->sel0 & ~MASTER_CLEAR_MASK, 0); +} + +void dmc_set_run(CTLR *controller) +{ + dmc_setreg(controller, 0, controller->csrs->sel0 | RUN_MASK, 0); +} + +int dmc_get_input_transfer_type(CTLR *controller) +{ + int ans = 0; + + if (dmc_is_dmc(controller)) + { + ans = controller->csrs->sel0 & DMC_TYPE_INPUT_MASK; + } + else + { + ans = controller->csrs->sel2 & DMP_TYPE_INPUT_MASK; + } + + return ans; +} +int dmc_get_output_transfer_type(CTLR *controller) +{ + return controller->csrs->sel2 & TYPE_OUTPUT_MASK; +} +void dmc_set_type_output(CTLR *controller, int type) +{ + dmc_setreg(controller, 2, controller->csrs->sel2 | (type & TYPE_OUTPUT_MASK), 0); +} + +void dmc_set_out_io(CTLR *controller) +{ + dmc_setreg(controller, 2, controller->csrs->sel2 | OUT_IO_MASK, 0); +} + +void dmc_clear_out_io(CTLR *controller) +{ + dmc_setreg(controller, 2, controller->csrs->sel2 & ~OUT_IO_MASK, 0); +} + +void dmc_process_master_clear(CTLR *controller) +{ + sim_debug(DBG_INF, controller->device, "Master clear\n"); + dmc_clear_master_clear(controller); + dmc_close_socket(controller, "Master clear"); /* to resynch both ends */ + controller->state = Initialised; + dmc_setreg(controller, 0, 0, 0); + if (controller->dev_type == DMR) + { + /* DMR-11 indicates microdiagnostics complete when this is set */ + dmc_setreg(controller, 2, 0x8000, 0); + } + else + { + /* preserve contents of BSEL3 if DMC-11 */ + dmc_setreg(controller, 2, controller->csrs->sel2 & 0xFF00, 0); + } + if (controller->dev_type == DMP) + { + dmc_setreg(controller, 4, 077, 0); + } + else + { + dmc_setreg(controller, 4, 0, 0); + } + + if (controller->dev_type == DMP) + { + dmc_setreg(controller, 6, 0305, 0); + } + else + { + dmc_setreg(controller, 6, 0, 0); + } + dmc_buffer_queue_init_all(controller); + + controller->transfer_state = Idle; + dmc_set_run(controller); + + sim_cancel (controller->device->units); /* stop poll */ + sim_clock_coschedule (controller->device->units, tmxr_poll); /* reactivate */ +} + +void dmc_start_input_transfer(CTLR *controller) +{ + int ok = 1; + int type = dmc_get_input_transfer_type(controller); + + /* if this is a BA/CC I then check that the relevant queue has room first */ + if (type == TYPE_BACCI) + { + ok = (dmc_is_in_io_set(controller) && !dmc_buffer_queue_full(controller->receive_queue)) + || + (!dmc_is_in_io_set(controller) && !dmc_buffer_queue_full(controller->transmit_queue)); + } + + if (ok) + { + sim_debug(DBG_INF, controller->device, "Starting input transfer\n"); + controller->transfer_state = InputTransfer; + controller->transfer_type = type; + controller->transfer_in_io = dmc_is_in_io_set(controller); + dmc_set_rdyi(controller); + } + else + { + sim_debug(DBG_WRN, controller->device, "Input transfer request not granted as queue is full\n"); + } +} + +void dmc_start_data_output_transfer(CTLR *controller, uint32 addr, int16 count, int is_receive) +{ + if (is_receive) + { + sim_debug(DBG_INF, controller->device, "Starting data output transfer for receive, address=0x%08x, count=%d\n", addr, count); + dmc_set_out_io(controller); + } + else + { + sim_debug(DBG_INF, controller->device, "Starting data output transfer for transmit, address=0x%08x, count=%d\n", addr, count); + dmc_clear_out_io(controller); + } + + dmc_setreg(controller, 4, addr & 0xFFFF, 0); + dmc_setreg(controller, 6, (((addr & 0x30000)) >> 2) | count, 0); + controller->transfer_state = OutputTransfer; + dmc_set_type_output(controller, TYPE_BACCO); + dmc_set_rdyo(controller); +} + +void dmc_start_control_output_transfer(CTLR *controller) +{ + sim_debug(DBG_INF, controller->device, "Starting control output transfer\n"); + controller->transfer_state = OutputTransfer; + dmc_set_type_output(controller, TYPE_CNTLO); + dmc_set_rdyo(controller); +} + +t_stat dmc_svc(UNIT* uptr) +{ + CTLR *controller; + TIMER *poll_timer; + TIMER *between_polls_timer; + + controller = dmc_get_controller_from_unit(uptr); + + poll_timer = &controller->stats->poll_timer; + between_polls_timer = &controller->stats->between_polls_timer; + + if (dmc_timer_started(between_polls_timer)) + { + dmc_timer_stop(between_polls_timer); + } + + if (dmc_timer_started(poll_timer)) + { + dmc_timer_resume(poll_timer); + } + else + { + dmc_timer_start(poll_timer); + } + + if (dmc_isattached(controller)) + { + dmc_line_update_speed_stats(controller->line); + + dmc_buffer_fill_receive_buffers(controller); + if (controller->transfer_state == Idle) dmc_start_transfer_receive_buffer(controller); + + dmc_buffer_send_transmit_buffers(controller); + if (controller->transfer_state == Idle) dmc_start_transfer_transmit_buffer(controller); + } + + /* resubmit service timer */ + sim_clock_coschedule (controller->device->units, tmxr_poll); + + dmc_timer_stop(poll_timer); + if (dmc_timer_started(between_polls_timer)) + { + dmc_timer_resume(between_polls_timer); + } + else + { + dmc_timer_start(between_polls_timer); + } + controller->stats->poll_count++; + + return SCPE_OK; +} + +void dmc_line_update_speed_stats(LINE *line) +{ + clock_t current = clock(); + int current_second = current / CLOCKS_PER_SEC; + if (current_second != line->last_second) + { + line->bytes_received_in_last_second = 0; + line->bytes_sent_in_last_second = 0; + line->last_second = current_second; + } +} + +/* given the number of bytes sent/received in the last second, the number of bytes to send or receive and the line speed, calculate how many bytes can be sent/received now */ +int dmc_line_speed_calculate_byte_length(int bytes_in_last_second, int num_bytes, int speed) +{ + int ans; + + if (speed == 0) + { + ans = num_bytes; + } + else + { + int clocks_this_second = clock() % CLOCKS_PER_SEC; + int allowable_bytes_to_date = ((speed/8) * clocks_this_second)/CLOCKS_PER_SEC; + int allowed_bytes = allowable_bytes_to_date - bytes_in_last_second; + if (allowed_bytes < 0) + { + allowed_bytes = 0; + } + + if (num_bytes > allowed_bytes) + { + ans = allowed_bytes; + } + else + { + ans = num_bytes; + } +//sim_debug(DBG_WRN, dmc_ctrls[0].device, "Bytes in last second %4d, clocks this sec %3d allowable bytes %4d, requested %4d allowed %4d\n", bytes_in_last_second, clocks_this_second, allowable_bytes_to_date, num_bytes, ans); + } + + return ans; +} + +void dmc_buffer_trace_line(int tracelevel, CTLR *controller, uint8 *buf, int length, char *prefix) +{ + char hex[TRACE_BYTES_PER_LINE*3+1]; + char ascii[TRACE_BYTES_PER_LINE+1]; + int i; + hex[0] = 0; + ascii[TRACE_BYTES_PER_LINE] = 0; + + for (i = 0; i=length) + { + strcat(hex, " "); + ascii[i] = ' '; + } + else + { + char hexByte[4]; + sprintf(hexByte, "%02X ", buf[i]); + strcat(hex, hexByte); + if (isprint(buf[i])) + { + ascii[i] = (char)buf[i]; + } + else + { + ascii[i] = '.'; + } + } + } + + sim_debug(tracelevel, controller->device, "%s %s %s\n", prefix, hex, ascii); +} + +void dmc_buffer_trace(CTLR *controller, uint8 *buf, int length, char *prefix, uint32 address) +{ + int i; + if (length >= 0 && controller->device->dctrl & DBG_DAT) + { + sim_debug(DBG_DAT, controller->device, "%s Buffer address 0x%08x (%d bytes)\n", prefix, address, length); + for(i = 0; i < length / TRACE_BYTES_PER_LINE; i++) + { + dmc_buffer_trace_line(DBG_DAT, controller, buf + i*TRACE_BYTES_PER_LINE, TRACE_BYTES_PER_LINE, prefix); + } + + if (length %TRACE_BYTES_PER_LINE > 0) + { + dmc_buffer_trace_line(DBG_DAT, controller, buf + length/TRACE_BYTES_PER_LINE, length % TRACE_BYTES_PER_LINE, prefix); + } + } + else if (length >= 0 && controller->device->dctrl & DBG_DTS) + { + char prefix2[80]; + sprintf(prefix2, "%s (len=%d)", prefix, length); + dmc_buffer_trace_line(DBG_DTS, controller, buf, (length > TRACE_BYTES_PER_LINE)? TRACE_BYTES_PER_LINE : length, prefix2); + } +} + +void dmc_buffer_queue_init(CTLR *controller, BUFFER_QUEUE *q, char *name) +{ + q->name = name; + q->head = 0; + q->tail = 0; + q->count = 0; + q->controller = controller; +} + +void dmc_buffer_queue_init_all(CTLR *controller) +{ + dmc_buffer_queue_init(controller, controller->receive_queue, "receive"); + dmc_buffer_queue_init(controller, controller->transmit_queue, "transmit"); +} + +int dmc_buffer_queue_full(BUFFER_QUEUE *q) +{ + return q->count > BUFFER_QUEUE_SIZE; +} + +void dmc_buffer_queue_add(BUFFER_QUEUE *q, uint32 address, uint16 count) +{ + if (!dmc_buffer_queue_full(q)) + { + int new_buffer = 0; + if (q->count > 0) + { + int last_buffer = q->tail; + new_buffer = (q->tail +1) % BUFFER_QUEUE_SIZE; + + /* Link last buffer to the new buffer */ + q->queue[last_buffer].next = &q->queue[new_buffer]; + } + else + { + q->head = 0; + new_buffer = 0; + } + + q->tail = new_buffer; + q->queue[new_buffer].address = address; + q->queue[new_buffer].count = count; + q->queue[new_buffer].actual_block_len = 0; + q->queue[new_buffer].transfer_buffer = NULL; + q->queue[new_buffer].block_len_bytes_read = 0; + q->queue[new_buffer].actual_bytes_transferred = 0; + q->queue[new_buffer].next = NULL; + q->queue[new_buffer].state = Available; + q->queue[new_buffer].is_loopback = dmc_is_lu_loop_set(q->controller); + q->count++; + sim_debug(DBG_INF, q->controller->device, "Queued %s buffer address=0x%08x count=%d\n", q->name, address, count); + } + else + { + sim_debug(DBG_WRN, q->controller->device, "Failed to queue %s buffer address=0x%08x, queue full\n", q->name, address); + // TODO: Report error here. + } +} + +void dmc_buffer_queue_release_head(BUFFER_QUEUE *q) +{ + if (q->count > 0) + { + q->head = (q->head + 1) % BUFFER_QUEUE_SIZE; + q->count--; + } + else + { + sim_debug(DBG_INF, q->controller->device, "Failed to release %s buffer, queue already empty\n", q->name); + } +} + +BUFFER *dmc_buffer_queue_head(BUFFER_QUEUE *q) +{ + BUFFER *ans = NULL; + if (q->count >0) + { + ans = &q->queue[q->head]; + } + + return ans; +} + +BUFFER *dmc_buffer_queue_find_first_available(BUFFER_QUEUE *q) +{ + BUFFER *ans = dmc_buffer_queue_head(q); + while (ans != NULL) + { + if (ans->state == Available) + { + break; + } + + ans = ans->next; + } + + return ans; +} + +BUFFER *dmc_buffer_queue_find_first_contains_data(BUFFER_QUEUE *q) +{ + BUFFER *ans = dmc_buffer_queue_head(q); + while (ans != NULL) + { + if (ans->state == ContainsData) + { + break; + } + + ans = ans->next; + } + + return ans; +} + +void dmc_buffer_queue_get_stats(BUFFER_QUEUE *q, int *available, int *contains_data, int *transfer_in_progress) +{ + BUFFER *buf = dmc_buffer_queue_head(q); + *available = 0; + *contains_data = 0; + *transfer_in_progress = 0; + + while (buf != NULL) + { + switch (buf->state) + { + case Available: + { + (*available)++; + break; + } + + case ContainsData: + { + (*contains_data)++; + break; + } + + case TransferInProgress: + { + (*transfer_in_progress)++; + break; + } + } + + buf = buf->next; + } +} + +t_stat dmc_open_master_socket(CTLR *controller, char *port) +{ + t_stat ans; + ans = SCPE_OK; + if (controller->master_socket == INVALID_SOCKET) + { + controller->master_socket = sim_master_sock(port, &ans); + if (controller->master_socket == INVALID_SOCKET) + { + sim_debug(DBG_WRN, controller->device, "Failed to open master socket on port %s\n", port); + ans = SCPE_OPENERR; + } + else + { + printf ("DMC-11 %s listening on port %s\n", controller->device->name, port); + } + } + + return ans; +} + +t_stat dmc_close_master_socket(CTLR *controller) +{ + sim_close_sock (controller->master_socket, TRUE); + controller->master_socket = INVALID_SOCKET; + return SCPE_OK; +} + +// Gets the bidirectional socket and handles arbitration of determining which socket to use. +int dmc_get_socket(CTLR *controller, int forRead) +{ + int ans = 0; + if (controller->line->isPrimary) + { + ans = dmc_get_transmit_socket(controller, 0, forRead); // TODO: After change to single socket, loopback may not work. + } + else + { + ans = dmc_get_receive_socket(controller, forRead); // TODO: After change to single socket, loopback may not work. + } + return ans; +} + +int dmc_get_receive_socket(CTLR *controller, int forRead) +{ + int ans = 0; + if (controller->line->socket == INVALID_SOCKET) + { + char *ipaddr; + //sim_debug(DBG_SOK, controller->device, "Trying to open receive socket\n"); + controller->line->socket = sim_accept_conn (controller->master_socket, &ipaddr); /* poll connect */ + if (controller->line->socket != INVALID_SOCKET) + { + char host[sizeof(controller->line->peer)]; + + if (sim_parse_addr (controller->line->peer, host, sizeof(host), NULL, NULL, 0, NULL, ipaddr)) + { + sim_debug(DBG_WRN, controller->device, "Received connection from unexpected source IP %s. Closing the connection.\n", ipaddr); + dmc_close_receive(controller, "Unathorized connection", ipaddr); + } + else + { + sim_debug(DBG_SOK, controller->device, "Opened receive socket %d\n", controller->line->socket); + controller->line->receive_readable = FALSE; + } + free(ipaddr); + } + } + + if (controller->line->socket != INVALID_SOCKET) + { + int readable = sim_check_conn(controller->line->socket, forRead); + if (readable == 0) /* Still opening */ + { + // Socket is still being opened, or is open but there is no data ready to be read. + ans = 0; + } + else if (readable == -1) /* Failed to open */ + { + dmc_close_receive(controller, "failed to connect", NULL); + ans = 0; + } + else /* connected */ + { + if (!controller->line->receive_readable) + { + sim_debug(DBG_CON, controller->device, "Receive socket is now readable\n"); + } + controller->line->receive_readable = TRUE; + ans = 1; + } + } + + return ans; +} + +int dmc_get_transmit_socket(CTLR *controller, int is_loopback, int forRead) +{ + int ans = 0; + /* close transmit socket if there is a change in the loopback setting */ + if (is_loopback ^ controller->line->transmit_is_loopback) + { + dmc_close_transmit(controller, "loopback change"); + } + + if (controller->line->socket == INVALID_SOCKET && ((int32)(time(NULL) - controller->line->last_connect_attempt)) > controller->connect_poll_interval) + { + char host_port_buf[CBUFSIZE]; + char *host_port = host_port_buf; + + controller->line->transmit_is_loopback = is_loopback; + + controller->line->last_connect_attempt = time(NULL); + if (is_loopback) + { + if (strrchr(controller->line->receive_port, ':')) + { + host_port = controller->line->receive_port; + } + else + { + sprintf(host_port_buf, "localhost:%s", controller->line->receive_port); + } + } + else + { + host_port = controller->line->peer; + } + + sim_debug(DBG_SOK, controller->device, "Trying to open transmit socket to address:port %s\n", host_port); + controller->line->last_connect_attempt = time(NULL); + controller->line->socket = sim_connect_sock(host_port, NULL, NULL); + if (controller->line->socket != INVALID_SOCKET) + { + sim_debug(DBG_SOK, controller->device, "Opened transmit socket to port %s\n", host_port); + controller->line->transmit_writeable = FALSE; + } + } + + if (controller->line->socket != INVALID_SOCKET) + { + int writeable = sim_check_conn(controller->line->socket, forRead); + if (writeable == 0) /* Still opening */ + { + //sim_debug(DBG_SOK, controller->device, "Waiting for transmit socket to become writeable\n"); + ans = 0; + } + else if (writeable == -1) /* Failed to open */ + { + dmc_close_transmit(controller, "failed to connect"); + ans = 0; + } + else /* connected */ + { + if (!controller->line->transmit_writeable) + { + sim_debug(DBG_CON, controller->device, "Transmit socket is now writeable\n"); + } + controller->line->transmit_writeable = TRUE; + ans = 1; + } + } + + return ans; +} + +void dmc_error_and_close_socket(CTLR *controller, char *format) +{ + int err = WSAGetLastError(); + char errmsg[80]; + sprintf(errmsg, format, err); + dmc_close_socket(controller, errmsg); +} + +void dmc_close_socket(CTLR *controller, char *reason) +{ + if (controller->line->isPrimary) + { + dmc_close_transmit(controller, reason); + } + else + { + dmc_close_receive(controller, reason, NULL); + } +} + +void dmc_close_receive(CTLR *controller, char *reason, char *from) +{ + if (controller->line->socket != INVALID_SOCKET) + { + sim_debug(DBG_SOK, controller->device, "Closing receive socket on port %s, reason: %s%s%s\n", controller->line->receive_port, reason, from ? " from " : "", from ? from : ""); + sim_close_sock(controller->line->socket, FALSE); + controller->line->socket = INVALID_SOCKET; + + if (controller->line->receive_readable) + { + sim_debug(DBG_CON, controller->device, "Readable receive socket closed, reason: %s\n", reason); + } + controller->line->receive_readable = FALSE; + } +} + +void dmc_close_transmit(CTLR *controller, char *reason) +{ + if (controller->line->socket != INVALID_SOCKET) + { + sim_debug(DBG_SOK, controller->device, "Closing transmit socket to port %s, socket %d, reason: %s\n", controller->line->peer, controller->line->socket, reason); + sim_close_sock(controller->line->socket, FALSE); + controller->line->socket = INVALID_SOCKET; + + if (controller->line->transmit_writeable) + { + sim_debug(DBG_CON, controller->device, "Writeable transmit socket closed, reason: %s\n", reason); + } + controller->line->transmit_writeable = FALSE; + } +} + +/* returns true if some data was received */ +int dmc_buffer_fill_receive_buffers(CTLR *controller) +{ + int ans = FALSE; + SOCKET socket; + if (controller->state == Initialised) + { + /* accept any inbound connection but just throw away any data */ + if (dmc_get_socket(controller, TRUE)) + { + char buffer[1000]; + int bytes_read = 0; + socket = controller->line->socket; + bytes_read = sim_read_sock(socket, buffer, sizeof(buffer)); + if (bytes_read < 0) + { + dmc_error_and_close_socket(controller, "read error, code=%d"); + } + else if (bytes_read > 0) + { + sim_debug(DBG_SOK, controller->device, "Discarding received data while controller is not running\n"); + } + } + } + else + { + BUFFER *buffer = dmc_buffer_queue_find_first_available(controller->receive_queue); + while (buffer != NULL && buffer->state == Available) + { + if (dmc_get_socket(controller, TRUE)) + { + int bytes_read = 0; + int lost_data = 0; + + socket = controller->line->socket; + /* read block length and allocate buffer */ + if ((size_t)buffer->block_len_bytes_read < sizeof(buffer->actual_block_len)) + { + char *start_addr = ((char *)&buffer->actual_block_len) + buffer->block_len_bytes_read; + bytes_read = sim_read_sock(socket, start_addr, sizeof(buffer->actual_block_len) - buffer->block_len_bytes_read); + if (bytes_read >= 0) + { + buffer->block_len_bytes_read += bytes_read; + if (buffer->block_len_bytes_read == sizeof(buffer->actual_block_len)) + { + buffer->actual_block_len = ntohs(buffer->actual_block_len); + if (buffer->actual_block_len > buffer->count) + { + sim_debug(DBG_WRN, controller->device, "LOST DATA, buffer available has %d bytes, but the block is %d bytes\n", buffer->count, buffer->actual_block_len); + dmc_setreg(controller, 4, 0, 0); + dmc_setreg(controller, 6, 0, 0); + dmc_set_lost_data(controller); + dmc_start_control_output_transfer(controller); + lost_data = 1; + } + + if (buffer->actual_block_len > 0) + { + buffer->transfer_buffer = (uint8 *)malloc(buffer->actual_block_len); /* read full buffer regardless, so bad buffer is flushed */ + } + } + } + } + else + { + lost_data = buffer->actual_block_len > buffer->count; /* need to preserve this variable if need more than one attempt to read the buffer */ + } + + /* read the actual block */ + if (buffer->block_len_bytes_read == sizeof(buffer->actual_block_len)) + { + bytes_read = 0; + if (buffer->actual_block_len > 0) + { + int bytes_to_read = dmc_line_speed_calculate_byte_length(controller->line->bytes_received_in_last_second, buffer->actual_block_len - buffer->actual_bytes_transferred, controller->line->speed); + if (bytes_to_read > 0) + { + bytes_read = sim_read_sock(controller->line->socket, (char *)(buffer->transfer_buffer + buffer->actual_bytes_transferred), bytes_to_read); + } + } + + if (bytes_read >= 0) + { + buffer->actual_bytes_transferred += bytes_read; + controller->line->bytes_received_in_last_second += bytes_read; + + if (buffer->actual_bytes_transferred >= buffer->actual_block_len) + { + dmc_buffer_trace(controller, buffer->transfer_buffer, buffer->actual_bytes_transferred, "REC ", buffer->address); + controller->buffers_received_from_net++; + buffer->state = ContainsData; + if (!lost_data) + { + Map_WriteB(buffer->address, buffer->actual_bytes_transferred, buffer->transfer_buffer); + } + else + { + buffer->actual_block_len = 0; /* so an empty buffer is returned to the driver */ + } + + if (buffer->actual_block_len > 0) + { + free(buffer->transfer_buffer); + buffer->transfer_buffer = NULL; + } + + ans = TRUE; + } + } + } + + /* Only close the socket if there was an error or no more data */ + if (bytes_read < 0) + { + dmc_error_and_close_socket(controller, "read error, code=%d"); + break; + } + + /* if buffer is incomplete do not try to read any more buffers and continue filling this one later */ + if (buffer->state == Available) + { + break; /* leave buffer available and continue filling it later */ + } + } + else + { + break; + } + + buffer = buffer ->next; + } + } + + return ans; +} + +/* returns true if some data was actually sent */ +int dmc_buffer_send_transmit_buffers(CTLR *controller) +{ + int ans = FALSE; + /* when transmit buffer is queued it is marked as available, not as ContainsData */ + BUFFER *buffer = dmc_buffer_queue_find_first_available(controller->transmit_queue); + while (buffer != NULL) + { + if (dmc_get_socket(controller, FALSE)) // TODO: , buffer->is_loopback); + { + int bytes = 0; + int bytes_to_send; + uint16 block_len; + int total_buffer_len = (buffer->count > 0) ? buffer->count + sizeof(block_len) : 0; + + /* only send the buffer if it actually has some data, sometimes get zero length buffers - don't send these */ + if (total_buffer_len > 0) + { + if (buffer->transfer_buffer == NULL) + { + int n; + /* construct buffer and include block length bytes */ + buffer->transfer_buffer = (uint8 *)malloc(total_buffer_len); + block_len = htons(buffer->count); + memcpy(buffer->transfer_buffer, (char *)&block_len, sizeof(block_len)); + n = Map_ReadB(buffer->address, buffer->count, buffer->transfer_buffer + sizeof(block_len)); + if (n > 0) + { + sim_debug(DBG_WRN, controller->device, "DMA error\n"); + } + } + + bytes_to_send = dmc_line_speed_calculate_byte_length(controller->line->bytes_sent_in_last_second, buffer->count + sizeof(block_len) - buffer->actual_bytes_transferred, controller->line->speed); + if (bytes_to_send > 0) + { + bytes = sim_write_sock (controller->line->socket, (char *)(buffer->transfer_buffer + buffer->actual_bytes_transferred), bytes_to_send); + if (bytes >= 0) + { + buffer->actual_bytes_transferred += bytes; + controller->line->bytes_sent_in_last_second += bytes; + } + + if (buffer->actual_bytes_transferred >= total_buffer_len || bytes < 0) + { + dmc_buffer_trace(controller, buffer->transfer_buffer+sizeof(block_len), buffer->count, "TRAN", buffer->address); + free(buffer->transfer_buffer); + } + } + } + + if (buffer->actual_bytes_transferred >= total_buffer_len) + { + controller->buffers_transmitted_to_net++; + buffer->state = ContainsData; // so won't try to transmit again + ans = TRUE; + } + else if (bytes < 0) + { + int err = WSAGetLastError (); + char errmsg[80]; + sprintf(errmsg, "write failure, code=%d", err); + + dmc_close_transmit(controller, errmsg); + break; + } + else + { + break; /* poll again later to send more bytes */ + } + + } + else + { + break; + } + + buffer = buffer ->next; + } + + return ans; +} + +void dmc_start_transfer_receive_buffer(CTLR *controller) +{ + BUFFER *head = dmc_buffer_queue_head(controller->receive_queue); + if (head != NULL) + { + if (head->state == ContainsData) + { + head->state = TransferInProgress; + dmc_start_data_output_transfer(controller, head->address, head->actual_block_len, TRUE); + } + } +} + +void dmc_start_transfer_transmit_buffer(CTLR *controller) +{ + BUFFER *head = dmc_buffer_queue_head(controller->transmit_queue); + if (head != NULL) + { + if (head->state == ContainsData) + { + head->state = TransferInProgress; + dmc_start_data_output_transfer(controller, head->address, head->count, FALSE); + } + } +} + +void dmc_check_for_output_transfer_completion(CTLR *controller) +{ + if (!dmc_is_rdyo_set(controller)) + { + sim_debug(DBG_INF, controller->device, "Output transfer completed\n"); + controller->transfer_state = Idle; + if (dmc_get_output_transfer_type(controller) == TYPE_BACCO) + { + if (dmc_is_out_io_set(controller)) + { + dmc_buffer_queue_release_head(controller->receive_queue); + controller->receive_buffer_output_transfers_completed++; + } + else + { + dmc_buffer_queue_release_head(controller->transmit_queue); + controller->transmit_buffer_output_transfers_completed++; + } + } + dmc_process_command(controller); // check for any input transfers + } +} + +void dmc_process_input_transfer_completion(CTLR *controller) +{ + if (dmc_is_dmc(controller)) + { + if (!dmc_is_rqi_set(controller)) + { + uint16 sel4 = controller->csrs->sel4; + uint16 sel6 = controller->csrs->sel6; + dmc_clear_rdyi(controller); + if (controller->transfer_type == TYPE_BASEI) + { + uint32 baseaddr = ((sel6 >> 14) << 16) | sel4; + uint16 count = sel6 & 0x3FFF; + sim_debug(DBG_INF, controller->device, "Completing Base In input transfer, base address=0x%08x count=%d\n", baseaddr, count); + } + else if (controller->transfer_type == TYPE_BACCI) + { + uint32 addr = ((sel6 >> 14) << 16) | sel4; + uint16 count = sel6 & 0x3FFF; + if (controller->transfer_in_io != dmc_is_in_io_set(controller)) + { + sim_debug(DBG_TRC, controller->device, "IN IO MISMATCH\n"); + } + + controller->transfer_in_io = dmc_is_in_io_set(controller); // using evdmc the flag is set when the transfer completes - not when it starts, evdca seems to set in only at the start of the transfer - clearing it when it completes + controller->state = Running; + if (controller->transfer_in_io) + { + dmc_buffer_queue_add(controller->receive_queue, addr, count); + dmc_buffer_fill_receive_buffers(controller); + controller->receive_buffer_input_transfers_completed++; + } + else + { + dmc_buffer_queue_add(controller->transmit_queue, addr, count); + dmc_buffer_send_transmit_buffers(controller); + controller->transmit_buffer_input_transfers_completed++; + } + } + + controller->transfer_state = Idle; + } + } + else + { + if (!dmc_is_rdyi_set(controller)) + { + uint16 sel6 = controller->csrs->sel6; + if (controller->transfer_type == TYPE_DMP_MODE) + { + uint16 mode = sel6 & DMP_TYPE_INPUT_MASK; + char * duplex = (mode & 1) ? "Full-Duplex" : "Half-Duplex"; + char * config; + if (mode & 4) + { + config = "Point-to-point"; + } + else + { + config = (mode & 2) ? "Tributary station" : "Control Station"; + } + + sim_debug(DBG_INF, controller->device, "Completing Mode input transfer, %s %s\n", duplex, config); + } + else if (controller->transfer_type == TYPE_DMP_CONTROL) + { + sim_debug(DBG_WRN, controller->device, "Control command (not processed yet)\n"); + } + else if (controller->transfer_type == TYPE_DMP_RECEIVE) + { + sim_debug(DBG_WRN, controller->device, "Receive Buffer command (not processed yet)\n"); + } + else if (controller->transfer_type == TYPE_DMP_TRANSMIT) + { + sim_debug(DBG_WRN, controller->device, "Transmit Buffer command (not processed yet)\n"); + } + else + { + sim_debug(DBG_WRN, controller->device, "Unrecognised command code %hu\n", controller->transfer_type); + } + + controller->transfer_state = Idle; + } + } +} + +void dmc_process_command(CTLR *controller) +{ + if (dmc_is_master_clear_set(controller)) + { + dmc_process_master_clear(controller); + } + else + { + if (controller->transfer_state == InputTransfer) + { + dmc_process_input_transfer_completion(controller); + } + else if (controller->transfer_state == OutputTransfer) + { + dmc_check_for_output_transfer_completion(controller); + } + else if (dmc_is_rqi_set(controller)) + { + dmc_start_input_transfer(controller); + } + } +} + +t_stat dmc_rd(int32 *data, int32 PA, int32 access) +{ + CTLR *controller = dmc_get_controller_from_address(PA); + sim_debug(DBG_TRC, controller->device, "dmc_rd(), addr=0x%x access=%d\n", PA, access); + *data = dmc_getreg(controller, PA, 1); + + return SCPE_OK; +} + +t_stat dmc_wr(int32 data, int32 PA, int32 access) +{ + CTLR *controller = dmc_get_controller_from_address(PA); + int reg = PA & 07; + uint16 oldValue = dmc_getreg(controller, PA, 0); + if (access == WRITE) + { + sim_debug(DBG_TRC, controller->device, "dmc_wr(), addr=0x%08x, SEL%d, data=0x%04x\n", PA, reg, data); + } + else + { + sim_debug(DBG_TRC, controller->device, "dmc_wr(), addr=0x%08x, BSEL%d, data=%04x\n", PA, reg, data); + } + + if (access == WRITE) + { + if (PA & 1) + sim_debug(DBG_WRN, controller->device, "dmc_wr(), Unexpected non-16-bit write access to SEL%d\n", reg); + dmc_setreg(controller, PA, data, 1); + } + else + { + uint16 mask; + if (PA & 1) + { + mask = 0xFF00; + data = data << 8; + } + else + { + mask = 0x00FF; + } + + dmc_setreg(controller, PA, (oldValue & ~mask) | (data & mask), 1); + } + + if (dmc_getsel(reg) == 0 || dmc_getsel(reg) == 1) + { + dmc_process_command(controller); + } + + return SCPE_OK; +} + +int32 dmc_rxint (void) +{ + int i; + int32 ans = 0; /* no interrupt request active */ + for (i=0; irxi != 0) + { + DIB *dib = (DIB *)controller->device->ctxt; + ans = dib->vec; + dmc_clrrxint(controller); + break; + } + } + + return ans; + } + +int32 dmc_txint (void) +{ + int i; + int32 ans = 0; /* no interrupt request active */ + for (i=0; itxi != 0) + { + DIB *dib = (DIB *)controller->device->ctxt; + ans = dib->vec + 4; + dmc_clrtxint(controller); + break; + } + } + + return ans; +} + +t_stat dmc_reset (DEVICE *dptr) +{ + t_stat ans = SCPE_OK; + CTLR *controller = dmc_get_controller_from_device(dptr); + + sim_debug(DBG_TRC, dptr, "dmc_reset()\n"); + + dmc_buffer_queue_init_all(controller); + dmc_clrrxint(controller); + dmc_clrtxint(controller); + sim_cancel (controller->device->units); /* stop poll */ + + if (!(dptr->flags & DEV_DIS)) + { + ans = auto_config (dptr->name, DMC_UNITSPERDEVICE); + } + return ans; +} + +t_stat dmc_attach (UNIT *uptr, char *cptr) +{ + CTLR *controller = dmc_get_controller_from_unit(uptr); + t_stat ans = SCPE_OK; + + ans = dmc_open_master_socket(controller, cptr); + if (ans == SCPE_OK) + { + controller->line->socket = INVALID_SOCKET; + uptr->flags = uptr->flags | UNIT_ATT; /* set unit attached flag */ + uptr->filename = (char *)malloc(strlen(cptr)+1); + strcpy(uptr->filename, cptr); + controller->line->receive_port = uptr->filename; + dmc_reset_unit_stats(controller->stats); + } + + return ans; +} + +int dmc_isattached(CTLR *controller) +{ + return controller->master_socket != INVALID_SOCKET; +} + +t_stat dmc_detach (UNIT *uptr) +{ + CTLR *controller = dmc_get_controller_from_unit(uptr); + dmc_error_and_close_socket(controller, "Detach"); + dmc_close_master_socket(controller); + uptr->flags = uptr->flags & ~UNIT_ATT; /* clear unit attached flag */ + free(uptr->filename); + uptr->filename = NULL; + sim_cancel(uptr); + + return SCPE_OK; +} diff --git a/PDP11/pdp11_dmc.h b/PDP11/pdp11_dmc.h new file mode 100644 index 00000000..bfa9104b --- /dev/null +++ b/PDP11/pdp11_dmc.h @@ -0,0 +1,136 @@ +/* pdp11_dmc.h: DMC11 Emulation + ------------------------------------------------------------------------------ + + Copyright (c) 2011, Robert M. A. Jarratt + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHOR BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name of the author shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from the author. + + ------------------------------------------------------------------------------*/ + +// Notes +// Base address needs to be 760060 according to DMC11 manual, but SYSGEN seems to think CSR is 0760100. However if I use +// 0760100 I get a conflict with the DZ because the first 13 bits are still 00100. If I use 760060 VMS sees the XM device, but +// if I remove the DZ to prevent the conflict VMS does not see an XM device, but I do get lots of reads and writes, possibly +// because it thinks it is a different device. What worries me more though is that there seems to be overlap in the 13-bit base +// addresses of the DZ and DMC. + + +#ifndef _PDP11_DMC_H +#define _PDP11_DMC_H + +#if defined (VM_VAX) /* VAX version */ +#include "vax_defs.h" +extern int32 int_req[IPL_HLVL]; +#elif defined(VM_PDP10) +#include "pdp10_defs.h" +//#define IPL_HLVL 8 /* # int levels */ +extern int32 int_req; +#else /* PDP-11 version */ +#include "pdp11_defs.h" +extern int32 int_req[IPL_HLVL]; +#endif + +#include "sim_sock.h" + +#define DMC_NUMDEVICE 4 /* # DMC-11 devices */ +#define DMC_UNITSPERDEVICE 1 /* # units per DMC-11 */ + +#define DMP_NUMDEVICE 1 /* # DMP-11 devices */ +#define DMP_UNITSPERDEVICE 1 /* # units per DMP-11 */ + +#define DMC_RDX 8 + +/* debugging bitmaps */ +#define DBG_TRC 0x0001 /* trace routine calls */ +#define DBG_REG 0x0002 /* trace read/write registers */ +#define DBG_WRN 0x0004 /* display warnings */ +#define DBG_INF 0x0008 /* display informational messages (high level trace) */ +#define DBG_DAT 0x0010 /* display data buffer contents */ +#define DBG_DTS 0x0020 /* display data summary */ +#define DBG_SOK 0x0040 /* display socket open/close */ +#define DBG_CON 0x0080 /* display socket connection establishment */ + +#define TYPE_BACCI 0 +#define TYPE_CNTLI 1 +#define TYPE_BASEI 03 +#define TYPE_BACCO 0 +#define TYPE_CNTLO 1 + +#define TYPE_DMP_MODE 2 +#define TYPE_DMP_CONTROL 1 +#define TYPE_DMP_RECEIVE 0 +#define TYPE_DMP_TRANSMIT 4 + + +/* SEL0 */ +#define DMC_TYPE_INPUT_MASK 0x0003 +#define DMC_IN_IO_MASK 0x0004 +#define DMP_IEO_MASK 0x0010 +#define DMC_RQI_MASK 0x0020 +#define DMP_RQI_MASK 0x0080 +#define DMC_RDYI_MASK 0x0080 +#define DMC_IEI_MASK 0x0040 +#define DMP_IEI_MASK 0x0001 +#define LU_LOOP_MASK 0x0800 +#define MASTER_CLEAR_MASK 0x4000 +#define RUN_MASK 0x8000 + +/* SEL2 */ +#define DMP_IN_IO_MASK 0x0004 +#define DMP_TYPE_INPUT_MASK 0x0007 +#define TYPE_OUTPUT_MASK 0x0003 +#define OUT_IO_MASK 0x0004 +#define DMC_RDYO_MASK 0x0080 +#define DMC_IEO_MASK 0x0040 +#define DMP_RDYI_MASK 0x0010 + +/* BSEL6 */ +#define LOST_DATA_MASK 0x0010 +#define DISCONNECT_MASK 0x0040 + +#define SEL0_RUN_BIT 15 +#define SEL0_MCLR_BIT 14 +#define SEL0_LU_LOOP_BIT 11 +#define SEL0_RDI_BIT 7 +#define SEL0_DMC_IEI_BIT 6 +#define SEL0_DMP_IEI_BIT 0 +#define SEL0_DMP_IEO_BIT 4 +#define SEL0_DMC_RQI_BIT 5 +#define SEL0_DMP_RQI_BIT 7 +#define SEL0_IN_IO_BIT 2 +#define SEL0_TYPEI_BIT 0 + +#define SEL2_TYPEO_BIT 0 +#define SEL2_RDO_BIT 7 +#define SEL2_IEO_BIT 6 +#define SEL2_OUT_IO_BIT 2 +#define SEL2_LINE_BIT 8 +#define SEL2_LINE_BIT_LENGTH 6 +#define SEL2_PRIO_BIT 14 +#define SEL2_PRIO_BIT_LENGTH 2 + +#define SEL6_LOST_DATA_BIT 4 +#define SEL6_DISCONNECT_BIT 6 + +#define BUFFER_QUEUE_SIZE 7 + +#endif /* _VAX_DMC_H */ diff --git a/PDP11/pdp11_dz.c b/PDP11/pdp11_dz.c index cf002910..0b4363b9 100644 --- a/PDP11/pdp11_dz.c +++ b/PDP11/pdp11_dz.c @@ -84,8 +84,13 @@ extern int32 int_req[IPL_HLVL]; #if !defined (DZ_LINES) #define DZ_LINES 8 #endif +#define MAX_DZ_MUXES 32 -#define DZ_MNOMASK (DZ_MUXES - 1) /* mask for mux no */ +#if DZ_MUXES > MAX_DZ_MUXES +#error "Too many DZ multiplexers" +#endif + +#define DZ_MNOMASK (dz_desc.lines/DZ_LINES - 1) /* mask for mux no */ #define DZ_LNOMASK (DZ_LINES - 1) /* mask for lineno */ #define DZ_LMASK ((1 << DZ_LINES) - 1) /* mask of lines */ #define DZ_SILO_ALM 16 /* silo alarm level */ @@ -119,9 +124,26 @@ extern int32 int_req[IPL_HLVL]; #define RBUF_VALID 0100000 /* rcv valid */ #define RBUF_MBZ 0004000 +char *dz_charsizes[] = {"5", "6", "7", "8"}; +char *dz_baudrates[] = {"50", "75", "110", "134.5", "150", "300", "600", "1200", + "1800", "2000", "2400", "3600", "4800", "7200", "9600", "19200"}; +char *dz_parity[] = {"N", "E", "N", "O"}; +char *dz_stopbits[] = {"1", "2", "1", "1.5"}; + /* DZLPR - 160102 - line parameter register, write only, word access only */ #define LPR_V_LINE 0 /* line */ +#define LPR_V_SPEED 8 /* speed code */ +#define LPR_M_SPEED 0007400 /* speed code mask */ +#define LPR_V_CHARSIZE 3 /* char size code */ +#define LPR_M_CHARSIZE 0000030 /* char size code mask */ +#define LPR_V_STOPBITS 5 /* stop bits code */ +#define LPR_V_PARENB 6 /* parity enable */ +#define LPR_V_PARODD 7 /* parity odd */ +#define LPR_GETSPD(x) dz_baudrates[((x) & LPR_M_SPEED) >> LPR_V_SPEED] +#define LPR_GETCHARSIZE(x) dz_charsizes[((x) & LPR_M_CHARSIZE) >> LPR_V_CHARSIZE] +#define LPR_GETPARITY(x) dz_parity[(((x) >> LPR_V_PARENB) & 1) | (((x) >> (LPR_V_PARODD-1)) & 2)] +#define LPR_GETSTOPBITS(x) dz_stopbits[(((x) >> LPR_V_STOPBITS) & 1) + (((((x) & LPR_M_CHARSIZE) >> LPR_V_CHARSIZE) == 5) ? 2 : 0)] #define LPR_LPAR 0007770 /* line pars - NI */ #define LPR_RCVE 0010000 /* receive enb */ #define LPR_GETLN(x) (((x) >> LPR_V_LINE) & DZ_LNOMASK) @@ -142,37 +164,37 @@ extern int32 int_req[IPL_HLVL]; #define TDR_V_TBR 8 /* xmit break - NI */ extern int32 IREQ (HLVL); -extern int32 sim_switches; -extern FILE *sim_log; extern int32 tmxr_poll; /* calibrated delay */ -uint16 dz_csr[DZ_MUXES] = { 0 }; /* csr */ -uint16 dz_rbuf[DZ_MUXES] = { 0 }; /* rcv buffer */ -uint16 dz_lpr[DZ_MUXES] = { 0 }; /* line param */ -uint16 dz_tcr[DZ_MUXES] = { 0 }; /* xmit control */ -uint16 dz_msr[DZ_MUXES] = { 0 }; /* modem status */ -uint16 dz_tdr[DZ_MUXES] = { 0 }; /* xmit data */ -uint8 dz_sae[DZ_MUXES] = { 0 }; /* silo alarm enabled */ +uint16 dz_csr[MAX_DZ_MUXES] = { 0 }; /* csr */ +uint16 dz_rbuf[MAX_DZ_MUXES] = { 0 }; /* rcv buffer */ +uint16 dz_lpr[MAX_DZ_MUXES] = { 0 }; /* line param */ +uint16 dz_tcr[MAX_DZ_MUXES] = { 0 }; /* xmit control */ +uint16 dz_msr[MAX_DZ_MUXES] = { 0 }; /* modem status */ +uint16 dz_tdr[MAX_DZ_MUXES] = { 0 }; /* xmit data */ +uint8 dz_sae[MAX_DZ_MUXES] = { 0 }; /* silo alarm enabled */ uint32 dz_rxi = 0; /* rcv interrupts */ uint32 dz_txi = 0; /* xmt interrupts */ int32 dz_mctl = 0; /* modem ctrl enabled */ int32 dz_auto = 0; /* autodiscon enabled */ -TMLN dz_ldsc[DZ_MUXES * DZ_LINES] = { {0} }; /* line descriptors */ -TMXR dz_desc = { DZ_MUXES * DZ_LINES, 0, 0, dz_ldsc }; /* mux descriptor */ +TMLN *dz_ldsc = NULL; /* line descriptors */ +TMXR dz_desc = { DZ_MUXES * DZ_LINES, 0, 0, NULL }; /* mux descriptor */ /* debugging bitmaps */ #define DBG_REG 0x0001 /* trace read/write registers */ #define DBG_INT 0x0002 /* display transfer requests */ -#define DBG_TRC TMXR_DBG_TRC /* trace routine calls */ #define DBG_XMT TMXR_DBG_XMT /* display Transmitted Data */ #define DBG_RCV TMXR_DBG_RCV /* display Received Data */ +#define DBG_TRC TMXR_DBG_TRC /* display trace routine calls */ +#define DBG_ASY TMXR_DBG_ASY /* display Asynchronous Activities */ DEBTAB dz_debug[] = { {"REG", DBG_REG}, {"INT", DBG_INT}, - {"TRC", DBG_TRC}, {"XMT", DBG_XMT}, {"RCV", DBG_RCV}, + {"TRC", DBG_TRC}, + {"ASY", DBG_ASY}, {0} }; @@ -197,6 +219,8 @@ t_stat dz_setnl (UNIT *uptr, int32 val, char *cptr, void *desc); t_stat dz_set_log (UNIT *uptr, int32 val, char *cptr, void *desc); t_stat dz_set_nolog (UNIT *uptr, int32 val, char *cptr, void *desc); t_stat dz_show_log (FILE *st, UNIT *uptr, int32 val, void *desc); +t_stat dz_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr); +t_stat dz_help_attach (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr); /* DZ data structures @@ -205,25 +229,27 @@ t_stat dz_show_log (FILE *st, UNIT *uptr, int32 val, void *desc); dz_reg DZ register list */ +#define IOLN_DZ 010 + DIB dz_dib = { - IOBA_DZ, IOLN_DZ * DZ_MUXES, &dz_rd, &dz_wr, - 2, IVCL (DZRX), VEC_DZRX, { &dz_rxinta, &dz_txinta } + IOBA_AUTO, IOLN_DZ * DZ_MUXES, &dz_rd, &dz_wr, + 2, IVCL (DZRX), VEC_AUTO, { &dz_rxinta, &dz_txinta } }; UNIT dz_unit = { UDATA (&dz_svc, UNIT_IDLE|UNIT_ATTABLE|DZ_8B_DFLT, 0) }; REG dz_reg[] = { - { BRDATA (CSR, dz_csr, DEV_RDX, 16, DZ_MUXES) }, - { BRDATA (RBUF, dz_rbuf, DEV_RDX, 16, DZ_MUXES) }, - { BRDATA (LPR, dz_lpr, DEV_RDX, 16, DZ_MUXES) }, - { BRDATA (TCR, dz_tcr, DEV_RDX, 16, DZ_MUXES) }, - { BRDATA (MSR, dz_msr, DEV_RDX, 16, DZ_MUXES) }, - { BRDATA (TDR, dz_tdr, DEV_RDX, 16, DZ_MUXES) }, - { BRDATA (SAENB, dz_sae, DEV_RDX, 1, DZ_MUXES) }, - { GRDATA (RXINT, dz_rxi, DEV_RDX, DZ_MUXES, 0) }, - { GRDATA (TXINT, dz_txi, DEV_RDX, DZ_MUXES, 0) }, - { FLDATA (MDMCTL, dz_mctl, 0) }, - { FLDATA (AUTODS, dz_auto, 0) }, + { BRDATAD (CSR, dz_csr, DEV_RDX, 16, MAX_DZ_MUXES, "control/status register") }, + { BRDATAD (RBUF, dz_rbuf, DEV_RDX, 16, MAX_DZ_MUXES, "receive buffer") }, + { BRDATAD (LPR, dz_lpr, DEV_RDX, 16, MAX_DZ_MUXES, "line parameter register") }, + { BRDATAD (TCR, dz_tcr, DEV_RDX, 16, MAX_DZ_MUXES, "transmission control register") }, + { BRDATAD (MSR, dz_msr, DEV_RDX, 16, MAX_DZ_MUXES, "modem status register") }, + { BRDATAD (TDR, dz_tdr, DEV_RDX, 16, MAX_DZ_MUXES, "transmit data register") }, + { BRDATAD (SAENB, dz_sae, DEV_RDX, 1, MAX_DZ_MUXES, "silo alarm enabled") }, + { GRDATAD (RXINT, dz_rxi, DEV_RDX, MAX_DZ_MUXES, 0, "receive interrupts") }, + { GRDATAD (TXINT, dz_txi, DEV_RDX, MAX_DZ_MUXES, 0, "transmit interrupts") }, + { FLDATAD (MDMCTL, dz_mctl, 0, "modem control enabled") }, + { FLDATAD (AUTODS, dz_auto, 0, "autodisconnect enabled") }, { GRDATA (DEVADDR, dz_dib.ba, DEV_RDX, 32, 0), REG_HRO }, { GRDATA (DEVVEC, dz_dib.vec, DEV_RDX, 16, 0), REG_HRO }, { NULL } @@ -265,8 +291,10 @@ DEVICE dz_dev = { 1, DEV_RDX, 8, 1, DEV_RDX, 8, &tmxr_ex, &tmxr_dep, &dz_reset, NULL, &dz_attach, &dz_detach, - &dz_dib, DEV_FLTA | DEV_DISABLE | DEV_NET | DEV_UBUS | DEV_QBUS | DEV_DEBUG, - 0, dz_debug + &dz_dib, DEV_DISABLE | DEV_UBUS | DEV_QBUS | DEV_DEBUG | DEV_MUX, + 0, dz_debug, NULL, NULL, + &dz_help, &dz_help_attach, /* help and attach_help routines */ + (void *)&dz_desc /* help context variable */ }; /* Register names for Debug tracing */ @@ -279,6 +307,7 @@ static char *dz_wr_regs[] = t_stat dz_rd (int32 *data, int32 PA, int32 access) { +int i; int32 dz = ((PA - dz_dib.ba) >> 3) & DZ_MNOMASK; /* get mux num */ switch ((PA >> 1) & 03) { /* case on PA<2:1> */ @@ -308,6 +337,20 @@ switch ((PA >> 1) & 03) { /* case on PA<2:1> */ break; case 03: /* MSR */ + if (dz_mctl) + for (i=0; i> 3) & DZ_MNOMASK; /* get mux num */ int32 i, c, line; +char lineconfig[16]; TMLN *lp; sim_debug(DBG_REG, &dz_dev, "dz_wr(PA=0x%08X [%s], access=%d, data=0x%X)\n", PA, dz_wr_regs[(PA >> 1) & 03], access, data); @@ -356,6 +400,11 @@ switch ((PA >> 1) & 03) { /* case on PA<2:1> */ if (dz_lpr[dz] & LPR_RCVE) /* rcv enb? on */ lp->rcve = 1; else lp->rcve = 0; /* else line off */ + if (dz_mctl) { + sprintf(lineconfig, "%s-%s%s%s", LPR_GETSPD(data), LPR_GETCHARSIZE(data), LPR_GETPARITY(data), LPR_GETSTOPBITS(data)); + if (!lp->serconfig || (0 != strcmp(lp->serconfig, lineconfig))) /* config changed? */ + tmxr_set_config_line (lp, lineconfig); /* set it */ + } tmxr_poll_rx (&dz_desc); /* poll input */ dz_update_rcvi (); /* update rx intr */ break; @@ -365,23 +414,20 @@ switch ((PA >> 1) & 03) { /* case on PA<2:1> */ (dz_tcr[dz] & 0377) | (data << 8): (dz_tcr[dz] & ~0377) | data; if (dz_mctl) { /* modem ctl? */ - dz_msr[dz] |= ((data & 0177400) & /* dcd |= dtr & ring */ - ((dz_msr[dz] & DZ_LMASK) << MSR_V_CD)); - dz_msr[dz] &= ~(data >> TCR_V_DTR); /* ring &= ~dtr */ - if (dz_auto) { /* auto disconnect? */ - int32 drop; - drop = (dz_tcr[dz] & ~data) >> TCR_V_DTR; /* drop = dtr & ~data */ - for (i = 0; i < DZ_LINES; i++) { /* drop hangups */ - line = (dz * DZ_LINES) + i; /* get line num */ - lp = &dz_ldsc[line]; /* get line desc */ - if (lp->conn && (drop & (1 << i))) { - tmxr_linemsg (lp, "\r\nLine hangup\r\n"); - tmxr_reset_ln (lp); /* reset line, cdet */ - dz_msr[dz] &= ~(1 << (i + MSR_V_CD)); - } /* end if drop */ - } /* end for */ - } /* end if auto */ - } /* end if modem */ + int32 changed = data ^ dz_tcr[dz]; + + for (i = 0; i < DZ_LINES; i++) { + if (0 == (changed & (1 << (TCR_V_DTR + i)))) + continue; /* line unchanged skip */ + line = (dz * DZ_LINES) + i; /* get line num */ + lp = &dz_ldsc[line]; /* get line desc */ + if (data & (1 << (TCR_V_DTR + i))) + tmxr_set_get_modem_bits (lp, TMXR_MDM_DTR|TMXR_MDM_RTS, 0, NULL); + else + if (dz_auto) + tmxr_set_get_modem_bits (lp, 0, TMXR_MDM_DTR|TMXR_MDM_RTS, NULL); + } + } dz_tcr[dz] = data; tmxr_poll_tx (&dz_desc); /* poll output */ dz_update_xmti (); /* update int */ @@ -421,19 +467,19 @@ return SCPE_OK; t_stat dz_svc (UNIT *uptr) { -int32 dz, t, newln; +int32 dz, t, newln, muxln; sim_debug(DBG_TRC, find_dev_from_unit(uptr), "dz_svc()\n"); - -for (dz = t = 0; dz < DZ_MUXES; dz++) /* check enabled */ +for (dz = t = 0; dz < dz_desc.lines/DZ_LINES; dz++) /* check enabled */ t = t | (dz_csr[dz] & CSR_MSE); if (t) { /* any enabled? */ newln = tmxr_poll_conn (&dz_desc); /* poll connect */ if ((newln >= 0) && dz_mctl) { /* got a live one? */ dz = newln / DZ_LINES; /* get mux num */ - if (dz_tcr[dz] & (1 << (newln + TCR_V_DTR))) /* DTR set? */ - dz_msr[dz] |= (1 << (newln + MSR_V_CD)); /* set cdet */ - else dz_msr[dz] |= (1 << newln); /* set ring */ + muxln = newln % DZ_LINES; /* get line in mux */ + if (dz_tcr[dz] & (1 << (muxln + TCR_V_DTR))) /* DTR set? */ + dz_msr[dz] |= (1 << (muxln + MSR_V_CD)); /* set cdet */ + else dz_msr[dz] |= (1 << (muxln + MSR_V_RI)); /* set ring */ } tmxr_poll_rx (&dz_desc); /* poll input */ dz_update_rcvi (); /* upd rcv intr */ @@ -465,10 +511,10 @@ return c; void dz_update_rcvi (void) { -int32 i, dz, line, scnt[DZ_MUXES]; +int32 i, dz, line, scnt[MAX_DZ_MUXES]; TMLN *lp; -for (dz = 0; dz < DZ_MUXES; dz++) { /* loop thru muxes */ +for (dz = 0; dz < dz_desc.lines/DZ_LINES; dz++) { /* loop thru muxes */ scnt[dz] = 0; /* clr input count */ for (i = 0; i < DZ_LINES; i++) { /* poll lines */ line = (dz * DZ_LINES) + i; /* get line num */ @@ -478,7 +524,7 @@ for (dz = 0; dz < DZ_MUXES; dz++) { /* loop thru muxes */ dz_msr[dz] &= ~(1 << (i + MSR_V_CD)); /* reset car det */ } } -for (dz = 0; dz < DZ_MUXES; dz++) { /* loop thru muxes */ +for (dz = 0; dz < dz_desc.lines/DZ_LINES; dz++) { /* loop thru muxes */ if (scnt[dz] && (dz_csr[dz] & CSR_MSE)) { /* input & enabled? */ dz_csr[dz] |= CSR_RDONE; /* set done */ if (dz_sae[dz] && (scnt[dz] >= DZ_SILO_ALM)) { /* alm enb & cnt hi? */ @@ -502,7 +548,7 @@ void dz_update_xmti (void) { int32 dz, linemask, i, j, line; -for (dz = 0; dz < DZ_MUXES; dz++) { /* loop thru muxes */ +for (dz = 0; dz < dz_desc.lines/DZ_LINES; dz++) { /* loop thru muxes */ linemask = dz_tcr[dz] & DZ_LMASK; /* enabled lines */ dz_csr[dz] &= ~CSR_TRDY; /* assume not rdy */ j = CSR_GETTL (dz_csr[dz]); /* start at current */ @@ -544,7 +590,7 @@ int32 dz_rxinta (void) { int32 dz; -for (dz = 0; dz < DZ_MUXES; dz++) { /* find 1st mux */ +for (dz = 0; dz < dz_desc.lines/DZ_LINES; dz++) { /* find 1st mux */ if (dz_rxi & (1 << dz)) { sim_debug(DBG_INT, &dz_dev, "dz_rzinta(dz=%d)\n", dz); dz_clr_rxint (dz); /* clear intr */ @@ -574,7 +620,7 @@ int32 dz_txinta (void) { int32 dz; -for (dz = 0; dz < DZ_MUXES; dz++) { /* find 1st mux */ +for (dz = 0; dz < dz_desc.lines/DZ_LINES; dz++) { /* find 1st mux */ if (dz_txi & (1 << dz)) { sim_debug(DBG_INT, &dz_dev, "dz_txinta(dz=%d)\n", dz); dz_clr_txint (dz); /* clear intr */ @@ -613,7 +659,9 @@ t_stat dz_reset (DEVICE *dptr) { int32 i, ndev; -for (i = 0; i < DZ_MUXES; i++) /* init muxes */ +if (dz_ldsc == NULL) + dz_desc.ldsc = dz_ldsc = calloc (dz_desc.lines, sizeof(*dz_ldsc)); +for (i = 0; i < dz_desc.lines/DZ_LINES; i++) /* init muxes */ dz_clear (i, TRUE); dz_rxi = dz_txi = 0; /* clr master int */ CLR_INT (DZRX); @@ -627,13 +675,16 @@ return auto_config (dptr->name, ndev); /* auto config */ t_stat dz_attach (UNIT *uptr, char *cptr) { +int32 dz, muxln; t_stat r; -extern int32 sim_switches; -dz_mctl = dz_auto = 0; /* modem ctl off */ +if (sim_switches & SWMASK ('M')) /* modem control? */ + tmxr_set_modem_control_passthru (&dz_desc); r = tmxr_attach (&dz_desc, uptr, cptr); /* attach mux */ -if (r != SCPE_OK) /* error? */ +if (r != SCPE_OK) { /* error? */ + tmxr_clear_modem_control_passthru (&dz_desc); return r; + } if (sim_switches & SWMASK ('M')) { /* modem control? */ dz_mctl = 1; printf ("Modem control activated\n"); @@ -646,6 +697,18 @@ if (sim_switches & SWMASK ('M')) { /* modem control? */ fprintf (sim_log, "Auto disconnect activated\n"); } } + +for (dz = 0; dz < dz_desc.lines/DZ_LINES; dz++) { + if (!dz_mctl || (0 == (dz_csr[dz] & CSR_MSE))) /* enabled? */ + continue; + for (muxln = 0; muxln < DZ_LINES; muxln++) { + if (dz_tcr[dz] & (1 << (muxln + TCR_V_DTR))) { + TMLN *lp = &dz_ldsc[(dz * DZ_LINES) + muxln]; + + tmxr_set_get_modem_bits (lp, TMXR_MDM_DTR|TMXR_MDM_RTS, 0, NULL); + } + } + } return SCPE_OK; } @@ -653,6 +716,7 @@ return SCPE_OK; t_stat dz_detach (UNIT *uptr) { +dz_mctl = dz_auto = 0; /* modem ctl off */ return tmxr_detach (&dz_desc, uptr); } @@ -660,12 +724,12 @@ return tmxr_detach (&dz_desc, uptr); t_stat dz_setnl (UNIT *uptr, int32 val, char *cptr, void *desc) { -int32 newln, i, t, ndev; +int32 newln, i, t; t_stat r; if (cptr == NULL) return SCPE_ARG; -newln = (int32) get_uint (cptr, 10, (DZ_MUXES * DZ_LINES), &r); +newln = (int32) get_uint (cptr, 10, (MAX_DZ_MUXES * DZ_LINES), &r); if ((r != SCPE_OK) || (newln == dz_desc.lines)) return r; if ((newln == 0) || (newln % DZ_LINES)) @@ -685,9 +749,11 @@ if (newln < dz_desc.lines) { } } dz_dib.lnt = (newln / DZ_LINES) * IOLN_DZ; /* set length */ +dz_desc.ldsc = dz_ldsc = realloc(dz_ldsc, newln*sizeof(*dz_ldsc)); +if (dz_desc.lines < newln) + memset (dz_ldsc + dz_desc.lines, 0, sizeof(*dz_ldsc)*(newln-dz_desc.lines)); dz_desc.lines = newln; -ndev = ((dz_dev.flags & DEV_DIS)? 0: (dz_desc.lines / DZ_LINES)); -return auto_config (dz_dev.name, ndev); /* auto config */ +return dz_reset (&dz_dev); /* setup lines and auto config */ } /* SET LOG processor */ @@ -704,7 +770,7 @@ tptr = strchr (cptr, '='); if ((tptr == NULL) || (*tptr == 0)) return SCPE_ARG; *tptr++ = 0; -ln = (int32) get_uint (cptr, 10, (DZ_MUXES * DZ_LINES), &r); +ln = (int32) get_uint (cptr, 10, dz_desc.lines, &r); if ((r != SCPE_OK) || (ln >= dz_desc.lines)) return SCPE_ARG; return tmxr_set_log (NULL, ln, tptr, desc); @@ -719,7 +785,7 @@ int32 ln; if (cptr == NULL) return SCPE_ARG; -ln = (int32) get_uint (cptr, 10, (DZ_MUXES * DZ_LINES), &r); +ln = (int32) get_uint (cptr, 10, dz_desc.lines, &r); if ((r != SCPE_OK) || (ln >= dz_desc.lines)) return SCPE_ARG; return tmxr_set_nolog (NULL, ln, NULL, desc); @@ -739,5 +805,61 @@ for (i = 0; i < dz_desc.lines; i++) { return SCPE_OK; } +t_stat dz_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr) +{ +char *devtype = (UNIBUS) ? "DZ11" : "DZV11"; +fprintf (st, "%s Terminal Multiplexer (DZ)\n\n", devtype); +fprintf (st, "The %s is a %d line terminal multiplexor. Up to %d %s's (%d lines) are\n", devtype, DZ_LINES, MAX_DZ_MUXES, devtype, DZ_LINES*MAX_DZ_MUXES); +fprintf (st, "supported. The default number of lines is %d. The number of lines can\n", DZ_LINES*DZ_MUXES); +fprintf (st, "be changed with the command\n\n"); +fprintf (st, " sim> SET %s LINES=n set line count to n\n\n", dptr->name); +fprintf (st, "The line count must be a multiple of %d, with a maximum of %d.\n\n", DZ_LINES, DZ_LINES*MAX_DZ_MUXES); +fprintf (st, "The %s supports three character processing modes, 7P, 7B, and 8B:\n\n", devtype); +fprintf (st, " mode input characters output characters\n"); +fprintf (st, " =============================================\n"); +fprintf (st, " 7P high-order bit cleared high-order bit cleared,\n"); +fprintf (st, " non-printing characters suppressed\n"); +fprintf (st, " 7B high-order bit cleared high-order bit cleared\n"); +fprintf (st, " 8B no changes no changes\n\n"); +fprintf (st, "The default is 8B.\n\n"); +fprintf (st, "The %s supports logging on a per-line basis. The command\n\n", devtype); +fprintf (st, " sim> SET %s LOG=n=filename\n\n", dptr->name); +fprintf (st, "enables logging for the specified line(n) to the indicated file. The command\n\n"); +fprintf (st, " sim> SET %s NOLOG=line\n\n", dptr->name); +fprintf (st, "disables logging for the specified line and closes any open log file. Finally,\n"); +fprintf (st, "the command:\n\n"); +fprintf (st, " sim> SHOW %s LOG\n\n", dptr->name); +fprintf (st, "displays logging information for all %s lines.\n\n", dptr->name); +fprintf (st, "Once the %s is attached and the simulator is running, the %s will listen for\n", devtype, devtype); +fprintf (st, "connections on the specified port. It assumes that the incoming connections\n"); +fprintf (st, "are Telnet connections. The connection remains open until disconnected by the\n"); +fprintf (st, "simulated program, the Telnet client, a SET %s DISCONNECT command, or a\n", dptr->name); +fprintf (st, "DETACH %s command.\n\n", dptr->name); +fprintf (st, "Other special %s commands:\n\n", dptr->name); +fprintf (st, " sim> SHOW %s CONNECTIONS show current connections\n", dptr->name); +fprintf (st, " sim> SHOW %s STATISTICS show statistics for active connections\n", dptr->name); +fprintf (st, " sim> SET %s DISCONNECT=linenumber disconnects the specified line.\n\n\n", dptr->name); +fprintf (st, "All open connections are lost when the simulator shuts down or the %s is\n", dptr->name); +fprintf (st, "detached.\n"); +return SCPE_OK; +} + +t_stat dz_help_attach (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr) +{ +char *devtype = (UNIBUS) ? "DZ11" : "DZV11"; + +tmxr_attach_help (st, dptr, uptr, flag, cptr); +fprintf (st, "The terminal lines perform input and output through Telnet sessions connected\n"); +fprintf (st, "to a user-specified port. The ATTACH command specifies the port to be used:\n\n"); +fprintf (st, " sim> ATTACH {-am} %s {interface:}port set up listening port\n\n", dptr->name); +fprintf (st, "where port is a decimal number between 1 and 65535 that is not being used for\n"); +fprintf (st, "other TCP/IP activities. The optional switch -m turns on the %s's modem\n", devtype); +fprintf (st, "controls; the optional switch -a turns on active disconnects (disconnect\n"); +fprintf (st, "session if computer clears Data Terminal Ready). Without modem control, the\n"); +fprintf (st, "%s behaves as though terminals were directly connected; disconnecting the\n", devtype); +fprintf (st, "Telnet session does not cause any operating system-visible change in line\n"); +fprintf (st, "status.\n\n"); +return SCPE_OK; +} diff --git a/PDP11/pdp11_hk.c b/PDP11/pdp11_hk.c index 7d949d07..ca62cd82 100644 --- a/PDP11/pdp11_hk.c +++ b/PDP11/pdp11_hk.c @@ -25,6 +25,7 @@ hk RK611/RK06/RK07 disk + 10-Dec-12 RMS Fixed interrupt logic 19-Mar-12 RMS Fixed declaration of cpu_opt (Mark Pizzolato) 29-Apr-07 RMS NOP and DCLR (at least) do not check drive type MR2 and MR3 only updated on NOP @@ -136,12 +137,44 @@ extern uint16 *M; #define GET_UAE(x) (((x) >> CS1_V_UAE) & CS1_M_UAE) #define PUT_UAE(x,n) (((x) & ~ CS1_UAE) | (((n) << CS1_V_UAE) & CS1_UAE)) +static const char *hk_funcs[] = { + "NOP", "PACK", "DCLR", "UNLOAD", "START", "RECAL", "OFFSET", "SEEK", + "READ", "WRITE", "READH", "WRITEH", "WCHK"}; + +BITFIELD hk_cs1_bits[] = { + BIT(GO), /* go */ + BITFNAM(FNC,4,hk_funcs), /* function */ + BIT(SPARE), /* Spare Bit */ + BIT(IE), /* Interrupt Enable */ + BIT(RDY), /* Controller Ready */ + BIT(BA16), /* Unibus addr ext bit 16 */ + BIT(BA17), /* Unibus addr ext bit 17 */ + BIT(DT), /* Controller Drive Type */ + BIT(CTO), /* Controller Timeout */ + BIT(CFMT), /* Controller Format */ + BIT(DTCPAR), /* Drive-To-Controller Parity Error */ + BIT(DI), /* Drive Interrupt */ + BIT(ERR), /* error */ + ENDBITS +}; + + /* HKWC - 177442 - word count */ +BITFIELD hk_wc_bits[] = { + BITF(WC,16), /* Word Count */ + ENDBITS +}; + /* HKBA - 177444 - base address */ #define BA_MBZ 0000001 /* must be zero */ +BITFIELD hk_ba_bits[] = { + BITF(BA,16), /* Bus Address */ + ENDBITS +}; + /* HKDA - 177446 - sector/track */ #define DA_V_SC 0 /* sector pos */ @@ -152,6 +185,14 @@ extern uint16 *M; #define GET_SC(x) (((x) >> DA_V_SC) & DA_M_SC) #define GET_SF(x) (((x) >> DA_V_SF) & DA_M_SF) +BITFIELD hk_da_bits[] = { + BITF(SA,5), /* Sector */ + BITNCF(3), /* 05:07 Zero */ + BITF(TA,3), /* Track */ + BITNCF(5), /* 11:15 Zero */ + ENDBITS +}; + /* HKCS2 - 177450 - control/status 2 */ #define CS2_V_UNIT 0 /* unit pos */ @@ -176,6 +217,25 @@ extern uint16 *M; CS2_NED | CS2_PE | CS2_WCE | CS2_DLT ) #define GET_UNIT(x) (((x) >> CS2_V_UNIT) & CS2_M_UNIT) +BITFIELD hk_cs2_bits[] = { + BITF(DS,3), /* Drive Select */ + BIT(RLS), /* Release */ + BIT(BAI), /* Bus Address Increment Inhibit */ + BIT(SCLR), /* Subsystem Clear */ + BIT(IR), /* Input Ready */ + BIT(OR), /* Output Ready */ + BIT(UFE), /* Unit Field Error */ + BIT(MDS), /* Multiple Drive Select */ + BIT(PGE), /* Programming Error */ + BIT(NEM), /* Nonexistant Memory */ + BIT(NED), /* Nonexistant Drive */ + BIT(UPE), /* Unibus Parity Error */ + BIT(WCE), /* Write Check Error */ + BIT(DLT), /* Data Late Error */ + ENDBITS +}; + + /* HKDS - 177452 - drive status ^ = calculated dynamically */ #define DS_DRA 0000001 /* ^drive avail */ @@ -192,6 +252,25 @@ extern uint16 *M; #define DS_VLD 0100000 /* ^status valid */ #define DS_MBZ 0013002 +BITFIELD hk_ds_bits[] = { + BIT(DRA), /* Drive Available */ + BITNCF(1), /* 01 Spare */ + BIT(OFST), /* Offset */ + BIT(ACLO), /* Drive AC Low */ + BIT(SPLS), /* Speed Loss */ + BIT(DROT), /* Drive Off Track */ + BIT(VV), /* Volume Valid */ + BIT(DRDY), /* Drive Ready */ + BIT(DDT), /* Disk Drive Type */ + BITNCF(2), /* 09:10 Spare */ + BIT(WRL), /* Write Lock */ + BITNCF(1), /* 12 Spare */ + BIT(PIP), /* Positioning in Progress */ + BIT(ATA), /* Current Drive Attention */ + BIT(SVAL), /* Status Valid */ + ENDBITS +}; + /* HKER - 177454 - error status */ #define ER_ILF 0000001 /* illegal func */ @@ -211,11 +290,44 @@ extern uint16 *M; #define ER_UNS 0040000 /* drive unsafe */ #define ER_DCK 0100000 /* data check NI */ +BITFIELD hk_er_bits[] = { + BIT(ILF), /* Illegal Function */ + BIT(SKI), /* Seek Incomplete */ + BIT(NXF), /* Nonexecutable Function */ + BIT(DROAR), /* Control-to-Drive Parity Error */ + BIT(FMTE), /* Format Error */ + BIT(DTYE), /* Drive Type Error */ + BIT(ECH), /* Error Correction Hard */ + BIT(BSE), /* Bad Sector Error */ + BIT(HRVC), /* Header Virtical Redundancy */ + BIT(COE), /* Cylinder Overflow Error */ + BIT(IDAE), /* Invalid Disk Address Error */ + BIT(WLE), /* Write Lock Error */ + BIT(DTE), /* Drive Timing Error */ + BIT(OPI), /* Operation Incomplete */ + BIT(UNS), /* Drive Unsafe */ + BIT(DCK), /* Data Check */ + ENDBITS +}; + /* HKAS - 177456 - attention summary/offset */ #define AS_U0 0000400 /* unit 0 flag */ #define AS_OF 0000277 /* offset mask */ +BITFIELD hk_as_bits[] = { + BITF(OF,8), /* Offset */ + BIT(ATN0), /* Attention Drive 0 */ + BIT(ATN1), /* Attention Drive 1 */ + BIT(ATN2), /* Attention Drive 2 */ + BIT(ATN3), /* Attention Drive 3 */ + BIT(ATN4), /* Attention Drive 4 */ + BIT(ATN5), /* Attention Drive 5 */ + BIT(ATN6), /* Attention Drive 6 */ + BIT(ATN7), /* Attention Drive 7 */ + ENDBITS +}; + /* HKDC - 177460 - desired cylinder */ #define DC_V_CY 0 /* cylinder pos */ @@ -225,6 +337,12 @@ extern uint16 *M; #define GET_DA(c,fs) ((((GET_CY (c) * HK_NUMSF) + \ GET_SF (fs)) * HK_NUMSC) + GET_SC (fs)) +BITFIELD hk_dc_bits[] = { + BITF(DC,10), /* Desired Cylinder */ + BITNCF(6), /* 10:15 Spare */ + ENDBITS +}; + /* Spare - 177462 - read/write */ #define XM_KMASK 0177700 /* Qbus XM key mask */ @@ -234,6 +352,11 @@ extern uint16 *M; /* HKDB - 177464 - read/write */ +BITFIELD hk_db_bits[] = { + BITF(DB,16), /* Data Buffer Register */ + ENDBITS +}; + /* HKMR - 177466 - maintenance register 1 */ #define MR_V_MS 0 /* message select */ @@ -244,9 +367,37 @@ extern uint16 *M; #define MR_DMD 0000040 /* diagnostic mode */ #define MR_RW 0001777 +BITFIELD hk_mr_bits[] = { + BITF(MS,4), /* Message Select */ + BIT(PAT), /* Parity Test */ + BIT(DMD), /* Diagnostic Mode */ + BIT(MSP), /* Maintenance Selector Pulse */ + BIT(MIND), /* Maintenance Index */ + BIT(MCLK), /* Maintenance Clock */ + BIT(MERD), /* Maintenance Encoded Read Data */ + BIT(MEWD), /* Maintenance Encoded Write Data */ + BIT(PCA), /* Precompensation Advance */ + BIT(PCD), /* Precompensation Delay */ + BIT(ECCW), /* ECC Word */ + BIT(WRTGT), /* Write Gate */ + BIT(RDGT), /* Read Gate */ + ENDBITS +}; + /* HKEC1 - 177470 - ECC status 1 - always reads as 0 */ + +BITFIELD hk_ec1_bits[] = { + BITF(EC1,16), /* ECC status 1 */ + ENDBITS +}; + /* HKEC2 - 177472 - ECC status 2 - always reads as 0 */ +BITFIELD hk_ec2_bits[] = { + BITF(EC2,16), /* ECC status 2 */ + ENDBITS +}; + /* HKMR2 - 177474 - maintenance register 2 */ #define AX_V_UNIT 0 /* unit #, all msgs */ @@ -280,6 +431,11 @@ extern uint16 *M; #define A3_V_SNO 3 /* serial # */ +BITFIELD hk_mr2_bits[] = { + BITF(MR2,16), /* Maintenance Register 2 */ + ENDBITS +}; + /* HKMR3 - 177476 - maintenance register 3 */ #define B0_IAE 0000040 /* invalid addr */ @@ -317,14 +473,58 @@ extern uint16 *M; #define RDH2_V_DHA 5 /* decoded head */ #define RDH2_GOOD 0140000 /* good sector flags */ +BITFIELD hk_mr3_bits[] = { + BITF(MR3,16), /* Maintenance Register 3 */ + ENDBITS +}; + +char *hk_regnames[] = { + "HKCS1", + "HKWC", + "HKBA", + "HKDA", + "HKCS2", + "HKDS", + "HKER", + "HKAS", + "HKDC", + "spare", + "HKDB", + "HKMR", + "HKEC1", + "HKEC2", + "HKMR2", + "HKMR3" + }; + +BITFIELD *hk_reg_bits[] = { + hk_cs1_bits, + hk_wc_bits, + hk_ba_bits, + hk_da_bits, + hk_cs2_bits, + hk_ds_bits, + hk_er_bits, + hk_as_bits, + hk_dc_bits, + NULL, + hk_db_bits, + hk_mr_bits, + hk_ec1_bits, + hk_ec2_bits, + hk_mr2_bits, + hk_mr3_bits, + }; + /* Debug detail levels */ #define HKDEB_OPS 001 /* transactions */ #define HKDEB_RRD 002 /* reg reads */ #define HKDEB_RWR 004 /* reg writes */ +#define HKDEB_TRC 010 /* trace */ +#define HKDEB_INT 020 /* interrupts */ extern int32 int_req[IPL_HLVL]; -extern FILE *sim_deb; uint16 *hkxb = NULL; /* xfer buffer */ int32 hkcs1 = 0; /* control/status 1 */ @@ -375,9 +575,11 @@ t_stat hk_set_bad (UNIT *uptr, int32 val, char *cptr, void *desc); hk_mod HK modifier list */ +#define IOLN_HK 040 + DIB hk_dib = { - IOBA_HK, IOLN_HK, &hk_rd, &hk_wr, - 1, IVCL (HK), VEC_HK, { NULL } + IOBA_AUTO, IOLN_HK, &hk_rd, &hk_wr, + 1, IVCL (HK), VEC_AUTO, { NULL } }; UNIT hk_unit[] = { @@ -464,6 +666,8 @@ DEBTAB hk_deb[] = { { "OPS", HKDEB_OPS }, { "RRD", HKDEB_RRD }, { "RWR", HKDEB_RWR }, + { "INTERRUPT", HKDEB_INT }, + { "TRACE", HKDEB_TRC }, { NULL, 0 } }; @@ -563,18 +767,16 @@ switch (j) { /* decode PA<4:1> */ break; } -if (DEBUG_PRI (hk_dev, HKDEB_RRD)) - fprintf (sim_deb, ">>HK%d read: reg%d=%o\n", drv, j, *data); +sim_debug (HKDEB_RRD, &hk_dev, ">>HK%d read: %s=0%o\n", drv, hk_regnames[j], *data); +sim_debug_bits (HKDEB_RRD, &hk_dev, hk_reg_bits[j], *data, *data, 1); return SCPE_OK; } t_stat hk_wr (int32 data, int32 PA, int32 access) { -int32 drv, i, j; -UNIT *uptr; +int32 drv, i, j, old_val = 0, new_val = 0; drv = GET_UNIT (hkcs2); /* get current unit */ -uptr = hk_dev.units + drv; /* get unit */ j = (PA >> 1) & 017; /* get reg offset */ if ((hkcs1 & CS1_GO) && /* busy? */ !(((j == 0) && (data & CS1_CCLR)) || /* not cclr or sclr? */ @@ -584,11 +786,11 @@ if ((hkcs1 & CS1_GO) && /* busy? */ return SCPE_OK; } -if (DEBUG_PRI (hk_dev, HKDEB_RWR)) - fprintf (sim_deb, ">>HK%d write: reg%d=%o\n", drv, j, data); +sim_debug (HKDEB_RWR, &hk_dev, ">>HK%d write: %s=0%o\n", drv, hk_regnames[j], data); switch (j) { /* decode PA<4:1> */ case 000: /* HKCS1 */ + old_val = hkcs1; if (data & CS1_CCLR) { /* controller reset? */ hkcs1 = CS1_DONE; /* CS1 = done */ hkcs2 = CS2_IR; /* CS2 = ready */ @@ -599,68 +801,98 @@ switch (j) { /* decode PA<4:1> */ CLR_INT (HK); /* clr int */ for (i = 0; i < HK_NUMDR; i++) { /* stop data xfr */ if (sim_is_active (&hk_unit[i]) && - ((uptr->FNC & CS1_M_FNC) >= FNC_XFER)) + ((hk_unit[i].FNC & CS1_M_FNC) >= FNC_XFER)) sim_cancel (&hk_unit[i]); } drv = 0; break; } if (data & CS1_IE) { /* setting IE? */ - if (data & CS1_DONE) /* write to DONE+IE? */ + if (data & CS1_DONE) { /* write to DONE+IE? */ + sim_debug (HKDEB_INT, &hk_dev, "hk_wr(SET_INT)\n"); SET_INT (HK); + } + } + else { + sim_debug (HKDEB_INT, &hk_dev, "hk_wr(CLR_INT)\n"); + CLR_INT (HK); /* no, clr intr */ } - else CLR_INT (HK); /* no, clr intr */ hkcs1 = (hkcs1 & ~CS1_RW) | (data & CS1_RW); /* merge data */ if (SC02C) hkspr = (hkspr & ~CS1_M_UAE) | GET_UAE (hkcs1); if ((data & CS1_GO) && !(hkcs1 & CS1_ERR)) /* go? */ hk_go (drv); + new_val = hkcs1; break; case 001: /* HKWC */ - hkwc = data; + old_val = hkwc; + new_val = hkwc = data; break; case 002: /* HKBA */ - hkba = data & ~BA_MBZ; + old_val = hkba; + new_val = hkba = data & ~BA_MBZ; break; case 003: /* HKDA */ - hkda = data & ~DA_MBZ; + old_val = hkda; + new_val = hkda = data & ~DA_MBZ; break; case 004: /* HKCS2 */ + old_val = hkcs2; if (data & CS2_CLR) /* init? */ hk_reset (&hk_dev); else hkcs2 = (hkcs2 & ~CS2_RW) | (data & CS2_RW) | CS2_IR; drv = GET_UNIT (hkcs2); + new_val = hkcs2; break; case 007: /* HKAS */ - hkof = data & AS_OF; + old_val = hkof; + new_val = hkof = data & AS_OF; break; case 010: /* HKDC */ - hkdc = data & ~DC_MBZ; + old_val = hkdc; + new_val = hkdc = data & ~DC_MBZ; break; case 011: /* spare */ - hkspr = data; + old_val = hkspr; + new_val = hkspr = data; if (SC02C) /* SC02C? upd UAE */ hkcs1 = PUT_UAE (hkcs1, hkspr & 03); break; case 012: /* HKDB */ - hkdb[0] = data; + old_val = hkdb[0]; + new_val = hkdb[0] = data; break; case 013: /* HKMR */ - hkmr = data & MR_RW; + old_val = hkmr; + new_val = hkmr = data & MR_RW; break; - default: /* all others RO */ + case 014: /* HKEC1 */ + new_val = old_val = hkmr; + break; + + case 015: /* HKEC2 */ + new_val = old_val = hkmr; + break; + + case 016: /* HKMR2 */ + new_val = old_val = hkmr2; + break; + + case 017: /* HKMR3 */ + new_val = old_val = hkmr3; break; } /* end switch */ +sim_debug_bits (HKDEB_RWR, &hk_dev, hk_reg_bits[j], old_val, new_val, 1); update_hkcs (0, drv); /* update status */ return SCPE_OK; @@ -691,9 +923,8 @@ static uint8 fnc_cyl[16] = { }; fnc = GET_FNC (hkcs1); -if (DEBUG_PRI (hk_dev, HKDEB_OPS)) - fprintf (sim_deb, ">>HK%d strt: fnc=%o, cs1=%o, cs2=%o, ds=%o, er=%o, cyl=%o, da=%o, ba=%o, wc=%o\n", - drv, fnc, hkcs1, hkcs2, hkds[drv], hker[drv], hkdc, hkda, hkba, hkwc); +sim_debug (HKDEB_OPS, &hk_dev, ">>HK%d strt: fnc=%s, cs1=%o, cs2=%o, ds=%o, er=%o, cyl=%o, da=%o, ba=%o, wc=%o\n", + drv, hk_funcs[fnc], hkcs1, hkcs2, hkds[drv], hker[drv], hkdc, hkda, hkba, hkwc); uptr = hk_dev.units + drv; /* get unit */ if (fnc != FNC_NOP) /* !nop, clr msg sel */ hkmr = hkmr & ~MR_MS; @@ -730,7 +961,7 @@ switch (fnc) { /* case on function */ /* Instantaneous functions (unit may be busy, can't schedule thread) */ - case FNC_NOP: /* no operation */ + case FNC_NOP: /* no operation/select drive */ hkmr2 = hk_rdmr2 (GET_MS (hkmr)); /* get serial msgs */ hkmr3 = hk_rdmr3 (GET_MS (hkmr)); update_hkcs (CS1_DONE, drv); /* done */ @@ -804,6 +1035,7 @@ uint16 comp; drv = (uint32) (uptr - hk_dev.units); /* get drv number */ fnc = uptr->FNC & CS1_M_FNC; /* get function */ +sim_debug (HKDEB_TRC, &hk_dev, "hk_svc(HK%d, fnc=%s)\n", drv, hk_funcs[fnc]); switch (fnc) { /* case on function */ /* Fast commands - start spindle only provides one interrupt @@ -985,27 +1217,38 @@ return SCPE_OK; void update_hkcs (int32 flag, int32 drv) { -int32 i; +int32 i, old_hkcs1 = hkcs1, old_hkcs2 = hkcs2; +sim_debug (HKDEB_TRC, &hk_dev, "update_hkcs(flag=0%o, drv=%d)\n", flag, drv); update_hkds (drv); /* upd drv status */ -if (flag & CS1_DONE) /* clear go */ - hkcs1 = hkcs1 & ~CS1_GO; -if (hkcs1 & CS1_IE) { /* intr enable? */ - if (((flag & CS1_DONE) && ((hkcs1 & CS1_DONE) == 0)) || - ((flag & CS1_DI) && (hkcs1 & CS1_DONE))) /* done 0->1 or DI? */ - SET_INT (HK); - } -else CLR_INT (HK); hkcs1 = (hkcs1 & (CS1_DT|CS1_UAE|CS1_DONE|CS1_IE|CS1_SPA|CS1_FNC|CS1_GO)) | flag; +if (hkcs1 & CS1_DONE) /* done? clear GO */ + hkcs1 = hkcs1 & ~CS1_GO; for (i = 0; i < HK_NUMDR; i++) { /* if ATA, set DI */ - if (hkds[i] & DS_ATA) hkcs1 = hkcs1 | CS1_DI; + if (hkds[i] & DS_ATA) + hkcs1 = hkcs1 | CS1_DI; + } +if (hker[drv] || (hkcs1 & (CS1_PAR | CS1_CTO)) || (hkcs2 & CS2_ERR)) + hkcs1 = hkcs1 | CS1_ERR; /* if err, set ERR */ +if (hkcs1 & CS1_IE) { /* intr enable? */ + if (((hkcs1 & CS1_DONE) && ((old_hkcs1 & CS1_DONE) == 0)) || + ((hkcs1 & CS1_DI) && (hkcs1 & CS1_DONE))) { /* done 0->1 or DI&done? */ + sim_debug (HKDEB_INT, &hk_dev, "update_hkcs(SET_INT)\n"); + SET_INT (HK); + } + } +else { + sim_debug (HKDEB_INT, &hk_dev, "update_hkcs(CLR_INT)\n"); + CLR_INT (HK); + } +if (old_hkcs1 != hkcs1) + sim_debug_bits (HKDEB_OPS, &hk_dev, hk_cs1_bits, old_hkcs1, hkcs1, 1); +if (old_hkcs2 != hkcs2) + sim_debug_bits (HKDEB_OPS, &hk_dev, hk_cs2_bits, old_hkcs2, hkcs2, 1); +if (flag & CS1_DONE) { /* set done */ + sim_debug (HKDEB_OPS, &hk_dev, ">>HK%d done: fnc=%s, cs1=%o, cs2=%o, ds=%o, er=%o, cyl=%o, da=%o, ba=%o, wc=%o\n", + drv, hk_funcs[GET_FNC (hkcs1)], hkcs1, hkcs2, hkds[drv], hker[drv], hkdc, hkda, hkba, hkwc); } -if (hker[drv] | (hkcs1 & (CS1_PAR | CS1_CTO)) | /* if err, set ERR */ - (hkcs2 & CS2_ERR)) hkcs1 = hkcs1 | CS1_ERR; -if ((flag & CS1_DONE) && /* set done && debug? */ - (DEBUG_PRI (hk_dev, HKDEB_OPS))) - fprintf (sim_deb, ">>HK%d done: fnc=%o, cs1=%o, cs2=%o, ds=%o, er=%o, cyl=%o, da=%o, ba=%o, wc=%o\n", - drv, GET_FNC (hkcs1), hkcs1, hkcs2, hkds[drv], hker[drv], hkdc, hkda, hkba, hkwc); return; } @@ -1013,10 +1256,13 @@ return; void update_hkds (int32 drv) { +int old_ds = hkds[drv]; + if (hk_unit[drv].flags & UNIT_DIS) { /* disabled? */ hkds[drv] = hker[drv] = 0; /* all clear */ return; } +sim_debug (HKDEB_TRC, &hk_dev, "update_hkds(drv=%d)\n", drv); hkds[drv] = (hkds[drv] & (DS_VV | DS_PIP | DS_ATA)) | DS_VLD | DS_DRA; if (hk_unit[drv].flags & UNIT_ATT) { /* attached? */ if (!sim_is_active (&hk_unit[drv])) /* not busy? */ @@ -1034,6 +1280,8 @@ else { } if (hk_unit[drv].flags & UNIT_RK07) hkds[drv] = hkds[drv] | DS_DT; +if (old_ds != hkds[drv]) + sim_debug_bits (HKDEB_TRC, &hk_dev, hk_ds_bits, old_ds, hkds[drv], 1); return; } @@ -1041,6 +1289,7 @@ return; void hk_cmderr (int32 err, int32 drv) { +sim_debug (HKDEB_TRC, &hk_dev, "update_hkds(drv=%d, err=%d)\n", drv, err); hker[drv] = hker[drv] | err; /* set error */ hkds[drv] = hkds[drv] | DS_ATA; /* set attn */ update_hkcs (CS1_DONE, drv); /* set done */ @@ -1158,6 +1407,7 @@ t_stat hk_reset (DEVICE *dptr) int32 i; UNIT *uptr; +sim_debug (HKDEB_TRC, &hk_dev, "hk_reset()\n"); hkcs1 = CS1_DONE; /* set done */ hkcs2 = CS2_IR; /* clear state */ hkmr = hkmr2 = hkmr3 = 0; @@ -1303,7 +1553,7 @@ static const uint16 boot_rom[] = { t_stat hk_boot (int32 unitno, DEVICE *dptr) { -int32 i; +size_t i; extern int32 saved_PC; for (i = 0; i < BOOT_LEN; i++) diff --git a/PDP11/pdp11_io.c b/PDP11/pdp11_io.c index 66aca571..2a197622 100644 --- a/PDP11/pdp11_io.c +++ b/PDP11/pdp11_io.c @@ -23,6 +23,7 @@ used in advertising or otherwise to promote the sale, use or other dealings in this Software without prior written authorization from Robert M Supnik. + 27-Mar-12 RMS Fixed order of int_internal (Jordi Guillaumes i Pons) 19-Mar-12 RMS Fixed declaration of cpu_opt (Mark Pizzolato) 12-Dec-11 RMS Fixed Qbus interrupts to treat all IO devices as BR4 19-Nov-08 RMS Moved I/O support routines to I/O library @@ -59,8 +60,7 @@ extern int32 trap_req, ipl; extern int32 cpu_log; extern int32 autcon_enb; extern int32 uba_last; -extern FILE *sim_log; -extern DEVICE *sim_devices[], cpu_dev; +extern DEVICE cpu_dev; extern t_addr cpu_memsize; int32 calc_ints (int32 nipl, int32 trq); @@ -83,8 +83,8 @@ static const int32 pirq_bit[7] = { }; static const int32 int_internal[IPL_HLVL] = { - INT_INTERNAL7, INT_INTERNAL6, INT_INTERNAL5, INT_INTERNAL4, - INT_INTERNAL3, INT_INTERNAL2, INT_INTERNAL1, 0 + 0, INT_INTERNAL1, INT_INTERNAL2, INT_INTERNAL3, + INT_INTERNAL4, INT_INTERNAL5, INT_INTERNAL6, INT_INTERNAL7 }; /* I/O page lookup and linkage routines diff --git a/PDP11/pdp11_io_lib.c b/PDP11/pdp11_io_lib.c index 167d5d10..59af9a78 100644 --- a/PDP11/pdp11_io_lib.c +++ b/PDP11/pdp11_io_lib.c @@ -36,8 +36,6 @@ #include "sim_sock.h" #include "sim_tmxr.h" -extern FILE *sim_log; -extern DEVICE *sim_devices[]; extern int32 autcon_enb; extern int32 int_vec[IPL_HLVL][32]; extern int32 (*int_ack[IPL_HLVL][32])(void); @@ -48,6 +46,11 @@ extern t_stat build_dib_tab (void); static DIB *iodibp[IOPAGESIZE >> 1]; +#define AUTO_MAXC 32 /* Maximum number of controllers */ +#define AUTO_CSRBASE 0010 +#define AUTO_CSRMAX 04000 +#define AUTO_VECBASE 0300 + /* Enable/disable autoconfiguration */ t_stat set_autocon (UNIT *uptr, int32 val, char *cptr, void *desc) @@ -93,7 +96,6 @@ if ((newba <= IOPAGEBASE) || /* > IO page base? */ (newba % ((uint32) val))) /* check modulus */ return SCPE_ARG; dibp->ba = newba; /* store */ -dptr->flags = dptr->flags & ~DEV_FLTA; /* not floating */ autcon_enb = 0; /* autoconfig off */ return SCPE_OK; } @@ -119,7 +121,7 @@ if (dibp->lnt > 1) { fprintf (st, "-"); fprint_val (st, (t_value) dibp->ba + dibp->lnt - 1, DEV_RDX, 32, PV_LEFT); } -if (dptr->flags & DEV_FLTA) +if (dibp->ba < IOPAGEBASE + AUTO_CSRBASE + AUTO_CSRMAX) fprintf (st, "*"); return SCPE_OK; } @@ -137,7 +139,6 @@ if (uptr == NULL) dptr = find_dev_from_unit (uptr); if (dptr == NULL) return SCPE_IERR; -dptr->flags = dptr->flags | DEV_FLTA; /* floating */ return auto_config (NULL, 0); /* autoconfigure */ } @@ -166,7 +167,6 @@ if ((r != SCPE_OK) || (newvec == VEC_Q) || (newvec & ((dibp->vnum > 1)? 07: 03))) return SCPE_ARG; dibp->vec = newvec; -dptr->flags = dptr->flags & ~DEV_FLTA; /* not floating */ autcon_enb = 0; /* autoconfig off */ return SCPE_OK; } @@ -201,6 +201,8 @@ else { fprint_val (st, (t_value) vec + (4 * (numvec - 1)), DEV_RDX, 16, PV_LEFT); } } +if (vec >= VEC_Q + AUTO_VECBASE) + fprintf (st, "*"); return SCPE_OK; } @@ -312,7 +314,7 @@ for (i = 0, dibp = NULL; i < (IOPAGESIZE >> 1); i++) { /* loop thru entries */ fprintf (st, " - "); fprint_val (st, (t_value) dibp->ba + dibp->lnt - 1, DEV_RDX, 32, PV_LEFT); fprintf (st, "%c\t%s\n", /* print block entry */ - (dptr && (dptr->flags & DEV_FLTA))? '*': ' ', + (dibp->ba < IOPAGEBASE + AUTO_CSRBASE + AUTO_CSRMAX)? '*': ' ', dptr? sim_dname (dptr): "CPU"); } /* end if */ } /* end for i */ @@ -321,16 +323,19 @@ return SCPE_OK; /* Autoconfiguration - The table reflects the MicroVAX 3900 microcode, with one addition - the + The table reflects the MicroVAX 3900 microcode, with one field addition - the number of controllers field handles devices where multiple instances - are simulated through a single DEVICE structure (e.g., DZ, VH). + are simulated through a single DEVICE structure (e.g., DZ, VH, DL, DC). + + The table has been reviewed, extended and updated to reflect the contents of + the auto configure table in VMS sysgen (V5.5-2) A minus number of vectors indicates a field that should be calculated - but not placed in the DIB (RQ, TQ dynamic vectors) */ + but not placed in the DIB (RQ, TQ dynamic vectors) + + An amod value of 0 indicates that all addresses are FIXED + An vmod value of 0 indicates that all vectors are FIXED */ -#define AUTO_MAXC 4 -#define AUTO_CSRBASE 0010 -#define AUTO_VECBASE 0300 typedef struct { char *dnam[AUTO_MAXC]; @@ -342,67 +347,214 @@ typedef struct { uint32 fixv[AUTO_MAXC]; } AUTO_CON; -AUTO_CON auto_tab[] = { - { { "DCI" }, DCX_LINES, 2, 0, 8, { 0 } }, /* DC11 - fx CSRs */ - { { "DLI" }, DLX_LINES, 2, 0, 8, { 0 } }, /* KL11/DL11/DLV11 - fx CSRs */ - { { NULL }, 1, 2, 0, 8, { 0 } }, /* DLV11J - fx CSRs */ - { { NULL }, 1, 2, 8, 8 }, /* DJ11 */ - { { NULL }, 1, 2, 16, 8 }, /* DH11 */ - { { NULL }, 1, 2, 8, 8 }, /* DQ11 */ - { { NULL }, 1, 2, 8, 8 }, /* DU11 */ - { { NULL }, 1, 2, 8, 8 }, /* DUP11 */ - { { NULL }, 10, 2, 8, 8 }, /* LK11A */ - { { NULL }, 1, 2, 8, 8 }, /* DMC11 */ - { { "DZ" }, DZ_MUXES, 2, 8, 8 }, /* DZ11 */ - { { NULL }, 1, 2, 8, 8 }, /* KMC11 */ - { { NULL }, 1, 2, 8, 8 }, /* LPP11 */ - { { NULL }, 1, 2, 8, 8 }, /* VMV21 */ - { { NULL }, 1, 2, 16, 8 }, /* VMV31 */ - { { NULL }, 1, 2, 8, 8 }, /* DWR70 */ - { { "RL", "RLB" }, 1, 1, 8, 4, {IOBA_RL}, {VEC_RL} }, /* RL11 */ - { { "TS", "TSB", "TSC", "TSD" }, 1, 1, 0, 4, /* TS11 */ - {IOBA_TS, IOBA_TS + 4, IOBA_TS + 8, IOBA_TS + 12}, - {VEC_TS} }, - { { NULL }, 1, 2, 16, 8 }, /* LPA11K */ - { { NULL }, 1, 2, 8, 8 }, /* KW11C */ - { { NULL }, 1, 1, 8, 8 }, /* reserved */ - { { "RX", "RY" }, 1, 1, 8, 4, {IOBA_RX} , {VEC_RX} }, /* RX11/RX211 */ - { { NULL }, 1, 1, 8, 4 }, /* DR11W */ - { { NULL }, 1, 1, 8, 4, { 0, 0 }, { 0 } }, /* DR11B - fx CSRs,vec */ - { { NULL }, 1, 2, 8, 8 }, /* DMP11 */ - { { NULL }, 1, 2, 8, 8 }, /* DPV11 */ - { { NULL }, 1, 2, 8, 8 }, /* ISB11 */ - { { NULL }, 1, 2, 16, 8 }, /* DMV11 */ - { { "XU", "XUB" }, 1, 1, 8, 4, {IOBA_XU}, {VEC_XU} }, /* DEUNA */ - { { "XQ", "XQB" }, 1, 1, 0, 4, /* DEQNA */ - {IOBA_XQ,IOBA_XQB}, {VEC_XQ} }, - { { "RQ", "RQB", "RQC", "RQD" }, 1, -1, 4, 4, /* RQDX3 */ - {IOBA_RQ}, {VEC_RQ} }, - { { NULL }, 1, 8, 32, 4 }, /* DMF32 */ - { { NULL }, 1, 2, 16, 8 }, /* KMS11 */ - { { NULL }, 1, 1, 16, 4 }, /* VS100 */ - { { "TQ", "TQB" }, 1, -1, 4, 4, {IOBA_TQ}, {VEC_TQ} }, /* TQK50 */ - { { NULL }, 1, 2, 16, 8 }, /* KMV11 */ - { { "VH" }, VH_MUXES, 2, 16, 8 }, /* DHU11/DHQ11 */ - { { NULL }, 1, 6, 32, 4 }, /* DMZ32 */ - { { NULL }, 1, 6, 32, 4 }, /* CP132 */ - { { NULL }, 1, 2, 64, 8, { 0 } }, /* QVSS - fx CSR */ - { { NULL }, 1, 1, 8, 4 }, /* VS31 */ - { { NULL }, 1, 1, 0, 4, { 0 } }, /* LNV11 - fx CSR */ - { { NULL }, 1, 1, 16, 4 }, /* LNV21/QPSS */ - { { NULL }, 1, 1, 8, 4, { 0 } }, /* QTA - fx CSR */ - { { NULL }, 1, 1, 8, 4 }, /* DSV11 */ - { { NULL }, 1, 2, 8, 8 }, /* CSAM */ - { { NULL }, 1, 2, 8, 8 }, /* ADV11C */ - { { NULL }, 1, 0, 8, 0 }, /* AAV11C */ - { { NULL }, 1, 2, 8, 8, { 0 }, { 0 } }, /* AXV11C - fx CSR,vec */ - { { NULL }, 1, 2, 4, 8, { 0 } }, /* KWV11C - fx CSR */ - { { NULL }, 1, 2, 8, 8, { 0 } }, /* ADV11D - fx CSR */ - { { NULL }, 1, 2, 8, 8, { 0 } }, /* AAV11D - fx CSR */ - { { "QDSS" }, 1, 3, 0, 16, {IOBA_QDSS} }, /* QDSS - fx CSR */ +AUTO_CON auto_tab[] = {/*c #v am vm fxa fxv */ + { { "QBA" }, 1, 0, 0, 0, + {017500} }, /* doorbell - fx CSR, no VEC */ + { { "MCTL" }, 1, 0, 0, 0, + {012100} }, /* MSV11-P - fx CSR, no VEC */ + { { "KE" }, 1, 0, 0, 0, + {017300} }, /* KE11-A - fx CSR, no VEC */ + { { "KG" }, 1, 0, 0, 0, + {010700} }, /* KG11-A - fx CSR, no VEC */ + { { "RHA", "RHB" }, 1, 1, 0, 0, + {016700, 012440}, {0254, 0224} }, /* RH11/RH70 - fx CSR, fx VEC */ + { { "CLK" }, 1, 1, 0, 0, + {017546}, {0100} }, /* KW11L - fx CSR, fx VEC */ + { { "PCLK" }, 1, 1, 0, 0, + {012540}, {0104} }, /* KW11P - fx CSR, fx VEC */ + { { "PTR" }, 1, 1, 0, 0, + {017550}, {0070} }, /* PC11 reader - fx CSR, fx VEC */ + { { "PTP" }, 1, 1, 0, 0, + {017554}, {0074} }, /* PC11 punch - fx CSR, fx VEC */ + { { "RK" }, 1, 1, 0, 0, + {017400}, {0220} }, /* RK11 - fx CSR, fx VEC */ + { { "TM" }, 1, 1, 0, 0, + {012520}, {0224} }, /* TM11 - fx CSR, fx VEC */ + { { "RC" }, 1, 1, 0, 0, + {017440}, {0210} }, /* RC11 - fx CSR, fx VEC */ + { { "RF" }, 1, 1, 0, 0, + {017460}, {0204} }, /* RF11 - fx CSR, fx VEC */ + { { "CR" }, 1, 1, 0, 0, + {017160}, {0230} }, /* CR11 - fx CSR, fx VEC */ + { { "HK" }, 1, 1, 0, 0, + {017440}, {0210} }, /* RK611 - fx CSR, fx VEC */ + { { "LPT" }, 1, 1, 0, 0, + {017514, 004004, 004014, 004024, 004034}, + {0200, 0170, 0174, 0270, 0274} }, /* LP11 - fx CSR, fx VEC */ + { { "RB" }, 1, 1, 0, 0, + {015606}, {0250} }, /* RB730 - fx CSR, fx VEC */ + { { "RL" }, 1, 1, 0, 0, + {014400}, {0160} }, /* RL11 - fx CSR, fx VEC */ + { { "RL" }, 1, 1, 0, 0, + {014400}, {0160} }, /* RL11 - fx CSR, fx VEC */ + { { "DCI" }, 1, 2, 0, 8, + {014000, 014010, 014020, 014030, + 014040, 014050, 014060, 014070, + 014100, 014110, 014120, 014130, + 014140, 014150, 014160, 014170, + 014200, 014210, 014220, 014230, + 014240, 014250, 014260, 014270, + 014300, 014310, 014320, 014330, + 014340, 014350, 014360, 014370} }, /* DC11 - fx CSRs */ + { { NULL }, 1, 2, 0, 8, + {016500, 016510, 016520, 016530, + 016540, 016550, 016560, 016570, + 016600, 016610, 016620, 016630, + 016640, 016650, 016660, 016670} }, /* TU58 - fx CSRs */ + { { NULL }, 1, 1, 0, 4, + {015200, 015210, 015220, 015230, + 015240, 015250, 015260, 015270, + 015300, 015310, 015320, 015330, + 015340, 015350, 015360, 015370} }, /* DN11 - fx CSRs */ + { { NULL }, 1, 1, 0, 4, + {010500, 010510, 010520, 010530, + 010540, 010550, 010560, 010570, + 010600, 010610, 010620, 010630, + 010640, 010650, 010660, 010670} }, /* DM11B - fx CSRs */ + { { NULL }, 1, 2, 0, 8, + {007600, 007570, 007560, 007550, + 007540, 007530, 007520, 007510, + 007500, 007470, 007460, 007450, + 007440, 007430, 007420, 007410} }, /* DR11C - fx CSRs */ + { { NULL }, 1, 1, 0, 8, + {012600, 012604, 012610, 012614, + 012620, 012624, 012620, 012624} }, /* PR611 - fx CSRs */ + { { NULL }, 1, 1, 0, 8, + {017420, 017422, 017424, 017426, + 017430, 017432, 017434, 017436} }, /* DT11 - fx CSRs */ + { { NULL }, 1, 2, 0, 8, + {016200, 016240} }, /* DX11 */ + { { "DLI" }, 1, 2, 0, 8, + {016500, 016510, 016520, 016530, + 016540, 016550, 016560, 016570, + 016600, 016610, 016620, 016630, + 016740, 016750, 016760, 016770} }, /* KL11/DL11/DLV11 - fx CSRs */ + { { NULL }, 1, 2, 0, 8, { 0 } }, /* DLV11J - fx CSRs */ + { { NULL }, 1, 2, 8, 8 }, /* DJ11 */ + { { NULL }, 1, 2, 16, 8 }, /* DH11 */ + { { NULL }, 1, 4, 0, 8, + {012000, 012010, 012020, 012030} }, /* GT40 */ + { { NULL }, 1, 2, 0, 8, + {010400} }, /* LPS11 */ + { { NULL }, 1, 2, 8, 8 }, /* DQ11 */ + { { NULL }, 1, 2, 0, 8, + {012400} }, /* KW11W */ + { { NULL }, 1, 2, 8, 8 }, /* DU11 */ + { { NULL }, 1, 2, 8, 8 }, /* DUP11 */ + { { NULL }, 1, 3, 0, 8, + {015000, 015040, 015100, 015140, }}, /* DV11 */ + { { NULL }, 1, 2, 8, 8 }, /* LK11A */ + { { "DMC0", "DMC1", "DMC2", "DMC3" }, + 1, 2, 8, 8 }, /* DMC11 */ + { { "DZ" }, 1, 2, 8, 8 }, /* DZ11 */ + { { NULL }, 1, 2, 8, 8 }, /* KMC11 */ + { { NULL }, 1, 2, 8, 8 }, /* LPP11 */ + { { NULL }, 1, 2, 8, 8 }, /* VMV21 */ + { { NULL }, 1, 2, 16, 8 }, /* VMV31 */ + { { NULL }, 1, 2, 8, 8 }, /* DWR70 */ + { { "RL", "RLB"}, 1, 1, 8, 4, + {014400}, {0160} }, /* RL11 */ + { { "TS", "TSB", "TSC", "TSD"}, + 1, 1, 0, 4, /* TS11 */ + {012520, 012524, 012530, 012534}, + {0224} }, + { { NULL }, 1, 2, 16, 8, + {010460} }, /* LPA11K */ + { { NULL }, 1, 2, 8, 8 }, /* KW11C */ + { { NULL }, 1, 1, 8, 8 }, /* reserved */ + { { "RX", "RY" }, 1, 1, 8, 4, + {017170} , {0264} }, /* RX11/RX211 */ + { { NULL }, 1, 1, 8, 4 }, /* DR11W */ + { { NULL }, 1, 1, 8, 4, + {012410, 012410}, {0124} }, /* DR11B - fx CSRs,vec */ + { { "DMP" }, 1, 2, 8, 8 }, /* DMP11 */ + { { NULL }, 1, 2, 8, 8 }, /* DPV11 */ + { { NULL }, 1, 2, 8, 8 }, /* ISB11 */ + { { NULL }, 1, 2, 16, 8 }, /* DMV11 */ + { { "XU", "XUB" }, 1, 1, 8, 4, + {014510}, {0120} }, /* DEUNA */ + { { "XQ", "XQB" }, 1, -1, 0, 4, + {014440, 014460, 014520, 014540}, {0120} }, /* DEQNA */ + { { "RQ", "RQB", "RQC", "RQD" }, + 1, -1, 4, 4, /* RQDX3 */ + {012150}, {0154} }, + { { NULL }, 1, 8, 32, 4 }, /* DMF32 */ + { { NULL }, 1, 3, 16, 8 }, /* KMS11 */ + { { NULL }, 1, 2, 0, 8, + {004200, 004240, 004300, 004340} }, /* PLC11 */ + { { NULL }, 1, 1, 16, 4 }, /* VS100 */ + { { "TQ", "TQB" }, 1, -1, 4, 4, + {014500}, {0260} }, /* TQK50 */ + { { NULL }, 1, 2, 16, 8 }, /* KMV11 */ + { { NULL }, 1, 2, 0, 8, + {004400, 004440, 004500, 004540} }, /* KTC32 */ + { { NULL }, 1, 2, 0, 8, + {004100} }, /* IEQ11 */ + { { "VH" }, 1, 2, 16, 8 }, /* DHU11/DHQ11 */ + { { NULL }, 1, 6, 32, 4 }, /* DMZ32 */ + { { NULL }, 1, 6, 32, 4 }, /* CP132 */ + { { "TC" }, 1, 1, 0, 0, + {017340}, {0214} }, /* TC11 */ + { { "TA" }, 1, 1, 0, 0, + {017500}, {0260} }, /* TA11 */ + { { NULL }, 1, 2, 64, 8, + {017200} }, /* QVSS - fx CSR */ + { { NULL }, 1, 1, 8, 4 }, /* VS31 */ + { { NULL }, 1, 1, 0, 4, + {016200} }, /* LNV11 - fx CSR */ + { { NULL }, 1, 1, 16, 4 }, /* LNV21/QPSS */ + { { NULL }, 1, 1, 8, 4, + {012570} }, /* QTA - fx CSR */ + { { NULL }, 1, 1, 8, 4 }, /* DSV11 */ + { { NULL }, 1, 2, 8, 8 }, /* CSAM */ + { { NULL }, 1, 2, 8, 8 }, /* ADV11C */ + { { NULL }, 1, 0, 8, 8, + {010440} }, /* AAV11/AAV11C */ + { { NULL }, 1, 2, 8, 8, + {016400}, {0140} }, /* AXV11C - fx CSR,vec */ + { { NULL }, 1, 2, 4, 8, + {010420} }, /* KWV11C - fx CSR */ + { { NULL }, 1, 2, 8, 8, + {016410} }, /* ADV11D - fx CSR */ + { { NULL }, 1, 2, 8, 8, + {016420} }, /* AAV11D - fx CSR */ + { { "QDSS" }, 1, 3, 0, 16, + {017400, 017402, 017404, 017406, + 017410, 017412, 017414, 017416} }, /* VCB02 - QDSS - fx CSR */ + { { NULL }, 1, 16, 0, 4, + {004160, 004140, 004120} }, /* DRV11J - fx CSR */ + { { NULL }, 1, 2, 16, 8 }, /* DRQ3B */ + { { NULL }, 1, 1, 8, 4 }, /* VSV24 */ + { { NULL }, 1, 1, 8, 4 }, /* VSV21 */ + { { NULL }, 1, 1, 8, 4 }, /* IBQ01 */ + { { NULL }, 1, 1, 8, 8 }, /* IDV11A */ + { { NULL }, 1, 0, 8, 8 }, /* IDV11B */ + { { NULL }, 1, 0, 8, 8 }, /* IDV11C */ + { { NULL }, 1, 1, 8, 8 }, /* IDV11D */ + { { NULL }, 1, 2, 8, 8 }, /* IAV11A */ + { { NULL }, 1, 0, 8, 8 }, /* IAV11B */ + { { NULL }, 1, 2, 8, 8 }, /* MIRA */ + { { NULL }, 1, 2, 16, 8 }, /* IEQ11 */ + { { NULL }, 1, 2, 32, 8 }, /* ADQ32 */ + { { NULL }, 1, 2, 8, 8 }, /* DTC04, DECvoice */ + { { NULL }, 1, 1, 32, 4 }, /* DESNA */ + { { NULL }, 1, 2, 4, 8 }, /* IGQ11 */ + { { NULL }, 1, 2, 32, 8 }, /* KMV1F */ + { { NULL }, 1, 1, 8, 4 }, /* DIV32 */ + { { NULL }, 1, 2, 4, 8 }, /* DTCN5, DECvoice */ + { { NULL }, 1, 2, 4, 8 }, /* DTC05, DECvoice */ + { { NULL }, 1, 2, 8, 8 }, /* KWV32 (DSV11) */ + { { NULL }, 1, 1, 64, 4 }, /* QZA */ { { NULL }, -1 } /* end table */ }; +#if !defined(DEV_NEXUS) +#if defined(DEV_MBUS) +#define DEV_NEXUS DEV_MBUS +#else +#define DEV_NEXUS 0 +#endif +#endif t_stat auto_config (char *name, int32 nctrl) { uint32 csr = IOPAGEBASE + AUTO_CSRBASE; @@ -410,7 +562,7 @@ uint32 vec = VEC_Q + AUTO_VECBASE; AUTO_CON *autp; DEVICE *dptr; DIB *dibp; -uint32 j, k, vmask, amask; +uint32 j, vmask, amask; if (autcon_enb == 0) /* enabled? */ return SCPE_OK; @@ -429,40 +581,38 @@ for (autp = auto_tab; autp->numc >= 0; autp++) { /* loop thru table */ amask = autp->amod - 1; csr = (csr + amask) & ~amask; /* align csr */ } - for (j = k = 0; (j < AUTO_MAXC) && autp->dnam[j]; j++) { + for (j = 0; (j < AUTO_MAXC) && autp->dnam[j]; j++) { if (autp->dnam[j] == NULL) /* no device? */ - continue; + break; dptr = find_dev (autp->dnam[j]); /* find ctrl */ - if ((dptr == NULL) || /* enabled, floating? */ + if ((dptr == NULL) || /* enabled, not (nexus or unibus or qbus)? */ (dptr->flags & DEV_DIS) || - !(dptr->flags & DEV_FLTA)) + (dptr->flags & DEV_NEXUS) || + !(dptr->flags & (DEV_UBUS | DEV_QBUS | DEV_Q18)) ) continue; dibp = (DIB *) dptr->ctxt; /* get DIB */ if (dibp == NULL) /* not there??? */ return SCPE_IERR; - if (autp->amod) { /* dyn csr needed? */ - if (autp->fixa[k]) /* fixed csr avail? */ - dibp->ba = autp->fixa[k]; /* use it */ - else { /* no fixed left */ - dibp->ba = csr; /* set CSR */ - csr += (autp->numc * autp->amod); /* next CSR */ - } /* end else */ - } /* end if dyn csr */ - if (autp->numv && autp->vmod) { /* dyn vec needed? */ - uint32 numv = abs (autp->numv); /* get num vec */ - if (autp->fixv[k]) { /* fixed vec avail? */ + if (autp->fixa[j]) /* fixed csr avail? */ + dibp->ba = IOPAGEBASE + autp->fixa[j]; /* use it */ + else { /* no fixed left */ + dibp->ba = csr; /* set CSR */ + csr += (autp->numc * autp->amod); /* next CSR */ + } /* end else */ + if (autp->numv) { /* vec needed? */ + if (autp->fixv[j]) { /* fixed vec avail? */ if (autp->numv > 0) - dibp->vec = autp->fixv[k]; /* use it */ + dibp->vec = VEC_Q + autp->fixv[j]; /* use it */ } else { /* no fixed left */ + uint32 numv = abs (autp->numv); /* get num vec */ vmask = autp->vmod - 1; vec = (vec + vmask) & ~vmask; /* align vector */ if (autp->numv > 0) dibp->vec = vec; /* set vector */ vec += (autp->numc * numv * 4); } /* end else */ - } /* end if dyn vec */ - k++; /* next instance */ + } /* end vec needed */ } /* end for j */ if (autp->amod) /* flt CSR? gap */ csr = csr + 2; diff --git a/PDP11/pdp11_ke.c b/PDP11/pdp11_ke.c index c82ddeef..d2c91058 100644 --- a/PDP11/pdp11_ke.c +++ b/PDP11/pdp11_ke.c @@ -71,7 +71,9 @@ t_stat ke_wr (int32 data, int32 PA, int32 access); t_stat ke_reset (DEVICE *dptr); uint32 ke_set_SR (void); -DIB ke_dib = { IOBA_KE, IOLN_KE, &ke_rd, &ke_wr, 0 }; +#define IOLN_KE 020 + +DIB ke_dib = { IOBA_AUTO, IOLN_KE, &ke_rd, &ke_wr, 0 }; UNIT ke_unit = { UDATA (NULL, UNIT_DISABLE, 0) @@ -344,5 +346,5 @@ ke_SR = 0; ke_SC = 0; ke_AC = 0; ke_MQ = 0; -return SCPE_OK; +return auto_config(0, 0); } diff --git a/PDP11/pdp11_kg.c b/PDP11/pdp11_kg.c index 6597250f..121b766f 100644 --- a/PDP11/pdp11_kg.c +++ b/PDP11/pdp11_kg.c @@ -95,7 +95,6 @@ #endif #include "pdp11_defs.h" -extern FILE *sim_deb; extern REG cpu_reg[]; extern int32 R[]; @@ -195,8 +194,10 @@ static t_stat set_units (UNIT *, int32, char *, void *); kg_dev KG device descriptor */ +#define IOLN_KG 006 + static DIB kg_dib = { - IOBA_KG, + IOBA_AUTO, (IOLN_KG + 2) * KG_UNITS, &kg_rd, &kg_wr, @@ -406,7 +407,7 @@ static t_stat kg_reset (DEVICE *dptr) kg_unit[i].BCC = 0; kg_unit[i].PULSCNT = 0; } - return (SCPE_OK); + return auto_config(0, 0); } static void cycleOneBit (int unit) diff --git a/PDP11/pdp11_lp.c b/PDP11/pdp11_lp.c index c535daed..74d0ff98 100644 --- a/PDP11/pdp11_lp.c +++ b/PDP11/pdp11_lp.c @@ -71,9 +71,11 @@ t_stat lpt_detach (UNIT *uptr); lpt_reg LPT register list */ +#define IOLN_LPT 004 + DIB lpt_dib = { - IOBA_LPT, IOLN_LPT, &lpt_rd, &lpt_wr, - 1, IVCL (LPT), VEC_LPT, { NULL } + IOBA_AUTO, IOLN_LPT, &lpt_rd, &lpt_wr, + 1, IVCL (LPT), VEC_AUTO, { NULL } }; UNIT lpt_unit = { diff --git a/PDP11/pdp11_mscp.h b/PDP11/pdp11_mscp.h index b000df7d..f655474a 100644 --- a/PDP11/pdp11_mscp.h +++ b/PDP11/pdp11_mscp.h @@ -24,6 +24,7 @@ used in advertising or otherwise to promote the sale, use or other dealings in this Software without prior written authorization from Robert M Supnik. + 24-Oct-12 MB Added working map base address 09-Jan-03 RMS Tape read/write end pkt is longer than disk read/write 20-Sep-02 RMS Merged TMSCP definitions */ @@ -412,6 +413,8 @@ #define RW_WBAH 21 #define RW_WBLL 22 /* working lbn */ #define RW_WBLH 23 +#define RW_WMPL 24 /* working map */ +#define RW_WMPH 25 /* Tape specific status */ diff --git a/PDP11/pdp11_pclk.c b/PDP11/pdp11_pclk.c index f83f5e83..0984b1d3 100644 --- a/PDP11/pdp11_pclk.c +++ b/PDP11/pdp11_pclk.c @@ -151,9 +151,11 @@ void pclk_tick (void); pclk_reg PCLK register list */ +#define IOLN_PCLK 006 + DIB pclk_dib = { - IOBA_PCLK, IOLN_PCLK, &pclk_rd, &pclk_wr, - 1, IVCL (PCLK), VEC_PCLK, { NULL } + IOBA_AUTO, IOLN_PCLK, &pclk_rd, &pclk_wr, + 1, IVCL (PCLK), VEC_AUTO, { NULL } }; UNIT pclk_unit = { UDATA (&pclk_svc, UNIT_IDLE, 0) }; @@ -304,7 +306,7 @@ pclk_ctr = 0; CLR_INT (PCLK); /* clear int */ sim_cancel (&pclk_unit); /* cancel */ pclk_unit.wait = xtim[0]; /* reset delay */ -return SCPE_OK; +return auto_config (0, 0); } /* Set line frequency */ diff --git a/PDP11/pdp11_pt.c b/PDP11/pdp11_pt.c index 62a6d46d..ba4f480c 100644 --- a/PDP11/pdp11_pt.c +++ b/PDP11/pdp11_pt.c @@ -79,9 +79,11 @@ t_stat ptp_detach (UNIT *uptr); ptr_reg PTR register list */ +#define IOLN_PTR 004 + DIB ptr_dib = { - IOBA_PTR, IOLN_PTR, &ptr_rd, &ptr_wr, - 1, IVCL (PTR), VEC_PTR, { NULL } + IOBA_AUTO, IOLN_PTR, &ptr_rd, &ptr_wr, + 1, IVCL (PTR), VEC_AUTO, { NULL } }; UNIT ptr_unit = { @@ -127,9 +129,11 @@ DEVICE ptr_dev = { ptp_reg PTP register list */ +#define IOLN_PTP 004 + DIB ptp_dib = { - IOBA_PTP, IOLN_PTP, &ptp_rd, &ptp_wr, - 1, IVCL (PTP), VEC_PTP, { NULL } + IOBA_AUTO, IOLN_PTP, &ptp_rd, &ptp_wr, + 1, IVCL (PTP), VEC_AUTO, { NULL } }; UNIT ptp_unit = { @@ -249,7 +253,7 @@ if ((ptr_unit.flags & UNIT_ATT) == 0) ptr_csr = ptr_csr | CSR_ERR; CLR_INT (PTR); sim_cancel (&ptr_unit); -return SCPE_OK; +return auto_config (dptr->name, 1); } t_stat ptr_attach (UNIT *uptr, char *cptr) @@ -344,7 +348,7 @@ if ((ptp_unit.flags & UNIT_ATT) == 0) ptp_csr = ptp_csr | CSR_ERR; CLR_INT (PTP); sim_cancel (&ptp_unit); /* deactivate unit */ -return SCPE_OK; +return auto_config (dptr->name, 1); } t_stat ptp_attach (UNIT *uptr, char *cptr) diff --git a/PDP11/pdp11_rc.c b/PDP11/pdp11_rc.c index 1f32ec59..d85e7b3b 100644 --- a/PDP11/pdp11_rc.c +++ b/PDP11/pdp11_rc.c @@ -147,7 +147,6 @@ ((double) RC_NUMWD))) extern int32 int_req[IPL_HLVL]; -extern FILE *sim_deb; extern int32 R[]; static uint32 rc_la = 0; /* look-ahead */ @@ -180,12 +179,14 @@ static uint32 update_rccs (uint32, uint32); rc_reg RC register list */ +#define IOLN_RC 020 + static DIB rc_dib = { - IOBA_RC, + IOBA_AUTO, IOLN_RC, &rc_rd, &rc_wr, - 1, IVCL (RC), VEC_RC, { NULL } + 1, IVCL (RC), VEC_AUTO, { NULL } }; static UNIT rc_unit = { @@ -437,7 +438,7 @@ static uint32 sectorCRC (const uint16 *data) static t_stat rc_svc (UNIT *uptr) { - uint32 ma, da, t, u_old, u_new, last_da; + uint32 ma, da, t, u_old, u_new, last_da = 0; uint16 dat; uint16 *fbuf = uptr->filebuf; @@ -549,7 +550,7 @@ static t_stat rc_reset (DEVICE *dptr) rc_db = 0; CLR_INT (RC); sim_cancel (&rc_unit); - return (SCPE_OK); + return auto_config(0, 0); } /* Attach routine */ diff --git a/PDP11/pdp11_rf.c b/PDP11/pdp11_rf.c index 439fa7b2..c79d41a6 100644 --- a/PDP11/pdp11_rf.c +++ b/PDP11/pdp11_rf.c @@ -110,7 +110,6 @@ extern uint16 *M; extern int32 int_req[IPL_HLVL]; -extern FILE *sim_deb; uint32 rf_cs = 0; /* status register */ uint32 rf_cma = 0; @@ -142,9 +141,11 @@ uint32 update_rfcs (uint32 newcs, uint32 newdae); rf_reg RF register list */ +#define IOLN_RF 020 + DIB rf_dib = { - IOBA_RF, IOLN_RF, &rf_rd, &rf_wr, - 1, IVCL (RF), VEC_RF, NULL + IOBA_AUTO, IOLN_RF, &rf_rd, &rf_wr, + 1, IVCL (RF), VEC_AUTO, {NULL} }; @@ -428,7 +429,7 @@ rf_wc = 0; rf_maint = 0; CLR_INT (RF); sim_cancel (&rf_unit); -return SCPE_OK; +return auto_config (0, 0); } /* Bootstrap routine */ @@ -461,7 +462,7 @@ static const uint16 boot_rom[] = { t_stat rf_boot (int32 unitno, DEVICE *dptr) { -int32 i; +size_t i; extern int32 saved_PC; for (i = 0; i < BOOT_LEN; i++) diff --git a/PDP11/pdp11_rh.c b/PDP11/pdp11_rh.c index efc7c043..fc268f17 100644 --- a/PDP11/pdp11_rh.c +++ b/PDP11/pdp11_rh.c @@ -164,9 +164,6 @@ extern int32 cpu_bme; extern uint16 *M; extern int32 int_req[IPL_HLVL]; extern t_addr cpu_memsize; -extern FILE *sim_deb; -extern FILE *sim_log; -extern int32 sim_switches; t_stat mba_reset (DEVICE *dptr); t_stat mba_rd (int32 *val, int32 pa, int32 access); @@ -206,9 +203,11 @@ static int32 mba_mapofs[(MBA_OFSMASK + 1) >> 1] = { mbax_reg RHx register list */ +#define IOLN_RP 054 + DIB mba0_dib = { - IOBA_RP, IOLN_RP, &mba_rd, &mba_wr, - 1, IVCL (RP), VEC_RP, { &mba0_inta } + IOBA_AUTO, IOLN_RP, &mba_rd, &mba_wr, + 1, IVCL (RP), VEC_AUTO, { &mba0_inta } }; UNIT mba0_unit = { UDATA (NULL, 0, 0) }; @@ -239,9 +238,11 @@ MTAB mba0_mod[] = { { 0 } }; +#define IOLN_TU 040 + DIB mba1_dib = { - IOBA_TU, IOLN_TU, &mba_rd, &mba_wr, - 1, IVCL (TU), VEC_TU, { &mba1_inta } + IOBA_AUTO, IOLN_TU, &mba_rd, &mba_wr, + 1, IVCL (TU), VEC_AUTO, { &mba1_inta } }; UNIT mba1_unit = { UDATA (NULL, 0, 0) }; @@ -776,7 +777,7 @@ massbus[mb].iff = 0; mba_clr_int (mb); if (mbabort[mb]) mbabort[mb] (); -return SCPE_OK; +return auto_config (0, 0); } /* Enable/disable Massbus adapter */ diff --git a/PDP11/pdp11_rk.c b/PDP11/pdp11_rk.c index d870ca8f..af865465 100644 --- a/PDP11/pdp11_rk.c +++ b/PDP11/pdp11_rk.c @@ -212,9 +212,11 @@ t_stat rk_boot (int32 unitno, DEVICE *dptr); rk_mod RK modifier list */ +#define IOLN_RK 020 + DIB rk_dib = { - IOBA_RK, IOLN_RK, &rk_rd, &rk_wr, - 1, IVCL (RK), VEC_RK, { &rk_inta } + IOBA_AUTO, IOLN_RK, &rk_rd, &rk_wr, + 1, IVCL (RK), VEC_AUTO, { &rk_inta } }; UNIT rk_unit[] = { @@ -707,7 +709,7 @@ if (rkxb == NULL) rkxb = (uint16 *) calloc (RK_MAXFR, sizeof (uint16)); if (rkxb == NULL) return SCPE_MEM; -return SCPE_OK; +return auto_config (0, 0); } /* Device bootstrap */ @@ -746,7 +748,7 @@ static const uint16 boot_rom[] = { t_stat rk_boot (int32 unitno, DEVICE *dptr) { -int32 i; +size_t i; extern int32 saved_PC; for (i = 0; i < BOOT_LEN; i++) diff --git a/PDP11/pdp11_rl.c b/PDP11/pdp11_rl.c index 107b8077..2b920585 100644 --- a/PDP11/pdp11_rl.c +++ b/PDP11/pdp11_rl.c @@ -227,7 +227,6 @@ extern UNIT cpu_unit; #define RLBAE_IMP (0000077) /* implemented */ extern int32 int_req[IPL_HLVL]; -extern FILE *sim_deb; uint16 *rlxb = NULL; /* xfer buffer */ int32 rlcs = 0; /* control/status */ @@ -270,9 +269,11 @@ t_stat rl_show_ctrl (FILE *st, UNIT *uptr, int32 val, void *desc); rl_mod RL modifier list */ +#define IOLN_RL 012 + static DIB rl_dib = { - IOBA_RL, IOLN_RL, &rl_rd, &rl_wr, - 1, IVCL (RL), VEC_RL, { NULL } }; + IOBA_AUTO, IOLN_RL, &rl_rd, &rl_wr, + 1, IVCL (RL), VEC_AUTO, { NULL } }; static UNIT rl_unit[] = { { UDATA (&rl_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+ @@ -1093,7 +1094,7 @@ t_stat rl_show_dstate (FILE *st, UNIT *uptr, int32 val, void *desc) (uptr->STAT & RLDS_WGE) ? '1' : '0', (uptr->STAT & RLDS_SPE) ? '1' : '0'); if (uptr->flags & UNIT_ATT) { - if ((cnt = sim_is_active (uptr)) != 0) + if ((cnt = sim_activate_time (uptr)) != 0) fprintf (st, "FNC: %d, %d\n", uptr->FNC, cnt); else fputs ("FNC: none\n", st); @@ -1187,7 +1188,7 @@ static const uint16 boot_rom[] = { t_stat rl_boot (int32 unitno, DEVICE *dptr) { -int32 i; +size_t i; extern uint16 *M; extern int32 saved_PC; diff --git a/PDP11/pdp11_rp.c b/PDP11/pdp11_rp.c index 2b8cfef6..57786356 100644 --- a/PDP11/pdp11_rp.c +++ b/PDP11/pdp11_rp.c @@ -131,6 +131,29 @@ #define CS1_DVA 04000 /* drive avail */ #define GET_FNC(x) (((x) >> CS1_V_FNC) & CS1_M_FNC) +static const char *rp_fname[CS1_N_FNC] = { + "NOP", "UNLD", "SEEK", "RECAL", "DCLR", "RLS", "OFFS", "RETN", + "PRESET", "PACK", "12", "13", "SEARCH", "15", "16", "17", + "20", "21", "22", "23", "WRCHK", "25", "26", "27", + "WRITE", "WRHDR", "32", "33", "READ", "RDHDR", "36", "37" + }; + +BITFIELD rp_cs1_bits[] = { + BIT(GO), /* Go */ + BITFNAM(FUNC,5,rp_fname), /* Function Code */ + BIT(IE), /* Interrupt Enable */ + BIT(RDY), /* Drive Ready */ + BIT(A16), /* Bus Address Extension Bit 16 */ + BIT(A17), /* Bus Address Extension Bit 17 */ + BIT(PSEL), /* Port Select */ + BIT(DVA), /* Drive Available */ + BITNCF(1), /* 12 Reserved */ + BIT(MCPE), /* Massbus Control Parity Error */ + BIT(TRE), /* Transfer Error */ + BIT(SC), /* Special Condition */ + ENDBITS +}; + /* RPDS, RMDS - drive status - offset 1 */ #define RP_DS_OF 1 @@ -148,6 +171,22 @@ #define DS_ATA 0100000 /* attention active */ #define DS_MBZ 0000076 +BITFIELD rp_ds_bits[] = { + BIT(OM), /* offset mode */ + BITF(MBZ,5), /* must be zero */ + BIT(VV), /* volume valid */ + BIT(RDY), /* drive ready */ + BIT(DPR), /* drive present */ + BIT(PGM), /* programmable NI */ + BIT(LST), /* write clk fail NI */ + BIT(WRL), /* ECC hard err NI */ + BIT(MOL), /* hdr comp err NI */ + BIT(PIP), /* hdr CRC err NI */ + BIT(ERR), /* addr ovflo err */ + BIT(ATA), /* invalid addr err */ + ENDBITS +}; + /* RPER1, RMER1 - error status 1 - offset 2 */ #define RP_ER1_OF 2 @@ -169,17 +208,55 @@ #define ER1_UNS 0040000 /* drive unsafe */ #define ER1_DCK 0100000 /* data check NI */ +BITFIELD rp_er1_bits[] = { + BIT(ILF), /* Illegal Function */ + BIT(ILR), /* Illegal Register */ + BIT(RMR), /* reg mod refused */ + BIT(PAR), /* parity err */ + BIT(FER), /* format err NI */ + BIT(WCF), /* write clk fail NI */ + BIT(ECH), /* ECC hard err NI */ + BIT(HCE), /* hdr comp err NI */ + BIT(HCR), /* hdr CRC err NI */ + BIT(AOE), /* addr ovflo err */ + BIT(IAE), /* invalid addr err */ + BIT(WLE), /* write lock err */ + BIT(DTE), /* drive time err NI */ + BIT(OPI), /* op incomplete */ + BIT(UNS), /* drive unsafe */ + BIT(DCK), /* data check NI */ + ENDBITS +}; + /* RPMR, RMMR - maintenace register - offset 3*/ #define RP_MR_OF 3 #define RM_MR_OF (3 + RM_OF) +BITFIELD rp_mr_bits[] = { + BITF(MR,16), /* Maintenance Register */ + ENDBITS +}; + /* RPAS, RMAS - attention summary - offset 4 */ #define RP_AS_OF 4 #define RM_AS_OF (4 + RM_OF) #define AS_U0 0000001 /* unit 0 flag */ +BITFIELD rp_as_bits[] = { + BIT(ATA0), /* Drive 0 Attention */ + BIT(ATA1), /* Drive 1 Attention */ + BIT(ATA2), /* Drive 2 Attention */ + BIT(ATA3), /* Drive 3 Attention */ + BIT(ATA4), /* Drive 4 Attention */ + BIT(ATA5), /* Drive 5 Attention */ + BIT(ATA6), /* Drive 6 Attention */ + BIT(ATA7), /* Drive 7 Attention */ + BITNCF(8), /* 08:15 Reserved */ + ENDBITS +}; + /* RPDA, RMDA - sector/track - offset 5 */ #define RP_DA_OF 5 @@ -192,22 +269,52 @@ #define GET_SC(x) (((x) >> DA_V_SC) & DA_M_SC) #define GET_SF(x) (((x) >> DA_V_SF) & DA_M_SF) +BITFIELD rp_da_bits[] = { + BITF(SA,5), /* Sector Address */ + BITNCF(3), /* 05:07 Reserved */ + BITF(TA,5), /* Track Address */ + BITNCF(3), /* 13:15 Reserved */ + ENDBITS +}; + /* RPDT, RMDT - drive type - offset 6 */ #define RP_DT_OF 6 #define RM_DT_OF (6 + RM_OF) +BITFIELD rp_dt_bits[] = { + BITF(DT,9), /* Drive Type */ + BITNCF(2), /* 09:10 Reserved */ + BIT(DRQ), /* Drive Request Required */ + BITNCF(1), /* 12 Reserved */ + BIT(MOH), /* Moving Head */ + BITNCF(2), /* 14:15 Reserved */ + ENDBITS +}; + /* RPLA, RMLA - look ahead register - offset 7 */ #define RP_LA_OF 7 #define RM_LA_OF (7 + RM_OF) #define LA_V_SC 6 /* sector pos */ +BITFIELD rp_la_bits[] = { + BITNCF(6), /* 00:05 Reserved */ + BITF(SC,5), /* sector pos */ + BITNCF(5), /* 12:15 Reserved */ + ENDBITS +}; + /* RPSN, RMSN - serial number - offset 8 */ #define RP_SN_OF 8 #define RM_SN_OF (8 + RM_OF) +BITFIELD rp_sn_bits[] = { + BITF(SN,16), /* Serial Number */ + ENDBITS +}; + /* RPOF, RMOF - offset register - offset 9 */ #define RP_OF_OF 9 @@ -217,6 +324,17 @@ #define OF_F22 0010000 /* format NI */ #define OF_MBZ 0161400 +BITFIELD rp_of_bits[] = { + BITNCF(7), /* 00:06 Reserved */ + BIT(OFFDIR), /* Offset Direction */ + BITNCF(2), /* 08:09 Reserved */ + BIT(HCI), /* hdr comp inh NI */ + BIT(ECI), /* ECC inh NI */ + BIT(FMT), /* format NI */ + BITNCF(3), /* 13:15 Reserved */ + ENDBITS +}; + /* RPDC, RMDC - desired cylinder - offset 10 */ #define RP_DC_OF 10 @@ -228,34 +346,125 @@ #define GET_DA(c,fs,d) ((((GET_CY (c) * drv_tab[d].surf) + \ GET_SF (fs)) * drv_tab[d].sect) + GET_SC (fs)) +BITFIELD rp_dc_bits[] = { + BITF(DC,10), /* Offset Direction */ + BITNCF(6), /* 10:15 Unused */ + ENDBITS +}; + /* RPCC - current cylinder - offset 11 RMHR - holding register - offset 11 */ #define RP_CC_OF 11 #define RM_HR_OF (11 + RM_OF) +BITFIELD rp_cc_bits[] = { + BITF(CC,16), /* current cylinder */ + ENDBITS +}; + /* RPER2 - error status 2 - drive unsafe conditions - unimplemented - offset 12 RMMR2 - maintenance register - unimplemented - offset 12 */ #define RP_ER2_OF 12 #define RM_MR2_OF (12 + RM_OF) +BITFIELD rp_er2_bits[] = { + BITNCF(3), /* 00:02 Unused */ + BIT(DPE), /* data parity error */ + BITNCF(3), /* 04:06 Unused */ + BIT(DVC), /* device check */ + BITNCF(2), /* 08:09 Unused */ + BIT(LBC), /* Loss of bit clock */ + BIT(LSC), /* Loss of system clock */ + BIT(IVC), /* Invalid Command */ + BIT(OPE), /* Operator Plug Error */ + BIT(SKI), /* Seek Incomplete */ + BIT(BSE), /* Bad Sector Error */ + ENDBITS +}; + /* RPER3 - error status 3 - more unsafe conditions - unimplemented - offset 13 RMER2 - error status 2 - unimplemented - offset 13 */ #define RP_ER3_OF 13 #define RM_ER2_OF (13 + RM_OF) +BITFIELD rp_er3_bits[] = { + BITNCF(3), /* 00:02 Unused */ + BIT(DPE), /* data parity error */ + BITNCF(3), /* 04:06 Unused */ + BIT(DVC), /* device check */ + BITNCF(2), /* 08:09 Unused */ + BIT(LBC), /* Loss of bit clock */ + BIT(LSC), /* Loss of system clock */ + BIT(IVC), /* Invalid Command */ + BIT(OPE), /* Operator Plug Error */ + BIT(SKI), /* Seek Incomplete */ + BIT(BSE), /* Bad Sector Error */ + ENDBITS +}; + /* RPEC1, RMEC1 - ECC status 1 - unimplemented - offset 14 */ #define RP_EC1_OF 14 #define RM_EC1_OF (14 + RM_OF) +BITFIELD rp_ec1_bits[] = { + BITF(P,13), /* ECC Position Register */ + BITNCF(3), /* 13:15 Unused */ + ENDBITS +}; + /* RPEC2, RMEC1 - ECC status 2 - unimplemented - offset 15 */ #define RP_EC2_OF 15 #define RM_EC2_OF (15 + RM_OF) +BITFIELD rp_ec2_bits[] = { + BITF(PAT,11), /* ECC Pattern Register */ + BITNCF(5), /* 11:15 Unused */ + ENDBITS +}; + +BITFIELD *rp_reg_bits[] = { + rp_cs1_bits, + rp_ds_bits, + rp_er1_bits, + rp_mr_bits, + rp_as_bits, + rp_da_bits, + rp_dt_bits, + rp_la_bits, + rp_sn_bits, + rp_of_bits, + rp_dc_bits, + rp_cc_bits, + rp_er2_bits, + rp_er3_bits, + rp_ec1_bits, + rp_ec2_bits, + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, + rp_cs1_bits, + rp_ds_bits, + rp_er1_bits, + rp_mr_bits, + rp_as_bits, + rp_da_bits, + rp_dt_bits, + rp_la_bits, + rp_sn_bits, + rp_of_bits, + rp_dc_bits, + rp_cc_bits, + rp_er2_bits, + rp_er3_bits, + rp_ec1_bits, + rp_ec2_bits, +}; + + + /* This controller supports many different disk drive types: type #sectors/ #surfaces/ #cylinders/ @@ -357,14 +566,6 @@ uint16 rpec2[RP_NUMDR] = { 0 }; /* ECC correction 2 */ int32 rp_stopioe = 1; /* stop on error */ int32 rp_swait = 26; /* seek time */ int32 rp_rwait = 10; /* rotate time */ -static const char *rp_fname[CS1_N_FNC] = { - "NOP", "UNLD", "SEEK", "RECAL", "DCLR", "RLS", "OFFS", "RETN", - "PRESET", "PACK", "12", "13", "SCH", "15", "16", "17", - "20", "21", "22", "23", "WRCHK", "25", "26", "27", - "WRITE", "WRHDR", "32", "33", "READ", "RDHDR", "36", "37" - }; - -extern FILE *sim_deb; t_stat rp_mbrd (int32 *data, int32 ofs, int32 drv); t_stat rp_mbwr (int32 data, int32 ofs, int32 drv); @@ -479,12 +680,97 @@ MTAB rp_mod[] = { { 0 } }; +/* debugging bitmaps */ +#define DBG_TRC 0x0001 /* trace routine calls */ +#define DBG_REG 0x0002 /* trace read/write registers */ +#define DBG_REQ 0x0004 /* display transfer requests */ +#define DBG_DSK 0x0008 /* display sim_disk activities */ +#define DBG_DAT 0x0010 /* display transfer data */ + +DEBTAB rp_debug[] = { + {"TRACE", DBG_TRC}, + {"REG", DBG_REG}, + {"REQ", DBG_REQ}, + {"DISK", DBG_DSK}, + {"DATA", DBG_DAT}, + {0} +}; + DEVICE rp_dev = { "RP", rp_unit, rp_reg, rp_mod, RP_NUMDR, DEV_RDX, 30, 1, DEV_RDX, 16, NULL, NULL, &rp_reset, &rp_boot, &rp_attach, &rp_detach, - &rp_dib, DEV_DISABLE | DEV_UBUS | DEV_QBUS | DEV_MBUS | DEV_DEBUG + &rp_dib, DEV_DISABLE | DEV_UBUS | DEV_QBUS | DEV_MBUS | DEV_DEBUG | DEV_DISK, + 0, rp_debug + }; + +char *rp_regnam[] = + { + "RP_CS1", /* 0 */ + "RP_DS", /* 1 */ + "RP_ER1", /* 2 */ + "RP_MR", /* 3 */ + "RP_AS", /* 4 */ + "RP_DA", /* 5 */ + "RP_DT", /* 6 */ + "RP_LA", /* 7 */ + "RP_SN", /* 8 */ + "RP_OF", /* 9 */ + "RP_DC", /* 10 */ + "RP_CC", /* 11 */ + "RP_ER2", /* 12 */ + "RP_ER3", /* 13 */ + "RP_EC1", /* 14 */ + "RP_EC2", /* 15 */ + "16", /* 16 */ + "17", /* 17 */ + "18", /* 18 */ + "19", /* 19 */ + "20", /* 20 */ + "21", /* 21 */ + "22", /* 22 */ + "23", /* 23 */ + "24", /* 24 */ + "25", /* 25 */ + "26", /* 26 */ + "27", /* 27 */ + "28", /* 28 */ + "29", /* 29 */ + "30", /* 30 */ + "31", /* 31 */ + "RM_CS1", /* 32 */ + "RM_DS", /* 33 */ + "RM_ER1", /* 34 */ + "RM_MR", /* 35 */ + "RM_AS", /* 36 */ + "RM_DA", /* 37 */ + "RM_DT", /* 38 */ + "RM_LA", /* 39 */ + "RM_SN", /* 40 */ + "RM_OF", /* 41 */ + "RM_DC", /* 42 */ + "RM_CC", /* 43 */ + "RM_MR2", /* 44 */ + "RM_ER2", /* 45 */ + "RM_EC1", /* 46 */ + "RM_EC2", /* 47 */ + "48", /* 48 */ + "49", /* 49 */ + "50", /* 50 */ + "51", /* 51 */ + "52", /* 52 */ + "53", /* 53 */ + "54", /* 54 */ + "55", /* 55 */ + "56", /* 56 */ + "57", /* 57 */ + "58", /* 58 */ + "59", /* 59 */ + "60", /* 60 */ + "61", /* 61 */ + "62", /* 62 */ + "63", /* 63 */ }; /* Massbus register read */ @@ -588,6 +874,9 @@ switch (ofs) { /* decode offset */ return MBE_NXR; } +sim_debug(DBG_REG, &rp_dev, "rp_mbrd(drv=%d(%s), %s=0x%X)\n", drv, drv_tab[dtype].name, rp_regnam[ofs], val); +sim_debug_bits(DBG_REG, &rp_dev, rp_reg_bits[ofs], val, val, 1); + *data = val; return SCPE_OK; } @@ -596,10 +885,12 @@ return SCPE_OK; t_stat rp_mbwr (int32 data, int32 ofs, int32 drv) { -int32 dtype; -UNIT *uptr; +uint32 old_reg; +UNIT *uptr = rp_dev.units + drv; /* get unit */ +int32 dtype = GET_DTYPE (uptr->flags); /* get drive type */ + +sim_debug(DBG_REG, &rp_dev, "rp_mbwr(drv=%d(%s), %s=0x%X)\n", drv, drv_tab[dtype].name, rp_regnam[ofs], data); -uptr = rp_dev.units + drv; /* get unit */ if (uptr->flags & UNIT_DIS) /* nx disk */ return MBE_NXD; if ((ofs != RP_AS_OF) && sim_is_active (uptr)) { /* unit busy? */ @@ -608,7 +899,6 @@ if ((ofs != RP_AS_OF) && sim_is_active (uptr)) { /* unit busy? */ return SCPE_OK; } rmhr[drv] = data; /* save write */ -dtype = GET_DTYPE (uptr->flags); /* get drive type */ ofs = ofs & MBA_RMASK; /* mask offset */ if (drv_tab[dtype].ctrl == RM_CTRL) /* RM? convert */ ofs = ofs + RM_OF; @@ -616,33 +906,46 @@ if (drv_tab[dtype].ctrl == RM_CTRL) /* RM? convert */ switch (ofs) { /* decode PA<5:1> */ case RP_CS1_OF: case RM_CS1_OF: /* RPCS1 */ + old_reg = rpcs1[drv]; rpcs1[drv] = data & CS1_RW; + sim_debug_bits(DBG_REG, &rp_dev, rp_reg_bits[ofs], old_reg, rpcs1[drv], 1); if (data & CS1_GO) /* start op */ return rp_go (drv); break; case RP_DA_OF: case RM_DA_OF: /* RPDA */ + old_reg = rpds[drv]; rpda[drv] = data & ~DA_MBZ; + sim_debug_bits(DBG_REG, &rp_dev, rp_reg_bits[ofs], old_reg, rpds[drv], 1); break; case RP_AS_OF: case RM_AS_OF: /* RPAS */ + sim_debug_bits(DBG_REG, &rp_dev, rp_reg_bits[ofs], data, data, 1); rp_clr_as (data); break; case RP_MR_OF: case RM_MR_OF: /* RPMR */ + old_reg = rpmr[drv]; rpmr[drv] = data; + sim_debug_bits(DBG_REG, &rp_dev, rp_reg_bits[ofs], old_reg, rpmr[drv], 1); break; case RP_OF_OF: case RM_OF_OF: /* RPOF */ + old_reg = rpof[drv]; rpof[drv] = data & ~OF_MBZ; + sim_debug_bits(DBG_REG, &rp_dev, rp_reg_bits[ofs], old_reg, rpof[drv], 1); break; case RP_DC_OF: case RM_DC_OF: /* RPDC */ + old_reg = rpdc[drv]; rpdc[drv] = data & ~DC_MBZ; + sim_debug_bits(DBG_REG, &rp_dev, rp_reg_bits[ofs], old_reg, rpdc[drv], 1); break; case RM_MR2_OF: /* RMMR2 */ + old_reg = rmmr2[drv]; rmmr2[drv] = data; + sim_debug_bits(DBG_REG, &rp_dev, rp_reg_bits[ofs], old_reg, rmmr2[drv], 1); break; case RP_ER1_OF: case RM_ER1_OF: /* RPER1 */ @@ -670,16 +973,17 @@ return SCPE_OK; t_stat rp_go (int32 drv) { -int32 dc, fnc, dtype, t; -UNIT *uptr; +int32 dc, fnc, t; +DEVICE *dptr = &rp_dev; +UNIT *uptr = dptr->units + drv; /* get unit */ +int32 dtype = GET_DTYPE (uptr->flags); /* get drive type */ + +sim_debug(DBG_REQ, dptr, "rp_go(drv=%d(%s))\n", drv, drv_tab[dtype].name); fnc = GET_FNC (rpcs1[drv]); /* get function */ -if (DEBUG_PRS (rp_dev)) - fprintf (sim_deb, ">>RP%d STRT: fnc=%s, ds=%o, cyl=%o, da=%o, er=%o\n", - drv, rp_fname[fnc], rpds[drv], rpdc[drv], rpda[drv], rper1[drv]); -uptr = rp_dev.units + drv; /* get unit */ +sim_debug(DBG_REQ, dptr, ">>RP%d STRT: fnc=%s, ds=%o, cyl=%o, da=%o, er=%o\n", + drv, rp_fname[fnc], rpds[drv], rpdc[drv], rpda[drv], rper1[drv]); rp_clr_as (AS_U0 << drv); /* clear attention */ -dtype = GET_DTYPE (uptr->flags); /* get drive type */ dc = rpdc[drv]; /* assume seek, sch */ if ((fnc != FNC_DCLR) && (rpds[drv] & DS_ERR)) { /* err & ~clear? */ rp_set_er (ER1_ILF, drv); /* not allowed */ @@ -689,14 +993,17 @@ if ((fnc != FNC_DCLR) && (rpds[drv] & DS_ERR)) { /* err & ~clear? */ switch (fnc) { /* case on function */ + case FNC_RELEASE: /* port release */ case FNC_DCLR: /* drive clear */ rper1[drv] = rper2[drv] = rper3[drv] = 0; /* clear errors */ rpec2[drv] = 0; /* clear EC2 */ if (drv_tab[dtype].ctrl == RM_CTRL) /* RM? */ rpmr[drv] = 0; /* clear maint */ else rpec1[drv] = 0; /* RP, clear EC1 */ + rpds[drv] = rpds[drv] & ~DS_ERR; /* Clear ERR */ case FNC_NOP: /* no operation */ - case FNC_RELEASE: /* port release */ + sim_debug (DBG_REQ, dptr, ">>RP%d DONE: fnc=%s, ds=%o, cyl=%o, da=%o, er=%d\n", + drv, rp_fname[fnc], rpds[drv], rpdc[drv], rpda[drv], rper1[drv]); return SCPE_OK; case FNC_PRESET: /* read-in preset */ @@ -718,6 +1025,13 @@ switch (fnc) { /* case on function */ return SCPE_OK; case FNC_UNLOAD: /* unload */ + if (drv_tab[dtype].ctrl == RM_CTRL) { /* RM? */ + rp_set_er (ER1_ILF, drv); /* not supported */ + break; + } + rp_detach (uptr); /* detach unit */ + return SCPE_OK; + case FNC_RECAL: /* recalibrate */ dc = 0; /* seek to 0 */ case FNC_SEEK: /* seek */ @@ -773,6 +1087,7 @@ return MBE_GOE; int32 rp_abort (void) { +sim_debug(DBG_TRC, &rp_dev, "rp_abort()\n"); return rp_reset (&rp_dev); } @@ -780,8 +1095,13 @@ return rp_reset (&rp_dev); void rp_io_complete (UNIT *uptr, t_stat status) { +DEVICE *dptr = find_dev_from_unit (uptr); + +sim_debug(DBG_TRC, dptr, "rp_io_complete(rp%d, status=%d)\n", (int)(uptr - dptr->units), status); uptr->io_status = status; uptr->io_complete = 1; +/* Initiate Bottom End processing */ +sim_activate (uptr, 0); } /* Service unit timeout @@ -795,16 +1115,20 @@ t_stat rp_svc (UNIT *uptr) { int32 i, fnc, dtype, drv, err; int32 wc, abc, awc, mbc, da; +DEVICE *dptr = find_dev_from_unit (uptr); +DIB *dibp = (DIB *) dptr->ctxt; dtype = GET_DTYPE (uptr->flags); /* get drive type */ drv = (int32) (uptr - rp_dev.units); /* get drv number */ da = GET_DA (rpdc[drv], rpda[drv], dtype) * RP_NUMWD; /* get disk addr */ fnc = GET_FNC (rpcs1[drv]); /* get function */ +sim_debug(DBG_TRC, dptr, "rp_svc(rp%d(%s), %s, da=0x%X, fnc=%s)\n", drv, drv_tab[dtype].name, uptr->io_complete ? "Bottom" : "Top", da, rp_fname[fnc]); + if ((uptr->flags & UNIT_ATT) == 0) { /* not attached? */ rp_set_er (ER1_UNS, drv); /* set drive error */ if (fnc >= FNC_XFER) /* xfr? set done */ - mba_set_don (rp_dib.ba); + mba_set_don (dibp->ba); rp_update_ds (DS_ATA, drv); /* set attn */ return (rp_stopioe? SCPE_UNATT: SCPE_OK); } @@ -821,10 +1145,6 @@ if (!uptr->io_complete) { /* Top End (I/O Initiation) Processing */ rp_update_ds (DS_ATA, drv); break; - case FNC_UNLOAD: /* unload */ - rp_detach (uptr); /* detach unit */ - break; - case FNC_RECAL: /* recalibrate */ case FNC_SEARCH: /* search */ case FNC_SEEK: /* seek */ @@ -834,31 +1154,32 @@ if (!uptr->io_complete) { /* Top End (I/O Initiation) Processing */ case FNC_WRITE: /* write */ if (uptr->flags & UNIT_WPRT) { /* write locked? */ rp_set_er (ER1_WLE, drv); /* set drive error */ - mba_set_exc (rp_dib.ba); /* set exception */ + mba_set_exc (dibp->ba); /* set exception */ rp_update_ds (DS_ATA, drv); /* set attn */ return SCPE_OK; } case FNC_WCHK: /* write check */ case FNC_READ: /* read */ case FNC_READH: /* read headers */ - mbc = mba_get_bc (rp_dib.ba); /* get byte count */ + mbc = mba_get_bc (dibp->ba); /* get byte count */ wc = (mbc + 1) >> 1; /* convert to words */ if ((da + wc) > drv_tab[dtype].size) { /* disk overrun? */ rp_set_er (ER1_AOE, drv); /* set err */ wc = drv_tab[dtype].size - da; /* trim xfer */ mbc = wc << 1; /* trim mb count */ if (da >= drv_tab[dtype].size) { /* none left? */ - mba_set_exc (rp_dib.ba); /* set exception */ + mba_set_exc (dibp->ba); /* set exception */ rp_update_ds (DS_ATA, drv); /* set attn */ break; } } if (fnc == FNC_WRITE) { /* write? */ - abc = mba_rdbufW (rp_dib.ba, mbc, rpxb[drv]);/* get buffer */ + abc = mba_rdbufW (dibp->ba, mbc, rpxb[drv]);/* get buffer */ wc = (abc + 1) >> 1; /* actual # wds */ awc = (wc + (RP_NUMWD - 1)) & ~(RP_NUMWD - 1); for (i = wc; i < awc; i++) /* fill buf */ rpxb[drv][i] = 0; + sim_disk_data_trace (uptr, (void *)rpxb[drv], da/RP_NUMWD, awc, "sim_disk_wrsect-WR", DBG_DAT & dptr->dctrl, DBG_REQ); sim_disk_wrsect_a (uptr, da/RP_NUMWD, (void *)rpxb[drv], NULL, awc/RP_NUMWD, rp_io_complete); return SCPE_OK; } /* end if wr */ @@ -869,7 +1190,7 @@ if (!uptr->io_complete) { /* Top End (I/O Initiation) Processing */ } /* end if read */ case FNC_WRITEH: /* write headers stub */ - mba_set_don (rp_dib.ba); /* set done */ + mba_set_don (dibp->ba); /* set done */ rp_update_ds (0, drv); /* update ds */ break; } /* end case func */ @@ -893,17 +1214,18 @@ else { /* Bottom End (After I/O processing) */ case FNC_WCHK: /* write check */ case FNC_READ: /* read */ case FNC_READH: /* read headers */ - mbc = mba_get_bc (rp_dib.ba); /* get byte count */ + mbc = mba_get_bc (dibp->ba); /* get byte count */ wc = (mbc + 1) >> 1; /* convert to words */ if (fnc == FNC_WRITE) { /* write? */ } /* end if wr */ else { /* read or wchk */ awc = uptr->sectsread * RP_NUMWD; + sim_disk_data_trace (uptr, (uint8*)rpxb[drv], da/RP_NUMWD, awc << 1, "sim_disk_rdsect", DBG_DAT & dptr->dctrl, DBG_REQ); for (i = awc; i < wc; i++) /* fill buf */ rpxb[drv][i] = 0; if (fnc == FNC_WCHK) /* write check? */ - mba_chbufW (rp_dib.ba, mbc, rpxb[drv]); /* check vs mem */ - else mba_wrbufW (rp_dib.ba, mbc, rpxb[drv]);/* store in mem */ + mba_chbufW (dibp->ba, mbc, rpxb[drv]); /* check vs mem */ + else mba_wrbufW (dibp->ba, mbc, rpxb[drv]);/* store in mem */ } /* end if read */ da = da + wc + (RP_NUMWD - 1); if (da >= drv_tab[dtype].size) @@ -917,21 +1239,20 @@ else { /* Bottom End (After I/O processing) */ if (err != 0) { /* error? */ rp_set_er (ER1_PAR, drv); /* set drive error */ - mba_set_exc (rp_dib.ba); /* set exception */ + mba_set_exc (dibp->ba); /* set exception */ rp_update_ds (DS_ATA, drv); perror ("RP I/O error"); return SCPE_IOERR; } - mba_set_don (rp_dib.ba); /* set done */ + mba_set_don (dibp->ba); /* set done */ rp_update_ds (0, drv); /* update ds */ break; } /* end case func */ } rpds[drv] = (rpds[drv] & ~DS_PIP) | DS_RDY; /* change drive status */ -if (DEBUG_PRS (rp_dev)) - fprintf (sim_deb, ">>RP%d DONE: fnc=%s, ds=%o, cyl=%o, da=%o, er=%d\n", +sim_debug (DBG_REQ, dptr, ">>RP%d DONE: fnc=%s, ds=%o, cyl=%o, da=%o, er=%d\n", drv, rp_fname[fnc], rpds[drv], rpdc[drv], rpda[drv], rper1[drv]); return SCPE_OK; } @@ -940,6 +1261,7 @@ return SCPE_OK; void rp_set_er (int32 flag, int32 drv) { +sim_debug(DBG_TRC, &rp_dev, "rp_set_er(rp%d, flag=0x%X)\n", drv, flag); rper1[drv] = rper1[drv] | flag; rpds[drv] = rpds[drv] | DS_ATA; mba_upd_ata (rp_dib.ba, 1); @@ -958,6 +1280,9 @@ for (i = as = 0; i < RP_NUMDR; i++) { if (rpds[i] & DS_ATA) as = 1; } + +sim_debug(DBG_TRC, &rp_dev, "rp_clr_as(mask=0x%X, as=0x%X)\n", mask, as); + mba_upd_ata (rp_dib.ba, as); return; } @@ -966,6 +1291,8 @@ return; void rp_update_ds (int32 flag, int32 drv) { +uint16 o_ds = rpds[drv]; + if (rp_unit[drv].flags & UNIT_DIS) rpds[drv] = rper1[drv] = 0; else rpds[drv] = (rpds[drv] | DS_DPR) & ~DS_PGM; @@ -978,6 +1305,12 @@ else rpds[drv] = rpds[drv] & ~DS_ERR; rpds[drv] = rpds[drv] | flag; if (flag & DS_ATA) mba_upd_ata (rp_dib.ba, 1); + +if (o_ds != rpds[drv]) { + sim_debug(DBG_TRC, &rp_dev, "rp_update_ds(rp%d, flag=0x%X, ds=0x%X)\n", drv, flag, rpds[drv]); + sim_debug_bits(DBG_TRC, &rp_dev, rp_ds_bits, o_ds, rpds[drv], 1); + } + return; } @@ -988,9 +1321,11 @@ t_stat rp_reset (DEVICE *dptr) int32 i; UNIT *uptr; -mba_set_enbdis (MBA_RP, rp_dev.flags & DEV_DIS); +sim_debug(DBG_TRC, dptr, "rp_reset()\n"); + +mba_set_enbdis (MBA_RP, dptr->flags & DEV_DIS); for (i = 0; i < RP_NUMDR; i++) { - uptr = rp_dev.units + i; + uptr = dptr->units + i; sim_cancel (uptr); uptr->CYL = 0; if (uptr->flags & UNIT_ATT) @@ -1025,6 +1360,7 @@ t_stat rp_attach (UNIT *uptr, char *cptr) { int32 drv, i, p; t_stat r; +DEVICE *dptr = find_dev_from_unit (uptr); uptr->capac = drv_tab[GET_DTYPE (uptr->flags)].size; r = sim_disk_attach (uptr, cptr, RP_NUMWD * sizeof (uint16), @@ -1032,7 +1368,7 @@ r = sim_disk_attach (uptr, cptr, RP_NUMWD * sizeof (uint16), drv_tab[GET_DTYPE (uptr->flags)].name, drv_tab[GET_DTYPE (uptr->flags)].sect, 0); if (r != SCPE_OK) /* error? */ return r; -drv = (int32) (uptr - rp_dev.units); /* get drv number */ +drv = (int32) (uptr - dptr->units); /* get drv number */ rpds[drv] = DS_MOL | DS_RDY | DS_DPR | /* upd drv status */ ((uptr->flags & UNIT_WPRT)? DS_WRL: 0); rper1[drv] = 0; @@ -1056,12 +1392,14 @@ return SCPE_OK; t_stat rp_detach (UNIT *uptr) { int32 drv; +DEVICE *dptr = find_dev_from_unit (uptr); if (!(uptr->flags & UNIT_ATT)) /* attached? */ return SCPE_OK; -drv = (int32) (uptr - rp_dev.units); /* get drv number */ +drv = (int32) (uptr - dptr->units); /* get drv number */ rpds[drv] = rpds[drv] & ~(DS_MOL | DS_RDY | DS_WRL | DS_VV | DS_OFM); -rp_update_ds (DS_ATA, drv); /* request intr */ +if (!sim_is_running) /* from console? */ + rp_update_ds (DS_ATA, drv); /* request intr */ return sim_disk_detach (uptr); } @@ -1120,10 +1458,10 @@ static const uint16 boot_rom[] = { t_stat rp_boot (int32 unitno, DEVICE *dptr) { -int32 i; +size_t i; extern int32 saved_PC; extern uint16 *M; -UNIT *uptr = rp_dev.units + unitno; +UNIT *uptr = dptr->units + unitno; for (i = 0; i < BOOT_LEN; i++) M[(BOOT_START >> 1) + i] = boot_rom[i]; diff --git a/PDP11/pdp11_rq.c b/PDP11/pdp11_rq.c index e860a866..7a7f4790 100644 --- a/PDP11/pdp11_rq.c +++ b/PDP11/pdp11_rq.c @@ -24,8 +24,22 @@ used in advertising or otherwise to promote the sale, use or other dealings in this Software without prior written authorization from Robert M Supnik. - rq RQDX3 disk controller + rq MSCP disk controller + 09-Dec-12 MB Added support for changing controller type. + 24-Oct-12 MB Added mapped transfers for VAX + 29-Jan-11 HUH Added RC25, RCF25 and RA80 disks + Not all disk parameters set yet + "KLESI" MSCP controller (3) / port (1) types for RC25 + not yet implemented + + Remarks on the RC25 disk drives: + In "real" life the RC25 drives exist in pairs only, + one RC25 (removable) and one RCF25 (fixed) in one housing. + The removable platter has always got an even drive number + (e.g. "0"), the fixed platter has always got the next (odd) + drive number (e.g. "1"). These two rules are not enforced + by the disk drive simulation. 07-Mar-11 MP Added working behaviors for removable device types. This allows physical CDROM's to come online and be ejected. @@ -127,8 +141,8 @@ extern uint32 cpu_opt; #define RQU_UQPM 6 /* UB port model */ #define RQQ_UQPM 19 /* QB port model */ #define RQ_UQPM (UNIBUS? RQU_UQPM: RQQ_UQPM) -#define RQU_MODEL 6 /* UB MSCP ctrl model */ -#define RQQ_MODEL 19 /* QB MSCP ctrl model */ +#define RQU_MODEL 6 /* UB MSCP ctrl model (UDA50A) */ +#define RQQ_MODEL 19 /* QB MSCP ctrl model (RQDX3) */ #define RQ_MODEL (UNIBUS? RQU_MODEL: RQQ_MODEL) #define RQ_HVER 1 /* hardware version */ #define RQ_SVER 3 /* software version */ @@ -137,6 +151,8 @@ extern uint32 cpu_opt; #define RQ_NUMDR 4 /* # drives */ #define RQ_NUMBY 512 /* bytes per block */ #define RQ_MAXFR (1 << 16) /* max xfer */ +#define RQ_MAPXFER (1 << 31) /* mapped xfer */ +#define RQ_M_PFN 0x1FFFFF /* map entry PFN */ #define UNIT_V_ONL (UNIT_V_UF + 0) /* online */ #define UNIT_V_WLK (UNIT_V_UF + 1) /* hwre write lock */ @@ -249,6 +265,7 @@ x RD33 17 7 1170 ? ? ? 138565 RA60 42(+1) 6 1600 6 1 1008 400176 x RA70 33(+1) 11 1507+ 11 1 ? 547041 + RA80 31 14 546 ? ? ? 237212 RA81 51(+1) 14 1258 14 1 2856 891072 RA82 57(+1) 15 1435 15 1 3420 1216665 RA71 51(+1) 14 1921 14 1 1428 1367310 @@ -257,6 +274,11 @@ x RA70 33(+1) 11 1507+ 11 1 ? 547041 RA92 73(+1) 13 3101 13 1 949 2940951 x RA73 70(+1) 21 2667+ 21 1 ? 3920490 + LESI attached RC25 disks (one removable, one fixed) + type sec surf cyl tpg gpc RCT LBNs + RC25 31 2 821 ? ? ? 50902 + RCF25 31 2 821 ? ? ? 50902 + Each drive can be a different type. The drive field in the unit flags specified the drive type and thus, indirectly, the drive size. @@ -533,7 +555,7 @@ x RA73 70(+1) 21 2667+ 21 1 ? 3920490 #define RD32_GPC 1 #define RD32_XBN 54 #define RD32_DBN 48 -#define RD32_LBN 83204 +#define RD32_LBN 83236 #define RD32_RCTS 4 #define RD32_RCTC 8 #define RD32_RBN 200 @@ -541,6 +563,74 @@ x RA73 70(+1) 21 2667+ 21 1 ? 3920490 #define RD32_MED 0x25644020 #define RD32_FLGS 0 +#define RC25_DTYPE 17 /* */ +#define RC25_SECT 50 /* */ +#define RC25_SURF 8 +#define RC25_CYL 1260 /* */ +#define RC25_TPG RC25_SURF +#define RC25_GPC 1 +#define RC25_XBN 0 /* */ +#define RC25_DBN 0 /* */ +#define RC25_LBN 50902 /* ? 50*8*1260 ? */ +#define RC25_RCTS 0 /* */ +#define RC25_RCTC 1 +#define RC25_RBN 0 /* */ +#define RC25_MOD 3 +#define RC25_MED 0x20643019 +#define RC25_FLGS RQDF_RMV + +#define RCF25_DTYPE 18 /* */ +#define RCF25_SECT 50 /* */ +#define RCF25_SURF 8 +#define RCF25_CYL 1260 /* */ +#define RCF25_TPG RCF25_SURF +#define RCF25_GPC 1 +#define RCF25_XBN 0 /* */ +#define RCF25_DBN 0 /* */ +#define RCF25_LBN 50902 /* ? 50*8*1260 ? */ +#define RCF25_RCTS 0 /* */ +#define RCF25_RCTC 1 +#define RCF25_RBN 0 /* */ +#define RCF25_MOD 3 +#define RCF25_MED 0x20643319 +#define RCF25_FLGS 0 + +#define RA80_DTYPE 19 /* SDI drive */ +#define RA80_SECT 31 /* +1 spare/track */ +#define RA80_SURF 14 +#define RA80_CYL 546 /* */ +#define RA80_TPG RA80_SURF +#define RA80_GPC 1 +#define RA80_XBN 0 /* */ +#define RA80_DBN 0 /* */ +#define RA80_LBN 237212 /* 31*14*546 */ +#define RA80_RCTS 0 /* */ +#define RA80_RCTC 1 +#define RA80_RBN 0 /* */ +#define RA80_MOD 1 +#define RA80_MED 0x25641050 +#define RA80_FLGS RQDF_SDI + +/* Controller parameters */ + +#define DEFAULT_CTYPE 0 + +#define KLESI_CTYPE 1 +#define KLESI_UQPM 1 +#define KLESI_MODEL 1 + +#define RUX50_CTYPE 2 +#define RUX50_UQPM 2 +#define RUX50_MODEL 2 + +#define UDA50_CTYPE 3 +#define UDA50_UQPM 6 +#define UDA50_MODEL 6 + +#define RQDX3_CTYPE 4 +#define RQDX3_UQPM 19 +#define RQDX3_MODEL 19 + struct drvtyp { int32 sect; /* sectors */ int32 surf; /* surfaces */ @@ -567,24 +657,49 @@ struct drvtyp { #define RQ_SIZE(d) (d##_LBN * RQ_NUMBY) static struct drvtyp drv_tab[] = { - { RQ_DRV (RX50), "RX50" }, { RQ_DRV (RX33), "RX33" }, - { RQ_DRV (RD51), "RD51" }, { RQ_DRV (RD31), "RD31" }, - { RQ_DRV (RD52), "RD52" }, { RQ_DRV (RD53), "RD53" }, - { RQ_DRV (RD54), "RD54" }, { RQ_DRV (RA82), "RA82" }, - { RQ_DRV (RRD40), "RRD40" }, { RQ_DRV (RA72), "RA72" }, - { RQ_DRV (RA90), "RA90" }, { RQ_DRV (RA92), "RA92" }, - { RQ_DRV (RA8U), "RAUSER" }, { RQ_DRV (RA60), "RA60" }, - { RQ_DRV (RA81), "RA81" }, { RQ_DRV (RA71), "RA71" }, - { RQ_DRV (RD32), "RD32" }, + { RQ_DRV (RX50), "RX50" }, + { RQ_DRV (RX33), "RX33" }, + { RQ_DRV (RD51), "RD51" }, + { RQ_DRV (RD31), "RD31" }, + { RQ_DRV (RD52), "RD52" }, + { RQ_DRV (RD53), "RD53" }, + { RQ_DRV (RD54), "RD54" }, + { RQ_DRV (RA82), "RA82" }, + { RQ_DRV (RRD40), "RRD40" }, + { RQ_DRV (RA72), "RA72" }, + { RQ_DRV (RA90), "RA90" }, + { RQ_DRV (RA92), "RA92" }, + { RQ_DRV (RA8U), "RAUSER" }, + { RQ_DRV (RA60), "RA60" }, + { RQ_DRV (RA81), "RA81" }, + { RQ_DRV (RA71), "RA71" }, + { RQ_DRV (RD32), "RD32" }, + { RQ_DRV (RC25), "RC25" }, + { RQ_DRV (RCF25), "RCF25" }, + { RQ_DRV (RA80), "RA80" }, + { 0 } + }; + +struct ctlrtyp { + uint32 uqpm; /* port model */ + uint32 model; /* controller model */ + char *name; /* name */ + }; + +#define RQ_CTLR(d) \ + d##_UQPM, d##_MODEL + +static struct ctlrtyp ctlr_tab[] = { + { 0, 0, "DEFAULT" }, + { RQ_CTLR (KLESI), "KLESI" }, + { RQ_CTLR (RUX50), "RUX50" }, + { RQ_CTLR (UDA50), "UDA50" }, + { RQ_CTLR (RQDX3), "RQDX3" }, { 0 } }; extern int32 int_req[IPL_HLVL]; extern int32 tmr_poll, clk_tps; -extern UNIT cpu_unit; -extern FILE *sim_deb; -extern uint32 sim_taddr_64; -extern int32 sim_switches; int32 rq_itime = 200; /* init time, except */ int32 rq_itime4 = 10; /* stage 4 */ @@ -610,6 +725,7 @@ typedef struct { uint32 credits; /* credits */ uint32 hat; /* host timer */ uint32 htmo; /* host timeout */ + uint32 ctype; /* controller type */ struct uq_ring cq; /* cmd ring */ struct uq_ring rq; /* rsp ring */ struct rqpkt pak[RQ_NPKTS]; /* packet queue */ @@ -677,7 +793,9 @@ t_stat rq_detach (UNIT *uptr); t_stat rq_boot (int32 unitno, DEVICE *dptr); t_stat rq_set_wlk (UNIT *uptr, int32 val, char *cptr, void *desc); t_stat rq_set_type (UNIT *uptr, int32 val, char *cptr, void *desc); +t_stat rq_set_ctype (UNIT *uptr, int32 val, char *cptr, void *desc); t_stat rq_show_type (FILE *st, UNIT *uptr, int32 val, void *desc); +t_stat rq_show_ctype (FILE *st, UNIT *uptr, int32 val, void *desc); t_stat rq_show_wlk (FILE *st, UNIT *uptr, int32 val, void *desc); t_stat rq_show_ctrl (FILE *st, UNIT *uptr, int32 val, void *desc); t_stat rq_show_unitq (FILE *st, UNIT *uptr, int32 val, void *desc); @@ -707,6 +825,10 @@ t_bool rq_getdesc (MSC *cp, struct uq_ring *ring, uint32 *desc); t_bool rq_putdesc (MSC *cp, struct uq_ring *ring, uint32 desc); int32 rq_rw_valid (MSC *cp, int32 pkt, UNIT *uptr, uint32 cmd); t_bool rq_rw_end (MSC *cp, UNIT *uptr, uint32 flg, uint32 sts); +uint32 rq_map_ba (uint32 ba, uint32 ma); +int32 rq_readb (uint32 ba, int32 bc, uint32 ma, uint8 *buf); +int32 rq_readw (uint32 ba, int32 bc, uint32 ma, uint16 *buf); +int32 rq_writew (uint32 ba, int32 bc, uint32 ma, uint16 *buf); void rq_putr (MSC *cp, int32 pkt, uint32 cmd, uint32 flg, uint32 sts, uint32 lnt, uint32 typ); void rq_putr_unit (MSC *cp, int32 pkt, UNIT *uptr, uint32 lu, t_bool all); @@ -730,8 +852,10 @@ int32 rq_inta (void); MSC rq_ctx = { 0 }; +#define IOLN_RQ 004 + DIB rq_dib = { - IOBA_RQ, IOLN_RQ, &rq_rd, &rq_wr, + IOBA_AUTO, IOLN_RQ, &rq_rd, &rq_wr, 1, IVCL (RQ), 0, { &rq_inta } }; @@ -801,6 +925,14 @@ MTAB rq_mod[] = { NULL, &rq_show_ctrl, 0 }, { MTAB_XTD | MTAB_VDV | MTAB_NMO, RQ_SH_ALL, "ALL", NULL, NULL, &rq_show_ctrl, 0 }, + { MTAB_XTD | MTAB_VDV, KLESI_CTYPE, NULL, "KLESI", + &rq_set_ctype, NULL, NULL }, + { MTAB_XTD | MTAB_VDV, RUX50_CTYPE, NULL, "RUX50", + &rq_set_ctype, NULL, NULL }, + { MTAB_XTD | MTAB_VDV, UDA50_CTYPE, NULL, "UDA50", + &rq_set_ctype, NULL, NULL }, + { MTAB_XTD | MTAB_VDV, RQDX3_CTYPE, NULL, "RQDX3", + &rq_set_ctype, NULL, NULL }, { MTAB_XTD | MTAB_VUN | MTAB_NMO, 0, "UNITQ", NULL, NULL, &rq_show_unitq, 0 }, { MTAB_XTD | MTAB_VUN, 0, "WRITE", NULL, @@ -839,6 +971,12 @@ MTAB rq_mod[] = { &rq_set_type, NULL, NULL }, { MTAB_XTD | MTAB_VUN, RA92_DTYPE, NULL, "RA92", &rq_set_type, NULL, NULL }, + { MTAB_XTD | MTAB_VUN, RC25_DTYPE, NULL, "RC25", + &rq_set_type, NULL, NULL }, + { MTAB_XTD | MTAB_VUN, RCF25_DTYPE, NULL, "RCF25", + &rq_set_type, NULL, NULL }, + { MTAB_XTD | MTAB_VUN, RA80_DTYPE, NULL, "RA80", + &rq_set_type, NULL, NULL }, { MTAB_XTD | MTAB_VUN, RA8U_DTYPE, NULL, "RAUSER", &rq_set_type, NULL, NULL }, { MTAB_XTD | MTAB_VUN, 0, "TYPE", NULL, @@ -858,6 +996,8 @@ MTAB rq_mod[] = { #endif { MTAB_XTD|MTAB_VDV, 0, "VECTOR", NULL, NULL, &show_vec, NULL }, + { MTAB_XTD | MTAB_VDV, 0, "TYPE", NULL, + NULL, &rq_show_ctype, NULL }, { 0 } }; @@ -866,7 +1006,7 @@ DEVICE rq_dev = { RQ_NUMDR + 2, DEV_RDX, T_ADDR_W, 2, DEV_RDX, 16, NULL, NULL, &rq_reset, &rq_boot, &rq_attach, &rq_detach, - &rq_dib, DEV_FLTA | DEV_DISABLE | DEV_UBUS | DEV_QBUS | DEV_DEBUG, + &rq_dib, DEV_DISABLE | DEV_UBUS | DEV_QBUS | DEV_DEBUG | DEV_DISK, 0, rq_debug }; @@ -881,7 +1021,7 @@ DEVICE rq_dev = { MSC rqb_ctx = { 1 }; DIB rqb_dib = { - IOBA_RQB, IOLN_RQB, &rq_rd, &rq_wr, + IOBA_AUTO, IOLN_RQ, &rq_rd, &rq_wr, 1, IVCL (RQ), 0, { &rq_inta } }; @@ -894,7 +1034,7 @@ UNIT rqb_unit[] = { (RD54_DTYPE << UNIT_V_DTYPE), RQ_SIZE (RD54)) }, { UDATA (&rq_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+UNIT_ROABLE+ (RD54_DTYPE << UNIT_V_DTYPE), RQ_SIZE (RD54)) }, - { UDATA (&rq_tmrsvc, UNIT_DIS, 0) }, + { UDATA (&rq_tmrsvc, UNIT_IDLE|UNIT_DIS, 0) }, { UDATA (&rq_quesvc, UNIT_DIS, 0) } }; @@ -938,7 +1078,7 @@ DEVICE rqb_dev = { RQ_NUMDR + 2, DEV_RDX, T_ADDR_W, 2, DEV_RDX, 16, NULL, NULL, &rq_reset, &rq_boot, &rq_attach, &rq_detach, - &rqb_dib, DEV_FLTA | DEV_DISABLE | DEV_DIS | DEV_UBUS | DEV_QBUS | DEV_DEBUG, + &rqb_dib, DEV_DISABLE | DEV_DIS | DEV_UBUS | DEV_QBUS | DEV_DEBUG | DEV_DISK, 0, rq_debug }; @@ -953,7 +1093,7 @@ DEVICE rqb_dev = { MSC rqc_ctx = { 2 }; DIB rqc_dib = { - IOBA_RQC, IOLN_RQC, &rq_rd, &rq_wr, + IOBA_AUTO, IOLN_RQ, &rq_rd, &rq_wr, 1, IVCL (RQ), 0, { &rq_inta } }; @@ -966,7 +1106,7 @@ UNIT rqc_unit[] = { (RD54_DTYPE << UNIT_V_DTYPE), RQ_SIZE (RD54)) }, { UDATA (&rq_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+UNIT_ROABLE+ (RD54_DTYPE << UNIT_V_DTYPE), RQ_SIZE (RD54)) }, - { UDATA (&rq_tmrsvc, UNIT_DIS, 0) }, + { UDATA (&rq_tmrsvc, UNIT_IDLE|UNIT_DIS, 0) }, { UDATA (&rq_quesvc, UNIT_DIS, 0) } }; @@ -1010,7 +1150,7 @@ DEVICE rqc_dev = { RQ_NUMDR + 2, DEV_RDX, T_ADDR_W, 2, DEV_RDX, 16, NULL, NULL, &rq_reset, &rq_boot, &rq_attach, &rq_detach, - &rqc_dib, DEV_FLTA | DEV_DISABLE | DEV_DIS | DEV_UBUS | DEV_QBUS | DEV_DEBUG, + &rqc_dib, DEV_DISABLE | DEV_DIS | DEV_UBUS | DEV_QBUS | DEV_DEBUG | DEV_DISK, 0, rq_debug }; @@ -1025,7 +1165,7 @@ DEVICE rqc_dev = { MSC rqd_ctx = { 3 }; DIB rqd_dib = { - IOBA_RQD, IOLN_RQD, &rq_rd, &rq_wr, + IOBA_AUTO, IOLN_RQ, &rq_rd, &rq_wr, 1, IVCL (RQ), 0, { &rq_inta } }; @@ -1038,7 +1178,7 @@ UNIT rqd_unit[] = { (RD54_DTYPE << UNIT_V_DTYPE), RQ_SIZE (RD54)) }, { UDATA (&rq_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+UNIT_ROABLE+ (RD54_DTYPE << UNIT_V_DTYPE), RQ_SIZE (RD54)) }, - { UDATA (&rq_tmrsvc, UNIT_DIS, 0) }, + { UDATA (&rq_tmrsvc, UNIT_IDLE|UNIT_DIS, 0) }, { UDATA (&rq_quesvc, UNIT_DIS, 0) } }; @@ -1082,7 +1222,7 @@ DEVICE rqd_dev = { RQ_NUMDR + 2, DEV_RDX, T_ADDR_W, 2, DEV_RDX, 16, NULL, NULL, &rq_reset, &rq_boot, &rq_attach, &rq_detach, - &rqd_dib, DEV_FLTA | DEV_DISABLE | DEV_DIS | DEV_UBUS | DEV_QBUS | DEV_DEBUG, + &rqd_dib, DEV_DISABLE | DEV_DIS | DEV_UBUS | DEV_QBUS | DEV_DEBUG | DEV_DISK, 0, rq_debug }; @@ -1203,7 +1343,8 @@ for (i = 0; i < (lnt >> 1); i++) /* clr buffer */ zero[i] = 0; if (Map_WriteW (base, lnt, zero)) /* zero comm area */ return rq_fatal (cp, PE_QWE); /* error? */ -cp->sa = SA_S4 | (RQ_UQPM << SA_S4C_V_MOD) | /* send step 4 */ +cp->sa = SA_S4 | /* send step 4 */ + (ctlr_tab[cp->ctype].uqpm << SA_S4C_V_MOD) | (RQ_SVER << SA_S4C_V_VER); cp->csta = CST_S4; /* set step 4 */ rq_init_int (cp); /* poke host */ @@ -1636,7 +1777,7 @@ else { cp->pak[pkt].d[SCC_CIDB] = 0; cp->pak[pkt].d[SCC_CIDC] = 0; cp->pak[pkt].d[SCC_CIDD] = (RQ_CLASS << SCC_CIDD_V_CLS) | - (RQ_MODEL << SCC_CIDD_V_MOD); + (ctlr_tab[cp->ctype].model << SCC_CIDD_V_MOD); cp->pak[pkt].d[SCC_MBCL] = 0; /* max bc */ cp->pak[pkt].d[SCC_MBCH] = 0; } @@ -1737,6 +1878,8 @@ if ((uptr = rq_getucb (cp, lu))) { /* unit exist? */ cp->pak[pkt].d[RW_WBCH] = cp->pak[pkt].d[RW_BCH]; cp->pak[pkt].d[RW_WBLL] = cp->pak[pkt].d[RW_LBNL]; cp->pak[pkt].d[RW_WBLH] = cp->pak[pkt].d[RW_LBNH]; + cp->pak[pkt].d[RW_WMPL] = cp->pak[pkt].d[RW_MAPL]; + cp->pak[pkt].d[RW_WMPH] = cp->pak[pkt].d[RW_MAPH]; uptr->iostarttime = sim_grtime(); sim_activate (uptr, 0); /* activate */ sim_debug (DBG_TRC, rq_devmap[cp->cnum], "rq_rw - started\n"); @@ -1803,6 +1946,100 @@ uptr->io_complete = 1; sim_activate_notbefore (uptr, uptr->iostarttime+rq_xtime); } +/* Map buffer address */ + +uint32 rq_map_ba (uint32 ba, uint32 ma) +{ +#if defined (VM_VAX) /* VAX version */ +int32 idx; +uint32 rg; + +idx = (VA_GETVPN(ba) << 2); /* map register index */ +rg = ReadL (ma + idx); /* map register */ +if (rg & PTE_V) /* valid? */ + return ((rg & RQ_M_PFN) << VA_N_OFF) | (ba & VA_M_OFF); +#endif +return 0; +} + +/* Read byte buffer from memory */ + +int32 rq_readb (uint32 ba, int32 bc, uint32 ma, uint8 *buf) +{ +#if defined (VM_VAX) /* VAX version */ +int32 lbc, t, tbc = 0; +uint32 pba; + +if (ba & RQ_MAPXFER) { /* mapped xfer? */ + while (tbc < bc) { + if (!(pba = rq_map_ba (ba, ma))) /* get physical ba */ + return (bc - tbc); + lbc = 0x200 - (ba & VA_M_OFF); /* bc for this tx */ + if (lbc > (bc - tbc)) lbc = (bc - tbc); + t = Map_ReadB (pba, lbc, buf); + tbc += (lbc - t); /* bytes xfer'd so far */ + if (t) return (bc - tbc); /* incomplete xfer? */ + ba += lbc; + buf += lbc; + } + return 0; + } +#endif +return Map_ReadB (ba, bc, buf); /* unmapped xfer */ +} + +/* Read word buffer from memory */ + +int32 rq_readw (uint32 ba, int32 bc, uint32 ma, uint16 *buf) +{ +#if defined (VM_VAX) /* VAX version */ +int32 lbc, t, tbc = 0; +uint32 pba; + +if (ba & RQ_MAPXFER) { /* mapped xfer? */ + while (tbc < bc) { + if (!(pba = rq_map_ba (ba, ma))) /* get physical ba */ + return (bc - tbc); + lbc = 0x200 - (ba & VA_M_OFF); /* bc for this tx */ + if (lbc > (bc - tbc)) lbc = (bc - tbc); + t = Map_ReadW (pba, lbc, buf); + tbc += (lbc - t); /* bytes xfer'd so far */ + if (t) return (bc - tbc); /* incomplete xfer? */ + ba += lbc; + buf += (lbc >> 1); + } + return 0; + } +#endif +return Map_ReadW (ba, bc, buf); /* unmapped xfer */ +} + +/* Write word buffer to memory */ + +int32 rq_writew (uint32 ba, int32 bc, uint32 ma, uint16 *buf) +{ +#if defined (VM_VAX) /* VAX version */ +int32 lbc, t, tbc = 0; +uint32 pba; + +if (ba & RQ_MAPXFER) { /* mapped xfer? */ + while (tbc < bc) { + if (!(pba = rq_map_ba (ba, ma))) /* get physical ba */ + return (bc - tbc); + lbc = 0x200 - (ba & VA_M_OFF); /* bc for this tx */ + if (lbc > (bc - tbc)) lbc = (bc - tbc); + t = Map_WriteW (pba, lbc, buf); + tbc += (lbc - t); /* bytes xfer'd so far */ + if (t) return (bc - tbc); /* incomplete xfer? */ + ba += lbc; + buf += (lbc >> 1); + } + return 0; + } +#endif +return Map_WriteW (ba, bc, buf); /* unmapped xfer */ +} + /* Unit service for data transfer commands */ t_stat rq_svc (UNIT *uptr) @@ -1815,6 +2052,7 @@ uint32 cmd = GETP (pkt, CMD_OPC, OPC); /* get cmd */ uint32 ba = GETP32 (pkt, RW_WBAL); /* buf addr */ uint32 bc = GETP32 (pkt, RW_WBCL); /* byte count */ uint32 bl = GETP32 (pkt, RW_WBLL); /* block addr */ +uint32 ma = GETP32 (pkt, RW_WMPL); /* block addr */ sim_debug (DBG_TRC, rq_devmap[cp->cnum], "rq_svc(unit=%d, pkt=%d, cmd=%s, lbn=%0X, bc=%0x, phase=%s)\n", uptr-rq_devmap[cp->cnum]->units, pkt, rq_cmdname[cp->pak[pkt].d[CMD_OPC]&0x3f], bl, bc, @@ -1853,7 +2091,7 @@ if (!uptr->io_complete) { /* Top End (I/O Initiation) Processing */ } else if (cmd == OP_WR) { /* write? */ - t = Map_ReadW (ba, tbc, uptr->rqxb); /* fetch buffer */ + t = rq_readw (ba, tbc, ma, uptr->rqxb); /* fetch buffer */ if ((abc = tbc - t)) { /* any xfer? */ wwc = ((abc + (RQ_NUMBY - 1)) & ~(RQ_NUMBY - 1)) >> 1; for (i = (abc >> 1); i < wwc; i++) @@ -1875,7 +2113,7 @@ else { /* Bottom End (After I/O processing) */ } else if (cmd == OP_WR) { /* write? */ - t = Map_ReadW (ba, tbc, uptr->rqxb); /* fetch buffer */ + t = rq_readw (ba, tbc, ma, uptr->rqxb); /* fetch buffer */ abc = tbc - t; /* any xfer? */ if (t) { /* nxm? */ PUTP32 (pkt, RW_WBCL, bc - abc); /* adj bc */ @@ -1889,7 +2127,7 @@ else { /* Bottom End (After I/O processing) */ else { sim_disk_data_trace(uptr, uptr->rqxb, bl, tbc, "sim_disk_rdsect", DBG_DAT & rq_devmap[cp->cnum]->dctrl, DBG_REQ); if ((cmd == OP_RD) && !err) { /* read? */ - if ((t = Map_WriteW (ba, tbc, uptr->rqxb))) {/* store, nxm? */ + if ((t = rq_writew (ba, tbc, ma, uptr->rqxb))) {/* store, nxm? */ PUTP32 (pkt, RW_WBCL, bc - (tbc - t)); /* adj bc */ PUTP32 (pkt, RW_WBAL, ba + (tbc - t)); /* adj ba */ if (rq_hbe (cp, uptr)) /* post err log */ @@ -1900,7 +2138,7 @@ else { /* Bottom End (After I/O processing) */ else if ((cmd == OP_CMP) && !err) { /* compare? */ uint8 dby, mby; for (i = 0; i < tbc; i++) { /* loop */ - if (Map_ReadB (ba + i, 1, &mby)) { /* fetch, nxm? */ + if (rq_readb (ba + i, 1, ma, &mby)) { /* fetch, nxm? */ PUTP32 (pkt, RW_WBCL, bc - i); /* adj bc */ PUTP32 (pkt, RW_WBAL, bc - i); /* adj ba */ if (rq_hbe (cp, uptr)) /* post err log */ @@ -1920,9 +2158,8 @@ else { /* Bottom End (After I/O processing) */ if (err != 0) { /* error? */ if (rq_dte (cp, uptr, ST_DRV)) /* post err log */ rq_rw_end (cp, uptr, EF_LOG, ST_DRV); /* if ok, report err */ - perror ("RQ I/O error"); - if (!(uptr->flags & UNIT_RAW)) - clearerr (uptr->fileref); + sim_disk_perror (uptr, "RQ I/O error"); + sim_disk_clearerr (uptr); return SCPE_IOERR; } ba = ba + tbc; /* incr bus addr */ @@ -1957,6 +2194,8 @@ cp->pak[pkt].d[RW_WBCL] = 0; cp->pak[pkt].d[RW_WBCH] = 0; cp->pak[pkt].d[RW_WBLL] = 0; cp->pak[pkt].d[RW_WBLH] = 0; +cp->pak[pkt].d[RW_WMPL] = 0; +cp->pak[pkt].d[RW_WMPH] = 0; rq_putr (cp, pkt, cmd | OP_END, flg, sts, RW_LNT_D, UQ_TYP_SEQ); /* fill pkt */ if (!rq_putpkt (cp, pkt, TRUE)) /* send pkt */ return ERR; @@ -1999,7 +2238,7 @@ cp->pak[pkt].d[DTE_CIDA] = 0; /* ctrl ID */ cp->pak[pkt].d[DTE_CIDB] = 0; cp->pak[pkt].d[DTE_CIDC] = 0; cp->pak[pkt].d[DTE_CIDD] = (RQ_CLASS << DTE_CIDD_V_CLS) | - (RQ_MODEL << DTE_CIDD_V_MOD); + (ctlr_tab[cp->ctype].model << DTE_CIDD_V_MOD); cp->pak[pkt].d[DTE_VER] = (RQ_HVER << DTE_VER_V_HVER) | (RQ_SVER << DTE_VER_V_SVER); cp->pak[pkt].d[DTE_MLUN] = lu; /* MLUN */ @@ -2041,7 +2280,7 @@ cp->pak[pkt].d[HBE_CIDA] = 0; /* ctrl ID */ cp->pak[pkt].d[HBE_CIDB] = 0; cp->pak[pkt].d[HBE_CIDC] = 0; cp->pak[pkt].d[HBE_CIDD] = (RQ_CLASS << DTE_CIDD_V_CLS) | - (RQ_MODEL << DTE_CIDD_V_MOD); + (ctlr_tab[cp->ctype].model << DTE_CIDD_V_MOD); cp->pak[pkt].d[HBE_VER] = (RQ_HVER << HBE_VER_V_HVER) | /* versions */ (RQ_SVER << HBE_VER_V_SVER); cp->pak[pkt].d[HBE_RSV] = 0; @@ -2069,7 +2308,7 @@ cp->pak[pkt].d[PLF_CIDA] = 0; /* cntl ID */ cp->pak[pkt].d[PLF_CIDB] = 0; cp->pak[pkt].d[PLF_CIDC] = 0; cp->pak[pkt].d[PLF_CIDD] = (RQ_CLASS << PLF_CIDD_V_CLS) | - (RQ_MODEL << PLF_CIDD_V_MOD); + (ctlr_tab[cp->ctype].model << PLF_CIDD_V_MOD); cp->pak[pkt].d[PLF_VER] = (RQ_SVER << PLF_VER_V_SVER) | (RQ_HVER << PLF_VER_V_HVER); cp->pak[pkt].d[PLF_ERR] = err; @@ -2480,6 +2719,27 @@ fprintf (st, "%s", drv_tab[GET_DTYPE (uptr->flags)].name); return SCPE_OK; } +/* Set controller type */ + +t_stat rq_set_ctype (UNIT *uptr, int32 val, char *cptr, void *desc) +{ +MSC *cp = rq_ctxmap[uptr->cnum]; + +if (val < 0) + return SCPE_ARG; +cp->ctype = val; +return SCPE_OK; +} + +/* Show controller type */ + +t_stat rq_show_ctype (FILE *st, UNIT *uptr, int32 val, void *desc) +{ +MSC *cp = rq_ctxmap[uptr->cnum]; +fprintf (st, "%s", ctlr_tab[cp->ctype].name); +return SCPE_OK; +} + /* Device attach */ t_stat rq_attach (UNIT *uptr, char *cptr) @@ -2529,6 +2789,8 @@ if (cidx < 0) /* not found??? */ return SCPE_IERR; cp = rq_ctxmap[cidx]; /* get context */ cp->cnum = cidx; /* init index */ +if (cp->ctype == DEFAULT_CTYPE) + cp->ctype = (UNIBUS? UDA50_CTYPE : RQDX3_CTYPE); #if defined (VM_VAX) /* VAX */ cp->ubase = 0; /* unit base = 0 */ @@ -2654,7 +2916,7 @@ static const uint16 boot_rom[] = { t_stat rq_boot (int32 unitno, DEVICE *dptr) { -int32 i; +size_t i; extern int32 saved_PC; extern uint16 *M; DIB *dibp = (DIB *) dptr->ctxt; diff --git a/PDP11/pdp11_rx.c b/PDP11/pdp11_rx.c index f4267b61..8d599578 100644 --- a/PDP11/pdp11_rx.c +++ b/PDP11/pdp11_rx.c @@ -140,9 +140,11 @@ void rx_done (int32 esr_flags, int32 new_ecode); rx_mod RX modifier list */ +#define IOLN_RX 004 + DIB rx_dib = { - IOBA_RX, IOLN_RX, &rx_rd, &rx_wr, - 1, IVCL (RX), VEC_RX, { NULL } + IOBA_AUTO, IOLN_RX, &rx_rd, &rx_wr, + 1, IVCL (RX), VEC_AUTO, { NULL } }; UNIT rx_unit[] = { @@ -200,7 +202,7 @@ DEVICE rx_dev = { RX_NUMDR, 8, 20, 1, 8, 8, NULL, NULL, &rx_reset, &rx_boot, NULL, NULL, - &rx_dib, DEV_FLTA | DEV_DISABLE | DEV_UBUS | DEV_QBUS + &rx_dib, DEV_DISABLE | DEV_UBUS | DEV_QBUS }; /* I/O dispatch routine, I/O addresses 17777170 - 17777172 @@ -522,7 +524,7 @@ static const uint16 boot_rom[] = { t_stat rx_boot (int32 unitno, DEVICE *dptr) { -int32 i; +size_t i; extern int32 saved_PC; extern uint16 *M; diff --git a/PDP11/pdp11_ry.c b/PDP11/pdp11_ry.c index a973e2e0..c98cdefe 100644 --- a/PDP11/pdp11_ry.c +++ b/PDP11/pdp11_ry.c @@ -173,9 +173,11 @@ t_stat ry_attach (UNIT *uptr, char *cptr); ry_mod RY modifier list */ +#define IOLN_RY 004 + DIB ry_dib = { - IOBA_RY, IOLN_RY, &ry_rd, &ry_wr, - 1, IVCL (RY), VEC_RY, { NULL } + IOBA_AUTO, IOLN_RY, &ry_rd, &ry_wr, + 1, IVCL (RY), VEC_AUTO, { NULL } }; UNIT ry_unit[] = { @@ -244,7 +246,7 @@ DEVICE ry_dev = { RX_NUMDR, DEV_RDX, 20, 1, DEV_RDX, 8, NULL, NULL, &ry_reset, &ry_boot, &ry_attach, NULL, - &ry_dib, DEV_FLTA | DEV_DISABLE | DEV_DISI | DEV_UBUS | DEV_Q18 + &ry_dib, DEV_DISABLE | DEV_DISI | DEV_UBUS | DEV_Q18 }; /* I/O dispatch routine, I/O addresses 17777170 - 17777172 @@ -577,7 +579,7 @@ else if (ry_unit[0].flags & UNIT_BUF) { /* attached? */ sim_activate (&ry_unit[0], ry_swait * abs (1 - ry_unit[0].TRACK)); } else ry_done (RYES_ID, 0010); /* no, error */ -return auto_config (0, 0); /* run autoconfig */ +return auto_config (dptr->name, 1); /* run autoconfig */ } /* Attach routine */ @@ -678,7 +680,7 @@ static const uint16 boot_rom[] = { t_stat ry_boot (int32 unitno, DEVICE *dptr) { -int32 i; +size_t i; extern int32 saved_PC; extern uint16 *M; diff --git a/PDP11/pdp11_stddev.c b/PDP11/pdp11_stddev.c index c20a0168..1bc6777f 100644 --- a/PDP11/pdp11_stddev.c +++ b/PDP11/pdp11_stddev.c @@ -61,6 +61,7 @@ */ #include "pdp11_defs.h" +#include "sim_tmxr.h" #define TTICSR_IMP (CSR_DONE + CSR_IE) /* terminal input */ #define TTICSR_RW (CSR_IE) @@ -199,9 +200,11 @@ DEVICE tto_dev = { clk_reg CLK register list */ +#define IOLN_CLK 002 + DIB clk_dib = { - IOBA_CLK, IOLN_CLK, &clk_rd, &clk_wr, - 1, IVCL (CLK), VEC_CLK, { &clk_inta } + IOBA_AUTO, IOLN_CLK, &clk_rd, &clk_wr, + 1, IVCL (CLK), VEC_AUTO, { &clk_inta } }; UNIT clk_unit = { UDATA (&clk_svc, UNIT_IDLE, 0), CLK_DELAY }; @@ -288,8 +291,7 @@ t_stat tti_svc (UNIT *uptr) { int32 c; -sim_activate (uptr, KBD_WAIT (uptr->wait, clk_cosched (tmr_poll))); - /* continue poll */ +sim_clock_coschedule (uptr, tmxr_poll); /* continue poll */ if ((c = sim_poll_kbd ()) < SCPE_KFLAG) /* no char or error? */ return c; if (c & SCPE_BREAK) /* break? */ @@ -306,6 +308,7 @@ return SCPE_OK; t_stat tti_reset (DEVICE *dptr) { +tmxr_set_console_units (&tti_unit, &tto_unit); tti_unit.buf = 0; tti_csr = 0; CLR_INT (TTI); @@ -456,16 +459,6 @@ if (CPUT (CPUT_24)) return clk_dib.vec; } -/* Clock coscheduling routine */ - -int32 clk_cosched (int32 wait) -{ -int32 t; - -t = sim_is_active (&clk_unit); -return (t? t - 1: wait); -} - /* Clock reset */ t_stat clk_reset (DEVICE *dptr) diff --git a/PDP11/pdp11_sys.c b/PDP11/pdp11_sys.c index c663095a..265b011c 100644 --- a/PDP11/pdp11_sys.c +++ b/PDP11/pdp11_sys.c @@ -1,6 +1,6 @@ /* pdp11_sys.c: PDP-11 simulator interface - Copyright (c) 1993-2008, Robert M Supnik + Copyright (c) 1993-2012, Robert M Supnik Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), @@ -23,6 +23,7 @@ used in advertising or otherwise to promote the sale, use or other dealings in this Software without prior written authorization from Robert M Supnik. + 29-Apr-12 RMS Fixed compiler warning (Mark Pizzolato) 19-Nov-08 RMS Moved I/O support routines to I/O library 15-May-08 RMS Added KE11-A, DC11 support Renamed DL11 @@ -101,6 +102,7 @@ extern DEVICE xq_dev, xqb_dev; extern DEVICE xu_dev, xub_dev; extern DEVICE ke_dev; extern DEVICE kg_dev; +extern DEVICE dmc_dev[]; extern UNIT cpu_unit; extern REG cpu_reg[]; extern uint16 *M; @@ -165,6 +167,10 @@ DEVICE *sim_devices[] = { &xub_dev, &ke_dev, &kg_dev, + &dmc_dev[0], + &dmc_dev[1], + &dmc_dev[2], + &dmc_dev[3], NULL }; diff --git a/PDP11/pdp11_ta.c b/PDP11/pdp11_ta.c index f777eff9..814d497f 100644 --- a/PDP11/pdp11_ta.c +++ b/PDP11/pdp11_ta.c @@ -106,7 +106,6 @@ #define UST_GAP 01 /* last op hit gap */ extern int32 int_req[IPL_HLVL]; -extern FILE *sim_deb; uint32 ta_cs = 0; /* control/status */ uint32 ta_idb = 0; /* input data buf */ @@ -145,9 +144,11 @@ uint32 ta_crc (uint8 *buf, uint32 cnt); ta_mod TA modifier list */ +#define IOLN_TA 004 + DIB ta_dib = { - IOBA_TA, IOLN_TA, &ta_rd, &ta_wr, - 1, IVCL (TA), VEC_TA, { NULL } + IOBA_AUTO, IOLN_TA, &ta_rd, &ta_wr, + 1, IVCL (TA), VEC_AUTO, { NULL } }; UNIT ta_unit[] = { @@ -197,7 +198,7 @@ DEVICE ta_dev = { TA_NUMDR, 10, 31, 1, 8, 8, NULL, NULL, &ta_reset, NULL, &ta_attach, &ta_detach, - &ta_dib, DEV_DISABLE | DEV_DIS | DEV_DEBUG + &ta_dib, DEV_DISABLE | DEV_DIS | DEV_DEBUG | DEV_TAPE }; /* I/O dispatch routines, I/O addresses 17777500 - 17777503 @@ -580,7 +581,7 @@ if (ta_xb == NULL) ta_xb = (uint8 *) calloc (TA_MAXFR + 2, sizeof (uint8)); if (ta_xb == NULL) return SCPE_MEM; -return SCPE_OK; +return auto_config (0, 0); } /* Attach routine */ diff --git a/PDP11/pdp11_tc.c b/PDP11/pdp11_tc.c index 1af3df29..d18f21b9 100644 --- a/PDP11/pdp11_tc.c +++ b/PDP11/pdp11_tc.c @@ -274,8 +274,6 @@ extern uint16 *M; /* memory */ extern int32 int_req[IPL_HLVL]; extern UNIT cpu_unit; -extern int32 sim_switches; -extern FILE *sim_deb; int32 tcst = 0; /* status */ int32 tccm = 0; /* command */ @@ -308,7 +306,6 @@ void dt_stopunit (UNIT *uptr); int32 dt_comobv (int32 val); int32 dt_csum (UNIT *uptr, int32 blk); int32 dt_gethdr (UNIT *uptr, int32 blk, int32 relpos); -extern int32 sim_is_running; /* DT data structures @@ -318,9 +315,11 @@ extern int32 sim_is_running; dt_mod DT modifier list */ +#define IOLN_TC 012 + DIB dt_dib = { - IOBA_TC, IOLN_TC, &dt_rd, &dt_wr, - 1, IVCL (DTA), VEC_DTA, { NULL } + IOBA_AUTO, IOLN_TC, &dt_rd, &dt_wr, + 1, IVCL (DTA), VEC_AUTO, { NULL } }; UNIT dt_unit[] = { @@ -749,7 +748,7 @@ t_bool dt_setpos (UNIT *uptr) { uint32 new_time, ut, ulin, udelt; int32 mot = DTS_GETMOT (uptr->STATE); -int32 unum, delta; +int32 unum, delta = 0; new_time = sim_grtime (); /* current time */ ut = new_time - uptr->LASTT; /* elapsed time */ @@ -1130,7 +1129,7 @@ for (i = 0; i < DT_NUMDR; i++) { /* stop all activity */ tcst = tcwc = tcba = tcdt = 0; /* clear reg */ tccm = CSR_DONE; CLR_INT (DTA); /* clear int req */ -return SCPE_OK; +return auto_config (0, 0); } /* Device bootstrap */ @@ -1183,7 +1182,7 @@ static const uint16 boot_rom[] = { t_stat dt_boot (int32 unitno, DEVICE *dptr) { -int32 i; +size_t i; extern int32 saved_PC; dt_unit[unitno].pos = DT_EZLIN; diff --git a/PDP11/pdp11_tm.c b/PDP11/pdp11_tm.c index e8430b17..c50b4aa4 100644 --- a/PDP11/pdp11_tm.c +++ b/PDP11/pdp11_tm.c @@ -154,7 +154,6 @@ extern uint16 *M; /* memory */ extern int32 int_req[IPL_HLVL]; -extern FILE *sim_deb; uint8 *tmxb = NULL; /* xfer buffer */ int32 tm_sta = 0; /* status register */ @@ -188,9 +187,11 @@ t_stat tm_vlock (UNIT *uptr, int32 val, char *cptr, void *desc); tm_mod MT modifier list */ +#define IOLN_TM 014 + DIB tm_dib = { - IOBA_TM, IOLN_TM, &tm_rd, &tm_wr, - 1, IVCL (TM), VEC_TM, { NULL } + IOBA_AUTO, IOLN_TM, &tm_rd, &tm_wr, + 1, IVCL (TM), VEC_AUTO, { NULL } }; UNIT tm_unit[] = { @@ -244,7 +245,7 @@ DEVICE tm_dev = { TM_NUMDR, 10, T_ADDR_W, 1, 8, 8, NULL, NULL, &tm_reset, &tm_boot, &tm_attach, &tm_detach, - &tm_dib, DEV_DISABLE | DEV_UBUS | DEV_Q18 | DEV_DEBUG + &tm_dib, DEV_DISABLE | DEV_UBUS | DEV_Q18 | DEV_DEBUG | DEV_TAPE }; /* I/O dispatch routines, I/O addresses 17772520 - 17772532 @@ -596,7 +597,7 @@ if (tmxb == NULL) tmxb = (uint8 *) calloc (MT_MAXFR, sizeof (uint8)); if (tmxb == NULL) return SCPE_MEM; -return SCPE_OK; +return auto_config (0, 0); } /* Attach routine */ @@ -711,9 +712,8 @@ static const uint16 boot2_rom[] = { t_stat tm_boot (int32 unitno, DEVICE *dptr) { -int32 i; +size_t i; extern int32 saved_PC; -extern int32 sim_switches; sim_tape_rewind (&tm_unit[unitno]); if (sim_switches & SWMASK ('O')) { diff --git a/PDP11/pdp11_tq.c b/PDP11/pdp11_tq.c index 95d76ba2..f6c6f886 100644 --- a/PDP11/pdp11_tq.c +++ b/PDP11/pdp11_tq.c @@ -246,8 +246,6 @@ static struct drvtyp drv_tab[] = { extern int32 int_req[IPL_HLVL]; extern int32 tmr_poll, clk_tps; -extern FILE *sim_deb; -extern uint32 sim_taddr_64; uint32 tq_sa = 0; /* status, addr */ uint32 tq_saw = 0; /* written data */ @@ -414,8 +412,10 @@ UNIT *tq_getucb (uint32 lu); tq_mod TQ modifier list */ +#define IOLN_TQ 004 + DIB tq_dib = { - IOBA_TQ, IOLN_TQ, &tq_rd, &tq_wr, + IOBA_AUTO, IOLN_TQ, &tq_rd, &tq_wr, 1, IVCL (TQ), 0, { &tq_inta } }; @@ -539,7 +539,7 @@ DEVICE tq_dev = { TQ_NUMDR + 2, 10, T_ADDR_W, 1, DEV_RDX, 8, NULL, NULL, &tq_reset, &tq_boot, &tq_attach, &tq_detach, - &tq_dib, DEV_DISABLE | DEV_UBUS | DEV_QBUS | DEV_DEBUG, + &tq_dib, DEV_DISABLE | DEV_UBUS | DEV_QBUS | DEV_DEBUG | DEV_TAPE, 0, tq_debug }; @@ -1691,7 +1691,7 @@ return tq_putpkt (pkt, TRUE); t_bool tq_plf (uint32 err) { -int32 pkt; +int32 pkt = 0; if (!tq_deqf (&pkt)) /* get log pkt */ return ERR; @@ -2202,7 +2202,7 @@ static const uint16 boot_rom[] = { t_stat tq_boot (int32 unitno, DEVICE *dptr) { -int32 i; +size_t i; extern int32 saved_PC; extern uint16 *M; diff --git a/PDP11/pdp11_ts.c b/PDP11/pdp11_ts.c index 5966a062..64e21326 100644 --- a/PDP11/pdp11_ts.c +++ b/PDP11/pdp11_ts.c @@ -268,7 +268,6 @@ extern uint32 cpu_opt; extern int32 int_req[IPL_HLVL]; extern UNIT cpu_unit; -extern FILE *sim_deb; uint8 *tsxb = NULL; /* xfer buffer */ int32 tssr = 0; /* status register */ @@ -306,9 +305,11 @@ int32 ts_map_status (t_stat st); ts_mod TS modifier list */ +#define IOLN_TS 004 + DIB ts_dib = { - IOBA_TS, IOLN_TS, &ts_rd, &ts_wr, - 1, IVCL (TS), VEC_TS, { NULL } + IOBA_AUTO, IOLN_TS, &ts_rd, &ts_wr, + 1, IVCL (TS), VEC_AUTO, { NULL } }; UNIT ts_unit = { UDATA (&ts_svc, UNIT_ATTABLE + UNIT_ROABLE + UNIT_DISABLE, 0) }; @@ -364,7 +365,7 @@ DEVICE ts_dev = { 1, 10, T_ADDR_W, 1, DEV_RDX, 8, NULL, NULL, &ts_reset, &ts_boot, &ts_attach, &ts_detach, - &ts_dib, DEV_DISABLE | TS_DIS | DEV_UBUS | DEV_QBUS | DEV_DEBUG + &ts_dib, DEV_DISABLE | TS_DIS | DEV_UBUS | DEV_QBUS | DEV_DEBUG | DEV_TAPE }; /* I/O dispatch routines, I/O addresses 17772520 - 17772522 @@ -1055,7 +1056,7 @@ if (tsxb == NULL) tsxb = (uint8 *) calloc (MT_MAXFR, sizeof (uint8)); if (tsxb == NULL) return SCPE_MEM; -return SCPE_OK; +return auto_config (0, 0); } /* Attach */ @@ -1150,7 +1151,7 @@ static const uint16 boot_rom[] = { t_stat ts_boot (int32 unitno, DEVICE *dptr) { -int32 i; +size_t i; extern int32 saved_PC; extern uint16 *M; diff --git a/PDP11/pdp11_tu.c b/PDP11/pdp11_tu.c index d0ced0a9..7bcbef8c 100644 --- a/PDP11/pdp11_tu.c +++ b/PDP11/pdp11_tu.c @@ -239,9 +239,6 @@ static char *tu_fname[CS1_N_FNC] = { "WRITE", "31", "32", "33", "READF", "35", "36" "READR" }; -extern int32 sim_switches; -extern FILE *sim_deb; - t_stat tu_mbrd (int32 *data, int32 PA, int32 fmtr); t_stat tu_mbwr (int32 data, int32 PA, int32 fmtr); t_stat tu_svc (UNIT *uptr); @@ -323,7 +320,7 @@ DEVICE tu_dev = { TU_NUMDR, 10, T_ADDR_W, 1, DEV_RDX, 8, NULL, NULL, &tu_reset, &tu_boot, &tu_attach, &tu_detach, - &tu_dib, DEV_MBUS|DEV_UBUS|DEV_QBUS|DEV_DEBUG|DEV_DISABLE|DEV_DIS_INIT|DEV_TM03 + &tu_dib, DEV_MBUS|DEV_UBUS|DEV_QBUS|DEV_DEBUG|DEV_DISABLE|DEV_DIS_INIT|DEV_TM03|DEV_TAPE }; /* Massbus register read */ @@ -793,7 +790,7 @@ if (DEBUG_PRS (tu_dev)) { fprintf (sim_deb, ">>TU%d DONE: fnc=%s, fc=%06o, fs=%06o, er=%06o, pos=", drv, tu_fname[fnc], tufc, tufs, tuer); fprint_val (sim_deb, uptr->pos, 10, T_ADDR_W, PV_LEFT); - fprintf (sim_deb, "\n"); + fprintf (sim_deb, ", r=%d\n", r); } return SCPE_OK; } @@ -822,7 +819,7 @@ return; void tu_update_fs (int32 flg, int32 drv) { -int32 act = sim_is_active (&tu_unit[drv]); +int32 act = sim_activate_time (&tu_unit[drv]); tufs = (tufs & ~FS_DYN) | FS_FPR | flg; if (tu_unit[drv].flags & UNIT_ATT) { @@ -933,7 +930,7 @@ if (wbuf == NULL) wbuf = (uint16 *) calloc ((MT_MAXFR + 4) >> 1, sizeof (uint16)); if (wbuf == NULL) return SCPE_MEM; -return SCPE_OK; +return auto_config(0, 0); } /* Attach routine */ @@ -1036,7 +1033,7 @@ static const uint16 boot_rom[] = { t_stat tu_boot (int32 unitno, DEVICE *dptr) { -int32 i; +size_t i; extern int32 saved_PC; extern uint16 *M; diff --git a/PDP11/pdp11_vh.c b/PDP11/pdp11_vh.c index dd8ef599..9a43c80b 100644 --- a/PDP11/pdp11_vh.c +++ b/PDP11/pdp11_vh.c @@ -34,6 +34,7 @@ of lines available to be 8, 16, 24, or 32. Fixed performance issue avoiding redundant polling 03-Jan-10 JAD Eliminate gcc warnings + 24-Nov-08 JDB Removed tmxr_send_buffered_data declaration (now in sim_tmxr.h) 19-Nov-08 RMS Revised for common TMXR show routines 18-Jun-07 RMS Added UNIT_IDLE flag 29-Oct-06 RMS Synced poll and clock @@ -94,7 +95,16 @@ extern int32 tmxr_poll, clk_tps; #endif #define VH_MNOMASK (VH_MUXES - 1) +#if defined(VM_VAX) +#if VEC_QBUS #define VH_LINES (8) +#else +#define VH_LINES (16) +#endif +#else +#define VH_LINES (UNIBUS?16:8) +#endif +#define VH_LINES_ALLOC 16 #define UNIT_V_MODEDHU (UNIT_V_UF + 0) #define UNIT_V_FASTDMA (UNIT_V_UF + 1) @@ -285,9 +295,9 @@ typedef struct { uint16 txchar; /* single character I/O */ } TMLX; -static TMLN vh_ldsc[VH_MUXES * VH_LINES] = { { 0 } }; -static TMXR vh_desc = { VH_MUXES * VH_LINES, 0, 0, vh_ldsc }; -static TMLX vh_parm[VH_MUXES * VH_LINES] = { { 0 } }; +static TMLN vh_ldsc[VH_MUXES * VH_LINES_ALLOC] = { { 0 } }; +static TMXR vh_desc = { VH_MUXES * VH_LINES_ALLOC, 0, 0, vh_ldsc }; +static TMLX vh_parm[VH_MUXES * VH_LINES_ALLOC] = { { 0 } }; /* debugging bitmaps */ #define DBG_REG 0x0001 /* trace read/write registers */ @@ -295,6 +305,8 @@ static TMLX vh_parm[VH_MUXES * VH_LINES] = { { 0 } }; #define DBG_TRC TMXR_DBG_TRC /* trace routine calls */ #define DBG_XMT TMXR_DBG_XMT /* display Transmitted Data */ #define DBG_RCV TMXR_DBG_RCV /* display Received Data */ +#define DBG_TRC TMXR_DBG_TRC /* display trace routine calls */ +#define DBG_ASY TMXR_DBG_ASY /* display Asynchronous Activities */ DEBTAB vh_debug[] = { {"REG", DBG_REG}, @@ -302,6 +314,8 @@ DEBTAB vh_debug[] = { {"TRC", DBG_TRC}, {"XMT", DBG_XMT}, {"RCV", DBG_RCV}, + {"TRC", DBG_TRC}, + {"ASY", DBG_ASY}, {0} }; @@ -321,23 +335,27 @@ static t_stat vh_show_rbuf (FILE *st, UNIT *uptr, int32 val, void *desc); static t_stat vh_show_txq (FILE *st, UNIT *uptr, int32 val, void *desc); static t_stat vh_putc (int32 vh, TMLX *lp, int32 chan, int32 data); static void doDMA (int32 vh, int32 chan); +static t_stat vh_setmode (UNIT *uptr, int32 val, char *cptr, void *desc); +static t_stat vh_show_vec (FILE *st, UNIT *uptr, int32 val, void *desc); static t_stat vh_setnl (UNIT *uptr, int32 val, char *cptr, void *desc); static t_stat vh_set_log (UNIT *uptr, int32 val, char *cptr, void *desc); static t_stat vh_set_nolog (UNIT *uptr, int32 val, char *cptr, void *desc); static t_stat vh_show_log (FILE *st, UNIT *uptr, int32 val, void *desc); - -int32 tmxr_send_buffered_data (TMLN *lp); +static t_stat vh_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr); +static t_stat vh_help_attach (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr); /* SIMH I/O Structures */ +#define IOLN_VH 020 + static DIB vh_dib = { - IOBA_VH, + IOBA_AUTO, IOLN_VH * VH_MUXES, &vh_rd, /* read */ &vh_wr, /* write */ 2, /* # of vectors */ IVCL (VHRX), - VEC_VHRX, + VEC_FLOAT, { &vh_rxinta, &vh_txinta } /* int. ack. routines */ }; @@ -354,8 +372,10 @@ static const REG vh_reg[] = { }; static const MTAB vh_mod[] = { - { UNIT_MODEDHU, 0, "DHV mode", "DHV", NULL }, - { UNIT_MODEDHU, UNIT_MODEDHU, "DHU mode", "DHU", NULL }, +#if !UNIBUS + { UNIT_MODEDHU, 0, "DHV mode", "DHV", &vh_setmode }, +#endif + { UNIT_MODEDHU, UNIT_MODEDHU, "DHU mode", "DHU", &vh_setmode }, { UNIT_FASTDMA, 0, NULL, "NORMAL", NULL }, { UNIT_FASTDMA, UNIT_FASTDMA, "fast DMA", "FASTDMA", NULL }, { UNIT_MODEM, 0, NULL, "NOMODEM", NULL }, @@ -364,8 +384,8 @@ static const MTAB vh_mod[] = { { UNIT_HANGUP, UNIT_HANGUP, "hangup", "HANGUP", NULL }, { MTAB_XTD|MTAB_VDV, 020, "ADDRESS", "ADDRESS", &set_addr, &show_addr, NULL }, - { MTAB_XTD|MTAB_VDV, VH_LINES, "VECTOR", "VECTOR", - &set_vec, &show_vec_mux, (void *) &vh_desc }, + { MTAB_XTD|MTAB_VDV, 0, "VECTOR", "VECTOR", + &set_vec, &vh_show_vec, (void *) &vh_desc }, { MTAB_XTD|MTAB_VDV, 0, NULL, "AUTOCONFIGURE", &set_addr_flt, NULL, NULL }, { MTAB_XTD|MTAB_VDV, 0, "LINES", "LINES", @@ -411,8 +431,13 @@ DEVICE vh_dev = { &vh_attach, /* attach routine */ &vh_detach, /* detach routine */ (void *)&vh_dib,/* context */ - DEV_FLTA | DEV_DISABLE | DEV_DIS |DEV_NET | DEV_QBUS | DEV_UBUS | DEV_DEBUG, /* flags */ - 0, vh_debug + DEV_DISABLE | DEV_DIS | DEV_QBUS | DEV_UBUS | DEV_DEBUG | DEV_MUX, /* flags */ + 0, vh_debug, /* debug control and debug flags */ + NULL, /* memory size routine */ + NULL, /* logical name */ + &vh_help, /* help routine */ + &vh_help_attach,/* attach_help routines */ + (void *)&vh_desc/* help context variable */ }; /* Register names for Debug tracing */ @@ -716,7 +741,7 @@ static void vh_getc ( int32 vh ) uint32 i, c; TMLX *lp; - for (i = 0; i < VH_LINES; i++) { + for (i = 0; i < (uint32)VH_LINES; i++) { lp = &vh_parm[(vh * VH_LINES) + i]; while ((c = tmxr_getc_ln (lp->tmln)) != 0) { if (c & SCPE_BREAK) { @@ -1307,14 +1332,15 @@ static t_stat vh_reset ( DEVICE *dptr ) { int32 i; + if (vh_desc.lines > VH_MUXES*VH_LINES) + vh_desc.lines = VH_MUXES*VH_LINES; for (i = 0; i < vh_desc.lines; i++) vh_parm[i].tmln = &vh_ldsc[i]; + vh_dev.numunits = (vh_desc.lines / VH_LINES); for (i = 0; i < vh_desc.lines/VH_LINES; i++) { -#if defined (VM_PDP11) /* if Unibus, force DHU mode */ if (UNIBUS) vh_unit[i].flags |= UNIT_MODEDHU; -#endif vh_clear (i, TRUE); } vh_rxi = vh_txi = 0; @@ -1338,6 +1364,13 @@ static t_stat vh_detach ( UNIT *uptr ) return (tmxr_detach (&vh_desc, uptr)); } +t_stat vh_show_vec (FILE *st, UNIT *uptr, int32 arg, void *desc) +{ +TMXR *mp = (TMXR *) desc; + +return show_vec (st, uptr, ((mp->lines * 2) / VH_LINES), desc); +} + static void vh_detail_line ( FILE *st, int32 vh, int32 chan ) @@ -1434,6 +1467,17 @@ vh_dev.numunits = (newln / VH_LINES); return auto_config (vh_dev.name, ndev); /* auto config */ } +/* SET DHU/DHV mode processor */ + +static t_stat vh_setmode (UNIT *uptr, int32 val, char *cptr, void *desc) +{ +if (cptr) + return SCPE_ARG; +if ((UNIBUS) && (val != UNIT_MODEDHU)) + return SCPE_ARG; +return SCPE_OK; +} + /* SET LOG processor */ static t_stat vh_set_log (UNIT *uptr, int32 val, char *cptr, void *desc) @@ -1482,3 +1526,64 @@ for (i = 0; i < vh_desc.lines; i++) { } return SCPE_OK; } + +static t_stat vh_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr) +{ +char *devtype = (UNIBUS) ? "DH11" : "DHQ11"; + +fprintf (st, "%s Terminal Multiplexer (%s)\n\n", devtype, dptr->name); +fprintf (st, "The %s is an %d-line terminal multiplexer for %s systems. Up to %d %s's\n", devtype, VH_LINES, (UNIBUS) ? "Unibus" : "Qbus", VH_MUXES, devtype); +fprintf (st, "are supported.\n\n"); +fprintf (st, "The %s is a programmable asynchronous terminal multiplexer. It has two\n", devtype); +fprintf (st, "programming modes: DHV11 and DHU11. The register sets are compatible with\n"); +fprintf (st, "these devices. For transmission, the %s can be used in either DMA or\n", devtype); +fprintf (st, "programmed I/O mode. For reception, there is a 256-entry FIFO for received\n"); +fprintf (st, "characters, dataset status changes, and diagnostic information, and a\n"); +fprintf (st, "programmable input interrupt timer (in DHU mode). The device supports\n"); +fprintf (st, "16-, 18-, and 22-bit addressing. The %s can be programmed to filter\n", devtype); +fprintf (st, "and/or handle XON/XOFF characters independently of the processor.\n"); +fprintf (st, "The %s supports programmable bit width (between 5 and 8) for the input\n", devtype); +fprintf (st, "and output of characters.\n\n"); +fprintf (st, "By default, the DHV11 mode is selected, though DHU11 mode is recommended\n"); +fprintf (st, "for applications that can support it. The %s controller may be adjusted\n", dptr->name); +fprintf (st, "on a per controller basis as follows:\n\n"); +fprintf (st, " sim> SET %sn DHU use the DHU programming mode\n", dptr->name); +fprintf (st, " sim> SET %sn DHV use the DHV programming mode\n\n", dptr->name); +fprintf (st, "DMA output is supported. In a real %s, DMA is not initiated immediately\n", devtype); +fprintf (st, "upon receipt of TX.DMA.START but is dependent upon some internal processes.\n"); +fprintf (st, "The %s controller mimics this behavior by default. It may be desirable to\n", dptr->name); +fprintf (st, "alter this and start immediately, though this may not be compatible with all\n"); +fprintf (st, "operating systems and diagnostics. You can change the behavior of the %s\n", dptr->name); +fprintf (st, "controller as follows:\n\n"); +fprintf (st, " sim> SET %sn NORMAL use normal DMA procedures\n", dptr->name); +fprintf (st, " sim> SET %sn FASTDMA set DMA to initiate immediately\n\n", dptr->name); +fprintf (st, "The number of lines (and therefore the number of %s devices\n", devtype); +fprintf (st, "simulated) can be changed with the command:\n\n"); +fprintf (st, " sim> SET %s LINES=n set line count to n\n\n", dptr->name); +fprintf (st, "The line count must be a multiple of %d, with a maximum of %d.\n\n", VH_LINES, VH_LINES*VH_MUXES); +fprintf (st, "Modem and auto-disconnect support may be set on an individual controller\n"); +fprintf (st, "basis. The SET MODEM command directs the controller to report modem status\n"); +fprintf (st, "changes to the computer. The SET HANGUP command turns on active disconnects\n"); +fprintf (st, "(disconnect session if computer clears Data Terminal Ready).\n\n"); +fprintf (st, " sim> SET %sn [NO]MODEM disable/enable modem control\n", dptr->name); +fprintf (st, " sim> SET %sn [NO]HANGUP disable/enable disconnect on DTR drop\n\n", dptr->name); +fprintf (st, "Once the %s devuce is attached and the simulator is running, the %s will\n", dptr->name, dptr->name); +fprintf (st, "listen for connections on the specified port. It assumes that the incoming\n"); +fprintf (st, "connections are Telnet connections. The connection remains open until\n"); +fprintf (st, "disconnected by the simulated program, the Telnet client, a SET %s DISCONNECT\n", dptr->name); +fprintf (st, "command, or a DETACH %s command.\n\n", dptr->name); +fprintf (st, "Other special %s commands:\n\n", dptr->name); +fprintf (st, " sim> SHOW %s CONNECTIONS show current connections\n", dptr->name); +fprintf (st, " sim> SHOW %s STATISTICS show statistics for active connections\n", dptr->name); +fprintf (st, " sim> SET %s DISCONNECT=linenumber disconnects the specified line.\n\n", dptr->name); +fprintf (st, "The %s does not support save and restore. All open connections are lost\n", devtype); +fprintf (st, "when the simulator shuts down or the %s is detached.\n", dptr->name); +return SCPE_OK; +} + +static t_stat vh_help_attach (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr) +{ +char *devtype = (UNIBUS) ? "DH11" : "DHQ11"; + +return tmxr_attach_help (st, dptr, uptr, flag, cptr); +} diff --git a/PDP11/pdp11_xq.c b/PDP11/pdp11_xq.c index 86c1ae28..4d50c87b 100644 --- a/PDP11/pdp11_xq.c +++ b/PDP11/pdp11_xq.c @@ -254,9 +254,6 @@ extern int32 tmxr_poll; extern int32 tmr_poll, clk_tps; -extern t_bool sim_idle_enab; -extern FILE* sim_deb; -extern FILE *sim_log; extern char* read_line (char *ptr, int32 size, FILE *stream); /* forward declarations */ @@ -278,6 +275,7 @@ t_stat xq_show_sanity (FILE* st, UNIT* uptr, int32 val, void* desc); t_stat xq_set_sanity (UNIT* uptr, int32 val, char* cptr, void* desc); t_stat xq_show_poll (FILE* st, UNIT* uptr, int32 val, void* desc); t_stat xq_set_poll (UNIT* uptr, int32 val, char* cptr, void* desc); +t_stat xq_show_leds (FILE* st, UNIT* uptr, int32 val, void* desc); t_stat xq_process_xbdl(CTLR* xq); t_stat xq_dispatch_xbdl(CTLR* xq); t_stat xq_process_turbo_rbdl(CTLR* xq); @@ -322,7 +320,10 @@ struct xq_device xqb = { }; /* SIMH device structures */ -DIB xqa_dib = { IOBA_XQ, IOLN_XQ, &xq_rd, &xq_wr, + +#define IOLN_XQ 020 + +DIB xqa_dib = { IOBA_AUTO, IOLN_XQ, &xq_rd, &xq_wr, 1, IVCL (XQ), 0, { &xq_int } }; UNIT xqa_unit[] = { @@ -378,7 +379,7 @@ REG xqa_reg[] = { { NULL }, }; -DIB xqb_dib = { IOBA_XQB, IOLN_XQB, &xq_rd, &xq_wr, +DIB xqb_dib = { IOBA_AUTO, IOLN_XQ, &xq_rd, &xq_wr, 1, IVCL (XQ), 0, { &xq_int } }; UNIT xqb_unit[] = { @@ -458,6 +459,8 @@ MTAB xq_mod[] = { #endif { MTAB_XTD | MTAB_VDV | MTAB_NMO, 0, "SANITY", "SANITY={ON|OFF}", &xq_set_sanity, &xq_show_sanity, NULL }, + { MTAB_XTD | MTAB_VDV , 0, "LEDS", "LEDS", + NULL, &xq_show_leds, NULL }, { 0 }, }; @@ -480,7 +483,7 @@ DEVICE xq_dev = { 2, XQ_RDX, 11, 1, XQ_RDX, 16, &xq_ex, &xq_dep, &xq_reset, NULL, &xq_attach, &xq_detach, - &xqa_dib, DEV_FLTA | DEV_DISABLE | DEV_QBUS | DEV_DEBUG, + &xqa_dib, DEV_DISABLE | DEV_QBUS | DEV_DEBUG | DEV_ETHER, 0, xq_debug }; @@ -489,7 +492,7 @@ DEVICE xqb_dev = { 2, XQ_RDX, 11, 1, XQ_RDX, 16, &xq_ex, &xq_dep, &xq_reset, NULL, &xq_attach, &xq_detach, - &xqb_dib, DEV_FLTA | DEV_DISABLE | DEV_DIS | DEV_QBUS | DEV_DEBUG, + &xqb_dib, DEV_DISABLE | DEV_DIS | DEV_QBUS | DEV_DEBUG | DEV_ETHER, 0, xq_debug }; @@ -514,19 +517,22 @@ const char* const xqt_xmit_regnames[] = { "IBAL", "IBAH", "ICR", "", "SRQR", "", "", "ARQR" }; -const char* const xq_csr_bits[] = { - "RE", "SR", "NI", "BD", "XL", "RL", "IE", "XI", - "IL", "EL", "SE", "RR", "OK", "CA", "PE", "RI" +BITFIELD xq_csr_bits[] = { + BIT(RE), BIT(SR), BIT(NI), BIT(BD), BIT(XL), BIT(RL), BIT(IE), BIT(XI), + BIT(IL), BIT(EL), BIT(SE), BIT(RR), BIT(OK), BIT(CA), BIT(PE), BIT(RI), + ENDBITS }; -const char* const xq_var_bits[] = { - "ID", "RR", "V0", "V1", "V2", "V3", "V4", "V5", - "V6", "V7", "S1", "S2", "S3", "RS", "OS", "MS" +BITFIELD xq_var_bits[] = { + BIT(ID), BIT(RR), BIT(V0), BIT(V1), BIT(V2), BIT(V3), BIT(V4), BIT(V5), + BIT(V6), BIT(V7), BIT(S1), BIT(S2), BIT(S3), BIT(RS), BIT(OS), BIT(MS), + ENDBITS }; -const char* const xq_srr_bits[] = { - "RS0", "RS1", "", "", "", "", "", "", - "", "TBL", "IME", "PAR", "NXM", "", "CHN", "FES" +BITFIELD xq_srr_bits[] = { + BIT(RS0), BIT(RS1), BITNC, BITNC, BITNC, BITNC, BITNC, BITNC, + BITNC, BIT(TBL), BIT(IME), BIT(PAR), BIT(NXM), BITNC, BIT(CHN), BIT(FES), + ENDBITS }; /* internal debugging routines */ @@ -822,6 +828,16 @@ t_stat xq_set_sanity (UNIT* uptr, int32 val, char* cptr, void* desc) return SCPE_OK; } +t_stat xq_show_leds (FILE* st, UNIT* uptr, int32 val, void* desc) +{ + CTLR* xq = xq_unit2ctlr(uptr); + + fprintf(st, "leds=(%s,%s,%s)", xq->var->setup.l1 ? "ON" : "OFF", + xq->var->setup.l2 ? "ON" : "OFF", + xq->var->setup.l3 ? "ON" : "OFF"); + return SCPE_OK; +} + /*============================================================================*/ t_stat xq_nxm_error(CTLR* xq) @@ -912,16 +928,16 @@ t_stat xq_rd(int32* data, int32 PA, int32 access) break; case 6: if (xq->var->mode != XQ_T_DELQA_PLUS) { - sim_debug_u16(DBG_VAR, xq->dev, xq_var_bits, xq->var->var, xq->var->var, 0); - sim_debug (DBG_VAR, xq->dev, ", vec = 0%o\n", (xq->var->var & XQ_VEC_IV)); + sim_debug_bits(DBG_VAR, xq->dev, xq_var_bits, xq->var->var, xq->var->var, 0); + sim_debug (DBG_VAR, xq->dev, ", vec = 0%o\n", (xq->var->var & XQ_VEC_IV)); *data = xq->var->var; } else { - sim_debug_u16(DBG_VAR, xq->dev, xq_srr_bits, xq->var->srr, xq->var->srr, 0); + sim_debug_bits(DBG_VAR, xq->dev, xq_srr_bits, xq->var->srr, xq->var->srr, 0); *data = xq->var->srr; } break; case 7: - sim_debug_u16(DBG_CSR, xq->dev, xq_csr_bits, xq->var->csr, xq->var->csr, 1); + sim_debug_bits(DBG_CSR, xq->dev, xq_csr_bits, xq->var->csr, xq->var->csr, 1); *data = xq->var->csr; break; } @@ -985,6 +1001,8 @@ t_stat xq_process_rbdl(CTLR* xq) item = &xq->var->ReadQ.item[xq->var->ReadQ.head]; rbl = item->packet.len; rbuf = item->packet.msg; + if (item->packet.oversize) + rbuf = item->packet.oversize; /* see if packet must be size-adjusted or is splitting */ if (item->packet.used) { @@ -992,8 +1010,11 @@ t_stat xq_process_rbdl(CTLR* xq) rbl -= used; rbuf = &item->packet.msg[used]; } else { - /* adjust runt packets */ - if (rbl < ETH_MIN_PACKET) { + /* there should be no need to adjust runt packets + the physical layer (sim_ether) won't deliver any short packets + via eth_read, so the only short packets which get here are loopback + packets sent by the host diagnostics */ + if ((item->type != 1) && (rbl < ETH_MIN_PACKET)) { xq->var->stats.runt += 1; sim_debug(DBG_WRN, xq->dev, "Runt detected, size = %d\n", rbl); /* pad runts with zeros up to minimum size - this allows "legal" (size - 60) @@ -1003,12 +1024,14 @@ t_stat xq_process_rbdl(CTLR* xq) }; /* adjust oversized packets */ - if (rbl > ETH_MAX_PACKET) { + if (rbl > ETH_FRAME_SIZE) { xq->var->stats.giant += 1; sim_debug(DBG_WRN, xq->dev, "Giant detected, size=%d\n", rbl); /* trim giants down to maximum size - no documentation on how to handle the data loss */ - item->packet.len = ETH_MAX_PACKET; - rbl = ETH_MAX_PACKET; + if (rbl > XQ_MAX_RCV_PACKET) { + item->packet.len = XQ_MAX_RCV_PACKET; + rbl = XQ_MAX_RCV_PACKET; + } }; }; @@ -1038,6 +1061,7 @@ t_stat xq_process_rbdl(CTLR* xq) case 2: /* normal packet */ rbl -= 60; /* keeps max packet size in 11 bits */ xq->var->rbdl_buf[4] = (rbl & 0x0700); /* high bits of rbl */ + xq->var->rbdl_buf[4] |= 0x00f8; /* set reserved bits to 1 */ break; } if (item->packet.used < item->packet.len) @@ -1048,12 +1072,16 @@ t_stat xq_process_rbdl(CTLR* xq) xq->var->rbdl_buf[4] |= 0x0001; /* set overflow bit */ xq->var->stats.dropped += xq->var->ReadQ.loss; xq->var->ReadQ.loss = 0; /* reset loss counter */ - } + } + if ((rbl + ((item->type == 2) ? 60 : 0)) > ETH_MAX_PACKET) + xq->var->rbdl_buf[4] |= 0x4000; /* set Error bit (LONG) */ /* update read status words*/ wstatus = Map_WriteW(xq->var->rbdl_ba + 8, 4, &xq->var->rbdl_buf[4]); if (wstatus) return xq_nxm_error(xq); + sim_debug(DBG_TRC, xq->dev, "xq_process_rdbl(bd=0x%X, addr=0x%X, size=0x%X, len=0x%X, st1=0x%04X, st2=0x%04X)\n", xq->var->rbdl_ba, address, b_length, rbl + ((item->type == 2) ? 60 : 0), xq->var->rbdl_buf[4], xq->var->rbdl_buf[5]); + /* remove packet from queue */ if (item->packet.used >= item->packet.len) ethq_remove(&xq->var->ReadQ); @@ -1072,7 +1100,6 @@ t_stat xq_process_rbdl(CTLR* xq) t_stat xq_process_mop(CTLR* xq) { uint32 address; - uint16 size; int32 wstatus; struct xq_meb* meb = (struct xq_meb*) &xq->var->write_buffer.msg[0200]; const struct xq_meb* limit = (struct xq_meb*) &xq->var->write_buffer.msg[0400]; @@ -1084,7 +1111,6 @@ t_stat xq_process_mop(CTLR* xq) while ((meb->type != 0) && (meb < limit)) { address = (meb->add_hi << 16) || (meb->add_mi << 8) || meb->add_lo; - size = (meb->siz_hi << 8) || meb->siz_lo; /* MOP stuff here - NOT YET FULLY IMPLEMENTED */ sim_debug (DBG_WRN, xq->dev, "Processing MEB type: %d\n", meb->type); @@ -1263,6 +1289,8 @@ t_stat xq_process_xbdl(CTLR* xq) /* clear write buffer */ xq->var->write_buffer.len = 0; + free (xq->var->write_buffer.oversize); + xq->var->write_buffer.oversize = NULL; /* process buffer descriptors until not valid */ while (1) { @@ -1297,9 +1325,12 @@ t_stat xq_process_xbdl(CTLR* xq) } /* add to transmit buffer, making sure it's not too big */ - if ((xq->var->write_buffer.len + b_length) > sizeof(xq->var->write_buffer.msg)) - b_length = (uint16)(sizeof(xq->var->write_buffer.msg) - xq->var->write_buffer.len); - rstatus = Map_ReadB(address, b_length, &xq->var->write_buffer.msg[xq->var->write_buffer.len]); + if ((xq->var->write_buffer.len + b_length) > sizeof(xq->var->write_buffer.msg)) { + xq->var->write_buffer.oversize = realloc (xq->var->write_buffer.oversize, xq->var->write_buffer.len + b_length); + if (xq->var->write_buffer.len <= sizeof(xq->var->write_buffer.msg)) + memcpy (xq->var->write_buffer.oversize, xq->var->write_buffer.msg, xq->var->write_buffer.len); + } + rstatus = Map_ReadB(address, b_length, xq->var->write_buffer.oversize ? &xq->var->write_buffer.oversize[xq->var->write_buffer.len] : &xq->var->write_buffer.msg[xq->var->write_buffer.len]); if (rstatus) return xq_nxm_error(xq); xq->var->write_buffer.len += b_length; @@ -1315,6 +1346,8 @@ t_stat xq_process_xbdl(CTLR* xq) } else { /* loopback */ /* put packet in read buffer */ ethq_insert (&xq->var->ReadQ, 1, &xq->var->write_buffer, 0); + if ((DBG_PCK & xq->dev->dctrl) && xq->var->etherface) + eth_packet_trace_ex(xq->var->etherface, xq->var->write_buffer.msg, xq->var->write_buffer.len, "xq-write-loopback", DBG_DAT & xq->dev->dctrl, DBG_PCK); } /* update write status */ @@ -1323,6 +1356,8 @@ t_stat xq_process_xbdl(CTLR* xq) /* clear write buffer */ xq->var->write_buffer.len = 0; + free (xq->var->write_buffer.oversize); + xq->var->write_buffer.oversize = NULL; /* reset sanity timer */ xq_reset_santmr(xq); @@ -1361,6 +1396,54 @@ t_stat xq_process_xbdl(CTLR* xq) } /* while */ } +void xq_show_debug_bdl(CTLR* xq, uint32 bdl_ba) +{ + uint16 bdl_buf[6]; + uint16 b_length, w_length; + uint32 address, initial_bdl_ba = bdl_ba; + int32 rstatus; + + sim_debug(DBG_TRC, xq->dev, " Descriptor list at: 0x%X\n", bdl_ba); + + while (1) { + + /* get the beginning of the buffer descriptor */ + rstatus = Map_ReadW (bdl_ba, 4, &bdl_buf[0]); + if (rstatus) return; + + /* invalid buffer? */ + if (~bdl_buf[1] & XQ_DSC_V) + break; + + /* get the rest of the buffer descriptor */ + rstatus = Map_ReadW (bdl_ba + 4, 8, &bdl_buf[2]); + if (rstatus) return; + + /* explicit chain buffer? */ + if (bdl_buf[1] & XQ_DSC_C) { + sim_debug(DBG_TRC, xq->dev, " descriptor=0x%X, flags=0x%04X, chain=0x%X\n", bdl_ba, bdl_buf[0], ((bdl_buf[1] & 0x3F) << 16) | bdl_buf[2]); + bdl_ba = ((bdl_buf[1] & 0x3F) << 16) | bdl_buf[2]; + if (initial_bdl_ba == bdl_ba) + break; + continue; + } + + /* get host memory address */ + address = ((bdl_buf[1] & 0x3F) << 16) | bdl_buf[2]; + + /* decode buffer length - two's complement (in words) */ + w_length = ~bdl_buf[3] + 1; + b_length = w_length * 2; + if (bdl_buf[1] & XQ_DSC_H) b_length -= 1; + if (bdl_buf[1] & XQ_DSC_L) b_length -= 1; + + sim_debug(DBG_TRC, xq->dev, " descriptor=0x%X, flags=0x%04X, bits=0x%04X, addr=0x%X, len=0x%X, st1=0x%04X, st2=0x%04X\n", + bdl_ba, bdl_buf[0], bdl_buf[1] & 0xFFC0, address, b_length, bdl_buf[4], bdl_buf[5]); + + bdl_ba += 12; + } +} + t_stat xq_dispatch_rbdl(CTLR* xq) { int i; @@ -1388,7 +1471,10 @@ t_stat xq_dispatch_rbdl(CTLR* xq) if (~xq->var->rbdl_buf[1] & XQ_DSC_V) { xq_csr_set_clr(xq, XQ_CSR_RL, 0); return SCPE_OK; - } + } + + /* When debugging, walk and display the buffer descriptor list */ + xq_show_debug_bdl(xq, xq->var->rbdl_ba); /* process any waiting packets in receive queue */ if (xq->var->ReadQ.count) @@ -1413,10 +1499,15 @@ t_stat xq_dispatch_xbdl(CTLR* xq) /* clear transmit buffer */ xq->var->write_buffer.len = 0; + free (xq->var->write_buffer.oversize); + xq->var->write_buffer.oversize = NULL; /* get base address of first transmit descriptor */ xq->var->xbdl_ba = ((xq->var->xbdl[1] & 0x3F) << 16) | (xq->var->xbdl[0] & ~01); + /* When debugging, walk and display the buffer descriptor list */ + xq_show_debug_bdl(xq, xq->var->xbdl_ba); + /* process xbdl */ status = xq_process_xbdl(xq); @@ -1475,8 +1566,8 @@ t_stat xq_process_turbo_rbdl(CTLR* xq) rbl -= used; rbuf = &item->packet.msg[used]; } else { - /* adjust runt packets */ - if (rbl < ETH_MIN_PACKET) { + /* adjust non loopback runt packets */ + if ((item->type != 1) && (rbl < ETH_MIN_PACKET)) { xq->var->stats.runt += 1; sim_debug(DBG_WRN, xq->dev, "Runt detected, size = %d\n", rbl); /* pad runts with zeros up to minimum size - this allows "legal" (size - 60) @@ -1540,8 +1631,9 @@ t_stat xq_process_turbo_rbdl(CTLR* xq) ethq_remove(&xq->var->ReadQ); } while (0 == (xq->var->rring[xq->var->rbindx].rmd3 & XQ_RMD3_OWN)); - if (xq->var->rring[xq->var->rbindx].rmd3 & XQ_RMD3_OWN) + if (xq->var->rring[xq->var->rbindx].rmd3 & XQ_RMD3_OWN) { sim_debug(DBG_WRN, xq->dev, "xq_process_turbo_rbdl() - receive ring full\n"); + } if (descriptors_consumed) /* Interrupt for Packet Reception Completion */ @@ -1564,6 +1656,8 @@ t_stat xq_process_turbo_xbdl(CTLR* xq) /* clear transmit buffer */ xq->var->write_buffer.len = 0; + free (xq->var->write_buffer.oversize); + xq->var->write_buffer.oversize = NULL; /* Process each descriptor in the transmit ring */ do { @@ -1587,10 +1681,13 @@ t_stat xq_process_turbo_xbdl(CTLR* xq) address = ((xq->var->xring[i].hadr & 0x3F ) << 16) | xq->var->xring[i].ladr; b_length = (xq->var->xring[i].tmd3 & XQ_TMD3_BCT); - /* add to transmit buffer, making sure it's not too big */ - if ((xq->var->write_buffer.len + b_length) > sizeof(xq->var->write_buffer.msg)) - b_length = (uint16)(sizeof(xq->var->write_buffer.msg) - xq->var->write_buffer.len); - status = Map_ReadB(address, b_length, &xq->var->write_buffer.msg[xq->var->write_buffer.len]); + /* add to transmit buffer, accomodating it if it is too big */ + if ((xq->var->write_buffer.len + b_length) > sizeof(xq->var->write_buffer.msg)) { + xq->var->write_buffer.oversize = realloc (xq->var->write_buffer.oversize, xq->var->write_buffer.len + b_length); + if (xq->var->write_buffer.len <= sizeof(xq->var->write_buffer.msg)) + memcpy (xq->var->write_buffer.oversize, xq->var->write_buffer.msg, xq->var->write_buffer.len); + } + status = Map_ReadB(address, b_length, xq->var->write_buffer.oversize ? &xq->var->write_buffer.oversize[xq->var->write_buffer.len] : &xq->var->write_buffer.msg[xq->var->write_buffer.len]); if (status != SCPE_OK) return xq_nxm_error(xq); @@ -1895,7 +1992,7 @@ t_stat xq_wr_var(CTLR* xq, int32 data) else xq->dib->vec = 0; - sim_debug_u16(DBG_VAR, xq->dev, xq_var_bits, save_var, xq->var->var, 1); + sim_debug_bits(DBG_VAR, xq->dev, xq_var_bits, save_var, xq->var->var, 1); return SCPE_OK; } @@ -1920,7 +2017,8 @@ t_stat xq_process_bootrom (CTLR* xq) uint16 b_length, w_length; uint32 address; uint8* bootrom = (uint8*) xq_bootrom; - int i, checksum; + size_t i; + int checksum; sim_debug(DBG_TRC, xq->dev, "xq_process_bootrom()\n"); @@ -2086,6 +2184,11 @@ t_stat xq_process_bootrom (CTLR* xq) /* reset sanity timer */ xq_reset_santmr(xq); + /* Turn on all 3 DEQNA Leds */ + xq->var->setup.l1 = 1; + xq->var->setup.l2 = 1; + xq->var->setup.l3 = 1; + return SCPE_OK; } #endif /* ifdef VM_PDP11 */ @@ -2394,6 +2497,13 @@ t_stat xq_reset(DEVICE* dptr) xq->var->sanity.quarter_secs = XQ_HW_SANITY_SECS * 4/*qsec*/; } + if (sim_switches & SWMASK ('P')) { /* Powerup? */ + /* Turn on all 3 DEQNA Leds */ + xq->var->setup.l1 = 1; + xq->var->setup.l2 = 1; + xq->var->setup.l3 = 1; + } + return auto_config (0, 0); /* run autoconfig */ } @@ -2544,7 +2654,7 @@ t_stat xq_tmrsvc(UNIT* uptr) /* has sanity timer expired? if so, reboot */ if (xq->var->sanity.enabled) - if (--xq->var->sanity.timer <= 0) + if (--xq->var->sanity.timer <= 0) { if (xq->var->mode != XQ_T_DELQA_PLUS) return xq_boot_host(xq); else { /* DELQA-T Host Inactivity Timer expiration means switch out of DELQA-T mode */ @@ -2553,6 +2663,7 @@ t_stat xq_tmrsvc(UNIT* uptr) xq->var->iba = xq->var->srr = 0; xq->var->var = XQ_VEC_MS | XQ_VEC_OS; } + } /* has system id timer expired? if so, do system id */ if (--xq->var->idtmr <= 0) { @@ -2741,7 +2852,7 @@ void xq_csr_set_clr (CTLR* xq, uint16 set_bits, uint16 clear_bits) /* set the bits in the csr */ xq->var->csr = (xq->var->csr | set_bits) & ~clear_bits; - sim_debug_u16(DBG_CSR, xq->dev, xq_csr_bits, saved_csr, xq->var->csr, 1); + sim_debug_bits(DBG_CSR, xq->dev, xq_csr_bits, saved_csr, xq->var->csr, 1); /* check and correct the state of controller interrupt */ @@ -2794,8 +2905,9 @@ void xq_debug_setup(CTLR* xq) if (!(sim_deb && (xq->dev->dctrl & DBG_SET))) return; - if (xq->var->write_buffer.msg[0]) + if (xq->var->write_buffer.msg[0]) { sim_debug(DBG_SET, xq->dev, "%s: setup> MOP info present!\n", xq->dev->name); + } for (i = 0; i < XQ_FILTER_MAX; i++) { eth_mac_fmt(&xq->var->setup.macs[i], buffer); diff --git a/PDP11/pdp11_xq.h b/PDP11/pdp11_xq.h index b71a725e..4f76ee75 100644 --- a/PDP11/pdp11_xq.h +++ b/PDP11/pdp11_xq.h @@ -96,6 +96,8 @@ extern int32 int_req[IPL_HLVL]; #define XQ_HW_SANITY_SECS 240 /* seconds before HW sanity timer expires */ #define XQ_MAX_CONTROLLERS 2 /* maximum controllers allowed */ +#define XQ_MAX_RCV_PACKET 1600 /* Maximum receive packet data */ + enum xq_type {XQ_T_DEQNA, XQ_T_DELQA, XQ_T_DELQA_PLUS}; struct xq_sanity { diff --git a/PDP11/pdp11_xu.c b/PDP11/pdp11_xu.c index 8ef1cd7b..0a422e21 100644 --- a/PDP11/pdp11_xu.c +++ b/PDP11/pdp11_xu.c @@ -129,8 +129,10 @@ void xu_dump_rxring(CTLR* xu); void xu_dump_txring(CTLR* xu); t_stat xu_show_filters (FILE* st, UNIT* uptr, int32 val, void* desc); -DIB xua_dib = { IOBA_XU, IOLN_XU, &xu_rd, &xu_wr, -1, IVCL (XU), VEC_XU, {&xu_int} }; +#define IOLN_XU 010 + +DIB xua_dib = { IOBA_AUTO, IOLN_XU, &xu_rd, &xu_wr, +1, IVCL (XU), VEC_AUTO, {&xu_int} }; UNIT xua_unit[] = { { UDATA (&xu_svc, UNIT_IDLE|UNIT_ATTABLE|UNIT_DISABLE, 0) }, /* receive timer */ @@ -190,15 +192,13 @@ DEVICE xu_dev = { 2, XU_RDX, 8, 1, XU_RDX, 8, &xu_ex, &xu_dep, &xu_reset, NULL, &xu_attach, &xu_detach, - &xua_dib, DEV_FLTA | DEV_DISABLE | DEV_DIS | DEV_UBUS | DEV_DEBUG, + &xua_dib, DEV_DISABLE | DEV_DIS | DEV_UBUS | DEV_DEBUG | DEV_ETHER, 0, xu_debug }; +#define IOLN_XU 010 -/* XUB does not exist in the PDP10 simulation */ -#if defined(IOBA_XUB) - -DIB xub_dib = { IOBA_XUB, IOLN_XUB, &xu_rd, &xu_wr, +DIB xub_dib = { IOBA_AUTO, IOLN_XU, &xu_rd, &xu_wr, 1, IVCL (XU), 0, { &xu_int } }; UNIT xub_unit[] = { @@ -220,7 +220,7 @@ DEVICE xub_dev = { 1, XU_RDX, 8, 1, XU_RDX, 8, &xu_ex, &xu_dep, &xu_reset, NULL, &xu_attach, &xu_detach, - &xub_dib, DEV_FLTA | DEV_DISABLE | DEV_DIS | DEV_UBUS | DEV_DEBUG, + &xub_dib, DEV_DISABLE | DEV_DIS | DEV_UBUS | DEV_DEBUG | DEV_ETHER, 0, xu_debug }; @@ -229,12 +229,6 @@ CTLR xu_ctrl[] = { {&xu_dev, xua_unit, &xua_dib, &xua} /* XUA controller */ ,{&xub_dev, xub_unit, &xub_dib, &xub} /* XUB controller */ }; -#else /* IOBA_XUB */ -#define XU_MAX_CONTROLLERS 1 -CTLR xu_ctrl[] = { - {&xu_dev, xua_unit, &xua_dib, &xua} /* XUA controller */ -}; -#endif /* IOBA_XUB */ /*============================================================================*/ @@ -578,7 +572,7 @@ t_stat xu_svc(UNIT* uptr) switch (xu->var->pcsr1 & PCSR1_STATE) { case STATE_READY: case STATE_RUNNING: - sim_activate(&xu->unit[0], clk_cosched(tmxr_poll)); + sim_clock_coschedule (&xu->unit[0], tmxr_poll); break; }; @@ -674,18 +668,16 @@ t_stat xu_sw_reset (CTLR* xu) for (i=0; i<6; i++) xu->var->setup.macs[1][i] = 0xff; /* Broadcast Address */ xu->var->setup.mac_count = 2; - if (xu->var->etherface) + if (xu->var->etherface) { eth_filter (xu->var->etherface, xu->var->setup.mac_count, xu->var->setup.macs, xu->var->setup.multicast, xu->var->setup.promiscuous); - /* activate device if not disabled */ - if ((xu->dev->flags & DEV_DIS) == 0) { - sim_activate_abs(&xu->unit[0], clk_cosched (tmxr_poll)); + /* activate device */ + sim_clock_coschedule (&xu->unit[0], tmxr_poll); /* start service timer */ - if (xu->var->etherface) - sim_activate_abs(&xu->unit[1], tmr_poll * clk_tps); + sim_activate_abs(&xu->unit[1], tmr_poll * clk_tps); } /* clear load_server address */ @@ -1033,7 +1025,7 @@ int32 xu_command(CTLR* xu) void xu_process_receive(CTLR* xu) { uint32 segb, ba; - int slen, wlen, off; + int slen, wlen, off = 0; t_stat rstatus, wstatus; ETH_ITEM* item = 0; int state = xu->var->pcsr1 & PCSR1_STATE; @@ -1215,6 +1207,7 @@ void xu_process_transmit(CTLR* xu) sim_debug(DBG_TRC, xu->dev, "xu_process_transmit()\n"); /* xu_dump_txring(xu); *//* debug receive ring */ + off = giant = runt = 0; for (;;) { /* get next transmit buffer */ @@ -1481,8 +1474,9 @@ t_stat xu_rd(int32 *data, int32 PA, int32 access) break; } sim_debug(DBG_REG, xu->dev, "xu_rd(), PCSR%d, data=%04x\n", reg, *data); - if (PA & 1) + if (PA & 1) { sim_debug(DBG_WRN, xu->dev, "xu_rd(), Unexpected Odd address access of PCSR%d\n", reg); + } return SCPE_OK; } @@ -1622,6 +1616,8 @@ t_stat xu_detach(UNIT* uptr) sim_debug(DBG_TRC, xu->dev, "xu_detach()\n"); if (uptr->flags & UNIT_ATT) { + sim_cancel (uptr); /* stop the receiver */ + sim_cancel (uptr+1); /* stop the timer services */ eth_close (xu->var->etherface); free(xu->var->etherface); xu->var->etherface = 0; @@ -1684,7 +1680,8 @@ void xu_dump_rxring (CTLR* xu) int own = (rxhdr[2] & RXR_OWN) >> 15; int len = rxhdr[0]; uint32 addr = rxhdr[1] + ((rxhdr[2] & 3) << 16); - printf (" header[%d]: own:%d, len:%d, address:%08x data:{%04x,%04x,%04x,%04x}\n", i, own, len, addr, rxhdr[0], rxhdr[1], rxhdr[2], rxhdr[3]); + if (rstatus == 0) + printf (" header[%d]: own:%d, len:%d, address:%08x data:{%04x,%04x,%04x,%04x}\n", i, own, len, addr, rxhdr[0], rxhdr[1], rxhdr[2], rxhdr[3]); } } @@ -1700,6 +1697,7 @@ void xu_dump_txring (CTLR* xu) int own = (txhdr[2] & RXR_OWN) >> 15; int len = txhdr[0]; uint32 addr = txhdr[1] + ((txhdr[2] & 3) << 16); - printf (" header[%d]: own:%d, len:%d, address:%08x data:{%04x,%04x,%04x,%04x}\n", i, own, len, addr, txhdr[0], txhdr[1], txhdr[2], txhdr[3]); + if (tstatus == 0) + printf (" header[%d]: own:%d, len:%d, address:%08x data:{%04x,%04x,%04x,%04x}\n", i, own, len, addr, txhdr[0], txhdr[1], txhdr[2], txhdr[3]); } } diff --git a/PDP18B/pdp18b_cpu.c b/PDP18B/pdp18b_cpu.c index 7bf7ab28..20bcc2f2 100644 --- a/PDP18B/pdp18b_cpu.c +++ b/PDP18B/pdp18b_cpu.c @@ -379,13 +379,6 @@ int32 hst_p = 0; /* history pointer */ int32 hst_lnt = 0; /* history length */ InstHistory *hst = NULL; /* instruction history */ -extern int32 sim_int_char; -extern int32 sim_interval; -extern uint32 sim_brk_types, sim_brk_dflt, sim_brk_summ; /* breakpoint info */ -extern t_bool sim_idle_enab; -extern DEVICE *sim_devices[]; -extern FILE *sim_log; - t_bool build_dev_tab (void); t_stat cpu_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw); t_stat cpu_dep (t_value val, t_addr addr, UNIT *uptr, int32 sw); @@ -2321,8 +2314,6 @@ char *cptr = (char *) desc; t_value sim_eval[2]; t_stat r; InstHistory *h; -extern t_stat fprint_sym (FILE *ofile, t_addr addr, t_value *val, - UNIT *uptr, int32 sw); if (hst_lnt == 0) /* enabled? */ return SCPE_NOFNC; diff --git a/PDP18B/pdp18b_defs.h b/PDP18B/pdp18b_defs.h index 9a997886..16388e1b 100644 --- a/PDP18B/pdp18b_defs.h +++ b/PDP18B/pdp18b_defs.h @@ -496,6 +496,4 @@ typedef struct { t_stat set_devno (UNIT *uptr, int32 val, char *cptr, void *desc); t_stat show_devno (FILE *st, UNIT *uptr, int32 val, void *desc); -int32 clk_cosched (int32 wait); - #endif diff --git a/PDP18B/pdp18b_drm.c b/PDP18B/pdp18b_drm.c index c65990b1..4141e465 100644 --- a/PDP18B/pdp18b_drm.c +++ b/PDP18B/pdp18b_drm.c @@ -244,7 +244,7 @@ static const int32 boot_rom[] = { t_stat drm_boot (int32 unitno, DEVICE *dptr) { -int32 i; +size_t i; extern int32 PC; if (drm_dib.dev != DEV_DRM) /* non-std addr? */ diff --git a/PDP18B/pdp18b_dt.c b/PDP18B/pdp18b_dt.c index 6b78f81b..ea9462fd 100644 --- a/PDP18B/pdp18b_dt.c +++ b/PDP18B/pdp18b_dt.c @@ -327,9 +327,6 @@ extern int32 M[]; extern int32 int_hwre[API_HLVL+1]; extern UNIT cpu_unit; -extern int32 sim_switches; -extern int32 sim_is_running; -extern FILE *sim_deb; int32 dtsa = 0; /* status A */ int32 dtsb = 0; /* status B */ diff --git a/PDP18B/pdp18b_mt.c b/PDP18B/pdp18b_mt.c index db4d598f..7f552741 100644 --- a/PDP18B/pdp18b_mt.c +++ b/PDP18B/pdp18b_mt.c @@ -127,7 +127,6 @@ extern int32 M[]; extern int32 int_hwre[API_HLVL+1]; extern UNIT cpu_unit; -extern FILE *sim_deb; int32 mt_cu = 0; /* command/unit */ int32 mt_sta = 0; /* status register */ @@ -199,7 +198,7 @@ DEVICE mt_dev = { MT_NUMDR, 10, 31, 1, 8, 8, NULL, NULL, &mt_reset, NULL, &mt_attach, &mt_detach, - &mt_dib, DEV_DISABLE | DEV_DEBUG + &mt_dib, DEV_DISABLE | DEV_DEBUG | DEV_TAPE }; /* IOT routine */ diff --git a/PDP18B/pdp18b_stddev.c b/PDP18B/pdp18b_stddev.c index 78cfeba3..15019a49 100644 --- a/PDP18B/pdp18b_stddev.c +++ b/PDP18B/pdp18b_stddev.c @@ -74,6 +74,7 @@ */ #include "pdp18b_defs.h" +#include "sim_tmxr.h" #include #define UNIT_V_RASCII (UNIT_V_UF + 0) /* reader ASCII */ @@ -85,8 +86,6 @@ extern int32 M[]; extern int32 int_hwre[API_HLVL+1], PC, ASW; -extern int32 sim_switches; -extern int32 sim_is_running; extern UNIT cpu_unit; int32 clk_state = 0; @@ -453,7 +452,6 @@ int32 clk_task_upd (t_bool clr) { uint32 delta, val, iusec10; uint32 cur = sim_grtime (); -uint32 old = clk_task_timer; double usec10; if (cur > clk_task_last) @@ -479,16 +477,6 @@ int32 clk_iors (void) return (TST_INT (CLK)? IOS_CLK: 0); } -/* Clock coscheduling routine */ - -int32 clk_cosched (int32 wait) -{ -int32 t; - -t = sim_is_active (&clk_unit); -return (t? t - 1: wait); -} - /* Reset routine */ t_stat clk_reset (DEVICE *dptr) @@ -861,8 +849,8 @@ static const int32 boot_rom[] = { t_stat ptr_boot (int32 unitno, DEVICE *dptr) { -int32 i, mask, wd; -extern int32 sim_switches; +size_t i; +int32 mask, wd; #if defined (PDP7) if (sim_switches & SWMASK ('H')) /* hardware RIM load? */ @@ -994,7 +982,7 @@ if (pulse & 001) { /* KSF */ } if (pulse & 002) { /* KRS/KRB */ CLR_INT (TTI); /* clear flag */ - dat = dat | tti_unit.buf & TTI_MASK; /* return buffer */ + dat = dat | (tti_unit.buf & TTI_MASK); /* return buffer */ #if defined (PDP15) if (pulse & 020) /* KRS? */ tti_fdpx = 1; @@ -1014,8 +1002,7 @@ t_stat tti_svc (UNIT *uptr) #if defined (KSR28) /* Baudot... */ int32 in, c, out; -sim_activate (uptr, KBD_WAIT (uptr->wait, clk_cosched (tmxr_poll))); - /* continue poll */ +sim_clock_coschedule (uptr, tmxr_poll); /* continue poll */ if (tti_2nd) { /* char waiting? */ uptr->buf = tti_2nd; /* return char */ tti_2nd = 0; /* not waiting */ @@ -1050,8 +1037,7 @@ else { #else /* ASCII... */ int32 c, out; -sim_activate (uptr, KBD_WAIT (uptr->wait, clk_cosched (tmxr_poll))); - /* continue poll */ +sim_clock_coschedule (uptr, tmxr_poll); /* continue poll */ if ((c = sim_poll_kbd ()) < SCPE_KFLAG) /* no char or error? */ return c; out = c & 0177; /* mask echo to 7b */ @@ -1082,6 +1068,7 @@ return (TST_INT (TTI)? IOS_TTI: 0); t_stat tti_reset (DEVICE *dptr) { +tmxr_set_console_units (&tti_unit, &tto_unit); CLR_INT (TTI); /* clear flag */ if (!sim_is_running) { /* RESET (not CAF)? */ tti_unit.buf = 0; /* clear buffer */ diff --git a/PDP18B/pdp18b_sys.c b/PDP18B/pdp18b_sys.c index 86bedcf5..239af0a0 100644 --- a/PDP18B/pdp18b_sys.c +++ b/PDP18B/pdp18b_sys.c @@ -345,8 +345,6 @@ return SCPE_OK; t_stat sim_load (FILE *fileref, char *cptr, char *fnam, int flag) { -extern int32 sim_switches; - if (flag != 0) return SCPE_NOFNC; if (sim_switches & SWMASK ('S')) /* RIM format? */ diff --git a/PDP18B/pdp18b_tt1.c b/PDP18B/pdp18b_tt1.c index d29bde0e..815002f3 100644 --- a/PDP18B/pdp18b_tt1.c +++ b/PDP18B/pdp18b_tt1.c @@ -57,7 +57,7 @@ uint32 ttix_done = 0; /* input flags */ uint32 ttox_done = 0; /* output flags */ uint8 ttix_buf[TTX_MAXL] = { 0 }; /* input buffers */ uint8 ttox_buf[TTX_MAXL] = { 0 }; /* output buffers */ -TMLN ttx_ldsc[TTX_MAXL] = { 0 }; /* line descriptors */ +TMLN ttx_ldsc[TTX_MAXL] = { {0} }; /* line descriptors */ TMXR ttx_desc = { 1, 0, 0, ttx_ldsc }; /* mux descriptor */ #define ttx_lines ttx_desc.lines /* current number of lines */ @@ -128,7 +128,7 @@ DEVICE tti1_dev = { 1, 10, 31, 1, 8, 8, &tmxr_ex, &tmxr_dep, &ttx_reset, NULL, &ttx_attach, &ttx_detach, - &ttix_dib, DEV_NET | DEV_DISABLE + &ttix_dib, DEV_MUX | DEV_DISABLE }; /* TTOx data structures @@ -215,7 +215,7 @@ int32 ln, c, temp; if ((uptr->flags & UNIT_ATT) == 0) /* attached? */ return SCPE_OK; -sim_activate (uptr, clk_cosched (tmxr_poll)); /* continue poll */ +sim_clock_coschedule (uptr, tmxr_poll); /* continue poll */ ln = tmxr_poll_conn (&ttx_desc); /* look for connect */ if (ln >= 0) /* got one? rcv enab */ ttx_ldsc[ln].rcve = 1; diff --git a/PDP8/pdp8_clk.c b/PDP8/pdp8_clk.c index 968ac229..327d6f80 100644 --- a/PDP8/pdp8_clk.c +++ b/PDP8/pdp8_clk.c @@ -44,8 +44,6 @@ extern int32 int_req, int_enable, dev_done, stop_inst; int32 clk_tps = 60; /* ticks/second */ int32 tmxr_poll = 16000; /* term mux poll */ -extern int32 sim_is_running; - int32 clk (int32 IR, int32 AC); t_stat clk_svc (UNIT *uptr); t_stat clk_reset (DEVICE *dptr); @@ -153,16 +151,6 @@ tmxr_poll = t; /* set mux poll */ return SCPE_OK; } -/* Clock coscheduling routine */ - -int32 clk_cosched (int32 wait) -{ -int32 t; - -t = sim_is_active (&clk_unit); -return (t? t - 1: wait); -} - /* Reset routine */ t_stat clk_reset (DEVICE *dptr) diff --git a/PDP8/pdp8_cpu.c b/PDP8/pdp8_cpu.c index 98ad5846..4a561109 100644 --- a/PDP8/pdp8_cpu.c +++ b/PDP8/pdp8_cpu.c @@ -240,13 +240,6 @@ int32 hst_p = 0; /* history pointer */ int32 hst_lnt = 0; /* history length */ InstHistory *hst = NULL; /* instruction history */ -extern int32 sim_interval; -extern int32 sim_int_char; -extern uint32 sim_brk_types, sim_brk_dflt, sim_brk_summ; /* breakpoint info */ -extern DEVICE *sim_devices[]; -extern FILE *sim_log; -extern t_bool sim_idle_enab; - t_stat cpu_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw); t_stat cpu_dep (t_value val, t_addr addr, UNIT *uptr, int32 sw); t_stat cpu_reset (DEVICE *dptr); @@ -1543,8 +1536,6 @@ char *cptr = (char *) desc; t_stat r; t_value sim_eval; InstHistory *h; -extern t_stat fprint_sym (FILE *ofile, t_addr addr, t_value *val, - UNIT *uptr, int32 sw); if (hst_lnt == 0) /* enabled? */ return SCPE_NOFNC; diff --git a/PDP8/pdp8_ct.c b/PDP8/pdp8_ct.c index 31ac1e75..45289576 100644 --- a/PDP8/pdp8_ct.c +++ b/PDP8/pdp8_ct.c @@ -138,7 +138,6 @@ extern int32 int_req, stop_inst; extern UNIT cpu_unit; -extern FILE *sim_deb; uint32 ct_sra = 0; /* status reg A */ uint32 ct_srb = 0; /* status reg B */ @@ -226,7 +225,7 @@ DEVICE ct_dev = { CT_NUMDR, 10, 31, 1, 8, 8, NULL, NULL, &ct_reset, &ct_boot, &ct_attach, &ct_detach, - &ct_dib, DEV_DISABLE | DEV_DIS | DEV_DEBUG + &ct_dib, DEV_DISABLE | DEV_DIS | DEV_DEBUG | DEV_TAPE }; /* IOT routines */ diff --git a/PDP8/pdp8_defs.h b/PDP8/pdp8_defs.h index 5d2ee547..73bbf844 100644 --- a/PDP8/pdp8_defs.h +++ b/PDP8/pdp8_defs.h @@ -210,6 +210,4 @@ typedef struct { t_stat set_dev (UNIT *uptr, int32 val, char *cptr, void *desc); t_stat show_dev (FILE *st, UNIT *uptr, int32 val, void *desc); -int32 clk_cosched (int32 wait); - #endif diff --git a/PDP8/pdp8_df.c b/PDP8/pdp8_df.c index a802e6e0..7acd6541 100644 --- a/PDP8/pdp8_df.c +++ b/PDP8/pdp8_df.c @@ -334,8 +334,8 @@ static const uint16 dm4_rom[] = { t_stat df_boot (int32 unitno, DEVICE *dptr) { -int32 i; -extern int32 sim_switches, saved_PC; +size_t i; +extern int32 saved_PC; if (sim_switches & SWMASK ('D')) { for (i = 0; i < DM4_LEN; i = i + 2) diff --git a/PDP8/pdp8_dt.c b/PDP8/pdp8_dt.c index 2b0ffe9b..e8e37028 100644 --- a/PDP8/pdp8_dt.c +++ b/PDP8/pdp8_dt.c @@ -265,8 +265,6 @@ extern uint16 M[]; extern int32 int_req; extern UNIT cpu_unit; -extern int32 sim_switches; -extern FILE *sim_deb; int32 dtsa = 0; /* status A */ int32 dtsb = 0; /* status B */ @@ -293,7 +291,6 @@ void dt_seterr (UNIT *uptr, int32 e); int32 dt_comobv (int32 val); int32 dt_csum (UNIT *uptr, int32 blk); int32 dt_gethdr (UNIT *uptr, int32 blk, int32 relpos, int32 dir); -extern int32 sim_is_running; /* DT data structures @@ -1178,7 +1175,7 @@ static const uint16 boot_rom[] = { t_stat dt_boot (int32 unitno, DEVICE *dptr) { -int32 i; +size_t i; extern int32 saved_PC; if (unitno) /* only unit 0 */ diff --git a/PDP8/pdp8_fpp.c b/PDP8/pdp8_fpp.c index 6845dbe8..01636e37 100644 --- a/PDP8/pdp8_fpp.c +++ b/PDP8/pdp8_fpp.c @@ -96,8 +96,6 @@ #include "pdp8_defs.h" extern int32 int_req; -extern int32 sim_switches; -extern int32 sim_interval; extern uint16 M[]; extern int32 stop_inst; extern UNIT cpu_unit; diff --git a/PDP8/pdp8_mt.c b/PDP8/pdp8_mt.c index 844f414c..96b635ba 100644 --- a/PDP8/pdp8_mt.c +++ b/PDP8/pdp8_mt.c @@ -217,7 +217,7 @@ DEVICE mt_dev = { MT_NUMDR, 10, 31, 1, 8, 8, NULL, NULL, &mt_reset, NULL, &mt_attach, &mt_detach, - &mt_dib, DEV_DISABLE + &mt_dib, DEV_DISABLE | DEV_TAPE }; /* IOT routines */ diff --git a/PDP8/pdp8_pt.c b/PDP8/pdp8_pt.c index f2b1352a..f7102012 100644 --- a/PDP8/pdp8_pt.c +++ b/PDP8/pdp8_pt.c @@ -278,7 +278,7 @@ static const uint16 boot_rom[] = { t_stat ptr_boot (int32 unitno, DEVICE *dptr) { -int32 i; +size_t i; extern int32 saved_PC; extern uint16 M[]; diff --git a/PDP8/pdp8_rf.c b/PDP8/pdp8_rf.c index aef1c76d..74b28ad2 100644 --- a/PDP8/pdp8_rf.c +++ b/PDP8/pdp8_rf.c @@ -398,8 +398,8 @@ static const uint16 dm4_rom[] = { t_stat rf_boot (int32 unitno, DEVICE *dptr) { -int32 i; -extern int32 sim_switches, saved_PC; +size_t i; +extern int32 saved_PC; if (rf_dib.dev != DEV_RF) /* only std devno */ return STOP_NOTSTD; diff --git a/PDP8/pdp8_rk.c b/PDP8/pdp8_rk.c index 10b0e5ad..93293e49 100644 --- a/PDP8/pdp8_rk.c +++ b/PDP8/pdp8_rk.c @@ -450,7 +450,7 @@ static const uint16 boot_rom[] = { t_stat rk_boot (int32 unitno, DEVICE *dptr) { -int32 i; +size_t i; extern int32 saved_PC; if (rk_dib.dev != DEV_RK) /* only std devno */ diff --git a/PDP8/pdp8_rl.c b/PDP8/pdp8_rl.c index 22beb05a..de3cda88 100644 --- a/PDP8/pdp8_rl.c +++ b/PDP8/pdp8_rl.c @@ -689,7 +689,7 @@ static const uint16 boot_rom[] = { t_stat rl_boot (int32 unitno, DEVICE *dptr) { -int32 i; +size_t i; extern int32 saved_PC; if (unitno) /* only unit 0 */ diff --git a/PDP8/pdp8_rx.c b/PDP8/pdp8_rx.c index 7a51df0d..18b43c22 100644 --- a/PDP8/pdp8_rx.c +++ b/PDP8/pdp8_rx.c @@ -733,7 +733,7 @@ static const uint16 boot2_rom[] = { t_stat rx_boot (int32 unitno, DEVICE *dptr) { -int32 i; +size_t i; extern int32 saved_PC; extern uint16 M[]; diff --git a/PDP8/pdp8_sys.c b/PDP8/pdp8_sys.c index ed7ff85b..20eba5ec 100644 --- a/PDP8/pdp8_sys.c +++ b/PDP8/pdp8_sys.c @@ -65,7 +65,6 @@ extern DEVICE mt_dev, ct_dev; extern DEVICE ttix_dev, ttox_dev; extern REG cpu_reg[]; extern uint16 M[]; -extern int32 sim_switches; t_stat fprint_sym_fpp (FILE *of, t_value *val); t_stat parse_sym_fpp (char *cptr, t_value *val); diff --git a/PDP8/pdp8_td.c b/PDP8/pdp8_td.c index 46703def..c4333820 100644 --- a/PDP8/pdp8_td.c +++ b/PDP8/pdp8_td.c @@ -208,8 +208,6 @@ int32 td_set_mtk (int32 code, int32 u, int32 k); t_stat td_show_pos (FILE *st, UNIT *uptr, int32 val, void *desc); extern uint16 M[]; -extern int32 sim_switches; -extern int32 sim_is_running; /* TD data structures @@ -742,7 +740,7 @@ static const uint16 boot_rom[] = { t_stat td_boot (int32 unitno, DEVICE *dptr) { -int32 i; +size_t i; extern int32 saved_PC; if (unitno) diff --git a/PDP8/pdp8_tt.c b/PDP8/pdp8_tt.c index 9f39b5d1..bd918d87 100644 --- a/PDP8/pdp8_tt.c +++ b/PDP8/pdp8_tt.c @@ -42,10 +42,11 @@ */ #include "pdp8_defs.h" +#include "sim_tmxr.h" #include extern int32 int_req, int_enable, dev_done, stop_inst; -extern int32 tmxr_poll, sim_is_running; +extern int32 tmxr_poll; int32 tti (int32 IR, int32 AC); int32 tto (int32 IR, int32 AC); @@ -176,8 +177,7 @@ t_stat tti_svc (UNIT *uptr) { int32 c; -sim_activate (uptr, KBD_WAIT (uptr->wait, clk_cosched (tmxr_poll))); - /* continue poll */ +sim_clock_coschedule (uptr, tmxr_poll); /* continue poll */ if ((c = sim_poll_kbd ()) < SCPE_KFLAG) /* no char or error? */ return c; if (c & SCPE_BREAK) /* break? */ @@ -193,6 +193,7 @@ return SCPE_OK; t_stat tti_reset (DEVICE *dptr) { +tmxr_set_console_units (&tti_unit, &tto_unit); tti_unit.buf = 0; dev_done = dev_done & ~INT_TTI; /* clear done, int */ int_req = int_req & ~INT_TTI; diff --git a/PDP8/pdp8_ttx.c b/PDP8/pdp8_ttx.c index 5c335a48..f65f23be 100644 --- a/PDP8/pdp8_ttx.c +++ b/PDP8/pdp8_ttx.c @@ -61,12 +61,12 @@ #define TTX_GETLN(x) (((x) >> 4) & TTX_MASK) extern int32 int_req, int_enable, dev_done, stop_inst; -extern int32 tmxr_poll, sim_is_running; +extern int32 tmxr_poll; uint8 ttix_buf[TTX_LINES] = { 0 }; /* input buffers */ uint8 ttox_buf[TTX_LINES] = { 0 }; /* output buffers */ int32 ttx_tps = 100; /* polls per second */ -TMLN ttx_ldsc[TTX_LINES] = { 0 }; /* line descriptors */ +TMLN ttx_ldsc[TTX_LINES] = { {0} }; /* line descriptors */ TMXR ttx_desc = { TTX_LINES, 0, 0, ttx_ldsc }; /* mux descriptor */ DEVICE ttix_dev, ttox_dev; @@ -123,7 +123,7 @@ DEVICE ttix_dev = { 1, 10, 31, 1, 8, 8, &tmxr_ex, &tmxr_dep, &ttix_reset, NULL, &ttx_attach, &ttx_detach, - &ttix_dib, DEV_NET | DEV_DISABLE + &ttix_dib, DEV_MUX | DEV_DISABLE }; /* TTOx data structures @@ -226,7 +226,7 @@ int32 ln, c, temp; if ((uptr->flags & UNIT_ATT) == 0) /* attached? */ return SCPE_OK; -sim_activate (uptr, clk_cosched (tmxr_poll)); /* continue poll */ +sim_clock_coschedule (uptr, tmxr_poll); /* continue poll */ ln = tmxr_poll_conn (&ttx_desc); /* look for connect */ if (ln >= 0) /* got one? rcv enb*/ ttx_ldsc[ln].rcve = 1; diff --git a/S3/s3_cpu.c b/S3/s3_cpu.c index e3f06482..6906b7e2 100644 --- a/S3/s3_cpu.c +++ b/S3/s3_cpu.c @@ -382,8 +382,6 @@ int32 saved_PC; /* Saved (old) PC) */ int32 debug_reg = 0; /* set for debug/trace */ int32 debug_flag = 0; /* 1 when trace.log open */ FILE *trace; -extern int32 sim_int_char; -extern uint32 sim_brk_types, sim_brk_dflt, sim_brk_summ;/* breakpoint info */ t_stat cpu_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw); t_stat cpu_dep (t_value val, t_addr addr, UNIT *uptr, int32 sw); @@ -396,9 +394,6 @@ extern int32 lpt (int32 op, int32 m, int32 n, int32 data); extern int32 dsk1 (int32 op, int32 m, int32 n, int32 data); extern int32 dsk2 (int32 op, int32 m, int32 n, int32 data); extern int32 cpu (int32 op, int32 m, int32 n, int32 data); -extern t_stat sim_activate (UNIT *uptr, int32 delay); -extern int32 fprint_sym (FILE *of, int32 addr, uint32 *val, - UNIT *uptr, int32 sw); int32 nulldev (int32 opcode, int32 m, int32 n, int32 data); int32 add_zoned (int32 addr1, int32 len1, int32 addr2, int32 len2); int32 subtract_zoned (int32 addr1, int32 len1, int32 addr2, int32 len2); @@ -507,7 +502,6 @@ DEVICE cpu_dev = { t_stat sim_instr (void) { -extern int32 sim_interval; register int32 PC, IR; int32 i, j, carry, zero, op1, op2; int32 opcode = 0, qbyte = 0, rbyte = 0; diff --git a/S3/s3_pkb.c b/S3/s3_pkb.c index 0ba62090..461fc736 100644 --- a/S3/s3_pkb.c +++ b/S3/s3_pkb.c @@ -35,8 +35,6 @@ extern int32 int_req, dev_busy, dev_done, dev_disable; t_stat pkb_svc (UNIT *uptr); t_stat pkb_reset (DEVICE *dptr); -extern t_stat sim_poll_kbd (void); -extern t_stat sim_putchar (int32 out); extern int32 IAR[], level; extern int32 debug_reg; diff --git a/S3/s3_sys.c b/S3/s3_sys.c index 39cec895..dacdd2d7 100644 --- a/S3/s3_sys.c +++ b/S3/s3_sys.c @@ -44,9 +44,9 @@ extern REG cpu_reg[]; extern unsigned char M[]; extern int32 saved_PC, IAR[]; extern unsigned char ebcdic_to_ascii[]; -char *parse_addr(char *cptr, char *gbuf, int32 *addr, int32 *addrtype); +char *parse_addr(char *cptr, char *gbuf, t_addr *addr, int32 *addrtype); -int32 printf_sym (FILE *of, char *strg, int32 addr, uint32 *val, +int32 printf_sym (FILE *of, char *strg, t_addr addr, uint32 *val, UNIT *uptr, int32 sw); /* SCP data structures @@ -225,7 +225,7 @@ char regname[15][8] = { "(P2IAR)", load starts at the current value of the P1IAR. */ -int32 sim_load (FILE *fileref, char *cptr, char *fnam, int flag) +t_stat sim_load (FILE *fileref, char *cptr, char *fnam, int flag) { int32 i, addr = 0, cnt = 0; @@ -252,7 +252,7 @@ return (SCPE_OK); status = error code */ -int32 fprint_sym (FILE *of, int32 addr, uint32 *val, +t_stat fprint_sym (FILE *of, t_addr addr, t_value *val, UNIT *uptr, int32 sw) { int32 r; @@ -267,16 +267,15 @@ int32 fprint_sym (FILE *of, int32 addr, uint32 *val, return (r); } -int32 printf_sym (FILE *of, char *strg, int32 addr, uint32 *val, +int32 printf_sym (FILE *of, char *strg, t_addr addr, uint32 *val, UNIT *uptr, int32 sw) { -int32 cflag, c1, c2, group, len1, len2, inst, aaddr, baddr; +int32 c1, c2, group, len1, len2, inst, aaddr, baddr; int32 oplen, groupno, i, j, vpos, qbyte, da, m, n; char bld[128], bldaddr[32], boperand[32], aoperand[32]; int32 blk[16], blt[16]; int32 blkadd; -cflag = (uptr == NULL) || (uptr == &cpu_unit); c1 = val[0] & 0xff; if (sw & SWMASK ('A')) { for (i = 0; i < 16; i++) { @@ -502,7 +501,7 @@ return -(oplen - 1); status = error status */ -int32 parse_sym (char *cptr, int32 addr, UNIT *uptr, uint32 *val, int32 sw) +t_stat parse_sym (char *cptr, t_addr addr, UNIT *uptr, t_value *val, int32 sw) { int32 cflag, i = 0, j, r, oplen, addtyp, saveaddr, vptr; char gbuf[CBUFSIZE]; @@ -924,7 +923,7 @@ switch (opcode[j].form) { /* Get operands based on return (-(oplen-1)); } -char *parse_addr(char *cptr, char *gbuf, int32 *addr, int32 *addrtype) +char *parse_addr(char *cptr, char *gbuf, t_addr *addr, int32 *addrtype) { int32 nybble = 0; char temp[32]; diff --git a/SDS/sds_cpu.c b/SDS/sds_cpu.c index f045b6e7..c80ce356 100644 --- a/SDS/sds_cpu.c +++ b/SDS/sds_cpu.c @@ -194,9 +194,6 @@ InstHistory *hst = NULL; /* instruction history * int32 rtc_pie = 0; /* rtc pulse ie */ int32 rtc_tps = 60; /* rtc ticks/sec */ -extern int32 sim_int_char; -extern uint32 sim_brk_types, sim_brk_dflt, sim_brk_summ; /* breakpoint info */ - t_stat cpu_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw); t_stat cpu_dep (t_value val, t_addr addr, UNIT *uptr, int32 sw); t_stat cpu_reset (DEVICE *dptr); @@ -359,7 +356,6 @@ static const uint32 int_vec[32] = { t_stat sim_instr (void) { -extern int32 sim_interval; uint32 inst, tinst, pa, save_P, save_mode; t_stat reason, tr; @@ -1341,7 +1337,7 @@ if (sc >= 24) { A = sgn; } else { - B = ((B >> sc) | (A << (24 - sc)) & DMASK); + B = ((B >> sc) | (A << (24 - sc))) & DMASK; A = ((A >> sc) | (sgn << (24 - sc))) & DMASK; } return; @@ -1667,8 +1663,6 @@ char *cptr = (char *) desc; t_stat r; t_value sim_eval; InstHistory *h; -extern t_stat fprint_sym (FILE *ofile, t_addr addr, t_value *val, - UNIT *uptr, int32 sw); static char *cyc[] = { " ", " ", "INT", "TRP" }; if (hst_lnt == 0) /* enabled? */ diff --git a/SDS/sds_io.c b/SDS/sds_io.c index bd0b01f4..dc5e7618 100644 --- a/SDS/sds_io.c +++ b/SDS/sds_io.c @@ -86,8 +86,6 @@ extern int32 rtc_pie; extern int32 stop_invins, stop_invdev, stop_inviop; extern uint32 mon_usr_trap; extern UNIT cpu_unit; -extern FILE *sim_log; -extern DEVICE *sim_devices[]; t_stat chan_reset (DEVICE *dptr); t_stat chan_read (int32 ch); @@ -224,7 +222,7 @@ uint32 dev_map[64][NUM_CHAN]; /* dev_dsp maps device and channel numbers to dispatch routines */ -t_stat (*dev_dsp[64][NUM_CHAN])() = { NULL }; +t_stat (*dev_dsp[64][NUM_CHAN])() = { {NULL} }; /* dev3_dsp maps system device numbers to dispatch routines */ diff --git a/SDS/sds_mt.c b/SDS/sds_mt.c index 3e398ac5..f7fc56d4 100644 --- a/SDS/sds_mt.c +++ b/SDS/sds_mt.c @@ -168,7 +168,7 @@ DEVICE mt_dev = { MT_NUMDR, 10, 31, 1, 8, 8, NULL, NULL, &mt_reset, &mt_boot, &mt_attach, NULL, - &mt_dib, DEV_DISABLE + &mt_dib, DEV_DISABLE | DEV_TAPE }; /* Mag tape routine diff --git a/SDS/sds_mux.c b/SDS/sds_mux.c index 8cc7023a..2b5054ab 100644 --- a/SDS/sds_mux.c +++ b/SDS/sds_mux.c @@ -112,7 +112,7 @@ uint32 mux_tps = 100; /* polls/second */ uint32 mux_scan = 0; /* scanner */ uint32 mux_slck = 0; /* scanner locked */ -TMLN mux_ldsc[MUX_LINES] = { 0 }; /* line descriptors */ +TMLN mux_ldsc[MUX_LINES] = { {0} }; /* line descriptors */ TMXR mux_desc = { MUX_LINES, 0, 0, mux_ldsc }; /* mux descriptor */ t_stat mux (uint32 fnc, uint32 inst, uint32 *dat); @@ -169,7 +169,7 @@ DEVICE mux_dev = { 1, 10, 31, 1, 8, 8, &tmxr_ex, &tmxr_dep, &mux_reset, NULL, &mux_attach, &mux_detach, - &mux_dib, DEV_NET | DEV_DISABLE + &mux_dib, DEV_MUX | DEV_DISABLE }; /* MUXL data structures diff --git a/SDS/sds_stddev.c b/SDS/sds_stddev.c index 13877418..537acca1 100644 --- a/SDS/sds_stddev.c +++ b/SDS/sds_stddev.c @@ -33,6 +33,7 @@ */ #include "sds_defs.h" +#include "sim_tmxr.h" #define TT_CR 052 /* typewriter */ #define TT_TB 072 @@ -518,6 +519,7 @@ return SCPE_OK; t_stat tti_reset (DEVICE *dptr) { +tmxr_set_console_units (&tti_unit, &tto_unit); chan_disc (tti_dib.chan); /* disconnect */ tti_unit.buf = 0; /* clear state */ xfr_req = xfr_req & ~XFR_TTI; /* clr xfr flag */ diff --git a/SDS/sds_sys.c b/SDS/sds_sys.c index 44f98173..1f2a0cef 100644 --- a/SDS/sds_sys.c +++ b/SDS/sds_sys.c @@ -217,7 +217,6 @@ t_stat sim_load (FILE *fileref, char *cptr, char *fnam, int flag) { int32 i, wd, buf[8]; int32 ldr = 1; -extern int32 sim_switches; extern uint32 P; if ((*cptr != 0) || (flag != 0)) diff --git a/TX-0/bin_newMouse_3-22-66.bin b/TX-0/bin_newMouse_3-22-66.bin new file mode 100644 index 00000000..82bb88ee --- /dev/null +++ b/TX-0/bin_newMouse_3-22-66.bin @@ -0,0 +1 @@ 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\ No newline at end of file diff --git a/TX-0/loader.simh b/TX-0/loader.simh new file mode 100644 index 00000000..5ffb4400 --- /dev/null +++ b/TX-0/loader.simh @@ -0,0 +1,6 @@ +; TX-0 Loader Routine, pp20 of TX0_funcDescr.pdf +att petr test.tap +set cpu debug=readin +;boot petr +;s 500 +;d pc 20 diff --git a/TX-0/mouse.simh b/TX-0/mouse.simh new file mode 100644 index 00000000..0ff6814a --- /dev/null +++ b/TX-0/mouse.simh @@ -0,0 +1,17 @@ +; TX-0 Initialization file for the Mouse Maze Game +att petr bin_newMouse_3-22-66.bin + +; The mouse maze game mode is manipulated under TAC control. +; 400014 = Erase Wall mode. +; 400024 = Write Wall mode. +; 400011 = Erase Cheese mode. +; 400021 = Write Cheese mode. +; 400012 = Erase Mouse mode. +; 400022 = Write Mouse mode. +; 400002 = "do mouse" (start the mouse searching.) +; 400017 = "do over" + +; Start in "Erase Wall" mode +d tac 400014 +boot petr + diff --git a/TX-0/tic.simh b/TX-0/tic.simh new file mode 100644 index 00000000..47636aff --- /dev/null +++ b/TX-0/tic.simh @@ -0,0 +1,5 @@ +; TX-0 Initialization file for the tic-tac-toe game +att petr bin_tic-tac-toe_new_code_12-16-61.bin +boot petr +g + diff --git a/TX-0/tx0_cpu.c b/TX-0/tx0_cpu.c new file mode 100644 index 00000000..0fbda2a6 --- /dev/null +++ b/TX-0/tx0_cpu.c @@ -0,0 +1,1476 @@ +/************************************************************************* + * * + * $Id: tx0_cpu.c 2066 2009-02-27 15:57:22Z hharte $ * + * * + * Copyright (c) 2009-2012 Howard M. Harte. * + * Based on pdp1_cpu.c, Copyright (c) 1993-2007, Robert M. Supnik * + * * + * Permission is hereby granted, free of charge, to any person obtaining * + * a copy of this software and associated documentation files (the * + * "Software"), to deal in the Software without restriction, including * + * without limitation the rights to use, copy, modify, merge, publish, * + * distribute, sublicense, and/or sell copies of the Software, and to * + * permit persons to whom the Software is furnished to do so, subject to * + * the following conditions: * + * * + * The above copyright notice and this permission notice shall be * + * included in all copies or substantial portions of the Software. * + * * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * + * NONINFRINGEMENT. IN NO EVENT SHALL HOWARD M. HARTE BE LIABLE FOR ANY * + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * + * * + * Except as contained in this notice, the name of Howard M. Harte shall * + * not be used in advertising or otherwise to promote the sale, use or * + * other dealings in this Software without prior written authorization * + * of Howard M. Harte. * + * * + * Module Description: * + * TX-0 Central Processor * + * * + * Environment: * + * User mode only * + * * + * References: * + * See: www.bitsavers.org/pdf/mit/tx-0/ for documentation. * + * See: www.bitsavers.org/bits/MIT/tx-0/ for software. * + *************************************************************************/ + +/* + +The original Lincoln Labs TX-0 had only two bits of opcode and no index +register. The machine was moved to room 26-248 at MIT in July 1958 and +after about a year and a half the opcode field was extended to four bits +and an index register was added. + +(ref. Computer Museum Report Vol 8, Spring 1984) + +-------------------------------------------------------------- +Original TX-0 Registers and Instruction Set +from "A Functional Description of the TX-0 Computer" Oct, 1958 +-------------------------------------------------------------- + + The register state for the TX-0 is: + + MBR[0:17] Memory Buffer Register (18 bits) + AC[0:17] Accumulator (18 bits) + MAR[0:15] Memory Address Register (16 bits) + PC[0:15] Program Counter (16 bits) + IR[0:1] Instruction Register (2 bits) + LR[0:17] Live Register (18 bits) + TBR[0:17] Toggle Switch Buffer Register (18 toggle switches) + TAC[0:17] Toggle Switch Accumulator (18 toggle switches) + + 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 + +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ + | op | address | + +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ + + This routine is the instruction decode routine for the TX-0. + It is called from the simulator control program to execute + instructions in simulated memory, starting at the simulated PC. + It runs until 'reason' is set non-zero. + + General notes: + + 1. Instruction Set: The TX-0 had (at least) two different instruction sets. + The original instruction set from 1956 had two bits for the opcode (IR) + while the later 1961 instruction set used five bits for this purpose. + This simulator is designed to simulate both of these modes. The micro + orders were also changed along with the new instruction set. The main + part of the instruction fetch/decode logic is the same for both + instruction sets. Memory address range is adjusted depending on the mode. + IR[2:4] are forced to 0 in the 1956 mode. The Micro Orders are vastly + different, so the main loop decodes and executes the 1961 micro-orders, + while the sim_opr_orig() function decodes and executes the 1956 micro-orders. + + 2. Reasons to stop. The simulator can be stopped by: + + HALT instruction + breakpoint encountered + I/O error in I/O simulator + + 3. Arithmetic. The TX-0 is a 1's complement system. In 1's + complement arithmetic, a negative number is represented by the + complement (XOR 0777777) of its absolute value. Addition of 1's + complement numbers requires propagating the carry out of the high + order bit back to the low order bit. + + 4. Adding I/O devices. Three modules must be modified: + + tx0_cpu.c add dispatch code + tx0_sys.c add sim_devices table entry + + 5. Bugs, limitations, and known issues: + o There is a bug in the 1961 instruction set simulation, which causes the + mouse maze program's searching algorithm to fail. + o The CRY micro-order is not implemented. + o The instruction timing (ie, sim_interval) is not accurate, so implementing a + timing-critical I/O device like the Magtape would require this to be added first. + o PCQ and History do not work. + o Symbolic input does not work. + o Probably lots of other bugs, as Tic-Tac-Toe and Mouse Maze are the only tapes + that I've tested to mostly work. It's difficult to tell what tapes on + bitsavers.org are designed for the 1956 instruction set vs. the later one. + + +OP Description +-- ----------- + +00 sto x Replace the contents of register x with the contents of the AC + Let the AC remain the same. +01 add x Add the word in register x to the contents of the AC and leave + the sum in the AC +10 trn x If the sign digit of the accumulator (AC bit 0) is negative (i.e., a one) + take the next instruction from register x and continue from there. + If the sign is positive (i.e., a zero ignore this instruction and proceed + to the next instruction +11 opr x Execute one of the operate class commands indicated by the number x + +Around 1961, the TX-0 was modified to include additional instructions, and the addressable +memory range was lowered to 8K words. The IR was increased from two bits to five bits. +In addtion, many of the operate-class micro-orders changed. + + OPERATE CLASS MICRO-ORDERS FOR 1961 INSTRUCTION SET + --------------------------------------------------- + Cycle.tp + cla --1 --- --- --- --- --- 0.8 Clear AC + amb --- 1-- --- --- --- --- 0.7 Transfer AC contents to MBR + cyr --- --- --- 110 --- --- 1.6 Cycle AC contents right one binary position (AC 17 -> AC 0) + shr --- --- --- 100 --- --- 1.6 Shift AC contents right one binary position (AC 0 unchanged) + mbl --- --- --- 01x --- --- 1.4 Transfer MBR contents to LR + xmb --- --- --- 0x1 --- --- 1.2 Transfer XR contents to MBR + com --- --- --- --- 1-- --- 1.2 Compliment AC + pad --- --- --- --- -1- --- 1.5 Parital add MBR to AC (for each MBR one, complement the correp AC bit) + cry --- --- --- --- --1 --- 1.7 A carry digit is a one if in the next least sigmificant digit, + either ac=0 and mbr=1 or ac=1 and carry digit=1. The carry digits + so determined are partial added to the AC by cry. pad and cry used + together give a full one's complement addition of C(MBR) to C(AC) + anb --- --- --- --- --- 111 1.2-2 And LR and MBR + orb --- --- --- --- --- 101 1.3 Or LR into MBR + lmb --- --- --- --- --- 01x 1.4 Tranfer LR contents to MBR + mbx --- --- --- --- --- 0x1 1.8 Transfer MBR contents to XR +*/ +#include "tx0_defs.h" + +#define OPR_CLA 0100000 /* 0.8 */ +#define OPR_AMB 0040000 /* 0.7 */ + +#define OPR_SHF_MASK 0000700 /* 1.6 */ +#define OPR_CYR 0000600 +#define OPR_SHR 0000400 + +#define OPR_MBL_MASK 0000600 /* 1.4 */ +#define OPR_MBL 0000200 +#define OPR_XMB_MASK 0000500 /* 1.2 */ +#define OPR_XMB 0000100 + +#define OPR_COM 0000040 /* 1.2 */ +#define OPR_PAD 0000020 /* 1.5 */ +#define OPR_CRY 0000010 /* 1.7 */ + +#define OPR_LOG_MASK 0000007 /* Logical operation mask */ +#define OPR_ANB 0000007 /* 1.2-2 */ +#define OPR_ORB 0000005 /* 1.3 */ + +#define OPR_LMB_MASK 0000006 /* 1.4 */ +#define OPR_LMB 0000002 +#define OPR_MBX_MASK 0000005 /* 1.8 */ +#define OPR_MBX 0000001 + +/* + IN OUT GROUP + ------------ + nop --- -00 000 --- --- --- NOP + tac --- -00 001 --- --- --- 1.1 + tbr --- -00 010 --- --- --- 1.2 + pen --- -00 011 --- --- --- 1.1 + sel --- -00 100 --- --- --- + spare--- -00 101 --- --- --- + rpf --- -00 110 --- --- --- 1.2 + spf --- -00 111 --- --- --- 1.6 + exN --- -01 nnn --- --- --- IOS + cpy --- -10 000 --- --- --- IOS + r1l --- -10 001 --- --- --- IOS + dis --- -10 010 --- --- --- IOS + r3l --- -10 011 --- --- --- IOS + prt --- -10 100 --- --- --- IOS + spare--- -10 101 --- --- --- + p6h --- -10 110 --- --- --- IOS + p7h --- -10 111 --- --- --- IOS + hlt --- -11 000 --- --- --- 1.8 + cll --- -11 001 --- --- --- 0.6 + clr --- -11 010 --- --- --- 0.6 +*/ +#define IOS_MASK 0037000 +#define IOS_EX_MASK 0030000 +#define IOS_NOP 0000000 +#define IOS_TAC 0001000 +#define IOS_TBR 0002000 +#define IOS_PEN 0003000 +#define IOS_SEL 0004000 +#define IOS_RPF 0006000 +#define IOS_SPF 0007000 +#define IOS_CPY 0020000 +#define IOS_R1L 0021000 +#define IOS_DIS 0022000 +#define IOS_R3L 0023000 +#define IOS_PRT 0024000 +#define IOS_P6H 0026000 +#define IOS_P7H 0027000 +#define IOS_HLT 0030000 +#define IOS_CLL 0031000 +#define IOS_CLR 0032000 + +#define PCQ_SIZE 64 /* must be 2**n */ +#define PCQ_MASK (PCQ_SIZE - 1) +#define PCQ_ENTRY pcq[pcq_p = (pcq_p - 1) & PCQ_MASK] = PC +#define UNIT_V_MSIZE (UNIT_V_UF + 4) /* dummy mask */ +#define UNIT_V_EXT (UNIT_V_UF + 2) +#define UNIT_EXT_INST (1 << UNIT_V_EXT) +#define UNIT_MSIZE (1 << UNIT_V_MSIZE) + +#define HIST_PC 0x40000000 +#define HIST_V_SHF 18 +#define HIST_MIN 64 +#define HIST_MAX 65536 + +#define TRACE_PRINT(level, args) if(cpu_dev.dctrl & level) { \ + printf args; \ + } +typedef struct { + uint32 pc; + uint32 ir; + uint32 ovac; + uint32 pfio; + uint32 ea; + uint32 opnd; +} InstHistory; + +int32 M[MAXMEMSIZE] = { 0 }; /* memory */ +int32 AC = 0; /* AC */ +int32 IR = 0; /* IR */ +int32 PC = 0; /* PC */ +int32 MAR = 0; /* MAR */ +int32 XR = 0; /* XR (index register) */ +int32 MBR = 0; /* MBR */ +int32 LR = 0; /* LR (Live Register) */ +int32 OV = 0; /* overflow */ +int32 TBR = 0; /* sense switches */ +int32 PF = 0; /* program flags */ +int32 TAC = 0; /* Toggle Switch Accumulator */ +int32 iosta = 0; /* status reg */ +int32 ios = 0; /* I/O Stop */ +int32 ch = 0; /* Chime Alarm */ +int32 LP = 0; /* Light Pen / Light Gun flops */ +int32 mode_tst = 1; /* Test Mode Flip-flop */ +int32 mode_rdin = 1; /* Read-In Mode Flip-flop */ + +uint16 pcq[PCQ_SIZE] = { 0 }; /* PC queue */ +int32 pcq_p = 0; /* PC queue ptr */ +REG *pcq_r = NULL; /* PC queue reg ptr */ +int32 hst_p = 0; /* history pointer */ +int32 hst_lnt = 0; /* history length */ +InstHistory *hst = NULL; /* inst history */ + +int32 fpc_MA; /* shadow ma for FPC access */ +int32 fpc_OP; /* shadow op for FPC access */ + +int32 addr_mask = YMASK; + +t_stat cpu_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw); +t_stat cpu_dep (t_value val, t_addr addr, UNIT *uptr, int32 sw); +t_stat cpu_reset (DEVICE *dptr); +t_stat cpu_set_size (UNIT *uptr, int32 val, char *cptr, void *desc); +t_stat cpu_set_mode (UNIT *uptr, int32 val, char *cptr, void *desc); +int32 cpu_get_mode (void); +t_stat cpu_set_hist (UNIT *uptr, int32 val, char *cptr, void *desc); +t_stat cpu_set_ext (UNIT *uptr, int32 val, char *cptr, void *desc); +t_stat cpu_set_noext (UNIT *uptr, int32 val, char *cptr, void *desc); +t_stat cpu_show_hist (FILE *st, UNIT *uptr, int32 val, void *desc); +t_stat Read (void); +t_stat Write (void); + +extern int32 petr (int32 inst, int32 dev, int32 dat); +extern int32 ptp (int32 inst, int32 dev, int32 dat); +extern int32 tti (int32 inst, int32 dev, int32 dat); +extern int32 tto (int32 inst, int32 dev, int32 dat); +extern int32 lpt (int32 inst, int32 dev, int32 dat); +extern int32 dt (int32 inst, int32 dev, int32 dat); +extern int32 drm (int32 inst, int32 dev, int32 dat); +#ifdef USE_DISPLAY +extern int32 dpy (int32 ac); +#endif + +/* CPU data structures + + cpu_dev CPU device descriptor + cpu_unit CPU unit + cpu_reg CPU register list + cpu_mod CPU modifier list +*/ + +UNIT cpu_unit = { UDATA (NULL, UNIT_FIX | UNIT_BINK | UNIT_EXT_INST | UNIT_MODE_READIN, MAXMEMSIZE) }; + +REG cpu_reg[] = { + { ORDATA (PC, PC, ASIZE) }, + { ORDATA (AC, AC, 18) }, + { ORDATA (IR, IR, 5) }, + { ORDATA (MAR, MAR, 16) }, + { ORDATA (XR, XR, 14) }, + { ORDATA (MBR, MBR, 18) }, + { ORDATA (LR, LR, 18) }, + { ORDATA (TAC, TAC, 18) }, + { ORDATA (TBR, TBR, 18) }, + { ORDATA (PF, PF, 18) }, + { BRDATA (PCQ, pcq, 8, ASIZE, PCQ_SIZE), REG_RO+REG_CIRC }, + { ORDATA (PCQP, pcq_p, 6), REG_HRO }, + { FLDATA (IOS, ios, 0) }, /* In Out Stop */ + { FLDATA (CH, ch, 0) }, /* Chime Alarm */ + { ORDATA (LP, LP, 2) }, /* Light Pen */ + { FLDATA (R, mode_rdin, 0), REG_HRO }, /* Mode "R" (Read In) Flip-Flop */ + { FLDATA (T, mode_tst, 0), REG_HRO }, /* Mode "T" (Test) Flip-Flop */ + { NULL } + }; + +MTAB cpu_mod[] = { + { UNIT_EXT_INST, 0, "standard CPU", "TX0STD", &cpu_set_noext }, + { UNIT_EXT_INST, UNIT_EXT_INST, "Extended Instruction Set", "TX0EXT", &cpu_set_ext }, + { UNIT_MSIZE, 4096, NULL, "4K", &cpu_set_size }, + { UNIT_MSIZE, 8192, NULL, "8K", &cpu_set_size }, + { UNIT_MSIZE, 65536, NULL, "64K", &cpu_set_size }, + { UNIT_MODE, 0, "NORMAL", "NORMAL", &cpu_set_mode }, + { UNIT_MODE, UNIT_MODE_TEST, "TEST", "TEST", &cpu_set_mode }, + { UNIT_MODE, UNIT_MODE_READIN, "READIN", "READIN", &cpu_set_mode }, + { MTAB_XTD|MTAB_VDV|MTAB_NMO|MTAB_SHP, 0, "HISTORY", "HISTORY", + &cpu_set_hist, &cpu_show_hist }, + { 0 } + }; + +/* Debug flags */ +#define ERROR_MSG (1 << 0) +#define TRACE_MSG (1 << 1) +#define STO_MSG (1 << 2) +#define ADD_MSG (1 << 3) +#define TRN_MSG (1 << 4) +#define ORD_MSG (1 << 5) +#define IOS_MSG (1 << 6) +#define READIN_MSG (1 << 7) +#define VERBOSE_MSG (1 << 8) +#define COUNTERS_MSG (1 << 9) + +/* Debug Flags */ +static DEBTAB cpu_dt[] = { + { "ERROR", ERROR_MSG }, + { "TRACE", TRACE_MSG }, + { "STO", STO_MSG }, + { "ADD", ADD_MSG }, + { "TRN", TRN_MSG }, + { "ORD", ORD_MSG }, + { "IOS", IOS_MSG }, + { "READIN", READIN_MSG }, + { "VERBOSE",VERBOSE_MSG }, + { "COUNTERS",COUNTERS_MSG }, + { NULL, 0 } +}; + +DEVICE cpu_dev = { + "CPU", &cpu_unit, cpu_reg, cpu_mod, + 1, 8, ASIZE, 1, 8, 18, + &cpu_ex, &cpu_dep, &cpu_reset, + NULL, NULL, NULL, + NULL, DEV_DEBUG, ERROR_MSG, + cpu_dt, NULL + }; + +int32 compute_index (int32 y, int32 XR) +{ + int32 sum; + + y &= YMASK; /* force 13-bit (0 sign) */ + XR &= 037777; /* force 14-bit */ + + sum = y + XR; + + if (sum > 037777) { /* Carry from bit 4 into bit 17. */ + sum += 1; + } + + sum &= YMASK; /* truncate to 13-bit */ + + return (sum); +} + +/* CPU Instruction usage counters */ +typedef struct { +/* Store group */ + int32 sto, stx, sxa, ado, slr, slx, stz; +/* Add group */ + int32 add, adx, ldx, aux, llr, llx, lda, lax; +/* TRN Group */ + int32 trn, tze, tsx, tix, tra, trx, tlv; +/* OPR Group */ + int32 cla, amb, cyr, shr, mbl, xmb, com, pad, cry, anb, orb, lmb, mbx; +} INST_CTRS; + +INST_CTRS inst_ctr; + + +void tx0_dump_regs(char *desc) +{ + TRACE_PRINT(TRACE_MSG, ("%s: AC=%06o, MAR=%05o, MBR=%06o, LR=%06o, XR=%05o\n", desc, AC, MAR, MBR, LR, XR)); + + /* Check regs sanity */ + if (AC > DMASK) { + printf("Error: AC > DMASK\n"); + } + if (MBR > DMASK) { + printf("Error: MBR > DMASK\n"); + } + if (LR > DMASK) { + printf("Error: LR > DMASK\n"); + } + if (!MEM_ADDR_OK(MAR)) { + printf("Error: MAR > %06o\n", MEMSIZE); + } + +} + +t_stat sim_opr_orig(int32 op); + +t_stat sim_instr (void) +{ + int32 IR, op, inst_class, y; + int32 tempLR; /* LR temporary storage in case both LMB and MBL are set (swap LR<->MBR) */ + t_stat reason; + + /* Clear Instruction counters */ + inst_ctr.sto = inst_ctr.stx = inst_ctr.sxa = inst_ctr.ado = inst_ctr.slr = inst_ctr.slx = inst_ctr.stz = 0; + inst_ctr.add = inst_ctr.adx = inst_ctr.ldx = inst_ctr.aux = inst_ctr.llr = inst_ctr.llx = inst_ctr.lda = inst_ctr.lax = 0; + inst_ctr.trn = inst_ctr.trn = inst_ctr.tze = inst_ctr.tsx = inst_ctr.tix = inst_ctr.tra = inst_ctr.trx = inst_ctr.tlv = 0; + inst_ctr.cla = inst_ctr.amb = inst_ctr.cyr = inst_ctr.shr = inst_ctr.mbl = inst_ctr.xmb = inst_ctr.com = inst_ctr.pad = inst_ctr.cry = inst_ctr.anb = inst_ctr.orb = inst_ctr.lmb = inst_ctr.mbx = 0; + + #define INCR_ADDR(x) ((x+=1) & (MEMSIZE-1)) + + /* Main instruction fetch/decode loop: check events */ + + reason = 0; + while (reason == 0) { /* loop until halted */ + + if (sim_interval <= 0) { /* check clock queue */ + reason = sim_process_event (); + if (reason != SCPE_OK) + break; + } + + if (sim_brk_summ && sim_brk_test (PC, SWMASK ('E'))) { /* breakpoint? */ + reason = STOP_IBKPT; /* stop simulation */ + break; + } + + if (ios) { + TRACE_PRINT(ERROR_MSG, ("I/O Stop - Waiting...\n")); + continue; + } + + /* Handle Instruction Execution in TEST and READIN modes */ + if (mode_tst) { /* Test Mode / Readin mode */ + if (mode_rdin) { /* Readin Mode */ + reason = SCPE_OK; /* Default is to continue reading, and transfer control when done. */ + AC = petr(3,0,0); /* Read three chars from tape into AC */ + MAR = AC & AMASK; /* Set memory address */ + IR = AC >> 16; + + if (!MEM_ADDR_OK(MAR)) { + TRACE_PRINT(ERROR_MSG, ("READIN: Tape address out of range.\n")); + reason = SCPE_FMT; + } + + switch (IR) { + case 00: /* Storage (sto x) */ + case 03: /* Storage (opr x) */ + MBR = petr(3,0,0); /* Read three characters from tape. */ + TRACE_PRINT(READIN_MSG, ("READIN: sto @%06o = %06o\n", MAR, MBR)); + Write(); + break; + case 02: /* Transfer Control (trn x) Start Execution */ + PC = MAR; + reason = SCPE_OK; /* let SIMH start execution. */ + TRACE_PRINT(READIN_MSG, ("READIN: trn %06o (Start Execution)\n", PC)); + reason = cpu_set_mode(&cpu_unit, 0, NULL, NULL); + break; + case 01: /* Transfer (add x) - Halt */ + PC = MAR; + reason = SCPE_STOP; /* let SIMH halt. */ + TRACE_PRINT(READIN_MSG, ("READIN: add %06o (Halt)\n", PC)); + reason = cpu_set_mode(&cpu_unit, 0, NULL, NULL); + break; + default: + reason = SCPE_IERR; + break; + } + } else if (mode_tst) { /* Test mode not implemented yet. */ + TRACE_PRINT(ERROR_MSG, ("TEST Mode not implemented.\n")); + reason = SCPE_STOP; + + } else { + TRACE_PRINT(ERROR_MSG, ("Invalid CPU mode.\n")); + reason = SCPE_IERR; + } + continue; /* Proceed with next instruction */ + } + + /* Fetch, decode instruction in NORMAL mode */ + MAR = PC; + if (Read ()) break; /* fetch inst */ + + IR = (MBR >> 13); /* save in IR */ + inst_class = IR >> 3; + op = MBR & AMASK; + y = MBR & YMASK; + sim_interval = sim_interval - 1; + + if ((cpu_unit.flags & UNIT_EXT_INST) == 0) { /* Original instruction set */ + IR &= 030; + MAR = MBR & AMASK; /* 16-bit address field */ + } else { + MAR = MBR & YMASK; /* 13-bit address field */ + } + + if (hst_lnt) { /* history enabled? */ + hst_p = (hst_p + 1); /* next entry */ + if (hst_p >= hst_lnt) hst_p = 0; + hst[hst_p].pc = MAR | HIST_PC; /* save state */ + hst[hst_p].ir = IR; + hst[hst_p].ovac = (OV << HIST_V_SHF) | AC; + } + + PC = INCR_ADDR (PC); /* increment PC */ + +#ifdef USE_FPC + fpc_OP = op; /* shadow opcode for FPC */ +#endif + + tx0_dump_regs("START"); + + switch (inst_class) { /* decode IR<0:1> */ + + /* Logical, load, store instructions */ + case 00: /* sto x */ + switch (IR & 07) { + case 0: /* sto */ + MBR = AC; + Write(); + inst_ctr.sto++; + break; + case 1: /* stx */ + MBR = AC; + MAR = compute_index(y, XR); + Write(); + inst_ctr.stx++; + break; + case 2: /* sxa */ + { + int32 temp = M[MAR]; + temp &= 0760000; + temp |= (XR & YMASK); + MBR = temp; + Write(); + } + inst_ctr.sxa++; + break; + case 3: /* ado */ + { + int32 temp = M[MAR]; + temp += 1; /* add 1 */ + if (temp > DMASK) { /* Overflow, */ + temp += 1; /* propagate carry from bit 0 to bit 17. */ + } + temp &= DMASK; + MBR = temp; + AC = temp; + Write(); + } + inst_ctr.ado++; + break; + case 4: /* slr */ + MBR = LR; + Write(); + inst_ctr.slr++; + break; + case 5: /* slx */ + MAR = compute_index(y, XR); + MBR = LR; + Write(); + inst_ctr.slx++; + break; + case 6: /* stz */ + MBR = 0; + Write(); + inst_ctr.stz++; + break; + case 7: /* no-op */ + break; + } + break; + + case 01: /* add x */ + switch (IR & 07) { + case 0: /* add */ + Read(); + AC = AC + MBR; + if (AC > DMASK) { + AC += 1; + } else; + AC &= DMASK; + inst_ctr.add++; + break; + case 1: /* adx */ + MAR = compute_index(y, XR); + Read(); + AC = AC + MBR; + if (AC > DMASK) { + AC += 1; + } else; + AC &= DMASK; + inst_ctr.adx++; + break; + case 2: /* ldx */ + Read(); + XR = MBR & YMASK; /* load XR[5:17] from C(y[5:17]) */ + XR |= ((MBR & SIGN) >> 4); /* Load XR[4] from C(y[0]) */ + inst_ctr.ldx++; + break; + case 3: /* aux (Augment Index) */ + { + uint32 newY = (y & 0017777) | ((y & SIGN) >> 4); + TRACE_PRINT(ADD_MSG, ("[%06o] AUX: y=%05o, XR=%05o = ", PC-1, newY, XR)); + XR = XR + newY; + TRACE_PRINT(ADD_MSG, ("%05o\n", XR)); + break; + } + inst_ctr.aux++; + case 4: /* llr (Load Live Register) */ + Read(); + LR = MBR; + inst_ctr.llr++; + break; + case 5: /* llx (Load Live Register, Indexed) */ + MAR = compute_index(y, XR); + Read(); + LR = MBR; + inst_ctr.llx++; + break; + case 6: /* lda (Load Accumulator) */ + Read(); + AC = MBR; + inst_ctr.lda++; + break; + case 7: /* lax (Load Accumulator, Indexed) */ + MAR = compute_index(y, XR); + Read(); + AC = MBR; + inst_ctr.lax++; + break; + } + break; + + case 02: /* trn x */ + switch (IR & 07) { + case 0: /* trn (Transfer on Negative AC) */ + if (AC & SIGN) { + TRACE_PRINT(TRN_MSG, ("[%06o] TRN: Transfer taken: PC=%06o\n", PC-1, y)); + PC = MAR; + } + inst_ctr.trn++; + break; + case 1: /* tze (Transfer on +/- Zero) */ + if ((AC == 0777777) || (AC == 0000000)) { + TRACE_PRINT(TRN_MSG, ("[%06o] TZE: Transfer taken: PC=%06o\n", PC-1, y)); + PC = y; + } + inst_ctr.tze++; + break; + case 2: /* tsx (Transfer and set Index) */ + XR = PC & 0017777; /* XR[4] = 0; */ + TRACE_PRINT(TRN_MSG, ("[%06o] TSX: PC=%06o, XR=%05o\n", PC-1, y, XR)); + PC = y; + inst_ctr.tsx++; + break; + case 3: /* tix (Transfer and Index) */ + TRACE_PRINT(TRN_MSG, ("[%06o] TIX: XR=%05o\n", PC-1, XR)); + if ((XR == 037777) || (XR == 000000)) { /* +/- 0, take next instruction */ + TRACE_PRINT(TRN_MSG, ("+/- 0, transfer not taken.\n")); + } else { /* Not +/- 0 */ + if (XR & 0020000) { /* XR[4] == 1 */ + TRACE_PRINT(TRN_MSG, ("XR is negative, transfer taken,")); + XR ++; + } else { /* XR[4] = 0 */ + TRACE_PRINT(TRN_MSG, ("XR is positive, transfer taken,")); + XR --; + } + PC = y; + XR &= 037777; + TRACE_PRINT(TRN_MSG, (" PC=%06o, XR=%05o\n", PC, XR)); + + } + inst_ctr.tix++; + break; + case 4: /* tra (Unconditional Transfer) */ + TRACE_PRINT(TRN_MSG, ("[%06o] TRA: Transfer taken: PC=%06o\n", PC-1, y)); + PC = y; + inst_ctr.tra++; + break; + case 5: /* trx */ + { + int32 newPC; + newPC = compute_index(y, XR); + TRACE_PRINT(TRN_MSG, ("[%06o] TRA: Transfer taken: PC=%06o\n", PC-1, newPC)); + PC = newPC; + } + inst_ctr.trx++; + break; + case 6: /* tlv (Transfer on External Level) */ + TRACE_PRINT(ERROR_MSG, ("[%06o] TODO: Implement TLV\n", PC-1)); + inst_ctr.tlv++; + break; + case 7: /* no-op */ + break; + } + break; + + case 03: /* opr x */ + if ((cpu_unit.flags & UNIT_EXT_INST) == 0) { /* Original instruction set */ + reason = sim_opr_orig(op); + break; + } + + /* I can't find this mentioned in the TX-0 Documentation, but for the + * lro and xro instructions, this must be needed. + */ + MBR = 0; + +/* Cycle 0 */ + if (op & OPR_AMB) { /* 0.7 */ + inst_ctr.amb++; + MBR = AC; + TRACE_PRINT(ORD_MSG, ("[%06o]: AMB: MBR=%06o\n", PC-1, MBR)); + } + + if (op & OPR_CLA) { /* 0.8 */ + inst_ctr.cla++; + AC = 0; + TRACE_PRINT(ORD_MSG, ("[%06o]: CLA: AC=%06o\n", PC-1, AC)); + } + +/* IOS - In / Out Stop */ + /* Check TTI for character. If so, put in LR and set LR bit 0. */ + if (iosta & IOS_TTI) { + int32 rbuf; + rbuf = tti(0,0,0); + TRACE_PRINT(IOS_MSG, ("TTI: character received=%03o\n", rbuf &077)); + LR &= 0266666; /* Clear bits 0,2,5,8,...,17 */ + + LR |= SIGN; /* Set bit 0, character available. */ + LR |= ((rbuf & 001) >> 0) << 15;/* bit 2 */ + LR |= ((rbuf & 002) >> 1) << 12;/* bit 5 */ + LR |= ((rbuf & 004) >> 2) << 9; /* bit 8 */ + LR |= ((rbuf & 010) >> 3) << 6; /* bit 11 */ + LR |= ((rbuf & 020) >> 4) << 3; /* bit 14 */ + LR |= ((rbuf & 040) >> 5) << 0; /* bit 17 */ + } + + switch(op & IOS_MASK) { + case IOS_NOP: + break; + case IOS_TAC: + TRACE_PRINT(IOS_MSG, ("[%06o] TAC %06o\n", PC-1, TAC)); + AC |= TAC; + break; + case IOS_TBR: + TRACE_PRINT(IOS_MSG, ("[%06o] TBR %06o\n", PC-1, TBR)); + MBR |= TBR; + break; + case IOS_PEN: + TRACE_PRINT(IOS_MSG, ("[%06o] Light Pen %01o\n", PC-1, LP)); + AC &= AMASK; + AC |= (LP & 1) << 17; + AC |= (LP & 2) << 16; + AC &= DMASK; + break; + case IOS_SEL: + { /* These are used for Magtape control. + Magtape is compatible with IBM 709. Maybe the SIMH 7090 magtape can be leveraged. */ + int32 CLRA = (op & 0100000); + int32 BINDEC = (op & 020); + int32 device = op & 03; + int32 tape_ord = (op >> 2) & 03; + char *tape_cmd[] = {"Backspace Tape", "Read/Select Tape", "Rewind Tape", "Write/Select Tape" }; + + TRACE_PRINT(ERROR_MSG, ("[%06o] TODO: SEL (magtape)\n", PC-1)); + printf("Device %d: CLRA=%d, BINDEC=%d: %s\n", device, CLRA, BINDEC, tape_cmd[tape_ord]); + } + break; + case IOS_RPF: /* These are used for Magtape control. */ + TRACE_PRINT(IOS_MSG, ("[%06o] RPF %06o\n", PC-1, PF)); + MBR |= PF; + break; + case IOS_SPF: /* These are used for Magtape control. */ + TRACE_PRINT(IOS_MSG, ("[%06o] SPF %06o\n", PC-1, MBR)); + PF = MBR; + break; + case IOS_CPY: /* These are used for Magtape control. */ + TRACE_PRINT(ERROR_MSG, ("[%06o] TODO: CPY\n", PC-1)); + break; + case IOS_R1L: + AC &= 0333333; /* Clear bits 0,3,6,9,12,15 */ + AC |= petr(1, 0, 0); /* Read one line from PETR */ + break; + case IOS_DIS: +#ifdef USE_DISPLAY + LP = dpy (AC); /* Display point on the CRT */ +#endif /* USE_DISPLAY */ + break; + case IOS_R3L: + AC = petr(3, 0, 0); /* Read three lines from PETR */ + break; + case IOS_PRT: + { + uint32 tmpAC = 0; + tmpAC |= ((AC & 0000001) >> 0) << 0; /* bit 17 */ + tmpAC |= ((AC & 0000010) >> 3) << 1; /* bit 14 */ + tmpAC |= ((AC & 0000100) >> 6) << 2; /* bit 11 */ + tmpAC |= ((AC & 0001000) >> 9) << 3; /* bit 8 */ + tmpAC |= ((AC & 0010000) >> 12) << 4; /* bit 5 */ + tmpAC |= ((AC & 0100000) >> 15) << 5; /* bit 2 */ + tto (0, 0, tmpAC & 077); /* Print one character on TTO */ + } + break; + case IOS_P6H: + case IOS_P7H: + { + uint32 tmpAC = 0; + tmpAC |= ((AC & 0000001) >> 0) << 0; /* bit 17 */ + tmpAC |= ((AC & 0000010) >> 3) << 1; /* bit 14 */ + tmpAC |= ((AC & 0000100) >> 6) << 2; /* bit 11 */ + tmpAC |= ((AC & 0001000) >> 9) << 3; /* bit 8 */ + tmpAC |= ((AC & 0010000) >> 12) << 4; /* bit 5 */ + tmpAC |= ((AC & 0100000) >> 15) << 5; /* bit 2 */ + tmpAC &= 0077; + if ((op & IOS_MASK) == IOS_P7H) { + tmpAC |= 0100; /* Punch 7th hole. */ + TRACE_PRINT(ERROR_MSG, ("[%06o] Punch 7 holes\n", PC-1)); + } else { + TRACE_PRINT(ERROR_MSG, ("[%06o] Punch 6 holes\n", PC-1)); + } + ptp (0, 0, tmpAC); /* Punch character on PTP */ + } + break; + case IOS_HLT: + TRACE_PRINT(IOS_MSG, ("[%06o] HALT Instruction\n", PC-1)); + reason = STOP_HALT; + break; + case IOS_CLL: + AC &= 0000777; + break; + case IOS_CLR: + AC &= 0777000; + break; + default: /* Could be ex0-ex7, handle them here. */ + if ((op & IOS_EX_MASK) == 0010000) { + TRACE_PRINT(ERROR_MSG, ("[%06o] TODO: EX%o\n", PC-1, (op >> 9) & 07)); + } + break; + } + +/* Cycle 1 */ + if (op & OPR_COM) { /* 1.2 */ + AC = ~AC; + AC &= DMASK; + TRACE_PRINT(ORD_MSG, ("[%06o]: COM: AC=%06o\n", PC-1, AC)); + inst_ctr.com++; + } + + if ((op & OPR_XMB_MASK) == OPR_XMB) { /* 1.2 XR[5:17] -> MBR[5:17], XR[4] -> MBR[0:4] */ + int32 bit14 = (XR >> 13) & 1; + MBR = XR & YMASK; /* XR[5:17] -> MBR[5:17] */ + MBR |= (bit14 << 17); /* XR[4] -> MBR[0] */ + MBR |= (bit14 << 16); /* XR[4] -> MBR[1] */ + MBR |= (bit14 << 15); /* XR[4] -> MBR[2] */ + MBR |= (bit14 << 14); /* XR[4] -> MBR[3] */ + MBR |= (bit14 << 13); /* XR[4] -> MBR[4] */ + + TRACE_PRINT(ORD_MSG, ("[%06o]: XMB: XR=%05o, MBR=%06o\n", PC-1, XR, MBR)); + inst_ctr.xmb++; + } + + if ((op & OPR_LOG_MASK) == OPR_ANB) { /* 1.2-2 */ + MBR &= LR; + TRACE_PRINT(ORD_MSG, ("[%06o]: ANB: MBR=%06o\n", PC-1, MBR)); + inst_ctr.anb++; + } + + if ((op & OPR_LOG_MASK) == OPR_ORB) { /* 1.3 */ + MBR |= LR; + TRACE_PRINT(ORD_MSG, ("[%06o]: ORB: MBR=%06o\n", PC-1, MBR)); + inst_ctr.orb++; + } + + tempLR = LR; /* LR temporary storage in case both LMB and MBL are set (swap LR<->MBR) */ + if ((op & OPR_MBL_MASK) == OPR_MBL) { /* 1.4 */ + LR = MBR; + TRACE_PRINT(ORD_MSG, ("[%06o]: MBL: LR=%06o, prev LR=%06o\n", PC-1, LR, tempLR)); + inst_ctr.mbl++; + } + + if ((op & OPR_LMB_MASK) == OPR_LMB) { /* 1.4 */ + MBR = tempLR; + TRACE_PRINT(ORD_MSG, ("[%06o]: LMB: LR=%06o, MBR=%06o\n", PC-1, LR, MBR)); + inst_ctr.lmb++; + } + + if (op & OPR_PAD) { /* 1.5 Partial Add (XOR): AC = MBR ^ AC */ + if (op & OPR_CRY) { /* 1.7 */ + TRACE_PRINT(ORD_MSG, ("[%06o] PAD+CRY: AC=%06o, MBR=%06o = ", PC-1, AC, MBR)); + AC = AC + MBR; + if (AC > DMASK) { + AC += 1; + } else; + AC &= DMASK; + TRACE_PRINT(ORD_MSG, ("%06o\n", AC)); + } else { + TRACE_PRINT(ORD_MSG, ("[%06o] PAD: AC=%06o, MBR=%06o\n", PC-1, AC, MBR)); + AC = AC ^ MBR; + AC &= DMASK; + TRACE_PRINT(ORD_MSG, ("[%06o] PAD: Check: AC=%06o\n", PC-1, AC)); + } + inst_ctr.pad++; + } + + if ((op & OPR_SHF_MASK) == OPR_CYR) { /* 1.6 */ + int32 bit17; + bit17 = (AC & 1) << 17; + AC >>= 1; + AC |= bit17; + TRACE_PRINT(ORD_MSG, ("[%06o]: CYR: AC=%06o\n", PC-1, AC)); + inst_ctr.cyr++; + } + + if ((op & OPR_SHF_MASK) == OPR_SHR) { /* 1.6 Shift AC Right, preserve bit 0. */ + int32 bit0; + bit0 = AC & 0400000; + AC = AC >> 1; + AC |= bit0; + TRACE_PRINT(ORD_MSG, ("[%06o]: SHR: AC=%06o\n", PC-1, AC)); + inst_ctr.shr++; + } + + if (op & OPR_CRY) { /* 1.7 */ + if (op & OPR_PAD) { + } else { + TRACE_PRINT(ERROR_MSG, ("[%06o] CRY: TODO: AC=%06o\n", PC-1, AC)); + inst_ctr.cry++; + } + } + + if ((op & OPR_MBX_MASK) == OPR_MBX) { /* 1.8 MBR[5:17] -> XR[5:17], MBR[0] -> XR[4] */ + int32 tempXR; + tempXR = MBR & YMASK; + tempXR |= (((MBR >> 17) & 1) << 13); + + XR = tempXR; + TRACE_PRINT(ORD_MSG, ("[%06o]: MBX: MBR=%06o, XR=%06o\n", PC-1, MBR, XR)); + inst_ctr.mbx++; + } + } + + tx0_dump_regs("END"); + +#ifdef USE_FPC + fpc_MA = MAR; /* shadow MAR for FPC */ +#endif + + } /* end while */ + pcq_r->qptr = pcq_p; /* update pc q ptr */ + + TRACE_PRINT(COUNTERS_MSG, ("Instruction Counters\nSTO=%d, STX=%d, SXA=%d, ADO=%d, SLR=%d, SLX=%d, STZ=%d\n", + inst_ctr.sto, inst_ctr.stx, inst_ctr.sxa, inst_ctr.ado, inst_ctr.slr, inst_ctr.slx, inst_ctr.stz)); + TRACE_PRINT(COUNTERS_MSG, ("ADD=%d, ADX=%d, LDX=%d, AUX=%d, LLR=%d, LLX=%d, LDA=%d, LAX=%d\n", + inst_ctr.add, inst_ctr.adx, inst_ctr.ldx, inst_ctr.aux, inst_ctr.llr, inst_ctr.llx, inst_ctr.lda, inst_ctr.lax)); + TRACE_PRINT(COUNTERS_MSG, ("TRN=%d, TZE=%d, TSX=%d, TIX=%d, TRA=%d, TRX=%d, TLV=%d\n", + inst_ctr.trn, inst_ctr.tze, inst_ctr.tsx, inst_ctr.tix, inst_ctr.tra, inst_ctr.trx, inst_ctr.tlv)); + TRACE_PRINT(COUNTERS_MSG, ("CLA=%d, AMB=%d, CYR=%d, SHR=%d, MBL=%d, XMB=%d, COM=%d, PAD=%d, CRY=%d, ANB=%d, ORB=%d, LMB=%d, MBX=%d\n", + inst_ctr.cla, inst_ctr.amb, inst_ctr.cyr, inst_ctr.shr, inst_ctr.mbl, inst_ctr.xmb, inst_ctr.com, inst_ctr.pad, inst_ctr.cry, inst_ctr.anb, inst_ctr.orb, inst_ctr.lmb, inst_ctr.mbx)); + + return reason; +} + +/* Read and write memory */ +t_stat Read (void) +{ + MAR &= (MEMSIZE - 1); + MBR = M[MAR]; + MBR &= DMASK; + return SCPE_OK; +} + +t_stat Write (void) +{ + MAR &= (MEMSIZE - 1); + MBR &= DMASK; + M[MAR] = MBR; + return SCPE_OK; +} + +/* Reset routine */ + +t_stat cpu_reset (DEVICE *dptr) +{ + ios = 0; + PF = 0; + MAR = 0; + MBR = 0; + pcq_r = find_reg ("PCQ", NULL, dptr); + + if (pcq_r) { + pcq_r->qptr = 0; + } else { + return SCPE_IERR; + } + + sim_brk_types = sim_brk_dflt = SWMASK ('E'); + + return SCPE_OK; +} + +/* Memory examine */ + +t_stat cpu_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw) +{ + if (addr >= MEMSIZE) return SCPE_NXM; + if (vptr != NULL) *vptr = M[addr] & DMASK; + + return SCPE_OK; +} + +/* Memory deposit */ + +t_stat cpu_dep (t_value val, t_addr addr, UNIT *uptr, int32 sw) +{ + if (addr >= MEMSIZE) return SCPE_NXM; + + M[addr] = val & DMASK; + + return SCPE_OK; +} + +/* Change memory size */ + +t_stat cpu_set_size (UNIT *uptr, int32 val, char *cptr, void *desc) +{ + int32 mc = 0; + uint32 i; + + if ((val <= 0) || (val > MAXMEMSIZE) || ((val & 07777) != 0)) + return SCPE_ARG; + for (i = val; i < MEMSIZE; i++) mc = mc | M[i]; + if ((mc != 0) && (!get_yn ("Really truncate memory [N]?", FALSE))) + return SCPE_OK; + MEMSIZE = val; + for (i = MEMSIZE; i < MAXMEMSIZE; i++) M[i] = 0; + return SCPE_OK; +} + +/* Change CPU Mode (Normal, Test, Readin) */ + +t_stat cpu_set_mode (UNIT *uptr, int32 val, char *cptr, void *desc) +{ + if (val == UNIT_MODE_TEST) { + mode_tst = 1; + mode_rdin = 0; + } else if (val == UNIT_MODE_READIN) { + mode_tst = 1; + mode_rdin = 1; + } else { /* Normal Mode */ + mode_tst = 0; + mode_rdin = 0; + } + + return SCPE_OK; +} + + +/* Set TX-0 with Extended Instruction Set */ + +t_stat cpu_set_ext (UNIT *uptr, int32 val, char *cptr, void *desc) +{ + printf("Set CPU Extended Mode\n"); + return SCPE_OK; +} + +t_stat cpu_set_noext (UNIT *uptr, int32 val, char *cptr, void *desc) +{ + printf("Set CPU Non-Extended Mode\n"); + return SCPE_OK; +} + +int32 cpu_get_mode (void) +{ + return (cpu_unit.flags & UNIT_EXT_INST); +} + + + +/* Set history */ + +t_stat cpu_set_hist (UNIT *uptr, int32 val, char *cptr, void *desc) +{ +int32 i, lnt; +t_stat r; + +if (cptr == NULL) { + for (i = 0; i < hst_lnt; i++) hst[i].pc = 0; + hst_p = 0; + return SCPE_OK; + } +lnt = (int32) get_uint (cptr, 10, HIST_MAX, &r); +if ((r != SCPE_OK) || (lnt && (lnt < HIST_MIN))) return SCPE_ARG; +hst_p = 0; +if (hst_lnt) { + free (hst); + hst_lnt = 0; + hst = NULL; + } +if (lnt) { + hst = (InstHistory *) calloc (lnt, sizeof (InstHistory)); + if (hst == NULL) return SCPE_MEM; + hst_lnt = lnt; + } +return SCPE_OK; +} + +/* Show history */ + +t_stat cpu_show_hist (FILE *st, UNIT *uptr, int32 val, void *desc) +{ +int32 ov, pf, op, k, di, lnt; +char *cptr = (char *) desc; +t_stat r; +t_value sim_eval; +InstHistory *h; + +if (hst_lnt == 0) return SCPE_NOFNC; /* enabled? */ +if (cptr) { + lnt = (int32) get_uint (cptr, 10, hst_lnt, &r); + if ((r != SCPE_OK) || (lnt == 0)) return SCPE_ARG; + } +else lnt = hst_lnt; +di = hst_p - lnt; /* work forward */ +if (di < 0) di = di + hst_lnt; +fprintf (st, "PC OV AC IO PF EA IR\n\n"); +for (k = 0; k < lnt; k++) { /* print specified */ + h = &hst[(++di) % hst_lnt]; /* entry pointer */ + if (h->pc & HIST_PC) { /* instruction? */ + ov = (h->ovac >> HIST_V_SHF) & 1; /* overflow */ + pf = 0; + op = ((h->ir >> 13) & 037); /* get opcode */ + fprintf (st, "%06o %o %06o %06o %03o ", + h->pc & AMASK, ov, h->ovac & DMASK, h->pfio & DMASK, pf); + if ((op < 032) && (op != 007)) /* mem ref instr */ + fprintf (st, "%06o ", h->ea); + else fprintf (st, " "); + sim_eval = h->ir; + if ((fprint_sym (st, h->pc & AMASK, &sim_eval, &cpu_unit, SWMASK ('M'))) > 0) + fprintf (st, "(undefined) %06o", h->ir); + else if (op < 030) /* mem ref instr */ + fprintf (st, " [%06o]", h->opnd); + fputc ('\n', st); /* end line */ + } /* end else instruction */ + } /* end for */ +return SCPE_OK; +} + +/* set "test switches"; from display code */ +void +cpu_set_switches(unsigned long bits) +{ + /* just what we want; smaller CPUs might want to shift down? */ + TAC = bits; +} + +unsigned long +cpu_get_switches(void) +{ + return TAC; +} + +t_stat sim_load(FILE *fileref, char *cptr, char *fnam, int flag) { + uint32 cnt = 0, word; + t_addr j, lo, hi, sz, sz_words; + char *result; + + if (flag) { /* Dump to file. */ + result = get_range(NULL, cptr, &lo, &hi, 8, 0xFFFF, 0); + if (result == NULL) return SCPE_ARG; + + for (j = lo; j <= hi; j++) { + if (sim_fwrite(&j, 4, 1, fileref) == 0) return SCPE_IOERR; + if (sim_fwrite(&M[j], 4, 1, fileref) == 0) return SCPE_IOERR; + } + } else { + lo = strtotv(cptr, &result, 8) & 0xFFFF; + sz = sim_fsize(fileref); + sz_words = sz / 4; + for (j = lo; j < sz_words; j++) { + sim_fread(&word, 4, 1, fileref); + M[j] = word; + } + } + + printf("%d words %s [%06o - %06o].\n", j - lo, flag ? "dumped" : "loaded", lo, j-1); + + return SCPE_OK; +} + +/* +Original Operate-class instruction micro orders for the 1956 TX-0 Instruction Set + + Operate Fields + -------------- + --1 --- --- --- --- --- CLL 0.8 + --- 1-- --- --- --- --- CLR 0.8 + --- -10 --- --- --- --- IOS 0.8 + --- -11 --- --- --- --- HLT 1.8 + --- --- 111 --- --- --- P7H 0.8 + --- --- 110 --- --- --- P6H 0.8 + --- --- 100 --- --- --- PNT 0.8 + --- --- 001 --- --- --- R1C 0.8 + --- --- 011 --- --- --- R3C 0.8 + --- --- 010 --- --- --- DIS 0.8 + --- --- --- 10- --- --- SHR 1.4 + --- --- --- 11- --- --- CYR 1.4 + --- --- --- 01- --- --- MLR 1.3 + --- --- --- --1 --- 0-- PEN 1.1 + --- --- --- --0 --- 1-- TAC 1.1 + --- --- --- --- 1-- --- COM 1.2 + --- --- --- --- -1- --- PAD 1.4 + --- --- --- --- --1 --- CRY 1.7 + --- --- --- --- --- -01 AMB 1.2 AC -> MBR + --- --- --- --- --- -11 TBR 1.2 TBR -> MBR + --- --- --- --- --- -10 LMB 1.3 LR -> MBR +*/ +#define OOPR_CLL 0100000 +#define OOPR_CLR 0040000 +#define OOPR_IOS 0020000 +#define OOPR_HLT 0030000 +#define OOPR_IOS_MASK 0007000 +#define OOPR_P7H 0007000 +#define OOPR_P6H 0006000 +#define OOPR_PNT 0004000 +#define OOPR_R3C 0003000 +#define OOPR_DIS 0002000 +#define OOPR_R1C 0001000 + +#define OOPR_SHF_MASK 0000300 +#define OOPR_SHR 0000400 +#define OOPR_CYR 0000300 +#define OOPR_MLR 0000200 + +#define OOPR_PEN_MASK 0000104 +#define OOPR_PEN 0000100 + +#define OOPR_TAC_MASK 0000104 +#define OOPR_TAC 0000004 + +#define OOPR_COM 0000040 +#define OOPR_PAD 0000020 +#define OOPR_CRY 0000010 + +#define OOPR_AMB_MASK 0000007 +#define OOPR_AMB 0000001 +#define OOPR_TBR 0000003 +#define OOPR_LMB 0000002 + +t_stat sim_opr_orig(int32 op) +{ + t_stat reason = SCPE_OK; + + if (op & OOPR_CLL) { /* cll 0.8 Clear the left nine digital positions of the AC */ + AC &= 0000777; + TRACE_PRINT(ORD_MSG, ("[%06o]: CLL\n", PC-1)); + } + if (op & OOPR_CLR) { /* clr 0.8 Clear the right nine digital positions of the AC */ + AC &= 0777000; + TRACE_PRINT(ORD_MSG, ("[%06o]: CLR\n", PC-1)); + } + +/* IOS - In / Out Stop */ + /* Check TTI for character. If so, put in LR and set LR bit 0. */ + if (iosta & IOS_TTI) { + int32 rbuf; + rbuf = tti(0,0,0); + TRACE_PRINT(IOS_MSG, ("TTI: character received='%c'\n", rbuf &077)); + printf("TTI: character received='%c'\n", rbuf &077); + LR &= 0266666; /* Clear bits 0,2,5,8,...,17 */ + + LR |= SIGN; /* Set bit 0, character available. */ + LR |= ((rbuf & 001) >> 0) << 15;/* bit 2 */ + LR |= ((rbuf & 002) >> 1) << 12;/* bit 5 */ + LR |= ((rbuf & 004) >> 2) << 9; /* bit 8 */ + LR |= ((rbuf & 010) >> 3) << 6; /* bit 11 */ + LR |= ((rbuf & 020) >> 4) << 3; /* bit 14 */ + LR |= ((rbuf & 040) >> 5) << 0; /* bit 17 */ + } + + + + if ((op & OOPR_HLT) == OOPR_IOS) { /* I/O 0.8 IOS */ + TRACE_PRINT(IOS_MSG, ("[%06o] I/O Operation\n", PC-1)); + + switch (op & OOPR_IOS_MASK) { + case OOPR_P7H: + case OOPR_P6H: + { + uint32 tmpAC = 0; + tmpAC |= ((AC & 0000001) >> 0) << 0; /* bit 17 */ + tmpAC |= ((AC & 0000010) >> 3) << 1; /* bit 14 */ + tmpAC |= ((AC & 0000100) >> 6) << 2; /* bit 11 */ + tmpAC |= ((AC & 0001000) >> 9) << 3; /* bit 8 */ + tmpAC |= ((AC & 0010000) >> 12) << 4; /* bit 5 */ + tmpAC |= ((AC & 0100000) >> 15) << 5; /* bit 2 */ + tmpAC &= 0077; + if ((op & OOPR_IOS_MASK) == OOPR_P7H) { + tmpAC |= 0100; /* Punch 7th hole. */ + TRACE_PRINT(ERROR_MSG, ("[%06o] Punch 7 holes\n", PC-1)); + } else { + TRACE_PRINT(ERROR_MSG, ("[%06o] Punch 6 holes\n", PC-1)); + } + ptp (0, 0, tmpAC); /* Punch one character on TTO */ + } + break; + case OOPR_PNT: + { + uint32 tmpAC = 0; + tmpAC |= ((AC & 0000001) >> 0) << 0; /* bit 17 */ + tmpAC |= ((AC & 0000010) >> 3) << 1; /* bit 14 */ + tmpAC |= ((AC & 0000100) >> 6) << 2; /* bit 11 */ + tmpAC |= ((AC & 0001000) >> 9) << 3; /* bit 8 */ + tmpAC |= ((AC & 0010000) >> 12) << 4; /* bit 5 */ + tmpAC |= ((AC & 0100000) >> 15) << 5; /* bit 2 */ + tto (0, 0, tmpAC & 077); /* Print one character on TTO */ + } + break; + case OOPR_R3C: + AC = petr(3, 0, 0); + break; + case OOPR_R1C: + AC &= 0333333; /* Clear bits 0,3,6,9,12,15 */ + AC |= petr(1, 0, 0); + break; + case OOPR_DIS: +#ifdef USE_DISPLAY + LP = dpy (AC); /* Display point on the CRT */ +#endif /* USE_DISPLAY */ + break; + } + } + +/* 1.1 TAC and PEN */ + if ((op & OOPR_PEN_MASK) == OOPR_PEN) { /* pen 1.1 Read the light pen flip flops 1 and 2 into AC0 and AC1 */ + TRACE_PRINT(IOS_MSG, ("[%06o] Light Pen %01o\n", PC-1, LP)); + AC &= AMASK; + AC |= (LP & 1) << 17; + AC |= (LP & 2) << 16; + AC &= DMASK; + } + + if ((op & OOPR_TAC_MASK) == OOPR_TAC) { /* tac 1.1 Insert a one in each digital position of the AC whereever there is a one in the corresponding digital position of the TAC */ + TRACE_PRINT(IOS_MSG, ("[%06o] TAC %06o\n", PC-1, TAC)); + AC |= TAC; + } + + /* 1.2: COM, AMB, TBR */ + if (op & OOPR_COM) { /* com 1.2 Complement every digit in the accumulator */ + AC = ~AC; + inst_ctr.com++; + } + + switch (op & OOPR_AMB_MASK) { + case OOPR_AMB: + inst_ctr.amb++; + MBR = AC; + break; + case OOPR_TBR: + TRACE_PRINT(IOS_MSG, ("[%06o] TBR %06o\n", PC-1, TBR)); + MBR |= TBR; + break; + case OOPR_LMB: + MBR = LR; + inst_ctr.lmb++; + break; + } + + /* 1.3, 1.4: can these happen together? */ + switch (op & OOPR_SHF_MASK) { + case OOPR_MLR: + LR = MBR; + inst_ctr.mbl++; + break; + case OOPR_SHR: /* Shift AC Right, preserve bit 0. */ + { + int32 bit0; + bit0 = AC & 0400000; + AC = AC >> 1; + AC |= bit0; + inst_ctr.shr++; + break; + } + case OOPR_CYR: /* cyr 1.4 Cycle the AC right one digital position (AC17 -> AC0) */ + { + int32 bit17; + bit17 = (AC & 1) << 17; + AC >>= 1; + AC |= bit17; + inst_ctr.cyr++; + } + break; + } + + if (op & OOPR_PAD) { /* 1.5 Partial Add (XOR): AC = MBR ^ AC */ + if (op & OOPR_CRY) { /* 1.7 */ + TRACE_PRINT(ORD_MSG, ("[%06o] PAD+CRY: AC=%06o, MBR=%06o = ", PC-1, AC, MBR)); + AC = AC + MBR; + if (AC & 01000000) { + AC += 1; + } else; + AC &= DMASK; + TRACE_PRINT(ORD_MSG, ("%06o\n", AC)); + inst_ctr.cry++; + } else { + TRACE_PRINT(ORD_MSG, ("[%06o] PAD: AC=%06o, MBR=%06o\n", PC-1, AC, MBR)); + AC = AC ^ MBR; + AC &= DMASK; + TRACE_PRINT(ORD_MSG, ("[%06o] PAD: Check: AC=%06o\n", PC-1, AC)); + } + inst_ctr.pad++; + } + + if (op & OOPR_CRY) { /* 1.7 */ + if (op & OOPR_PAD) { + } else { + TRACE_PRINT(ERROR_MSG, ("[%06o] CRY: TODO: AC=%06o\n", PC-1, AC)); + inst_ctr.cry++; + } + } + + if ((op & OOPR_HLT) == OOPR_HLT) { /* hlt 1.8 Halt the computer */ + TRACE_PRINT(IOS_MSG, ("[%06o] HALT Instruction\n", PC-1)); + reason = STOP_HALT; + } + + return reason; +} diff --git a/TX-0/tx0_defs.h b/TX-0/tx0_defs.h new file mode 100644 index 00000000..58073561 --- /dev/null +++ b/TX-0/tx0_defs.h @@ -0,0 +1,93 @@ +/************************************************************************* + * * + * $Id: tx0_defs.h 2059 2009-02-23 05:59:14Z hharte $ * + * * + * Copyright (c) 2009 Howard M. Harte. * + * Based on pdp1_defs.h, Copyright (c) 1993-2006, Robert M. Supnik * + * * + * Permission is hereby granted, free of charge, to any person obtaining * + * a copy of this software and associated documentation files (the * + * "Software"), to deal in the Software without restriction, including * + * without limitation the rights to use, copy, modify, merge, publish, * + * distribute, sublicense, and/or sell copies of the Software, and to * + * permit persons to whom the Software is furnished to do so, subject to * + * the following conditions: * + * * + * The above copyright notice and this permission notice shall be * + * included in all copies or substantial portions of the Software. * + * * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * + * NONINFRINGEMENT. IN NO EVENT SHALL HOWARD M. HARTE BE LIABLE FOR ANY * + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * + * * + * Except as contained in this notice, the name of Howard M. Harte shall * + * not be used in advertising or otherwise to promote the sale, use or * + * other dealings in this Software without prior written authorization * + * of Howard M. Harte. * + * * + * Module Description: * + * cpu TX-0 Central Processor * + * * + * Environment: * + * User mode only * + * * + *************************************************************************/ + +#ifndef _PDP1_DEFS_H_ +#define _PDP1_DEFS_H_ 0 + +#include "sim_defs.h" + +/* Simulator stop codes */ +#define STOP_RSRV 1 /* must be 1 */ +#define STOP_HALT 2 /* HALT */ +#define STOP_IBKPT 3 /* breakpoint */ + +/* Memory */ +#define ASIZE 16 /* address bits */ +#define MAXMEMSIZE (1u << ASIZE) /* max mem size */ +#define AMASK (MAXMEMSIZE - 1) /* address mask */ +#define MEMSIZE (cpu_unit.capac) /* actual memory size */ +#define MEM_ADDR_OK(x) (((uint32) (x)) < MEMSIZE) + +/* Architectural constants */ +#define SIGN 0400000 /* sign */ +#define DMASK 0777777 /* data mask */ +#define YMASK 0017777 /* "Y" Mask for address calculation (13 bits) */ + +/* I/O status flags */ +#define IOS_V_LPN 17 /* light pen */ +#define IOS_V_PETR 16 /* paper tape reader */ +#define IOS_V_TTO 15 /* typewriter out */ +#define IOS_V_TTI 14 /* typewriter in */ +#define IOS_V_PTP 13 /* paper tape punch */ +#define IOS_V_DRM 12 /* drum */ +#define IOS_V_SQB 11 /* sequence break */ +#define IOS_V_PNT 3 /* print done */ +#define IOS_V_SPC 2 /* space done */ +#define IOS_V_DCS 1 /* data comm sys */ +#define IOS_V_DRP 0 /* parallel drum busy */ + +#define IOS_LPN (1 << IOS_V_LPN) +#define IOS_PETR (1 << IOS_V_PETR) +#define IOS_TTO (1 << IOS_V_TTO) +#define IOS_TTI (1 << IOS_V_TTI) +#define IOS_PTP (1 << IOS_V_PTP) +#define IOS_DRM (1 << IOS_V_DRM) +#define IOS_SQB (1 << IOS_V_SQB) +#define IOS_PNT (1 << IOS_V_PNT) +#define IOS_SPC (1 << IOS_V_SPC) +#define IOS_DCS (1 << IOS_V_DCS) +#define IOS_DRP (1 << IOS_V_DRP) + +#define UNIT_V_MODE (UNIT_V_UF + 0) +#define UNIT_MODE (3 << UNIT_V_MODE) +#define UNIT_MODE_READIN (3 << UNIT_V_MODE) +#define UNIT_MODE_TEST (1 << UNIT_V_MODE) + + +#endif diff --git a/TX-0/tx0_diag.txt b/TX-0/tx0_diag.txt new file mode 100644 index 00000000..e7fdabd0 --- /dev/null +++ b/TX-0/tx0_diag.txt @@ -0,0 +1,16 @@ + +Programs that are known to work well: + +bin_tic-tac-toe_new_code_12-16-61.bin, seems to fully work: + sim> boot petr + sim> g (will halt with 205200 in LR) + sim> e lr + LR: 205200 + sim> g (again to start game.) +bin_tstDisplay.bin, makes a diagonal line on the DPY +bin_lightGunTst.bin, can draw on screen with light pen. + + +bin_newMouse_3-22-66.bin - These kind of work, but mouse gives up easy +bin_newMouse_8-14-61.bin - and can crash on complex mazes. Sim bug + somewhere. diff --git a/TX-0/tx0_dpy.c b/TX-0/tx0_dpy.c new file mode 100644 index 00000000..09d193b2 --- /dev/null +++ b/TX-0/tx0_dpy.c @@ -0,0 +1,139 @@ +/************************************************************************* + * * + * $Id: tx0_dpy.c 2060 2009-02-24 06:49:07Z hharte $ * + * * + * Copyright (c) 2009-2012, Howard M. Harte * + * Copyright (c) 2004, Philip L. Budne * + * Copyright (c) 1993-2003, Robert M. Supnik * + * * + * Permission is hereby granted, free of charge, to any person obtaining * + * a copy of this software and associated documentation files (the * + * "Software"), to deal in the Software without restriction, including * + * without limitation the rights to use, copy, modify, merge, publish, * + * distribute, sublicense, and/or sell copies of the Software, and to * + * permit persons to whom the Software is furnished to do so, subject to * + * the following conditions: * + * * + * The above copyright notice and this permission notice shall be * + * included in all copies or substantial portions of the Software. * + * * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * + * NONINFRINGEMENT. IN NO EVENT SHALL HOWARD M. HARTE BE LIABLE FOR ANY * + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * + * * + * Except as contained in this notice, the name of Howard M. Harte shall * + * not be used in advertising or otherwise to promote the sale, use or * + * other dealings in this Software without prior written authorization * + * of Howard M. Harte. * + * * + * Module Description: * + * TX-0 display simulator * + * * + * Environment: * + * User mode only * + * * + *************************************************************************/ + +#ifdef USE_DISPLAY +#include "tx0_defs.h" +#include "display/display.h" + +extern int32 ios, iosta, PF; +extern int32 stop_inst; +extern int32 PEN_HIT; + +t_stat dpy_svc (UNIT *uptr); +t_stat dpy_reset (DEVICE *dptr); + +/* DPY data structures + dpy_dev DPY device descriptor + dpy_unit DPY unit + dpy_reg DPY register list +*/ + +#define CYCLE_TIME 5 /* 5us memory cycle */ +#define DPY_WAIT (50/CYCLE_TIME) /* 50us */ + +UNIT dpy_unit = { + UDATA (&dpy_svc, UNIT_ATTABLE, 0), DPY_WAIT }; + +DEVICE dpy_dev = { + "DPY", &dpy_unit, NULL, NULL, + 1, 10, 31, 1, 8, 8, + NULL, NULL, &dpy_reset, + NULL, NULL, NULL, + NULL, DEV_DISABLE }; + +/* Display Routine */ +int32 dpy (int32 ac) +{ + int32 pen_hit; + int32 x, y; + int level; + + if (dpy_dev.flags & DEV_DIS) /* disabled? */ + return SCPE_UDIS; + + x = (ac >> 9) & 0777; /* X = high nine bits of AC */ + y = (ac & 0777); /* Y = low nine bits of AC */ + + /* + * convert one's complement -255..+255 center origin + * to 0..511 (lower left origin) + */ + if (x & 0400) + x ^= 0400; + else + x += 255; + if (y & 0400) + y ^= 0400; + else + y += 255; + + level = DISPLAY_INT_MAX; /* Maximum intensity */ + + if (display_point(x,y,level,0)) { + /* here with light pen hit */ + PF = PF | 010; /* set prog flag 3 */ + pen_hit = 1; + + } else { + pen_hit = 0; + } + + sim_activate (&dpy_unit, dpy_unit.wait); /* activate */ + + return pen_hit; +} + +/* + * Unit service routine + * + * Under X11 this includes polling for events, so it can't be + * call TOO infrequently... + */ +t_stat dpy_svc (UNIT *uptr) +{ + display_age(dpy_unit.wait*CYCLE_TIME, 1); + sim_activate (&dpy_unit, dpy_unit.wait); /* requeue! */ + return SCPE_OK; +} + +/* Reset routine */ + +t_stat dpy_reset (DEVICE *dptr) +{ + display_init(DIS_TX0, RES_FULL); + display_reset(); + iosta = iosta & ~(IOS_PNT | IOS_SPC); /* clear flags */ + sim_cancel (&dpy_unit); /* deactivate unit */ + return SCPE_OK; +} + +#else /* USE_DISPLAY not defined */ +char tx0_dpy_unused; /* sometimes empty object modules cause problems */ +#endif /* USE_DISPLAY not defined */ diff --git a/TX-0/tx0_stddev.c b/TX-0/tx0_stddev.c new file mode 100644 index 00000000..d90d6be8 --- /dev/null +++ b/TX-0/tx0_stddev.c @@ -0,0 +1,640 @@ +/************************************************************************* + * * + * $Id: tx0_stddev.c 2063 2009-02-25 07:37:57Z hharte $ * + * * + * Copyright (c) 2009-2012 Howard M. Harte. * + * Based on pdp1_stddev.c, Copyright (c) 1993-2006, Robert M. Supnik * + * * + * Permission is hereby granted, free of charge, to any person obtaining * + * a copy of this software and associated documentation files (the * + * "Software"), to deal in the Software without restriction, including * + * without limitation the rights to use, copy, modify, merge, publish, * + * distribute, sublicense, and/or sell copies of the Software, and to * + * permit persons to whom the Software is furnished to do so, subject to * + * the following conditions: * + * * + * The above copyright notice and this permission notice shall be * + * included in all copies or substantial portions of the Software. * + * * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * + * NONINFRINGEMENT. IN NO EVENT SHALL HOWARD M. HARTE BE LIABLE FOR ANY * + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * + * * + * Except as contained in this notice, the name of Howard M. Harte shall * + * not be used in advertising or otherwise to promote the sale, use or * + * other dealings in this Software without prior written authorization * + * of Howard M. Harte. * + * * + * Module Description: * + * TX-0 Standard Devices * + * * + * Environment: * + * User mode only * + * * + *************************************************************************/ + +/* + petr paper tape reader + ptp paper tape punch + tti keyboard + tto teleprinter + + Note: PTP timeout must be >10X faster than TTY output timeout for Macro + to work correctly! +*/ + +#include "tx0_defs.h" +#include "sim_tmxr.h" + +#define FLEXO_STOP 061 /* stop code */ +#define FLEXO_UC 071 +#define FLEXO_LC 075 +#define UC_V 6 /* upper case */ +#define UC (1 << UC_V) +#define BOTH (1 << (UC_V + 1)) /* both cases */ +#define CW (1 << (UC_V + 2)) /* char waiting */ +#define TT_WIDTH 077 +#define UNIT_V_ASCII (UNIT_V_UF + 0) /* ASCII/binary mode */ +#define UNIT_ASCII (1 << UNIT_V_ASCII) +#define PETR_LEADER 20 /* ASCII leader chars */ + +#define TRACE_PRINT(dev, level, args) if(dev.dctrl & level) { \ + printf args; \ + } + +int32 petr_state = 0; +int32 petr_wait = 0; +int32 petr_stopioe = 0; +int32 petr_uc = 0; /* upper/lower case */ +int32 petr_hold = 0; /* holding buffer */ +int32 petr_leader = PETR_LEADER; /* leader count */ +int32 ptp_stopioe = 0; +int32 tti_hold = 0; /* tti hold buf */ +int32 tty_buf = 0; /* tty buffer */ +int32 tty_uc = 0; /* tty uc/lc */ +int32 tto_sbs = 0; + +extern int32 ios, iosta; +extern int32 PF, IR, PC, TA; +extern int32 M[]; + +t_stat petr_svc (UNIT *uptr); +t_stat ptp_svc (UNIT *uptr); +t_stat tti_svc (UNIT *uptr); +t_stat tto_svc (UNIT *uptr); +t_stat petr_reset (DEVICE *dptr); +t_stat ptp_reset (DEVICE *dptr); +t_stat tty_reset (DEVICE *dptr); +t_stat petr_boot (int32 unitno, DEVICE *dptr); +t_stat petr_attach (UNIT *uptr, char *cptr); + +/* Character translation tables */ + +int32 flexo_to_ascii[128] = { +/*00*/ 0, 0, 'e', '8', 0, '|', 'a', '3', /* lower case */ +/*10*/ ' ', '=', 's', '4', 'i', '+', 'u', '2', +/*20*/ 0, '.', 'd', '5', 'r', '1', 'j', '7', +/*30*/ 'n', ',', 'f', '6', 'c', '-', 'k', 0, +/*40*/ 't', 0, 'z', '\b','l', '\t','w', 0, +/*50*/ 'h', '\r','y', 0, 'p', 0, 'q', 0, +/*60*/ 'o', '*', 'b', 0, 'g', 0, '9', 0, +/*70*/ 'm', 0, 'x', 0, 'v', 0, '0', 0, +/*00*/ 0, 0, 'E', '8', 0, '_', 'A', '3', /* upper case */ +/*10*/ ' ', ':', 'S', '4', 'I', '/', 'U', '2', +/*20*/ 0, ')', 'D', '5', 'R', '1', 'J', '7', +/*30*/ 'N', '(', 'F', '6', 'C', '-', 'K', 0, +/*40*/ 'T', 0, 'Z', '\b','L', '\t','W', 0, +/*50*/ 'H', '\r','Y', 0, 'P', 0, 'Q', 0, +/*60*/ 'O', '*', 'B', 0, 'G', 0, '9', 0, +/*70*/ 'M', 0, 'X', 0, 'V', 0, '0', 0, + }; + +int32 ascii_to_flexo[128] = { +/*00*/ 0, 0, 0, BOTH+061, 0, 0, 0, 0, /* STOP mapped to ^C */ +/*10*/ BOTH+043, BOTH+045, 0, 0, 0, BOTH+051, 0, 0, +/*20*/ 0, 0, 0, 0, 0, 0, 0, 0, +/*30*/ 0, 0, 0, BOTH+020, 0, 0, 0, 0, /* Color Shift mapped to ESC */ +/*40*/ BOTH+010, 0, 0, 0, 0, 0, 0, 0, /* " ", */ +/*50*/ UC+021, UC+031, 021, 015, 031, UC+035, UC+011, UC+015, /* ()*+,-./ */ +/*60*/ 076, 025, 017, 007, 013, 023, 033, 027, /* 0-7 */ +/*70*/ 003, 066, 0, 0, 0, 011, 0, 0, /* 89:;<=>? */ +/*00*/ 040, UC+006, UC+062, UC+034, UC+022, UC+002, UC+032, UC+064, /* A-G */ +/*10*/ UC+050, UC+014, UC+026, UC+036, UC+044, UC+070, UC+030, UC+060, /* H-O */ +/*20*/ UC+054, UC+056, UC+024, UC+012, 040, 016, 074, 046, /* P-W */ +/*30*/ UC+072, UC+052, UC+042, 0, 0, 0, 0, UC+005, /* X-Z, */ +/*40*/ 00, 006, 062, 034, 022, 002, 032, 064, /* a-g */ +/*50*/ 050, 014, 026, 036, 044, 070, 030, 060, /* h-o */ +/*60*/ 054, 056, 024, 012, 040, 016, 074, 046, /* p-w */ +/*70*/ 072, 052, 042, 0, 005, 0, UC+035, BOTH+077 /* x-z, */ + }; + +/* PETR data structures + + petr_dev PETR device descriptor + petr_unit PETR unit + petr_reg PETR register list +*/ + +UNIT petr_unit = { + UDATA (&petr_svc, UNIT_SEQ+UNIT_ATTABLE+UNIT_ROABLE, 0), + SERIAL_IN_WAIT + }; + +REG petr_reg[] = { + { ORDATA (BUF, petr_unit.buf, 18) }, + { FLDATA (UC, petr_uc, UC_V) }, + { FLDATA (DONE, iosta, IOS_V_PETR) }, + { ORDATA (HOLD, petr_hold, 9), REG_HRO }, + { ORDATA (STATE, petr_state, 5), REG_HRO }, + { FLDATA (WAIT, petr_wait, 0), REG_HRO }, + { DRDATA (POS, petr_unit.pos, T_ADDR_W), PV_LEFT }, + { DRDATA (TIME, petr_unit.wait, 24), PV_LEFT }, + { DRDATA (LEADER, petr_leader, 6), REG_HRO }, + { FLDATA (STOP_IOE, petr_stopioe, 0) }, + { NULL } + }; + +MTAB petr_mod[] = { + { UNIT_ASCII, UNIT_ASCII, "ASCII", "ASCII", NULL }, + { UNIT_ASCII, 0, "FLEXO", "FLEXO", NULL }, + { 0 } + }; + +/* Debug flags */ +#define ERROR_MSG (1 << 0) +#define TRACE_MSG (1 << 1) +#define VERBOSE_MSG (1 << 2) + +/* Debug Flags */ +static DEBTAB petr_dt[] = { + { "ERROR", ERROR_MSG }, + { "TRACE", TRACE_MSG }, + { "VERBOSE",VERBOSE_MSG }, + { NULL, 0 } +}; + +DEVICE petr_dev = { + "PETR", &petr_unit, petr_reg, petr_mod, + 1, 10, 31, 1, 8, 8, + NULL, NULL, &petr_reset, + &petr_boot, &petr_attach, NULL, + NULL, DEV_DEBUG, (ERROR_MSG), + petr_dt, NULL + }; + +/* PTP data structures + + ptp_dev PTP device descriptor + ptp_unit PTP unit + ptp_reg PTP register list +*/ + +UNIT ptp_unit = { + UDATA (&ptp_svc, UNIT_SEQ+UNIT_ATTABLE, 0), SERIAL_OUT_WAIT + }; + +REG ptp_reg[] = { + { ORDATA (BUF, ptp_unit.buf, 8) }, + { FLDATA (DONE, iosta, IOS_V_PTP) }, + { DRDATA (POS, ptp_unit.pos, T_ADDR_W), PV_LEFT }, + { DRDATA (TIME, ptp_unit.wait, 24), PV_LEFT }, + { FLDATA (STOP_IOE, ptp_stopioe, 0) }, + { NULL } + }; + +MTAB ptp_mod[] = { + { 0 } + }; + +DEVICE ptp_dev = { + "PTP", &ptp_unit, ptp_reg, ptp_mod, + 1, 10, 31, 1, 8, 8, + NULL, NULL, &ptp_reset, + NULL, NULL, NULL, + NULL, DEV_DEBUG, (ERROR_MSG|TRACE_MSG), + petr_dt, NULL + }; + +/* TTI data structures + + tti_dev TTI device descriptor + tti_unit TTI unit + tti_reg TTI register list +*/ + +UNIT tti_unit = { UDATA (&tti_svc, 0, 0), KBD_POLL_WAIT }; + +REG tti_reg[] = { + { ORDATA (BUF, tty_buf, 6) }, + { FLDATA (UC, tty_uc, UC_V) }, + { ORDATA (HOLD, tti_hold, 9), REG_HRO }, + { FLDATA (DONE, iosta, IOS_V_TTI) }, + { DRDATA (POS, tti_unit.pos, T_ADDR_W), PV_LEFT }, + { DRDATA (TIME, tti_unit.wait, 24), REG_NZ + PV_LEFT }, + { NULL } + }; + +MTAB tti_mod[] = { + { 0 } + }; + +DEVICE tti_dev = { + "TTI", &tti_unit, tti_reg, tti_mod, + 1, 10, 31, 1, 8, 8, + NULL, NULL, &tty_reset, + NULL, NULL, NULL, + NULL, DEV_DEBUG, (ERROR_MSG|TRACE_MSG), + petr_dt, NULL + }; + +/* TTO data structures + + tto_dev TTO device descriptor + tto_unit TTO unit + tto_reg TTO register list +*/ + +UNIT tto_unit = { UDATA (&tto_svc, 0, 0), SERIAL_OUT_WAIT * 10 }; + +REG tto_reg[] = { + { ORDATA (BUF, tty_buf, 6) }, + { FLDATA (UC, tty_uc, UC_V) }, + { FLDATA (DONE, iosta, IOS_V_TTO) }, + { DRDATA (POS, tto_unit.pos, T_ADDR_W), PV_LEFT }, + { DRDATA (TIME, tto_unit.wait, 24), PV_LEFT }, + { NULL } + }; + +MTAB tto_mod[] = { + { 0 } + }; + +DEVICE tto_dev = { + "TTO", &tto_unit, tto_reg, tto_mod, + 1, 10, 31, 1, 8, 8, + NULL, NULL, &tty_reset, + NULL, NULL, NULL, + NULL, DEV_DEBUG, (ERROR_MSG|TRACE_MSG), + petr_dt, NULL + }; + +/* Photoelectric Tape Reader: + +The PETR is a 250 line per minute Ferranti photoelectric paper tape reader +using standard seven-hole Flexowriter tape that was modified to solid state +circuitry. Lines without seventh hole punched are ignored by the PETR. +As each line of the tape is read in, the data is stored into an 18-bit BUF +register with bits mapped as follows: + +Tape BUF +0 0 +1 3 +2 6 +3 9 +4 12 +5 15 + +Up to three lines of tape may be read into a single the single BUF register. +Before subsequent lines are read, the BUF register is cycled one bit right. + +The PETR reads data from or a disk file. The POS register specifies the +number of the next data item to be read. Thus, by changing POS, the user can +backspace or advance the reader. + +The PETR supports the BOOT command. BOOT PETR switches the CPU to Read-In +mode, and starts the processor running. +*/ + +int32 petr (int32 inst, int32 dev, int32 dat) +{ + int32 tmpAC = 0; + int i = 0; + t_stat result; + ios = 1; + + for (i=0;i> 0) << 17; /* bit 0 */ + tmpAC |= ((petr_unit.buf & 002) >> 1) << 14; /* bit 3 */ + tmpAC |= ((petr_unit.buf & 004) >> 2) << 11; /* bit 6 */ + tmpAC |= ((petr_unit.buf & 010) >> 3) << 8; /* bit 9 */ + tmpAC |= ((petr_unit.buf & 020) >> 4) << 5; /* bit 12 */ + tmpAC |= ((petr_unit.buf & 040) >> 5) << 2; /* bit 15 */ + + if (i < (inst-1)) { + uint32 bit0 = (tmpAC & 1) << 17; + TRACE_PRINT(petr_dev, TRACE_MSG, ("PETR read [%04x=0x%02x] %03o\n", petr_unit.pos-1, petr_unit.buf, petr_unit.buf)); + tmpAC >>= 1; + tmpAC |= bit0; + } else { + TRACE_PRINT(petr_dev, TRACE_MSG, ("PETR read [%04x=0x%02x] %03o, tmpAC=%06o\n", petr_unit.pos-1, petr_unit.buf, petr_unit.buf, tmpAC)); + } + } + return tmpAC; + + /* sim_activate (&petr_unit, petr_unit.wait); */ /* start reader */ + +} + +/* Unit service */ + +t_stat petr_svc (UNIT *uptr) +{ +int32 temp; + +if ((uptr->flags & UNIT_ATT) == 0) { /* attached? */ + ios = 0; + return SCPE_OK; + } + + if ((temp = getc (uptr->fileref)) != EOF) { /* no, get raw char */ + uptr->pos = uptr->pos + 1; /* if not eof, count */ + } + if (temp == EOF) { /* end of file? */ + if (feof (uptr->fileref)) { + ios = 0; + return SCPE_IOERR; + } + else perror ("PETR I/O error"); + clearerr (uptr->fileref); + ios = 0; + return SCPE_IOERR; + } + + uptr->buf = temp; + +ios = 0; + +return SCPE_OK; +} + +/* Reset routine */ + +t_stat petr_reset (DEVICE *dptr) +{ + petr_state = 0; /* clear state */ + petr_wait = 0; + petr_hold = 0; + petr_uc = 0; + petr_unit.buf = 0; + iosta = iosta & ~IOS_PETR; /* clear flag */ + sim_cancel (&petr_unit); /* deactivate unit */ + return SCPE_OK; +} + +/* Attach routine */ + +t_stat petr_attach (UNIT *uptr, char *cptr) +{ + petr_leader = PETR_LEADER; /* set up leader */ + return attach_unit (uptr, cptr); +} + +/* Bootstrap routine */ +extern t_stat cpu_set_mode (UNIT *uptr, int32 val, char *cptr, void *desc); +extern UNIT cpu_unit; + +//#define SANITY_CHECK_TAPE + +/* Switches the CPU to READIN mode and starts execution. */ +t_stat petr_boot (int32 unitno, DEVICE *dptr) +{ + t_stat reason = SCPE_OK; + +#ifdef SANITY_CHECK_TAPE + int32 AC, MBR, MAR, IR = 0; + int32 blkcnt, chksum = 0, fa, la; + int32 addr, tdata; +#endif /* SANITY_CHECK_TAPE */ + + /* Switch to READIN mode. */ + cpu_set_mode(&cpu_unit, UNIT_MODE_READIN, NULL, NULL); +#ifdef SANITY_CHECK_TAPE + for(;(IR != 2) && (IR != 1);) { + AC = petr(3,0,0); /* Read three chars from tape into AC */ + MAR = AC & AMASK; /* Set memory address */ + IR = AC >> 16; + + if (!MEM_ADDR_OK(MAR)) { + TRACE_PRINT(petr_dev, ERROR_MSG, ("READIN: Tape address out of range.\n")); + reason = SCPE_FMT; + } + + switch (IR) { + case 00: /* Storage (sto x) */ + case 03: /* Storage (opr x) */ + MBR = petr(3,0,0); /* Read three characters from tape. */ + TRACE_PRINT(petr_dev, ERROR_MSG, ("READIN: sto @%06o = %06o\n", MAR, MBR)); + printf("[%06o] = %06o\n", MAR, MBR); + break; + case 02: /* Transfer Control (trn x) Start Execution */ + PC = MAR; + reason = SCPE_OK; /* let SIMH start execution. */ + TRACE_PRINT(petr_dev, ERROR_MSG, ("READIN: trn %06o (Start Execution)\n", PC)); + reason = cpu_set_mode(&cpu_unit, 0, NULL, NULL); + break; + case 01: /* Transfer (add x) - Halt */ + PC = MAR; + reason = SCPE_STOP; /* let SIMH halt. */ + TRACE_PRINT(petr_dev, ERROR_MSG, ("READIN: add %06o (Halt)\n", PC)); + reason = cpu_set_mode(&cpu_unit, 0, NULL, NULL); + break; + default: + reason = SCPE_IERR; + break; + } + } + + blkcnt = 0; + while (1) { + chksum = 0; + + fa = petr(3,0,0); /* Read three characters from tape. */ + + if ((fa & 0400000) || (fa & 0200000)) { + break; + } + + chksum += fa; + if (chksum > 0777777) { + chksum +=1; + } + chksum &= 0777777; + + la = petr(3,0,0); /* Read three characters from tape. */ + + chksum += la; + if (chksum > 0777777) { + chksum +=1; + } + chksum &= 0777777; + + la = (~la) & 0177777; + + printf("First Address=%06o, Last Address=%06o\n", fa, la); + + for(addr = fa; addr <= la; addr++) { + tdata = petr(3,0,0); /* Read three characters from tape. */ + chksum += tdata; + if (chksum > 0777777) { + chksum +=1; + } + chksum &= 0777777; + } + + chksum = (~chksum) & 0777777; + + tdata = petr(3,0,0); + + if (chksum != tdata) { + reason = SCPE_FMT; + } + + printf("Block %d: Calculated checksum=%06o, real checksum=%06o, %s\n", blkcnt, chksum, tdata, chksum == tdata ? "OK" : "BAD Checksum!"); + blkcnt++; + } + + fseek (petr_dev.units[0].fileref, 0, SEEK_SET); +#endif /* SANITY_CHECK_TAPE */ + + /* Start Execution */ + return (reason); + +} + +/* Paper tape punch: punches standard seven-hole Flexowriter tape. */ + +int32 ptp (int32 inst, int32 dev, int32 dat) +{ + iosta = iosta & ~IOS_PTP; /* clear flag */ + ptp_unit.buf = dat & 0177; + ptp_svc (&ptp_unit); + /* sim_activate (&ptp_unit, ptp_unit.wait); */ /* start unit */ + return dat; +} + +/* Unit service */ + +t_stat ptp_svc (UNIT *uptr) +{ + ios = 1; /* restart */ + iosta = iosta | IOS_PTP; /* set flag */ + if ((uptr->flags & UNIT_ATT) == 0) /* not attached? */ + return SCPE_UNATT; + if (putc (uptr->buf, uptr->fileref) == EOF) { /* I/O error? */ + perror ("PTP I/O error"); + clearerr (uptr->fileref); + return SCPE_IOERR; + } + uptr->pos = uptr->pos + 1; + return SCPE_OK; +} + +/* Reset routine */ + +t_stat ptp_reset (DEVICE *dptr) +{ + ptp_unit.buf = 0; /* clear state */ + iosta = iosta & ~IOS_PTP; /* clear flag */ + sim_cancel (&ptp_unit); /* deactivate unit */ + return SCPE_OK; +} + +/* Typewriter IOT routines */ + +int32 tti (int32 inst, int32 dev, int32 dat) +{ + iosta = iosta & ~IOS_TTI; /* clear flag */ + return tty_buf & 077; +} + +int32 tto (int32 inst, int32 dev, int32 dat) +{ + tty_buf = dat & TT_WIDTH; /* load buffer */ + ios = 0; + tto_svc(&tto_unit); + /* sim_activate (&tto_unit, tto_unit.wait); */ /* activate unit */ + return dat; +} + +/* Unit service routines */ + +t_stat tti_svc (UNIT *uptr) +{ + int32 in = 0, temp = 0; + + sim_activate (uptr, uptr->wait); /* continue poll */ + if (tti_hold & CW) { /* char waiting? */ + tty_buf = tti_hold & TT_WIDTH; /* return char */ + tti_hold = 0; /* not waiting */ + } else { + if ((temp = sim_poll_kbd ()) < SCPE_KFLAG) return temp; + if (temp & SCPE_BREAK) return SCPE_OK; /* ignore break */ + temp = temp & 0177; + if (temp == 0177) temp = '\b'; /* rubout? bs */ + sim_putchar (temp); /* echo */ + if (temp == '\r') sim_putchar ('\n'); /* cr? add nl */ + in = ascii_to_flexo[temp]; /* translate char */ + + if (in == 0) return SCPE_OK; /* no xlation? */ + if ((in & BOTH) || ((in & UC) == (tty_uc & UC))) { + tty_buf = in & TT_WIDTH; + } else { /* must shift */ + tty_uc = in & UC; /* new case */ + tty_buf = tty_uc? FLEXO_UC: FLEXO_LC; + tti_hold = in | CW; /* set 2nd waiting */ + } + } + iosta = iosta | IOS_TTI; /* set flag */ + TRACE_PRINT(tti_dev, TRACE_MSG, ("TTI read ASCII: %02x / FLEXO=%03o\n", temp, tty_buf)); + uptr->pos = uptr->pos + 1; + return SCPE_OK; +} + +t_stat tto_svc (UNIT *uptr) +{ + int32 c = 0; + t_stat r; + + if (tty_buf == FLEXO_UC) tty_uc = UC; /* upper case? */ + else if (tty_buf == FLEXO_LC) tty_uc = 0; /* lower case? */ + else { + c = flexo_to_ascii[tty_buf | tty_uc]; /* translate */ + if (c && ((r = sim_putchar_s (c)) != SCPE_OK)) { /* output; error? */ + sim_activate (uptr, uptr->wait); /* retry */ + return ((r == SCPE_STALL)? SCPE_OK: r); + } + } + iosta = iosta | IOS_TTO; /* set flag */ + uptr->pos = uptr->pos + 1; + if (c == '\r') { /* cr? add lf */ + sim_putchar ('\n'); + uptr->pos = uptr->pos + 1; + } + return SCPE_OK; +} + +/* Reset routine */ + +t_stat tty_reset (DEVICE *dptr) +{ + tmxr_set_console_units (&tti_unit, &tto_unit); + tty_buf = 0; /* clear buffer */ + tty_uc = 0; /* clear case */ + tti_hold = 0; /* clear hold buf */ + iosta = (iosta & ~IOS_TTI) | IOS_TTO; /* clear flag */ + sim_activate (&tti_unit, tti_unit.wait); /* activate keyboard */ + sim_cancel (&tto_unit); /* stop printer */ + return SCPE_OK; +} diff --git a/TX-0/tx0_sys.c b/TX-0/tx0_sys.c new file mode 100644 index 00000000..a571ecac --- /dev/null +++ b/TX-0/tx0_sys.c @@ -0,0 +1,439 @@ +/************************************************************************* + * * + * $Id: tx0_sys.c 2061 2009-02-24 07:05:58Z hharte $ * + * * + * Copyright (c) 2009-2012 Howard M. Harte. * + * Based on pdp1_sys.c, Copyright (c) 1993-2007, Robert M. Supnik * + * * + * Permission is hereby granted, free of charge, to any person obtaining * + * a copy of this software and associated documentation files (the * + * "Software"), to deal in the Software without restriction, including * + * without limitation the rights to use, copy, modify, merge, publish, * + * distribute, sublicense, and/or sell copies of the Software, and to * + * permit persons to whom the Software is furnished to do so, subject to * + * the following conditions: * + * * + * The above copyright notice and this permission notice shall be * + * included in all copies or substantial portions of the Software. * + * * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * + * NONINFRINGEMENT. IN NO EVENT SHALL HOWARD M. HARTE BE LIABLE FOR ANY * + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * + * * + * Except as contained in this notice, the name of Howard M. Harte shall * + * not be used in advertising or otherwise to promote the sale, use or * + * other dealings in this Software without prior written authorization * + * of Howard M. Harte. * + * * + * Module Description: * + * TX-0 simulator interface * + * * + * Environment: * + * User mode only * + * * + *************************************************************************/ + +#include "tx0_defs.h" +#include + +extern DEVICE cpu_dev; +extern DEVICE petr_dev; +extern DEVICE tto_dev; +extern DEVICE tti_dev; +extern DEVICE ptp_dev; +#ifdef USE_DISPLAY +extern DEVICE dpy_dev; +#endif /* USE_DISPLAY */ + +#ifdef USE_FPC +extern DEVICE fpc_dev; +#endif /* USE_FPC */ +extern UNIT cpu_unit; +extern REG cpu_reg[]; +extern int32 M[]; +extern int32 PC; +extern int32 ascii_to_flexo[], flexo_to_ascii[]; +extern int32 sc_map[]; +extern int32 sim_switches; + +/* SCP data structures and interface routines + + sim_name simulator name string + sim_PC pointer to saved PC register descriptor + sim_emax number of words for examine + sim_devices array of pointers to simulated devices + sim_stop_messages array of pointers to stop messages + sim_load binary loader +*/ + +char sim_name[] = "TX-0"; + +REG *sim_PC = &cpu_reg[0]; + +int32 sim_emax = 1; + +DEVICE *sim_devices[] = { + &cpu_dev, + &petr_dev, + &tti_dev, + &tto_dev, + &ptp_dev, +#ifdef USE_DISPLAY + &dpy_dev, +#endif/* USE_DISPLAY */ +#ifdef USE_FPC + &fpc_dev, +#endif /* USE_FPC */ + NULL + }; + +const char *sim_stop_messages[] = { + "Unknown error", + "Undefined instruction", + "HALT instruction", + "Breakpoint", + "Nested XCT's", + "Nested indirect addresses", + "Infinite I/O wait state", + "DECtape off reel" + }; + +int32 tx0_getw (FILE *inf) +{ +int32 i, tmp, word; + +word = 0; +for (i = 0; i < 3;) { + if ((tmp = getc (inf)) == EOF) return -1; + if (tmp & 0200) { + word = (word << 6) | (tmp & 077); + i++; + } + } +return word; +} + +/* Symbol tables */ +typedef struct { + int32 opr; + char *mnemonic; + char *desc; +} OPMAP; + +typedef struct { + char *mnemonic; + char *desc; +} INSTMAP; + +const INSTMAP instmap[] = { +/* Store Class */ + { "sto", "Store AC" }, + { "stx", "Store AC, Indexed" }, + { "sxa", "Store XR in Address" }, + { "ado", "Add One" }, + { "slr", "Store LR" }, + { "slx", "Store LR, Indexed" }, + { "stz", "Store Zero" }, + { "[!sto-nop]", "NOP" }, + +/* Add Class */ + { "add", "Add" }, + { "adx", "Add, Indexed" }, + { "ldx", "Load XR" }, + { "aux", "Augment XR" }, + { "llr", "Load LR" }, + { "llx", "Load LR, Indexed" }, + { "lda", "Load AC" }, + { "lax", "Load AC, Indexed" }, + +/* Transfer Class */ + { "trn", "Transfer Negative" }, + { "trz", "Transfer +/- Zero" }, + { "tsx", "Transfer and set Index" }, + { "tix", "Transfer and Index" }, + { "tra", "Transfer" }, + { "trx", "Transfer Indexed" }, + { "tlv", "Transfer on external Level" }, + { "[!tra-nop]", "NOP" } +}; + +const OPMAP opmap [] = { + { 0600000, "opr", "No operation" }, + { 0600001, "xro", "Clear XR to +0" }, + { 0600003, "lxr", "Place LR in XR" }, + { 0600012, "cry", "Carry the contents of AC according to bits of LR" }, + { 0600022, "lpd", "Logical exclusive or of AC is placed in AC (partial add)" }, + { 0600032, "lad", "Add LR to AC" }, + { 0600040, "com", "Compliment the AC" }, + { 0600072, "lcd", "Contents of LR minus those of AC are placed in AC" }, + { 0600130, "xad", "Add index register to accumulator" }, + { 0600170, "xcd", "Contents of XR minus those of AC are placed in AC" }, + { 0600200, "lro", "Clear LR to +0" }, + { 0600300, "xlr", "Place XR in LR" }, + { 0600303, "ixl", "Interchange XR and LR" }, + { 0600400, "shr", "Shift accumulator right one place, bit 0 remains unchanged" }, + { 0600600, "cyr", "Cycle AC right one place" }, + { 0603000, "pen", "Contents of light pen and light cannon flip-flops replace contents of AC bits 0 and 1. The flip-flops are cleared." }, + { 0604000, "bsr", "Backspace tape unit by one record" }, + { 0604004, "rtb", "Read tape binary (odd parity)" }, + { 0604004, "rds", "Select tape unit for reading a record" }, + { 0604010, "rew", "Rewind tape unit" }, + { 0604014, "wtb", "Write tape binary (odd parity)" }, + { 0604014, "wrs", "Select tape unit for writing a record" }, + { 0604024, "rtd", "Read tape decimal (even parity)" }, + { 0604034, "wtd", "Write tape decimal (even parity)" }, + { 0607000, "cpf", "The program flag is cleared" }, + { 0620000, "cpy", "Transmit information between the live register and selected input-output unit" }, + { 0622000, "dis", "Display point on CRT corresponding to contents of AC" }, + { 0624000, "prt", "Print one on-line flexo character from bits 2, 5, etc." }, + { 0624600, "pnt", "PRT, then cycle AC right once to set up another character" }, + { 0625000, "typ", "Read one character from on-line flexowriter into LR bits 12-17" }, + { 0626600, "p6h", "Punch one line of paper tape; 6 holes from bits 2, 5, etc. of AC then cycle right once." }, + { 0627600, "p7h", "Same as p6h, but punch 7th hole" }, + { 0630000, "hlt", "Stops computer" }, + { 0631000, "cll", "Clear left half of AC to zero" }, + { 0632000, "clr", "Clear right half of AC" }, + { 0632022, "---", "CLR+PAD+LMB" }, + { 0640001, "axr", "Place AC contents in XR" }, + { 0640021, "axo", "AXR, then set AC to +0" }, + { 0640030, "cyl", "Cycle AC left one place" }, + { 0640031, "alx", "AXR, then cycle AC left once" }, + { 0640040, "amz", "Add minus zero to AC" }, + { 0640061, "axc", "AXR, then set AC to -0" }, + { 0640200, "alr", "Place accumulator contents in live register" }, + { 0640201, "---", "ALR+MBX, Place accumulator contents in live register, Transfer MBR to XR." }, + { 0640203, "rax", "Place LR in XR, then place AC in LR" }, + { 0640205, "orl", "Logical or of AC and LR is placed in LR" }, + { 0640207, "anl", "Logical and of AC and LR is placed in LR" }, + { 0640220, "alo", "ALR, then set AC to +0" }, + { 0640230, "all", "ALR, then cycle left once" }, + { 0640231, "---", "AMB+MBL+PAD+CRY+MBX" }, + { 0640232, "iad", "Interchange and add AC contents are placed in the LR and the previous contents of the LR ar added to AC" }, + { 0640260, "alc", "ALR, then set AC to -0" }, + { 0640601, "arx", "AXR, then cycle AC right once" }, + { 0647000, "spf", "Place AC in program flag register" }, + { 0662020, "dso", "DIS, then clear AC" }, + { 0664020, "pno", "PRT, then clear AC" }, + { 0664060, "pnc", "PRT, then clear AC to -0" }, + { 0666020, "p6o", "p6h then clear AC" }, + { 0667020, "p7o", "p7h then clear AC" }, + { 0700000, "cla", "Clear entire AC to +0" }, + { 0700001, "cax", "Clear AC and XR to +0" }, + { 0700012, "lal", "Place LR in AC cycled left once" }, + { 0700022, "lac", "Place LR in AC" }, + { 0700040, "clc", "Clear and complement: set AC to -0" }, + { 0700062, "lcc", "Place complement of LR in AC" }, + { 0700072, "laz", "Add LR to minus zero in AC" }, + { 0700110, "xal", "XAC, then cycle AC left once" }, + { 0700120, "xac", "Place index register in accumulator" }, + { 0700160, "xcc", "Place complement of XR in accumulator" }, + { 0700200, "cal", "Clear AC and LR to +0" }, + { 0700322, "rxe", "Place LR in AC, then place XR in LR" }, + { 0700622, "lar", "Place LR in AC cycled right once" }, + { 0701000, "tac", "Contents of test accumulator are placed in AC" }, + { 0702020, "tbr", "Contents of test buffer register are placed in AC" }, + { 0703000, "---", "Clear AC and read light pen" }, + { 0706020, "rpf", "The program flag register is placed in AC" }, + { 0721000, "rlc", "Read one line paper tape into AC bits 0, 3, etc." }, + { 0721600, "rlr", "rlc, then cycle AC right once" }, + { 0723000, "r3c", "Read three lines of paper tape" }, + { 0723032, "---", "R3C+LMB+PAD+CRY" }, + { 0726000, "p6a", "Clear AC and punch a line of blank tape" }, + { 0740025, "ora", "Logical or of AC and LR is placed in AC" }, + { 0740027, "ana", "Logical and of AC and LR is placed in AC" }, + { 0740207, "anc", "ANL, then clear AC" }, + { 0740205, "oro", "ORL, then clear AC" }, + { 0740222, "ial", "Interchange AC and LR" }, + { 0763232, "---", "AMB+CLA+R3L+MBL+LMB+PAD+CRY" }, + { 0766020, "p6b", "Punch a line of blank tape, but save AC" }, + { 0000000, NULL, NULL } +}; + +/* Symbolic decode + + Inputs: + *of = output stream + addr = current PC + *val = pointer to values + *uptr = pointer to unit + sw = switches + Outputs: + return = status code +*/ + +#define FMTASC(x) ((x) < 040)? "<%03o>": "%c", (x) +#define SIXTOASC(x) flexo_to_ascii[x] +#define ASCTOSIX(x) (ascii_to_flexo[x] & 077) + +extern int32 cpu_get_mode (void); +extern t_stat fprint_sym_orig (FILE *of, t_addr addr, t_value *val, + UNIT *uptr, int32 sw); + + +t_stat fprint_sym (FILE *of, t_addr addr, t_value *val, + UNIT *uptr, int32 sw) +{ +int32 cflag, i, inst, op; + +if(!cpu_get_mode()) { + return fprint_sym_orig (of, addr, val, uptr, sw); +} + + +inst = val[0]; +cflag = (uptr == NULL) || (uptr == &cpu_unit); +if (sw & SWMASK ('A')) { /* ASCII? */ + if (inst > 0377) return SCPE_ARG; + fprintf (of, FMTASC (inst & 0177)); + return SCPE_OK; + } +if (sw & SWMASK ('F')) { + fputc (flexo_to_ascii[inst & 077], of); + return SCPE_OK; + } +if (sw & SWMASK ('C')) { /* character? */ + fprintf (of, "%c", SIXTOASC ((inst >> 12) & 077)); + fprintf (of, "%c", SIXTOASC ((inst >> 6) & 077)); + fprintf (of, "%c", SIXTOASC (inst & 077)); + return SCPE_OK; + } +if (!(sw & SWMASK ('M'))) return SCPE_ARG; + +/* Instruction decode */ + + op = (inst >> 13) & 037; + + if ((op & 030) != 030) /* sto, add, trn (not an opr) */ + { + fprintf (of, "%s %05o (%s)", instmap[op].mnemonic, inst & 017777, instmap[op].desc); + } else { /* opr */ + for(i=0;opmap[i].opr != 0;i++) { + if(inst == opmap[i].opr) { + fprintf (of, "opr %s (%s)", opmap[i].mnemonic, opmap[i].desc); + } + } + } +return SCPE_OK; +} + +/* Get 18b signed number + + Inputs: + *cptr = pointer to input string + *sign = pointer to sign + *status = pointer to error status + Outputs: + val = output value +*/ + +t_value get_sint (char *cptr, int32 *sign, t_stat *status) +{ +*sign = 1; +if (*cptr == '+') { + *sign = 0; + cptr++; + } +else if (*cptr == '-') { + *sign = -1; + cptr++; + } +return get_uint (cptr, 8, DMASK, status); +} + +/* Symbolic input + + Inputs: + *cptr = pointer to input string + addr = current PC + uptr = pointer to unit + *val = pointer to output values + sw = switches + Outputs: + status = error status +*/ +t_stat parse_sym (char *cptr, t_addr addr, UNIT *uptr, t_value *val, int32 sw) +{ +#if 0 + int32 cflag, d, i, j, k, sign; +t_stat r; +static int32 sc_enc[10] = { 0, 01, 03, 07, 017, 037, 077, 0177, 0377, 0777 }; +char gbuf[CBUFSIZE]; + +cflag = (uptr == NULL) || (uptr == &cpu_unit); +while (isspace (*cptr)) cptr++; +for (i = 1; (i < 3) && (cptr[i] != 0); i++) + if (cptr[i] == 0) for (j = i + 1; j <= 3; j++) cptr[j] = 0; +if ((sw & SWMASK ('A')) || ((*cptr == '\'') && cptr++)) { /* ASCII char? */ + if (cptr[0] == 0) return SCPE_ARG; /* must have 1 char */ + val[0] = (t_value) cptr[0]; + return SCPE_OK; + } +if ((sw & SWMASK ('C')) || ((*cptr == '"') && cptr++)) { /* sixbit string? */ + if (cptr[0] == 0) return SCPE_ARG; /* must have 1 char */ + val[0] = ((ASCTOSIX (cptr[0]) & 077) << 12) | + ((ASCTOSIX (cptr[1]) & 077) << 6) | + (ASCTOSIX (cptr[2]) & 077); + return SCPE_OK; + } + +cptr = get_glyph (cptr, gbuf, 0); /* get opcode */ +for (i = 0; (opcode[i] != NULL) && (strcmp (opcode[i], gbuf) != 0) ; i++) ; +if (opcode[i] == NULL) return SCPE_ARG; +val[0] = opc_val[i] & DMASK; /* get value */ +j = (opc_val[i] >> I_V_FL) & I_M_FL; /* get class */ + +switch (j) { /* case on class */ + + case I_V_LAW: /* LAW */ + cflag = 0; /* fall through */ + case I_V_MRF: case I_V_MRI: /* mem ref */ + cptr = get_glyph (cptr, gbuf, 0); /* get next field */ + if ((j != I_V_MRI) && strcmp (gbuf, "I") == 0) { /* indirect? */ + val[0] = val[0] | IA; + cptr = get_glyph (cptr, gbuf, 0); + } + d = get_uint (gbuf, 8, AMASK, &r); + if (r != SCPE_OK) return SCPE_ARG; + if (d <= DAMASK) val[0] = val[0] | d; + else if (cflag && (((addr ^ d) & EPCMASK) == 0)) + val[0] = val[0] | (d & DAMASK); + else return SCPE_ARG; + break; + + case I_V_SHF: /* shift */ + cptr = get_glyph (cptr, gbuf, 0); + d = get_uint (gbuf, 10, 9, &r); + if (r != SCPE_OK) return SCPE_ARG; + val[0] = val[0] | sc_enc[d]; + break; + + case I_V_NPN: case I_V_IOT: + case I_V_OPR: case I_V_SKP: case I_V_SPC: + for (cptr = get_glyph (cptr, gbuf, 0); gbuf[0] != 0; + cptr = get_glyph (cptr, gbuf, 0)) { + for (i = 0; (opcode[i] != NULL) && + (strcmp (opcode[i], gbuf) != 0); i++) ; + if (opcode[i] != NULL) { + k = opc_val[i] & DMASK; + if ((k != IA) && (((k ^ val[0]) & 0760000) != 0)) + return SCPE_ARG; + val[0] = val[0] | k; + } + else { + d = get_sint (gbuf, &sign, &r); + if (r != SCPE_OK) return SCPE_ARG; + if (sign == 0) val[0] = val[0] + d; + else if (sign < 0) val[0] = val[0] - d; + else val[0] = val[0] | d; + } + } + break; + } /* end case */ +if (*cptr != 0) return SCPE_ARG; /* junk at end? */ +#endif +return SCPE_ARG; +} diff --git a/TX-0/tx0_sys_orig.c b/TX-0/tx0_sys_orig.c new file mode 100644 index 00000000..a85c9d32 --- /dev/null +++ b/TX-0/tx0_sys_orig.c @@ -0,0 +1,133 @@ +/************************************************************************* + * * + * $Id: tx0_sys_orig.c 2065 2009-02-25 15:05:00Z hharte $ * + * * + * Copyright (c) 2009-2012 Howard M. Harte. * + * * + * Permission is hereby granted, free of charge, to any person obtaining * + * a copy of this software and associated documentation files (the * + * "Software"), to deal in the Software without restriction, including * + * without limitation the rights to use, copy, modify, merge, publish, * + * distribute, sublicense, and/or sell copies of the Software, and to * + * permit persons to whom the Software is furnished to do so, subject to * + * the following conditions: * + * * + * The above copyright notice and this permission notice shall be * + * included in all copies or substantial portions of the Software. * + * * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * + * NONINFRINGEMENT. IN NO EVENT SHALL HOWARD M. HARTE BE LIABLE FOR ANY * + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * + * * + * Except as contained in this notice, the name of Howard M. Harte shall * + * not be used in advertising or otherwise to promote the sale, use or * + * other dealings in this Software without prior written authorization * + * of Howard M. Harte. * + * * + * Module Description: * + * TX-0 simulator interface * + * * + * Environment: * + * User mode only * + * * + *************************************************************************/ + +#include "tx0_defs.h" +#include + +typedef struct { + int32 opr; + char *mnemonic; + char *desc; +} OPMAP; + +const OPMAP opmap_orig [] = { + { 0700000, "cll", "Clear the left nine digital positions of the AC" }, + { 0640000, "clr", "Clear the right nine digital positions of the AC" }, + { 0620000, "ios", "In-Out Stop" }, + { 0630000, "hlt", "Halt the computer" }, + { 0607000, "p7h", "Punch holes 1-6 in flexo tape Also punch a 7th hole on tape" }, + { 0606000, "p6h", "Punch holes 1-6 in flexo tape" }, + { 0604000, "pnt", "Print one flexowrite charater" }, + { 0601000, "r1c", "Read one line of flexo tape" }, + { 0603000, "r3c", "Read three lines of flexo tape" }, + { 0602000, "dis", "Intesnsify a point on the scope from x,y in AC" }, + { 0600400, "shr", "Shift the AC right one place" }, + { 0600600, "cyr", "Cycle the AC right one digital position (AC17 -> AC0)" }, + { 0600200, "mlr", "Store the contents of the MBR in the LR" }, + { 0600100, "pen", "Read the light pen flip flops 1 and 2 into AC0 and AC1" }, + { 0600004, "tac", "Insert a one in each digital position of the AC whereever there is a one in the corresponding digital position of the TAC" }, + { 0600040, "com", "Complement every digit in the accumulator" }, + { 0600020, "pad", "Partial add AC to MBR" }, + { 0600010, "cry", "Partial add the 18 digits of the AC to the corresponding 18 digits of the carry" }, + { 0600001, "amb", "Store the contents of the AC in the MBR" }, + { 0600003, "tbr", "Store the contents of the TBR in the MBR" }, + { 0600002, "lmb", "Store the contents of the LR in the MBR" }, +/* Combined Operate Class Commands */ + { 0740000, "cla", "Clear the AC" }, + { 0600031, "cyl", "Cycle the AC left one digital position" }, + { 0740040, "clc", "Clear and complement AC" }, + { 0622000, "dis", "Display (note IOS must be included for in-out cmds)" }, + { 0760000, "ios+cll+clr", "In out stop with AC cleared" }, + { 0627600, "ios+p7h+cyr", "Punch 7 holes and cycle AC right" }, + { 0626600, "ios+p6h+cyr", "Punch 6 holes and cycle AC right" }, + { 0766000, "ios+cll+clr+p6h", "Clear the AC and punch a blank space on tape" }, + { 0624600, "ios+pnt+cyr", "Print and cycle AC right" }, + { 0627021, "ios+p7h+amb+pad", "Punch 7 holes and leave AC cleared" }, + { 0626021, "ios+p6h+amb+pad", "Punch 6 holes and leave AC cleared" }, + { 0624021, "ios+pnt+amb+pad", "Print and leave AC cleared" }, + { 0741000, "cll+clr+ric", "Clear AC and start PETR running (note computer hasn't stopped to wait for information" }, + { 0601031, "ric+amb+pad+cry", "Start PETR running and cycle AC left" }, + { 0601600, "ric+cyr", "Start PETR running and cycle right" }, + { 0763000, "cll+clr+ios+r3c", "Clear AC and read 3 lines of tape" }, + { 0761000, "cll+clr+ios+ric", "Clear AC and read one line of tape" }, + { 0761031, "cll+clr+ios+ric+pad+cry", "Read 1 line of tape and cycle AC left" }, + { 0761600, "cll+clr+ios+ric+cyr", "Read 1 line of tape and cycle right" }, + { 0740004, "cll+clr+tac", "Put contents of TAC in AC" }, + { 0600030, "pad+cry", "Full-add the MBR and AC and leave sum in AC" }, + { 0740022, "cll+clr+lmb+pad", "Clear the AC - store LR contents in memory buffer register add memory buffer to AC - i.e., store live reg. contents in AC (LAC)" }, + { 0600201, "amb+mlr", "Store contents of AC in MBR, store contents of MBR in LR i.e., store contents of AC in LR. (ALR)" }, + { 0600022, "lmb+pad", "Store the contents of LR in MBR, partial add AC and MBR i.e., partial add LR to AC. (LPD)" }, +/* { 0600200, "mlr", "Since MLR alone will ahve a clear MBR, this is really clear LR (LRO)" }, */ + { 0600032, "lmb+pad+cry", "Full-add the LR to the AC (LAD)" }, + { 0740023, "cll+clr+tbr+pad", "Store contents of TBR in AC" }, + { 0000000, NULL, NULL } +}; + +t_stat fprint_sym_orig (FILE *of, t_addr addr, t_value *val, + UNIT *uptr, int32 sw) +{ +int32 i, inst, op; + +inst = val[0]; + +/* Instruction decode */ + +op = (inst >> 16) & 3; + +switch (op) { + case 0: + fprintf (of, "sto %06o", inst & 0177777); /* opcode */ + break; + case 1: + fprintf (of, "add %06o", inst & 0177777); /* opcode */ + break; + case 2: + fprintf (of, "trn %06o", inst & 0177777); /* opcode */ + break; + case 3: + for(i=0;opmap_orig[i].opr != 0;i++) { + if(inst == opmap_orig[i].opr) { + fprintf (of, "opr %s (%s)", opmap_orig[i].mnemonic, opmap_orig[i].desc); /* opcode */ + } + } + break; +} + +return SCPE_OK; +} + diff --git a/VAX/ka610.bin b/VAX/ka610.bin new file mode 100644 index 00000000..e0f345cf Binary files /dev/null and b/VAX/ka610.bin differ diff --git a/VAX/ka620.bin b/VAX/ka620.bin new file mode 100644 index 00000000..5cf2bd82 Binary files /dev/null and b/VAX/ka620.bin differ diff --git a/VAX/ka620_patch.com b/VAX/ka620_patch.com new file mode 100644 index 00000000..daad0149 --- /dev/null +++ b/VAX/ka620_patch.com @@ -0,0 +1,25 @@ +$! +$! This procedure patches KA620.BIN (V1.1) Boot ROM image to work under +$! the SIMH simulator +$! +$ PATCH /ABSOLUTE /NEW_VERSION /OUTPUT=KA620.BIN KA620_ORIG.BIN +! +! Test D - ROM checksum & TOY RAM +! +! - ROM checksum needs to be updated to reflect changes below +! +REPLACE/WORD 0B888 = 0279F +0163D +EXIT +! +! Test 3 - Interrupt tests +! +! - Need to skip console loopback test and memory parity test +! +REPLACE/INSTRUCTION 0547C = 'MOVAL W^0000571A,B^04(R11)' +'BRW 05CCC' +EXIT +! +UPDATE +EXIT +$ diff --git a/VAX/ka630.bin b/VAX/ka630.bin new file mode 100644 index 00000000..9ed59bf0 Binary files /dev/null and b/VAX/ka630.bin differ diff --git a/VAX/ka630_patch.com b/VAX/ka630_patch.com new file mode 100644 index 00000000..e18647a5 --- /dev/null +++ b/VAX/ka630_patch.com @@ -0,0 +1,25 @@ +$! +$! This procedure patches KA630.BIN (V1.3) Boot ROM image to work under +$! the SIMH simulator +$! +$ PATCH /ABSOLUTE /NEW_VERSION /OUTPUT=KA630.BIN KA630_ORIG.BIN +! +! Test D - ROM checksum & TOY RAM +! +! - ROM checksum needs to be updated to reflect changes below +! +REPLACE/WORD 0B888 = 0EAAA +0FAB3 +EXIT +! +! Test 3 - Interrupt tests +! +! - Need to skip console loopback test and memory parity test +! +REPLACE/INSTRUCTION 0547C = 'MOVAL W^0000571A,B^04(R11)' +'BRW 05CCC' +EXIT +! +UPDATE +EXIT +$ diff --git a/VAX/vax610_defs.h b/VAX/vax610_defs.h new file mode 100644 index 00000000..097d2595 --- /dev/null +++ b/VAX/vax610_defs.h @@ -0,0 +1,336 @@ +/* vax610_defs.h: MicroVAX I model-specific definitions file + + Copyright (c) 2011-2012, Matt Burke + This module incorporates code from SimH, Copyright (c) 2004-2008, Robert M Supnik + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name(s) of the author(s) shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from the author(s). + + 15-Feb-2012 MB First Version + + This file covers the MicroVAX I + + System memory map + + 0000 0000 - 003F FFFF main memory + 0040 0000 - 1FFF FFFF reserved + 2000 0000 - 2000 1FFF qbus address space + 2000 2000 - 3FFF FFFF reserved +*/ + +#ifdef FULL_VAX /* subset VAX */ +#undef FULL_VAX +#endif + +#ifndef _VAX_610_DEFS_H_ +#define _VAX_610_DEFS_H_ 1 + +/* Microcode constructs */ + +#define VAX610_SID (7 << 24) /* system ID */ +#define VAX610_FLOAT (1 << 16) /* floating point type */ +#define VAX610_MREV (5 << 8) /* microcode revision */ +#define VAX610_HWREV 1 /* hardware revision */ +#define CON_HLTPIN 0x0200 /* external CPU halt */ +#define CON_PWRUP 0x0300 /* powerup code */ +#define CON_HLTINS 0x0600 /* HALT instruction */ +#define CON_BADPSL 0x4000 /* invalid PSL flag */ +#define CON_MAPON 0x8000 /* mapping on flag */ +#define MCHK_TBM_P0 0x05 /* PPTE in P0 */ +#define MCHK_TBM_P1 0x06 /* PPTE in P1 */ +#define MCHK_M0_P0 0x07 /* PPTE in P0 */ +#define MCHK_M0_P1 0x08 /* PPTE in P1 */ +#define MCHK_INTIPL 0x09 /* invalid ireq */ +#define MCHK_READ 0x02 /* read check */ +#define MCHK_WRITE 0x02 /* write check */ + +/* Machine specific IPRs */ + +#define MT_TBDR 36 /* Translation Buffer Disable */ +#define MT_CADR 37 /* Cache Disable Register */ +#define MT_MCESR 38 /* Machine Check Error Summary */ +#define MT_CAER 39 /* Cache Error Register */ +#define MT_CONISP 41 /* Console Saved ISP */ +#define MT_CONPC 42 /* Console Saved PC */ +#define MT_CONPSL 43 /* Console Saved PSL */ +#define MT_SBIFS 48 /* SBI fault status */ +#define MT_SBIS 49 /* SBI silo */ +#define MT_SBISC 50 /* SBI silo comparator */ +#define MT_SBIMT 51 /* SBI maint */ +#define MT_SBIER 52 /* SBI error */ +#define MT_SBITA 53 /* SBI timeout addr */ +#define MT_SBIQC 54 /* SBI timeout clear */ +#define MT_IORESET 55 /* I/O Bus Reset */ +#define MT_TBDATA 59 /* Translation Buffer Data */ +#define MT_MBRK 60 /* microbreak */ +#define MT_MAX 63 /* last valid IPR */ + +/* Memory */ + +#define MAXMEMWIDTH 22 /* max mem, KA610 */ +#define MAXMEMSIZE (1 << MAXMEMWIDTH) /* max mem size */ +#define MAXMEMWIDTH_X 22 /* max mem, KA610 */ +#define MAXMEMSIZE_X (1 << MAXMEMWIDTH_X) +#define INITMEMSIZE (1 << 22) /* initial memory size */ +#define MEMSIZE (cpu_unit.capac) +#define ADDR_IS_MEM(x) (((uint32) (x)) < MEMSIZE) +#undef PAMASK +#define PAMASK 0x203FFFFF /* KA610 needs a special mask */ +#define MEM_MODIFIERS { UNIT_MSIZE, (1u << 19), NULL, "512k", &cpu_set_size }, \ + { UNIT_MSIZE, (1u << 20), NULL, "1M", &cpu_set_size }, \ + { UNIT_MSIZE, (1u << 21), NULL, "2M", &cpu_set_size }, \ + { UNIT_MSIZE, (1u << 22), NULL, "4M", &cpu_set_size } +#define CPU_MODEL_MODIFIERS { MTAB_XTD|MTAB_VDV, 0, "LEDS", NULL, \ + NULL, &cpu_show_leds }, \ + { MTAB_XTD|MTAB_VDV, 0, "MODEL", NULL, \ + NULL, &cpu_show_model }, + +/* Qbus I/O page */ + +#define IOPAGEAWIDTH 13 /* IO addr width */ +#define IOPAGESIZE (1u << IOPAGEAWIDTH) /* IO page length */ +#define IOPAGEMASK (IOPAGESIZE - 1) /* IO addr mask */ +#define IOPAGEBASE 0x20000000 /* IO page base */ +#define ADDR_IS_IO(x) ((((uint32) (x)) >= IOPAGEBASE) && \ + (((uint32) (x)) < (IOPAGEBASE + IOPAGESIZE))) + +/* Other address spaces */ + +#define ADDR_IS_CDG(x) (0) +#define ADDR_IS_ROM(x) (0) +#define ADDR_IS_NVR(x) (0) + +/* Machine specific reserved operand tests (all NOPs) */ + +#define ML_PA_TEST(r) +#define ML_LR_TEST(r) +#define ML_SBR_TEST(r) +#define ML_PXBR_TEST(r) +#define LP_AST_TEST(r) +#define LP_MBZ84_TEST(r) +#define LP_MBZ92_TEST(r) + +/* Qbus I/O modes */ + +#define READ 0 /* PDP-11 compatibility */ +#define WRITE (L_WORD) +#define WRITEB (L_BYTE) + +/* Common CSI flags */ + +#define CSR_V_GO 0 /* go */ +#define CSR_V_IE 6 /* interrupt enable */ +#define CSR_V_DONE 7 /* done */ +#define CSR_V_BUSY 11 /* busy */ +#define CSR_V_ERR 15 /* error */ +#define CSR_GO (1u << CSR_V_GO) +#define CSR_IE (1u << CSR_V_IE) +#define CSR_DONE (1u << CSR_V_DONE) +#define CSR_BUSY (1u << CSR_V_BUSY) +#define CSR_ERR (1u << CSR_V_ERR) + +/* Timers */ + +#define TMR_CLK 0 /* 100Hz clock */ + +/* I/O system definitions */ + +#define DZ_MUXES 4 /* max # of DZV muxes */ +#define DZ_LINES 4 /* lines per DZV mux */ +#define VH_MUXES 4 /* max # of DHQ muxes */ +#define DLX_LINES 16 /* max # of KL11/DL11's */ +#define DCX_LINES 16 /* max # of DC11's */ +#define MT_MAXFR (1 << 16) /* magtape max rec */ +#define AUTO_LNT 34 /* autoconfig ranks */ + +#define DEV_V_UBUS (DEV_V_UF + 0) /* Unibus */ +#define DEV_V_QBUS (DEV_V_UF + 1) /* Qbus */ +#define DEV_V_Q18 (DEV_V_UF + 2) /* Qbus, mem <= 256KB */ +#define DEV_UBUS (1u << DEV_V_UBUS) +#define DEV_QBUS (1u << DEV_V_QBUS) +#define DEV_Q18 (1u << DEV_V_Q18) + +#define UNIBUS FALSE /* 22b only */ + +#define DEV_RDX 16 /* default device radix */ + +/* Device information block */ + +#define VEC_DEVMAX 4 /* max device vec */ + +typedef struct { + uint32 ba; /* base addr */ + uint32 lnt; /* length */ + t_stat (*rd)(int32 *dat, int32 ad, int32 md); + t_stat (*wr)(int32 dat, int32 ad, int32 md); + int32 vnum; /* vectors: number */ + int32 vloc; /* locator */ + int32 vec; /* value */ + int32 (*ack[VEC_DEVMAX])(void); /* ack routine */ + } DIB; + +/* Qbus I/O page layout - see pdp11_ui_lib.c for address layout details */ + +#define IOBA_AUTO (0) /* Assigned by Auto Configure */ + + +/* The KA610 maintains 4 separate hardware IPL levels, IPL 17 to IPL 14; + however, DEC Qbus controllers all interrupt on IPL 14 + Within each IPL, priority is right to left +*/ + +/* IPL 17 */ + +/* IPL 16 */ + +#define INT_V_CLK 0 /* clock */ + +/* IPL 15 */ + +/* IPL 14 - devices through RY are IPL 15 on Unibus systems */ + +#define INT_V_RQ 0 /* RQDX3 */ +#define INT_V_RL 1 /* RLV12/RL02 */ +#define INT_V_DZRX 2 /* DZ11 */ +#define INT_V_DZTX 3 +#define INT_V_TS 4 /* TS11/TSV05 */ +#define INT_V_TQ 5 /* TMSCP */ +#define INT_V_XQ 6 /* DEQNA/DELQA */ +#define INT_V_RY 7 /* RXV21 */ + +#define INT_V_TTI 8 /* console */ +#define INT_V_TTO 9 +#define INT_V_PTR 10 /* PC11 */ +#define INT_V_PTP 11 +#define INT_V_LPT 12 /* LP11 */ +#define INT_V_CSI 13 /* SSC cons UART */ +#define INT_V_CSO 14 +#define INT_V_TMR0 15 /* SSC timers */ +#define INT_V_TMR1 16 +#define INT_V_VHRX 17 /* DHQ11 */ +#define INT_V_VHTX 18 +#define INT_V_QDSS 19 /* QDSS */ +#define INT_V_CR 20 +#define INT_V_QVSS 21 /* QVSS */ + +#define INT_CLK (1u << INT_V_CLK) +#define INT_RQ (1u << INT_V_RQ) +#define INT_RL (1u << INT_V_RL) +#define INT_DZRX (1u << INT_V_DZRX) +#define INT_DZTX (1u << INT_V_DZTX) +#define INT_TS (1u << INT_V_TS) +#define INT_TQ (1u << INT_V_TQ) +#define INT_XQ (1u << INT_V_XQ) +#define INT_RY (1u << INT_V_RY) +#define INT_TTI (1u << INT_V_TTI) +#define INT_TTO (1u << INT_V_TTO) +#define INT_PTR (1u << INT_V_PTR) +#define INT_PTP (1u << INT_V_PTP) +#define INT_LPT (1u << INT_V_LPT) +#define INT_CSI (1u << INT_V_CSI) +#define INT_CSO (1u << INT_V_CSO) +#define INT_TMR0 (1u << INT_V_TMR0) +#define INT_TMR1 (1u << INT_V_TMR1) +#define INT_VHRX (1u << INT_V_VHRX) +#define INT_VHTX (1u << INT_V_VHTX) +#define INT_QDSS (1u << INT_V_QDSS) +#define INT_CR (1u << INT_V_CR) +#define INT_QVSS (1u << INT_V_QVSS) + +#define IPL_CLK (0x16 - IPL_HMIN) /* relative IPL */ +#define IPL_RQ (0x14 - IPL_HMIN) +#define IPL_RL (0x14 - IPL_HMIN) +#define IPL_DZRX (0x14 - IPL_HMIN) +#define IPL_DZTX (0x14 - IPL_HMIN) +#define IPL_TS (0x14 - IPL_HMIN) +#define IPL_TQ (0x14 - IPL_HMIN) +#define IPL_XQ (0x14 - IPL_HMIN) +#define IPL_RY (0x14 - IPL_HMIN) +#define IPL_TTI (0x14 - IPL_HMIN) +#define IPL_TTO (0x14 - IPL_HMIN) +#define IPL_PTR (0x14 - IPL_HMIN) +#define IPL_PTP (0x14 - IPL_HMIN) +#define IPL_LPT (0x14 - IPL_HMIN) +#define IPL_CSI (0x14 - IPL_HMIN) +#define IPL_CSO (0x14 - IPL_HMIN) +#define IPL_TMR0 (0x14 - IPL_HMIN) +#define IPL_TMR1 (0x14 - IPL_HMIN) +#define IPL_VHRX (0x14 - IPL_HMIN) +#define IPL_VHTX (0x14 - IPL_HMIN) +#define IPL_QDSS (0x14 - IPL_HMIN) +#define IPL_CR (0x14 - IPL_HMIN) +#define IPL_QVSS (0x14 - IPL_HMIN) + +#define IPL_HMAX 0x17 /* highest hwre level */ +#define IPL_HMIN 0x14 /* lowest hwre level */ +#define IPL_HLVL (IPL_HMAX - IPL_HMIN + 1) /* # hardware levels */ +#define IPL_SMAX 0xF /* highest swre level */ + +/* Device vectors */ + +#define VEC_AUTO (0) /* Assigned by Auto Configure */ +#define VEC_FLOAT (0) /* Assigned by Auto Configure */ + +#define VEC_QBUS 1 /* Qbus system */ +#define VEC_Q 0x200 /* Qbus vector offset */ + +/* Interrupt macros */ + +#define IVCL(dv) ((IPL_##dv * 32) + INT_V_##dv) +#define IREQ(dv) int_req[IPL_##dv] +#define SET_INT(dv) int_req[IPL_##dv] = int_req[IPL_##dv] | (INT_##dv) +#define CLR_INT(dv) int_req[IPL_##dv] = int_req[IPL_##dv] & ~(INT_##dv) +#define IORETURN(f,v) ((f)? (v): SCPE_OK) /* cond error return */ + +/* Logging */ + +#define LOG_CPU_I 0x1 /* intexc */ +#define LOG_CPU_R 0x2 /* REI */ +#define LOG_CPU_P 0x4 /* context */ + +/* Function prototypes for virtual memory interface */ + +int32 Read (uint32 va, int32 lnt, int32 acc); +void Write (uint32 va, int32 val, int32 lnt, int32 acc); + +/* Function prototypes for physical memory interface (inlined) */ + +SIM_INLINE int32 ReadB (uint32 pa); +SIM_INLINE int32 ReadW (uint32 pa); +SIM_INLINE int32 ReadL (uint32 pa); +SIM_INLINE int32 ReadLP (uint32 pa); +SIM_INLINE void WriteB (uint32 pa, int32 val); +SIM_INLINE void WriteW (uint32 pa, int32 val); +SIM_INLINE void WriteL (uint32 pa, int32 val); +void WriteLP (uint32 pa, int32 val); + +/* Function prototypes for I/O */ + +int32 Map_ReadB (uint32 ba, int32 bc, uint8 *buf); +int32 Map_ReadW (uint32 ba, int32 bc, uint16 *buf); +int32 Map_WriteB (uint32 ba, int32 bc, uint8 *buf); +int32 Map_WriteW (uint32 ba, int32 bc, uint16 *buf); + +t_stat cpu_show_leds (FILE *st, UNIT *uptr, int32 val, void *desc); + +#include "pdp11_io_lib.h" + +#endif diff --git a/VAX/vax610_io.c b/VAX/vax610_io.c new file mode 100644 index 00000000..e0dd2d2d --- /dev/null +++ b/VAX/vax610_io.c @@ -0,0 +1,375 @@ +/* vax610_io.c: MicroVAX I Qbus IO simulator + + Copyright (c) 2011-2012, Matt Burke + This module incorporates code from SimH, Copyright (c) 1998-2008, Robert M Supnik + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name(s) of the author(s) shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from the author(s). + + qba Qbus adapter + + 15-Feb-2012 MB First Version +*/ + +#include "vax_defs.h" + +int32 int_req[IPL_HLVL] = { 0 }; /* intr, IPL 14-17 */ +int32 autcon_enb = 1; /* autoconfig enable */ + +extern int32 PSL, SISR, trpirq, mem_err, hlt_pin; +extern int32 p1; +extern jmp_buf save_env; + +int32 eval_int (void); +t_stat qba_reset (DEVICE *dptr); + +/* Qbus adapter data structures + + qba_dev QBA device descriptor + qba_unit QBA units + qba_reg QBA register list +*/ + +UNIT qba_unit = { UDATA (NULL, 0, 0) }; + +REG qba_reg[] = { + { HRDATAD (IPL17, int_req[3], 32, "IPL 17 interrupt flags"), REG_RO }, + { HRDATAD (IPL16, int_req[2], 32, "IPL 16 interrupt flags"), REG_RO }, + { HRDATAD (IPL15, int_req[1], 32, "IPL 15 interrupt flags"), REG_RO }, + { HRDATAD (IPL14, int_req[0], 32, "IPL 14 interrupt flags"), REG_RO }, + { FLDATA (AUTOCON, autcon_enb, 0), REG_HRO }, + { NULL } + }; + +MTAB qba_mod[] = { + { MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, "IOSPACE", NULL, + NULL, &show_iospace }, + { MTAB_XTD|MTAB_VDV, 1, "AUTOCONFIG", "AUTOCONFIG", + &set_autocon, &show_autocon }, + { MTAB_XTD|MTAB_VDV, 0, NULL, "NOAUTOCONFIG", + &set_autocon, NULL }, + { 0 } + }; + +DEVICE qba_dev = { + "QBUS", &qba_unit, qba_reg, qba_mod, + 1, 16, 4, 2, 16, 16, + NULL, NULL, &qba_reset, + NULL, NULL, NULL, + NULL, DEV_QBUS + }; + +/* IO page dispatches */ + +t_stat (*iodispR[IOPAGESIZE >> 1])(int32 *dat, int32 ad, int32 md); +t_stat (*iodispW[IOPAGESIZE >> 1])(int32 dat, int32 ad, int32 md); + +/* Interrupt request to interrupt action map */ + +int32 (*int_ack[IPL_HLVL][32])(void); /* int ack routines */ + +/* Interrupt request to vector map */ + +int32 int_vec[IPL_HLVL][32]; /* int req to vector */ + +/* The KA610 handles errors in I/O space as follows + + - read: machine check + - write: machine check (?) +*/ + +int32 ReadQb (uint32 pa) +{ +int32 idx, val; + +idx = (pa & IOPAGEMASK) >> 1; +if (iodispR[idx]) { + iodispR[idx] (&val, pa, READ); + return val; + } +MACH_CHECK (MCHK_READ); +return 0; +} + +void WriteQb (uint32 pa, int32 val, int32 mode) +{ +int32 idx; + +idx = (pa & IOPAGEMASK) >> 1; +if (iodispW[idx]) { + iodispW[idx] (val, pa, mode); + return; + } +MACH_CHECK (MCHK_WRITE); /* FIXME: is this correct? */ +return; +} + +/* ReadIO - read I/O space + + Inputs: + pa = physical address + lnt = length (BWLQ) + Output: + longword of data +*/ + +int32 ReadIO (uint32 pa, int32 lnt) +{ +int32 iod; + +iod = ReadQb (pa); /* wd from Qbus */ +if (lnt < L_LONG) /* bw? position */ + iod = iod << ((pa & 2)? 16: 0); +else iod = (ReadQb (pa + 2) << 16) | iod; /* lw, get 2nd wd */ +SET_IRQL; +return iod; +} + +/* WriteIO - write I/O space + + Inputs: + pa = physical address + val = data to write, right justified in 32b longword + lnt = length (BWLQ) + Outputs: + none +*/ + +void WriteIO (uint32 pa, int32 val, int32 lnt) +{ +if (lnt == L_BYTE) + WriteQb (pa, val, WRITEB); +else if (lnt == L_WORD) + WriteQb (pa, val, WRITE); +else { + WriteQb (pa, val & 0xFFFF, WRITE); + WriteQb (pa + 2, (val >> 16) & 0xFFFF, WRITE); + } +SET_IRQL; +return; +} + +/* Find highest priority outstanding interrupt */ + +int32 eval_int (void) +{ +int32 ipl = PSL_GETIPL (PSL); +int32 i, t; + +static const int32 sw_int_mask[IPL_SMAX] = { + 0xFFFE, 0xFFFC, 0xFFF8, 0xFFF0, /* 0 - 3 */ + 0xFFE0, 0xFFC0, 0xFF80, 0xFF00, /* 4 - 7 */ + 0xFE00, 0xFC00, 0xF800, 0xF000, /* 8 - B */ + 0xE000, 0xC000, 0x8000 /* C - E */ + }; + +if (hlt_pin) /* hlt pin int */ + return IPL_HLTPIN; +if ((ipl < IPL_MEMERR) && mem_err) /* mem err int */ + return IPL_MEMERR; +for (i = IPL_HMAX; i >= IPL_HMIN; i--) { /* chk hwre int */ + if (i <= ipl) /* at ipl? no int */ + return 0; + if (int_req[i - IPL_HMIN]) /* req != 0? int */ + return i; + } +if (ipl >= IPL_SMAX) /* ipl >= sw max? */ + return 0; +if ((t = SISR & sw_int_mask[ipl]) == 0) /* eligible req */ + return 0; +for (i = IPL_SMAX; i > ipl; i--) { /* check swre int */ + if ((t >> i) & 1) /* req != 0? int */ + return i; + } +return 0; +} + +/* Return vector for highest priority hardware interrupt at IPL lvl */ + +int32 get_vector (int32 lvl) +{ +int32 i; +int32 l = lvl - IPL_HMIN; + +if (lvl == IPL_MEMERR) { /* mem error? */ + mem_err = 0; + return SCB_MEMERR; + } +if (lvl > IPL_HMAX) { /* error req lvl? */ + ABORT (STOP_UIPL); /* unknown intr */ + } +for (i = 0; int_req[l] && (i < 32); i++) { + if ((int_req[l] >> i) & 1) { + int_req[l] = int_req[l] & ~(1u << i); + if (int_ack[l][i]) + return int_ack[l][i](); + return int_vec[l][i]; + } + } +return 0; +} + +/* Reset I/O bus */ + +void ioreset_wr (int32 data) +{ +reset_all (5); /* from qba on... */ +return; +} + +/* Reset Qbus */ + +t_stat qba_reset (DEVICE *dptr) +{ +int32 i; + +for (i = 0; i < IPL_HLVL; i++) + int_req[i] = 0; +return SCPE_OK; +} + +/* Qbus I/O buffer routines, aligned access + + Map_ReadB - fetch byte buffer from memory + Map_ReadW - fetch word buffer from memory + Map_WriteB - store byte buffer into memory + Map_WriteW - store word buffer into memory +*/ + +int32 Map_ReadB (uint32 ba, int32 bc, uint8 *buf) +{ +int32 i; +uint32 ma = ba & 0x3FFFFF; +uint32 dat; + +if ((ba | bc) & 03) { /* check alignment */ + for (i = 0; i < bc; i++, buf++) { /* by bytes */ + *buf = ReadB (ma); + ma = ma + 1; + } + } +else { + for (i = 0; i < bc; i = i + 4, buf++) { /* by longwords */ + dat = ReadL (ma); /* get lw */ + *buf++ = dat & BMASK; /* low 8b */ + *buf++ = (dat >> 8) & BMASK; /* next 8b */ + *buf++ = (dat >> 16) & BMASK; /* next 8b */ + *buf = (dat >> 24) & BMASK; + ma = ma + 4; + } + } +return 0; +} + +int32 Map_ReadW (uint32 ba, int32 bc, uint16 *buf) +{ +int32 i; +uint32 ma = ba & 0x3FFFFF; +uint32 dat; + +ba = ba & ~01; +bc = bc & ~01; +if ((ba | bc) & 03) { /* check alignment */ + for (i = 0; i < bc; i = i + 2, buf++) { /* by words */ + *buf = ReadW (ma); + ma = ma + 2; + } + } +else { + for (i = 0; i < bc; i = i + 4, buf++) { /* by longwords */ + dat = ReadL (ma); /* get lw */ + *buf++ = dat & WMASK; /* low 16b */ + *buf = (dat >> 16) & WMASK; /* high 16b */ + ma = ma + 4; + } + } +return 0; +} + +int32 Map_WriteB (uint32 ba, int32 bc, uint8 *buf) +{ +int32 i; +uint32 ma = ba & 0x3FFFFF; +uint32 dat; + +if ((ba | bc) & 03) { /* check alignment */ + for (i = 0; i < bc; i++, buf++) { /* by bytes */ + WriteB (ma, *buf); + ma = ma + 1; + } + } +else { + for (i = 0; i < bc; i = i + 4, buf++) { /* by longwords */ + dat = (uint32) *buf++; /* get low 8b */ + dat = dat | (((uint32) *buf++) << 8); /* merge next 8b */ + dat = dat | (((uint32) *buf++) << 16); /* merge next 8b */ + dat = dat | (((uint32) *buf) << 24); /* merge hi 8b */ + WriteL (ma, dat); /* store lw */ + ma = ma + 4; + } + } +return 0; +} + +int32 Map_WriteW (uint32 ba, int32 bc, uint16 *buf) +{ +int32 i; +uint32 ma = ba & 0x3FFFFF; +uint32 dat; + +ba = ba & ~01; +bc = bc & ~01; +if ((ba | bc) & 03) { /* check alignment */ + for (i = 0; i < bc; i = i + 2, buf++) { /* by words */ + WriteW (ma, *buf); + ma = ma + 2; + } + } +else { + for (i = 0; i < bc; i = i + 4, buf++) { /* by longwords */ + dat = (uint32) *buf++; /* get low 16b */ + dat = dat | (((uint32) *buf) << 16); /* merge hi 16b */ + WriteL (ma, dat); /* store lw */ + ma = ma + 4; + } + } +return 0; +} + +/* Build dib_tab from device list */ + +t_stat build_dib_tab (void) +{ +int32 i; +DEVICE *dptr; +DIB *dibp; +t_stat r; + +init_ubus_tab (); /* init bus tables */ +for (i = 0; (dptr = sim_devices[i]) != NULL; i++) { /* loop thru dev */ + dibp = (DIB *) dptr->ctxt; /* get DIB */ + if (dibp && !(dptr->flags & DEV_DIS)) { /* defined, enabled? */ + if ((r = build_ubus_tab (dptr, dibp))) /* add to bus tab */ + return r; + } /* end if enabled */ + } /* end for */ +return SCPE_OK; +} diff --git a/VAX/vax610_mem.c b/VAX/vax610_mem.c new file mode 100644 index 00000000..887ce027 --- /dev/null +++ b/VAX/vax610_mem.c @@ -0,0 +1,114 @@ +/* vax610_mem.c: MSV11-P memory controller + + Copyright (c) 2011-2012, Matt Burke + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHOR BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name of the author shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from the author. + + 15-Feb-2012 MB First Version +*/ + +#include "vax_defs.h" + +#define MAX_MCTL_COUNT 16 + +#define MCSR_PEN 0x0001 /* parity enable */ +#define MCSR_WWP 0x0004 /* write wrong parity */ +#define MCSR_ECR 0x4000 /* extended CSR read enable */ +#define MCSR_RW (MCSR_ECR|MCSR_WWP|MCSR_PEN) + +extern UNIT cpu_unit; + +int32 mctl_csr[MAX_MCTL_COUNT]; +int32 mctl_count = 0; + +t_stat mctl_rd (int32 *data, int32 PA, int32 access); +t_stat mctl_wr (int32 data, int32 PA, int32 access); +t_stat mctl_reset (DEVICE *dptr); + +/* MCTL data structures + + mctl_dev MCTL device descriptor + mctl_unit MCTL unit list + mctl_reg MCTL register list + mctl_mod MCTL modifier list +*/ + +#define IOLN_MEM 040 + +DIB mctl_dib = { + IOBA_AUTO, IOLN_MEM, &mctl_rd, &mctl_wr, + 1, 0, 0, { NULL } + }; + +UNIT mctl_unit = { UDATA (NULL, 0, 0) }; + +REG mctl_reg[] = { + { DRDATAD (COUNT, mctl_count, 16, "Memory Module Count") }, + { BRDATAD (CSR, mctl_csr, DEV_RDX, 16, MAX_MCTL_COUNT, "control/status registers") }, + { NULL } + }; + +DEVICE mctl_dev = { + "MCTL", &mctl_unit, mctl_reg, NULL, + 1, DEV_RDX, 20, 1, DEV_RDX, 8, + NULL, NULL, &mctl_reset, + NULL, NULL, NULL, + &mctl_dib, DEV_Q18 + }; + +/* I/O dispatch routines */ + +t_stat mctl_rd (int32 *data, int32 PA, int32 access) +{ +int32 rg = (PA >> 1) & 0xF; +if (rg >= mctl_count) + return SCPE_NXM; +*data = mctl_csr[rg]; +return SCPE_OK; +} + +t_stat mctl_wr (int32 data, int32 PA, int32 access) +{ +int32 rg = (PA >> 1) & 0xF; +if (rg >= mctl_count) + return SCPE_NXM; +mctl_csr[rg] = data & MCSR_RW; +return SCPE_OK; +} + +t_stat mctl_reset (DEVICE *dptr) +{ +int32 rg; +for (rg = 0; rg < MAX_MCTL_COUNT; rg++) { + mctl_csr[rg] = 0; + } +mctl_count = (int32)(MEMSIZE >> 18); /* memory controllers enabled */ +return SCPE_OK; +} + +/* Used by CPU */ + +void rom_wr_B (int32 pa, int32 val) +{ +return; +} + diff --git a/VAX/vax610_stddev.c b/VAX/vax610_stddev.c new file mode 100644 index 00000000..2c095bde --- /dev/null +++ b/VAX/vax610_stddev.c @@ -0,0 +1,422 @@ +/* vax610_stddev.c: MicroVAX I standard I/O devices + + Copyright (c) 2011-2012, Matt Burke + This module incorporates code from SimH, Copyright (c) 1998-2008, Robert M Supnik + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name(s) of the author(s) shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from the author(s). + + tti terminal input + tto terminal output + clk 100Hz clock + + 15-Feb-2012 MB First Version +*/ + +#include "vax_defs.h" +#include "sim_tmxr.h" +#include + +#define TTICSR_IMP (CSR_DONE + CSR_IE) /* terminal input */ +#define TTICSR_RW (CSR_IE) +#define TTIBUF_ERR 0x8000 /* error */ +#define TTIBUF_OVR 0x4000 /* overrun */ +#define TTIBUF_FRM 0x2000 /* framing error */ +#define TTIBUF_RBR 0x0400 /* receive break */ +#define TTOCSR_IMP (CSR_DONE + CSR_IE) /* terminal output */ +#define TTOCSR_RW (CSR_IE) +#define TXDB_V_SEL 8 /* unit select */ +#define TXDB_M_SEL 0xF +#define TXDB_MISC 0xF /* console misc */ +#define MISC_MASK 0xFF /* console data mask */ +#define MISC_NOOP0 0x0 /* no operation */ +#define MISC_NOOP1 0x1 /* no operation */ +#define MISC_BOOT 0x2 /* reboot */ +#define MISC_CLWS 0x3 /* clear warm start */ +#define MISC_CLCS 0x4 /* clear cold start */ +#define MISC_SWDN 0x5 /* software done */ +#define MISC_LEDS0 0x8 /* LEDs 000 (all on) */ +#define MISC_LEDS1 0x9 /* LEDs 001 (on, on, off) */ +#define MISC_LEDS2 0xA /* LEDs 010 (on, off, on)*/ +#define MISC_LEDS3 0xB /* LEDs 011 (on, off, off)*/ +#define MISC_LEDS4 0xC /* LEDs 100 (off, on, on)*/ +#define MISC_LEDS5 0xD /* LEDs 101 (off, on, off)*/ +#define MISC_LEDS6 0xE /* LEDs 110 (off, off, on)*/ +#define MISC_LEDS7 0xF /* LEDs 111 (all off)*/ +#define TXDB_SEL (TXDB_M_SEL << TXDB_V_SEL) /* non-terminal */ +#define TXDB_GETSEL(x) (((x) >> TXDB_V_SEL) & TXDB_M_SEL) +#define CLKCSR_IMP (CSR_IE) /* real-time clock */ +#define CLKCSR_RW (CSR_IE) +#define CLK_DELAY 5000 /* 100 Hz */ +#define TMXR_MULT 1 /* 100 Hz */ + +extern int32 int_req[IPL_HLVL]; +extern int32 hlt_pin; +extern jmp_buf save_env; +extern int32 p1; + +int32 tti_csr = 0; /* control/status */ +int32 tto_csr = 0; /* control/status */ +int32 tto_leds = 0; /* processor board LEDs */ +int32 clk_csr = 0; /* control/status */ +int32 clk_tps = 100; /* ticks/second */ +int32 tmxr_poll = CLK_DELAY * TMXR_MULT; /* term mux poll */ +int32 tmr_poll = CLK_DELAY; /* pgm timer poll */ + +t_stat tti_svc (UNIT *uptr); +t_stat tto_svc (UNIT *uptr); +t_stat clk_svc (UNIT *uptr); +t_stat tti_reset (DEVICE *dptr); +t_stat tto_reset (DEVICE *dptr); +t_stat clk_reset (DEVICE *dptr); +void txdb_func (int32 data); + +extern int32 sysd_hlt_enb (void); +extern int32 con_halt (int32 code, int32 cc); + +/* TTI data structures + + tti_dev TTI device descriptor + tti_unit TTI unit descriptor + tti_reg TTI register list +*/ + +DIB tti_dib = { 0, 0, NULL, NULL, 1, IVCL (TTI), SCB_TTI, { NULL } }; + +UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), 0 }; + +REG tti_reg[] = { + { HRDATAD (BUF, tti_unit.buf, 16, "last data item processed") }, + { HRDATAD (CSR, tti_csr, 16, "control/status register") }, + { FLDATAD (INT, int_req[IPL_TTI], INT_V_TTI, "interrupt pending flag") }, + { FLDATAD (ERR, tti_csr, CSR_V_ERR, "error flag (CSR<15>)") }, + { FLDATAD (DONE, tti_csr, CSR_V_DONE, "device done flag (CSR<7>)") }, + { FLDATAD (IE, tti_csr, CSR_V_IE, "interrupt enable flag (CSR<6>)") }, + { DRDATAD (POS, tti_unit.pos, T_ADDR_W, "number of characters input"), PV_LEFT }, + { DRDATAD (TIME, tti_unit.wait, 24, "input polling interval"), PV_LEFT }, + { NULL } + }; + +MTAB tti_mod[] = { + { TT_MODE, TT_MODE_7B, "7b", "7B", NULL }, + { TT_MODE, TT_MODE_8B, "8b", "8B", NULL }, + { MTAB_XTD|MTAB_VDV, 0, "VECTOR", NULL, + NULL, &show_vec, NULL }, + { 0 } + }; + +DEVICE tti_dev = { + "TTI", &tti_unit, tti_reg, tti_mod, + 1, 10, 31, 1, 16, 8, + NULL, NULL, &tti_reset, + NULL, NULL, NULL, + &tti_dib, 0 + }; + +/* TTO data structures + + tto_dev TTO device descriptor + tto_unit TTO unit descriptor + tto_reg TTO register list +*/ + +DIB tto_dib = { 0, 0, NULL, NULL, 1, IVCL (TTO), SCB_TTO, { NULL } }; + +UNIT tto_unit = { UDATA (&tto_svc, TT_MODE_8B, 0), SERIAL_OUT_WAIT }; + +REG tto_reg[] = { + { HRDATAD (BUF, tto_unit.buf, 8, "last data item processed") }, + { HRDATAD (CSR, tto_csr, 16, "control/status register") }, + { FLDATAD (INT, int_req[IPL_TTO], INT_V_TTO, "interrupt pending flag") }, + { FLDATAD (ERR, tto_csr, CSR_V_ERR, "error flag (CSR<15>)") }, + { FLDATAD (DONE, tto_csr, CSR_V_DONE, "device done flag (CSR<7>)") }, + { FLDATAD (IE, tto_csr, CSR_V_IE, "interrupt enable flag (CSR<6>)") }, + { DRDATAD (POS, tto_unit.pos, T_ADDR_W, "number of characters output"), PV_LEFT }, + { DRDATAD (TIME, tto_unit.wait, 24, "time from I/O initiation to interrupt"), PV_LEFT }, + { NULL } + }; + +MTAB tto_mod[] = { + { TT_MODE, TT_MODE_7B, "7b", "7B", NULL }, + { TT_MODE, TT_MODE_8B, "8b", "8B", NULL }, + { TT_MODE, TT_MODE_7P, "7p", "7P", NULL }, + { MTAB_XTD|MTAB_VDV, 0, "VECTOR", NULL, NULL, &show_vec }, + { 0 } + }; + +DEVICE tto_dev = { + "TTO", &tto_unit, tto_reg, tto_mod, + 1, 10, 31, 1, 16, 8, + NULL, NULL, &tto_reset, + NULL, NULL, NULL, + &tto_dib, 0 + }; + +/* CLK data structures + + clk_dev CLK device descriptor + clk_unit CLK unit descriptor + clk_reg CLK register list +*/ + +DIB clk_dib = { 0, 0, NULL, NULL, 1, IVCL (CLK), SCB_INTTIM, { NULL } }; + +UNIT clk_unit = { UDATA (&clk_svc, UNIT_IDLE, 0), CLK_DELAY }; + +REG clk_reg[] = { + { HRDATAD (CSR, clk_csr, 16, "control/status register") }, + { FLDATAD (INT, int_req[IPL_CLK], INT_V_CLK, "interrupt pending flag") }, + { FLDATAD (IE, clk_csr, CSR_V_IE, "interrupt enable flag (CSR<6>)") }, + { DRDATAD (TIME, clk_unit.wait, 24, "initial poll interval"), REG_NZ + PV_LEFT }, + { DRDATAD (POLL, tmr_poll, 24, "calibrated poll interval"), REG_NZ + PV_LEFT + REG_HRO }, + { DRDATAD (TPS, clk_tps, 8, "ticks per second (100)"), REG_NZ + PV_LEFT }, +#if defined (SIM_ASYNCH_IO) + { DRDATAD (ASYNCH, sim_asynch_enabled, 1, "asynch I/O enabled flag"), PV_LEFT }, + { DRDATAD (LATENCY, sim_asynch_latency, 32, "desired asynch interrupt latency"), PV_LEFT }, + { DRDATAD (INST_LATENCY, sim_asynch_inst_latency, 32, "calibrated instruction latency"), PV_LEFT }, +#endif + { NULL } + }; + +DEVICE clk_dev = { + "CLK", &clk_unit, clk_reg, NULL, + 1, 0, 0, 0, 0, 0, + NULL, NULL, &clk_reset, + NULL, NULL, NULL, + &clk_dib, 0 + }; + +/* Clock and terminal MxPR routines + + iccs_rd/wr interval timer + rxcs_rd/wr input control/status + rxdb_rd input buffer + txcs_rd/wr output control/status + txdb_wr output buffer +*/ + +int32 iccs_rd (void) +{ +return (clk_csr & CLKCSR_IMP); +} + +int32 rxcs_rd (void) +{ +return (tti_csr & TTICSR_IMP); +} + +int32 rxdb_rd (void) +{ +int32 t = tti_unit.buf; /* char + error */ + +tti_csr = tti_csr & ~CSR_DONE; /* clr done */ +tti_unit.buf = tti_unit.buf & 0377; /* clr errors */ +CLR_INT (TTI); +return t; +} + +int32 txcs_rd (void) +{ +return (tto_csr & TTOCSR_IMP); +} + +void iccs_wr (int32 data) +{ +if ((data & CSR_IE) == 0) + CLR_INT (CLK); +clk_csr = (clk_csr & ~CLKCSR_RW) | (data & CLKCSR_RW); +return; +} + +void rxcs_wr (int32 data) +{ +if ((data & CSR_IE) == 0) + CLR_INT (TTI); +else if ((tti_csr & (CSR_DONE + CSR_IE)) == CSR_DONE) + SET_INT (TTI); +tti_csr = (tti_csr & ~TTICSR_RW) | (data & TTICSR_RW); +return; +} + +void txcs_wr (int32 data) +{ +if ((data & CSR_IE) == 0) + CLR_INT (TTO); +else if ((tto_csr & (CSR_DONE + CSR_IE)) == CSR_DONE) + SET_INT (TTO); +tto_csr = (tto_csr & ~TTOCSR_RW) | (data & TTOCSR_RW); +return; +} + +void txdb_wr (int32 data) +{ +if (data & TXDB_SEL) { /* internal function? */ + txdb_func (data); + return; + } +tto_unit.buf = data & 0377; +tto_csr = tto_csr & ~CSR_DONE; +CLR_INT (TTO); +sim_activate (&tto_unit, tto_unit.wait); +return; +} + +void txdb_func (int32 data) +{ +int32 sel = TXDB_GETSEL (data); /* get selection */ + +if (sel == TXDB_MISC) { /* misc function? */ + switch (data & MISC_MASK) { /* case on function */ + + case MISC_SWDN: + ABORT (STOP_SWDN); + break; + + case MISC_BOOT: + con_halt (0, 0); /* set up reboot */ + break; + case MISC_LEDS0: case MISC_LEDS1: case MISC_LEDS2: case MISC_LEDS3: + case MISC_LEDS4: case MISC_LEDS5: case MISC_LEDS6: case MISC_LEDS7: + tto_leds = 0x7 & (~((data & MISC_MASK)-MISC_LEDS0)); + sim_putchar ('.'); + sim_putchar ('0' + tto_leds); + sim_putchar ('.'); + break; + } + } +else + if (sel != 0) + RSVD_OPND_FAULT; + +} + +t_stat cpu_show_leds (FILE *st, UNIT *uptr, int32 val, void *desc) +{ +fprintf (st, "leds=%d(%s,%s,%s)", tto_leds, tto_leds&4 ? "ON" : "OFF", + tto_leds&2 ? "ON" : "OFF", + tto_leds&1 ? "ON" : "OFF"); +return SCPE_OK; +} + +/* Terminal input routines + + tti_svc process event (character ready) + tti_reset process reset +*/ + +t_stat tti_svc (UNIT *uptr) +{ +int32 c; + +sim_activate (uptr, KBD_WAIT (uptr->wait, tmr_poll)); /* continue poll */ +if ((c = sim_poll_kbd ()) < SCPE_KFLAG) /* no char or error? */ + return c; +if (c & SCPE_BREAK) { /* break? */ + if (sysd_hlt_enb ()) /* if enabled, halt */ + hlt_pin = 1; + tti_unit.buf = TTIBUF_ERR | TTIBUF_FRM | TTIBUF_RBR; + } +else tti_unit.buf = sim_tt_inpcvt (c, TT_GET_MODE (uptr->flags)); +uptr->pos = uptr->pos + 1; +tti_csr = tti_csr | CSR_DONE; +if (tti_csr & CSR_IE) + SET_INT (TTI); +return SCPE_OK; +} + +t_stat tti_reset (DEVICE *dptr) +{ +tmxr_set_console_units (&tti_unit, &tto_unit); +tti_unit.buf = 0; +tti_csr = 0; +CLR_INT (TTI); +sim_activate_abs (&tti_unit, KBD_WAIT (tti_unit.wait, tmr_poll)); +return SCPE_OK; +} + +/* Terminal output routines + + tto_svc process event (character typed) + tto_reset process reset +*/ + +t_stat tto_svc (UNIT *uptr) +{ +int32 c; +t_stat r; + +c = sim_tt_outcvt (tto_unit.buf, TT_GET_MODE (uptr->flags)); +if (c >= 0) { + if ((r = sim_putchar_s (c)) != SCPE_OK) { /* output; error? */ + sim_activate (uptr, uptr->wait); /* retry */ + return ((r == SCPE_STALL)? SCPE_OK: r); /* !stall? report */ + } + } +tto_csr = tto_csr | CSR_DONE; +if (tto_csr & CSR_IE) + SET_INT (TTO); +uptr->pos = uptr->pos + 1; +return SCPE_OK; +} + +t_stat tto_reset (DEVICE *dptr) +{ +tto_unit.buf = 0; +tto_csr = CSR_DONE; +CLR_INT (TTO); +sim_cancel (&tto_unit); /* deactivate unit */ +return SCPE_OK; +} + +/* Clock routines + + clk_svc process event (clock tick) + clk_reset process reset +*/ + +t_stat clk_svc (UNIT *uptr) +{ +int32 t; + +if (clk_csr & CSR_IE) + SET_INT (CLK); +t = sim_rtcn_calb (clk_tps, TMR_CLK); /* calibrate clock */ +sim_activate (&clk_unit, t); /* reactivate unit */ +tmr_poll = t; /* set tmr poll */ +tmxr_poll = t * TMXR_MULT; /* set mux poll */ +return SCPE_OK; +} + +/* Reset routine */ + +t_stat clk_reset (DEVICE *dptr) +{ +int32 t; + +clk_csr = 0; +CLR_INT (CLK); +t = sim_rtcn_init (clk_unit.wait, TMR_CLK); /* init timer */ +sim_activate_abs (&clk_unit, t); /* activate unit */ +tmr_poll = t; /* set tmr poll */ +tmxr_poll = t * TMXR_MULT; /* set mux poll */ +return SCPE_OK; +} + diff --git a/VAX/vax610_sysdev.c b/VAX/vax610_sysdev.c new file mode 100644 index 00000000..90a0ed11 --- /dev/null +++ b/VAX/vax610_sysdev.c @@ -0,0 +1,508 @@ +/* vax610_sysdev.c: MicroVAX I system-specific logic + + Copyright (c) 2011-2012, Matt Burke + This module incorporates code from SimH, Copyright (c) 1998-2008, Robert M Supnik + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name(s) of the author(s) shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from the author(s). + + This module contains the MicroVAX I system-specific registers and devices. + + sysd system devices + + 15-Feb-2012 MB First Version +*/ + +#include "vax_defs.h" +#include + +#ifdef DONT_USE_INTERNAL_ROM +#define BOOT_CODE_FILENAME "ka610.bin" +#else /* !DONT_USE_INTERNAL_ROM */ +#include "vax_ka610_bin.h" /* Defines BOOT_CODE_FILENAME and BOOT_CODE_ARRAY, etc */ +#endif /* DONT_USE_INTERNAL_ROM */ + +/* MicroVAX I boot device definitions */ + +struct boot_dev { + char *devname; + char *devalias; + int32 code; + }; + +extern int32 R[16]; +extern int32 in_ie; +extern int32 mchk_va, mchk_ref; +extern int32 int_req[IPL_HLVL]; +extern jmp_buf save_env; +extern int32 p1; +extern int32 trpirq, mem_err; + +int32 conisp, conpc, conpsl; /* console reg */ +int32 sys_model = 0; +char cpu_boot_cmd[CBUFSIZE] = { 0 }; /* boot command */ + +static struct boot_dev boot_tab[] = { + { "RQ", "DUA", 0x00415544 }, /* DUAn */ + { "RQ", "DU", 0x00415544 }, /* DUAn */ + { "XQ", "XQA", 0x00415158 }, /* XQAn */ + { NULL } + }; + +t_stat sysd_reset (DEVICE *dptr); +t_stat vax610_boot (int32 flag, char *ptr); +t_stat vax610_boot_parse (int32 flag, char *ptr); +t_stat cpu_boot (int32 unitno, DEVICE *dptr); + +extern int32 intexc (int32 vec, int32 cc, int32 ipl, int ei); +extern int32 iccs_rd (void); +extern int32 todr_rd (void); +extern int32 rxcs_rd (void); +extern int32 rxdb_rd (void); +extern int32 txcs_rd (void); +extern void iccs_wr (int32 dat); +extern void todr_wr (int32 dat); +extern void rxcs_wr (int32 dat); +extern void txcs_wr (int32 dat); +extern void txdb_wr (int32 dat); +extern void ioreset_wr (int32 dat); +extern int32 eval_int (void); + +/* SYSD data structures + + sysd_dev SYSD device descriptor + sysd_unit SYSD units + sysd_reg SYSD register list +*/ + +UNIT sysd_unit = { UDATA (NULL, 0, 0) }; + +REG sysd_reg[] = { + { HRDATAD (CONISP, conisp, 32, "console ISP") }, + { HRDATAD (CONPC, conpc, 32, "console PD") }, + { HRDATAD (CONPSL, conpsl, 32, "console PSL") }, + { BRDATA (BOOTCMD, cpu_boot_cmd, 16, 8, CBUFSIZE), REG_HRO }, + { NULL } + }; + +DEVICE sysd_dev = { + "SYSD", &sysd_unit, sysd_reg, NULL, + 1, 16, 16, 1, 16, 8, + NULL, NULL, &sysd_reset, + NULL, NULL, NULL, + NULL, 0 + }; + +/* Special boot command, overrides regular boot */ + +CTAB vax610_cmd[] = { + { "BOOT", &vax610_boot, RU_BOOT, + "bo{ot} {/R5:flg} boot device\n", &run_cmd_message }, + { NULL } + }; + +/* Read KA610 specific IPR's */ + +int32 ReadIPR (int32 rg) +{ +int32 val; + +switch (rg) { + + case MT_ICCS: /* ICCS */ + val = iccs_rd (); + break; + + case MT_RXCS: /* RXCS */ + val = rxcs_rd (); + break; + + case MT_RXDB: /* RXDB */ + val = rxdb_rd (); + break; + + case MT_TXCS: /* TXCS */ + val = txcs_rd (); + break; + + case MT_TXDB: /* TXDB */ + val = 0; + break; + + case MT_CONISP: /* console ISP */ + val = conisp; + break; + + case MT_CONPC: /* console PC */ + val = conpc; + break; + + case MT_CONPSL: /* console PSL */ + val = conpsl; + break; + + case MT_SID: /* SID */ + val = (VAX610_SID | VAX610_FLOAT | VAX610_MREV | VAX610_HWREV); + break; + + case MT_NICR: /* NICR */ + case MT_ICR: /* ICR */ + case MT_TODR: /* TODR */ + case MT_CSRS: /* CSRS */ + case MT_CSRD: /* CSRD */ + case MT_CSTS: /* CSTS */ + case MT_CSTD: /* CSTD */ + case MT_TBDR: /* TBDR */ + case MT_CADR: /* CADR */ + case MT_MCESR: /* MCESR */ + case MT_CAER: /* CAER */ + case MT_SBIFS: /* SBIFS */ + case MT_SBIS: /* SBIS */ + case MT_SBISC: /* SBISC */ + case MT_SBIMT: /* SBIMT */ + case MT_SBIER: /* SBIER */ + case MT_SBITA: /* SBITA */ + case MT_SBIQC: /* SBIQC */ + case MT_TBDATA: /* TBDATA */ + case MT_MBRK: /* MBRK */ + case MT_PME: /* PME */ + val = 0; + break; + + default: + RSVD_OPND_FAULT; + } + +return val; +} + +/* Write KA610 specific IPR's */ + +void WriteIPR (int32 rg, int32 val) +{ +switch (rg) { + + case MT_ICCS: /* ICCS */ + iccs_wr (val); + break; + + case MT_RXCS: /* RXCS */ + rxcs_wr (val); + break; + + case MT_RXDB: /* RXDB */ + break; + + case MT_TXCS: /* TXCS */ + txcs_wr (val); + break; + + case MT_TXDB: /* TXDB */ + txdb_wr (val); + break; + + case MT_IORESET: /* IORESET */ + ioreset_wr (val); + break; + + case MT_SID: + case MT_CONISP: + case MT_CONPC: + case MT_CONPSL: /* halt reg */ + RSVD_OPND_FAULT; + + case MT_NICR: /* NICR */ + case MT_ICR: /* ICR */ + case MT_TODR: /* TODR */ + case MT_CSRS: /* CSRS */ + case MT_CSRD: /* CSRD */ + case MT_CSTS: /* CSTS */ + case MT_CSTD: /* CSTD */ + case MT_TBDR: /* TBDR */ + case MT_CADR: /* CADR */ + case MT_MCESR: /* MCESR */ + case MT_CAER: /* CAER */ + case MT_SBIFS: /* SBIFS */ + case MT_SBIS: /* SBIS */ + case MT_SBISC: /* SBISC */ + case MT_SBIMT: /* SBIMT */ + case MT_SBIER: /* SBIER */ + case MT_SBITA: /* SBITA */ + case MT_SBIQC: /* SBIQC */ + case MT_TBDATA: /* TBDATA */ + case MT_MBRK: /* MBRK */ + case MT_PME: /* PME */ + break; + + default: + RSVD_OPND_FAULT; + } + +return; +} + +/* Read/write I/O register space + + These routines are the 'catch all' for address space map. Any + address that doesn't explicitly belong to memory or I/O + is given to these routines for processing. +*/ + +struct reglink { /* register linkage */ + uint32 low; /* low addr */ + uint32 high; /* high addr */ + t_stat (*read)(int32 pa); /* read routine */ + void (*write)(int32 pa, int32 val, int32 lnt); /* write routine */ + }; + +struct reglink regtable[] = { +/* { QVMBASE, QVMBASE+QVMSIZE, &qv_mem_rd, &qv_mem_wr }, */ + { 0, 0, NULL, NULL } + }; + +/* ReadReg - read register space + + Inputs: + pa = physical address + lnt = length (BWLQ) - ignored + Output: + longword of data +*/ + +int32 ReadReg (uint32 pa, int32 lnt) +{ +struct reglink *p; + +for (p = ®table[0]; p->low != 0; p++) { + if ((pa >= p->low) && (pa < p->high) && p->read) + return p->read (pa); + } +MACH_CHECK (MCHK_READ); +} + +/* WriteReg - write register space + + Inputs: + pa = physical address + val = data to write, right justified in 32b longword + lnt = length (BWLQ) + Outputs: + none +*/ + +void WriteReg (uint32 pa, int32 val, int32 lnt) +{ +struct reglink *p; + +for (p = ®table[0]; p->low != 0; p++) { + if ((pa >= p->low) && (pa < p->high) && p->write) { + p->write (pa, val, lnt); + return; + } + } +mem_err = 1; +SET_IRQL; +} + +/* Special boot command - linked into SCP by initial reset + + Syntax: BOOT {/R5:val} + + Sets up R0-R5, calls SCP boot processor with effective BOOT CPU +*/ + +t_stat vax610_boot (int32 flag, char *ptr) +{ +t_stat r; + +r = vax610_boot_parse (flag, ptr); /* parse the boot cmd */ +if (r != SCPE_OK) /* error? */ + return r; +strncpy (cpu_boot_cmd, ptr, CBUFSIZE); /* save for reboot */ +return run_cmd (flag, "CPU"); +} + +/* Parse boot command, set up registers - also used on reset */ + +t_stat vax610_boot_parse (int32 flag, char *ptr) +{ +char gbuf[CBUFSIZE], dbuf[CBUFSIZE], rbuf[CBUFSIZE]; +char *slptr, *regptr; +int32 i, r5v, unitno; +DEVICE *dptr; +UNIT *uptr; +t_stat r; + +if (ptr && (*ptr == '/')) { /* handle "BOOT /R5:n DEV" format */ + ptr = get_glyph (ptr, rbuf, 0); /* get glyph */ + regptr = rbuf; + ptr = get_glyph (ptr, gbuf, 0); /* get glyph */ + } +else { /* handle "BOOT DEV /R5:n" format */ + regptr = get_glyph (ptr, gbuf, 0); /* get glyph */ + if ((slptr = strchr (gbuf, '/'))) { /* found slash? */ + regptr = strchr (ptr, '/'); /* locate orig */ + *slptr = 0; /* zero in string */ + } + } +/* parse R5 parameter value */ +r5v = 0; +if ((strncmp (regptr, "/R5:", 4) == 0) || + (strncmp (regptr, "/R5=", 4) == 0) || + (strncmp (regptr, "/r5:", 4) == 0) || + (strncmp (regptr, "/r5=", 4) == 0)) { + r5v = (int32) get_uint (regptr + 4, 16, LMASK, &r); + if (r != SCPE_OK) + return r; + } +else if (*regptr == '/') { + r5v = (int32) get_uint (regptr + 1, 16, LMASK, &r); + if (r != SCPE_OK) + return r; + } +else if (*regptr != 0) + return SCPE_ARG; +if (gbuf[0]) { + unitno = -1; + for (i = 0; boot_tab[i].devname != NULL; i++) { + if (memcmp (gbuf, boot_tab[i].devalias, strlen(boot_tab[i].devalias)) == 0) { + sprintf(dbuf, "%s%s", boot_tab[i].devname, gbuf + strlen(boot_tab[i].devalias)); + dptr = find_unit (dbuf, &uptr); + if ((dptr == NULL) || (uptr == NULL)) + return SCPE_ARG; + unitno = (int32) (uptr - dptr->units); + } + if ((unitno == -1) && + (memcmp (gbuf, boot_tab[i].devname, strlen(boot_tab[i].devname)) == 0)) { + sprintf(dbuf, "%s%s", boot_tab[i].devname, gbuf + strlen(boot_tab[i].devname)); + dptr = find_unit (dbuf, &uptr); + if ((dptr == NULL) || (uptr == NULL)) + return SCPE_ARG; + unitno = (int32) (uptr - dptr->units); + } + if (unitno == -1) + continue; + R[0] = boot_tab[i].code | (('0' + unitno) << 24); + R[1] = 0xC0; + R[2] = 0; + R[3] = 0; + R[4] = 0; + R[5] = r5v; + return SCPE_OK; + } + } +else { + R[0] = 0; + R[1] = 0xC0; + R[2] = 0; + R[3] = 0; + R[4] = 0; + R[5] = r5v; + return SCPE_OK; + } +return SCPE_NOFNC; +} + +int32 sysd_hlt_enb (void) +{ +return 1; +} + +/* Machine check */ + +int32 machine_check (int32 p1, int32 opc, int32 cc, int32 delta) +{ +int32 p2, acc; + +p2 = mchk_va + 4; /* save vap */ +cc = intexc (SCB_MCHK, cc, 0, IE_EXC); /* take exception */ +acc = ACC_MASK (KERN); /* in kernel mode */ +in_ie = 1; +SP = SP - 16; /* push 4 words */ +Write (SP, 12, L_LONG, WA); /* # bytes */ +Write (SP + 4, p1, L_LONG, WA); /* mcheck type */ +Write (SP + 8, p2, L_LONG, WA); /* parameter 1 */ +Write (SP + 12, p2, L_LONG, WA); /* parameter 2 */ +in_ie = 0; +return cc; +} + +/* Console entry */ + +int32 con_halt (int32 code, int32 cc) +{ +if ((cpu_boot_cmd[0] == 0) || /* saved boot cmd? */ + (vax610_boot_parse (0, cpu_boot_cmd) != SCPE_OK) || /* reparse the boot cmd */ + (reset_all (0) != SCPE_OK) || /* reset the world */ + (cpu_boot (0, NULL) != SCPE_OK)) /* set up boot code */ + ABORT (STOP_BOOT); /* any error? */ +printf ("Rebooting...\n"); +if (sim_log) + fprintf (sim_log, "Rebooting...\n"); +return cc; +} + +/* Bootstrap */ + +t_stat cpu_boot (int32 unitno, DEVICE *dptr) +{ +t_stat r; + +r = cpu_load_bootcode (BOOT_CODE_FILENAME, BOOT_CODE_ARRAY, BOOT_CODE_SIZE, FALSE, 0x200); +if (r != SCPE_OK) + return r; +SP = PC = 512; +AP = 1; +return SCPE_OK; +} + +/* SYSD reset */ + +t_stat sysd_reset (DEVICE *dptr) +{ +sim_vm_cmd = vax610_cmd; +return SCPE_OK; +} + +t_stat cpu_set_model (UNIT *uptr, int32 val, char *cptr, void *desc) +{ +return SCPE_NOFNC; +} + +t_stat cpu_print_model (FILE *st) +{ +fprintf (st, "MicroVAX I"); +return SCPE_OK; +} + +t_stat cpu_model_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr) +{ +fprintf (st, "Initial memory size is 4MB.\n\n"); +fprintf (st, "The simulator is booted with the BOOT command:\n\n"); +fprintf (st, " sim> BO{OT} {/R5:flags}\n\n"); +fprintf (st, "where is one of:\n\n"); +fprintf (st, " RQn to boot from rqn\n"); +fprintf (st, " DUn to boot from rqn\n"); +fprintf (st, " DUAn to boot from rqn\n"); +fprintf (st, " XQ to boot from xq\n"); +fprintf (st, " XQA to boot from xq\n\n"); +return SCPE_OK; +} diff --git a/VAX/vax610_syslist.c b/VAX/vax610_syslist.c new file mode 100644 index 00000000..c262fad5 --- /dev/null +++ b/VAX/vax610_syslist.c @@ -0,0 +1,113 @@ +/* vax610_syslist.c: MicroVAX I device list + + Copyright (c) 2011-2012, Matt Burke + This module incorporates code from SimH, Copyright (c) 1998-2008, Robert M Supnik + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name(s) of the author(s) shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from the author(s). + + 15-Feb-2012 MB First version +*/ + +#include "vax_defs.h" + +char sim_name[] = "VAX610"; + +extern DEVICE cpu_dev; +extern DEVICE mctl_dev; +extern DEVICE tlb_dev; +extern DEVICE sysd_dev; +extern DEVICE qba_dev; +extern DEVICE tti_dev, tto_dev; +extern DEVICE cr_dev; +extern DEVICE lpt_dev; +extern DEVICE clk_dev; +extern DEVICE rq_dev, rqb_dev, rqc_dev, rqd_dev; +extern DEVICE rl_dev; +extern DEVICE ry_dev; +extern DEVICE ts_dev; +extern DEVICE tq_dev; +extern DEVICE dz_dev; +extern DEVICE xq_dev, xqb_dev; +extern DEVICE vh_dev; + +extern void WriteB (uint32 pa, int32 val); +extern UNIT cpu_unit; + +DEVICE *sim_devices[] = { + &cpu_dev, + &mctl_dev, + &tlb_dev, + &sysd_dev, + &qba_dev, + &clk_dev, + &tti_dev, + &tto_dev, + &dz_dev, + &vh_dev, + &cr_dev, + &lpt_dev, + &rl_dev, + &rq_dev, + &rqb_dev, + &rqc_dev, + &rqd_dev, + &ry_dev, + &ts_dev, + &tq_dev, + &xq_dev, + &xqb_dev, + NULL + }; + +/* Binary loader + + The binary loader handles absolute system images, that is, system + images linked /SYSTEM. These are simply a byte stream, with no + origin or relocation information. + + -o for memory, specify origin +*/ + +t_stat sim_load (FILE *fileref, char *cptr, char *fnam, int flag) +{ +t_stat r; +int32 i; +uint32 origin, limit; + +if (flag) /* dump? */ + return SCPE_ARG; +origin = 0; /* memory */ +limit = (uint32) cpu_unit.capac; +if (sim_switches & SWMASK ('O')) { /* origin? */ + origin = (int32) get_uint (cptr, 16, 0xFFFFFFFF, &r); + if (r != SCPE_OK) + return SCPE_ARG; + } +while ((i = getc (fileref)) != EOF) { /* read byte stream */ + if (origin >= limit) /* NXM? */ + return SCPE_NXM; + else WriteB (origin, i); /* store byte */ + origin = origin + 1; + } +return SCPE_OK; +} + diff --git a/VAX/vax630_defs.h b/VAX/vax630_defs.h new file mode 100644 index 00000000..ba868037 --- /dev/null +++ b/VAX/vax630_defs.h @@ -0,0 +1,388 @@ +/* vax630_defs.h: MicroVAX II model-specific definitions file + + Copyright (c) 2009-2012, Matt Burke + This module incorporates code from SimH, Copyright (c) 1998-2008, Robert M Supnik + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name(s) of the author(s) shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from the author(s). + + 08-Nov-12 MB First version + + This file covers the KA630 ("Mayflower") Qbus system. + + System memory map + + 0000 0000 - 00FF FFFF main memory + 0100 0000 - 1FFF FFFF reserved + + 2000 0000 - 2000 1FFF Qbus I/O page + 2004 0000 - 2004 FFFF ROM space, halt protected + 2005 0000 - 2005 FFFF ROM space, halt unprotected + 2008 0000 - 2008 000F Local register space + 2008 8000 - 2008 FFFF Qbus mapping registers + 200B 8000 - 200B 80FF Watch chip registers + 3000 0000 - 303F FFFF Qbus memory space + 3400 0000 - 3FFF FFFF reserved +*/ + +#ifdef FULL_VAX /* subset VAX */ +#undef FULL_VAX +#endif + +#ifndef _VAX_630_DEFS_H_ +#define _VAX_630_DEFS_H_ 1 + +/* Microcode constructs */ + +#define VAX620_SID (16 << 24) /* system ID */ +#define VAX630_SID (8 << 24) /* system ID */ +#define CON_HLTPIN 0x0200 /* external CPU halt */ +#define CON_PWRUP 0x0300 /* powerup code */ +#define CON_HLTINS 0x0600 /* HALT instruction */ +#define CON_DBLMCK 0x0500 /* Machine check in machine check */ +#define CON_BADPSL 0x4000 /* invalid PSL flag */ +#define CON_MAPON 0x8000 /* mapping on flag */ +#define MCHK_TBM_P0 0x05 /* PPTE in P0 */ +#define MCHK_TBM_P1 0x06 /* PPTE in P1 */ +#define MCHK_M0_P0 0x07 /* PPTE in P0 */ +#define MCHK_M0_P1 0x08 /* PPTE in P1 */ +#define MCHK_INTIPL 0x09 /* invalid ireq */ +#define MCHK_READ 0x80 /* read check */ +#define MCHK_WRITE 0x82 /* write check */ + +/* Machine specific IPRs */ + +#define MT_TBDR 36 /* Translation Buffer Disable */ +#define MT_CADR 37 /* Cache Disable Register */ +#define MT_MCESR 38 /* Machine Check Error Summary */ +#define MT_CAER 39 /* Cache Error Register */ +#define MT_CONISP 41 /* Console Saved ISP */ +#define MT_CONPC 42 /* Console Saved PC */ +#define MT_CONPSL 43 /* Console Saved PSL */ +#define MT_SBIFS 48 /* SBI fault status */ +#define MT_SBIS 49 /* SBI silo */ +#define MT_SBISC 50 /* SBI silo comparator */ +#define MT_SBIMT 51 /* SBI maint */ +#define MT_SBIER 52 /* SBI error */ +#define MT_SBITA 53 /* SBI timeout addr */ +#define MT_SBIQC 54 /* SBI timeout clear */ +#define MT_IORESET 55 /* I/O Bus Reset */ +#define MT_TBDATA 59 /* Translation Buffer Data */ +#define MT_MBRK 60 /* microbreak */ +#define MT_MAX 63 /* last valid IPR */ + +/* CPU */ + +#define CPU_MODEL_MODIFIERS \ + { MTAB_XTD|MTAB_VDV, 0, "MODEL", NULL, \ + NULL, &cpu_show_model }, +/* Memory */ + +#define MAXMEMWIDTH 24 /* max mem, std KA655 */ +#define MAXMEMSIZE (1 << MAXMEMWIDTH) /* max mem size */ +#define MAXMEMWIDTH_X 24 /* max mem, KA655X */ +#define MAXMEMSIZE_X (1 << MAXMEMWIDTH_X) +#define INITMEMSIZE (1 << 24) /* initial memory size */ +#define MEMSIZE (cpu_unit.capac) +#define ADDR_IS_MEM(x) (((uint32) (x)) < MEMSIZE) +#define MEM_MODIFIERS { UNIT_MSIZE, (1u << 20), NULL, "1M", &cpu_set_size }, \ + { UNIT_MSIZE, (1u << 21), NULL, "2M", &cpu_set_size }, \ + { UNIT_MSIZE, (1u << 22), NULL, "4M", &cpu_set_size }, \ + { UNIT_MSIZE, (1u << 23), NULL, "8M", &cpu_set_size }, \ + { UNIT_MSIZE, (1u << 23) + (1u << 22), NULL, "12M", &cpu_set_size }, \ + { UNIT_MSIZE, (1u << 24), NULL, "16M", &cpu_set_size } +#define CPU_MODEL_MODIFIERS \ + { MTAB_XTD|MTAB_VDV, 0, "MODEL", NULL, \ + NULL, &cpu_show_model }, + +/* Qbus I/O page */ + +#define IOPAGEAWIDTH 13 /* IO addr width */ +#define IOPAGESIZE (1u << IOPAGEAWIDTH) /* IO page length */ +#define IOPAGEMASK (IOPAGESIZE - 1) /* IO addr mask */ +#define IOPAGEBASE 0x20000000 /* IO page base */ +#define ADDR_IS_IO(x) ((((uint32) (x)) >= IOPAGEBASE) && \ + (((uint32) (x)) < (IOPAGEBASE + IOPAGESIZE))) + +/* Read only memory - appears twice */ + +#define ROMAWIDTH 16 /* ROM addr width */ +#define ROMSIZE (1u << ROMAWIDTH) /* ROM length */ +#define ROMAMASK (ROMSIZE - 1) /* ROM addr mask */ +#define ROMBASE 0x20040000 /* ROM base */ +#define ADDR_IS_ROM(x) ((((uint32) (x)) >= ROMBASE) && \ + (((uint32) (x)) < (ROMBASE + ROMSIZE + ROMSIZE))) + +/* KA630 board registers */ + +#define KAAWIDTH 4 /* REG addr width */ +#define KASIZE (1u << KAAWIDTH) /* REG length */ +#define KABASE 0x20080000 /* REG addr base */ + +/* Qbus map registers */ + +#define QBMAPAWIDTH 15 /* map addr width */ +#define QBMAPSIZE (1u << QBMAPAWIDTH) /* map length */ +#define QBMAPAMASK (QBMAPSIZE - 1) /* map addr mask */ +#define QBMAPBASE 0x20088000 /* map addr base */ + +/* Non-volatile RAM - 128 Bytes long */ + +#define NVRAWIDTH 7 /* NVR addr width */ +#define NVRSIZE (1u << NVRAWIDTH) /* NVR length */ +#define NVRAMASK (NVRSIZE - 1) /* NVR addr mask */ +#define NVRBASE 0x200B8000 /* NVR base */ +#define ADDR_IS_NVR(x) ((((uint32) (x)) >= NVRBASE) && \ + (((uint32) (x)) < (NVRBASE + NVRSIZE))) + +/* Qbus memory space */ + +#define QBMAWIDTH 22 /* Qmem addr width */ +#define QBMSIZE (1u << QBMAWIDTH) /* Qmem length */ +#define QBMAMASK (QBMSIZE - 1) /* Qmem addr mask */ +#define QBMBASE 0x30000000 /* Qmem base */ +#define ADDR_IS_QBM(x) ((((uint32) (x)) >= QBMBASE) && \ + (((uint32) (x)) < (QBMBASE + QBMSIZE))) + +/* Other address spaces */ + +#define ADDR_IS_CDG(x) (0) + +/* Machine specific reserved operand tests (all NOPs) */ + +#define ML_PA_TEST(r) +#define ML_LR_TEST(r) +#define ML_SBR_TEST(r) +#define ML_PXBR_TEST(r) +#define LP_AST_TEST(r) +#define LP_MBZ84_TEST(r) +#define LP_MBZ92_TEST(r) + +/* Qbus I/O modes */ + +#define READ 0 /* PDP-11 compatibility */ +#define WRITE (L_WORD) +#define WRITEB (L_BYTE) + +/* Common CSI flags */ + +#define CSR_V_GO 0 /* go */ +#define CSR_V_IE 6 /* interrupt enable */ +#define CSR_V_DONE 7 /* done */ +#define CSR_V_BUSY 11 /* busy */ +#define CSR_V_ERR 15 /* error */ +#define CSR_GO (1u << CSR_V_GO) +#define CSR_IE (1u << CSR_V_IE) +#define CSR_DONE (1u << CSR_V_DONE) +#define CSR_BUSY (1u << CSR_V_BUSY) +#define CSR_ERR (1u << CSR_V_ERR) + +/* Timers */ + +#define TMR_CLK 0 /* 100Hz clock */ + +/* I/O system definitions */ + +#define DZ_MUXES 4 /* max # of DZV muxes */ +#define DZ_LINES 4 /* lines per DZV mux */ +#define VH_MUXES 4 /* max # of DHQ muxes */ +#define DLX_LINES 16 /* max # of KL11/DL11's */ +#define DCX_LINES 16 /* max # of DC11's */ +#define MT_MAXFR (1 << 16) /* magtape max rec */ +#define AUTO_LNT 34 /* autoconfig ranks */ + +#define DEV_V_UBUS (DEV_V_UF + 0) /* Unibus */ +#define DEV_V_QBUS (DEV_V_UF + 1) /* Qbus */ +#define DEV_V_Q18 (DEV_V_UF + 2) /* Qbus, mem <= 256KB */ +#define DEV_UBUS (1u << DEV_V_UBUS) +#define DEV_QBUS (1u << DEV_V_QBUS) +#define DEV_Q18 (1u << DEV_V_Q18) + +#define UNIBUS FALSE /* 22b only */ + +#define DEV_RDX 16 /* default device radix */ + +/* Device information block */ + +#define VEC_DEVMAX 4 /* max device vec */ + +typedef struct { + uint32 ba; /* base addr */ + uint32 lnt; /* length */ + t_stat (*rd)(int32 *dat, int32 ad, int32 md); + t_stat (*wr)(int32 dat, int32 ad, int32 md); + int32 vnum; /* vectors: number */ + int32 vloc; /* locator */ + int32 vec; /* value */ + int32 (*ack[VEC_DEVMAX])(void); /* ack routine */ + } DIB; + +/* Qbus I/O page layout - see pdp11_ui_lib.c for address layout details */ + +#define IOBA_AUTO (0) /* Assigned by Auto Configure */ + + +/* The KA620/KA630 maintains 4 separate hardware IPL levels, IPL 17 to IPL 14; + however, DEC Qbus controllers all interrupt on IPL 14 + Within each IPL, priority is right to left +*/ + +/* IPL 17 */ + +/* IPL 16 */ + +#define INT_V_CLK 0 /* clock */ + +/* IPL 15 */ + +/* IPL 14 - devices through RY are IPL 15 on Unibus systems */ + +#define INT_V_RQ 0 /* RQDX3 */ +#define INT_V_RL 1 /* RLV12/RL02 */ +#define INT_V_DZRX 2 /* DZ11 */ +#define INT_V_DZTX 3 +#define INT_V_TS 4 /* TS11/TSV05 */ +#define INT_V_TQ 5 /* TMSCP */ +#define INT_V_XQ 6 /* DEQNA/DELQA */ +#define INT_V_RY 7 /* RXV21 */ + +#define INT_V_TTI 8 /* console */ +#define INT_V_TTO 9 +#define INT_V_PTR 10 /* PC11 */ +#define INT_V_PTP 11 +#define INT_V_LPT 12 /* LP11 */ +#define INT_V_CSI 13 /* SSC cons UART */ +#define INT_V_CSO 14 +#define INT_V_TMR0 15 /* SSC timers */ +#define INT_V_TMR1 16 +#define INT_V_VHRX 17 /* DHQ11 */ +#define INT_V_VHTX 18 +#define INT_V_QDSS 19 /* QDSS */ +#define INT_V_CR 20 +#define INT_V_QVSS 21 /* QVSS */ +#define INT_V_DMCRX 22 +#define INT_V_DMCTX 23 + +#define INT_CLK (1u << INT_V_CLK) +#define INT_RQ (1u << INT_V_RQ) +#define INT_RL (1u << INT_V_RL) +#define INT_DZRX (1u << INT_V_DZRX) +#define INT_DZTX (1u << INT_V_DZTX) +#define INT_TS (1u << INT_V_TS) +#define INT_TQ (1u << INT_V_TQ) +#define INT_XQ (1u << INT_V_XQ) +#define INT_RY (1u << INT_V_RY) +#define INT_TTI (1u << INT_V_TTI) +#define INT_TTO (1u << INT_V_TTO) +#define INT_PTR (1u << INT_V_PTR) +#define INT_PTP (1u << INT_V_PTP) +#define INT_LPT (1u << INT_V_LPT) +#define INT_CSI (1u << INT_V_CSI) +#define INT_CSO (1u << INT_V_CSO) +#define INT_TMR0 (1u << INT_V_TMR0) +#define INT_TMR1 (1u << INT_V_TMR1) +#define INT_VHRX (1u << INT_V_VHRX) +#define INT_VHTX (1u << INT_V_VHTX) +#define INT_QDSS (1u << INT_V_QDSS) +#define INT_CR (1u << INT_V_CR) +#define INT_QVSS (1u << INT_V_QVSS) +#define INT_DMCRX (1u << INT_V_DMCRX) +#define INT_DMCTX (1u << INT_V_DMCTX) + +#define IPL_CLK (0x16 - IPL_HMIN) /* relative IPL */ +#define IPL_RQ (0x14 - IPL_HMIN) +#define IPL_RL (0x14 - IPL_HMIN) +#define IPL_DZRX (0x14 - IPL_HMIN) +#define IPL_DZTX (0x14 - IPL_HMIN) +#define IPL_TS (0x14 - IPL_HMIN) +#define IPL_TQ (0x14 - IPL_HMIN) +#define IPL_XQ (0x14 - IPL_HMIN) +#define IPL_RY (0x14 - IPL_HMIN) +#define IPL_TTI (0x14 - IPL_HMIN) +#define IPL_TTO (0x14 - IPL_HMIN) +#define IPL_PTR (0x14 - IPL_HMIN) +#define IPL_PTP (0x14 - IPL_HMIN) +#define IPL_LPT (0x14 - IPL_HMIN) +#define IPL_CSI (0x14 - IPL_HMIN) +#define IPL_CSO (0x14 - IPL_HMIN) +#define IPL_TMR0 (0x14 - IPL_HMIN) +#define IPL_TMR1 (0x14 - IPL_HMIN) +#define IPL_VHRX (0x14 - IPL_HMIN) +#define IPL_VHTX (0x14 - IPL_HMIN) +#define IPL_QDSS (0x14 - IPL_HMIN) +#define IPL_CR (0x14 - IPL_HMIN) +#define IPL_QVSS (0x14 - IPL_HMIN) +#define IPL_DMCRX (0x15 - IPL_HMIN) +#define IPL_DMCTX (0x15 - IPL_HMIN) + +#define IPL_HMAX 0x17 /* highest hwre level */ +#define IPL_HMIN 0x14 /* lowest hwre level */ +#define IPL_HLVL (IPL_HMAX - IPL_HMIN + 1) /* # hardware levels */ +#define IPL_SMAX 0xF /* highest swre level */ + +/* Device vectors */ + +#define VEC_AUTO (0) /* Assigned by Auto Configure */ +#define VEC_FLOAT (0) /* Assigned by Auto Configure */ + +#define VEC_QBUS 1 /* Qbus system */ +#define VEC_Q 0x200 /* Qbus vector offset */ + +/* Interrupt macros */ + +#define IVCL(dv) ((IPL_##dv * 32) + INT_V_##dv) +#define IREQ(dv) int_req[IPL_##dv] +#define SET_INT(dv) int_req[IPL_##dv] = int_req[IPL_##dv] | (INT_##dv) +#define CLR_INT(dv) int_req[IPL_##dv] = int_req[IPL_##dv] & ~(INT_##dv) +#define IORETURN(f,v) ((f)? (v): SCPE_OK) /* cond error return */ + +/* Logging */ + +#define LOG_CPU_I 0x1 /* intexc */ +#define LOG_CPU_R 0x2 /* REI */ +#define LOG_CPU_P 0x4 /* context */ + +/* Function prototypes for virtual memory interface */ + +int32 Read (uint32 va, int32 lnt, int32 acc); +void Write (uint32 va, int32 val, int32 lnt, int32 acc); + +/* Function prototypes for physical memory interface (inlined) */ + +SIM_INLINE int32 ReadB (uint32 pa); +SIM_INLINE int32 ReadW (uint32 pa); +SIM_INLINE int32 ReadL (uint32 pa); +SIM_INLINE int32 ReadLP (uint32 pa); +SIM_INLINE void WriteB (uint32 pa, int32 val); +SIM_INLINE void WriteW (uint32 pa, int32 val); +SIM_INLINE void WriteL (uint32 pa, int32 val); +void WriteLP (uint32 pa, int32 val); + +/* Function prototypes for I/O */ + +int32 Map_ReadB (uint32 ba, int32 bc, uint8 *buf); +int32 Map_ReadW (uint32 ba, int32 bc, uint16 *buf); +int32 Map_WriteB (uint32 ba, int32 bc, uint8 *buf); +int32 Map_WriteW (uint32 ba, int32 bc, uint16 *buf); + +#include "pdp11_io_lib.h" + +#endif diff --git a/VAX/vax630_io.c b/VAX/vax630_io.c new file mode 100644 index 00000000..40e973ce --- /dev/null +++ b/VAX/vax630_io.c @@ -0,0 +1,622 @@ +/* vax630_io.c: MicroVAX II Qbus IO simulator + + Copyright (c) 2009-2012, Matt Burke + This module incorporates code from SimH, Copyright (c) 1998-2008, Robert M Supnik + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name(s) of the author(s) shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from the author(s). + + qba Qbus adapter + + 08-Nov-2012 MB First version +*/ + +#include "vax_defs.h" + +/* Qbus IPC register */ + +#define QBIPC_QPE 0x00008000 /* Qbus dma parity err */ +#define QBIPC_AHLT 0x00000100 /* aux halt NI */ +#define QBIPC_DBIE 0x00000040 /* dbell int enb NI */ +#define QBIPC_LME 0x00000020 /* local mem enb */ +#define QBIPC_DB 0x00000001 /* doorbell req NI */ +#define QBIPC_RW (QBIPC_AHLT | QBIPC_DBIE | QBIPC_LME | QBIPC_DB) +#define QBIPC_MASK (QBIPC_RW | QBIPC_QPE ) + +/* Qbus map registers */ + +#define QBNMAPR 8192 /* number of map reg */ +#define QBMAP_VLD 0x80000000 /* valid */ +#define QBMAP_PAG 0x00007FFF /* mem page */ +#define QBMAP_RD (QBMAP_VLD | QBMAP_PAG) +#define QBMAP_WR (QBMAP_VLD | QBMAP_PAG) + +/* KA630 Memory system error register */ + +#define MSER_NXM 0x00000080 /* CPU NXM */ + +int32 int_req[IPL_HLVL] = { 0 }; /* intr, IPL 14-17 */ +int32 qb_ipc = 0; /* IPC */ +int32 qb_map[QBNMAPR] = { 0 }; /* map registers */ +int32 autcon_enb = 1; /* autoconfig enable */ + +extern int32 R[16]; +extern uint32 *M; +extern UNIT cpu_unit; +extern int32 PSL, SISR, trpirq, mem_err, hlt_pin; +extern int32 p1; +extern jmp_buf save_env; +extern int32 ka_mser; /* KA630 mem sys err */ + +t_stat dbl_rd (int32 *data, int32 addr, int32 access); +t_stat dbl_wr (int32 data, int32 addr, int32 access); +int32 eval_int (void); +t_stat qba_reset (DEVICE *dptr); +t_stat qba_ex (t_value *vptr, t_addr exta, UNIT *uptr, int32 sw); +t_stat qba_dep (t_value val, t_addr exta, UNIT *uptr, int32 sw); +t_bool qba_map_addr (uint32 qa, uint32 *ma); +t_bool qba_map_addr_c (uint32 qa, uint32 *ma); +t_stat set_autocon (UNIT *uptr, int32 val, char *cptr, void *desc); +t_stat show_autocon (FILE *st, UNIT *uptr, int32 val, void *desc); +t_stat show_iospace (FILE *st, UNIT *uptr, int32 val, void *desc); +t_stat qba_show_virt (FILE *of, UNIT *uptr, int32 val, void *desc); + +/* Qbus adapter data structures + + qba_dev QBA device descriptor + qba_unit QBA units + qba_reg QBA register list +*/ + +#define IOLN_DBL 002 + +DIB qba_dib = { IOBA_AUTO, IOLN_DBL, &dbl_rd, &dbl_wr, 0 }; + +UNIT qba_unit = { UDATA (NULL, 0, 0) }; + +REG qba_reg[] = { + { HRDATAD (IPC, qb_ipc, 16, "interprocessor communications register") }, + { HRDATAD (IPL17, int_req[3], 32, "IPL 17 interrupt flags"), REG_RO }, + { HRDATAD (IPL16, int_req[2], 32, "IPL 16 interrupt flags"), REG_RO }, + { HRDATAD (IPL15, int_req[1], 32, "IPL 15 interrupt flags"), REG_RO }, + { HRDATAD (IPL14, int_req[0], 32, "IPL 14 interrupt flags"), REG_RO }, + { BRDATAD (MAP, qb_map, 16, 32, QBNMAPR, "map registers") }, + { FLDATA (AUTOCON, autcon_enb, 0), REG_HRO }, + { NULL } + }; + +MTAB qba_mod[] = { + { MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, "IOSPACE", NULL, + NULL, &show_iospace }, + { MTAB_XTD|MTAB_VDV, 1, "AUTOCONFIG", "AUTOCONFIG", + &set_autocon, &show_autocon }, + { MTAB_XTD|MTAB_VDV, 0, NULL, "NOAUTOCONFIG", + &set_autocon, NULL }, + { MTAB_XTD|MTAB_VDV|MTAB_NMO|MTAB_SHP, 0, "VIRTUAL", NULL, + NULL, &qba_show_virt }, + { 0 } + }; + +DEVICE qba_dev = { + "QBA", &qba_unit, qba_reg, qba_mod, + 1, 16, QBMAWIDTH, 2, 16, 16, + &qba_ex, &qba_dep, &qba_reset, + NULL, NULL, NULL, + &qba_dib, DEV_QBUS + }; + +/* IO page dispatches */ + +t_stat (*iodispR[IOPAGESIZE >> 1])(int32 *dat, int32 ad, int32 md); +t_stat (*iodispW[IOPAGESIZE >> 1])(int32 dat, int32 ad, int32 md); + +/* Interrupt request to interrupt action map */ + +int32 (*int_ack[IPL_HLVL][32])(void); /* int ack routines */ + +/* Interrupt request to vector map */ + +int32 int_vec[IPL_HLVL][32]; /* int req to vector */ + +/* The KA620/KA630 handles errors in I/O space as follows + + - read: machine check + - write: machine check (?) +*/ + +int32 ReadQb (uint32 pa) +{ +int32 idx, val; + +idx = (pa & IOPAGEMASK) >> 1; +if (iodispR[idx]) { + iodispR[idx] (&val, pa, READ); + return val; + } +MACH_CHECK (MCHK_READ); +return 0; +} + +void WriteQb (uint32 pa, int32 val, int32 mode) +{ +int32 idx; + +idx = (pa & IOPAGEMASK) >> 1; +if (iodispW[idx]) { + iodispW[idx] (val, pa, mode); + return; + } +MACH_CHECK (MCHK_WRITE); +return; +} + +/* ReadIO - read I/O space + + Inputs: + pa = physical address + lnt = length (BWLQ) + Output: + longword of data +*/ + +int32 ReadIO (uint32 pa, int32 lnt) +{ +int32 iod; + +iod = ReadQb (pa); /* wd from Qbus */ +if (lnt < L_LONG) /* bw? position */ + iod = iod << ((pa & 2)? 16: 0); +else iod = (ReadQb (pa + 2) << 16) | iod; /* lw, get 2nd wd */ +SET_IRQL; +return iod; +} + +/* WriteIO - write I/O space + + Inputs: + pa = physical address + val = data to write, right justified in 32b longword + lnt = length (BWLQ) + Outputs: + none +*/ + +void WriteIO (uint32 pa, int32 val, int32 lnt) +{ +if (lnt == L_BYTE) + WriteQb (pa, val, WRITEB); +else if (lnt == L_WORD) + WriteQb (pa, val, WRITE); +else { + WriteQb (pa, val & 0xFFFF, WRITE); + WriteQb (pa + 2, (val >> 16) & 0xFFFF, WRITE); + } +SET_IRQL; +return; +} + +/* Find highest priority outstanding interrupt */ + +int32 eval_int (void) +{ +int32 ipl = PSL_GETIPL (PSL); +int32 i, t; + +static const int32 sw_int_mask[IPL_SMAX] = { + 0xFFFE, 0xFFFC, 0xFFF8, 0xFFF0, /* 0 - 3 */ + 0xFFE0, 0xFFC0, 0xFF80, 0xFF00, /* 4 - 7 */ + 0xFE00, 0xFC00, 0xF800, 0xF000, /* 8 - B */ + 0xE000, 0xC000, 0x8000 /* C - E */ + }; + +if (hlt_pin) /* hlt pin int */ + return IPL_HLTPIN; +for (i = IPL_HMAX; i >= IPL_HMIN; i--) { /* chk hwre int */ + if (i <= ipl) /* at ipl? no int */ + return 0; + if (int_req[i - IPL_HMIN]) /* req != 0? int */ + return i; + } +if (ipl >= IPL_SMAX) /* ipl >= sw max? */ + return 0; +if ((t = SISR & sw_int_mask[ipl]) == 0) /* eligible req */ + return 0; +for (i = IPL_SMAX; i > ipl; i--) { /* check swre int */ + if ((t >> i) & 1) /* req != 0? int */ + return i; + } +return 0; +} + +/* Return vector for highest priority hardware interrupt at IPL lvl */ + +int32 get_vector (int32 lvl) +{ +int32 i; +int32 l = lvl - IPL_HMIN; + +if (lvl > IPL_HMAX) { /* error req lvl? */ + ABORT (STOP_UIPL); /* unknown intr */ + } +for (i = 0; int_req[l] && (i < 32); i++) { + if ((int_req[l] >> i) & 1) { + int_req[l] = int_req[l] & ~(1u << i); + if (int_ack[l][i]) + return int_ack[l][i](); + return int_vec[l][i]; + } + } +return 0; +} + +/* I/O page routines */ + +t_stat dbl_rd (int32 *data, int32 addr, int32 access) +{ +*data = qb_ipc & QBIPC_MASK; +return SCPE_OK; +} + +t_stat dbl_wr (int32 data, int32 addr, int32 access) +{ +int32 sc = (addr & 3) << 3; +int32 nval = data << sc; + +qb_ipc = nval & QBIPC_RW; + +if ((addr & 3) == 0) /* low byte only */ + qb_ipc = ((qb_ipc & ~QBIPC_RW) | (data & QBIPC_RW)) & QBIPC_MASK; +qb_ipc = qb_ipc & ~QBIPC_AHLT; /* Read only on arbiter */ +if (!(qb_ipc & QBIPC_DBIE)) + qb_ipc = qb_ipc & ~QBIPC_DB; /* Read only when not DBIE */ +return SCPE_OK; +} + +/* Qbus map read and write + + Read error: machine check? + Write error: machine check? +*/ + +int32 qbmap_rd (int32 pa) +{ +int32 idx = ((pa - QBMAPBASE) >> 2); + +return qb_map[idx] & QBMAP_RD; +} + +void qbmap_wr (int32 pa, int32 val, int32 lnt) +{ +int32 idx = ((pa - QBMAPBASE) >> 2); + +if (idx < QBNMAPR) { + if (lnt < L_LONG) { + int32 sc = (pa & 3) << 3; + int32 mask = (lnt == L_WORD)? 0xFFFF: 0xFF; + int32 t = qb_map[idx]; + val = ((val & mask) << sc) | (t & ~(mask << sc)); + } + qb_map[idx] = val & QBMAP_WR; + } +else + ka_mser |= MSER_NXM; +return; +} + +/* Qbus memory read and write (reflects to main memory) + + May give master or slave error, depending on where the failure occurs +*/ + +int32 qbmem_rd (int32 pa) +{ +int32 qa = pa & QBMAMASK; /* Qbus addr */ +uint32 ma; + +if (qba_map_addr (qa, &ma)) { /* map addr */ + return M[ma >> 2]; +} +MACH_CHECK (MCHK_READ); /* err? mcheck */ +return 0; +} + +void qbmem_wr (int32 pa, int32 val, int32 lnt) +{ +int32 qa = pa & QBMAMASK; /* Qbus addr */ +uint32 ma; + +if (qba_map_addr (qa, &ma)) { /* map addr */ + if (lnt < L_LONG) { + int32 sc = (pa & 3) << 3; + int32 mask = (lnt == L_WORD)? 0xFFFF: 0xFF; + int32 t = M[ma >> 2]; + val = ((val & mask) << sc) | (t & ~(mask << sc)); + } + M[ma >> 2] = val; + } +else mem_err = 1; +return; +} + +/* Map an address via the translation map */ + +t_bool qba_map_addr (uint32 qa, uint32 *ma) +{ +int32 qblk = (qa >> VA_V_VPN); /* Qbus blk */ + +if (qblk <= QBNMAPR) { + int32 qmap = qb_map[qblk]; + if (qmap & QBMAP_VLD) { /* valid? */ + *ma = ((qmap & QBMAP_PAG) << VA_V_VPN) + VA_GETOFF (qa); + if (ADDR_IS_MEM (*ma)) /* legit addr */ + return TRUE; + ka_mser |= MSER_NXM; + return FALSE; + } + ka_mser |= MSER_NXM; + return FALSE; + } +ka_mser |= MSER_NXM; +return FALSE; +} + +/* Map an address via the translation map - console version (no status changes) */ + +t_bool qba_map_addr_c (uint32 qa, uint32 *ma) +{ +int32 qblk = (qa >> VA_V_VPN); /* Qbus blk */ + +if (qblk <= QBNMAPR) { + int32 qmap = qb_map[qblk]; + if (qmap & QBMAP_VLD) { /* valid? */ + *ma = ((qmap & QBMAP_PAG) << VA_V_VPN) + VA_GETOFF (qa); + return TRUE; + } + } +return FALSE; +} + +/* Reset I/O bus */ + +void ioreset_wr (int32 data) +{ +reset_all (5); /* from qba on... */ +return; +} + +/* Reset Qbus */ + +t_stat qba_reset (DEVICE *dptr) +{ +int32 i; + +for (i = 0; i < IPL_HLVL; i++) + int_req[i] = 0; +return SCPE_OK; +} + +/* Qbus I/O buffer routines, aligned access + + Map_ReadB - fetch byte buffer from memory + Map_ReadW - fetch word buffer from memory + Map_WriteB - store byte buffer into memory + Map_WriteW - store word buffer into memory +*/ + +int32 Map_ReadB (uint32 ba, int32 bc, uint8 *buf) +{ +int32 i; +uint32 ma, dat; + +if ((ba | bc) & 03) { /* check alignment */ + for (i = ma = 0; i < bc; i++, buf++) { /* by bytes */ + if ((ma & VA_M_OFF) == 0) { /* need map? */ + if (!qba_map_addr (ba + i, &ma)) /* inv or NXM? */ + return (bc - i); + } + *buf = ReadB (ma); + ma = ma + 1; + } + } +else { + for (i = ma = 0; i < bc; i = i + 4, buf++) { /* by longwords */ + if ((ma & VA_M_OFF) == 0) { /* need map? */ + if (!qba_map_addr (ba + i, &ma)) /* inv or NXM? */ + return (bc - i); + } + dat = ReadL (ma); /* get lw */ + *buf++ = dat & BMASK; /* low 8b */ + *buf++ = (dat >> 8) & BMASK; /* next 8b */ + *buf++ = (dat >> 16) & BMASK; /* next 8b */ + *buf = (dat >> 24) & BMASK; + ma = ma + 4; + } + } +return 0; +} + +int32 Map_ReadW (uint32 ba, int32 bc, uint16 *buf) +{ +int32 i; +uint32 ma,dat; + +ba = ba & ~01; +bc = bc & ~01; +if ((ba | bc) & 03) { /* check alignment */ + for (i = ma = 0; i < bc; i = i + 2, buf++) { /* by words */ + if ((ma & VA_M_OFF) == 0) { /* need map? */ + if (!qba_map_addr (ba + i, &ma)) /* inv or NXM? */ + return (bc - i); + } + *buf = ReadW (ma); + ma = ma + 2; + } + } +else { + for (i = ma = 0; i < bc; i = i + 4, buf++) { /* by longwords */ + if ((ma & VA_M_OFF) == 0) { /* need map? */ + if (!qba_map_addr (ba + i, &ma)) /* inv or NXM? */ + return (bc - i); + } + dat = ReadL (ma); /* get lw */ + *buf++ = dat & WMASK; /* low 16b */ + *buf = (dat >> 16) & WMASK; /* high 16b */ + ma = ma + 4; + } + } +return 0; +} + +int32 Map_WriteB (uint32 ba, int32 bc, uint8 *buf) +{ +int32 i; +uint32 ma, dat; + +if ((ba | bc) & 03) { /* check alignment */ + for (i = ma = 0; i < bc; i++, buf++) { /* by bytes */ + if ((ma & VA_M_OFF) == 0) { /* need map? */ + if (!qba_map_addr (ba + i, &ma)) /* inv or NXM? */ + return (bc - i); + } + WriteB (ma, *buf); + ma = ma + 1; + } + } +else { + for (i = ma = 0; i < bc; i = i + 4, buf++) { /* by longwords */ + if ((ma & VA_M_OFF) == 0) { /* need map? */ + if (!qba_map_addr (ba + i, &ma)) /* inv or NXM? */ + return (bc - i); + } + dat = (uint32) *buf++; /* get low 8b */ + dat = dat | (((uint32) *buf++) << 8); /* merge next 8b */ + dat = dat | (((uint32) *buf++) << 16); /* merge next 8b */ + dat = dat | (((uint32) *buf) << 24); /* merge hi 8b */ + WriteL (ma, dat); /* store lw */ + ma = ma + 4; + } + } +return 0; +} + +int32 Map_WriteW (uint32 ba, int32 bc, uint16 *buf) +{ +int32 i; +uint32 ma, dat; + +ba = ba & ~01; +bc = bc & ~01; +if ((ba | bc) & 03) { /* check alignment */ + for (i = ma = 0; i < bc; i = i + 2, buf++) { /* by words */ + if ((ma & VA_M_OFF) == 0) { /* need map? */ + if (!qba_map_addr (ba + i, &ma)) /* inv or NXM? */ + return (bc - i); + } + WriteW (ma, *buf); + ma = ma + 2; + } + } +else { + for (i = ma = 0; i < bc; i = i + 4, buf++) { /* by longwords */ + if ((ma & VA_M_OFF) == 0) { /* need map? */ + if (!qba_map_addr (ba + i, &ma)) /* inv or NXM? */ + return (bc - i); + } + dat = (uint32) *buf++; /* get low 16b */ + dat = dat | (((uint32) *buf) << 16); /* merge hi 16b */ + WriteL (ma, dat); /* store lw */ + ma = ma + 4; + } + } +return 0; +} + +/* Memory examine via map (word only) */ + +t_stat qba_ex (t_value *vptr, t_addr exta, UNIT *uptr, int32 sw) +{ +uint32 qa = (uint32) exta, pa; + +if ((vptr == NULL) || (qa >= QBMSIZE)) + return SCPE_ARG; +if (qba_map_addr_c (qa, &pa) && ADDR_IS_MEM (pa)) { + *vptr = (uint32) ReadW (pa); + return SCPE_OK; + } +return SCPE_NXM; +} + +/* Memory deposit via map (word only) */ + +t_stat qba_dep (t_value val, t_addr exta, UNIT *uptr, int32 sw) +{ +uint32 qa = (uint32) exta, pa; + +if (qa >= QBMSIZE) + return SCPE_ARG; +if (qba_map_addr_c (qa, &pa) && ADDR_IS_MEM (pa)) { + WriteW (pa, (int32) val); + return SCPE_OK; + } +return SCPE_NXM; +} + +/* Build dib_tab from device list */ + +t_stat build_dib_tab (void) +{ +int32 i; +DEVICE *dptr; +DIB *dibp; +t_stat r; + +init_ubus_tab (); /* init bus tables */ +for (i = 0; (dptr = sim_devices[i]) != NULL; i++) { /* loop thru dev */ + dibp = (DIB *) dptr->ctxt; /* get DIB */ + if (dibp && !(dptr->flags & DEV_DIS)) { /* defined, enabled? */ + r = build_ubus_tab (dptr, dibp); /* add to bus tab */ + if (r) + return r; + } /* end if enabled */ + } /* end for */ +return SCPE_OK; +} + +/* Show QBA virtual address */ + +t_stat qba_show_virt (FILE *of, UNIT *uptr, int32 val, void *desc) +{ +t_stat r; +char *cptr = (char *) desc; +uint32 qa, pa; + +if (cptr) { + qa = (uint32) get_uint (cptr, 16, QBMSIZE - 1, &r); + if (r == SCPE_OK) { + if (qba_map_addr_c (qa, &pa)) + fprintf (of, "Qbus %-X = physical %-X\n", qa, pa); + else fprintf (of, "Qbus %-X: invalid mapping\n", qa); + return SCPE_OK; + } + } +fprintf (of, "Invalid argument\n"); +return SCPE_OK; +} diff --git a/VAX/vax630_stddev.c b/VAX/vax630_stddev.c new file mode 100644 index 00000000..ac3ee57a --- /dev/null +++ b/VAX/vax630_stddev.c @@ -0,0 +1,358 @@ +/* vax630_stddev.c: MicroVAX II standard I/O devices + + Copyright (c) 2009-2012, Matt Burke + This module incorporates code from SimH, Copyright (c) 1998-2008, Robert M Supnik + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name(s) of the author(s) shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from the author(s). + + tti terminal input + tto terminal output + clk 100Hz and TODR clock + + 08-Nov-2012 MB First version +*/ + +#include "vax_defs.h" +#include "sim_tmxr.h" +#include + +#define TTICSR_IMP (CSR_DONE + CSR_IE) /* terminal input */ +#define TTICSR_RW (CSR_IE) +#define TTIBUF_ERR 0x8000 /* error */ +#define TTIBUF_OVR 0x4000 /* overrun */ +#define TTIBUF_FRM 0x2000 /* framing error */ +#define TTIBUF_RBR 0x0400 /* receive break */ +#define TTOCSR_IMP (CSR_DONE + CSR_IE) /* terminal output */ +#define TTOCSR_RW (CSR_IE) +#define CLKCSR_IMP (CSR_IE) /* real-time clock */ +#define CLKCSR_RW (CSR_IE) +#define CLK_DELAY 5000 /* 100 Hz */ +#define TMXR_MULT 1 /* 100 Hz */ + +extern int32 int_req[IPL_HLVL]; +extern int32 hlt_pin; + +int32 tti_csr = 0; /* control/status */ +int32 tto_csr = 0; /* control/status */ +int32 clk_csr = 0; /* control/status */ +int32 clk_tps = 100; /* ticks/second */ +int32 tmxr_poll = CLK_DELAY * TMXR_MULT; /* term mux poll */ +int32 tmr_poll = CLK_DELAY; /* pgm timer poll */ + +t_stat tti_svc (UNIT *uptr); +t_stat tto_svc (UNIT *uptr); +t_stat clk_svc (UNIT *uptr); +t_stat tti_reset (DEVICE *dptr); +t_stat tto_reset (DEVICE *dptr); +t_stat clk_reset (DEVICE *dptr); + +extern int32 sysd_hlt_enb (void); + +/* TTI data structures + + tti_dev TTI device descriptor + tti_unit TTI unit descriptor + tti_reg TTI register list +*/ + +DIB tti_dib = { 0, 0, NULL, NULL, 1, IVCL (TTI), SCB_TTI, { NULL } }; + +UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), 0 }; + +REG tti_reg[] = { + { HRDATAD (BUF, tti_unit.buf, 16, "last data item processed") }, + { HRDATAD (CSR, tti_csr, 16, "control/status register") }, + { FLDATAD (INT, int_req[IPL_TTI], INT_V_TTI, "interrupt pending flag") }, + { FLDATAD (ERR, tti_csr, CSR_V_ERR, "error flag (CSR<15>)") }, + { FLDATAD (DONE, tti_csr, CSR_V_DONE, "device done flag (CSR<7>)") }, + { FLDATAD (IE, tti_csr, CSR_V_IE, "interrupt enable flag (CSR<6>)") }, + { DRDATAD (POS, tti_unit.pos, T_ADDR_W, "number of characters input"), PV_LEFT }, + { DRDATAD (TIME, tti_unit.wait, 24, "input polling interval"), PV_LEFT }, + { NULL } + }; + +MTAB tti_mod[] = { + { TT_MODE, TT_MODE_7B, "7b", "7B", NULL }, + { TT_MODE, TT_MODE_8B, "8b", "8B", NULL }, + { MTAB_XTD|MTAB_VDV, 0, "VECTOR", NULL, + NULL, &show_vec, NULL }, + { 0 } + }; + +DEVICE tti_dev = { + "TTI", &tti_unit, tti_reg, tti_mod, + 1, 10, 31, 1, 16, 8, + NULL, NULL, &tti_reset, + NULL, NULL, NULL, + &tti_dib, 0 + }; + +/* TTO data structures + + tto_dev TTO device descriptor + tto_unit TTO unit descriptor + tto_reg TTO register list +*/ + +DIB tto_dib = { 0, 0, NULL, NULL, 1, IVCL (TTO), SCB_TTO, { NULL } }; + +UNIT tto_unit = { UDATA (&tto_svc, TT_MODE_8B, 0), SERIAL_OUT_WAIT }; + +REG tto_reg[] = { + { HRDATAD (BUF, tto_unit.buf, 8, "last data item processed") }, + { HRDATAD (CSR, tto_csr, 16, "control/status register") }, + { FLDATAD (INT, int_req[IPL_TTO], INT_V_TTO, "interrupt pending flag") }, + { FLDATAD (ERR, tto_csr, CSR_V_ERR, "error flag (CSR<15>)") }, + { FLDATAD (DONE, tto_csr, CSR_V_DONE, "device done flag (CSR<7>)") }, + { FLDATAD (IE, tto_csr, CSR_V_IE, "interrupt enable flag (CSR<6>)") }, + { DRDATAD (POS, tto_unit.pos, T_ADDR_W, "number of characters output"), PV_LEFT }, + { DRDATAD (TIME, tto_unit.wait, 24, "time from I/O initiation to interrupt"), PV_LEFT }, + { NULL } + }; + +MTAB tto_mod[] = { + { TT_MODE, TT_MODE_7B, "7b", "7B", NULL }, + { TT_MODE, TT_MODE_8B, "8b", "8B", NULL }, + { TT_MODE, TT_MODE_7P, "7p", "7P", NULL }, + { MTAB_XTD|MTAB_VDV, 0, "VECTOR", NULL, NULL, &show_vec }, + { 0 } + }; + +DEVICE tto_dev = { + "TTO", &tto_unit, tto_reg, tto_mod, + 1, 10, 31, 1, 16, 8, + NULL, NULL, &tto_reset, + NULL, NULL, NULL, + &tto_dib, 0 + }; + +/* CLK data structures + + clk_dev CLK device descriptor + clk_unit CLK unit descriptor + clk_reg CLK register list +*/ + +DIB clk_dib = { 0, 0, NULL, NULL, 1, IVCL (CLK), SCB_INTTIM, { NULL } }; + +UNIT clk_unit = { UDATA (&clk_svc, UNIT_IDLE, 0), CLK_DELAY }; + +REG clk_reg[] = { + { HRDATAD (CSR, clk_csr, 16, "control/status register") }, + { FLDATAD (INT, int_req[IPL_CLK], INT_V_CLK, "interrupt pending flag") }, + { FLDATAD (IE, clk_csr, CSR_V_IE, "interrupt enable flag (CSR<6>)") }, + { DRDATAD (TIME, clk_unit.wait, 24, "initial poll interval"), REG_NZ + PV_LEFT }, + { DRDATAD (POLL, tmr_poll, 24, "calibrated poll interval"), REG_NZ + PV_LEFT + REG_HRO }, + { DRDATAD (TPS, clk_tps, 8, "ticks per second (100)"), REG_NZ + PV_LEFT }, +#if defined (SIM_ASYNCH_IO) + { DRDATAD (ASYNCH, sim_asynch_enabled, 1, "asynch I/O enabled flag"), PV_LEFT }, + { DRDATAD (LATENCY, sim_asynch_latency, 32, "desired asynch interrupt latency"), PV_LEFT }, + { DRDATAD (INST_LATENCY, sim_asynch_inst_latency, 32, "calibrated instruction latency"), PV_LEFT }, +#endif + { NULL } + }; + +DEVICE clk_dev = { + "CLK", &clk_unit, clk_reg, NULL, + 1, 0, 0, 0, 0, 0, + NULL, NULL, &clk_reset, + NULL, NULL, NULL, + &clk_dib, 0 + }; + +/* Clock and terminal MxPR routines + + iccs_rd/wr interval timer + todr_rd/wr time of year clock + rxcs_rd/wr input control/status + rxdb_rd input buffer + txcs_rd/wr output control/status + txdb_wr output buffer +*/ + +int32 iccs_rd (void) +{ +return (clk_csr & CLKCSR_IMP); +} + +int32 rxcs_rd (void) +{ +return (tti_csr & TTICSR_IMP); +} + +int32 rxdb_rd (void) +{ +int32 t = tti_unit.buf; /* char + error */ + +tti_csr = tti_csr & ~CSR_DONE; /* clr done */ +tti_unit.buf = tti_unit.buf & 0377; /* clr errors */ +CLR_INT (TTI); +return t; +} + +int32 txcs_rd (void) +{ +return (tto_csr & TTOCSR_IMP); +} + +void iccs_wr (int32 data) +{ +if ((data & CSR_IE) == 0) + CLR_INT (CLK); +clk_csr = (clk_csr & ~CLKCSR_RW) | (data & CLKCSR_RW); +return; +} + +void rxcs_wr (int32 data) +{ +if ((data & CSR_IE) == 0) + CLR_INT (TTI); +else if ((tti_csr & (CSR_DONE + CSR_IE)) == CSR_DONE) + SET_INT (TTI); +tti_csr = (tti_csr & ~TTICSR_RW) | (data & TTICSR_RW); +return; +} + +void txcs_wr (int32 data) +{ +if ((data & CSR_IE) == 0) + CLR_INT (TTO); +else if ((tto_csr & (CSR_DONE + CSR_IE)) == CSR_DONE) + SET_INT (TTO); +tto_csr = (tto_csr & ~TTOCSR_RW) | (data & TTOCSR_RW); +return; +} + +void txdb_wr (int32 data) +{ +tto_unit.buf = data & 0377; +tto_csr = tto_csr & ~CSR_DONE; +CLR_INT (TTO); +sim_activate (&tto_unit, tto_unit.wait); +return; +} + +/* Terminal input routines + + tti_svc process event (character ready) + tti_reset process reset +*/ + +t_stat tti_svc (UNIT *uptr) +{ +int32 c; + +sim_activate (uptr, KBD_WAIT (uptr->wait, tmr_poll)); /* continue poll */ +if ((c = sim_poll_kbd ()) < SCPE_KFLAG) /* no char or error? */ + return c; +if (c & SCPE_BREAK) { /* break? */ + if (sysd_hlt_enb ()) /* if enabled, halt */ + hlt_pin = 1; + tti_unit.buf = TTIBUF_ERR | TTIBUF_FRM | TTIBUF_RBR; + } +else tti_unit.buf = sim_tt_inpcvt (c, TT_GET_MODE (uptr->flags)); +uptr->pos = uptr->pos + 1; +tti_csr = tti_csr | CSR_DONE; +if (tti_csr & CSR_IE) + SET_INT (TTI); +return SCPE_OK; +} + +t_stat tti_reset (DEVICE *dptr) +{ +tmxr_set_console_units (&tti_unit, &tto_unit); +tti_unit.buf = 0; +tti_csr = 0; +CLR_INT (TTI); +sim_activate_abs (&tti_unit, KBD_WAIT (tti_unit.wait, tmr_poll)); +return SCPE_OK; +} + +/* Terminal output routines + + tto_svc process event (character typed) + tto_reset process reset +*/ + +t_stat tto_svc (UNIT *uptr) +{ +int32 c; +t_stat r; + +c = sim_tt_outcvt (tto_unit.buf, TT_GET_MODE (uptr->flags)); +if (c >= 0) { + if ((r = sim_putchar_s (c)) != SCPE_OK) { /* output; error? */ + sim_activate (uptr, uptr->wait); /* retry */ + return ((r == SCPE_STALL)? SCPE_OK: r); /* !stall? report */ + } + } +tto_csr = tto_csr | CSR_DONE; +if (tto_csr & CSR_IE) + SET_INT (TTO); +uptr->pos = uptr->pos + 1; +return SCPE_OK; +} + +t_stat tto_reset (DEVICE *dptr) +{ +tto_unit.buf = 0; +tto_csr = CSR_DONE; +CLR_INT (TTO); +sim_cancel (&tto_unit); /* deactivate unit */ +return SCPE_OK; +} + +/* Clock routines + + clk_svc process event (clock tick) + clk_reset process reset + todr_powerup powerup for TODR (get date from system) +*/ + +t_stat clk_svc (UNIT *uptr) +{ +int32 t; + +if (clk_csr & CSR_IE) + SET_INT (CLK); +t = sim_rtcn_calb (clk_tps, TMR_CLK); /* calibrate clock */ +sim_activate (&clk_unit, t); /* reactivate unit */ +tmr_poll = t; /* set tmr poll */ +tmxr_poll = t * TMXR_MULT; /* set mux poll */ +return SCPE_OK; +} + +/* Reset routine */ + +t_stat clk_reset (DEVICE *dptr) +{ +int32 t; + +clk_csr = 0; +CLR_INT (CLK); +t = sim_rtcn_init (clk_unit.wait, TMR_CLK); /* init timer */ +sim_activate_abs (&clk_unit, t); /* activate unit */ +tmr_poll = t; /* set tmr poll */ +tmxr_poll = t * TMXR_MULT; /* set mux poll */ +return SCPE_OK; +} + diff --git a/VAX/vax630_sysdev.c b/VAX/vax630_sysdev.c new file mode 100644 index 00000000..1aab4e67 --- /dev/null +++ b/VAX/vax630_sysdev.c @@ -0,0 +1,902 @@ +/* vax630_sysdev.c: MicroVAX II system-specific logic + + Copyright (c) 2009-2012, Matt Burke + This module incorporates code from SimH, Copyright (c) 1998-2008, Robert M Supnik + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name(s) of the author(s) shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from the author(s). + + This module contains the MicroVAX II system-specific registers and devices. + + rom bootstrap ROM (no registers) + nvr non-volatile ROM (no registers) + sysd system devices + + 08-Nov-2012 MB First version +*/ + +#include "vax_defs.h" +#include + +#ifdef DONT_USE_INTERNAL_ROM +#if defined(VAX_620) +#define BOOT_CODE_FILENAME "ka620.bin" +#else +#define BOOT_CODE_FILENAME "ka320.bin" +#endif +#else /* !DONT_USE_INTERNAL_ROM */ +#if defined(VAX_620) +#include "vax_ka620_bin.h" /* Defines BOOT_CODE_FILENAME and BOOT_CODE_ARRAY, etc */ +#else +#include "vax_ka630_bin.h" /* Defines BOOT_CODE_FILENAME and BOOT_CODE_ARRAY, etc */ +#endif +#endif /* DONT_USE_INTERNAL_ROM */ + + +#define UNIT_V_NODELAY (UNIT_V_UF + 0) /* ROM access equal to RAM access */ +#define UNIT_NODELAY (1u << UNIT_V_NODELAY) + +t_stat vax630_boot (int32 flag, char *ptr); +int32 sys_model = 0; + +/* Special boot command, overrides regular boot */ + +CTAB vax630_cmd[] = { + { "BOOT", &vax630_boot, RU_BOOT, + "bo{ot} boot simulator\n", &run_cmd_message }, + { NULL } + }; + +/* KA630 boot/diagnostic register */ + +#define BDR_DISP 0x0000000F /* LED display */ +#define BDR_V_BDC 8 /* boot/diag code */ +#define BDR_M_BDC 0x3 +#define BDR_BDC (BDR_M_BDC << BDR_V_BDC) +#define BDR_V_CPUC 11 /* cpu code */ +#define BDR_M_CPUC 0x3 +#define BDR_CPUC (BDR_M_CPUC << BDR_V_CPUC) +#define BDR_BRKENB 0x00004000 /* break enable */ +#define BDR_POK 0x00008000 /* power ok */ +#define BDR_RD (BDR_DISP | BDR_BDC | BDR_CPUC | BDR_BRKENB | BDR_POK) +#define BDR_WR (BDR_DISP) + +/* BDR boot/diagnostic codes */ + +#define BDC_NORM 0x0 /* normal startup */ +#define BDC_LNGI 0x1 /* language inquiry */ +#define BDC_TSTL 0x2 /* test loop */ +#define BDC_SKPM 0x3 /* skip mem test */ + +/* BDR CPU codes */ + +#define CPUC_ARB 0x0 /* arbiter */ +#define CPUC_AUX1 0x1 /* auxiliary 1 */ +#define CPUC_AUX2 0x2 /* auxiliary 2 */ +#define CPUC_AUX3 0x3 /* auxiliary 3 */ + +/* KA630 Memory system error register */ + +#define MSER_PE 0x00000001 /* Parity Enable */ +#define MSER_WWP 0x00000002 /* Write Wrong Parity */ +#define MSER_LEB 0x00000008 /* Lost Error Bit */ +#define MSER_DQPE 0x00000010 /* DMA Q22 Parity Err */ +#define MSER_CQPE 0x00000020 /* CPU Q22 Parity Err */ +#define MSER_CLPE 0x00000040 /* CPU Mem Parity Err */ +#define MSER_NXM 0x00000080 /* CPU NXM */ +#define MSER_MCD0 0x00000100 /* Mem Code 0 */ +#define MSER_MCD1 0x00000200 /* Mem Code 1 */ +#define MSER_MBZ 0xFFFFFC04 +#define MSER_RD (MSER_PE | MSER_WWP | MSER_LEB | \ + MSER_DQPE | MSER_CQPE | MSER_CLPE | \ + MSER_NXM | MSER_MCD0 | MSER_MCD1) +#define MSER_WR (MSER_PE | MSER_WWP) +#define MSER_RS (MSER_LEB | MSER_DQPE | MSER_CQPE | MSER_CLPE | MSER_NXM) + +/* KA630 CPU error address reg */ + +#define CEAR_LMADD 0x00007FFF /* local mem addr */ +#define CEAR_RD (CEAR_LMADD) + +/* KA630 DMA error address reg */ + +#define DEAR_LMADD 0x00007FFF /* local mem addr */ +#define DEAR_RD (DEAR_LMADD) + +extern int32 R[16]; +extern int32 STK[5]; +extern int32 PSL; +extern int32 SISR; +extern int32 SCBB; +extern int32 mapen; +extern int32 pcq[PCQ_SIZE]; +extern int32 pcq_p; +extern int32 ibcnt, ppc; +extern int32 in_ie; +extern int32 mchk_va, mchk_ref; +extern int32 fault_PC; +extern int32 int_req[IPL_HLVL]; +extern UNIT cpu_unit; +extern UNIT clk_unit; +extern jmp_buf save_env; +extern int32 p1; +extern int32 tmr_poll; + +uint32 *rom = NULL; /* boot ROM */ +uint32 *nvr = NULL; /* non-volatile mem */ +int32 conisp, conpc, conpsl; /* console reg */ +int32 ka_bdr = BDR_BRKENB; /* KA630 boot diag */ +int32 ka_mser = 0; /* KA630 mem sys err */ +int32 ka_cear = 0; /* KA630 cpu err */ +int32 ka_dear = 0; /* KA630 dma err */ +static uint32 rom_delay = 0; +t_bool rom_diag_full = 0; + +t_stat rom_ex (t_value *vptr, t_addr exta, UNIT *uptr, int32 sw); +t_stat rom_dep (t_value val, t_addr exta, UNIT *uptr, int32 sw); +t_stat rom_reset (DEVICE *dptr); +t_stat rom_set_diag (UNIT *uptr, int32 val, char *cptr, void *desc); +t_stat rom_show_diag (FILE *st, UNIT *uptr, int32 val, void *desc); +t_stat nvr_ex (t_value *vptr, t_addr exta, UNIT *uptr, int32 sw); +t_stat nvr_dep (t_value val, t_addr exta, UNIT *uptr, int32 sw); +t_stat nvr_reset (DEVICE *dptr); +t_stat nvr_attach (UNIT *uptr, char *cptr); +t_stat nvr_detach (UNIT *uptr); +t_stat sysd_reset (DEVICE *dptr); + +int32 rom_rd (int32 pa); +int32 nvr_rd (int32 pa); +void nvr_wr (int32 pa, int32 val, int32 lnt); +int32 ka_rd (int32 pa); +void ka_wr (int32 pa, int32 val, int32 lnt); +t_stat sysd_powerup (void); +int32 con_halt (int32 code, int32 cc); + +extern int32 intexc (int32 vec, int32 cc, int32 ipl, int ei); +extern int32 qbmap_rd (int32 pa); +extern void qbmap_wr (int32 pa, int32 val, int32 lnt); +extern int32 qbmem_rd (int32 pa); +extern void qbmem_wr (int32 pa, int32 val, int32 lnt); +extern int32 wtc_rd (int32 pa); +extern void wtc_wr (int32 pa, int32 val, int32 lnt); +extern void wtc_set_valid (void); +extern void wtc_set_invalid (void); +extern int32 iccs_rd (void); +extern int32 todr_rd (void); +extern int32 rxcs_rd (void); +extern int32 rxdb_rd (void); +extern int32 txcs_rd (void); +extern void iccs_wr (int32 dat); +extern void todr_wr (int32 dat); +extern void rxcs_wr (int32 dat); +extern void txcs_wr (int32 dat); +extern void txdb_wr (int32 dat); +extern void ioreset_wr (int32 dat); + +/* ROM data structures + + rom_dev ROM device descriptor + rom_unit ROM units + rom_reg ROM register list +*/ + +UNIT rom_unit = { UDATA (NULL, UNIT_FIX+UNIT_BINK, ROMSIZE) }; + +REG rom_reg[] = { + { NULL } + }; + +MTAB rom_mod[] = { + { UNIT_NODELAY, UNIT_NODELAY, "fast access", "NODELAY", NULL }, + { UNIT_NODELAY, 0, "1usec calibrated access", "DELAY", NULL }, + { MTAB_XTD|MTAB_VDV, 0, "DIAG", "DIAG={FULL|MIN}", &rom_set_diag, &rom_show_diag }, + { 0 } + }; + +DEVICE rom_dev = { + "ROM", &rom_unit, rom_reg, rom_mod, + 1, 16, ROMAWIDTH, 4, 16, 32, + &rom_ex, &rom_dep, &rom_reset, + NULL, NULL, NULL, + NULL, 0 + }; + +/* NVR data structures + + nvr_dev NVR device descriptor + nvr_unit NVR units + nvr_reg NVR register list +*/ + +UNIT nvr_unit = + { UDATA (NULL, UNIT_FIX+UNIT_BINK, NVRSIZE) }; + +REG nvr_reg[] = { + { NULL } + }; + +DEVICE nvr_dev = { + "NVR", &nvr_unit, nvr_reg, NULL, + 1, 16, NVRAWIDTH, 4, 16, 32, + &nvr_ex, &nvr_dep, &nvr_reset, + NULL, &nvr_attach, &nvr_detach, + NULL, 0 + }; + +/* SYSD data structures + + sysd_dev SYSD device descriptor + sysd_unit SYSD units + sysd_reg SYSD register list +*/ + +UNIT sysd_unit = { UDATA (NULL, 0, 0) }; + +REG sysd_reg[] = { + { HRDATAD (CONISP, conisp, 32, "console ISP") }, + { HRDATAD (CONPC, conpc, 32, "console PD") }, + { HRDATAD (CONPSL, conpsl, 32, "console PSL") }, + { HRDATAD (BDR, ka_bdr, 16, "KA630 boot diag") }, + { HRDATAD (MSER, ka_mser, 8, "KA630 mem sys err") }, + { HRDATAD (CEAR, ka_cear, 8, "KA630 cpu err") }, + { HRDATAD (DEAR, ka_dear, 8, "KA630 dma err") }, + { NULL } + }; + +DEVICE sysd_dev = { + "SYSD", &sysd_unit, sysd_reg, NULL, + 1, 16, 16, 1, 16, 8, + NULL, NULL, &sysd_reset, + NULL, NULL, NULL, + NULL, 0 + }; + +/* ROM: read only memory - stored in a buffered file + Register space access routines see ROM twice + + ROM access has been 'regulated' to about 1Mhz to avoid issues + with testing the interval timers in self-test. Specifically, + the VAX boot ROM (ka630.bin) contains code which presumes that + the VAX runs at a particular slower speed when code is running + from ROM (which is not cached). These assumptions are built + into instruction based timing loops. As the host platform gets + much faster than the original VAX, the assumptions embedded in + these code loops are no longer valid. + + Code has been added to the ROM implementation to limit CPU speed + to about 500K instructions per second. This heads off any future + issues with the embedded timing loops. +*/ + +int32 rom_swapb(int32 val) +{ +return ((val << 24) & 0xff000000) | (( val << 8) & 0xff0000) | + ((val >> 8) & 0xff00) | ((val >> 24) & 0xff); +} + +int32 rom_read_delay (int32 val) +{ +uint32 i, l = rom_delay; +int32 loopval = 0; + +if (rom_unit.flags & UNIT_NODELAY) + return val; + +/* Calibrate the loop delay factor when first used. + Do this 4 times to and use the largest value computed. */ + +if (rom_delay == 0) { + uint32 ts, te, c = 10000, samples = 0; + while (1) { + c = c * 2; + te = sim_os_msec(); + while (te == (ts = sim_os_msec ())); /* align on ms tick */ + +/* This is merely a busy wait with some "work" that won't get optimized + away by a good compiler. loopval always is zero. To avoid smart compilers, + the loopval variable is referenced in the function arguments so that the + function expression is not loop invariant. It also must be referenced + by subsequent code or to avoid the whole computation being eliminated. */ + + for (i = 0; i < c; i++) + loopval |= (loopval + ts) ^ rom_swapb (rom_swapb (loopval + ts)); + te = sim_os_msec (); + if ((te - ts) < 50) /* sample big enough? */ + continue; + if (rom_delay < (loopval + (c / (te - ts) / 1000) + 1)) + rom_delay = loopval + (c / (te - ts) / 1000) + 1; + if (++samples >= 4) + break; + c = c / 2; + } + if (rom_delay < 5) + rom_delay = 5; + } + +for (i = 0; i < l; i++) + loopval |= (loopval + val) ^ rom_swapb (rom_swapb (loopval + val)); +return val + loopval; +} + +int32 rom_rd (int32 pa) +{ +int32 rg = ((pa - ROMBASE) & ROMAMASK) >> 2; + +return rom_read_delay (rom[rg]); +} + +void rom_wr_B (int32 pa, int32 val) +{ +int32 rg = ((pa - ROMBASE) & ROMAMASK) >> 2; +int32 sc = (pa & 3) << 3; + +rom[rg] = ((val & 0xFF) << sc) | (rom[rg] & ~(0xFF << sc)); +return; +} + +/* ROM examine */ + +t_stat rom_ex (t_value *vptr, t_addr exta, UNIT *uptr, int32 sw) +{ +uint32 addr = (uint32) exta; + +if ((vptr == NULL) || (addr & 03)) + return SCPE_ARG; +if (addr >= ROMSIZE) + return SCPE_NXM; +*vptr = rom[addr >> 2]; +return SCPE_OK; +} + +/* ROM deposit */ + +t_stat rom_dep (t_value val, t_addr exta, UNIT *uptr, int32 sw) +{ +uint32 addr = (uint32) exta; + +if (addr & 03) + return SCPE_ARG; +if (addr >= ROMSIZE) + return SCPE_NXM; +rom[addr >> 2] = (uint32) val; +return SCPE_OK; +} + +/* ROM reset */ + +t_stat rom_reset (DEVICE *dptr) +{ +if (rom == NULL) + rom = (uint32 *) calloc (ROMSIZE >> 2, sizeof (uint32)); +if (rom == NULL) + return SCPE_MEM; +return SCPE_OK; +} + +/* NVR: non-volatile RAM - stored in a buffered file */ + +int32 nvr_rd (int32 pa) +{ +int32 rg = (pa - NVRBASE) >> 2; + +if (rg < 7) /* watch chip */ + return wtc_rd (pa); +else + return nvr[rg]; +} + +void nvr_wr (int32 pa, int32 val, int32 lnt) +{ +int32 rg = (pa - NVRBASE) >> 2; + +if (rg < 7) /* watch chip */ + wtc_wr (pa, val, lnt); +else { + int32 sc = (pa & 3) << 3; /* merge */ + int32 mask = 0xFF; + nvr[rg] = ((val & mask) << sc) | (nvr[rg] & ~(mask << sc)); + } +} + +/* NVR examine */ + +t_stat nvr_ex (t_value *vptr, t_addr exta, UNIT *uptr, int32 sw) +{ +uint32 addr = (uint32) exta; + +if ((vptr == NULL) || (addr & 03)) + return SCPE_ARG; +if (addr >= NVRSIZE) + return SCPE_NXM; +*vptr = nvr[addr >> 2]; +return SCPE_OK; +} + +/* NVR deposit */ + +t_stat nvr_dep (t_value val, t_addr exta, UNIT *uptr, int32 sw) +{ +uint32 addr = (uint32) exta; + +if (addr & 03) + return SCPE_ARG; +if (addr >= NVRSIZE) + return SCPE_NXM; +nvr[addr >> 2] = (uint32) val; +return SCPE_OK; +} + +/* NVR reset */ + +t_stat nvr_reset (DEVICE *dptr) +{ +if (nvr == NULL) { + nvr = (uint32 *) calloc (NVRSIZE >> 2, sizeof (uint32)); + nvr_unit.filebuf = nvr; + } +if (nvr == NULL) + return SCPE_MEM; +return SCPE_OK; +} + +/* NVR attach */ + +t_stat nvr_attach (UNIT *uptr, char *cptr) +{ +t_stat r; + +uptr->flags = uptr->flags | (UNIT_ATTABLE | UNIT_BUFABLE); +r = attach_unit (uptr, cptr); +if (r != SCPE_OK) + uptr->flags = uptr->flags & ~(UNIT_ATTABLE | UNIT_BUFABLE); +else { + uptr->hwmark = (uint32) uptr->capac; + wtc_set_valid (); + } +return r; +} + +/* NVR detach */ + +t_stat nvr_detach (UNIT *uptr) +{ +t_stat r; + +r = detach_unit (uptr); +if ((uptr->flags & UNIT_ATT) == 0) { + uptr->flags = uptr->flags & ~(UNIT_ATTABLE | UNIT_BUFABLE); + wtc_set_invalid (); + } +return r; +} + +/* Read KA630 specific IPR's */ + +int32 ReadIPR (int32 rg) +{ +int32 val; + +switch (rg) { + + case MT_ICCS: /* ICCS */ + val = iccs_rd (); + break; + + case MT_RXCS: /* RXCS */ + val = rxcs_rd (); + break; + + case MT_RXDB: /* RXDB */ + val = rxdb_rd (); + break; + + case MT_TXCS: /* TXCS */ + val = txcs_rd (); + break; + + case MT_TXDB: /* TXDB */ + val = 0; + break; + + case MT_CONISP: /* console ISP */ + val = conisp; + break; + + case MT_CONPC: /* console PC */ + val = conpc; + break; + + case MT_CONPSL: /* console PSL */ + val = conpsl; + break; + + case MT_SID: /* SID */ +#if defined(VAX_620) + val = VAX620_SID; +#else + val = VAX630_SID; +#endif + break; + + case MT_NICR: /* NICR */ + case MT_ICR: /* ICR */ + case MT_TODR: /* TODR */ + case MT_CSRS: /* CSRS */ + case MT_CSRD: /* CSRD */ + case MT_CSTS: /* CSTS */ + case MT_CSTD: /* CSTD */ + case MT_TBDR: /* TBDR */ + case MT_CADR: /* CADR */ + case MT_MCESR: /* MCESR */ + case MT_CAER: /* CAER */ + case MT_SBIFS: /* SBIFS */ + case MT_SBIS: /* SBIS */ + case MT_SBISC: /* SBISC */ + case MT_SBIMT: /* SBIMT */ + case MT_SBIER: /* SBIER */ + case MT_SBITA: /* SBITA */ + case MT_SBIQC: /* SBIQC */ + case MT_TBDATA: /* TBDATA */ + case MT_MBRK: /* MBRK */ + case MT_PME: /* PME */ + val = 0; + break; + + default: + RSVD_OPND_FAULT; + } + +return val; +} + +/* Write KA630 specific IPR's */ + +void WriteIPR (int32 rg, int32 val) +{ +switch (rg) { + + case MT_ICCS: /* ICCS */ + iccs_wr (val); + break; + + case MT_RXCS: /* RXCS */ + rxcs_wr (val); + break; + + case MT_RXDB: /* RXDB */ + break; + + case MT_TXCS: /* TXCS */ + txcs_wr (val); + break; + + case MT_TXDB: /* TXDB */ + txdb_wr (val); + break; + + case MT_IORESET: /* IORESET */ + ioreset_wr (val); + break; + + case MT_SID: + case MT_CONISP: + case MT_CONPC: + case MT_CONPSL: /* halt reg */ + RSVD_OPND_FAULT; + + case MT_NICR: /* NICR */ + case MT_ICR: /* ICR */ + case MT_TODR: /* TODR */ + case MT_CSRS: /* CSRS */ + case MT_CSRD: /* CSRD */ + case MT_CSTS: /* CSTS */ + case MT_CSTD: /* CSTD */ + case MT_TBDR: /* TBDR */ + case MT_CADR: /* CADR */ + case MT_MCESR: /* MCESR */ + case MT_CAER: /* CAER */ + case MT_SBIFS: /* SBIFS */ + case MT_SBIS: /* SBIS */ + case MT_SBISC: /* SBISC */ + case MT_SBIMT: /* SBIMT */ + case MT_SBIER: /* SBIER */ + case MT_SBITA: /* SBITA */ + case MT_SBIQC: /* SBIQC */ + case MT_TBDATA: /* TBDATA */ + case MT_MBRK: /* MBRK */ + case MT_PME: /* PME */ + break; + + default: + RSVD_OPND_FAULT; + } + +return; +} + +/* Read/write I/O register space + + These routines are the 'catch all' for address space map. Any + address that doesn't explicitly belong to memory, I/O, or ROM + is given to these routines for processing. +*/ + +struct reglink { /* register linkage */ + uint32 low; /* low addr */ + uint32 high; /* high addr */ + int32 (*read)(int32 pa); /* read routine */ + void (*write)(int32 pa, int32 val, int32 lnt); /* write routine */ + }; + +struct reglink regtable[] = { + { QBMAPBASE, QBMAPBASE+QBMAPSIZE, &qbmap_rd, &qbmap_wr }, + { ROMBASE, ROMBASE+ROMSIZE+ROMSIZE, &rom_rd, NULL }, + { NVRBASE, NVRBASE+NVRSIZE, &nvr_rd, &nvr_wr }, + { KABASE, KABASE+KASIZE, &ka_rd, &ka_wr }, +/* { QVMBASE, QVMBASE+QVMSIZE, &qv_mem_rd, &qv_mem_wr }, */ + { QBMBASE, QBMBASE+QBMSIZE, &qbmem_rd, &qbmem_wr }, + { 0, 0, NULL, NULL } + }; + +/* ReadReg - read register space + + Inputs: + pa = physical address + lnt = length (BWLQ) - ignored + Output: + longword of data +*/ + +int32 ReadReg (uint32 pa, int32 lnt) +{ +struct reglink *p; + +for (p = ®table[0]; p->low != 0; p++) { + if ((pa >= p->low) && (pa < p->high) && p->read) + return p->read (pa); + } + +MACH_CHECK (MCHK_READ); +} + +/* WriteReg - write register space + + Inputs: + pa = physical address + val = data to write, right justified in 32b longword + lnt = length (BWLQ) + Outputs: + none +*/ + +void WriteReg (uint32 pa, int32 val, int32 lnt) +{ +struct reglink *p; + +for (p = ®table[0]; p->low != 0; p++) { + if ((pa >= p->low) && (pa < p->high) && p->write) { + p->write (pa, val, lnt); + return; + } + } + +MACH_CHECK (MCHK_WRITE); +} + +/* KA630 registers */ + +int32 ka_rd (int32 pa) +{ +int32 rg = (pa - KABASE) >> 2; + +switch (rg) { + + case 0: /* BDR */ + return ka_bdr & BDR_RD; + + case 1: /* MSER */ + return ka_mser & MSER_RD; + + case 2: /* CEAR */ + return ka_cear & CEAR_RD; + + case 3: /* DEAR */ + return ka_dear & DEAR_RD; + } + +return 0; +} + +void ka_wr (int32 pa, int32 val, int32 lnt) +{ +int32 rg = (pa - KABASE) >> 2; + +switch (rg) { + + case 0: /* BDR */ + ka_bdr = (ka_bdr & ~BDR_WR) | (val & BDR_WR); + break; + + case 1: /* MSER */ + ka_mser = (ka_mser & ~MSER_WR) | (val & MSER_WR); + ka_mser = ka_mser & ~(val & MSER_RS); + break; + + case 2: /* CEAR */ + case 3: /* DEAR */ + break; + } +return; +} + +int32 sysd_hlt_enb (void) +{ +return ka_bdr & BDR_BRKENB; +} + +/* Machine check */ + +int32 machine_check (int32 p1, int32 opc, int32 cc, int32 delta) +{ +int32 st, p2, acc; + +if (in_ie) { + in_ie = 0; + return con_halt(CON_DBLMCK, cc); /* double machine check */ + } +if (p1 & 0x80) /* mref? set v/p */ + p1 = p1 + mchk_ref; +p2 = mchk_va + 4; /* save vap */ +st = 0; +if (p1 & 0x80) { /* mref? */ + cc = intexc (SCB_MCHK, cc, 0, IE_EXC); /* take normal exception */ + if (!(ka_mser & MSER_CQPE) && !(ka_mser & MSER_CLPE)) + ka_mser |= MSER_NXM; +} +else cc = intexc (SCB_MCHK, cc, 0, IE_SVE); /* take severe exception */ +acc = ACC_MASK (KERN); /* in kernel mode */ +in_ie = 1; +SP = SP - 16; /* push 4 words */ +Write (SP, 12, L_LONG, WA); /* # bytes */ +Write (SP + 4, p1, L_LONG, WA); /* mcheck type */ +Write (SP + 8, p2, L_LONG, WA); /* address */ +Write (SP + 12, st, L_LONG, WA); /* state */ +in_ie = 0; +return cc; +} + +/* Console entry */ + +int32 con_halt (int32 code, int32 cc) +{ +int32 temp; + +conisp = IS; /* save ISP */ +conpc = PC; /* save PC */ +conpsl = ((PSL | cc) & 0xFFFF00FF) | code; /* PSL, param */ +temp = (PSL >> PSL_V_CUR) & 0x7; /* get is'cur */ +if (temp > 4) /* invalid? */ + conpsl = conpsl | CON_BADPSL; +else STK[temp] = SP; /* save stack */ +if (mapen) /* mapping on? */ + conpsl = conpsl | CON_MAPON; +mapen = 0; /* turn off map */ +SP = IS; /* set SP from IS */ +PSL = PSL_IS | PSL_IPL1F; /* PSL = 41F0000 */ +JUMP (ROMBASE); /* PC = 20040000 */ +return 0; /* new cc = 0 */ +} + + +/* Special boot command - linked into SCP by initial reset + + Syntax: BOOT {CPU} + +*/ + +t_stat vax630_boot (int32 flag, char *ptr) +{ +char gbuf[CBUFSIZE]; + +get_glyph (ptr, gbuf, 0); /* get glyph */ +if (gbuf[0] && strcmp (gbuf, "CPU")) + return SCPE_ARG; /* Only can specify CPU device */ +return run_cmd (flag, "CPU"); +} + + +/* Bootstrap */ + +t_stat cpu_boot (int32 unitno, DEVICE *dptr) +{ +t_stat r; + +PC = ROMBASE; +PSL = PSL_IS | PSL_IPL1F; +conisp = 0; +conpc = 0; +conpsl = PSL_IS | PSL_IPL1F | CON_PWRUP; +if (rom == NULL) + return SCPE_IERR; +if (*rom == 0) { /* no boot? */ + r = cpu_load_bootcode (BOOT_CODE_FILENAME, BOOT_CODE_ARRAY, BOOT_CODE_SIZE, TRUE, 0); + if (r != SCPE_OK) + return r; + } +return SCPE_OK; +} + +t_stat rom_set_diag (UNIT *uptr, int32 val, char *cptr, void *desc) +{ +if (cptr != NULL) rom_diag_full = strcmp(cptr, "MIN"); +return SCPE_OK; +} + +t_stat rom_show_diag (FILE *st, UNIT *uptr, int32 val, void *desc) +{ +fprintf(st, "diag=%s", (rom_diag_full ? "full" :"min")); +return SCPE_OK; +} + +/* SYSD reset */ + +t_stat sysd_reset (DEVICE *dptr) +{ +if (sim_switches & SWMASK ('P')) sysd_powerup (); /* powerup? */ +ka_bdr = (BDR_POK | \ + ((rom_diag_full ? BDC_NORM : BDC_SKPM) << BDR_V_BDC) | \ + (CPUC_ARB << BDR_V_CPUC) | \ + BDR_BRKENB | \ + 0xF); +ka_mser = 0; +ka_cear = 0; +ka_dear = 0; + +sim_vm_cmd = vax630_cmd; + +return SCPE_OK; +} + +/* SYSD powerup */ + +t_stat sysd_powerup (void) +{ +rom_diag_full = 0; +return SCPE_OK; +} + +t_stat cpu_print_model (FILE *st) +{ +#if defined(VAX_620) +fprintf (st, "rtVAX 1000"); +#else +fprintf (st, "MicroVAX II"); +#endif +return SCPE_OK; +} + +t_stat cpu_model_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr) +{ +fprintf (st, "Initial memory size is 16MB.\n\n"); +fprintf (st, "The simulator is booted with the BOOT command:\n\n"); +fprintf (st, " sim> BOOT\n\n"); +return SCPE_OK; +} diff --git a/VAX/vax630_syslist.c b/VAX/vax630_syslist.c new file mode 100644 index 00000000..fa0e08bb --- /dev/null +++ b/VAX/vax630_syslist.c @@ -0,0 +1,135 @@ +/* vax630_syslist.c: MicroVAX II device list + + Copyright (c) 2009-2012, Matt Burke + This module incorporates code from SimH, Copyright (c) 1998-2008, Robert M Supnik + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name(s) of the author(s) shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from the author(s). + + 08-Nov-2012 MB First version +*/ + +#include "vax_defs.h" + +#if defined(VAX_620) +char sim_name[] = "VAX620"; +#else +char sim_name[] = "VAX630"; +#endif + +extern DEVICE cpu_dev; +extern DEVICE tlb_dev; +extern DEVICE rom_dev; +extern DEVICE nvr_dev; +extern DEVICE wtc_dev; +extern DEVICE sysd_dev; +extern DEVICE qba_dev; +extern DEVICE tti_dev, tto_dev; +extern DEVICE cr_dev; +extern DEVICE lpt_dev; +extern DEVICE clk_dev; +extern DEVICE rq_dev, rqb_dev, rqc_dev, rqd_dev; +extern DEVICE rl_dev; +extern DEVICE ry_dev; +extern DEVICE ts_dev; +extern DEVICE tq_dev; +extern DEVICE dz_dev; +extern DEVICE xq_dev, xqb_dev; +extern DEVICE vh_dev; + +extern void WriteB (uint32 pa, int32 val); +extern void rom_wr_B (int32 pa, int32 val); +extern UNIT cpu_unit; + +DEVICE *sim_devices[] = { + &cpu_dev, + &tlb_dev, + &rom_dev, + &nvr_dev, + &wtc_dev, + &sysd_dev, + &qba_dev, + &clk_dev, + &tti_dev, + &tto_dev, + &dz_dev, + &vh_dev, + &cr_dev, + &lpt_dev, + &rl_dev, + &rq_dev, + &rqb_dev, + &rqc_dev, + &rqd_dev, + &ry_dev, + &ts_dev, + &tq_dev, + &xq_dev, + &xqb_dev, + NULL + }; + +/* Binary loader + + The binary loader handles absolute system images, that is, system + images linked /SYSTEM. These are simply a byte stream, with no + origin or relocation information. + + -r load ROM + -n load NVR + -o for memory, specify origin +*/ + +t_stat sim_load (FILE *fileref, char *cptr, char *fnam, int flag) +{ +t_stat r; +int32 i; +uint32 origin, limit; + +if (flag) /* dump? */ + return SCPE_ARG; +if (sim_switches & SWMASK ('R')) { /* ROM? */ + origin = ROMBASE; + limit = ROMBASE + ROMSIZE; + } +else if (sim_switches & SWMASK ('N')) { /* NVR? */ + origin = NVRBASE; + limit = NVRBASE + NVRSIZE; + } +else { + origin = 0; /* memory */ + limit = (uint32) cpu_unit.capac; + if (sim_switches & SWMASK ('O')) { /* origin? */ + origin = (int32) get_uint (cptr, 16, 0xFFFFFFFF, &r); + if (r != SCPE_OK) + return SCPE_ARG; + } + } +while ((i = getc (fileref)) != EOF) { /* read byte stream */ + if (origin >= limit) /* NXM? */ + return SCPE_NXM; + if (sim_switches & SWMASK ('R')) /* ROM? */ + rom_wr_B (origin, i); /* not writeable */ + else WriteB (origin, i); /* store byte */ + origin = origin + 1; + } +return SCPE_OK; +} diff --git a/VAX/vax730_defs.h b/VAX/vax730_defs.h new file mode 100644 index 00000000..56061263 --- /dev/null +++ b/VAX/vax730_defs.h @@ -0,0 +1,364 @@ +/* vax730_defs.h: VAX 730 model-specific definitions file + + Copyright (c) 2010-2011, Matt Burke + This module incorporates code from SimH, Copyright (c) 2004-2008, Robert M Supnik + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name(s) of the author(s) shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from the author(s). + + 29-Mar-2011 MB First Version + + This file covers the VAX 11/730, the third VAX. + + System memory map + + 00 0000 - EF FFFF main memory + F0 0000 - F1 FFFF reserved + F2 0000 - F3 FFFF nexus register space + F4 0000 - FB FFFF reserved + FC 0000 - FF FFFF Unibus address space +*/ + +#ifndef FULL_VAX +#define FULL_VAX 1 +#endif + +#ifndef _VAX_730_DEFS_H_ +#define _VAX_730_DEFS_H_ 1 + +/* Microcode constructs */ + +#define VAX730_SID (3 << 24) /* system ID */ +#define VAX730_MICRO (123 << 8) /* ucode revision */ +#define CON_HLTPIN 0x0200 /* external CPU halt */ +#define CON_HLTINS 0x0600 /* HALT instruction */ +#define MCHK_NXM 0x08 /* NXM */ +#define MCHK_IIA 0x0A /* illegal i/o addr */ +#define MCHK_IUA 0x0B /* illegal unibus addr */ + +/* Interrupts */ + +#define IPL_HMAX 0x17 /* highest hwre level */ +#define IPL_HMIN 0x14 /* lowest hwre level */ +#define IPL_HLVL (IPL_HMAX - IPL_HMIN + 1) /* # hardware levels */ +#define IPL_SMAX 0xF /* highest swre level */ + +/* Nexus constants */ + +#define NEXUS_NUM 16 /* number of nexus */ +#define TR_MCTL 0 /* nexus assignments */ +#define TR_UBA 3 +#define NEXUS_HLVL (IPL_HMAX - IPL_HMIN + 1) +#define SCB_NEXUS 0x100 /* nexus intr base */ + +/* Internal I/O interrupts - relative except for clock and console */ + +#define IPL_CLKINT 0x18 /* clock IPL */ +#define IPL_TTINT 0x14 /* console IPL */ +#define IPL_CSINT 0x14 /* console storage IPL */ +#define IPL_UBA (0x15 - IPL_HMIN) + +/* Machine specific IPRs */ + +#define MT_CSRS 28 /* Console storage */ +#define MT_CSRD 29 +#define MT_CSTS 30 +#define MT_CSTD 31 +#define MT_CDR 37 /* Cache disable */ +#define MT_MCESR 38 /* MCHK err sts */ +#define MT_ACCS 40 /* FPA control */ +#define MT_ACCR 41 /* FPA maint */ +#define MT_SBIFS 48 /* SBI fault status */ +#define MT_SBIS 49 /* SBI silo */ +#define MT_SBISC 50 /* SBI silo comparator */ +#define MT_SBIMT 51 /* SBI maint */ +#define MT_SBIER 52 /* SBI error */ +#define MT_SBITA 53 /* SBI timeout addr */ +#define MT_SBIQC 54 /* SBI timeout clear */ +#define MT_UBINIT 55 /* Unibus Init */ +#define MT_MAX 63 /* last valid IPR */ + +/* Machine specific reserved operand tests */ + +/* 780 microcode patch 37 - only test LR<23:0> for appropriate length */ + +#define ML_LR_TEST(r) if ((uint32)((r) & 0xFFFFFF) > 0x200000) RSVD_OPND_FAULT + +/* 780 microcode patch 38 - only test PxBR<31>=1 and xBR<1:0> = 0 */ + +#define ML_PXBR_TEST(r) if ((((r) & 0x80000000) == 0) || \ + ((r) & 0x00000003)) RSVD_OPND_FAULT +#define ML_SBR_TEST(r) if ((r) & 0x00000003) RSVD_OPND_FAULT + +/* 780 microcode patch 78 - only test xCBB<1:0> = 0 */ + +#define ML_PA_TEST(r) if ((r) & 0x00000003) RSVD_OPND_FAULT + +#define LP_AST_TEST(r) if ((r) > AST_MAX) RSVD_OPND_FAULT +#define LP_MBZ84_TEST(r) if ((r) & 0xF8C00000) RSVD_OPND_FAULT +#define LP_MBZ92_TEST(r) if ((r) & 0x7FC00000) RSVD_OPND_FAULT + +/* Memory */ + +#define MAXMEMWIDTH 21 /* max mem, 16k chips */ +#define MAXMEMSIZE (1 << MAXMEMWIDTH) +#define MAXMEMWIDTH_X 23 /* max mem, 64k chips */ +#define MAXMEMSIZE_X (1 << MAXMEMWIDTH_X) +#define INITMEMSIZE (1 << MAXMEMWIDTH) /* initial memory size */ +#define MEMSIZE (cpu_unit.capac) +#define ADDR_IS_MEM(x) (((uint32) (x)) < MEMSIZE) +#define MEM_MODIFIERS { UNIT_MSIZE, (1u << 20), NULL, "1M", &cpu_set_size }, \ + { UNIT_MSIZE, (2u << 20), NULL, "2M", &cpu_set_size }, \ + { UNIT_MSIZE, (3u << 20), NULL, "2M", &cpu_set_size }, \ + { UNIT_MSIZE, (4u << 20), NULL, "4M", &cpu_set_size }, \ + { UNIT_MSIZE, (5u << 20), NULL, "5M", &cpu_set_size } +#define CPU_MODEL_MODIFIERS \ + { MTAB_XTD|MTAB_VDV, 0, "MODEL", NULL, \ + NULL, &cpu_show_model }, + +/* Unibus I/O registers */ + +#define UBADDRWIDTH 18 /* Unibus addr width */ +#define UBADDRSIZE (1u << UBADDRWIDTH) /* Unibus addr length */ +#define UBADDRMASK (UBADDRSIZE - 1) /* Unibus addr mask */ +#define IOPAGEAWIDTH 13 /* IO addr width */ +#define IOPAGESIZE (1u << IOPAGEAWIDTH) /* IO page length */ +#define IOPAGEMASK (IOPAGESIZE - 1) /* IO addr mask */ +#define UBAMAPWIDTH 11 /* Unibus map width */ +#define UBAMAPSIZE 0x7FC /* Unibus map length */ +#define UBADDRBASE 0xFC0000 /* Unibus addr base */ +#define IOPAGEBASE 0xFFE000 /* IO page base */ +#define UBAMAPBASE 0xF26800 /* Unibus map base */ +#define ADDR_IS_IO(x) ((((uint32) (x)) >= UBADDRBASE) && \ + (((uint32) (x)) < (UBADDRBASE + UBADDRSIZE))) +#define ADDR_IS_IOP(x) (((uint32) (x)) >= IOPAGEBASE) +#define ADDR_IS_IOM(x) ((((uint32) (x)) >= UBAMAPBASE) && \ + (((uint32) (x)) < (UBAMAPBASE + UBAMAPSIZE))) + +/* Nexus register space */ + +#define REGAWIDTH 19 /* REG addr width */ +#define REG_V_NEXUS 13 /* nexus number */ +#define REG_M_NEXUS 0xF +#define REG_V_OFS 2 /* register number */ +#define REG_M_OFS 0x7FF +#define REGSIZE (1u << REGAWIDTH) /* REG length */ +#define REGBASE 0xF00000 /* REG addr base */ +#define ADDR_IS_REG(x) ((((uint32) (x)) >= REGBASE) && \ + (((uint32) (x)) < (REGBASE + REGSIZE))) +#define NEXUS_GETNEX(x) (((x) >> REG_V_NEXUS) & REG_M_NEXUS) +#define NEXUS_GETOFS(x) (((x) >> REG_V_OFS) & REG_M_OFS) + +/* Other address spaces */ + +#define ADDR_IS_ROM(x) (0) +#define ADDR_IS_CDG(x) (0) +#define ADDR_IS_NVR(x) (0) + +/* Unibus I/O modes */ + +#define READ 0 /* PDP-11 compatibility */ +#define WRITE (L_WORD) +#define WRITEB (L_BYTE) + +/* Common CSI flags */ + +#define CSR_V_GO 0 /* go */ +#define CSR_V_IE 6 /* interrupt enable */ +#define CSR_V_DONE 7 /* done */ +#define CSR_V_BUSY 11 /* busy */ +#define CSR_V_ERR 15 /* error */ +#define CSR_GO (1u << CSR_V_GO) +#define CSR_IE (1u << CSR_V_IE) +#define CSR_DONE (1u << CSR_V_DONE) +#define CSR_BUSY (1u << CSR_V_BUSY) +#define CSR_ERR (1u << CSR_V_ERR) + +/* Timers */ + +#define TMR_CLK 0 /* 100Hz clock */ + +/* I/O system definitions */ + +#define DZ_MUXES 4 /* max # of DZV muxes */ +#define DZ_LINES 8 /* lines per DZV mux */ +#define VH_MUXES 4 /* max # of DHQ muxes */ +#define DLX_LINES 16 /* max # of KL11/DL11's */ +#define DCX_LINES 16 /* max # of DC11's */ +#define MT_MAXFR (1 << 16) /* magtape max rec */ + +#define DEV_V_UBUS (DEV_V_UF + 0) /* Unibus */ +#define DEV_V_NEXUS (DEV_V_UF + 1) /* Nexus */ +#define DEV_V_FFUF (DEV_V_UF + 2) /* first free flag */ +#define DEV_UBUS (1u << DEV_V_UBUS) +#define DEV_NEXUS (1u << DEV_V_NEXUS) +#define DEV_QBUS (0) +#define DEV_Q18 (0) + +#define UNIBUS TRUE /* Unibus only */ + +#define DEV_RDX 16 /* default device radix */ + +/* Device information block + + For Nexus devices, + ba = Nexus number + lnt = number of consecutive nexi */ + +#define VEC_DEVMAX 4 /* max device vec */ + +typedef struct { + uint32 ba; /* base addr */ + uint32 lnt; /* length */ + t_stat (*rd)(int32 *dat, int32 ad, int32 md); + t_stat (*wr)(int32 dat, int32 ad, int32 md); + int32 vnum; /* vectors: number */ + int32 vloc; /* locator */ + int32 vec; /* value */ + int32 (*ack[VEC_DEVMAX])(void); /* ack routine */ + } DIB; + +/* Unibus I/O page layout - see pdp11_ui_lib.c for address layout details */ + +#define IOBA_AUTO (0) /* Assigned by Auto Configure */ + +/* Interrupt assignments; within each level, priority is right to left */ + +#define INT_V_DZRX 0 /* BR5 */ +#define INT_V_DZTX 1 +#define INT_V_HK 2 +#define INT_V_RL 3 +#define INT_V_RB 4 +#define INT_V_RQ 5 +#define INT_V_TQ 6 +#define INT_V_TS 7 +#define INT_V_RY 8 +#define INT_V_XU 9 +#define INT_V_DMCRX 10 +#define INT_V_DMCTX 11 + +#define INT_V_LPT 0 /* BR4 */ +#define INT_V_PTR 1 +#define INT_V_PTP 2 +#define INT_V_CR 3 +#define INT_V_VHRX 4 +#define INT_V_VHTX 5 + +#define INT_DZRX (1u << INT_V_DZRX) +#define INT_DZTX (1u << INT_V_DZTX) +#define INT_HK (1u << INT_V_HK) +#define INT_RL (1u << INT_V_RL) +#define INT_RQ (1u << INT_V_RQ) +#define INT_TQ (1u << INT_V_TQ) +#define INT_TS (1u << INT_V_TS) +#define INT_RY (1u << INT_V_RY) +#define INT_XU (1u << INT_V_XU) +#define INT_RB (1u << INT_V_RB) +#define INT_LPT (1u << INT_V_LPT) +#define INT_VHRX (1u << INT_V_VHRX) +#define INT_VHTX (1u << INT_V_VHTX) +#define INT_PTR (1u << INT_V_PTR) +#define INT_PTP (1u << INT_V_PTP) +#define INT_CR (1u << INT_V_CR) +#define INT_DMCRX (1u << INT_V_DMCRX) +#define INT_DMCTX (1u << INT_V_DMCTX) + +#define IPL_DZRX (0x15 - IPL_HMIN) +#define IPL_DZTX (0x15 - IPL_HMIN) +#define IPL_HK (0x15 - IPL_HMIN) +#define IPL_RL (0x15 - IPL_HMIN) +#define IPL_RQ (0x15 - IPL_HMIN) +#define IPL_TQ (0x15 - IPL_HMIN) +#define IPL_TS (0x15 - IPL_HMIN) +#define IPL_RY (0x15 - IPL_HMIN) +#define IPL_XU (0x15 - IPL_HMIN) +#define IPL_RB (0x15 - IPL_HMIN) +#define IPL_LPT (0x14 - IPL_HMIN) +#define IPL_PTR (0x14 - IPL_HMIN) +#define IPL_PTP (0x14 - IPL_HMIN) +#define IPL_CR (0x14 - IPL_HMIN) +#define IPL_VHRX (0x14 - IPL_HMIN) +#define IPL_VHTX (0x14 - IPL_HMIN) +#define IPL_DMCRX (0x15 - IPL_HMIN) +#define IPL_DMCTX (0x15 - IPL_HMIN) + +/* Device vectors */ + +#define VEC_AUTO (0) /* Assigned by Auto Configure */ +#define VEC_FLOAT (0) /* Assigned by Auto Configure */ + +#define VEC_QBUS 0 +#define VEC_Q 0x200 + +/* Interrupt macros */ + +#define IVCL(dv) ((IPL_##dv * 32) + INT_V_##dv) +#define NVCL(dv) ((IPL_##dv * 32) + TR_##dv) +#define IREQ(dv) int_req[IPL_##dv] +#define SET_INT(dv) int_req[IPL_##dv] = int_req[IPL_##dv] | (INT_##dv) +#define CLR_INT(dv) int_req[IPL_##dv] = int_req[IPL_##dv] & ~(INT_##dv) +#define IORETURN(f,v) ((f)? (v): SCPE_OK) /* cond error return */ + +/* Logging */ + +#define LOG_CPU_I 0x1 /* intexc */ +#define LOG_CPU_R 0x2 /* REI */ +#define LOG_CPU_P 0x4 /* context */ + +/* Boot definitions */ + +#define BOOT_HK 1 /* device codes */ +#define BOOT_RL 2 /* for VMB */ +#define BOOT_RB 3 +#define BOOT_UDA 17 +#define BOOT_TK 18 +#define BOOT_TD 64 + +/* Function prototypes for virtual memory interface */ + +int32 Read (uint32 va, int32 lnt, int32 acc); +void Write (uint32 va, int32 val, int32 lnt, int32 acc); + +/* Function prototypes for physical memory interface (inlined) */ + +SIM_INLINE int32 ReadB (uint32 pa); +SIM_INLINE int32 ReadW (uint32 pa); +SIM_INLINE int32 ReadL (uint32 pa); +SIM_INLINE int32 ReadLP (uint32 pa); +SIM_INLINE void WriteB (uint32 pa, int32 val); +SIM_INLINE void WriteW (uint32 pa, int32 val); +SIM_INLINE void WriteL (uint32 pa, int32 val); +void WriteLP (uint32 pa, int32 val); + +/* Function prototypes for I/O */ + +int32 Map_ReadB (uint32 ba, int32 bc, uint8 *buf); +int32 Map_ReadW (uint32 ba, int32 bc, uint16 *buf); +int32 Map_WriteB (uint32 ba, int32 bc, uint8 *buf); +int32 Map_WriteW (uint32 ba, int32 bc, uint16 *buf); + +t_stat show_nexus (FILE *st, UNIT *uptr, int32 val, void *desc); + +void sbi_set_errcnf (void); + +#include "pdp11_io_lib.h" + +#endif diff --git a/VAX/vax730_mem.c b/VAX/vax730_mem.c new file mode 100644 index 00000000..62e0cf1b --- /dev/null +++ b/VAX/vax730_mem.c @@ -0,0 +1,195 @@ +/* vax730_mem.c: VAX 11/730 memory adapter + + Copyright (c) 2010-2011, Matt Burke + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name of the author shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from the author. + + This module contains the VAX 11/730 memory controller registers. + + mctl MS730 memory adapter + + 29-Mar-2011 MB First Version + +*/ + +#include "vax_defs.h" + +/* Memory adapter register 0 */ + +#define MCSR0_OF 0x00 +#define MCSR0_ES 0x0000007F /* Error syndrome */ +#define MCSR0_V_FPN 9 +#define MCSR0_M_FPN 0x7FFF +#define MCSR0_FPN (MCSR0_M_FPN << MCSR0_V_FPN) /* Failing page number */ + +/* Memory adapter register 1 */ + +#define MCSR1_OF 0x01 +#define MCSR1_RW 0x3E000000 +#define MCSR1_MBZ 0x01FFFF80 + +/* Memory adapter register 2 */ + +#define MCSR2_OF 0x02 +#define MCSR2_M_MAP 0xFFFF; +#define MCSR2_V_CS 24 +#define MCSR2_CS (1u << MCSR2_V_CS) +#define MCSR2_MBZ 0xFEFF0000 + +/* Debug switches */ + +#define MCTL_DEB_RRD 0x01 /* reg reads */ +#define MCTL_DEB_RWR 0x02 /* reg writes */ + +#define MEM_SIZE_16K (1u << 17) /* Board size (16k chips) */ +#define MEM_SIZE_64K (1u << 19) /* Board size (64k chips) */ + +#define MEM_BOARD_MASK(x,y) ((1u << (uint32)(x/y)) - 1) + +extern UNIT cpu_unit; + +uint32 mcsr0 = 0; +uint32 mcsr1 = 0; +uint32 mcsr2 = 0; + +t_stat mctl_reset (DEVICE *dptr); +t_stat mctl_rdreg (int32 *val, int32 pa, int32 mode); +t_stat mctl_wrreg (int32 val, int32 pa, int32 mode); + +/* MCTLx data structures + + mctlx_dev MCTLx device descriptor + mctlx_unit MCTLx unit + mctlx_reg MCTLx register list +*/ + +DIB mctl_dib = { TR_MCTL, 0, &mctl_rdreg, &mctl_wrreg, 0 }; + +UNIT mctl_unit = { UDATA (NULL, 0, 0) }; + +REG mctl_reg[] = { + { HRDATAD (CSR0, mcsr0, 32, "ECC syndrome bits") }, + { HRDATAD (CSR1, mcsr1, 32, "CPU error control/check bits") }, + { HRDATAD (CSR2, mcsr2, 32, "Unibus error control/check bits") }, + { NULL } + }; + +MTAB mctl_mod[] = { + { MTAB_XTD|MTAB_VDV, TR_MCTL, "NEXUS", NULL, + NULL, &show_nexus }, + { 0 } + }; + +DEBTAB mctl_deb[] = { + { "REGREAD", MCTL_DEB_RRD }, + { "REGWRITE", MCTL_DEB_RWR }, + { NULL, 0 } + }; + +DEVICE mctl_dev = { + "MCTL", &mctl_unit, mctl_reg, mctl_mod, + 1, 16, 16, 1, 16, 8, + NULL, NULL, &mctl_reset, + NULL, NULL, NULL, + &mctl_dib, DEV_NEXUS | DEV_DEBUG, 0, + mctl_deb, 0, 0 + }; + +/* Memory controller register read */ + +t_stat mctl_rdreg (int32 *val, int32 pa, int32 lnt) +{ +int32 ofs; +ofs = NEXUS_GETOFS (pa); /* get offset */ + +switch (ofs) { /* case on offset */ + + case MCSR0_OF: /* CSR0 */ + *val = mcsr0; + break; + + case MCSR1_OF: /* CSR1 */ + *val = mcsr1 & ~MCSR1_MBZ; + break; + + case MCSR2_OF: /* CSR2 */ + *val = mcsr2 & ~MCSR2_MBZ; + break; + + default: + return SCPE_NXM; + } + +if (DEBUG_PRI (mctl_dev, MCTL_DEB_RRD)) + fprintf (sim_deb, ">>MCTL: reg %d read, value = %X\n", ofs, *val); +return SCPE_OK; +} + +/* Memory controller register write */ + +t_stat mctl_wrreg (int32 val, int32 pa, int32 lnt) +{ +int32 ofs; + +ofs = NEXUS_GETOFS (pa); /* get offset */ + +switch (ofs) { /* case on offset */ + + case MCSR0_OF: /* CSR0 */ + break; + + case MCSR1_OF: /* CSR1 */ + mcsr1 = val & MCSR1_RW; + break; + + case MCSR2_OF: /* CSR2 */ + break; + + default: + return SCPE_NXM; + } + +if (DEBUG_PRI (mctl_dev, MCTL_DEB_RWR)) + fprintf (sim_deb, ">>MCTL: reg %d write, value = %X\n", ofs, val); +return SCPE_OK; +} + +/* Used by CPU and loader */ + +void rom_wr_B (int32 pa, int32 val) +{ +return; +} + +/* MEMCTL reset */ + +t_stat mctl_reset (DEVICE *dptr) +{ +mcsr0 = 0; +mcsr1 = 0; +mcsr2 = 0; +if (MEMSIZE > MAXMEMSIZE) /* More than 2MB? */ + mcsr2 = mcsr2 | MEM_BOARD_MASK(MEMSIZE, MEM_SIZE_64K) | MCSR2_CS; /* Use 64k chips */ +else + mcsr2 = mcsr2 | MEM_BOARD_MASK(MEMSIZE, MEM_SIZE_16K); /* Use 16k chips */ +return SCPE_OK; +} diff --git a/VAX/vax730_rb.c b/VAX/vax730_rb.c new file mode 100644 index 00000000..2400d640 --- /dev/null +++ b/VAX/vax730_rb.c @@ -0,0 +1,672 @@ +/* vax730_rb.c: RB730 disk simulator + + Copyright (c) 2010-2011, Matt Burke + This module incorporates code from SimH, Copyright (c) 1993-2008, Robert M Supnik + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name(s) of the author(s) shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from the author(s). + + rb RB730 - RB02/RB80 disk controller + + 29-Mar-2011 MB First Version + + The RB730 is a four drive disk subsystem consisting of up to three RL02 + drives (known as RB02) and one optional RA80 drive (known as RB80). + + Unlike the RL11 controller seeks are not done relative to the current + disk address. + + The RB730 has two regiter address spaces: + + - One dummy 16-bit register in unibus I/O space to allow the controller to + be detected by SYSGEN autoconfigure (and others). + - Eight 32-bit registers in the unibus controller space for the actual + device control. +*/ + +#include "vax_defs.h" + +/* Constants */ + +#define RB02_NUMWD 128 /* words/sector */ +#define RB02_NUMSC 40 /* sectors/track */ +#define RB02_NUMSF 2 /* tracks/cylinder */ +#define RB02_NUMCY 512 /* cylinders/drive */ +#define RB02_SIZE (RB02_NUMCY * RB02_NUMSF * \ + RB02_NUMSC * RB02_NUMWD) /* words/drive */ +#define RB80_NUMWD 256 /* words/sector */ +#define RB80_NUMSC 32 /* sectors/track */ +#define RB80_NUMSF 14 /* tracks/cylinder */ +#define RB80_NUMCY 559 /* cylinders/drive */ +#define RB80_SIZE (RB80_NUMCY * RB80_NUMSF * \ + RB80_NUMSC * RB80_NUMWD) /* words/drive */ + +#define RB_NUMWD(u) ((u->flags & UNIT_RB80) ? RB80_NUMWD : RB02_NUMWD) +#define RB_NUMSC(u) ((u->flags & UNIT_RB80) ? RB80_NUMSC : RB02_NUMSC) +#define RB_NUMSF(u) ((u->flags & UNIT_RB80) ? RB80_NUMSF : RB02_NUMSF) +#define RB_NUMCY(u) ((u->flags & UNIT_RB80) ? RB80_NUMCY : RB02_NUMCY) +#define RB_SIZE(u) ((u->flags & UNIT_RB80) ? RB80_SIZE : RB02_SIZE) + +#define RB_NUMDR 4 /* drives/controller */ +#define RB_MAXFR (1 << 16) /* max transfer */ + +/* Flags in the unit flags word */ + +#define UNIT_V_WLK (UNIT_V_UF + 0) /* hwre write lock */ +#define UNIT_V_RB80 (UNIT_V_UF + 1) /* RB02 vs RB80 */ +#define UNIT_V_DUMMY (UNIT_V_UF + 2) /* dummy flag */ +#define UNIT_DUMMY (1 << UNIT_V_DUMMY) +#define UNIT_WLK (1u << UNIT_V_WLK) +#define UNIT_RB80 (1u << UNIT_V_RB80) +#define UNIT_WPRT (UNIT_WLK | UNIT_RO) /* write protected */ + +/* Parameters in the unit descriptor */ + +#define TRK u3 /* current track */ +#define STAT u4 /* status */ +#define SIP u5 /* seek in progress */ + +/* RBDS, NI = not implemented, * = kept in STAT, ^ = kept in TRK */ + +#define RB02DS_LOAD 0 /* no cartridge */ +#define RB02DS_LOCK 5 /* lock on */ +#define RB02DS_BHO 0000010 /* brushes home NI */ +#define RB02DS_HDO 0000020 /* heads out NI */ +#define RB02DS_CVO 0000040 /* cover open NI */ +#define RB02DS_HD 0000100 /* head select ^ */ +#define RB02DS_DSE 0000400 /* drv sel err NI */ +#define RB02DS_VCK 0001000 /* vol check * */ +#define RB02DS_WGE 0002000 /* wr gate err * */ +#define RB02DS_SPE 0004000 /* spin err * */ +#define RB02DS_STO 0010000 /* seek time out NI */ +#define RB02DS_WLK 0020000 /* wr locked */ +#define RB02DS_HCE 0040000 /* hd curr err NI */ +#define RB02DS_WDE 0100000 /* wr data err NI */ +#define RB02DS_ATT (RB02DS_HDO+RB02DS_BHO+RB02DS_LOCK) /* att status */ +#define RB02DS_UNATT (RB02DS_CVO+RB02DS_LOAD) /* unatt status */ +#define RB02DS_ERR (RB02DS_WDE+RB02DS_HCE+RB02DS_STO+RB02DS_SPE+RB02DS_WGE+ \ + RB02DS_VCK+RB02DS_DSE) /* errors bits */ + +#define RB80DS_SCNT 0x0000000F +#define RB80DS_FLT 0x00000100 +#define RB80DS_PLV 0x00000200 +#define RB80DS_SKE 0x00000400 +#define RB80DS_OCY 0x00000800 +#define RB80DS_RDY 0x00001000 +#define RB80DS_WLK 0x00002000 + +/* RBCS */ + +#define RBCS_DRDY 0x00000001 /* drive ready */ +#define RBCS_M_FUNC 0x7 /* function */ +#define RBCS_NOP 0 +#define RBCS_WCHK 1 +#define RBCS_GSTA 2 +#define RBCS_SEEK 3 +#define RBCS_RHDR 4 +#define RBCS_WRITE 5 +#define RBCS_READ 6 +#define RBCS_RNOHDR 7 +#define RBCS_V_FUNC 1 +#define RBCS_M_DRIVE 0x3 +#define RBCS_V_DRIVE 8 +#define RBCS_INCMP 0x00000400 /* incomplete */ +#define RBCS_CRC 0x00000800 /* CRC error */ +#define RBCS_DLT 0x00001000 /* data late */ +#define RBCS_HDE 0x00001400 /* header error */ +#define RBCS_NXM 0x00002000 /* non-exist memory */ +#define RBCS_DRE 0x00004000 /* drive error */ +#define RBCS_ERR 0x00008000 /* error summary */ +#define RBCS_ALLERR (RBCS_ERR+RBCS_DRE+RBCS_NXM+RBCS_CRC+RBCS_INCMP) +#define RBCS_M_ATN 0xF +#define RBCS_V_ATN 16 +#define RBCS_ATN (RBCS_M_ATN << RBCS_V_ATN) +#define RBCS_M_ECC 0x2 +#define RBCS_V_ECC 20 +#define RBCS_SSI 0x00400000 +#define RBCS_SSE 0x00800000 +#define RBCS_IRQ 0x01000000 +#define RBCS_MTN 0x02000000 +#define RBCS_R80 0x04000000 +#define RBCS_ASI 0x08000000 +#define RBCS_TOI 0x10000000 +#define RBCS_FMT 0x20000000 +#define RBCS_MATN 0x80000000 +//#define RBCS_RW 0001716 /* read/write */ +#define RBCS_RW ((RBCS_M_FUNC << RBCS_V_FUNC) + \ + CSR_IE + CSR_DONE + \ + (RBCS_M_DRIVE << RBCS_V_DRIVE) + \ + RBCS_SSI + RBCS_MTN + RBCS_ASI + \ + RBCS_TOI + RBCS_FMT + RBCS_MATN) +#define RBCS_C0 RBCS_SSE +#define RBCS_C1 (rbcs & RBCS_MATN) ? RBCS_IRQ : \ + ((RBCS_M_ATN << RBCS_V_ATN) + RBCS_IRQ) +#define GET_FUNC(x) (((x) >> RBCS_V_FUNC) & RBCS_M_FUNC) +#define GET_DRIVE(x) (((x) >> RBCS_V_DRIVE) & RBCS_M_DRIVE) + +/* RBBA */ + +#define RBBA_RW 0x0003FFFF + +/* RBBC */ + +/* RBMP */ + +#define RBMP_MRK 0x00000001 +#define RBMP_GST 0x00000002 +#define RBMP_RST 0x00000008 + +/* RBDA */ + +#define RBDA_V_SECT 0 /* sector */ +#define RBDA_M_SECT 0xFF +#define RBDA_V_TRACK 8 /* track */ +#define RBDA_M_TRACK 0xFF +#define RBDA_V_CYL 16 /* cylinder */ +#define RBDA_M_CYL 0xFFFF +#define RBDA_TRACK (RBDA_M_TRACK << RBDA_V_TRACK) +#define RBDA_CYL (RBDA_M_CYL << RBDA_V_CYL) +#define GET_SECT(x) (((x) >> RBDA_V_SECT) & RBDA_M_SECT) +#define GET_CYL(x) (((x) >> RBDA_V_CYL) & RBDA_M_CYL) +#define GET_TRACK(x) (((x) >> RBDA_V_TRACK) & RBDA_M_TRACK) +//#define GET_DA(x) ((GET_CYL(x) * RB02_NUMSF * GET_TRACK (x) * RB02_NUMSC) + GET_SECT (x)) +#define GET_DA(x,u) ((GET_TRACK (x) * RB_NUMCY(u) * RB_NUMSC(u) * RB_NUMWD(u)) + \ + (GET_CYL(x) * RB_NUMSC(u) * RB_NUMWD(u)) + \ + (GET_SECT (x) * RB_NUMWD(u))) + +#define DBG_REG 0x0001 /* registers */ +#define DBG_CMD 0x0002 /* commands */ +#define DBG_RD 0x0004 /* disk reads */ +#define DBG_WR 0x0008 /* disk writes */ + +extern int32 int_req[IPL_HLVL]; + +uint16 *rbxb = NULL; /* xfer buffer */ +int32 rbcs = 0; /* control/status */ +int32 rbba = 0; /* memory address */ +int32 rbbc = 0; /* bytes count */ +int32 rbda = 0; /* disk addr */ +int32 rbmp = 0, rbmp1 = 0, rbmp2 = 0; /* mp register queue */ +int32 rb_swait = 150; /* seek wait */ +int32 rb_mwait = 300; /* seek wait */ +int32 rb_cwait = 50; /* seek wait */ + +t_stat rb_rd16 (int32 *data, int32 PA, int32 access); +t_stat rb_wr16 (int32 data, int32 PA, int32 access); +t_stat rb_rd32 (int32 *data, int32 PA, int32 access); +t_stat rb_wr32 (int32 data, int32 PA, int32 access); +t_stat rb_svc (UNIT *uptr); +t_stat rb_reset (DEVICE *dptr); +void rb_set_done (int32 error); +t_stat rb_attach (UNIT *uptr, char *cptr); +t_stat rb_set_size (UNIT *uptr, int32 val, char *cptr, void *desc); +t_stat rb_set_bad (UNIT *uptr, int32 val, char *cptr, void *desc); + +/* RB730 data structures + + rb_dev RB device descriptor + rb_unit RB unit list + rb_reg RB register list + rb_mod RB modifier list +*/ + +#define IOLN_RB 002 + +DIB rb_dib = { + IOBA_AUTO, IOLN_RB, &rb_rd16, &rb_wr16, + 1, IVCL (RB), VEC_AUTO, { NULL } }; + +UNIT rb_unit[] = { + { UDATA (&rb_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+ + UNIT_ROABLE+UNIT_RB80, RB80_SIZE) }, + { UDATA (&rb_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+ + UNIT_ROABLE, RB02_SIZE) }, + { UDATA (&rb_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+ + UNIT_ROABLE, RB02_SIZE) }, + { UDATA (&rb_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+ + UNIT_ROABLE, RB02_SIZE) }, + }; + +REG rb_reg[] = { + { NULL } + }; + +DEBTAB rb_debug[] = { + {"REG", DBG_REG}, + {"CMD", DBG_CMD}, + {"RD", DBG_RD}, + {"WR", DBG_WR}, + {0} +}; + +MTAB rb_mod[] = { + { UNIT_WLK, 0, "write enabled", "WRITEENABLED", NULL }, + { UNIT_WLK, UNIT_WLK, "write locked", "LOCKED", NULL }, + { UNIT_DUMMY, 0, NULL, "BADBLOCK", &rb_set_bad }, + { (UNIT_RB80+UNIT_ATT), UNIT_ATT, "RB02", NULL, NULL }, + { (UNIT_RB80+UNIT_ATT), (UNIT_RB80+UNIT_ATT), "RB80", NULL, NULL }, + { (UNIT_RB80+UNIT_ATT), 0, "RB02", NULL, NULL }, + { (UNIT_RB80+UNIT_ATT), UNIT_RB80, "RB80", NULL, NULL }, + { (UNIT_RB80), 0, NULL, "RB02", &rb_set_size }, + { (UNIT_RB80), UNIT_RB80, NULL, "RB80", &rb_set_size }, + { MTAB_XTD|MTAB_VDV, 010, "ADDRESS", "ADDRESS", + &set_addr, &show_addr, NULL }, + { MTAB_XTD|MTAB_VDV, 0, "VECTOR", "VECTOR", + &set_vec, &show_vec, NULL }, + { 0 } + }; + +DEVICE rb_dev = { + "RB", rb_unit, rb_reg, rb_mod, + RB_NUMDR, DEV_RDX, T_ADDR_W, 1, DEV_RDX, 16, + NULL, NULL, &rb_reset, + NULL, &rb_attach, NULL, + &rb_dib, DEV_DISABLE | DEV_UBUS | DEV_DEBUG, 0, + rb_debug, 0, 0 + }; + +/* I/O dispatch routines + + 17775606 RBDCS dummy csr to trigger sysgen +*/ + +t_stat rb_rd16 (int32 *data, int32 PA, int32 access) +{ +*data = 0; +return SCPE_OK; +} + +t_stat rb_wr16 (int32 data, int32 PA, int32 access) +{ +return SCPE_OK; +} + +t_stat rb_rd32 (int32 *data, int32 PA, int32 access) +{ +UNIT *uptr; + +switch ((PA >> 2) & 07) { + + case 0: /* RBCS */ + if (rbcs & RBCS_ALLERR) + rbcs = rbcs | RBCS_ERR; + uptr = rb_dev.units + GET_DRIVE (rbcs); + if ((sim_is_active (uptr)) || (uptr->flags & UNIT_DIS)) + rbcs = rbcs & ~RBCS_DRDY; + else rbcs = rbcs | RBCS_DRDY; /* see if ready */ + if (uptr->flags & UNIT_RB80) + rbcs = rbcs | RBCS_R80; + else rbcs = rbcs & ~RBCS_R80; + *data = rbcs; + break; + + case 1: /* RBBA */ + *data = rbba & RBBA_RW; + break; + + case 2: /* RBBC */ + *data = rbbc; + break; + + case 3: /* RBDA */ + *data = rbda; + break; + + case 4: /* RBMP */ + *data = rbmp; + rbmp = rbmp1; /* ripple data */ + rbmp1 = rbmp2; + break; + + case 5: /* ECCPS */ + case 6: /* ECCPT */ + case 7: /* INIT */ + *data = 0; + break; + } + +sim_debug(DBG_REG, &rb_dev, "reg %d read, value = %X\n", (PA >> 2) & 07, *data); + +return SCPE_OK; +} + +t_stat rb_wr32 (int32 data, int32 PA, int32 access) +{ +UNIT *uptr; + +sim_debug(DBG_REG, &rb_dev, "reg %d write, value = %X\n", (PA >> 2) & 07, data); + +switch ((PA >> 2) & 07) { + + case 0: /* CSR */ + if (rbcs & RBCS_ALLERR) + rbcs = rbcs | RBCS_ERR; + uptr = rb_dev.units + GET_DRIVE (data); + if ((sim_is_active (uptr)) || (uptr->flags & UNIT_DIS)) + rbcs = rbcs & ~RBCS_DRDY; + else rbcs = rbcs | RBCS_DRDY; /* see if ready */ + if (uptr->flags & UNIT_RB80) + rbcs = rbcs | RBCS_R80; + else rbcs = rbcs & ~RBCS_R80; + + rbcs = rbcs & ~(data & RBCS_C1); + rbcs = rbcs & ~(~data & RBCS_C0); + rbcs = (rbcs & ~RBCS_RW) | (data & RBCS_RW); + if (data & RBCS_ATN) CLR_INT (RB); + + if ((data & CSR_DONE) || (sim_is_active (uptr))) /* ready set? */ + return SCPE_OK; + + CLR_INT (RB); /* clear interrupt */ + rbcs = rbcs & ~RBCS_ALLERR; /* clear errors */ + uptr->SIP = 0; + if (uptr->flags & UNIT_DIS) { + rbcs = rbcs | (1u << (RBCS_V_ATN + GET_DRIVE (rbcs))); + rb_set_done (RBCS_ERR | RBCS_INCMP); + break; + } + switch (GET_FUNC (rbcs)) { /* case on RBCS<3:1> */ + case RBCS_NOP: /* nop */ + rb_set_done (0); + break; + case RBCS_SEEK: /* seek */ + sim_activate (uptr, rb_swait); + break; + default: /* data transfer */ + sim_activate (uptr, rb_cwait); /* activate unit */ + break; + } /* end switch func */ + break; + + case 1: /* BAR */ + rbba = data & RBBA_RW; + break; + + case 2: /* BCR */ + rbbc = data; + break; + + case 3: /* DAR */ + rbda = data; + break; + + case 4: /* MPR */ + rbmp = rbmp1 = rbmp2 = data; + break; + + case 5: /* ECCPS */ + case 6: /* ECCPT */ + break; + + case 7: /* INIT */ + return rb_reset(&rb_dev); + } + +return SCPE_OK; +} + +/* Service unit timeout + + If seek in progress, complete seek command + Else complete data transfer command + + The unit control block contains the function and cylinder for + the current command. +*/ + +t_stat rb_svc (UNIT *uptr) +{ +int32 curr, newc, swait; +int32 err, wc, maxwc, t; +int32 i, func, da, awc; +uint32 ma; +uint16 comp; + +func = GET_FUNC (rbcs); /* get function */ +if (func == RBCS_GSTA) { /* get status */ + sim_debug(DBG_CMD, &rb_dev, "Get Status\n"); + if (uptr->flags & UNIT_RB80) { + rbmp = uptr->STAT | RB80DS_PLV; + if (uptr->flags & UNIT_ATT) + rbmp = rbmp | RB80DS_RDY | RB80DS_OCY; + if (uptr->flags & UNIT_WPRT) + rbmp = rbmp | RB80DS_WLK; + } + else { + if (rbmp & RBMP_RST) + uptr->STAT = uptr->STAT & ~RB02DS_ERR; + rbmp = uptr->STAT | (uptr->flags & UNIT_ATT)? RB02DS_ATT: RB02DS_UNATT; + if (uptr->flags & UNIT_WPRT) + rbmp = rbmp | RB02DS_WLK; + } + rbmp2 = rbmp1 = rbmp; + rb_set_done (0); /* done */ + return SCPE_OK; + } + +if (func == RBCS_RHDR) { /* read header? */ + sim_debug(DBG_CMD, &rb_dev, "Read Header\n"); + rbmp = (uptr->TRK & RBDA_TRACK) | GET_SECT (rbda); + rbmp1 = rbmp2 = 0; + rbcs = rbcs | (1 << (RBCS_V_ATN + GET_DRIVE (rbcs))); + rb_set_done (0); /* done */ + return SCPE_OK; + } + +if ((uptr->flags & UNIT_ATT) == 0) { /* attached? */ + rbcs = rbcs & ~RBCS_DRDY; /* clear drive ready */ + rbcs = rbcs | (1u << (RBCS_V_ATN + GET_DRIVE (rbcs))); + if ((uptr->flags & UNIT_RB80) == 0) + uptr->STAT = uptr->STAT | RB02DS_SPE; /* spin error */ + rb_set_done (RBCS_ERR | RBCS_INCMP); /* flag error */ + //return IORETURN (rl_stopioe, SCPE_UNATT); + return SCPE_OK; + } + +if ((func == RBCS_WRITE) && (uptr->flags & UNIT_WPRT)) { + if ((uptr->flags & UNIT_RB80) == 0) + uptr->STAT = uptr->STAT | RB02DS_WGE; /* write and locked */ + rb_set_done (RBCS_ERR | RBCS_DRE); + return SCPE_OK; + } + +if (func == RBCS_SEEK) { /* seek? */ + if (uptr->SIP == 0) { + sim_debug(DBG_CMD, &rb_dev, "Seek, CYL=%d, TRK=%d, SECT=%d\n", GET_CYL(rbda), GET_TRACK(rbda), GET_SECT(rbda)); + uptr->SIP = 1; + if ((uint32)rbda == 0xFFFFFFFF) swait = rb_swait; + else { + curr = GET_CYL (uptr->TRK); /* current cylinder */ + newc = GET_CYL (rbda); /* offset */ + uptr->TRK = (newc << RBDA_V_CYL); /* put on track */ + swait = rb_cwait * abs (newc - curr); + if (swait < rb_mwait) swait = rb_mwait; + } + sim_activate (uptr, swait); + rbcs = rbcs | (1 << (RBCS_V_ATN + GET_DRIVE (rbcs))); + rbcs = rbcs | RBCS_IRQ; + rb_set_done(0); + return SCPE_OK; + } + else { + sim_debug(DBG_CMD, &rb_dev, "Seek done\n"); + rbcs = rbcs | (1 << (RBCS_V_ATN + GET_DRIVE (rbcs))); + uptr->SIP = 0; + rb_set_done (0); /* done */ + return SCPE_OK; + } + } + +if (((func != RBCS_RNOHDR) && ((uptr->TRK & RBDA_CYL) != (rbda & RBDA_CYL))) + || (GET_SECT (rbda) >= RB_NUMSC(uptr))) { /* bad cyl or sector? */ + sim_debug(DBG_CMD, &rb_dev, "Invalid cylinder or sector, CYL=%d, TRK=%d, SECT=%d\n", GET_CYL(rbda), GET_TRACK(rbda), GET_SECT(rbda)); + rb_set_done (RBCS_ERR | RBCS_HDE | RBCS_INCMP); /* wrong cylinder? */ + return SCPE_OK; + } + +ma = rbba; /* get mem addr */ +da = GET_DA (rbda, uptr); /* get disk addr */ +wc = ((rbbc * -1) >> 1); /* get true wc */ + +maxwc = (RB_NUMSC(uptr) - GET_SECT (rbda)) * RB_NUMWD(uptr); /* max transfer */ +if (wc > maxwc) /* track overrun? */ + wc = maxwc; +err = sim_fseek (uptr->fileref, da * sizeof (int16), SEEK_SET); + +if ((func >= RBCS_READ) && (err == 0)) { /* read (no hdr)? */ + sim_debug(DBG_CMD, &rb_dev, "Read, CYL=%d, TRK=%d, SECT=%d, WC=%d, DA=%d\n", GET_CYL(rbda), GET_TRACK(rbda), GET_SECT(rbda), wc, da); + i = sim_fread (rbxb, sizeof (uint16), wc, uptr->fileref); + err = ferror (uptr->fileref); + for ( ; i < wc; i++) /* fill buffer */ + rbxb[i] = 0; + if ((t = Map_WriteW (ma, wc << 1, rbxb))) { /* store buffer */ + rbcs = rbcs | RBCS_ERR | RBCS_NXM; /* nxm */ + wc = wc - t; /* adjust wc */ + } + } /* end read */ + +if ((func == RBCS_WRITE) && (err == 0)) { /* write? */ + sim_debug(DBG_CMD, &rb_dev, "Write, CYL=%d, TRK=%d, SECT=%d, WC=%d, DA=%d\n", GET_CYL(rbda), GET_TRACK(rbda), GET_SECT(rbda), wc, da); + if ((t = Map_ReadW (ma, wc << 1, rbxb))) { /* fetch buffer */ + rbcs = rbcs | RBCS_ERR | RBCS_NXM; /* nxm */ + wc = wc - t; /* adj xfer lnt */ + } + if (wc) { /* any xfer? */ + awc = (wc + (RB_NUMWD(uptr) - 1)) & ~(RB_NUMWD(uptr) - 1); /* clr to */ + for (i = wc; i < awc; i++) /* end of blk */ + rbxb[i] = 0; + sim_fwrite (rbxb, sizeof (uint16), awc, uptr->fileref); + err = ferror (uptr->fileref); + } + } /* end write */ + +if ((func == RBCS_WCHK) && (err == 0)) { /* write check? */ + sim_debug(DBG_CMD, &rb_dev, "WCheck, CYL=%d, TRK=%d, SECT=%d, WC=%d, DA=%d\n", GET_CYL(rbda), GET_TRACK(rbda), GET_SECT(rbda), wc, da); + i = sim_fread (rbxb, sizeof (uint16), wc, uptr->fileref); + err = ferror (uptr->fileref); + for ( ; i < wc; i++) /* fill buffer */ + rbxb[i] = 0; + awc = wc; /* save wc */ + for (wc = 0; (err == 0) && (wc < awc); wc++) { /* loop thru buf */ + if (Map_ReadW (ma + (wc << 1), 2, &comp)) { /* mem wd */ + rbcs = rbcs | RBCS_ERR | RBCS_NXM; /* nxm */ + break; + } + if (comp != rbxb[wc]) /* check to buf */ + rbcs = rbcs | RBCS_ERR | RBCS_CRC; + } /* end for */ + } /* end wcheck */ + +rbbc = (rbbc + (wc << 1)); /* final byte count */ +if (rbbc != 0) { /* completed? */ + rbcs = rbcs | RBCS_ERR | RBCS_INCMP; + } +ma = ma + (wc << 1); /* final byte addr */ +rbba = ma & RBBA_RW; +rbda = rbda + ((wc + (RB_NUMWD(uptr) - 1)) / RB_NUMWD(uptr)); +rb_set_done (0); + +if (err != 0) { /* error? */ + perror ("RB I/O error"); + clearerr (uptr->fileref); + return SCPE_IOERR; + } +return SCPE_OK; +} + +/* Set done and possibly errors */ + +void rb_set_done (int32 status) +{ +rbcs = rbcs | status | CSR_DONE; /* set done */ +rbcs = rbcs | RBCS_IRQ; +if (rbcs & CSR_IE) { + sim_debug(DBG_CMD, &rb_dev, "Done, INT\n"); + SET_INT (RB); + } +else { + sim_debug(DBG_CMD, &rb_dev, "Done, no INT\n"); + CLR_INT (RB); + } +return; +} + +/* Device reset */ + +t_stat rb_reset (DEVICE *dptr) +{ +int32 i; +UNIT *uptr; + +rbcs = CSR_DONE; +rbda = rbba = rbbc = rbmp = 0; +CLR_INT (RB); +for (i = 0; i < RB_NUMDR; i++) { + uptr = rb_dev.units + i; + sim_cancel (uptr); + uptr->STAT = 0; + uptr->SIP = 0; + } +if (rbxb == NULL) + rbxb = (uint16 *) calloc (RB_MAXFR, sizeof (uint16)); +if (rbxb == NULL) + return SCPE_MEM; +return SCPE_OK; +} + +/* Attach routine */ + +t_stat rb_attach (UNIT *uptr, char *cptr) +{ +uint32 p; +t_stat r; + +uptr->capac = (uptr->flags & UNIT_RB80)? RB80_SIZE: RB02_SIZE; +r = attach_unit (uptr, cptr); /* attach unit */ +if (r != SCPE_OK) /* error? */ + return r; +uptr->TRK = 0; /* cylinder 0 */ +if ((uptr->flags & UNIT_RB80) == 0) + uptr->STAT = RB02DS_VCK; /* new volume */ +if ((p = sim_fsize (uptr->fileref)) == 0) { /* new disk image? */ + if (uptr->flags & UNIT_RO) /* if ro, done */ + return SCPE_OK; + return pdp11_bad_block (uptr, RB_NUMSC(uptr), RB_NUMWD(uptr)); + } +return SCPE_OK; +} + +/* Set size routine */ + +t_stat rb_set_size (UNIT *uptr, int32 val, char *cptr, void *desc) +{ +if (uptr->flags & UNIT_ATT) + return SCPE_ALATT; +uptr->capac = (val & UNIT_RB80)? RB80_SIZE: RB02_SIZE; +return SCPE_OK; +} + +/* Set bad block routine */ + +t_stat rb_set_bad (UNIT *uptr, int32 val, char *cptr, void *desc) +{ +return pdp11_bad_block (uptr, RB_NUMSC(uptr), RB_NUMWD(uptr)); +} diff --git a/VAX/vax730_stddev.c b/VAX/vax730_stddev.c new file mode 100644 index 00000000..bf2ee949 --- /dev/null +++ b/VAX/vax730_stddev.c @@ -0,0 +1,1194 @@ +/* vax730_stddev.c: VAX 11/730 standard I/O devices + + Copyright (c) 2010-2011, Matt Burke + This module incorporates code from SimH, Copyright (c) 1998-2008, Robert M Supnik + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name(s) of the author(s) shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from the author(s). + + tti console input + tto console output + td console TU58 + todr TODR clock + tmr interval timer + + 28-Sep-11 MP Generalized setting TODR for all OSes. + Unbound the TODR value from the 100hz clock tick + interrupt. TODR now behaves like the original + battery backed-up clock and runs with the wall + clock, not the simulated instruction clock. + Two operational modes are available: + - Default VMS mode, which is similar to the previous + behavior in that without initializing the TODR it + would default to the value VMS would set it to if + VMS knew the correct time. This would be correct + almost all the time unless a VMS disk hadn't been + booted from for more than a year. This mode + produces strange time results for non VMS OSes on + each system boot. + - OS Agnostic mode. This mode behaves precisely like + the VAX780 TODR and works correctly for all OSes. + This mode is enabled by attaching the TODR to a + battery backup state file for the TOY clock + (i.e. sim> attach TODR TOY_CLOCK). When operating + in OS Agnostic mode, the TODR will initially start + counting from 0 and be adjusted differently when an + OS specifically writes to the TODR. VMS will prompt + to set the time on each boot unless the SYSGEN + parameter TIMEPROMPTWAIT is set to 0. + 29-Mar-2011 MB First Version +*/ + +#include "vax_defs.h" +#include "sim_tmxr.h" + +/* Terminal definitions */ + +#define RXCS_RD (CSR_DONE + CSR_IE) /* terminal input */ +#define RXCS_WR (CSR_IE) +#define RXDB_V_SEL 8 /* unit select */ +#define RXDB_M_SEL 0xF +#define RXDB_TERM 0x0 /* console terminal */ +#define RXDB_MISC 0xF /* console misc */ +#define RXDB_ERR 0x8000 /* error */ +#define TXCS_RD (CSR_DONE + CSR_IE) /* terminal output */ +#define TXCS_WR (CSR_IE) +#define TXDB_V_SEL 8 /* unit select */ +#define TXDB_M_SEL 0xF +#define TXDB_TERM 0x0 /* console terminal */ +#define TXDB_MISC 0xF /* console misc */ +#define MISC_MASK 0xFF /* console data mask */ +#define MISC_SWDN 0x1 /* software done */ +#define MISC_BOOT 0x2 /* reboot */ +#define MISC_CLWS 0x3 /* clear warm start */ +#define MISC_CLCS 0x4 /* clear cold start */ +#define TXDB_SEL (TXDB_M_SEL << TXDB_V_SEL) /* non-terminal */ +#define TXDB_GETSEL(x) (((x) >> TXDB_V_SEL) & TXDB_M_SEL) +#define CSTS_BRK 0x1 +#define CSTS_RD (CSR_DONE + CSR_IE + CSTS_BRK) /* terminal output */ +#define CSTS_WR (CSR_IE + CSTS_BRK) + +/* Clock definitions */ + +#define TMR_CSR_ERR 0x80000000 /* error W1C */ +#define TMR_CSR_DON 0x00000080 /* done W1C */ +#define TMR_CSR_IE 0x00000040 /* int enb RW */ +#define TMR_CSR_SGL 0x00000020 /* single WO */ +#define TMR_CSR_XFR 0x00000010 /* xfer WO */ +#define TMR_CSR_RUN 0x00000001 /* run RW */ +#define TMR_CSR_RD (TMR_CSR_W1C | TMR_CSR_WR) +#define TMR_CSR_W1C (TMR_CSR_ERR | TMR_CSR_DON) +#define TMR_CSR_WR (TMR_CSR_IE | TMR_CSR_RUN) +#define TMR_INC 10000 /* usec/interval */ +#define CLK_DELAY 5000 /* 100 Hz */ +#define TMXR_MULT 1 /* 100 Hz */ + +/* TU58 definitions */ + +#define UNIT_V_WLK (UNIT_V_UF) /* write locked */ +#define UNIT_WLK (1u << UNIT_V_UF) +#define UNIT_WPRT (UNIT_WLK | UNIT_RO) /* write protect */ + +#define TD_NUMBLK 512 /* blocks/tape */ +#define TD_NUMBY 512 /* bytes/block */ +#define TD_SIZE (TD_NUMBLK * TD_NUMBY) /* bytes/tape */ + +#define TD_OPDAT 001 /* Data */ +#define TD_OPCMD 002 /* Command */ +#define TD_OPINI 004 /* INIT */ +#define TD_OPBOO 010 /* Bootstrap */ +#define TD_OPCNT 020 /* Continue */ +#define TD_OPXOF 023 /* XOFF */ + +#define TD_CMDNOP 0000 /* NOP */ +#define TD_CMDINI 0001 /* INIT */ +#define TD_CMDRD 0002 /* Read */ +#define TD_CMDWR 0003 /* Write */ +#define TD_CMDPOS 0005 /* Position */ +#define TD_CMDDIA 0007 /* Diagnose */ +#define TD_CMDGST 0010 /* Get Status */ +#define TD_CMDSST 0011 /* Set Status */ +#define TD_CMDMRSP 0012 /* MRSP Request */ +#define TD_CMDEND 0100 /* END */ + +#define TD_STSOK 0000 /* Normal success */ +#define TD_STSRTY 0001 /* Success with retries */ +#define TD_STSFAIL 0377 /* Failed selftest */ +#define TD_STSPO 0376 /* Partial operation (end of medium) */ +#define TD_STSBUN 0370 /* Bad unit number */ +#define TD_STSNC 0367 /* No cartridge */ +#define TD_STSWP 0365 /* Write protected */ +#define TD_STSDCE 0357 /* Data check error */ +#define TD_STSSE 0340 /* Seek error (block not found) */ +#define TD_STSMS 0337 /* Motor stopped */ +#define TD_STSBOP 0320 /* Bad opcode */ +#define TD_STSBBN 0311 /* Bad block number (>511) */ + +#define TD_GETOPC 0 /* get opcode state */ +#define TD_GETLEN 1 /* get length state */ +#define TD_GETDATA 2 /* get data state */ + +#define TD_IDLE 0 /* idle state */ +#define TD_READ 1 /* read */ +#define TD_READ1 2 /* fill buffer */ +#define TD_READ2 3 /* empty buffer */ +#define TD_WRITE 4 /* write */ +#define TD_WRITE1 5 /* write */ +#define TD_WRITE2 6 /* write */ +#define TD_END 7 /* empty buffer */ +#define TD_END1 8 /* empty buffer */ +#define TD_INIT 9 /* empty buffer */ + +int32 tti_csr = 0; /* control/status */ +int32 tti_buf = 0; /* buffer */ +int32 tti_int = 0; /* interrupt */ +int32 tto_csr = 0; /* control/status */ +int32 tto_buf = 0; /* buffer */ +int32 tto_int = 0; /* interrupt */ + +int32 csi_csr = 0; /* control/status */ +int32 csi_buf = 0; /* buffer */ +int32 csi_int = 0; /* interrupt */ +int32 cso_csr = 0; /* control/status */ +int32 cso_buf = 0; /* buffer */ +int32 cso_int = 0; /* interrupt */ +int32 cso_state = 0; /* state */ + +int32 tmr_iccs = 0; /* interval timer csr */ +uint32 tmr_icr = 0; /* curr interval */ +uint32 tmr_nicr = 0; /* next interval */ +uint32 tmr_inc = 0; /* timer increment */ +int32 tmr_sav = 0; /* timer save */ +int32 tmr_int = 0; /* interrupt */ +int32 tmr_use_100hz = 1; /* use 100Hz for timer */ +int32 clk_tps = 100; /* ticks/second */ +int32 tmxr_poll = CLK_DELAY * TMXR_MULT; /* term mux poll */ +int32 tmr_poll = CLK_DELAY; /* pgm timer poll */ +int32 todr_reg = 0; /* TODR register */ +struct todr_battery_info { + uint32 toy_gmtbase; /* GMT base of set value */ + uint32 toy_gmtbasemsec; /* The milliseconds of the set value */ + }; +typedef struct todr_battery_info TOY; + +int32 td_swait = 100; /* seek, per block */ +int32 td_cwait = 150; /* command time */ +int32 td_xwait = 180; /* tr set time */ +int32 td_iwait = 180; /* init time */ +uint8 td_ibuf[TD_NUMBY] = { 0 }; /* input buffer */ +int32 td_ibptr = 0; /* input buffer pointer */ +int32 td_ilen = 0; /* input length */ +uint8 td_obuf[TD_NUMBY] = { 0 }; /* output buffer */ +int32 td_obptr = 0; /* output buffer pointer */ +int32 td_olen = 0; /* output length */ +int32 td_block = 0; /* current block number */ +int32 td_txsize = 0; /* remaining transfer size */ +int32 td_offset = 0; /* offset into current transfer */ +int32 td_state = TD_IDLE; +int32 td_unitno = 0; /* active unit number */ +int32 td_ecode = 0; /* end packet success code */ + +extern jmp_buf save_env; + +t_stat tti_svc (UNIT *uptr); +t_stat tto_svc (UNIT *uptr); +t_stat clk_svc (UNIT *uptr); +t_stat tmr_svc (UNIT *uptr); +t_stat tti_reset (DEVICE *dptr); +t_stat tto_reset (DEVICE *dptr); +t_stat clk_reset (DEVICE *dptr); +t_stat clk_attach (UNIT *uptr, char *cptr); +t_stat clk_detach (UNIT *uptr); +t_stat tmr_reset (DEVICE *dptr); +t_stat td_svc (UNIT *uptr); +t_stat td_reset (DEVICE *dptr); +int32 icr_rd (t_bool interp); +void tmr_incr (uint32 inc); +void tmr_sched (void); +t_stat todr_resync (void); +t_stat txdb_misc_wr (int32 data); +void td_process_packet(); +t_bool td_test_xfr (UNIT *uptr, int32 state); + +/* TTI data structures + + tti_dev TTI device descriptor + tti_unit TTI unit descriptor + tti_reg TTI register list +*/ + +UNIT tti_unit = { UDATA (&tti_svc, TT_MODE_8B, 0), 0 }; + +REG tti_reg[] = { + { HRDATAD (RXDB, tti_buf, 16, "last data item processed") }, + { HRDATAD (RXCS, tti_csr, 16, "control/status register") }, + { FLDATAD (INT, tti_int, 0, "interrupt pending flag") }, + { FLDATAD (DONE, tti_csr, CSR_V_DONE, "device done flag (CSR<7>)") }, + { FLDATAD (IE, tti_csr, CSR_V_IE, "interrupt enable flag (CSR<6>)") }, + { DRDATAD (POS, tti_unit.pos, T_ADDR_W, "number of characters input"), PV_LEFT }, + { DRDATAD (TIME, tti_unit.wait, 24, "input polling interval"), PV_LEFT }, + { NULL } + }; + +MTAB tti_mod[] = { + { TT_MODE, TT_MODE_7B, "7b", "7B", NULL }, + { TT_MODE, TT_MODE_8B, "8b", "8B", NULL }, + { 0 } + }; + +DEVICE tti_dev = { + "TTI", &tti_unit, tti_reg, tti_mod, + 1, 10, 31, 1, 16, 8, + NULL, NULL, &tti_reset, + NULL, NULL, NULL, + NULL, 0 + }; + +/* TTO data structures + + tto_dev TTO device descriptor + tto_unit TTO unit descriptor + tto_reg TTO register list +*/ + +UNIT tto_unit = { UDATA (&tto_svc, TT_MODE_8B, 0), SERIAL_OUT_WAIT }; + +REG tto_reg[] = { + { HRDATAD (TXDB, tto_buf, 16, "last data item processed") }, + { HRDATAD (TXCS, tto_csr, 16, "control/status register") }, + { FLDATAD (INT, tto_int, 0, "interrupt pending flag") }, + { FLDATAD (DONE, tto_csr, CSR_V_DONE, "device done flag (CSR<7>)") }, + { FLDATAD (IE, tto_csr, CSR_V_IE, "interrupt enable flag (CSR<6>)") }, + { DRDATAD (POS, tto_unit.pos, T_ADDR_W, "number of characters output"), PV_LEFT }, + { DRDATAD (TIME, tto_unit.wait, 24, "time from I/O initiation to interrupt"), PV_LEFT + REG_NZ }, + { NULL } + }; + +MTAB tto_mod[] = { + { TT_MODE, TT_MODE_7B, "7b", "7B", NULL }, + { TT_MODE, TT_MODE_8B, "8b", "8B", NULL }, + { TT_MODE, TT_MODE_7P, "7p", "7P", NULL }, + { 0 } + }; + +DEVICE tto_dev = { + "TTO", &tto_unit, tto_reg, tto_mod, + 1, 10, 31, 1, 16, 8, + NULL, NULL, &tto_reset, + NULL, NULL, NULL, + NULL, 0 + }; + +/* TODR and TMR data structures */ + +UNIT clk_unit = { UDATA (&clk_svc, UNIT_IDLE+UNIT_FIX, sizeof(TOY)), CLK_DELAY };/* 100Hz */ + +REG clk_reg[] = { + { DRDATAD (TODR, todr_reg, 32, "time-of-day register"), PV_LEFT }, + { DRDATAD (TIME, clk_unit.wait, 24, "initial poll interval"), REG_NZ + PV_LEFT }, + { DRDATAD (POLL, tmr_poll, 24, "calibrated poll interval"), REG_NZ + PV_LEFT + REG_HRO }, + { DRDATAD (TPS, clk_tps, 8, "ticks per second (100)"), REG_NZ + PV_LEFT }, +#if defined (SIM_ASYNCH_IO) + { DRDATAD (ASYNCH, sim_asynch_enabled, 1, "asynch I/O enabled flag"), PV_LEFT }, + { DRDATAD (LATENCY, sim_asynch_latency, 32, "desired asynch interrupt latency"), PV_LEFT }, + { DRDATAD (INST_LATENCY, sim_asynch_inst_latency, 32, "calibrated instruction latency"), PV_LEFT }, +#endif + { NULL } + }; + +DEVICE clk_dev = { + "TODR", &clk_unit, clk_reg, NULL, + 1, 0, 8, 4, 0, 32, + NULL, NULL, &clk_reset, + NULL, &clk_attach, &clk_detach, + NULL, 0 + }; + +UNIT tmr_unit = { UDATA (&tmr_svc, 0, 0) }; /* timer */ + +REG tmr_reg[] = { + { HRDATAD (ICCS, tmr_iccs, 32, "interval timer control and status") }, + { HRDATAD (ICR, tmr_icr, 32, "interval count register") }, + { HRDATAD (NICR, tmr_nicr, 32, "next interval count register") }, + { FLDATAD (INT, tmr_int, 0, "interrupt request") }, + { HRDATA (INCR, tmr_inc, 32), REG_HIDDEN }, + { HRDATA (SAVE, tmr_sav, 32), REG_HIDDEN }, + { FLDATA (USE100HZ, tmr_use_100hz, 0), REG_HIDDEN }, + { NULL } + }; + +DEVICE tmr_dev = { + "TMR", &tmr_unit, tmr_reg, NULL, + 1, 0, 0, 0, 0, 0, + NULL, NULL, &tmr_reset, + NULL, NULL, NULL, + NULL, 0 + }; + +/* TU58 data structures + + td_dev RX device descriptor + td_unit RX unit list + td_reg RX register list + td_mod RX modifier list +*/ + +UNIT td_unit[] = { + { UDATA (&td_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_BUFABLE+UNIT_MUSTBUF, TD_SIZE) }, + { UDATA (&td_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_BUFABLE+UNIT_MUSTBUF, TD_SIZE) } + }; + +REG td_reg[] = { + { HRDATAD (ECODE, td_ecode, 8, "end packet success code") }, + { HRDATAD (BLK, td_block, 8, "current block number") }, + { DRDATAD (PSTATE, td_state, 4, "state"), REG_RO }, + { DRDATAD (BPTR, td_obptr, 7, "output buffer pointer") }, + { DRDATAD (CTIME, td_cwait, 24, "command time"), PV_LEFT }, + { DRDATAD (STIME, td_swait, 24, "seek, per block"), PV_LEFT }, + { DRDATAD (XTIME, td_xwait, 24, "tr set time"), PV_LEFT }, + { NULL } + }; + +MTAB td_mod[] = { + { UNIT_WLK, 0, "write enabled", "WRITEENABLED", NULL }, + { UNIT_WLK, UNIT_WLK, "write locked", "LOCKED", NULL }, + { 0 } + }; + +DEVICE td_dev = { + "TD", td_unit, td_reg, td_mod, + 2, DEV_RDX, 20, 1, DEV_RDX, 8, + NULL, NULL, &td_reset, + NULL, NULL, NULL, + NULL, 0 + }; + +/* Console storage MxPR routines + + csrs_rd/wr input control/status + csrd_rd input buffer + csts_rd/wr output control/status + cstd_wr output buffer +*/ + +int32 csrs_rd (void) +{ +return (csi_csr & RXCS_RD); +} + +void csrs_wr (int32 data) +{ +if ((data & CSR_IE) == 0) + cso_int = 0; +else if ((csi_csr & (CSR_DONE + CSR_IE)) == CSR_DONE) + csi_int = 1; +csi_csr = (csi_csr & ~RXCS_WR) | (data & RXCS_WR); +return; +} + +int32 csrd_rd (void) +{ +int32 t = csi_buf; /* char + error */ + +csi_csr = csi_csr & ~CSR_DONE; /* clr done */ +csi_buf = csi_buf & BMASK; /* clr errors */ +csi_int = 0; +return t; +} + +int32 csts_rd (void) +{ +return (cso_csr & TXCS_RD); +} + +void csts_wr (int32 data) +{ +if ((cso_csr & CSTS_BRK) && !(data & CSTS_BRK)) { + td_ibptr = 0; + td_ibuf[td_ibptr++] = TD_OPINI; + td_process_packet(); /* check packet */ + } +if ((data & CSR_IE) == 0) + cso_int = 0; +else if ((cso_csr & (CSR_DONE + CSR_IE)) == CSR_DONE) + cso_int = 1; +cso_csr = (cso_csr & ~CSTS_WR) | (data & CSTS_WR); +return; +} + +void cstd_wr (int32 data) +{ +cso_buf = data & WMASK; /* save data */ +cso_csr = cso_csr & ~CSR_DONE; /* clear flag */ +cso_int = 0; /* clear int */ + +switch (cso_state) { + + case TD_GETOPC: + td_ibptr = 0; + td_ibuf[td_ibptr++] = cso_buf; + td_process_packet(); /* check packet */ + break; + + case TD_GETLEN: + td_ibuf[td_ibptr++] = cso_buf; + td_ilen = cso_buf + 4; /* packet length + header + checksum */ + cso_state = TD_GETDATA; + break; + + case TD_GETDATA: + td_ibuf[td_ibptr++] = cso_buf; + if (td_ibptr >= td_ilen) { + cso_state = TD_GETOPC; + td_process_packet(); + } + break; + } + +cso_csr = cso_csr | CSR_DONE; /* set input flag */ +if (cso_csr & CSR_IE) + cso_int = 1; +return; +} + +void td_process_packet() +{ +int32 opcode = td_ibuf[0]; + +switch (opcode) { + + case TD_OPDAT: + if (td_state != TD_WRITE1) { /* expecting data? */ + printf("TU58 protocol error 1\n"); + return; + } + if (td_ibptr < 2) { /* whole packet read? */ + cso_state = TD_GETLEN; /* get rest of packet */ + return; + } + td_state = TD_WRITE2; + sim_activate (&td_dev.units[td_unitno], td_cwait); /* sched command */ + break; + + case TD_OPCMD: + if (td_state != TD_IDLE) { /* expecting command? */ + printf("TU58 protocol error 2\n"); + return; + } + if (td_ibptr < 2) { /* whole packet read? */ + cso_state = TD_GETLEN; /* get rest of packet */ + return; + } + switch (td_ibuf[2]) { + case TD_CMDNOP: /* NOP */ + case TD_CMDGST: /* Get status */ + case TD_CMDSST: /* Set status */ + td_unitno = td_ibuf[4]; + td_state = TD_END; /* All treated as NOP */ + td_ecode = TD_STSOK; + td_offset = 0; + sim_activate (&td_dev.units[td_unitno], td_cwait); /* sched command */ + break; + + case TD_CMDINI: + printf("Warning: TU58 command 'INIT' not implemented\n"); + break; + + case TD_CMDRD: + td_unitno = td_ibuf[4]; + td_block = ((td_ibuf[11] << 8) | td_ibuf[10]); + td_txsize = ((td_ibuf[9] << 8) | td_ibuf[8]); + td_state = TD_READ; + td_offset = 0; + sim_activate (&td_dev.units[td_unitno], td_cwait); /* sched command */ + break; + + case TD_CMDWR: + td_unitno = td_ibuf[4]; + td_block = ((td_ibuf[11] << 8) | td_ibuf[10]); + td_txsize = ((td_ibuf[9] << 8) | td_ibuf[8]); + td_state = TD_WRITE; + td_offset = 0; + sim_activate (&td_dev.units[td_unitno], td_cwait); /* sched command */ + break; + + case TD_CMDPOS: + printf("Warning: TU58 command 'Position' not implemented\n"); + break; + + case TD_CMDDIA: + printf("Warning: TU58 command 'Diagnose' not implemented\n"); + break; + + case TD_CMDMRSP: /* MRSP supported? */ + csi_buf = TD_OPDAT; /* TP_OPCMD = yes, TP_OPDAT = no */ + csi_csr = csi_csr | CSR_DONE; /* set input flag */ + if (csi_csr & CSR_IE) + csi_int = 1; + break; + } + break; + + case TD_OPINI: + sim_cancel (&td_dev.units[0]); + sim_cancel (&td_dev.units[1]); + td_ibptr = 0; + td_obptr = 0; + td_olen = 0; + td_offset = 0; + td_txsize = 0; + cso_state = TD_GETOPC; + td_state = TD_INIT; + sim_activate (&td_dev.units[0], td_iwait); /* sched command */ + break; + + case TD_OPBOO: + if (td_state != TD_IDLE) { + printf("TU58 protocol error 3\n"); + return; + } + if (td_ibptr < 2) { /* whole packet read? */ + td_ilen = 2; + cso_state = TD_GETDATA; /* get rest of packet */ + return; + } + td_unitno = td_ibuf[1]; + td_block = 0; + td_txsize = 512; + td_state = TD_READ; + td_offset = 0; + sim_activate (&td_dev.units[td_unitno], td_cwait); /* sched command */ + break; + + case TD_OPCNT: + break; + + default: + //printf("TU58: Unknown opcode %d\n", opcode); + break; + } +} + +/* Terminal MxPR routines + + rxcs_rd/wr input control/status + rxdb_rd input buffer + txcs_rd/wr output control/status + txdb_wr output buffer +*/ + +int32 rxcs_rd (void) +{ +return (tti_csr & RXCS_RD); +} + +void rxcs_wr (int32 data) +{ +if ((data & CSR_IE) == 0) + tti_int = 0; +else if ((tti_csr & (CSR_DONE + CSR_IE)) == CSR_DONE) + tti_int = 1; +tti_csr = (tti_csr & ~RXCS_WR) | (data & RXCS_WR); +return; +} + +int32 rxdb_rd (void) +{ +int32 t = tti_buf; /* char + error */ + +tti_csr = tti_csr & ~CSR_DONE; /* clr done */ +tti_buf = tti_buf & BMASK; /* clr errors */ +tti_int = 0; +return t; +} + +int32 txcs_rd (void) +{ +return (tto_csr & TXCS_RD); +} + +void txcs_wr (int32 data) +{ +if ((data & CSR_IE) == 0) + tto_int = 0; +else if ((tto_csr & (CSR_DONE + CSR_IE)) == CSR_DONE) + tto_int = 1; +tto_csr = (tto_csr & ~TXCS_WR) | (data & TXCS_WR); +return; +} + +void txdb_wr (int32 data) +{ +tto_buf = data & WMASK; /* save data */ +tto_csr = tto_csr & ~CSR_DONE; /* clear flag */ +tto_int = 0; /* clear int */ +if (tto_buf & TXDB_SEL) /* console mailbox? */ + txdb_misc_wr (tto_buf); +sim_activate (&tto_unit, tto_unit.wait); /* no, console */ +return; +} + +/* Terminal input service (poll for character) */ + +t_stat tti_svc (UNIT *uptr) +{ +int32 c; + +sim_activate (uptr, KBD_WAIT (uptr->wait, tmr_poll)); /* continue poll */ +if ((c = sim_poll_kbd ()) < SCPE_KFLAG) /* no char or error? */ + return c; +if (c & SCPE_BREAK) /* break? */ + tti_buf = RXDB_ERR; +else tti_buf = sim_tt_inpcvt (c, TT_GET_MODE (uptr->flags)); +uptr->pos = uptr->pos + 1; +tti_csr = tti_csr | CSR_DONE; +if (tti_csr & CSR_IE) + tti_int = 1; +return SCPE_OK; +} + +/* Terminal input reset */ + +t_stat tti_reset (DEVICE *dptr) +{ +tmxr_set_console_units (&tti_unit, &tto_unit); +tti_buf = 0; +tti_csr = 0; +tti_int = 0; +sim_activate_abs (&tti_unit, KBD_WAIT (tti_unit.wait, tmr_poll)); +return SCPE_OK; +} + +/* Terminal output service (output character) */ + +t_stat tto_svc (UNIT *uptr) +{ +int32 c; +t_stat r; + +if ((tto_buf & TXDB_SEL) == 0) { /* for console? */ + c = sim_tt_outcvt (tto_buf, TT_GET_MODE (uptr->flags)); + if (c >= 0) { + if ((r = sim_putchar_s (c)) != SCPE_OK) { /* output; error? */ + sim_activate (uptr, uptr->wait); /* retry */ + return ((r == SCPE_STALL)? SCPE_OK: r); /* !stall? report */ + } + } + uptr->pos = uptr->pos + 1; + } +tto_csr = tto_csr | CSR_DONE; +if (tto_csr & CSR_IE) + tto_int = 1; +return SCPE_OK; +} + +/* Terminal output reset */ + +t_stat tto_reset (DEVICE *dptr) +{ +tto_buf = 0; +tto_csr = CSR_DONE; +tto_int = 0; +sim_cancel (&tto_unit); /* deactivate unit */ +return SCPE_OK; +} + +/* Programmable timer + + The architected VAX timer, which increments at 1Mhz, cannot be + accurately simulated due to the overhead that would be required + for 1M clock events per second. Instead, a hidden calibrated + 100Hz timer is run (because that's what VMS expects), and a + hack is used for the interval timer. + + When the timer is started, the timer interval is inspected. + + if the interval is >= 10msec, then the 100Hz timer drives the + next interval + if the interval is < 10mec, then count instructions + + If the interval register is read, then its value between events + is interpolated using the current instruction count versus the + count when the most recent event started, the result is scaled + to the calibrated system clock, unless the interval being timed + is less than a calibrated system clock tick (or the calibrated + clock is running very slowly) at which time the result will be + the elapsed instruction count. +*/ + +int32 iccs_rd (void) +{ +return tmr_iccs & TMR_CSR_RD; +} + +void iccs_wr (int32 val) +{ +if ((val & TMR_CSR_RUN) == 0) { /* clearing run? */ + sim_cancel (&tmr_unit); /* cancel timer */ + tmr_use_100hz = 0; + if (tmr_iccs & TMR_CSR_RUN) /* run 1 -> 0? */ + tmr_icr = icr_rd (TRUE); /* update itr */ + } +tmr_iccs = tmr_iccs & ~(val & TMR_CSR_W1C); /* W1C csr */ +tmr_iccs = (tmr_iccs & ~TMR_CSR_WR) | /* new r/w */ + (val & TMR_CSR_WR); +if (val & TMR_CSR_XFR) tmr_icr = tmr_nicr; /* xfr set? */ +if (val & TMR_CSR_RUN) { /* run? */ + if (val & TMR_CSR_XFR) /* new tir? */ + sim_cancel (&tmr_unit); /* stop prev */ + if (!sim_is_active (&tmr_unit)) /* not running? */ + tmr_sched (); /* activate */ + } +else if (val & TMR_CSR_SGL) { /* single step? */ + tmr_incr (1); /* incr tmr */ + if (tmr_icr == 0) /* if ovflo, */ + tmr_icr = tmr_nicr; /* reload tir */ + } +if ((tmr_iccs & (TMR_CSR_DON | TMR_CSR_IE)) != /* update int */ + (TMR_CSR_DON | TMR_CSR_IE)) + tmr_int = 0; +return; +} + +int32 icr_rd (t_bool interp) +{ +uint32 delta; + +if (interp || (tmr_iccs & TMR_CSR_RUN)) { /* interp, running? */ + delta = sim_grtime () - tmr_sav; /* delta inst */ + if (tmr_use_100hz && (tmr_poll > TMR_INC)) /* scale large int */ + delta = (uint32) ((((double) delta) * TMR_INC) / tmr_poll); + if (delta >= tmr_inc) + delta = tmr_inc - 1; + return tmr_icr + delta; + } +return tmr_icr; +} + +int32 nicr_rd () +{ +return tmr_nicr; +} + +void nicr_wr (int32 val) +{ +tmr_nicr = val; +} + +/* 100Hz base clock unit service */ + +t_stat clk_svc (UNIT *uptr) +{ +tmr_poll = sim_rtcn_calb (clk_tps, TMR_CLK); /* calibrate clock */ +sim_activate (&clk_unit, tmr_poll); /* reactivate unit */ +tmxr_poll = tmr_poll * TMXR_MULT; /* set mux poll */ +if ((tmr_iccs & TMR_CSR_RUN) && tmr_use_100hz) /* timer on, std intvl? */ + tmr_incr (TMR_INC); /* do timer service */ +return SCPE_OK; +} + +/* Interval timer unit service */ + +t_stat tmr_svc (UNIT *uptr) +{ +tmr_incr (tmr_inc); /* incr timer */ +return SCPE_OK; +} + +/* Timer increment */ + +void tmr_incr (uint32 inc) +{ +uint32 new_icr = (tmr_icr + inc) & LMASK; /* add incr */ + +if (new_icr < tmr_icr) { /* ovflo? */ + tmr_icr = 0; /* now 0 */ + if (tmr_iccs & TMR_CSR_DON) /* done? set err */ + tmr_iccs = tmr_iccs | TMR_CSR_ERR; + else tmr_iccs = tmr_iccs | TMR_CSR_DON; /* set done */ + if (tmr_iccs & TMR_CSR_RUN) { /* run? */ + tmr_icr = tmr_nicr; /* reload */ + tmr_sched (); /* reactivate */ + } + if (tmr_iccs & TMR_CSR_IE) /* ie? set int req */ + tmr_int = 1; + else tmr_int = 0; + } +else { + tmr_icr = new_icr; /* no, update icr */ + if (tmr_iccs & TMR_CSR_RUN) /* still running? */ + tmr_sched (); /* reactivate */ + } +return; +} + +/* Timer scheduling */ + +void tmr_sched (void) +{ +tmr_sav = sim_grtime (); /* save intvl base */ +tmr_inc = (~tmr_icr + 1); /* inc = interval */ +if (tmr_inc == 0) tmr_inc = 1; +if (tmr_inc < TMR_INC) { /* 100Hz multiple? */ + sim_activate (&tmr_unit, tmr_inc); /* schedule timer */ + tmr_use_100hz = 0; + } +else tmr_use_100hz = 1; /* let clk handle */ +return; +} + +/* 100Hz clock reset */ + +t_stat clk_reset (DEVICE *dptr) +{ +tmr_poll = sim_rtcn_init (clk_unit.wait, TMR_CLK); /* init 100Hz timer */ +sim_activate_abs (&clk_unit, tmr_poll); /* activate 100Hz unit */ +tmxr_poll = tmr_poll * TMXR_MULT; /* set mux poll */ +if (clk_unit.filebuf == NULL) { /* make sure the TODR is initialized */ + clk_unit.filebuf = calloc(sizeof(TOY), 1); + if (clk_unit.filebuf == NULL) + return SCPE_MEM; + todr_resync (); + } +return SCPE_OK; +} + +/* CLK attach */ + +t_stat clk_attach (UNIT *uptr, char *cptr) +{ +t_stat r; + +uptr->flags = uptr->flags | (UNIT_ATTABLE | UNIT_BUFABLE); +memset (uptr->filebuf, 0, (size_t)uptr->capac); +r = attach_unit (uptr, cptr); +if (r != SCPE_OK) + uptr->flags = uptr->flags & ~(UNIT_ATTABLE | UNIT_BUFABLE); +else + uptr->hwmark = (uint32) uptr->capac; +return r; +} + +/* CLK detach */ + +t_stat clk_detach (UNIT *uptr) +{ +t_stat r; + +r = detach_unit (uptr); +if ((uptr->flags & UNIT_ATT) == 0) + uptr->flags = uptr->flags & ~(UNIT_ATTABLE | UNIT_BUFABLE); +return r; +} + + +/* Interval timer reset */ + +t_stat tmr_reset (DEVICE *dptr) +{ +tmr_iccs = 0; +tmr_icr = 0; +tmr_nicr = 0; +tmr_int = 0; +tmr_use_100hz = 1; +sim_cancel (&tmr_unit); /* cancel timer */ +todr_resync (); /* resync TODR */ +return SCPE_OK; +} + +/* TODR routines */ + +int32 todr_rd (void) +{ +TOY *toy = (TOY *)clk_unit.filebuf; +struct timespec base, now, val; + +clock_gettime(CLOCK_REALTIME, &now); /* get curr time */ +base.tv_sec = toy->toy_gmtbase; +base.tv_nsec = toy->toy_gmtbasemsec * 1000000; +sim_timespec_diff (&val, &now, &base); +return (int32)(val.tv_sec*100 + val.tv_nsec/10000000); /* 100hz Clock Ticks */ +} + +void todr_wr (int32 data) +{ +TOY *toy = (TOY *)clk_unit.filebuf; +struct timespec now, val, base; + +/* Save the GMT time when set value was 0 to record the base for future + read operations in "battery backed-up" state */ + +if (-1 == clock_gettime(CLOCK_REALTIME, &now)) /* get curr time */ + return; /* error? */ +val.tv_sec = ((uint32)data) / 100; +val.tv_nsec = (((uint32)data) % 100) * 10000000; +sim_timespec_diff (&base, &now, &val); /* base = now - data */ +toy->toy_gmtbase = (uint32)base.tv_sec; +toy->toy_gmtbasemsec = base.tv_nsec/1000000; +} + +t_stat todr_resync (void) +{ +TOY *toy = (TOY *)clk_unit.filebuf; + +if (clk_unit.flags & UNIT_ATT) { /* Attached means behave like real VAX780 */ + if (!toy->toy_gmtbase) /* Never set? */ + todr_wr (0); /* Start ticking from 0 */ + } +else { /* Not-Attached means */ + uint32 base; /* behave like simh VMS default */ + time_t curr; + struct tm *ctm; + + curr = time (NULL); /* get curr time */ + if (curr == (time_t) -1) /* error? */ + return SCPE_NOFNC; + ctm = localtime (&curr); /* decompose */ + if (ctm == NULL) /* error? */ + return SCPE_NOFNC; + base = (((((ctm->tm_yday * 24) + /* sec since 1-Jan */ + ctm->tm_hour) * 60) + + ctm->tm_min) * 60) + + ctm->tm_sec; + todr_wr ((base * 100) + 0x10000000); /* use VMS form */ + } +return SCPE_OK; +} + +/* Console write, txdb<11:8> != 0 (console unit) */ + +t_stat txdb_misc_wr (int32 data) +{ +int32 sel = TXDB_GETSEL (data); /* get selection */ + +if (sel == TXDB_MISC) { /* misc function? */ + switch (data & MISC_MASK) { /* case on function */ + + case MISC_CLWS: + case MISC_CLCS: + break; + + case MISC_SWDN: + ABORT (STOP_SWDN); + break; + + case MISC_BOOT: + ABORT (STOP_BOOT); + break; + } + } +return SCPE_OK; +} + +t_stat td_svc (UNIT *uptr) +{ +int32 i, t, data_size; +uint16 c, w; +uint32 da; +int8 *fbuf = uptr->filebuf; + +switch (td_state) { /* case on state */ + + case TD_IDLE: /* idle */ + return SCPE_IERR; /* done */ + + case TD_READ: case TD_WRITE: /* read, write */ + if (td_test_xfr (uptr, td_state)) { /* transfer ok? */ + t = abs (td_block - 0); /* # blocks to seek */ + if (t == 0) /* minimum 1 */ + t = 1; + td_state++; /* set next state */ + sim_activate (uptr, td_swait * t); /* schedule seek */ + break; + } + else td_state = TD_END; + sim_activate (uptr, td_xwait); /* schedule next */ + break; + + case TD_READ1: /* build data packet */ +// da = CALC_DA (td_block); /* get tape address */ + da = (td_block * 512) + td_offset; /* get tape address */ + if (td_txsize > 128) /* Packet length */ + data_size = 128; + else data_size = td_txsize; + td_txsize = td_txsize - data_size; + td_offset = td_offset + data_size; + + td_obptr = 0; + td_obuf[td_obptr++] = TD_OPDAT; /* Data packet */ + td_obuf[td_obptr++] = data_size; /* Data length */ + for (i = 0; i < data_size; i++) /* copy sector to buf */ + td_obuf[td_obptr++] = fbuf[da + i]; + c = 0; + for (i = 0; i < (data_size + 2); i++) { /* Calculate checksum */ + w = (td_obuf[i] << ((i & 0x1) ? 8 : 0)); + c = c + w + ( (uint32)((uint32)c + (uint32)w) > 0xFFFF ? 1 : 0); + } + td_obuf[td_obptr++] = (c & 0xFF); /* Checksum L */ + td_obuf[td_obptr++] = ((c >> 8) & 0xFF); /* Checksum H */ + td_olen = td_obptr; + td_obptr = 0; + td_state = TD_READ2; /* go empty */ + sim_activate (uptr, td_xwait); /* schedule next */ + break; + + case TD_READ2: /* send data packet to host */ + if ((csi_csr & CSR_DONE) == 0) { /* prev data taken? */ + csi_buf = td_obuf[td_obptr++]; /* get next byte */ + csi_csr = csi_csr | CSR_DONE; /* set input flag */ + if (csi_csr & CSR_IE) + csi_int = 1; + if (td_obptr >= td_olen) { /* buffer empty? */ + if (td_txsize > 0) + td_state = TD_READ1; + else + td_state = TD_END; + } + } + sim_activate (uptr, td_xwait); /* schedule next */ + break; + + case TD_WRITE1: /* send continue */ + if ((csi_csr & CSR_DONE) == 0) { /* prev data taken? */ + csi_buf = TD_OPCNT; + csi_csr = csi_csr | CSR_DONE; /* set input flag */ + if (csi_csr & CSR_IE) + csi_int = 1; + break; + } + sim_activate (uptr, td_xwait); /* schedule next */ + break; + + case TD_WRITE2: /* write data to buffer */ + da = (td_block * 512) + td_offset; /* get tape address */ + td_olen = td_ibuf[1]; + for (i = 0; i < td_olen; i++) /* write data to buffer */ + fbuf[da + i] = td_ibuf[i + 2]; + td_offset += td_olen; + td_txsize -= td_olen; + da = da + td_olen; + if (da > uptr->hwmark) /* update hwmark */ + uptr->hwmark = da; + if (td_txsize > 0) + td_state = TD_WRITE1; + else { /* check whole number of blocks written */ + if ((td_olen = (512 - (td_offset % 512)) != 512)) { + for (i = 0; i < td_olen; i++) + fbuf[da + i] = 0; /* zero fill */ + da = da + td_olen; + if (da > uptr->hwmark) /* update hwmark */ + uptr->hwmark = da; + } + td_state = TD_END; + } + sim_activate (uptr, td_xwait); /* schedule next */ + break; + + case TD_END: /* build end packet */ + td_obptr = 0; + td_obuf[td_obptr++] = TD_OPCMD; /* Command packet */ + td_obuf[td_obptr++] = 0xA; /* ** Need definition ** */ + td_obuf[td_obptr++] = TD_CMDEND; + td_obuf[td_obptr++] = td_ecode; /* Success code */ + td_obuf[td_obptr++] = td_unitno; /* Unit number */ + td_obuf[td_obptr++] = 0; /* Not used */ + td_obuf[td_obptr++] = 0; /* Sequence L (not used) */ + td_obuf[td_obptr++] = 0; /* Sequence H (not used) */ + td_obuf[td_obptr++] = (td_offset & 0xFF); /* Byte count L */ + td_obuf[td_obptr++] = ((td_offset >> 8) & 0xFF);/* Byte count H */ + td_obuf[td_obptr++] = 0; /* Summary status L */ + td_obuf[td_obptr++] = 0; /* Summary status H */ + c = 0; + for (i = 0; i < (0xA + 2); i++) { /* Calculate checksum */ + w = (td_obuf[i] << ((i & 0x1) ? 8 : 0)); + c = c + w + ( (uint32)((uint32)c + (uint32)w) > 0xFFFF ? 1 : 0); + } + td_obuf[td_obptr++] = c & 0xFF; /* Checksum L */ + td_obuf[td_obptr++] = (c >> 8) & 0xFF; /* Checksum H */ + td_olen = td_obptr; + td_obptr = 0; + td_state = TD_END1; /* go empty */ + sim_activate (uptr, td_xwait); /* schedule next */ + break; + + case TD_END1: /* send end packet to host */ + if ((csi_csr & CSR_DONE) == 0) { /* prev data taken? */ + csi_buf = td_obuf[td_obptr++]; /* get next byte */ + csi_csr = csi_csr | CSR_DONE; /* set input flag */ + if (csi_csr & CSR_IE) + csi_int = 1; + if (td_obptr >= td_olen) { /* buffer empty? */ + td_state = TD_IDLE; + break; + } + } + sim_activate (uptr, td_xwait); /* schedule next */ + break; + + case TD_INIT: + if ((csi_csr & CSR_DONE) == 0) { /* prev data taken? */ + csi_buf = TD_OPCNT; + csi_csr = csi_csr | CSR_DONE; /* set input flag */ + if (csi_csr & CSR_IE) + csi_int = 1; + td_state = TD_IDLE; + break; + } + sim_activate (uptr, td_xwait); /* schedule next */ + break; + } +return SCPE_OK; +} + +/* Test for data transfer okay */ + +t_bool td_test_xfr (UNIT *uptr, int32 state) +{ +if ((uptr->flags & UNIT_BUF) == 0) /* not buffered? */ + td_ecode = TD_STSNC; +else if (td_block >= TD_NUMBLK) /* bad block? */ + td_ecode = TD_STSBBN; +else if ((state == TD_WRITE) && (uptr->flags & UNIT_WPRT)) /* write and locked? */ + td_ecode = TD_STSWP; +else { + td_ecode = TD_STSOK; + return TRUE; + } +return FALSE; +} + +/* Reset */ + +t_stat td_reset (DEVICE *dptr) +{ +cso_buf = 0; +cso_csr = CSR_DONE; +cso_int = 0; +cso_state = TD_GETOPC; +td_ibptr = 0; +td_obptr = 0; +td_olen = 0; +td_offset = 0; +td_txsize = 0; +sim_cancel (&td_dev.units[0]); +sim_cancel (&td_dev.units[1]); +return SCPE_OK; +} diff --git a/VAX/vax730_sys.c b/VAX/vax730_sys.c new file mode 100644 index 00000000..b95de462 --- /dev/null +++ b/VAX/vax730_sys.c @@ -0,0 +1,680 @@ +/* vax730_sys.c: VAX 11/730 system-specific logic + + Copyright (c) 2010-2011, Matt Burke + This module incorporates code from SimH, Copyright (c) 2004-2008, Robert M Supnik + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name(s) of the author(s) shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from the author(s). + + This module contains the VAX 11/730 system-specific registers and devices. + + sysb system bus controller + + 29-Mar-2011 MB First Version + +*/ + +#include "vax_defs.h" + +#ifdef DONT_USE_INTERNAL_ROM +#define BOOT_CODE_FILENAME "vmb.exe" +#define BOOT_CODE_ARRAY NULL +#define BOOT_CODE_SIZE 0 +#else /* !DONT_USE_INTERNAL_ROM */ +#include "vax_vmb_exe.h" /* Defines BOOT_CODE_FILENAME and BOOT_CODE_ARRAY, etc */ +#endif /* DONT_USE_INTERNAL_ROM */ + +static char cpu_boot_cmd[CBUFSIZE] = { 0 }; /* boot command */ +int32 sys_model = 0; + +/* VAX-11/730 boot device definitions */ + +struct boot_dev { + char *name; + int32 code; + int32 let; + }; + +static t_stat (*nexusR[NEXUS_NUM])(int32 *dat, int32 ad, int32 md); +static t_stat (*nexusW[NEXUS_NUM])(int32 dat, int32 ad, int32 md); + +static struct boot_dev boot_tab[] = { + { "HK", BOOT_HK, 0 }, + { "RL", BOOT_RL, 0 }, + { "RQ", BOOT_UDA, 1 << 24 }, + { "RQB", BOOT_UDA, 1 << 24 }, + { "RQC", BOOT_UDA, 1 << 24 }, + { "RQD", BOOT_UDA, 1 << 24 }, + { "TQ", BOOT_TK, 1 << 24 }, + { "TD", BOOT_TD, 0 }, + { "RB", BOOT_RB, 0 }, + { NULL } + }; + +extern int32 R[16]; +extern int32 PSL; +extern int32 ASTLVL, SISR; +extern int32 mapen, pme, trpirq; +extern int32 in_ie; +extern int32 mchk_va, mchk_ref; +extern int32 crd_err, mem_err, hlt_pin; +extern int32 tmr_int, tti_int, tto_int, csi_int, cso_int; +extern jmp_buf save_env; +extern int32 p1; + +t_stat sysb_reset (DEVICE *dptr); +t_stat vax730_boot (int32 flag, char *ptr); +t_stat vax730_boot_parse (int32 flag, char *ptr); +t_stat cpu_boot (int32 unitno, DEVICE *dptr); + +extern int32 intexc (int32 vec, int32 cc, int32 ipl, int ei); +extern int32 iccs_rd (void); +extern int32 nicr_rd (void); +extern int32 icr_rd (t_bool interp); +extern int32 todr_rd (void); +extern int32 rxcs_rd (void); +extern int32 rxdb_rd (void); +extern int32 txcs_rd (void); +extern int32 csrs_rd (void); +extern int32 csrd_rd (void); +extern int32 csts_rd (void); +extern void iccs_wr (int32 dat); +extern void nicr_wr (int32 dat); +extern void todr_wr (int32 dat); +extern void rxcs_wr (int32 dat); +extern void txcs_wr (int32 dat); +extern void txdb_wr (int32 dat); +extern void csrs_wr (int32 dat); +extern void csts_wr (int32 dat); +extern void cstd_wr (int32 dat); +extern void init_ubus_tab (void); +extern t_stat build_ubus_tab (DEVICE *dptr, DIB *dibp); +extern int32 ubamap_rd (int32 pa); +extern void ubamap_wr (int32 pa, int32 val, int32 lnt); +extern t_bool uba_eval_int (int32 lvl); +extern int32 uba_get_ubvector (int32 lvl); + +/* SYSB data structures + + sysb_dev SYSB device descriptor + sysb_unit SYSB unit + sysb_reg SYSB register list +*/ + +UNIT sysb_unit = { UDATA (NULL, 0, 0) }; + +REG sysb_reg[] = { + { BRDATA (BOOTCMD, cpu_boot_cmd, 16, 8, CBUFSIZE), REG_HRO }, + { NULL } + }; + +DEVICE sysb_dev = { + "SYSB", &sysb_unit, sysb_reg, NULL, + 1, 16, 16, 1, 16, 8, + NULL, NULL, &sysb_reset, + NULL, NULL, NULL, + NULL, 0 + }; + +/* Special boot command, overrides regular boot */ + +CTAB vax730_cmd[] = { + { "BOOT", &vax730_boot, RU_BOOT, + "bo{ot} {/R5:flg} boot device\n", &run_cmd_message }, + { NULL } + }; + +/* The VAX 11/730 has two sources of interrupts + + - internal device interrupts (CPU, console, clock, console storage) + - external device interrupts (Unibus) + + Find highest priority vectorable interrupt */ + +int32 eval_int (void) +{ +int32 ipl = PSL_GETIPL (PSL); +int32 i, t; + +static const int32 sw_int_mask[IPL_SMAX] = { + 0xFFFE, 0xFFFC, 0xFFF8, 0xFFF0, /* 0 - 3 */ + 0xFFE0, 0xFFC0, 0xFF80, 0xFF00, /* 4 - 7 */ + 0xFE00, 0xFC00, 0xF800, 0xF000, /* 8 - B */ + 0xE000, 0xC000, 0x8000 /* C - E */ + }; + +if (hlt_pin) /* hlt pin int */ + return IPL_HLTPIN; +if ((ipl < IPL_CLKINT) && tmr_int) /* clock int */ + return IPL_CLKINT; +for (i = IPL_HMAX; i >= IPL_HMIN; i--) { /* chk hwre int */ + if (i <= ipl) /* at ipl? no int */ + return 0; + if (uba_eval_int(i - IPL_HMIN)) + return i; + } +if ((ipl < IPL_TTINT) && (tti_int || tto_int)) /* console int */ + return IPL_TTINT; +if ((ipl < IPL_CSINT) && (csi_int || cso_int)) /* console storage int */ + return IPL_CSINT; +if (ipl >= IPL_SMAX) /* ipl >= sw max? */ + return 0; +if ((t = SISR & sw_int_mask[ipl]) == 0) /* eligible req */ + return 0; +for (i = IPL_SMAX; i > ipl; i--) { /* check swre int */ + if ((t >> i) & 1) /* req != 0? int */ + return i; + } +return 0; +} + +/* Return vector for highest priority hardware interrupt at IPL lvl */ + +int32 get_vector (int32 lvl) +{ +int32 l; + +if (lvl == IPL_CLKINT) { /* clock? */ + tmr_int = 0; /* clear req */ + return SCB_INTTIM; /* return vector */ + } +if (lvl > IPL_HMAX) { /* error req lvl? */ + ABORT (STOP_UIPL); /* unknown intr */ + } +if ((lvl <= IPL_HMAX) && (lvl >= IPL_HMIN)) { /* nexus? */ + l = lvl - IPL_HMIN; + if (uba_eval_int(l)) + return uba_get_ubvector(l); + } +if (lvl == IPL_TTINT) { /* console? */ + if (tti_int) { /* input? */ + tti_int = 0; /* clear req */ + return SCB_TTI; /* return vector */ + } + if (tto_int) { /* output? */ + tto_int = 0; /* clear req */ + return SCB_TTO; /* return vector */ + } + } +if (lvl == IPL_CSINT) { /* console storage? */ + if (csi_int) { /* input? */ + csi_int = 0; /* clear req */ + return SCB_CSI; /* return vector */ + } + if (cso_int) { /* output? */ + cso_int = 0; /* clear req */ + return SCB_CSO; /* return vector */ + } + } +return 0; +} + +/* Read 730-specific IPR's */ + +int32 ReadIPR (int32 rg) +{ +int32 val; + +switch (rg) { + + case MT_ICCS: /* ICCS */ + val = iccs_rd (); + break; + + case MT_NICR: /* NICR */ + val = nicr_rd (); + break; + + case MT_ICR: /* ICR */ + val = icr_rd (FALSE); + break; + + case MT_TODR: /* TODR */ + val = todr_rd (); + break; + + case MT_ACCS: /* ACCS (not impl) */ + val = 0; + break; + + case MT_RXCS: /* RXCS */ + val = rxcs_rd (); + break; + + case MT_RXDB: /* RXDB */ + val = rxdb_rd (); + break; + + case MT_TXCS: /* TXCS */ + val = txcs_rd (); + break; + + case MT_SID: /* SID */ + val = VAX730_SID | VAX730_MICRO; + break; + + case MT_MCESR: /* MCESR (not impl) */ + val = 0; + break; + + case MT_CSRS: /* CSRS */ + val = csrs_rd (); + break; + + case MT_CSRD: /* CSRD */ + val = csrd_rd (); + break; + + case MT_CSTS: /* CSTS */ + val = csts_rd (); + break; + + case MT_CDR: /* CDR */ + case MT_SBIFS: /* SBIFS */ + case MT_SBIS: /* SBIS */ + case MT_SBISC: /* SBISC */ + case MT_SBIMT: /* SBIMT */ + case MT_SBIER: /* SBIER */ + case MT_SBITA: /* SBITA */ + val = 0; + break; + + default: + RSVD_OPND_FAULT; + } + +return val; +} + +/* Write 730-specific IPR's */ + +void WriteIPR (int32 rg, int32 val) +{ +switch (rg) { + + case MT_ICCS: /* ICCS */ + iccs_wr (val); + break; + + case MT_NICR: /* NICR */ + nicr_wr (val); + break; + + case MT_TODR: /* TODR */ + todr_wr (val); + break; + + case MT_ACCS: /* ACCS (not impl) */ + break; + + case MT_RXCS: /* RXCS */ + rxcs_wr (val); + break; + + case MT_TXCS: /* TXCS */ + txcs_wr (val); + break; + + case MT_TXDB: /* TXDB */ + txdb_wr (val); + break; + + case MT_MCESR: /* MCESR (not impl) */ + break; + + case MT_UBINIT: /* UBINIT (not impl) */ + break; + + case MT_CSRS: /* CSRS */ + csrs_wr (val); + break; + + case MT_CSTS: /* CSTS */ + csts_wr (val); + break; + + case MT_CSTD: /* CSTD */ + cstd_wr (val); + break; + + case MT_CDR: /* CDR */ + case MT_SBIFS: /* SBIFS */ + case MT_SBISC: /* SBISC */ + case MT_SBIMT: /* SBIMT */ + case MT_SBIER: /* SBIER */ + case MT_SBIQC: /* SBIQC */ + break; + + default: + RSVD_OPND_FAULT; + } + +return; +} + +/* ReadReg - read register space + + Inputs: + pa = physical address + lnt = length (BWLQ) + Output: + longword of data +*/ + +int32 ReadReg (int32 pa, int32 lnt) +{ +int32 nexus, val; + +if (ADDR_IS_REG (pa)) { /* reg space? */ + nexus = NEXUS_GETNEX (pa); /* get nexus */ + if (nexusR[nexus] && /* valid? */ + (nexusR[nexus] (&val, pa, lnt) == SCPE_OK)) { + SET_IRQL; + return val; + } + } +MACH_CHECK (MCHK_NXM); +return 0; +} + +/* WriteReg - write register space + + Inputs: + pa = physical address + val = data to write, right justified in 32b longword + lnt = length (BWLQ) + Outputs: + none +*/ + +void WriteReg (int32 pa, int32 val, int32 lnt) +{ +int32 nexus; + +if (ADDR_IS_REG (pa)) { /* reg space? */ + nexus = NEXUS_GETNEX (pa); /* get nexus */ + if (nexusW[nexus] && /* valid? */ + (nexusW[nexus] (val, pa, lnt) == SCPE_OK)) { + SET_IRQL; + return; + } + } +MACH_CHECK (MCHK_NXM); +return; +} + +/* Machine check + + Error status word format + <2:0> = ASTLVL + <3> = PME + <6:4> = arith trap code + Rest will be zero +*/ + +int32 machine_check (int32 p1, int32 opc, int32 cc, int32 delta) +{ +int32 acc, nxm; + +nxm = ((p1 == MCHK_NXM) || (p1 == MCHK_IIA) || (p1 == MCHK_IUA)); +if (nxm) + cc = intexc (SCB_MCHK, cc, 0, IE_EXC); /* take normal exception */ +else + cc = intexc (SCB_MCHK, cc, 0, IE_SVE); /* take severe exception */ +acc = ACC_MASK (KERN); /* in kernel mode */ +in_ie = 1; +SP = SP - 16; /* push 4 words */ +Write (SP, 12, L_LONG, WA); /* # bytes */ +Write (SP + 4, p1, L_LONG, WA); /* mcheck type */ +if (nxm) + Write (SP + 8, mchk_va, L_LONG, WA); /* NXM addr */ +else + Write (SP + 8, 0, L_LONG, WA); /* first parameter */ +Write (SP + 12, 0, L_LONG, WA); /* second parameter */ +in_ie = 0; +return cc; +} + +/* Console entry - only reached if CONHALT is set (AUTORESTART is set */ + +int32 con_halt (int32 code, int32 cc) +{ +if ((cpu_boot_cmd[0] == 0) || /* saved boot cmd? */ + (vax730_boot_parse (0, cpu_boot_cmd) != SCPE_OK) || /* reparse the boot cmd */ + (reset_all (0) != SCPE_OK) || /* reset the world */ + (cpu_boot (0, NULL) != SCPE_OK)) /* set up boot code */ + ABORT (STOP_BOOT); /* any error? */ +printf ("Rebooting...\n"); +if (sim_log) + fprintf (sim_log, "Rebooting...\n"); +return cc; +} + +/* Special boot command - linked into SCP by initial reset + + Syntax: BOOT {/R5:val} + + Sets up R0-R5, calls SCP boot processor with effective BOOT CPU +*/ + +t_stat vax730_boot (int32 flag, char *ptr) +{ +t_stat r; + +r = vax730_boot_parse (flag, ptr); /* parse the boot cmd */ +if (r != SCPE_OK) /* error? */ + return r; +strncpy (cpu_boot_cmd, ptr, CBUFSIZE); /* save for reboot */ +return run_cmd (flag, "CPU"); +} + +/* Parse boot command, set up registers - also used on reset */ + +t_stat vax730_boot_parse (int32 flag, char *ptr) +{ +char gbuf[CBUFSIZE]; +char *slptr, *regptr; +int32 i, r5v, unitno; +DEVICE *dptr; +UNIT *uptr; +DIB *dibp; +uint32 ba; +t_stat r; + +regptr = get_glyph (ptr, gbuf, 0); /* get glyph */ +if ((slptr = strchr (gbuf, '/'))) { /* found slash? */ + regptr = strchr (ptr, '/'); /* locate orig */ + *slptr = 0; /* zero in string */ + } +dptr = find_unit (gbuf, &uptr); /* find device */ +if ((dptr == NULL) || (uptr == NULL)) + return SCPE_ARG; +dibp = (DIB *) dptr->ctxt; /* get DIB */ +if (dibp == NULL) + ba = 0; +else + ba = dibp->ba; +unitno = (int32) (uptr - dptr->units); +r5v = 0; +if ((strncmp (regptr, "/R5:", 4) == 0) || + (strncmp (regptr, "/R5=", 4) == 0) || + (strncmp (regptr, "/r5:", 4) == 0) || + (strncmp (regptr, "/r5=", 4) == 0)) { + r5v = (int32) get_uint (regptr + 4, 16, LMASK, &r); + if (r != SCPE_OK) + return r; + } +else + if (*regptr == '/') { + r5v = (int32) get_uint (regptr + 1, 16, LMASK, &r); + if (r != SCPE_OK) + return r; + } + else { + if (*regptr != 0) + return SCPE_ARG; + } +for (i = 0; boot_tab[i].name != NULL; i++) { + if (strcmp (dptr->name, boot_tab[i].name) == 0) { + R[0] = boot_tab[i].code; + if (boot_tab[i].code == BOOT_RB) { /* vector set by console for RB730 */ + extern DIB rb_dib; + R[0] = R[0] | ((rb_dib.vec - VEC_Q) << 16); + } + R[1] = TR_UBA; + R[2] = boot_tab[i].let | (ba & UBADDRMASK); + R[3] = unitno; + R[4] = 0; + R[5] = r5v; + return SCPE_OK; + } + } +return SCPE_NOFNC; +} + +/* Bootstrap - finish up bootstrap process */ + +t_stat cpu_boot (int32 unitno, DEVICE *dptr) +{ +t_stat r; + + +r = cpu_load_bootcode (BOOT_CODE_FILENAME, BOOT_CODE_ARRAY, BOOT_CODE_SIZE, FALSE, 0x200); +if (r != SCPE_OK) + return r; +SP = PC = 512; +return SCPE_OK; +} + +/* SYSB reset */ + +t_stat sysb_reset (DEVICE *dptr) +{ +sim_vm_cmd = vax730_cmd; +return SCPE_OK; +} + +/* Show nexus */ + +t_stat show_nexus (FILE *st, UNIT *uptr, int32 val, void *desc) +{ +fprintf (st, "nexus=%d", val); +return SCPE_OK; +} + +/* Init nexus tables */ + +void init_nexus_tab (void) +{ +uint32 i; + +for (i = 0; i < NEXUS_NUM; i++) { + nexusR[i] = NULL; + nexusW[i] = NULL; + } +return; +} + +/* Build nexus tables + + Inputs: + dptr = pointer to device + dibp = pointer to DIB + Outputs: + status +*/ + + +t_stat build_nexus_tab (DEVICE *dptr, DIB *dibp) +{ +uint32 idx; + +if ((dptr == NULL) || (dibp == NULL)) + return SCPE_IERR; +idx = dibp->ba; +if (idx >= NEXUS_NUM) + return SCPE_IERR; +if ((nexusR[idx] && dibp->rd && /* conflict? */ + (nexusR[idx] != dibp->rd)) || + (nexusW[idx] && dibp->wr && + (nexusW[idx] != dibp->wr))) { + printf ("Nexus %s conflict at %d\n", sim_dname (dptr), dibp->ba); + if (sim_log) + fprintf (sim_log, "Nexus %s conflict at %d\n", sim_dname (dptr), dibp->ba); + return SCPE_STOP; + } +if (dibp->rd) /* set rd dispatch */ + nexusR[idx] = dibp->rd; +if (dibp->wr) /* set wr dispatch */ + nexusW[idx] = dibp->wr; +return SCPE_OK; +} + +/* Build dib_tab from device list */ + +t_stat build_dib_tab (void) +{ +uint32 i; +DEVICE *dptr; +DIB *dibp; +t_stat r; + +init_nexus_tab (); +init_ubus_tab (); +for (i = 0; (dptr = sim_devices[i]) != NULL; i++) { /* loop thru dev */ + dibp = (DIB *) dptr->ctxt; /* get DIB */ + if (dibp && !(dptr->flags & DEV_DIS)) { /* defined, enabled? */ + if (dptr->flags & DEV_NEXUS) { /* Nexus? */ + if ((r = build_nexus_tab (dptr, dibp))) /* add to dispatch table */ + return r; + } + else { /* no, Unibus device */ + if ((r = build_ubus_tab (dptr, dibp))) /* add to dispatch tab */ + return r; + } /* end else */ + } /* end if enabled */ + } /* end for */ +return SCPE_OK; +} + +t_stat cpu_print_model (FILE *st) +{ +fprintf (st, "VAX 11/730"); +return SCPE_OK; +} + +t_stat cpu_model_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr) +{ +fprintf (st, "Initial memory size is 2MB.\n\n"); +fprintf (st, "The simulator is booted with the BOOT command:\n\n"); +fprintf (st, " sim> BO{OT} {/R5:flags}\n\n"); +fprintf (st, "where is one of:\n\n"); +fprintf (st, " HKn to boot from hkn\n"); +fprintf (st, " RLn to boot from rln\n"); +fprintf (st, " RQn to boot from rqn\n"); +fprintf (st, " RQBn to boot from rqbn\n"); +fprintf (st, " RQCn to boot from rqcn\n"); +fprintf (st, " RQDn to boot from rqdn\n"); +fprintf (st, " TQn to boot from tqn\n"); +fprintf (st, " TDn to boot from tdn (TU58)\n"); +fprintf (st, " RBn to boot from rbn\n\n"); +return SCPE_OK; +} diff --git a/VAX/vax730_syslist.c b/VAX/vax730_syslist.c new file mode 100644 index 00000000..6fa3946f --- /dev/null +++ b/VAX/vax730_syslist.c @@ -0,0 +1,136 @@ +/* vax730_syslist.c: VAX 730 device list + + Copyright (c) 2010-2011, Matt Burke + This module incorporates code from SimH, Copyright (c) 1998-2008, Robert M Supnik + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name(s) of the author(s) shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from the author(s). + + 29-Mar-2011 MB First Version +*/ + +#include "vax_defs.h" + +char sim_name[] = "VAX730"; + +extern DEVICE cpu_dev; +extern DEVICE tlb_dev; +extern DEVICE sysb_dev; +extern DEVICE mctl_dev; +extern DEVICE uba_dev; +extern DEVICE clk_dev; +extern DEVICE tmr_dev; +extern DEVICE tti_dev, tto_dev; +extern DEVICE td_dev; +extern DEVICE cr_dev; +extern DEVICE lpt_dev; +extern DEVICE rq_dev, rqb_dev, rqc_dev, rqd_dev; +extern DEVICE rb_dev; +extern DEVICE rl_dev; +extern DEVICE hk_dev; +extern DEVICE ry_dev; +extern DEVICE ts_dev; +extern DEVICE tq_dev; +extern DEVICE dz_dev; +extern DEVICE vh_dev; +extern DEVICE xu_dev, xub_dev; +extern DEVICE dmc_dev[]; + +extern UNIT cpu_unit; +extern void WriteB (uint32 pa, int32 val); + +DEVICE *sim_devices[] = { + &cpu_dev, + &tlb_dev, + &sysb_dev, + &mctl_dev, + &uba_dev, + &clk_dev, + &tmr_dev, + &tti_dev, + &tto_dev, + &td_dev, + &dz_dev, + &vh_dev, + &cr_dev, + &lpt_dev, + &rl_dev, + &hk_dev, + &rq_dev, + &rqb_dev, + &rqc_dev, + &rqd_dev, + &rb_dev, + &ry_dev, + &ts_dev, + &tq_dev, + &xu_dev, + &xub_dev, + &dmc_dev[0], + &dmc_dev[1], + &dmc_dev[2], + &dmc_dev[3], + NULL + }; + +/* Binary loader + + The binary loader handles absolute system images, that is, system + images linked /SYSTEM. These are simply a byte stream, with no + origin or relocation information. + + -r load ROM0 + -s load ROM1 + -o for memory, specify origin +*/ + +t_stat sim_load (FILE *fileref, char *cptr, char *fnam, int flag) +{ +t_stat r; +int32 val; +uint32 origin, limit; + +if (flag) /* dump? */ + return SCPE_ARG; +origin = 0; /* memory */ +limit = (uint32) cpu_unit.capac; +if (sim_switches & SWMASK ('O')) { /* origin? */ + origin = (int32) get_uint (cptr, 16, 0xFFFFFFFF, &r); + if (r != SCPE_OK) + return SCPE_ARG; + } + +while ((val = getc (fileref)) != EOF) { /* read byte stream */ + if (sim_switches & SWMASK ('R')) { /* ROM0? */ + return SCPE_NXM; + } + else if (sim_switches & SWMASK ('S')) { /* ROM1? */ + return SCPE_NXM; + } + else { + if (origin >= limit) /* NXM? */ + return SCPE_NXM; + WriteB (origin, val); /* memory */ + } + origin = origin + 1; + } +return SCPE_OK; +} diff --git a/VAX/vax730_uba.c b/VAX/vax730_uba.c new file mode 100644 index 00000000..b03f0bea --- /dev/null +++ b/VAX/vax730_uba.c @@ -0,0 +1,664 @@ +/* vax730_uba.c: VAX 11/730 Unibus adapter + + Copyright (c) 2010-2011, Matt Burke + This module incorporates code from SimH, Copyright (c) 2004-2008, Robert M Supnik + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name(s) of the author(s) shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from the author(s). + + uba DW730 Unibus adapter + + 29-Mar-2011 MB First Version +*/ + +#include "vax_defs.h" + +/* Unibus adapter */ + +#define UBA_NMAPR 496 /* number of map reg */ + +/* Unibus configuration register */ + +#define UBACNF_OF 0x00 +#define UBACNF_CODE 0x00000028 /* adapter code */ + +/* Data path registers */ + +#define UBADPR_OF 0x01 + +/* Control & Status register */ + +#define UBACSR_OF 0x04 +#define UBACSR_WNV 0x00004000 /* write not valid */ +#define UBACSR_TBPAR 0x00008000 /* TB parity err */ +#define UBACSR_NXM 0x00010000 /* UB NXM */ +#define UBACSR_RDS 0x80000000 /* UB read data subs */ + +/* Vector registers - read only */ + +#define UBA_UVEC 0x80000000 + +/* RB730 registers */ + +#define RB730_OF 0x80 +#define RB730_LN 8 + +/* Map registers */ + +#define UBAMAP_OF 0x200 +#define UBAMAP_VLD 0x80000000 /* valid */ +#define UBAMAP_LWAE 0x04000000 /* LW access enb - ni */ +#define UBAMAP_ODD 0x02000000 /* odd byte */ +#define UBAMAP_V_DP 21 /* data path */ +#define UBAMAP_M_DP 0xF +#define UBAMAP_DP (UBAMAP_M_DP << UBAMAP_V_DP) +#define UBAMAP_GETDP(x) (((x) >> UBAMAP_V_DP) & UBAMAP_M_DP) +#define UBAMAP_PAG 0x001FFFFF +#define UBAMAP_RD (0x86000000 | UBAMAP_DP | UBAMAP_PAG) +#define UBAMAP_WR (UBAMAP_RD) + +/* Debug switches */ + +#define UBA_DEB_RRD 0x01 /* reg reads */ +#define UBA_DEB_RWR 0x02 /* reg writes */ +#define UBA_DEB_MRD 0x04 /* map reads */ +#define UBA_DEB_MWR 0x08 /* map writes */ +#define UBA_DEB_XFR 0x10 /* transfers */ +#define UBA_DEB_ERR 0x20 /* errors */ + +int32 int_req[IPL_HLVL] = { 0 }; /* intr, IPL 14-17 */ +uint32 uba_csr = 0; /* control & status reg */ +uint32 uba_fmer = 0; /* failing map reg */ +uint32 uba_map[UBA_NMAPR] = { 0 }; /* map registers */ +int32 autcon_enb = 1; /* autoconfig enable */ + +extern int32 trpirq; +extern int32 autcon_enb; +extern jmp_buf save_env; +extern UNIT cpu_unit; +extern int32 p1; + +t_stat uba_reset (DEVICE *dptr); +t_stat uba_ex (t_value *vptr, t_addr exta, UNIT *uptr, int32 sw); +t_stat uba_dep (t_value val, t_addr exta, UNIT *uptr, int32 sw); +t_stat uba_rdreg (int32 *val, int32 pa, int32 mode); +t_stat uba_wrreg (int32 val, int32 pa, int32 lnt); +int32 uba_get_ubvector (int32 lvl); +t_bool uba_eval_int (int32 lvl); +void uba_ubpdn (int32 time); +t_bool uba_map_addr (uint32 ua, uint32 *ma); +t_stat set_autocon (UNIT *uptr, int32 val, char *cptr, void *desc); +t_stat show_autocon (FILE *st, UNIT *uptr, int32 val, void *desc); +t_stat show_iospace (FILE *st, UNIT *uptr, int32 val, void *desc); +t_stat uba_show_virt (FILE *st, UNIT *uptr, int32 val, void *desc); + +extern int32 eval_int (void); +extern t_stat build_dib_tab (void); +extern t_stat rb_rd32 (int32 *data, int32 PA, int32 access); +extern t_stat rb_wr32 (int32 data, int32 PA, int32 access); + +/* Unibus IO page dispatches */ + +t_stat (*iodispR[IOPAGESIZE >> 1])(int32 *dat, int32 ad, int32 md); +t_stat (*iodispW[IOPAGESIZE >> 1])(int32 dat, int32 ad, int32 md); + +/* Unibus interrupt request to interrupt action map */ + +int32 (*int_ack[IPL_HLVL][32])(void); /* int ack routines */ + +/* Unibus interrupt request to vector map */ + +int32 int_vec[IPL_HLVL][32]; /* int req to vector */ + +/* Unibus adapter data structures + + uba_dev UBA device descriptor + uba_unit UBA units + uba_reg UBA register list +*/ + +DIB uba_dib = { TR_UBA, 0, &uba_rdreg, &uba_wrreg, 0, 0 }; + +UNIT uba_unit = { UDATA (0, 0, 0) }; + +REG uba_reg[] = { + { HRDATAD (IPL17, int_req[3], 32, "IPL 17 interrupt flags"), REG_RO }, + { HRDATAD (IPL16, int_req[2], 32, "IPL 16 interrupt flags"), REG_RO }, + { HRDATAD (IPL15, int_req[1], 32, "IPL 15 interrupt flags"), REG_RO }, + { HRDATAD (IPL14, int_req[0], 32, "IPL 14 interrupt flags"), REG_RO }, + { HRDATAD (CSR, uba_csr, 32, "control/status register") }, + { BRDATAD (MAP, uba_map, 16, 32, 496, "Unibus map registers") }, + { FLDATA (AUTOCON, autcon_enb, 0), REG_HRO }, + { NULL } + }; + +MTAB uba_mod[] = { + { MTAB_XTD|MTAB_VDV, TR_UBA, "NEXUS", NULL, + NULL, &show_nexus }, + { MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, "IOSPACE", NULL, + NULL, &show_iospace }, + { MTAB_XTD|MTAB_VDV, 1, "AUTOCONFIG", "AUTOCONFIG", + &set_autocon, &show_autocon }, + { MTAB_XTD|MTAB_VDV, 0, NULL, "NOAUTOCONFIG", + &set_autocon, NULL }, + { MTAB_XTD|MTAB_VDV|MTAB_NMO|MTAB_SHP, 0, "VIRTUAL", NULL, + NULL, &uba_show_virt }, + { 0 } + }; + +DEBTAB uba_deb[] = { + { "REGREAD", UBA_DEB_RRD }, + { "REGWRITE", UBA_DEB_RWR }, + { "MAPREAD", UBA_DEB_MRD }, + { "MAPWRITE", UBA_DEB_MWR }, + { "XFER", UBA_DEB_XFR }, + { "ERROR", UBA_DEB_ERR }, + { NULL, 0 } + }; + +DEVICE uba_dev = { + "UBA", &uba_unit, uba_reg, uba_mod, + 1, 16, UBADDRWIDTH, 2, 16, 16, + &uba_ex, &uba_dep, &uba_reset, + NULL, NULL, NULL, + &uba_dib, DEV_NEXUS | DEV_DEBUG, 0, + uba_deb, 0, 0 + }; + +/* Read Unibus adapter register - aligned lw only */ + +t_stat uba_rdreg (int32 *val, int32 pa, int32 lnt) +{ +int32 idx, ofs; + +if ((pa & 3) || (lnt != L_LONG)) { /* unaligned or not lw? */ + printf (">>UBA: invalid adapter read mask, pa = %X, lnt = %d\r\n", pa, lnt); + // **FIXME** - Set error bit? + return SCPE_OK; + } +ofs = NEXUS_GETOFS (pa); /* get offset */ +if (ofs >= UBAMAP_OF) { /* map? */ + idx = ofs - UBAMAP_OF; + if (idx >= UBA_NMAPR) return SCPE_NXM; /* valid? */ + *val = uba_map[idx] & UBAMAP_RD; + if (DEBUG_PRI (uba_dev, UBA_DEB_MRD)) + fprintf (sim_deb, ">>UBA: map %d read, value = %X\n", idx, *val); + return SCPE_OK; + } +if (ofs >= RB730_OF) { /* RB730? */ + idx = ofs - RB730_OF; + if (idx >= RB730_LN) return SCPE_NXM; /* valid? */ + return rb_rd32 (val, pa, lnt); + } + +switch (ofs) { /* case on offset */ + + case UBACNF_OF: /* Config Reg */ + *val = UBACNF_CODE; + break; + + case UBADPR_OF + 0: /* DP Regs */ + case UBADPR_OF + 1: + case UBADPR_OF + 2: + *val = 0x0; /* Not used on 11/730 */ + break; + + case UBACSR_OF: /* CSR */ + *val = uba_csr; + break; + + default: + return SCPE_NXM; + } + +if (DEBUG_PRI (uba_dev, UBA_DEB_RRD)) + fprintf (sim_deb, ">>UBA: reg %d read, value = %X\n", ofs, *val); +return SCPE_OK; +} + +/* Write Unibus adapter register */ + +t_stat uba_wrreg (int32 val, int32 pa, int32 lnt) +{ +int32 idx, ofs; + +if ((pa & 3) || (lnt != L_LONG)) { /* unaligned or not lw? */ + printf (">>UBA: invalid adapter write mask, pa = %X, lnt = %d\r\n", pa, lnt); + // **FIXME** - Set error bit? + return SCPE_OK; + } +ofs = NEXUS_GETOFS (pa); /* get offset */ +if (ofs >= UBAMAP_OF) { /* map? */ + idx = ofs - UBAMAP_OF; + if (idx >= UBA_NMAPR) return SCPE_NXM; /* valid? */ + uba_map[idx] = val & UBAMAP_WR; + if (DEBUG_PRI (uba_dev, UBA_DEB_MWR)) + fprintf (sim_deb, ">>UBA: map %d write, value = %X\n", idx, val); + return SCPE_OK; + } +if (ofs >= RB730_OF) { /* RB730? */ + idx = ofs - RB730_OF; + if (idx >= RB730_LN) return SCPE_NXM; /* valid? */ + return rb_wr32 (val, pa, lnt); + } + +switch (ofs) { /* case on offset */ + + case UBACNF_OF: /* Config Reg */ + case UBADPR_OF + 0: /* DP Regs */ + case UBADPR_OF + 1: + case UBADPR_OF + 2: + break; /* ignore writes */ + + case UBACSR_OF: /* CSR */ + if(val & 0x10000) uba_csr = 0; + break; + + default: + return SCPE_NXM; + } + +if (DEBUG_PRI (uba_dev, UBA_DEB_RWR)) + fprintf (sim_deb, ">>UBA: reg %d write, value = %X\n", ofs, val); +return SCPE_OK; +} + +/* Read and write Unibus I/O space */ + +int32 ReadUb (uint32 pa) +{ +int32 idx, val; + +if (ADDR_IS_IOP (pa)) { /* iopage */ + idx = (pa & IOPAGEMASK) >> 1; + if (iodispR[idx]) { + iodispR[idx] (&val, pa, READ); + return val; + } + } +MACH_CHECK(MCHK_IIA); +return 0; +} + +void WriteUb (uint32 pa, int32 val, int32 mode) +{ +int32 idx; + +if (ADDR_IS_IOP (pa)) { /* iopage */ + idx = (pa & IOPAGEMASK) >> 1; + if (iodispW[idx]) { + iodispW[idx] (val, pa, mode); + return; + } + } +MACH_CHECK(MCHK_IIA); +return; +} + +/* ReadIO - read from IO - UBA only responds to byte, aligned word + + Inputs: + pa = physical address + lnt = length (BWLQ) + Output: + longword of data +*/ + +int32 ReadIO (uint32 pa, int32 lnt) +{ +uint32 iod; + +if ((lnt == L_BYTE) || /* byte? */ + ((lnt == L_WORD) && ((pa & 1) == 0))) { /* aligned word? */ + iod = ReadUb (pa); /* DATI from Unibus */ + if (pa & 2) /* position */ + iod = iod << 16; + } +else { + printf (">>UBA: invalid read mask, pa = %x, lnt = %d\n", pa, lnt); + // **FIXME** - Set error bit? + iod = 0; + } +SET_IRQL; +return iod; +} + +/* WriteIO - write to IO - UBA only responds to byte, aligned word + + Inputs: + pa = physical address + val = data to write, right justified in 32b longword + lnt = length (BWL) + Outputs: + none +*/ + +void WriteIO (uint32 pa, int32 val, int32 lnt) +{ +if (lnt == L_BYTE) /* byte? DATOB */ + WriteUb (pa, val, WRITEB); +else if ((lnt == L_WORD) && ((pa & 1) == 0)) /* aligned word? */ + WriteUb (pa, val, WRITE); /* DATO */ +else { + printf (">>UBA: invalid write mask, pa = %x, lnt = %d\n", pa, lnt); + // **FIXME** - Set error bit? + } +SET_IRQL; /* update ints */ +return; +} + +/* Update UBA nexus interrupts */ + +t_bool uba_eval_int (int32 lvl) +{ +return (int_req[lvl] != 0); +} + +/* Return vector for Unibus interrupt at relative IPL level [0-3] */ + +int32 uba_get_ubvector (int32 lvl) +{ +int32 i, vec; + +vec = 0; +for (i = 0; int_req[lvl] && (i < 32); i++) { + if ((int_req[lvl] >> i) & 1) { + int_req[lvl] = int_req[lvl] & ~(1u << i); + if (int_ack[lvl][i]) + return (vec | int_ack[lvl][i]()); + return (vec | int_vec[lvl][i]); + } + } +return vec; +} + +/* Unibus I/O buffer routines + + Map_ReadB - fetch byte buffer from memory + Map_ReadW - fetch word buffer from memory + Map_WriteB - store byte buffer into memory + Map_WriteW - store word buffer into memory +*/ + +int32 Map_ReadB (uint32 ba, int32 bc, uint8 *buf) +{ +int32 i, j, pbc; +uint32 ma, dat; + +ba = ba & UBADDRMASK; /* mask UB addr */ +for (i = 0; i < bc; i = i + pbc) { /* loop by pages */ + if (!uba_map_addr (ba + i, &ma)) /* page inv or NXM? */ + return (bc - i); + pbc = VA_PAGSIZE - VA_GETOFF (ma); /* left in page */ + if (pbc > (bc - i)) /* limit to rem xfr */ + pbc = bc - i; + if (DEBUG_PRI (uba_dev, UBA_DEB_XFR)) + fprintf (sim_deb, ">>UBA: 8b read, ma = %X, bc = %X\n", ma, pbc); + if ((ma | pbc) & 3) { /* aligned LW? */ + for (j = 0; j < pbc; ma++, j++) { /* no, do by bytes */ + *buf++ = ReadB (ma); + } + } + else { /* yes, do by LW */ + for (j = 0; j < pbc; ma = ma + 4, j = j + 4) { + dat = ReadL (ma); /* get lw */ + *buf++ = dat & BMASK; /* low 8b */ + *buf++ = (dat >> 8) & BMASK; /* next 8b */ + *buf++ = (dat >> 16) & BMASK; /* next 8b */ + *buf++ = (dat >> 24) & BMASK; + } + } + } +return 0; +} + +int32 Map_ReadW (uint32 ba, int32 bc, uint16 *buf) +{ +int32 i, j, pbc; +uint32 ma, dat; + +ba = ba & UBADDRMASK; /* mask UB addr */ +bc = bc & ~01; +for (i = 0; i < bc; i = i + pbc) { /* loop by pages */ + if (!uba_map_addr (ba + i, &ma)) /* page inv or NXM? */ + return (bc - i); + pbc = VA_PAGSIZE - VA_GETOFF (ma); /* left in page */ + if (pbc > (bc - i)) /* limit to rem xfr */ + pbc = bc - i; + if (DEBUG_PRI (uba_dev, UBA_DEB_XFR)) + fprintf (sim_deb, ">>UBA: 16b read, ma = %X, bc = %X\n", ma, pbc); + if ((ma | pbc) & 1) { /* aligned word? */ + for (j = 0; j < pbc; ma++, j++) { /* no, do by bytes */ + if ((i + j) & 1) { /* odd byte? */ + *buf = (*buf & BMASK) | (ReadB (ma) << 8); + buf++; + } + else *buf = (*buf & ~BMASK) | ReadB (ma); + } + } + else if ((ma | pbc) & 3) { /* aligned LW? */ + for (j = 0; j < pbc; ma = ma + 2, j = j + 2) { /* no, words */ + *buf++ = ReadW (ma); /* get word */ + } + } + else { /* yes, do by LW */ + for (j = 0; j < pbc; ma = ma + 4, j = j + 4) { + dat = ReadL (ma); /* get lw */ + *buf++ = dat & WMASK; /* low 16b */ + *buf++ = (dat >> 16) & WMASK; /* high 16b */ + } + } + } +return 0; +} + +int32 Map_WriteB (uint32 ba, int32 bc, uint8 *buf) +{ +int32 i, j, pbc; +uint32 ma, dat; + +ba = ba & UBADDRMASK; /* mask UB addr */ +for (i = 0; i < bc; i = i + pbc) { /* loop by pages */ + if (!uba_map_addr (ba + i, &ma)) /* page inv or NXM? */ + return (bc - i); + pbc = VA_PAGSIZE - VA_GETOFF (ma); /* left in page */ + if (pbc > (bc - i)) /* limit to rem xfr */ + pbc = bc - i; + if (DEBUG_PRI (uba_dev, UBA_DEB_XFR)) + fprintf (sim_deb, ">>UBA: 8b write, ma = %X, bc = %X\n", ma, pbc); + if ((ma | pbc) & 3) { /* aligned LW? */ + for (j = 0; j < pbc; ma++, j++) { /* no, do by bytes */ + WriteB (ma, *buf); + buf++; + } + } + else { /* yes, do by LW */ + for (j = 0; j < pbc; ma = ma + 4, j = j + 4) { + dat = (uint32) *buf++; /* get low 8b */ + dat = dat | (((uint32) *buf++) << 8); /* merge next 8b */ + dat = dat | (((uint32) *buf++) << 16); /* merge next 8b */ + dat = dat | (((uint32) *buf++) << 24); /* merge hi 8b */ + WriteL (ma, dat); /* store lw */ + } + } + } +return 0; +} + +int32 Map_WriteW (uint32 ba, int32 bc, uint16 *buf) +{ +int32 i, j, pbc; +uint32 ma, dat; + +ba = ba & UBADDRMASK; /* mask UB addr */ +bc = bc & ~01; +for (i = 0; i < bc; i = i + pbc) { /* loop by pages */ + if (!uba_map_addr (ba + i, &ma)) /* page inv or NXM? */ + return (bc - i); + pbc = VA_PAGSIZE - VA_GETOFF (ma); /* left in page */ + if (pbc > (bc - i)) /* limit to rem xfr */ + pbc = bc - i; + if (DEBUG_PRI (uba_dev, UBA_DEB_XFR)) + fprintf (sim_deb, ">>UBA: 16b write, ma = %X, bc = %X\n", ma, pbc); + if ((ma | pbc) & 1) { /* aligned word? */ + for (j = 0; j < pbc; ma++, j++) { /* no, bytes */ + if ((i + j) & 1) { + WriteB (ma, (*buf >> 8) & BMASK); + buf++; + } + else WriteB (ma, *buf & BMASK); + } + } + else if ((ma | pbc) & 3) { /* aligned LW? */ + for (j = 0; j < pbc; ma = ma + 2, j = j + 2) { /* no, words */ + WriteW (ma, *buf); /* write word */ + buf++; + } + } + else { /* yes, do by LW */ + for (j = 0; j < pbc; ma = ma + 4, j = j + 4) { + dat = (uint32) *buf++; /* get low 16b */ + dat = dat | (((uint32) *buf++) << 16); /* merge hi 16b */ + WriteL (ma, dat); /* store LW */ + } + } + } +return 0; +} + +/* Map an address via the translation map */ + +t_bool uba_map_addr (uint32 ua, uint32 *ma) +{ +uint32 ublk, umap; + +ublk = ua >> VA_V_VPN; /* Unibus blk */ +if (ublk >= UBA_NMAPR) /* unimplemented? */ + return FALSE; +umap = uba_map[ublk]; /* get map */ +if (umap & UBAMAP_VLD) { /* valid? */ + *ma = ((umap & UBAMAP_PAG) << VA_V_VPN) + VA_GETOFF (ua); + if ((umap & UBAMAP_DP) && (umap & UBAMAP_ODD)) /* buffered dp? */ + *ma = *ma + 1; /* byte offset? */ + return (ADDR_IS_MEM (*ma)); /* legit addr */ + } +return FALSE; +} + +/* Map an address via the translation map - console version (no status changes) */ + +t_bool uba_map_addr_c (uint32 ua, uint32 *ma) +{ +uint32 ublk, umap; + +ublk = ua >> VA_V_VPN; /* Unibus blk */ +if (ublk >= UBA_NMAPR) /* unimplemented? */ + return FALSE; +umap = uba_map[ublk]; /* get map */ +if (umap & UBAMAP_VLD) { /* valid? */ + *ma = ((umap & UBAMAP_PAG) << VA_V_VPN) + VA_GETOFF (ua); + if ((umap & UBAMAP_DP) && (umap & UBAMAP_ODD)) /* buffered dp? */ + *ma = *ma + 1; /* byte offset? */ + return TRUE; /* legit addr */ + } +return FALSE; +} + +/* Unibus power fail routines */ + +void uba_ubpdn (int32 time) +{ +int32 i; +DEVICE *dptr; + +for (i = 0; sim_devices[i] != NULL; i++) { /* reset Unibus */ + dptr = sim_devices[i]; + if (dptr->reset && (dptr->flags & DEV_UBUS)) + dptr->reset (dptr); + } +return; +} + +/* Reset Unibus adapter */ + +t_stat uba_reset (DEVICE *dptr) +{ +int32 i; + +for (i = 0; i < IPL_HLVL; i++) { + int_req[i] = 0; + } +for (i = 0; i < UBA_NMAPR; i++) + uba_map[i] = 0; +uba_csr = 0; +return SCPE_OK; +} + +/* Memory examine via map (word only) */ + +t_stat uba_ex (t_value *vptr, t_addr exta, UNIT *uptr, int32 sw) +{ +uint32 ua = (uint32) exta, pa; + +if ((vptr == NULL) || (ua >= UBADDRSIZE)) + return SCPE_ARG; +if (uba_map_addr_c (ua, &pa) && ADDR_IS_MEM (pa)) { + *vptr = (uint32) ReadW (pa); + return SCPE_OK; + } +return SCPE_NXM; +} + +/* Memory deposit via map (word only) */ + +t_stat uba_dep (t_value val, t_addr exta, UNIT *uptr, int32 sw) +{ +uint32 ua = (uint32) exta, pa; + +if (ua >= UBADDRSIZE) + return SCPE_ARG; +if (uba_map_addr_c (ua, &pa) && ADDR_IS_MEM (pa)) { + WriteW (pa, (int32) val); + return SCPE_OK; + } +return SCPE_NXM; +} + +/* Show UBA virtual address */ + +t_stat uba_show_virt (FILE *of, UNIT *uptr, int32 val, void *desc) +{ +t_stat r; +char *cptr = (char *) desc; +uint32 ua, pa; + +if (cptr) { + ua = (uint32) get_uint (cptr, 16, UBADDRSIZE - 1, &r); + if (r == SCPE_OK) { + if (uba_map_addr_c (ua, &pa)) + fprintf (of, "Unibus %-X = physical %-X\n", ua, pa); + else fprintf (of, "Unibus %-X: invalid mapping\n", ua); + return SCPE_OK; + } + } +fprintf (of, "Invalid argument\n"); +return SCPE_OK; +} diff --git a/VAX/vax750_cmi.c b/VAX/vax750_cmi.c new file mode 100644 index 00000000..b710b393 --- /dev/null +++ b/VAX/vax750_cmi.c @@ -0,0 +1,772 @@ +/* vax750_cmi.c: VAX 11/750 CMI + + Copyright (c) 2010-2011, Matt Burke + This module incorporates code from SimH, Copyright (c) 2004-2011, Robert M Supnik + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name(s) of the author(s) shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from the author(s). + + This module contains the VAX 11/750 system-specific registers and devices. + + cmi bus controller + + 21-Oct-2012 MB First Version +*/ + +#include "vax_defs.h" + +#ifdef DONT_USE_INTERNAL_ROM +#define BOOT_CODE_FILENAME "vmb.exe" +#else /* !DONT_USE_INTERNAL_ROM */ +#include "vax_vmb_exe.h" /* Defines BOOT_CODE_FILENAME and BOOT_CODE_ARRAY, etc */ +#endif /* DONT_USE_INTERNAL_ROM */ + +/* 11/750 specific IPRs */ + +#define CMIERR_CRD 0x00000001 +#define CMIERR_LEB 0x00000002 +#define CMIERR_RDS 0x00000004 +#define CMIERR_ME 0x00000008 +#define CMIERR_TBH 0x00000010 +#define CMIERR_TBG0DE 0x00000100 +#define CMIERR_TBG1DE 0x00000200 +#define CMIERR_TBG0TE 0x00000400 +#define CMIERR_TBG1TE 0x00000800 +#define CMIERR_V_MODE 16 +#define CMIERR_M_MODE 0x3 +#define CMIERR_MODE (CMIERR_M_MODE << CMIERR_V_MODE) +#define CMIERR_REF 0x00040000 +#define CMIERR_RM 0x00080000 +#define CMIERR_EN 0x00100000 + +/* System registers */ + +/* VAX-11/750 boot device definitions */ + +struct boot_dev { + char *name; + int32 code; + int32 let; + }; + +uint32 nexus_req[NEXUS_HLVL]; /* nexus int req */ +uint32 cmi_err = 0; +uint32 cmi_cadr = 0; +char cpu_boot_cmd[CBUFSIZE] = { 0 }; /* boot command */ +int32 sys_model = 0; + +static t_stat (*nexusR[NEXUS_NUM])(int32 *dat, int32 ad, int32 md); +static t_stat (*nexusW[NEXUS_NUM])(int32 dat, int32 ad, int32 md); + +static struct boot_dev boot_tab[] = { + { "RP", BOOT_MB, 0 }, + { "HK", BOOT_HK, 0 }, + { "RL", BOOT_RL, 0 }, + { "RQ", BOOT_UDA, 1 << 24 }, + { "RQB", BOOT_UDA, 1 << 24 }, + { "RQC", BOOT_UDA, 1 << 24 }, + { "RQD", BOOT_UDA, 1 << 24 }, + { "TQ", BOOT_TK, 1 << 24 }, + { "TD", BOOT_TD, 0 }, + { NULL } + }; + +extern int32 R[16]; +extern int32 PSL; +extern int32 ASTLVL, SISR; +extern int32 mapen, pme, trpirq; +extern int32 in_ie; +extern int32 mchk_va, mchk_ref; +extern int32 crd_err, mem_err, hlt_pin; +extern int32 tmr_int, tti_int, tto_int, csi_int, cso_int; +extern jmp_buf save_env; +extern int32 p1; + +t_stat cmi_reset (DEVICE *dptr); +void cmi_set_tmo (void); +t_stat vax750_boot (int32 flag, char *ptr); +t_stat vax750_boot_parse (int32 flag, char *ptr); +t_stat cpu_boot (int32 unitno, DEVICE *dptr); + +extern int32 intexc (int32 vec, int32 cc, int32 ipl, int ei); +extern int32 iccs_rd (void); +extern int32 nicr_rd (void); +extern int32 icr_rd (t_bool interp); +extern int32 todr_rd (void); +extern int32 rxcs_rd (void); +extern int32 rxdb_rd (void); +extern int32 txcs_rd (void); +extern int32 csrs_rd (void); +extern int32 csrd_rd (void); +extern int32 csts_rd (void); +extern void iccs_wr (int32 dat); +extern void nicr_wr (int32 dat); +extern void todr_wr (int32 dat); +extern void rxcs_wr (int32 dat); +extern void txcs_wr (int32 dat); +extern void txdb_wr (int32 dat); +extern void csrs_wr (int32 dat); +extern void csts_wr (int32 dat); +extern void cstd_wr (int32 dat); +extern void init_mbus_tab (void); +extern void init_ubus_tab (void); +extern t_stat build_mbus_tab (DEVICE *dptr, DIB *dibp); +extern t_stat build_ubus_tab (DEVICE *dptr, DIB *dibp); +extern void uba_eval_int (void); +extern int32 uba_get_ubvector (int32 lvl); +extern void uba_ioreset (void); + +/* CMI data structures + + cmi_dev CMI device descriptor + cmi_unit CMI unit + cmi_reg CMI register list +*/ + +UNIT cmi_unit = { UDATA (NULL, 0, 0) }; + +REG cmi_reg[] = { + { HRDATA (NREQ14, nexus_req[0], 16) }, + { HRDATA (NREQ15, nexus_req[1], 16) }, + { HRDATA (NREQ16, nexus_req[2], 16) }, + { HRDATA (NREQ17, nexus_req[3], 16) }, + { HRDATA (CMIERR, cmi_err, 32) }, + { BRDATA (BOOTCMD, cpu_boot_cmd, 16, 8, CBUFSIZE), REG_HRO }, + { NULL } + }; + +DEVICE cmi_dev = { + "CMI", &cmi_unit, cmi_reg, NULL, + 1, 16, 16, 1, 16, 8, + NULL, NULL, &cmi_reset, + NULL, NULL, NULL, + NULL, 0 + }; + +/* Special boot command, overrides regular boot */ + +CTAB vax750_cmd[] = { + { "BOOT", &vax750_boot, RU_BOOT, + "bo{ot} {/R5:flg} boot device\n", &run_cmd_message }, + { NULL } + }; + +/* The VAX 11/750 has three sources of interrupts + + - internal device interrupts (CPU, console, clock) + - nexus interupts (e.g., memory controller, MBA, UBA) + - external device interrupts (Unibus) + + Internal devices vector to fixed SCB locations. + + Nexus interrupts vector to an SCB location based on this + formula: SCB_NEXUS + ((IPL - 0x14) * 0x40) + (TR# * 0x4) + + External device interrupts do not vector directly. + Instead, the interrupt handler for a given UBA IPL + reads a vector register that contains the Unibus vector + for that IPL. + + Find highest priority vectorable interrupt */ + +int32 eval_int (void) +{ +int32 ipl = PSL_GETIPL (PSL); +int32 i, t; + +static const int32 sw_int_mask[IPL_SMAX] = { + 0xFFFE, 0xFFFC, 0xFFF8, 0xFFF0, /* 0 - 3 */ + 0xFFE0, 0xFFC0, 0xFF80, 0xFF00, /* 4 - 7 */ + 0xFE00, 0xFC00, 0xF800, 0xF000, /* 8 - B */ + 0xE000, 0xC000, 0x8000 /* C - E */ + }; + +if (hlt_pin) /* hlt pin int */ + return IPL_HLTPIN; +if ((ipl < IPL_MEMERR) && mem_err) /* mem err int */ + return IPL_MEMERR; +if ((ipl < IPL_CRDERR) && crd_err) /* crd err int */ + return IPL_CRDERR; +if ((ipl < IPL_CLKINT) && tmr_int) /* clock int */ + return IPL_CLKINT; +uba_eval_int (); /* update UBA */ +for (i = IPL_HMAX; i >= IPL_HMIN; i--) { /* chk hwre int */ + if (i <= ipl) /* at ipl? no int */ + return 0; + if (nexus_req[i - IPL_HMIN]) /* req != 0? int */ + return i; + } +if ((ipl < IPL_TTINT) && (tti_int || tto_int || csi_int || cso_int)) /* console int */ + return IPL_TTINT; +if (ipl >= IPL_SMAX) /* ipl >= sw max? */ + return 0; +if ((t = SISR & sw_int_mask[ipl]) == 0) + return 0; /* eligible req */ +for (i = IPL_SMAX; i > ipl; i--) { /* check swre int */ + if ((t >> i) & 1) /* req != 0? int */ + return i; + } +return 0; +} + +/* Return vector for highest priority hardware interrupt at IPL lvl */ + +int32 get_vector (int32 lvl) +{ +int32 i, l; + +if (lvl == IPL_MEMERR) { /* mem error? */ + mem_err = 0; + return SCB_MEMERR; + } +if (lvl == IPL_CRDERR) { /* CRD error? */ + crd_err = 0; + return SCB_CRDERR; + } +if (lvl == IPL_CLKINT) { /* clock? */ + tmr_int = 0; /* clear req */ + return SCB_INTTIM; /* return vector */ + } +if (lvl > IPL_HMAX) { /* error req lvl? */ + ABORT (STOP_UIPL); /* unknown intr */ + } +if ((lvl <= IPL_HMAX) && (lvl >= IPL_HMIN)) { /* nexus? */ + l = lvl - IPL_HMIN; + if (nexus_req[l] & (1u << TR_UBA)) { /* unibus int? */ + nexus_req[l] = nexus_req[l] & ~(1u << TR_UBA); + return uba_get_ubvector(l); + } + for (i = 0; nexus_req[l] && (i < NEXUS_NUM); i++) { + if ((nexus_req[l] >> i) & 1) { + nexus_req[l] = nexus_req[l] & ~(1u << i); + return SCB_NEXUS + (l << 6) + (i << 2); /* return vector */ + } + } + } +if (lvl == IPL_TTINT) { /* console? */ + if (tti_int) { /* input? */ + tti_int = 0; /* clear req */ + return SCB_TTI; /* return vector */ + } + if (tto_int) { /* output? */ + tto_int = 0; /* clear req */ + return SCB_TTO; /* return vector */ + } + if (csi_int) { /* input? */ + csi_int = 0; /* clear req */ + return SCB_CSI; /* return vector */ + } + if (cso_int) { /* output? */ + cso_int = 0; /* clear req */ + return SCB_CSO; /* return vector */ + } + } +return 0; +} + +/* Read 750-specific IPR's */ + +int32 ReadIPR (int32 rg) +{ +int32 val; + +switch (rg) { + + case MT_ICCS: /* ICCS */ + val = iccs_rd (); + break; + + case MT_NICR: /* NICR */ + val = nicr_rd (); + break; + + case MT_ICR: /* ICR */ + val = icr_rd (FALSE); + break; + + case MT_TODR: /* TODR */ + val = todr_rd (); + break; + + case MT_ACCS: /* ACCS (not impl) */ + val = 0; + break; + + case MT_RXCS: /* RXCS */ + val = rxcs_rd (); + break; + + case MT_RXDB: /* RXDB */ + val = rxdb_rd (); + break; + + case MT_TXCS: /* TXCS */ + val = txcs_rd (); + break; + + case MT_CADR: /* CADR */ + val = cmi_cadr; + break; + + case MT_CAER: /* CAER (not impl) */ + val = 0; + break; + + case MT_MCESR: /* MCESR (not impl) */ + val = 0; + break; + + case MT_CMIE: /* CMIE */ + val = cmi_err; + break; + + case MT_CSRS: /* CSRS */ + val = csrs_rd (); + break; + + case MT_CSRD: /* CSRD */ + val = csrd_rd (); + break; + + case MT_CSTS: /* CSTS */ + val = csts_rd (); + break; + + case MT_TBDR: /* TBDR */ + val = 0; + break; + + case MT_SID: /* SID */ + val = VAX750_SID | VAX750_MICRO | VAX750_HWREV; + break; + + default: + RSVD_OPND_FAULT; + } + +return val; +} + +/* Write 750-specific IPR's */ + +void WriteIPR (int32 rg, int32 val) +{ +switch (rg) { + + case MT_ICCS: /* ICCS */ + iccs_wr (val); + break; + + case MT_NICR: /* NICR */ + nicr_wr (val); + break; + + case MT_TODR: /* TODR */ + todr_wr (val); + break; + + case MT_ACCS: /* ACCS (not impl) */ + break; + + case MT_RXCS: /* RXCS */ + rxcs_wr (val); + break; + + case MT_TXCS: /* TXCS */ + txcs_wr (val); + break; + + case MT_TXDB: /* TXDB */ + txdb_wr (val); + break; + + case MT_CADR: /* CADR */ + cmi_cadr = (val & 0x1); + break; + + case MT_CAER: /* CAER (not impl) */ + break; + + case MT_MCESR: /* MCESR (not impl) */ + break; + + case MT_IORESET: /* IORESET */ + uba_ioreset (); + break; + + case MT_CSRS: /* CSRS */ + csrs_wr (val); + break; + + case MT_CSTS: /* CSTS */ + csts_wr (val); + break; + + case MT_CSTD: /* CSTD */ + cstd_wr (val); + break; + + case MT_TBDR: /* TBDR */ + break; + + default: + RSVD_OPND_FAULT; + } + +return; +} + +/* ReadReg - read register space + + Inputs: + pa = physical address + lnt = length (BWLQ) + Output: + longword of data +*/ + +int32 ReadReg (int32 pa, int32 lnt) +{ +int32 nexus, val; + +if (ADDR_IS_REG (pa)) { /* reg space? */ + nexus = NEXUS_GETNEX (pa); /* get nexus */ + if (nexusR[nexus] && /* valid? */ + (nexusR[nexus] (&val, pa, lnt) == SCPE_OK)) { + SET_IRQL; + return val; + } + } +cmi_set_tmo (); /* timeout */ +MACH_CHECK (MCHK_BPE); /* machine check */ +return 0; +} + +/* WriteReg - write register space + + Inputs: + pa = physical address + val = data to write, right justified in 32b longword + lnt = length (BWLQ) + Outputs: + none +*/ + +void WriteReg (int32 pa, int32 val, int32 lnt) +{ +int32 nexus; + +if (ADDR_IS_REG (pa)) { /* reg space? */ + nexus = NEXUS_GETNEX (pa); /* get nexus */ + if (nexusW[nexus] && /* valid? */ + (nexusW[nexus] (val, pa, lnt) == SCPE_OK)) { + SET_IRQL; + return; + } + } +cmi_set_tmo (); /* timeout */ +mem_err = 1; /* interrupt */ +SET_IRQL; +return; +} + +/* Set CMI timeout */ + +void cmi_set_tmo () +{ +if ((cmi_err & CMIERR_ME) == 0) { /* not yet set? */ + if (mchk_ref == REF_V) /* virt? add mode */ + cmi_err |= CMIERR_REF | (PSL_GETCUR (PSL) << CMIERR_V_MODE); + cmi_err |= CMIERR_ME; /* set tmo flag */ + } +else cmi_err |= CMIERR_LEB; /* yes, multiple */ +return; +} + +/* Machine check + + Error status word format + <2:0> = ASTLVL + <3> = PME + <6:4> = arith trap code + Rest will be zero +*/ + +int32 machine_check (int32 p1, int32 opc, int32 cc, int32 delta) +{ +int32 acc, err; +err = (GET_TRAP (trpirq) << 4) | (pme << 3) | ASTLVL; /* error word */ +if (p1 == MCHK_BPE) /* bus error? */ + cc = intexc (SCB_MCHK, cc, 0, IE_EXC); /* take normal exception */ +else + cc = intexc (SCB_MCHK, cc, 0, IE_SVE); /* take severe exception */ +acc = ACC_MASK (KERN); /* in kernel mode */ +in_ie = 1; +SP = SP - 44; /* push 11 words */ +Write (SP, 40, L_LONG, WA); /* # bytes */ +Write (SP + 4, p1, L_LONG, WA); /* error code */ +Write (SP + 8, mchk_va, L_LONG, WA); /* VA register */ +Write (SP + 12, 0, L_LONG, WA); /* Fault PC */ +Write (SP + 16, 0, L_LONG, WA); /* MDR */ +Write (SP + 20, 0, L_LONG, WA); /* saved mode reg */ +Write (SP + 24, 0, L_LONG, WA); /* read lock timeout */ +Write (SP + 28, 0, L_LONG, WA); /* TB group parity error reg */ +Write (SP + 32, 0, L_LONG, WA); /* cache error reg */ +Write (SP + 36, cmi_err, L_LONG, WA); /* bus error reg */ +Write (SP + 40, 0, L_LONG, WA); /* MCESR */ +in_ie = 0; +cmi_err = cmi_err & ~CMIERR_ME; /* clr CMIERR etc */ +return cc; +} + +/* Console entry - only reached if CONHALT is set (AUTORESTART is set) */ + +int32 con_halt (int32 code, int32 cc) +{ +if ((cpu_boot_cmd[0] == 0) || /* saved boot cmd? */ + (vax750_boot_parse (0, cpu_boot_cmd) != SCPE_OK) || /* reparse the boot cmd */ + (reset_all (0) != SCPE_OK) || /* reset the world */ + (cpu_boot (0, NULL) != SCPE_OK)) /* set up boot code */ + ABORT (STOP_BOOT); /* any error? */ +printf ("Rebooting...\n"); +if (sim_log) + fprintf (sim_log, "Rebooting...\n"); +return cc; +} + +/* Special boot command - linked into SCP by initial reset + + Syntax: BOOT {/R5:val} + + Sets up R0-R5, calls SCP boot processor with effective BOOT CPU +*/ + +t_stat vax750_boot (int32 flag, char *ptr) +{ +t_stat r; + +r = vax750_boot_parse (flag, ptr); /* parse the boot cmd */ +if (r != SCPE_OK) /* error? */ + return r; +strncpy (cpu_boot_cmd, ptr, CBUFSIZE); /* save for reboot */ +return run_cmd (flag, "CPU"); +} + +/* Parse boot command, set up registers - also used on reset */ + +t_stat vax750_boot_parse (int32 flag, char *ptr) +{ +char gbuf[CBUFSIZE]; +char *slptr, *regptr; +int32 i, r5v, unitno; +DEVICE *dptr; +UNIT *uptr; +DIB *dibp; +uint32 ba; +t_stat r; + +regptr = get_glyph (ptr, gbuf, 0); /* get glyph */ +if ((slptr = strchr (gbuf, '/'))) { /* found slash? */ + regptr = strchr (ptr, '/'); /* locate orig */ + *slptr = 0; /* zero in string */ + } +dptr = find_unit (gbuf, &uptr); /* find device */ +if ((dptr == NULL) || (uptr == NULL)) + return SCPE_ARG; +dibp = (DIB *) dptr->ctxt; /* get DIB */ +if (dibp == NULL) + ba = 0; +else + ba = dibp->ba; +unitno = (int32) (uptr - dptr->units); +r5v = 0; +if ((strncmp (regptr, "/R5:", 4) == 0) || + (strncmp (regptr, "/R5=", 4) == 0) || + (strncmp (regptr, "/r5:", 4) == 0) || + (strncmp (regptr, "/r5=", 4) == 0)) { + r5v = (int32) get_uint (regptr + 4, 16, LMASK, &r); + if (r != SCPE_OK) + return r; + } +else + if (*regptr == '/') { + r5v = (int32) get_uint (regptr + 1, 16, LMASK, &r); + if (r != SCPE_OK) + return r; + } + else { + if (*regptr != 0) + return SCPE_ARG; + } +for (i = 0; boot_tab[i].name != NULL; i++) { + if (strcmp (dptr->name, boot_tab[i].name) == 0) { + R[0] = boot_tab[i].code; + if (dptr->flags & DEV_MBUS) { + R[1] = (NEXUSBASE + (TR_MBA0 * NEXUSSIZE)); + R[2] = unitno; + } + else { + R[1] = ba; + R[2] = (ba & UBADDRMASK); + } + R[3] = unitno; + R[4] = 0; + R[5] = r5v; + return SCPE_OK; + } + } +return SCPE_NOFNC; +} + +/* Bootstrap - finish up bootstrap process */ + +t_stat cpu_boot (int32 unitno, DEVICE *dptr) +{ +t_stat r; + +r = cpu_load_bootcode (BOOT_CODE_FILENAME, BOOT_CODE_ARRAY, BOOT_CODE_SIZE, FALSE, 0x200); +if (r != SCPE_OK) + return r; +SP = PC = 512; +return SCPE_OK; +} + +/* CMI reset */ + +t_stat cmi_reset (DEVICE *dptr) +{ +sim_vm_cmd = vax750_cmd; +cmi_err = CMIERR_EN; +cmi_cadr = 0; +return SCPE_OK; +} + +/* Show nexus */ + +t_stat show_nexus (FILE *st, UNIT *uptr, int32 val, void *desc) +{ +fprintf (st, "nexus=%d", val); +return SCPE_OK; +} + +/* Init nexus tables */ + +void init_nexus_tab (void) +{ +uint32 i; + +for (i = 0; i < NEXUS_NUM; i++) { + nexusR[i] = NULL; + nexusW[i] = NULL; + } +return; +} + +/* Build nexus tables + + Inputs: + dptr = pointer to device + dibp = pointer to DIB + Outputs: + status +*/ + + +t_stat build_nexus_tab (DEVICE *dptr, DIB *dibp) +{ +uint32 idx; + +if ((dptr == NULL) || (dibp == NULL)) + return SCPE_IERR; +idx = dibp->ba; +if (idx >= NEXUS_NUM) + return SCPE_IERR; +if ((nexusR[idx] && dibp->rd && /* conflict? */ + (nexusR[idx] != dibp->rd)) || + (nexusW[idx] && dibp->wr && + (nexusW[idx] != dibp->wr))) { + printf ("Nexus %s conflict at %d\n", sim_dname (dptr), dibp->ba); + if (sim_log) + fprintf (sim_log, "Nexus %s conflict at %d\n", sim_dname (dptr), dibp->ba); + return SCPE_STOP; + } +if (dibp->rd) /* set rd dispatch */ + nexusR[idx] = dibp->rd; +if (dibp->wr) /* set wr dispatch */ + nexusW[idx] = dibp->wr; +return SCPE_OK; +} + +/* Build dib_tab from device list */ + +t_stat build_dib_tab (void) +{ +uint32 i; +DEVICE *dptr; +DIB *dibp; +t_stat r; + +init_nexus_tab (); +init_ubus_tab (); +init_mbus_tab (); +for (i = 0; (dptr = sim_devices[i]) != NULL; i++) { /* loop thru dev */ + dibp = (DIB *) dptr->ctxt; /* get DIB */ + if (dibp && !(dptr->flags & DEV_DIS)) { /* defined, enabled? */ + if (dptr->flags & DEV_NEXUS) { /* Nexus? */ + if ((r = build_nexus_tab (dptr, dibp))) /* add to dispatch table */ + return r; + } + else if (dptr->flags & DEV_MBUS) { /* Massbus? */ + if ((r = build_mbus_tab (dptr, dibp))) + return r; + } + else { /* no, Unibus device */ + if ((r = build_ubus_tab (dptr, dibp))) /* add to dispatch tab */ + return r; + } /* end else */ + } /* end if enabled */ + } /* end for */ +return SCPE_OK; +} + +t_stat cpu_print_model (FILE *st) +{ +fprintf (st, "VAX 11/750"); +return SCPE_OK; +} + +t_stat cpu_model_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr) +{ +fprintf (st, "Initial memory size is 2MB.\n\n"); +fprintf (st, "The simulator is booted with the BOOT command:\n\n"); +fprintf (st, " sim> BO{OT} {/R5:flags}\n\n"); +fprintf (st, "where is one of:\n\n"); +fprintf (st, " RPn to boot from rpn\n"); +fprintf (st, " HKn to boot from hkn\n"); +fprintf (st, " RLn to boot from rln\n"); +fprintf (st, " RQn to boot from rqn\n"); +fprintf (st, " RQBn to boot from rqbn\n"); +fprintf (st, " RQCn to boot from rqcn\n"); +fprintf (st, " RQDn to boot from rqdn\n"); +fprintf (st, " TQn to boot from tqn\n"); +fprintf (st, " TDn to boot from tdn (TU58)\n\n"); +return SCPE_OK; +} diff --git a/VAX/vax750_defs.h b/VAX/vax750_defs.h new file mode 100644 index 00000000..bb8955a8 --- /dev/null +++ b/VAX/vax750_defs.h @@ -0,0 +1,416 @@ +/* vax750_defs.h: VAX 750 model-specific definitions file + + Copyright (c) 2010-2011, Matt Burke + This module incorporates code from SimH, Copyright (c) 2004-2008, Robert M Supnik + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name(s) of the author(s) shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from the author(s). + + 21-Oct-2012 MB First Version + + This file covers the VAX 11/750, the second VAX. + + System memory map + + 00 0000 - 7F FFFF main memory + 80 0000 - EF FFFF reserved + F0 0000 - F0 FFFF writeable control store + F1 0000 - F1 FFFF reserved + F2 0000 - F2 0010 memory controller + F2 0400 - F2 07FF bootstrap ROM + F2 8000 - F2 88FF Massbus adapter 0 + F2 A000 - F2 A8FF Massbus adapter 1 + F2 C000 - F2 C8FF Massbus adapter 2 + F3 0000 - F3 09FF Unibus adapter 0 + F3 2000 - F3 29FF Unibus adapter 1 +*/ + +#ifndef FULL_VAX +#define FULL_VAX 1 +#endif + +#ifndef _VAX_750_DEFS_H_ +#define _VAX_750_DEFS_H_ 1 + +/* Microcode constructs */ + +#define VAX750_SID (2 << 24) /* system ID */ +#define VAX750_MICRO (99 << 8) /* ucode revision */ +#define VAX750_HWREV (156) /* hw revision */ +#define CON_HLTPIN 0x0200 /* external CPU halt */ +#define CON_HLTINS 0x0600 /* HALT instruction */ +#define MCHK_CSPE 0x01 /* control store parity error */ +#define MCHK_BPE 0x02 /* bus error or tb/cache parity error */ +#define VER_FPLA 0x0C /* FPLA version */ +#define VER_WCSP (VER_FPLA) /* WCS primary version */ +#define VER_WCSS 0x12 /* WCS secondary version */ +#define VER_PCS ((VER_WCSS >> 4) & 0x3) /* PCS version */ + +/* Interrupts */ + +#define IPL_HMAX 0x17 /* highest hwre level */ +#define IPL_HMIN 0x14 /* lowest hwre level */ +#define IPL_HLVL (IPL_HMAX - IPL_HMIN + 1) /* # hardware levels */ +#define IPL_SMAX 0xF /* highest swre level */ + +/* Nexus constants */ + +#define NEXUS_NUM 16 /* number of nexus */ +#define MCTL_NUM 2 /* number of mem ctrl */ +#define MBA_NUM 2 /* number of MBA's */ +#define TR_MCTL 0 /* nexus assignments */ +#define TR_MBA0 4 +#define TR_MBA1 5 +#define TR_UBA 8 +#define TR_CI 15 +#define NEXUS_HLVL (IPL_HMAX - IPL_HMIN + 1) +#define SCB_NEXUS 0x100 /* nexus intr base */ +#define SBI_FAULTS 0xFC000000 /* SBI fault flags */ + +/* Internal I/O interrupts - relative except for clock and console */ + +#define IPL_CLKINT 0x18 /* clock IPL */ +#define IPL_TTINT 0x14 /* console IPL */ + +#define IPL_MCTL0 (0x15 - IPL_HMIN) +#define IPL_MCTL1 (0x15 - IPL_HMIN) +#define IPL_UBA (0x15 - IPL_HMIN) +#define IPL_MBA0 (0x15 - IPL_HMIN) +#define IPL_MBA1 (0x15 - IPL_HMIN) +#define IPL_CI (0x15 - IPL_HMIN) + +/* Nexus interrupt macros */ + +#define SET_NEXUS_INT(dv) nexus_req[IPL_##dv] |= (1 << TR_##dv) +#define CLR_NEXUS_INT(dv) nexus_req[IPL_##dv] &= ~(1 << TR_##dv) + +/* Machine specific IPRs */ + +#define MT_CSRS 28 /* Console storage */ +#define MT_CSRD 29 +#define MT_CSTS 30 +#define MT_CSTD 31 +#define MT_CMIE 23 /* CMI error */ +#define MT_TBDR 36 /* TB disable */ +#define MT_CADR 37 /* Cache disable */ +#define MT_MCESR 38 /* MCHK err sts */ +#define MT_CAER 39 /* Cache error */ +#define MT_ACCS 40 /* FPA control */ +#define MT_IORESET 55 /* Unibus Init */ +#define MT_MAX 63 /* last valid IPR */ + +/* Machine specific reserved operand tests */ + +/* 780 microcode patch 37 - only test LR<23:0> for appropriate length */ + +#define ML_LR_TEST(r) if (((uint32)((r) & 0xFFFFFF)) > 0x200000) RSVD_OPND_FAULT + +/* 780 microcode patch 38 - only test PxBR<31>=1, PxBR<30> = 0, and xBR<1:0> = 0 */ + +#define ML_PXBR_TEST(r) if (((((uint32)(r)) & 0x80000000) == 0) || \ + ((((uint32)(r)) & 0x40000003) != 0)) RSVD_OPND_FAULT +#define ML_SBR_TEST(r) if ((((uint32)(r)) & 0xC0000003) != 0) RSVD_OPND_FAULT + +/* 780 microcode patch 78 - only test xCBB<1:0> = 0 */ + +#define ML_PA_TEST(r) if ((((uint32)(r)) & 0x00000003) != 0) RSVD_OPND_FAULT + +#define LP_AST_TEST(r) if ((r) > AST_MAX) RSVD_OPND_FAULT +#define LP_MBZ84_TEST(r) if ((((uint32)(r)) & 0xF8C00000) != 0) RSVD_OPND_FAULT +#define LP_MBZ92_TEST(r) if ((((uint32)(r)) & 0x7FC00000) != 0) RSVD_OPND_FAULT + +/* Memory */ + +#define MAXMEMWIDTH 21 /* max mem, 16k chips */ +#define MAXMEMSIZE (1 << MAXMEMWIDTH) +#define MAXMEMWIDTH_X 23 /* max mem, 64k chips */ +#define MAXMEMSIZE_X (1 << MAXMEMWIDTH_X) +#define INITMEMSIZE (1 << MAXMEMWIDTH) /* initial memory size */ +#define MEMSIZE (cpu_unit.capac) +#define ADDR_IS_MEM(x) (((uint32) (x)) < MEMSIZE) +#define MEM_MODIFIERS { UNIT_MSIZE, (1u << 20), NULL, "1M", &cpu_set_size }, \ + { UNIT_MSIZE, (1u << 21), NULL, "2M", &cpu_set_size }, \ + { UNIT_MSIZE, (1u << 22), NULL, "4M", &cpu_set_size }, \ + { UNIT_MSIZE, (1u << 23), NULL, "8M", &cpu_set_size } +#define CPU_MODEL_MODIFIERS \ + { MTAB_XTD|MTAB_VDV, 0, "MODEL", NULL, \ + NULL, &cpu_show_model }, + +/* Unibus I/O registers */ + +#define UBADDRWIDTH 18 /* Unibus addr width */ +#define UBADDRSIZE (1u << UBADDRWIDTH) /* Unibus addr length */ +#define UBADDRMASK (UBADDRSIZE - 1) /* Unibus addr mask */ +#define IOPAGEAWIDTH 13 /* IO addr width */ +#define IOPAGESIZE (1u << IOPAGEAWIDTH) /* IO page length */ +#define IOPAGEMASK (IOPAGESIZE - 1) /* IO addr mask */ +#define UBADDRBASE 0xFC0000 /* Unibus addr base */ +#define IOPAGEBASE 0xFFE000 /* IO page base */ +#define ADDR_IS_IO(x) ((((uint32) (x)) >= UBADDRBASE) && \ + (((uint32) (x)) < (UBADDRBASE + UBADDRSIZE))) +#define ADDR_IS_IOP(x) (((uint32) (x)) >= IOPAGEBASE) + +/* Nexus register space */ + +#define REGAWIDTH 19 /* REG addr width */ +#define REG_V_NEXUS 13 /* nexus number */ +#define REG_M_NEXUS 0xF +#define REG_V_OFS 2 /* register number */ +#define REG_M_OFS 0x7FF +#define REGSIZE (1u << REGAWIDTH) /* REG length */ +#define REGBASE 0xF00000 /* REG addr base */ +#define ADDR_IS_REG(x) ((((uint32) (x)) >= REGBASE) && \ + (((uint32) (x)) < (REGBASE + REGSIZE))) +#define NEXUSBASE (REGBASE + 0x20000) +#define NEXUSSIZE 0x2000 +#define NEXUS_GETNEX(x) (((x) >> REG_V_NEXUS) & REG_M_NEXUS) +#define NEXUS_GETOFS(x) (((x) >> REG_V_OFS) & REG_M_OFS) + +/* ROM address space in memory controllers */ + +#define ROMAWIDTH 12 /* ROM addr width */ +#define ROMSIZE (1u << ROMAWIDTH) /* ROM size */ +#define ROMBASE (REGBASE + (TR_MCTL << REG_V_NEXUS) + 0x400) +#define ADDR_IS_ROM(x) ((((uint32) (x)) >= ROMBASE) && \ + (((uint32) (x)) < (ROMBASE + ROMSIZE))) + +/* Other address spaces */ + +#define ADDR_IS_CDG(x) (0) +#define ADDR_IS_NVR(x) (0) + +/* Unibus I/O modes */ + +#define READ 0 /* PDP-11 compatibility */ +#define WRITE (L_WORD) +#define WRITEB (L_BYTE) + +/* Common CSI flags */ + +#define CSR_V_GO 0 /* go */ +#define CSR_V_IE 6 /* interrupt enable */ +#define CSR_V_DONE 7 /* done */ +#define CSR_V_BUSY 11 /* busy */ +#define CSR_V_ERR 15 /* error */ +#define CSR_GO (1u << CSR_V_GO) +#define CSR_IE (1u << CSR_V_IE) +#define CSR_DONE (1u << CSR_V_DONE) +#define CSR_BUSY (1u << CSR_V_BUSY) +#define CSR_ERR (1u << CSR_V_ERR) + +/* Timers */ + +#define TMR_CLK 0 /* 100Hz clock */ + +/* I/O system definitions */ + +#define DZ_MUXES 4 /* max # of DZV muxes */ +#define DZ_LINES 8 /* lines per DZV mux */ +#define VH_MUXES 4 /* max # of DHQ muxes */ +#define DLX_LINES 16 /* max # of KL11/DL11's */ +#define DCX_LINES 16 /* max # of DC11's */ +#define MT_MAXFR (1 << 16) /* magtape max rec */ + +#define DEV_V_UBUS (DEV_V_UF + 0) /* Unibus */ +#define DEV_V_MBUS (DEV_V_UF + 1) /* Massbus */ +#define DEV_V_NEXUS (DEV_V_UF + 2) /* Nexus */ +#define DEV_V_CI (DEV_V_UF + 3) /* CI */ +#define DEV_V_FFUF (DEV_V_UF + 4) /* first free flag */ +#define DEV_UBUS (1u << DEV_V_UBUS) +#define DEV_MBUS (1u << DEV_V_MBUS) +#define DEV_NEXUS (1u << DEV_V_NEXUS) +#define DEV_CI (1u << DEV_V_CI) +#define DEV_QBUS (0) +#define DEV_Q18 (0) + +#define UNIBUS TRUE /* Unibus only */ + +#define DEV_RDX 16 /* default device radix */ + +/* Device information block + + For Massbus devices, + ba = Massbus number + lnt = Massbus ctrl type + ack[0] = abort routine + + For Nexus devices, + ba = Nexus number + lnt = number of consecutive nexi */ + +#define VEC_DEVMAX 4 /* max device vec */ + +typedef struct { + uint32 ba; /* base addr */ + uint32 lnt; /* length */ + t_stat (*rd)(int32 *dat, int32 ad, int32 md); + t_stat (*wr)(int32 dat, int32 ad, int32 md); + int32 vnum; /* vectors: number */ + int32 vloc; /* locator */ + int32 vec; /* value */ + int32 (*ack[VEC_DEVMAX])(void); /* ack routine */ + } DIB; + +/* Unibus I/O page layout - see pdp11_ui_lib.c for address layout details + Massbus devices (RP, TU) do not appear in the Unibus IO page */ + +#define IOBA_AUTO (0) /* Assigned by Auto Configure */ + + +/* Interrupt assignments; within each level, priority is right to left */ + +#define INT_V_DZRX 0 /* BR5 */ +#define INT_V_DZTX 1 +#define INT_V_HK 2 +#define INT_V_RL 3 +#define INT_V_RQ 4 +#define INT_V_TQ 5 +#define INT_V_TS 6 +#define INT_V_RY 7 +#define INT_V_XU 8 +#define INT_V_DMCRX 9 +#define INT_V_DMCTX 10 + +#define INT_V_LPT 0 /* BR4 */ +#define INT_V_PTR 1 +#define INT_V_PTP 2 +#define INT_V_CR 3 +#define INT_V_VHRX 4 +#define INT_V_VHTX 5 + +#define INT_DZRX (1u << INT_V_DZRX) +#define INT_DZTX (1u << INT_V_DZTX) +#define INT_HK (1u << INT_V_HK) +#define INT_RL (1u << INT_V_RL) +#define INT_RQ (1u << INT_V_RQ) +#define INT_TQ (1u << INT_V_TQ) +#define INT_TS (1u << INT_V_TS) +#define INT_RY (1u << INT_V_RY) +#define INT_XU (1u << INT_V_XU) +#define INT_LPT (1u << INT_V_LPT) +#define INT_VHRX (1u << INT_V_VHRX) +#define INT_VHTX (1u << INT_V_VHTX) +#define INT_PTR (1u << INT_V_PTR) +#define INT_PTP (1u << INT_V_PTP) +#define INT_CR (1u << INT_V_CR) +#define INT_DMCRX (1u << INT_V_DMCRX) +#define INT_DMCTX (1u << INT_V_DMCTX) + +#define IPL_DZRX (0x15 - IPL_HMIN) +#define IPL_DZTX (0x15 - IPL_HMIN) +#define IPL_HK (0x15 - IPL_HMIN) +#define IPL_RL (0x15 - IPL_HMIN) +#define IPL_RQ (0x15 - IPL_HMIN) +#define IPL_TQ (0x15 - IPL_HMIN) +#define IPL_TS (0x15 - IPL_HMIN) +#define IPL_RY (0x15 - IPL_HMIN) +#define IPL_XU (0x15 - IPL_HMIN) +#define IPL_LPT (0x14 - IPL_HMIN) +#define IPL_PTR (0x14 - IPL_HMIN) +#define IPL_PTP (0x14 - IPL_HMIN) +#define IPL_CR (0x14 - IPL_HMIN) +#define IPL_VHRX (0x14 - IPL_HMIN) +#define IPL_VHTX (0x14 - IPL_HMIN) +#define IPL_DMCRX (0x15 - IPL_HMIN) +#define IPL_DMCTX (0x15 - IPL_HMIN) + +/* Device vectors */ + +#define VEC_AUTO (0) /* Assigned by Auto Configure */ +#define VEC_FLOAT (0) /* Assigned by Auto Configure */ + +#define VEC_QBUS 0 +#define VEC_Q 0x200 + +/* Interrupt macros */ + +#define IVCL(dv) ((IPL_##dv * 32) + INT_V_##dv) +#define NVCL(dv) ((IPL_##dv * 32) + TR_##dv) +#define IREQ(dv) int_req[IPL_##dv] +#define SET_INT(dv) int_req[IPL_##dv] = int_req[IPL_##dv] | (INT_##dv) +#define CLR_INT(dv) int_req[IPL_##dv] = int_req[IPL_##dv] & ~(INT_##dv) +#define IORETURN(f,v) ((f)? (v): SCPE_OK) /* cond error return */ + +/* Logging */ + +#define LOG_CPU_I 0x1 /* intexc */ +#define LOG_CPU_R 0x2 /* REI */ +#define LOG_CPU_P 0x4 /* context */ + +/* Massbus definitions */ + +#define MBA_RP (TR_MBA0 - TR_MBA0) /* MBA for RP */ +#define MBA_TU (TR_MBA1 - TR_MBA0) /* MBA for TU */ +#define MBA_RMASK 0x1F /* max 32 reg */ +#define MBE_NXD 1 /* nx drive */ +#define MBE_NXR 2 /* nx reg */ +#define MBE_GOE 3 /* err on GO */ + +/* Boot definitions */ + +#define BOOT_MB 0 /* device codes */ +#define BOOT_HK 1 /* for VMB */ +#define BOOT_RL 2 +#define BOOT_UDA 17 +#define BOOT_TK 18 +#define BOOT_CI 32 +#define BOOT_TD 64 + +/* Function prototypes for virtual memory interface */ + +int32 Read (uint32 va, int32 lnt, int32 acc); +void Write (uint32 va, int32 val, int32 lnt, int32 acc); + +/* Function prototypes for physical memory interface (inlined) */ + +SIM_INLINE int32 ReadB (uint32 pa); +SIM_INLINE int32 ReadW (uint32 pa); +SIM_INLINE int32 ReadL (uint32 pa); +SIM_INLINE int32 ReadLP (uint32 pa); +SIM_INLINE void WriteB (uint32 pa, int32 val); +SIM_INLINE void WriteW (uint32 pa, int32 val); +SIM_INLINE void WriteL (uint32 pa, int32 val); +void WriteLP (uint32 pa, int32 val); + +/* Function prototypes for I/O */ + +int32 Map_ReadB (uint32 ba, int32 bc, uint8 *buf); +int32 Map_ReadW (uint32 ba, int32 bc, uint16 *buf); +int32 Map_WriteB (uint32 ba, int32 bc, uint8 *buf); +int32 Map_WriteW (uint32 ba, int32 bc, uint16 *buf); + +int32 mba_rdbufW (uint32 mbus, int32 bc, uint16 *buf); +int32 mba_wrbufW (uint32 mbus, int32 bc, uint16 *buf); +int32 mba_chbufW (uint32 mbus, int32 bc, uint16 *buf); +int32 mba_get_bc (uint32 mbus); +void mba_upd_ata (uint32 mbus, uint32 val); +void mba_set_exc (uint32 mbus); +void mba_set_don (uint32 mbus); +void mba_set_enbdis (uint32 mbus, t_bool dis); +t_stat mba_show_num (FILE *st, UNIT *uptr, int32 val, void *desc); + +t_stat show_nexus (FILE *st, UNIT *uptr, int32 val, void *desc); + +void sbi_set_errcnf (void); + +#include "pdp11_io_lib.h" + +#endif diff --git a/VAX/vax750_mem.c b/VAX/vax750_mem.c new file mode 100644 index 00000000..15f60b26 --- /dev/null +++ b/VAX/vax750_mem.c @@ -0,0 +1,206 @@ +/* vax750_mem.c: VAX 11/750 memory controllers + + Copyright (c) 2010-2012, Matt Burke + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHOR BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name of the author shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from the author. + + mctl MS750 memory controller + + 21-Oct-2012 MB First Version +*/ + +#include "vax_defs.h" + +/* Memory adapter register 0 */ + +#define MCSR0_OF 0x00 +#define MCSR0_ES 0x0000007F /* Error syndrome */ +#define MCSR0_V_EP 9 +#define MCSR0_M_EP 0x7FFF +#define MCSR0_EP (MCSR0_M_EP << MCSR0_V_EP) /* Error page */ +#define MCSR0_CRD 0x20000000 /* Corrected read data */ +#define MCSR0_RDSH 0x40000000 /* Read data subs high */ +#define MCSR0_RDS 0x80000000 /* Read data substitute */ +#define MCSR0_RS (MCSR0_CRD | MCSR0_RDSH | MCSR0_RDS) + +/* Memory adapter register 1 */ + +#define MCSR1_OF 0x01 +#define MCSR1_CS 0x0000007F /* Check syndrome */ +#define MCSR1_V_EP 9 +#define MCSR1_M_EP 0x7FFF +#define MCSR1_EP (MCSR1_M_EP << MCSR1_V_EP) /* Page mode address */ +#define MCSR1_ECCD 0x02000000 /* ECC disable */ +#define MCSR1_DIAG 0x04000000 /* Diag mode */ +#define MCSR1_PM 0x08000000 /* Page mode */ +#define MCSR1_CRE 0x10000000 /* CRD enable */ +#define MCSR1_RW (MCSR1_CS | MCSR1_ECCD | MCSR1_DIAG | \ + MCSR1_PM | MCSR1_CRE) + +/* Memory adapter register 2 */ + +#define MCSR2_OF 0x02 +#define MCSR2_M_MAP 0xFFFF /* Memory present */ +#define MCSR2_INIT 0x00010000 /* Cold/warm restart flag */ +#define MCSR2_V_SA 17 +#define MCSR2_M_SA 0x7F /* Start address */ +#define MCSR2_V_CS 24 +#define MCSR2_CS (1u << MCSR2_V_CS) /* Chip size */ +#define MCSR2_MBZ 0xFF000000 + +/* Debug switches */ + +#define MCTL_DEB_RRD 0x01 /* reg reads */ +#define MCTL_DEB_RWR 0x02 /* reg writes */ + +#define MEM_SIZE_16K (1u << 17) /* Board size (16k chips) */ +#define MEM_SIZE_64K (1u << 19) /* Board size (64k chips) */ +#define MEM_BOARD_MASK(x,y) ((1u << (uint32)(x/y)) - 1) +#define MEM_64K_MASK 0x5555 + +extern UNIT cpu_unit; + +uint32 mcsr0 = 0; +uint32 mcsr1 = 0; +uint32 mcsr2 = 0; + +t_stat mctl_reset (DEVICE *dptr); +t_stat mctl_rdreg (int32 *val, int32 pa, int32 mode); +t_stat mctl_wrreg (int32 val, int32 pa, int32 mode); + +/* MCTL data structures + + mctl_dev MCTL device descriptor + mctl_unit MCTL unit + mctl_reg MCTL register list +*/ + +DIB mctl_dib = { TR_MCTL, 0, &mctl_rdreg, &mctl_wrreg, 0 }; + +UNIT mctl_unit = { UDATA (NULL, 0, 0) }; + +REG mctl_reg[] = { + { NULL } + }; + +MTAB mctl_mod[] = { + { MTAB_XTD|MTAB_VDV, TR_MCTL, "NEXUS", NULL, + NULL, &show_nexus }, + { 0 } + }; + +DEBTAB mctl_deb[] = { + { "REGREAD", MCTL_DEB_RRD }, + { "REGWRITE", MCTL_DEB_RWR }, + { NULL, 0 } + }; + +DEVICE mctl_dev = { + "MCTL", &mctl_unit, mctl_reg, mctl_mod, + 1, 16, 16, 1, 16, 8, + NULL, NULL, &mctl_reset, + NULL, NULL, NULL, + &mctl_dib, DEV_NEXUS | DEV_DEBUG, 0, + mctl_deb, 0, 0 + }; + +/* Memory controller register read */ + +t_stat mctl_rdreg (int32 *val, int32 pa, int32 lnt) +{ +int32 ofs; +ofs = NEXUS_GETOFS (pa); /* get offset */ + +switch (ofs) { /* case on offset */ + + case MCSR0_OF: /* CSR0 */ + *val = mcsr0; + break; + + case MCSR1_OF: /* CSR1 */ + *val = mcsr1; + break; + + case MCSR2_OF: /* CSR2 */ + *val = mcsr2 & ~MCSR2_MBZ; + break; + + default: + return SCPE_NXM; + } + +if (DEBUG_PRI (mctl_dev, MCTL_DEB_RRD)) + fprintf (sim_deb, ">>MCTL: reg %d read, value = %X\n", ofs, *val); + +return SCPE_OK; +} + +/* Memory controller register write */ + +t_stat mctl_wrreg (int32 val, int32 pa, int32 lnt) +{ +int32 ofs; + +ofs = NEXUS_GETOFS (pa); /* get offset */ + +switch (ofs) { /* case on offset */ + + case MCSR0_OF: /* CSR0 */ + mcsr0 = mcsr0 & ~(MCSR0_RS & val); + break; + + case MCSR1_OF: /* CSR1 */ + mcsr1 = val & MCSR1_RW; + break; + + case MCSR2_OF: /* CSR2 */ + break; + + default: + return SCPE_NXM; + } + +if (DEBUG_PRI (mctl_dev, MCTL_DEB_RWR)) + fprintf (sim_deb, ">>MCTL: reg %d write, value = %X\n", ofs, val); + +return SCPE_OK; +} + +/* Used by CPU */ + +void rom_wr_B (int32 pa, int32 val) +{ +return; +} + +/* Memory controller reset */ + +t_stat mctl_reset (DEVICE *dptr) +{ +mcsr0 = 0; +mcsr1 = 0; +if (MEMSIZE > MAXMEMSIZE) /* More than 2MB? */ + mcsr2 = MCSR2_INIT | (MEM_BOARD_MASK(MEMSIZE, MEM_SIZE_64K) & MEM_64K_MASK) | MCSR2_CS; /* Use 64k chips */ +else + mcsr2 = MCSR2_INIT | MEM_BOARD_MASK(MEMSIZE, MEM_SIZE_16K); /* Use 16k chips */ +return SCPE_OK; +} diff --git a/VAX/vax750_stddev.c b/VAX/vax750_stddev.c new file mode 100644 index 00000000..e1ea0891 --- /dev/null +++ b/VAX/vax750_stddev.c @@ -0,0 +1,1188 @@ +/* vax750_stddev.c: VAX 11/750 standard I/O devices + + Copyright (c) 2010-2012, Matt Burke + This module incorporates code from SimH, Copyright (c) 1998-2011, Robert M Supnik + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name(s) of the author(s) shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from the author(s). + + tti console input + tto console output + td console TU58 + todr TODR clock + tmr interval timer + + 22-Oct-12 MP Generalized setting TODR for all OSes. + Unbound the TODR value from the 100hz clock tick + interrupt. TODR now behaves like the original + battery backed-up clock and runs with the wall + clock, not the simulated instruction clock. + Two operational modes are available: + - Default VMS mode, which is similar to the previous + behavior in that without initializing the TODR it + would default to the value VMS would set it to if + VMS knew the correct time. This would be correct + almost all the time unless a VMS disk hadn't been + booted from for more than a year. This mode + produces strange time results for non VMS OSes on + each system boot. + - OS Agnostic mode. This mode behaves precisely like + the VAX780 TODR and works correctly for all OSes. + This mode is enabled by attaching the TODR to a + battery backup state file for the TOY clock + (i.e. sim> attach TODR TOY_CLOCK). When operating + in OS Agnostic mode, the TODR will initially start + counting from 0 and be adjusted differently when an + OS specifically writes to the TODR. VMS will prompt + to set the time on each boot (if the TODR value is + less than about 1 month) unless the SYSGEN + parameter TIMEPROMPTWAIT is set to 0. + 21-Oct-2012 MB First Version +*/ + +#include "vax_defs.h" +#include "sim_tmxr.h" +#include + +/* Terminal definitions */ + +#define RXCS_RD (CSR_DONE + CSR_IE) /* terminal input */ +#define RXCS_WR (CSR_IE) +#define RXDB_ERR 0x8000 /* error */ +#define RXDB_OVR 0x4000 /* overrun */ +#define RXDB_FRM 0x2000 /* framing error */ +#define TXCS_RD (CSR_DONE + CSR_IE) /* terminal output */ +#define TXCS_WR (CSR_IE) +#define TXDB_V_SEL 8 /* unit select */ +#define TXDB_M_SEL 0xF +#define TXDB_MISC 0xF /* console misc */ +#define MISC_MASK 0xFF /* console data mask */ +#define MISC_SWDN 0x1 /* software done */ +#define MISC_BOOT 0x2 /* reboot */ +#define MISC_CLWS 0x3 /* clear warm start */ +#define MISC_CLCS 0x4 /* clear cold start */ +#define TXDB_SEL (TXDB_M_SEL << TXDB_V_SEL) /* non-terminal */ +#define TXDB_GETSEL(x) (((x) >> TXDB_V_SEL) & TXDB_M_SEL) +#define CSTS_BRK 0x1 +#define CSTS_RD (CSR_DONE + CSR_IE + CSTS_BRK) /* terminal output */ +#define CSTS_WR (CSR_IE + CSTS_BRK) + +/* Clock definitions */ + +#define TMR_CSR_ERR 0x80000000 /* error W1C */ +#define TMR_CSR_DON 0x00000080 /* done W1C */ +#define TMR_CSR_IE 0x00000040 /* int enb RW */ +#define TMR_CSR_SGL 0x00000020 /* single WO */ +#define TMR_CSR_XFR 0x00000010 /* xfer WO */ +#define TMR_CSR_RUN 0x00000001 /* run RW */ +#define TMR_CSR_RD (TMR_CSR_W1C | TMR_CSR_WR) +#define TMR_CSR_W1C (TMR_CSR_ERR | TMR_CSR_DON) +#define TMR_CSR_WR (TMR_CSR_IE | TMR_CSR_RUN) +#define TMR_INC 10000 /* usec/interval */ +#define CLK_DELAY 5000 /* 100 Hz */ +#define TMXR_MULT 1 /* 100 Hz */ + +/* TU58 definitions */ + +#define UNIT_V_WLK (UNIT_V_UF) /* write locked */ +#define UNIT_WLK (1u << UNIT_V_UF) +#define UNIT_WPRT (UNIT_WLK | UNIT_RO) /* write protect */ + +#define TD_NUMBLK 512 /* blocks/tape */ +#define TD_NUMBY 512 /* bytes/block */ +#define TD_SIZE (TD_NUMBLK * TD_NUMBY) /* bytes/tape */ + +#define TD_OPDAT 001 /* Data */ +#define TD_OPCMD 002 /* Command */ +#define TD_OPINI 004 /* INIT */ +#define TD_OPBOO 010 /* Bootstrap */ +#define TD_OPCNT 020 /* Continue */ +#define TD_OPXOF 023 /* XOFF */ + +#define TD_CMDNOP 0000 /* NOP */ +#define TD_CMDINI 0001 /* INIT */ +#define TD_CMDRD 0002 /* Read */ +#define TD_CMDWR 0003 /* Write */ +#define TD_CMDPOS 0005 /* Position */ +#define TD_CMDDIA 0007 /* Diagnose */ +#define TD_CMDGST 0010 /* Get Status */ +#define TD_CMDSST 0011 /* Set Status */ +#define TD_CMDMRSP 0012 /* MRSP Request */ +#define TD_CMDEND 0100 /* END */ + +#define TD_STSOK 0000 /* Normal success */ +#define TD_STSRTY 0001 /* Success with retries */ +#define TD_STSFAIL 0377 /* Failed selftest */ +#define TD_STSPO 0376 /* Partial operation (end of medium) */ +#define TD_STSBUN 0370 /* Bad unit number */ +#define TD_STSNC 0367 /* No cartridge */ +#define TD_STSWP 0365 /* Write protected */ +#define TD_STSDCE 0357 /* Data check error */ +#define TD_STSSE 0340 /* Seek error (block not found) */ +#define TD_STSMS 0337 /* Motor stopped */ +#define TD_STSBOP 0320 /* Bad opcode */ +#define TD_STSBBN 0311 /* Bad block number (>511) */ + +#define TD_GETOPC 0 /* get opcode state */ +#define TD_GETLEN 1 /* get length state */ +#define TD_GETDATA 2 /* get data state */ + +#define TD_IDLE 0 /* idle state */ +#define TD_READ 1 /* read */ +#define TD_READ1 2 /* fill buffer */ +#define TD_READ2 3 /* empty buffer */ +#define TD_WRITE 4 /* write */ +#define TD_WRITE1 5 /* write */ +#define TD_WRITE2 6 /* write */ +#define TD_END 7 /* empty buffer */ +#define TD_END1 8 /* empty buffer */ +#define TD_INIT 9 /* empty buffer */ + +int32 tti_csr = 0; /* control/status */ +int32 tti_buf = 0; /* buffer */ +int32 tti_int = 0; /* interrupt */ +int32 tto_csr = 0; /* control/status */ +int32 tto_buf = 0; /* buffer */ +int32 tto_int = 0; /* interrupt */ + +int32 csi_csr = 0; /* control/status */ +int32 csi_buf = 0; /* buffer */ +int32 csi_int = 0; /* interrupt */ +int32 cso_csr = 0; /* control/status */ +int32 cso_buf = 0; /* buffer */ +int32 cso_int = 0; /* interrupt */ +int32 cso_state = 0; /* state */ + +int32 tmr_iccs = 0; /* interval timer csr */ +uint32 tmr_icr = 0; /* curr interval */ +uint32 tmr_nicr = 0; /* next interval */ +uint32 tmr_inc = 0; /* timer increment */ +int32 tmr_sav = 0; /* timer save */ +int32 tmr_int = 0; /* interrupt */ +int32 tmr_use_100hz = 1; /* use 100Hz for timer */ +int32 clk_tps = 100; /* ticks/second */ +int32 tmxr_poll = CLK_DELAY * TMXR_MULT; /* term mux poll */ +int32 tmr_poll = CLK_DELAY; /* pgm timer poll */ +int32 todr_reg = 0; /* TODR register */ +struct todr_battery_info { + uint32 toy_gmtbase; /* GMT base of set value */ + uint32 toy_gmtbasemsec; /* The milliseconds of the set value */ + }; +typedef struct todr_battery_info TOY; + +int32 td_swait = 100; /* seek, per block */ +int32 td_cwait = 150; /* command time */ +int32 td_xwait = 180; /* tr set time */ +int32 td_iwait = 180; /* init time */ +uint8 td_ibuf[TD_NUMBY] = { 0 }; /* input buffer */ +int32 td_ibptr = 0; /* input buffer pointer */ +int32 td_ilen = 0; /* input length */ +uint8 td_obuf[TD_NUMBY] = { 0 }; /* output buffer */ +int32 td_obptr = 0; /* output buffer pointer */ +int32 td_olen = 0; /* output length */ +int32 td_block = 0; /* current block number */ +int32 td_txsize = 0; /* remaining transfer size */ +int32 td_offset = 0; /* offset into current transfer */ +int32 td_state = TD_IDLE; +int32 td_ecode = 0; /* end packet success code */ + +extern jmp_buf save_env; + +t_stat tti_svc (UNIT *uptr); +t_stat tto_svc (UNIT *uptr); +t_stat clk_svc (UNIT *uptr); +t_stat tmr_svc (UNIT *uptr); +t_stat tti_reset (DEVICE *dptr); +t_stat tto_reset (DEVICE *dptr); +t_stat clk_reset (DEVICE *dptr); +t_stat clk_attach (UNIT *uptr, char *cptr); +t_stat clk_detach (UNIT *uptr); +t_stat tmr_reset (DEVICE *dptr); +t_stat td_svc (UNIT *uptr); +t_stat td_reset (DEVICE *dptr); +int32 icr_rd (t_bool interp); +void tmr_incr (uint32 inc); +void tmr_sched (void); +t_stat todr_resync (void); +t_stat txdb_misc_wr (int32 data); +void td_process_packet(); +t_bool td_test_xfr (UNIT *uptr, int32 state); + +extern int32 con_halt (int32 code, int32 cc); + +/* TTI data structures + + tti_dev TTI device descriptor + tti_unit TTI unit descriptor + tti_reg TTI register list +*/ + +UNIT tti_unit = { UDATA (&tti_svc, TT_MODE_8B, 0), 0 }; + +REG tti_reg[] = { + { HRDATAD (RXDB, tti_buf, 16, "last data item processed") }, + { HRDATAD (RXCS, tti_csr, 16, "control/status register") }, + { FLDATAD (INT, tti_int, 0, "interrupt pending flag") }, + { FLDATAD (DONE, tti_csr, CSR_V_DONE, "device done flag (CSR<7>)") }, + { FLDATAD (IE, tti_csr, CSR_V_IE, "interrupt enable flag (CSR<6>)") }, + { DRDATAD (POS, tti_unit.pos, T_ADDR_W, "number of characters input"), PV_LEFT }, + { DRDATAD (TIME, tti_unit.wait, 24, "input polling interval"), PV_LEFT }, + { NULL } + }; + +MTAB tti_mod[] = { + { TT_MODE, TT_MODE_7B, "7b", "7B", NULL }, + { TT_MODE, TT_MODE_8B, "8b", "8B", NULL }, + { 0 } + }; + +DEVICE tti_dev = { + "TTI", &tti_unit, tti_reg, tti_mod, + 1, 10, 31, 1, 16, 8, + NULL, NULL, &tti_reset, + NULL, NULL, NULL, + NULL, 0 + }; + +/* TTO data structures + + tto_dev TTO device descriptor + tto_unit TTO unit descriptor + tto_reg TTO register list +*/ + +UNIT tto_unit = { UDATA (&tto_svc, TT_MODE_8B, 0), SERIAL_OUT_WAIT }; + +REG tto_reg[] = { + { HRDATAD (TXDB, tto_buf, 16, "last data item processed") }, + { HRDATAD (TXCS, tto_csr, 16, "control/status register") }, + { FLDATAD (INT, tto_int, 0, "interrupt pending flag") }, + { FLDATAD (DONE, tto_csr, CSR_V_DONE, "device done flag (CSR<7>)") }, + { FLDATAD (IE, tto_csr, CSR_V_IE, "interrupt enable flag (CSR<6>)") }, + { DRDATAD (POS, tto_unit.pos, T_ADDR_W, "number of characters output"), PV_LEFT }, + { DRDATAD (TIME, tto_unit.wait, 24, "time from I/O initiation to interrupt"), PV_LEFT + REG_NZ }, + { NULL } + }; + +MTAB tto_mod[] = { + { TT_MODE, TT_MODE_7B, "7b", "7B", NULL }, + { TT_MODE, TT_MODE_8B, "8b", "8B", NULL }, + { TT_MODE, TT_MODE_7P, "7p", "7P", NULL }, + { 0 } + }; + +DEVICE tto_dev = { + "TTO", &tto_unit, tto_reg, tto_mod, + 1, 10, 31, 1, 16, 8, + NULL, NULL, &tto_reset, + NULL, NULL, NULL, + NULL, 0 + }; + +/* TODR and TMR data structures */ + +UNIT clk_unit = { UDATA (&clk_svc, UNIT_IDLE+UNIT_FIX, sizeof(TOY)), CLK_DELAY };/* 100Hz */ + +REG clk_reg[] = { + { DRDATAD (TODR, todr_reg, 32, "time-of-day register"), PV_LEFT }, + { DRDATAD (TIME, clk_unit.wait, 24, "initial poll interval"), REG_NZ + PV_LEFT }, + { DRDATAD (POLL, tmr_poll, 24, "calibrated poll interval"), REG_NZ + PV_LEFT + REG_HRO }, + { DRDATAD (TPS, clk_tps, 8, "ticks per second (100)"), REG_NZ + PV_LEFT }, +#if defined (SIM_ASYNCH_IO) + { DRDATAD (ASYNCH, sim_asynch_enabled, 1, "asynch I/O enabled flag"), PV_LEFT }, + { DRDATAD (LATENCY, sim_asynch_latency, 32, "desired asynch interrupt latency"), PV_LEFT }, + { DRDATAD (INST_LATENCY, sim_asynch_inst_latency, 32, "calibrated instruction latency"), PV_LEFT }, +#endif + { NULL } + }; + +DEVICE clk_dev = { + "TODR", &clk_unit, clk_reg, NULL, + 1, 0, 8, 4, 0, 32, + NULL, NULL, &clk_reset, + NULL, &clk_attach, &clk_detach, + NULL, 0 + }; + +UNIT tmr_unit = { UDATA (&tmr_svc, 0, 0) }; /* timer */ + +REG tmr_reg[] = { + { HRDATAD (ICCS, tmr_iccs, 32, "interval timer control and status") }, + { HRDATAD (ICR, tmr_icr, 32, "interval count register") }, + { HRDATAD (NICR, tmr_nicr, 32, "next interval count register") }, + { FLDATAD (INT, tmr_int, 0, "interrupt request") }, + { HRDATA (INCR, tmr_inc, 32), REG_HIDDEN }, + { HRDATA (SAVE, tmr_sav, 32), REG_HIDDEN }, + { FLDATA (USE100HZ, tmr_use_100hz, 0), REG_HIDDEN }, + { NULL } + }; + +DEVICE tmr_dev = { + "TMR", &tmr_unit, tmr_reg, NULL, + 1, 0, 0, 0, 0, 0, + NULL, NULL, &tmr_reset, + NULL, NULL, NULL, + NULL, 0 + }; + +/* TU58 data structures + + td_dev RX device descriptor + td_unit RX unit list + td_reg RX register list + td_mod RX modifier list +*/ + +UNIT td_unit = { UDATA (&td_svc, + UNIT_FIX+UNIT_ATTABLE+UNIT_BUFABLE+UNIT_MUSTBUF, TD_SIZE) }; + +REG td_reg[] = { + { HRDATAD (ECODE, td_ecode, 8, "end packet success code") }, + { HRDATAD (BLK, td_block, 8, "current block number") }, + { DRDATAD (PSTATE, td_state, 4, "state"), REG_RO }, + { DRDATAD (BPTR, td_obptr, 7, "output buffer pointer") }, + { DRDATAD (CTIME, td_cwait, 24, "command time"), PV_LEFT }, + { DRDATAD (STIME, td_swait, 24, "seek, per block"), PV_LEFT }, + { DRDATAD (XTIME, td_xwait, 24, "tr set time"), PV_LEFT }, + { NULL } + }; + +MTAB td_mod[] = { + { UNIT_WLK, 0, "write enabled", "WRITEENABLED", NULL }, + { UNIT_WLK, UNIT_WLK, "write locked", "LOCKED", NULL }, + { 0 } + }; + +DEVICE td_dev = { + "TD", &td_unit, td_reg, td_mod, + 1, DEV_RDX, 20, 1, DEV_RDX, 8, + NULL, NULL, &td_reset, + NULL, NULL, NULL, + NULL, 0 + }; + +/* Console storage MxPR routines + + csrs_rd/wr input control/status + csrd_rd input buffer + csts_rd/wr output control/status + cstd_wr output buffer +*/ + +int32 csrs_rd (void) +{ +return (csi_csr & RXCS_RD); +} + +void csrs_wr (int32 data) +{ +if ((data & CSR_IE) == 0) + cso_int = 0; +else if ((csi_csr & (CSR_DONE + CSR_IE)) == CSR_DONE) + csi_int = 1; +csi_csr = (csi_csr & ~RXCS_WR) | (data & RXCS_WR); +return; +} + +int32 csrd_rd (void) +{ +int32 t = csi_buf; /* char + error */ + +csi_csr = csi_csr & ~CSR_DONE; /* clr done */ +csi_buf = csi_buf & BMASK; /* clr errors */ +csi_int = 0; +return t; +} + +int32 csts_rd (void) +{ +return (cso_csr & TXCS_RD); +} + +void csts_wr (int32 data) +{ +if ((cso_csr & CSTS_BRK) && !(data & CSTS_BRK)) { + td_ibptr = 0; + td_ibuf[td_ibptr++] = TD_OPINI; + td_process_packet(); /* check packet */ + } +if ((data & CSR_IE) == 0) + cso_int = 0; +else if ((cso_csr & (CSR_DONE + CSR_IE)) == CSR_DONE) + cso_int = 1; +cso_csr = (cso_csr & ~CSTS_WR) | (data & CSTS_WR); +return; +} + +void cstd_wr (int32 data) +{ +cso_buf = data & WMASK; /* save data */ +cso_csr = cso_csr & ~CSR_DONE; /* clear flag */ +cso_int = 0; /* clear int */ + +switch (cso_state) { + + case TD_GETOPC: + td_ibptr = 0; + td_ibuf[td_ibptr++] = cso_buf; + td_process_packet(); /* check packet */ + break; + + case TD_GETLEN: + td_ibuf[td_ibptr++] = cso_buf; + td_ilen = cso_buf + 4; /* packet length + header + checksum */ + cso_state = TD_GETDATA; + break; + + case TD_GETDATA: + td_ibuf[td_ibptr++] = cso_buf; + if (td_ibptr >= td_ilen) { + cso_state = TD_GETOPC; + td_process_packet(); + } + break; + } + +cso_csr = cso_csr | CSR_DONE; /* set input flag */ +if (cso_csr & CSR_IE) + cso_int = 1; +return; +} + +void td_process_packet() +{ +int32 opcode = td_ibuf[0]; + +switch (opcode) { + + case TD_OPDAT: + if (td_state != TD_WRITE1) { /* expecting data? */ + printf("TU58 protocol error 1\n"); + return; + } + if (td_ibptr < 2) { /* whole packet read? */ + cso_state = TD_GETLEN; /* get rest of packet */ + return; + } + td_state = TD_WRITE2; + sim_activate (&td_unit, td_cwait); /* sched command */ + break; + + case TD_OPCMD: + if (td_state != TD_IDLE) { /* expecting command? */ + printf("TU58 protocol error 2\n"); + return; + } + if (td_ibptr < 2) { /* whole packet read? */ + cso_state = TD_GETLEN; /* get rest of packet */ + return; + } + switch (td_ibuf[2]) { + case TD_CMDNOP: /* NOP */ + case TD_CMDGST: /* Get status */ + case TD_CMDSST: /* Set status */ + td_state = TD_END; /* All treated as NOP */ + td_ecode = TD_STSOK; + td_offset = 0; + sim_activate (&td_unit, td_cwait); /* sched command */ + break; + + case TD_CMDINI: + printf("Warning: TU58 command 'INIT' not implemented\n"); + break; + + case TD_CMDRD: + td_block = ((td_ibuf[11] << 8) | td_ibuf[10]); + td_txsize = ((td_ibuf[9] << 8) | td_ibuf[8]); + td_state = TD_READ; + td_offset = 0; + sim_activate (&td_unit, td_cwait); /* sched command */ + break; + + case TD_CMDWR: + td_block = ((td_ibuf[11] << 8) | td_ibuf[10]); + td_txsize = ((td_ibuf[9] << 8) | td_ibuf[8]); + td_state = TD_WRITE; + td_offset = 0; + sim_activate (&td_unit, td_cwait); /* sched command */ + break; + + case TD_CMDPOS: + printf("Warning: TU58 command 'Position' not implemented\n"); + break; + + case TD_CMDDIA: + printf("Warning: TU58 command 'Diagnose' not implemented\n"); + break; + + case TD_CMDMRSP: + csi_buf = TD_OPDAT; + csi_csr = csi_csr | CSR_DONE; /* set input flag */ + if (csi_csr & CSR_IE) + csi_int = 1; + break; + } + break; + + case TD_OPINI: + sim_cancel (&td_unit); + td_ibptr = 0; + td_obptr = 0; + td_olen = 0; + td_offset = 0; + td_txsize = 0; + cso_state = TD_GETOPC; + td_state = TD_INIT; + sim_activate (&td_unit, td_iwait); /* sched command */ + break; + + case TD_OPBOO: + if (td_state != TD_IDLE) { + printf("TU58 protocol error 3\n"); + return; + } + if (td_ibptr < 2) { /* whole packet read? */ + td_ilen = 2; + cso_state = TD_GETDATA; /* get rest of packet */ + return; + } + td_block = 0; + td_txsize = 512; + td_state = TD_READ; + td_offset = 0; + sim_activate (&td_unit, td_cwait); /* sched command */ + break; + + case TD_OPCNT: + break; + + default: + //printf("TU58: Unknown opcode %d\n", opcode); + break; + } +} + +/* Terminal MxPR routines + + rxcs_rd/wr input control/status + rxdb_rd input buffer + txcs_rd/wr output control/status + txdb_wr output buffer +*/ + +int32 rxcs_rd (void) +{ +return (tti_csr & RXCS_RD); +} + +void rxcs_wr (int32 data) +{ +if ((data & CSR_IE) == 0) + tti_int = 0; +else if ((tti_csr & (CSR_DONE + CSR_IE)) == CSR_DONE) + tti_int = 1; +tti_csr = (tti_csr & ~RXCS_WR) | (data & RXCS_WR); +return; +} + +int32 rxdb_rd (void) +{ +int32 t = tti_buf; /* char + error */ + +tti_csr = tti_csr & ~CSR_DONE; /* clr done */ +tti_buf = tti_buf & BMASK; /* clr errors */ +tti_int = 0; +return t; +} + +int32 txcs_rd (void) +{ +return (tto_csr & TXCS_RD); +} + +void txcs_wr (int32 data) +{ +if ((data & CSR_IE) == 0) + tto_int = 0; +else if ((tto_csr & (CSR_DONE + CSR_IE)) == CSR_DONE) + tto_int = 1; +tto_csr = (tto_csr & ~TXCS_WR) | (data & TXCS_WR); +return; +} + +void txdb_wr (int32 data) +{ +tto_buf = data & WMASK; /* save data */ +tto_csr = tto_csr & ~CSR_DONE; /* clear flag */ +tto_int = 0; /* clear int */ +if (tto_buf & TXDB_SEL) /* console? */ + txdb_misc_wr (tto_buf); +else sim_activate (&tto_unit, tto_unit.wait); /* no, console terminal */ +return; +} + +/* Terminal input service (poll for character) */ + +t_stat tti_svc (UNIT *uptr) +{ +int32 c; + +sim_activate (uptr, KBD_WAIT (uptr->wait, tmr_poll)); /* continue poll */ +if ((c = sim_poll_kbd ()) < SCPE_KFLAG) /* no char or error? */ + return c; +if (c & SCPE_BREAK) /* break? */ + tti_buf = RXDB_ERR | RXDB_FRM; +else tti_buf = sim_tt_inpcvt (c, TT_GET_MODE (uptr->flags)); +uptr->pos = uptr->pos + 1; +tti_csr = tti_csr | CSR_DONE; +if (tti_csr & CSR_IE) + tti_int = 1; +return SCPE_OK; +} + +/* Terminal input reset */ + +t_stat tti_reset (DEVICE *dptr) +{ +tmxr_set_console_units (&tti_unit, &tto_unit); +tti_buf = 0; +tti_csr = 0; +tti_int = 0; +sim_activate_abs (&tti_unit, KBD_WAIT (tti_unit.wait, tmr_poll)); +csi_buf = 0; +csi_csr = 0; +csi_int = 0; +return SCPE_OK; +} + +/* Terminal output service (output character) */ + +t_stat tto_svc (UNIT *uptr) +{ +int32 c; +t_stat r; + +if ((tto_buf & TXDB_SEL) == 0) { /* for console? */ + c = sim_tt_outcvt (tto_buf, TT_GET_MODE (uptr->flags)); + if (c >= 0) { + if ((r = sim_putchar_s (c)) != SCPE_OK) { /* output; error? */ + sim_activate (uptr, uptr->wait); /* retry */ + return ((r == SCPE_STALL)? SCPE_OK: r); /* !stall? report */ + } + } + uptr->pos = uptr->pos + 1; + } +tto_csr = tto_csr | CSR_DONE; +if (tto_csr & CSR_IE) + tto_int = 1; +return SCPE_OK; +} + +/* Terminal output reset */ + +t_stat tto_reset (DEVICE *dptr) +{ +tto_buf = 0; +tto_csr = CSR_DONE; +tto_int = 0; +sim_cancel (&tto_unit); /* deactivate unit */ +return SCPE_OK; +} + +/* Programmable timer + + The architected VAX timer, which increments at 1Mhz, cannot be + accurately simulated due to the overhead that would be required + for 1M clock events per second. Instead, a hidden calibrated + 100Hz timer is run (because that's what VMS expects), and a + hack is used for the interval timer. + + When the timer is started, the timer interval is inspected. + + if the interval is >= 10msec, then the 100Hz timer drives the + next interval + if the interval is < 10mec, then count instructions + + If the interval register is read, then its value between events + is interpolated using the current instruction count versus the + count when the most recent event started, the result is scaled + to the calibrated system clock, unless the interval being timed + is less than a calibrated system clock tick (or the calibrated + clock is running very slowly) at which time the result will be + the elapsed instruction count. +*/ + +int32 iccs_rd (void) +{ +return tmr_iccs & TMR_CSR_RD; +} + +void iccs_wr (int32 val) +{ +if ((val & TMR_CSR_RUN) == 0) { /* clearing run? */ + sim_cancel (&tmr_unit); /* cancel timer */ + tmr_use_100hz = 0; + if (tmr_iccs & TMR_CSR_RUN) /* run 1 -> 0? */ + tmr_icr = icr_rd (TRUE); /* update itr */ + } +tmr_iccs = tmr_iccs & ~(val & TMR_CSR_W1C); /* W1C csr */ +tmr_iccs = (tmr_iccs & ~TMR_CSR_WR) | /* new r/w */ + (val & TMR_CSR_WR); +if (val & TMR_CSR_XFR) tmr_icr = tmr_nicr; /* xfr set? */ +if (val & TMR_CSR_RUN) { /* run? */ + if (val & TMR_CSR_XFR) /* new tir? */ + sim_cancel (&tmr_unit); /* stop prev */ + if (!sim_is_active (&tmr_unit)) /* not running? */ + tmr_sched (); /* activate */ + } +else if (val & TMR_CSR_SGL) { /* single step? */ + tmr_incr (1); /* incr tmr */ + if (tmr_icr == 0) /* if ovflo, */ + tmr_icr = tmr_nicr; /* reload tir */ + } +if ((tmr_iccs & (TMR_CSR_DON | TMR_CSR_IE)) != /* update int */ + (TMR_CSR_DON | TMR_CSR_IE)) + tmr_int = 0; +return; +} + +int32 icr_rd (t_bool interp) +{ +uint32 delta; + +if (interp || (tmr_iccs & TMR_CSR_RUN)) { /* interp, running? */ + delta = sim_grtime () - tmr_sav; /* delta inst */ + if (tmr_use_100hz && (tmr_poll > TMR_INC)) /* scale large int */ + delta = (uint32) ((((double) delta) * TMR_INC) / tmr_poll); + if (delta >= tmr_inc) + delta = tmr_inc - 1; + return tmr_icr + delta; + } +return tmr_icr; +} + +int32 nicr_rd () +{ +return tmr_nicr; +} + +void nicr_wr (int32 val) +{ +tmr_nicr = val; +} + +/* 100Hz base clock unit service */ + +t_stat clk_svc (UNIT *uptr) +{ +tmr_poll = sim_rtcn_calb (clk_tps, TMR_CLK); /* calibrate clock */ +sim_activate (&clk_unit, tmr_poll); /* reactivate unit */ +tmxr_poll = tmr_poll * TMXR_MULT; /* set mux poll */ +AIO_SET_INTERRUPT_LATENCY(tmr_poll*clk_tps); /* set interrrupt latency */ +if ((tmr_iccs & TMR_CSR_RUN) && tmr_use_100hz) /* timer on, std intvl? */ + tmr_incr (TMR_INC); /* do timer service */ +return SCPE_OK; +} + +/* Interval timer unit service */ + +t_stat tmr_svc (UNIT *uptr) +{ +tmr_incr (tmr_inc); /* incr timer */ +return SCPE_OK; +} + +/* Timer increment */ + +void tmr_incr (uint32 inc) +{ +uint32 new_icr = (tmr_icr + inc) & LMASK; /* add incr */ + +if (new_icr < tmr_icr) { /* ovflo? */ + tmr_icr = 0; /* now 0 */ + if (tmr_iccs & TMR_CSR_DON) /* done? set err */ + tmr_iccs = tmr_iccs | TMR_CSR_ERR; + else tmr_iccs = tmr_iccs | TMR_CSR_DON; /* set done */ + if (tmr_iccs & TMR_CSR_RUN) { /* run? */ + tmr_icr = tmr_nicr; /* reload */ + tmr_sched (); /* reactivate */ + } + if (tmr_iccs & TMR_CSR_IE) /* ie? set int req */ + tmr_int = 1; + else tmr_int = 0; + } +else { + tmr_icr = new_icr; /* no, update icr */ + if (tmr_iccs & TMR_CSR_RUN) /* still running? */ + tmr_sched (); /* reactivate */ + } +return; +} + +/* Timer scheduling */ + +void tmr_sched (void) +{ +tmr_sav = sim_grtime (); /* save intvl base */ +tmr_inc = (~tmr_icr + 1); /* inc = interval */ +if (tmr_inc == 0) tmr_inc = 1; +if (tmr_inc < TMR_INC) { /* 100Hz multiple? */ + sim_activate (&tmr_unit, tmr_inc); /* schedule timer */ + tmr_use_100hz = 0; + } +else tmr_use_100hz = 1; /* let clk handle */ +return; +} + +/* 100Hz clock reset */ + +t_stat clk_reset (DEVICE *dptr) +{ +tmr_poll = sim_rtcn_init (clk_unit.wait, TMR_CLK); /* init 100Hz timer */ +sim_activate_abs (&clk_unit, tmr_poll); /* activate 100Hz unit */ +tmxr_poll = tmr_poll * TMXR_MULT; /* set mux poll */ +if (clk_unit.filebuf == NULL) { /* make sure the TODR is initialized */ + clk_unit.filebuf = calloc(sizeof(TOY), 1); + if (clk_unit.filebuf == NULL) + return SCPE_MEM; + todr_resync (); + } +return SCPE_OK; +} + +/* CLK attach */ + +t_stat clk_attach (UNIT *uptr, char *cptr) +{ +t_stat r; + +uptr->flags = uptr->flags | (UNIT_ATTABLE | UNIT_BUFABLE); +memset (uptr->filebuf, 0, (size_t)uptr->capac); +r = attach_unit (uptr, cptr); +if (r != SCPE_OK) + uptr->flags = uptr->flags & ~(UNIT_ATTABLE | UNIT_BUFABLE); +else + uptr->hwmark = (uint32) uptr->capac; +return r; +} + +/* CLK detach */ + +t_stat clk_detach (UNIT *uptr) +{ +t_stat r; + +r = detach_unit (uptr); +if ((uptr->flags & UNIT_ATT) == 0) + uptr->flags = uptr->flags & ~(UNIT_ATTABLE | UNIT_BUFABLE); +return r; +} + + +/* Interval timer reset */ + +t_stat tmr_reset (DEVICE *dptr) +{ +tmr_iccs = 0; +tmr_icr = 0; +tmr_nicr = 0; +tmr_int = 0; +tmr_use_100hz = 1; +sim_cancel (&tmr_unit); /* cancel timer */ +todr_resync (); /* resync TODR */ +return SCPE_OK; +} + +/* TODR routines */ + +int32 todr_rd (void) +{ +TOY *toy = (TOY *)clk_unit.filebuf; +struct timespec base, now, val; + +clock_gettime(CLOCK_REALTIME, &now); /* get curr time */ +base.tv_sec = toy->toy_gmtbase; +base.tv_nsec = toy->toy_gmtbasemsec * 1000000; +sim_timespec_diff (&val, &now, &base); +return (int32)(val.tv_sec*100 + val.tv_nsec/10000000); /* 100hz Clock Ticks */ +} + + +void todr_wr (int32 data) +{ +TOY *toy = (TOY *)clk_unit.filebuf; +struct timespec now, val, base; + +/* Save the GMT time when set value was 0 to record the base for future + read operations in "battery backed-up" state */ + +if (-1 == clock_gettime(CLOCK_REALTIME, &now)) /* get curr time */ + return; /* error? */ +val.tv_sec = ((uint32)data) / 100; +val.tv_nsec = (((uint32)data) % 100) * 10000000; +sim_timespec_diff (&base, &now, &val); /* base = now - data */ +toy->toy_gmtbase = (uint32)base.tv_sec; +toy->toy_gmtbasemsec = base.tv_nsec/1000000; +} + +t_stat todr_resync (void) +{ +TOY *toy = (TOY *)clk_unit.filebuf; + +if (clk_unit.flags & UNIT_ATT) { /* Attached means behave like real VAX780 */ + if (!toy->toy_gmtbase) /* Never set? */ + todr_wr (0); /* Start ticking from 0 */ + } +else { /* Not-Attached means */ + uint32 base; /* behave like simh VMS default */ + time_t curr; + struct tm *ctm; + + curr = time (NULL); /* get curr time */ + if (curr == (time_t) -1) /* error? */ + return SCPE_NOFNC; + ctm = localtime (&curr); /* decompose */ + if (ctm == NULL) /* error? */ + return SCPE_NOFNC; + base = (((((ctm->tm_yday * 24) + /* sec since 1-Jan */ + ctm->tm_hour) * 60) + + ctm->tm_min) * 60) + + ctm->tm_sec; + todr_wr ((base * 100) + 0x10000000); /* use VMS form */ + } +return SCPE_OK; +} + +/* Console write, txdb<11:8> != 0 (console unit) */ + +t_stat txdb_misc_wr (int32 data) +{ +int32 sel = TXDB_GETSEL (data); /* get selection */ + +sim_activate (&tto_unit, tto_unit.wait); /* set up timeout */ +if (sel == TXDB_MISC) { /* misc function? */ + switch (data & MISC_MASK) { /* case on function */ + case MISC_CLWS: + case MISC_CLCS: + break; + case MISC_SWDN: + ABORT (STOP_SWDN); + break; + case MISC_BOOT: + con_halt (0, 0); /* set up reboot */ + break; + } + } +return SCPE_OK; +} + +t_stat td_svc (UNIT *uptr) +{ +int32 i, t, data_size; +uint16 c, w; +uint32 da; +int8 *fbuf = uptr->filebuf; + +switch (td_state) { /* case on state */ + + case TD_IDLE: /* idle */ + return SCPE_IERR; /* done */ + + case TD_READ: case TD_WRITE: /* read, write */ + if (td_test_xfr (uptr, td_state)) { /* transfer ok? */ + t = abs (td_block - 0); /* # blocks to seek */ + if (t == 0) /* minimum 1 */ + t = 1; + td_state++; /* set next state */ + sim_activate (uptr, td_swait * t); /* schedule seek */ + break; + } + else td_state = TD_END; + sim_activate (uptr, td_xwait); /* schedule next */ + break; + + case TD_READ1: /* build data packet */ + da = (td_block * 512) + td_offset; /* get tape address */ + if (td_txsize > 128) /* Packet length */ + data_size = 128; + else data_size = td_txsize; + td_txsize = td_txsize - data_size; + td_offset = td_offset + data_size; + + td_obptr = 0; + td_obuf[td_obptr++] = TD_OPDAT; /* Data packet */ + td_obuf[td_obptr++] = data_size; /* Data length */ + for (i = 0; i < data_size; i++) /* copy sector to buf */ + td_obuf[td_obptr++] = fbuf[da + i]; + c = 0; + for (i = 0; i < (data_size + 2); i++) { /* Calculate checksum */ + w = (td_obuf[i] << ((i & 0x1) ? 8 : 0)); + c = c + w + ( (uint32)((uint32)c + (uint32)w) > 0xFFFF ? 1 : 0); + } + td_obuf[td_obptr++] = (c & 0xFF); /* Checksum L */ + td_obuf[td_obptr++] = ((c >> 8) & 0xFF); /* Checksum H */ + td_olen = td_obptr; + td_obptr = 0; + td_state = TD_READ2; /* go empty */ + sim_activate (uptr, td_xwait); /* schedule next */ + break; + + case TD_READ2: /* send data packet to host */ + if ((csi_csr & CSR_DONE) == 0) { /* prev data taken? */ + csi_buf = td_obuf[td_obptr++]; /* get next byte */ + csi_csr = csi_csr | CSR_DONE; /* set input flag */ + if (csi_csr & CSR_IE) + csi_int = 1; + if (td_obptr >= td_olen) { /* buffer empty? */ + if (td_txsize > 0) + td_state = TD_READ1; + else + td_state = TD_END; + } + } + sim_activate (uptr, td_xwait); /* schedule next */ + break; + + case TD_WRITE1: /* send continue */ + if ((csi_csr & CSR_DONE) == 0) { /* prev data taken? */ + csi_buf = TD_OPCNT; + csi_csr = csi_csr | CSR_DONE; /* set input flag */ + if (csi_csr & CSR_IE) + csi_int = 1; + break; + } + sim_activate (uptr, td_xwait); /* schedule next */ + break; + + case TD_WRITE2: /* write data to buffer */ + da = (td_block * 512) + td_offset; /* get tape address */ + td_olen = td_ibuf[1]; + for (i = 0; i < td_olen; i++) /* write data to buffer */ + fbuf[da + i] = td_ibuf[i + 2]; + td_offset += td_olen; + td_txsize -= td_olen; + da = da + td_olen; + if (da > uptr->hwmark) /* update hwmark */ + uptr->hwmark = da; + if (td_txsize > 0) + td_state = TD_WRITE1; + else { /* check whole number of blocks written */ + if ((td_olen = (512 - (td_offset % 512))) != 512) { + for (i = 0; i < td_olen; i++) + fbuf[da + i] = 0; /* zero fill */ + da = da + td_olen; + if (da > uptr->hwmark) /* update hwmark */ + uptr->hwmark = da; + } + td_state = TD_END; + } + sim_activate (uptr, td_xwait); /* schedule next */ + break; + + case TD_END: /* build end packet */ + td_obptr = 0; + td_obuf[td_obptr++] = TD_OPCMD; /* Command packet */ + td_obuf[td_obptr++] = 0xA; /* ** Need definition ** */ + td_obuf[td_obptr++] = TD_CMDEND; + td_obuf[td_obptr++] = td_ecode; /* Success code */ + td_obuf[td_obptr++] = 0; /* Unit number */ + td_obuf[td_obptr++] = 0; /* Not used */ + td_obuf[td_obptr++] = 0; /* Sequence L (not used) */ + td_obuf[td_obptr++] = 0; /* Sequence H (not used) */ + td_obuf[td_obptr++] = (td_offset & 0xFF); /* Byte count L */ + td_obuf[td_obptr++] = ((td_offset >> 8) & 0xFF);/* Byte count H */ + td_obuf[td_obptr++] = 0; /* Summary status L */ + td_obuf[td_obptr++] = 0; /* Summary status H */ + c = 0; + for (i = 0; i < (0xA + 2); i++) { /* Calculate checksum */ + w = (td_obuf[i] << ((i & 0x1) ? 8 : 0)); + c = c + w + ( (uint32)((uint32)c + (uint32)w) > 0xFFFF ? 1 : 0); + } + td_obuf[td_obptr++] = c & 0xFF; /* Checksum L */ + td_obuf[td_obptr++] = (c >> 8) & 0xFF; /* Checksum H */ + td_olen = td_obptr; + td_obptr = 0; + td_state = TD_END1; /* go empty */ + sim_activate (uptr, td_xwait); /* schedule next */ + break; + + case TD_END1: /* send end packet to host */ + if ((csi_csr & CSR_DONE) == 0) { /* prev data taken? */ + csi_buf = td_obuf[td_obptr++]; /* get next byte */ + csi_csr = csi_csr | CSR_DONE; /* set input flag */ + if (csi_csr & CSR_IE) + csi_int = 1; + if (td_obptr >= td_olen) { /* buffer empty? */ + td_state = TD_IDLE; + break; + } + } + sim_activate (uptr, td_xwait); /* schedule next */ + break; + + case TD_INIT: + if ((csi_csr & CSR_DONE) == 0) { /* prev data taken? */ + csi_buf = TD_OPCNT; + csi_csr = csi_csr | CSR_DONE; /* set input flag */ + if (csi_csr & CSR_IE) + csi_int = 1; + td_state = TD_IDLE; + break; + } + sim_activate (uptr, td_xwait); /* schedule next */ + break; + } +return SCPE_OK; +} + +/* Test for data transfer okay */ + +t_bool td_test_xfr (UNIT *uptr, int32 state) +{ +if ((uptr->flags & UNIT_BUF) == 0) /* not buffered? */ + td_ecode = TD_STSNC; +else if (td_block >= TD_NUMBLK) /* bad block? */ + td_ecode = TD_STSBBN; +else if ((state == TD_WRITE) && (uptr->flags & UNIT_WPRT)) /* write and locked? */ + td_ecode = TD_STSWP; +else { + td_ecode = TD_STSOK; + return TRUE; + } +return FALSE; +} + +/* Reset */ + +t_stat td_reset (DEVICE *dptr) +{ +cso_buf = 0; +cso_csr = CSR_DONE; +cso_int = 0; +cso_state = TD_GETOPC; +td_ibptr = 0; +td_obptr = 0; +td_olen = 0; +td_offset = 0; +td_txsize = 0; +sim_cancel (&td_unit); +return SCPE_OK; +} diff --git a/VAX/vax750_syslist.c b/VAX/vax750_syslist.c new file mode 100644 index 00000000..634d8523 --- /dev/null +++ b/VAX/vax750_syslist.c @@ -0,0 +1,131 @@ +/* vax750_syslist.c: VAX 11/750 device list + + Copyright (c) 2010-2012, Matt Burke + This module incorporates code from SimH, Copyright (c) 1998-2008, Robert M Supnik + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name(s) of the author(s) shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from the author(s). + + 21-Oct-2012 MB First Version +*/ + +#include "vax_defs.h" + +char sim_name[] = "VAX750"; + +extern DEVICE cpu_dev; +extern DEVICE tlb_dev; +extern DEVICE cmi_dev; +extern DEVICE mctl_dev; +extern DEVICE uba_dev; +extern DEVICE mba_dev[MBA_NUM]; +extern DEVICE clk_dev; +extern DEVICE tmr_dev; +extern DEVICE tti_dev, tto_dev; +extern DEVICE td_dev; +extern DEVICE cr_dev; +extern DEVICE lpt_dev; +extern DEVICE rq_dev, rqb_dev, rqc_dev, rqd_dev; +extern DEVICE rl_dev; +extern DEVICE hk_dev; +extern DEVICE rp_dev; +extern DEVICE ry_dev; +extern DEVICE ts_dev; +extern DEVICE tq_dev; +extern DEVICE tu_dev; +extern DEVICE dz_dev; +extern DEVICE vh_dev; +extern DEVICE xu_dev, xub_dev; +extern DEVICE dmc_dev[]; + +extern UNIT cpu_unit; +extern void WriteB (uint32 pa, int32 val); + +DEVICE *sim_devices[] = { + &cpu_dev, + &tlb_dev, + &cmi_dev, + &mctl_dev, + &uba_dev, + &mba_dev[0], + &mba_dev[1], + &clk_dev, + &tmr_dev, + &tti_dev, + &tto_dev, + &td_dev, + &dz_dev, + &vh_dev, + &cr_dev, + &lpt_dev, + &rp_dev, + &rl_dev, + &hk_dev, + &rq_dev, + &rqb_dev, + &rqc_dev, + &rqd_dev, + &ry_dev, + &tu_dev, + &ts_dev, + &tq_dev, + &xu_dev, + &xub_dev, + &dmc_dev[0], + &dmc_dev[1], + &dmc_dev[2], + &dmc_dev[3], + NULL + }; + +/* Binary loader + + The binary loader handles absolute system images, that is, system + images linked /SYSTEM. These are simply a byte stream, with no + origin or relocation information. + + -o for memory, specify origin +*/ + +t_stat sim_load (FILE *fileref, char *cptr, char *fnam, int flag) +{ +t_stat r; +int32 val; +uint32 origin, limit; + +if (flag) /* dump? */ + return SCPE_ARG; +origin = 0; /* memory */ +limit = (uint32) cpu_unit.capac; +if (sim_switches & SWMASK ('O')) { /* origin? */ + origin = (int32) get_uint (cptr, 16, 0xFFFFFFFF, &r); + if (r != SCPE_OK) + return SCPE_ARG; + } + +while ((val = getc (fileref)) != EOF) { /* read byte stream */ + if (origin >= limit) /* NXM? */ + return SCPE_NXM; + WriteB (origin, val); /* memory */ + origin = origin + 1; + } +return SCPE_OK; +} diff --git a/VAX/vax750_uba.c b/VAX/vax750_uba.c new file mode 100644 index 00000000..c2e6fca9 --- /dev/null +++ b/VAX/vax750_uba.c @@ -0,0 +1,684 @@ +/* vax750_uba.c: VAX 11/750 Unibus adapter + + Copyright (c) 2010-2011, Matt Burke + This module incorporates code from SimH, Copyright (c) 2004-2008, Robert M Supnik + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name(s) of the author(s) shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from the author(s). + + uba DW750 Unibus adapter + + 21-Oct-2012 MB First Version +*/ + +#include "vax_defs.h" + +/* Unibus adapter */ + +#define UBA_NDPATH 16 /* number of data paths */ +#define UBA_NMAPR 496 /* number of map reg */ + +/* Unibus adapter configuration register */ + +#define UBACNF_OF 0x00 +#define UBACNF_CODE 0x00000028 /* adapter code */ + +/* Control/Status registers */ + +#define UBACSR1_OF 0x01 +#define UBACSR2_OF 0x02 +#define UBACSR3_OF 0x03 +#define UBACSR_PUR 0x00000001 /* Purge request */ +#define UBACSR_UCE 0x20000000 /* Uncorrectable err */ +#define UBACSR_NXM 0x40000000 /* NXM */ +#define UBACSR_ERR 0x80000000 /* Error flag */ +#define UBACSR_RD (UBACSR_PUR | UBACSR_UCE | UBACSR_NXM | \ + UBACSR_ERR) +#define UBACSR_WR 0 + +/* Map registers */ + +#define UBAMAP_OF 0x200 +#define UBAMAP_VLD 0x80000000 /* valid */ +#define UBAMAP_LWAE 0x04000000 /* LW access enb - ni */ +#define UBAMAP_ODD 0x02000000 /* odd byte */ +#define UBAMAP_V_DP 21 /* data path */ +#define UBAMAP_M_DP 0xF +#define UBAMAP_DP (UBAMAP_M_DP << UBAMAP_V_DP) +#define UBAMAP_GETDP(x) (((x) >> UBAMAP_V_DP) & UBAMAP_M_DP) +#define UBAMAP_PAG 0x001FFFFF +#define UBAMAP_RD (0x86000000 | UBAMAP_DP | UBAMAP_PAG) +#define UBAMAP_WR (UBAMAP_RD) + +/* Debug switches */ + +#define UBA_DEB_RRD 0x01 /* reg reads */ +#define UBA_DEB_RWR 0x02 /* reg writes */ +#define UBA_DEB_MRD 0x04 /* map reads */ +#define UBA_DEB_MWR 0x08 /* map writes */ +#define UBA_DEB_XFR 0x10 /* transfers */ +#define UBA_DEB_ERR 0x20 /* errors */ + +int32 int_req[IPL_HLVL] = { 0 }; /* intr, IPL 14-17 */ +uint32 uba_csr1 = 0; /* csr reg 1 */ +uint32 uba_csr2 = 0; /* csr reg 2 */ +uint32 uba_csr3 = 0; /* csr reg 3 */ +uint32 uba_int = 0; /* UBA interrupt */ +uint32 uba_map[UBA_NMAPR] = { 0 }; /* map registers */ +int32 autcon_enb = 1; /* autoconfig enable */ + +extern int32 trpirq; +extern int32 autcon_enb; +extern jmp_buf save_env; +extern UNIT cpu_unit; +extern uint32 nexus_req[NEXUS_HLVL]; +extern int32 p1; +extern int32 fault_PC; /* fault PC */ +extern int32 mem_err; + +t_stat uba_reset (DEVICE *dptr); +t_stat uba_ex (t_value *vptr, t_addr exta, UNIT *uptr, int32 sw); +t_stat uba_dep (t_value val, t_addr exta, UNIT *uptr, int32 sw); +t_stat uba_rdreg (int32 *val, int32 pa, int32 mode); +t_stat uba_wrreg (int32 val, int32 pa, int32 lnt); +int32 uba_get_ubvector (int32 lvl); +void uba_eval_int (void); +void uba_ioreset (void); +t_bool uba_map_addr (uint32 ua, uint32 *ma); +t_stat set_autocon (UNIT *uptr, int32 val, char *cptr, void *desc); +t_stat show_autocon (FILE *st, UNIT *uptr, int32 val, void *desc); +t_stat show_iospace (FILE *st, UNIT *uptr, int32 val, void *desc); +t_stat uba_show_virt (FILE *st, UNIT *uptr, int32 val, void *desc); + +extern int32 eval_int (void); +extern t_stat build_dib_tab (void); +extern void cmi_set_tmo (void); + +/* Unibus IO page dispatches */ + +t_stat (*iodispR[IOPAGESIZE >> 1])(int32 *dat, int32 ad, int32 md); +t_stat (*iodispW[IOPAGESIZE >> 1])(int32 dat, int32 ad, int32 md); + +/* Unibus interrupt request to interrupt action map */ + +int32 (*int_ack[IPL_HLVL][32])(void); /* int ack routines */ + +/* Unibus interrupt request to vector map */ + +int32 int_vec[IPL_HLVL][32]; /* int req to vector */ + +/* Unibus adapter data structures + + uba_dev UBA device descriptor + uba_unit UBA units + uba_reg UBA register list +*/ + +DIB uba_dib = { TR_UBA, 0, &uba_rdreg, &uba_wrreg, 0, 0 }; + +UNIT uba_unit = { UDATA (0, 0, 0) }; + +REG uba_reg[] = { + { HRDATAD (IPL17, int_req[3], 32, "IPL 17 interrupt flags"), REG_RO }, + { HRDATAD (IPL16, int_req[2], 32, "IPL 16 interrupt flags"), REG_RO }, + { HRDATAD (IPL15, int_req[1], 32, "IPL 15 interrupt flags"), REG_RO }, + { HRDATAD (IPL14, int_req[0], 32, "IPL 14 interrupt flags"), REG_RO }, + { HRDATAD (CSR1, uba_csr1, 32, "Control/Status register for BDP #1") }, + { HRDATAD (CSR2, uba_csr2, 32, "Control/Status register for BDP #2") }, + { HRDATAD (CSR3, uba_csr3, 32, "Control/Status register for BDP #3") }, + { FLDATAD (INT, uba_int, 0, "Interrupt pending") }, + { FLDATAD (NEXINT, nexus_req[IPL_UBA], TR_UBA, "Nexus interrupt pending") }, + { BRDATAD (MAP, uba_map, 16, 32, 496, "Unibus map registers") }, + { FLDATA (AUTOCON, autcon_enb, 0), REG_HRO }, + { NULL } + }; + +MTAB uba_mod[] = { + { MTAB_XTD|MTAB_VDV, TR_UBA, "NEXUS", NULL, + NULL, &show_nexus }, + { MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, "IOSPACE", NULL, + NULL, &show_iospace }, + { MTAB_XTD|MTAB_VDV, 1, "AUTOCONFIG", "AUTOCONFIG", + &set_autocon, &show_autocon }, + { MTAB_XTD|MTAB_VDV, 0, NULL, "NOAUTOCONFIG", + &set_autocon, NULL }, + { MTAB_XTD|MTAB_VDV|MTAB_NMO|MTAB_SHP, 0, "VIRTUAL", NULL, + NULL, &uba_show_virt }, + { 0 } + }; + +DEBTAB uba_deb[] = { + { "REGREAD", UBA_DEB_RRD }, + { "REGWRITE", UBA_DEB_RWR }, + { "MAPREAD", UBA_DEB_MRD }, + { "MAPWRITE", UBA_DEB_MWR }, + { "XFER", UBA_DEB_XFR }, + { "ERROR", UBA_DEB_ERR }, + { NULL, 0 } + }; + +DEVICE uba_dev = { + "UBA", &uba_unit, uba_reg, uba_mod, + 1, 16, UBADDRWIDTH, 2, 16, 16, + &uba_ex, &uba_dep, &uba_reset, + NULL, NULL, NULL, + &uba_dib, DEV_NEXUS | DEV_DEBUG, 0, + uba_deb, 0, 0 + }; + +/* Read Unibus adapter register - aligned lw only */ + +t_stat uba_rdreg (int32 *val, int32 pa, int32 lnt) +{ +int32 idx, ofs; + +if ((pa & 3) || (lnt != L_LONG)) { /* unaligned or not lw? */ + printf (">>UBA: invalid adapter read mask, pa = %X, lnt = %d\r\n", pa, lnt); + /* FIXME: set appropriate error bits */ + return SCPE_OK; + } +ofs = NEXUS_GETOFS (pa); /* get offset */ +if (ofs >= UBAMAP_OF) { /* map? */ + idx = ofs - UBAMAP_OF; + if (idx >= UBA_NMAPR) /* valid? */ + return SCPE_NXM; + *val = uba_map[idx] & UBAMAP_RD; + if (DEBUG_PRI (uba_dev, UBA_DEB_MRD)) + fprintf (sim_deb, ">>UBA: map %d read, value = %X at PC = %08X\n", idx, *val, fault_PC); + return SCPE_OK; + } + +switch (ofs) { /* case on offset */ + + case UBACNF_OF: /* Config Reg */ + *val = UBACNF_CODE; + break; + + case UBACSR1_OF: /* CSR1 */ + *val = (uba_csr1 & UBACSR_RD); + break; + + case UBACSR2_OF: /* CSR2 */ + *val = (uba_csr2 & UBACSR_RD); + break; + + case UBACSR3_OF: /* CSR3 */ + *val = (uba_csr3 & UBACSR_RD); + break; + + default: + return SCPE_NXM; + } + +if (DEBUG_PRI (uba_dev, UBA_DEB_RRD)) + fprintf (sim_deb, ">>UBA: reg %d read, value = %X at PC = %08X\n", ofs, *val, fault_PC); +return SCPE_OK; +} + +/* Write Unibus adapter register */ + +t_stat uba_wrreg (int32 val, int32 pa, int32 lnt) +{ +int32 idx, ofs; + +if ((pa & 3) || (lnt != L_LONG)) { /* unaligned or not lw? */ + printf (">>UBA: invalid adapter write mask, pa = %X, lnt = %d\r\n", pa, lnt); + /* FIXME: set appropriate error bits */ + return SCPE_OK; + } +ofs = NEXUS_GETOFS (pa); /* get offset */ +if (ofs >= UBAMAP_OF) { /* map? */ + idx = ofs - UBAMAP_OF; + if (idx >= UBA_NMAPR) /* valid? */ + return SCPE_NXM; + uba_map[idx] = val & UBAMAP_WR; + if (DEBUG_PRI (uba_dev, UBA_DEB_MWR)) + fprintf (sim_deb, ">>UBA: map %d write, value = %X at PC = %08X\n", idx, val, fault_PC); + return SCPE_OK; + } + +switch (ofs) { /* case on offset */ + + case UBACNF_OF: /* Config Reg */ + break; + + case UBACSR1_OF: /* CSR1 */ + uba_csr1 = (val & UBACSR_WR); + break; + + case UBACSR2_OF: /* CSR2 */ + uba_csr2 = (val & UBACSR_WR); + break; + + case UBACSR3_OF: /* CSR3 */ + uba_csr3 = (val & UBACSR_WR); + break; + + default: + return SCPE_NXM; + break; + } + +if (DEBUG_PRI (uba_dev, UBA_DEB_RWR)) + fprintf (sim_deb, ">>UBA: reg %d write, value = %X at PC = %08X\n", ofs, val, fault_PC); +return SCPE_OK; +} + +/* Read and write Unibus I/O space */ + +int32 ReadUb (uint32 pa) +{ +int32 idx, val; + +if (ADDR_IS_IOP (pa)) { /* iopage,!init */ + idx = (pa & IOPAGEMASK) >> 1; + if (iodispR[idx]) { + iodispR[idx] (&val, pa, READ); + return val; + } + } +cmi_set_tmo(); +MACH_CHECK(MCHK_BPE); +return 0; +} + +void WriteUb (uint32 pa, int32 val, int32 mode) +{ +int32 idx; + +if (ADDR_IS_IOP (pa)) { /* iopage,!init */ + idx = (pa & IOPAGEMASK) >> 1; + if (iodispW[idx]) { + iodispW[idx] (val, pa, mode); + return; + } + } +cmi_set_tmo(); +mem_err = 1; /* interrupt */ +SET_IRQL; +return; +} + +/* ReadIO - read from IO - UBA only responds to byte, aligned word + + Inputs: + pa = physical address + lnt = length (BWLQ) + Output: + longword of data +*/ + +int32 ReadIO (uint32 pa, int32 lnt) +{ +uint32 iod; + +if ((lnt == L_BYTE) || /* byte? */ + ((lnt == L_WORD) && ((pa & 1) == 0))) { /* aligned word? */ + iod = ReadUb (pa); /* DATI from Unibus */ + if (pa & 2) /* position */ + iod = iod << 16; + } +else { + printf (">>UBA: invalid read mask, pa = %x, lnt = %d\n", pa, lnt); + /* FIXME: set appropriate error bits */ + iod = 0; + } +SET_IRQL; +return iod; +} + +/* WriteIO - write to IO - UBA only responds to byte, aligned word + + Inputs: + pa = physical address + val = data to write, right justified in 32b longword + lnt = length (BWL) + Outputs: + none +*/ + +void WriteIO (uint32 pa, int32 val, int32 lnt) +{ +if (lnt == L_BYTE) /* byte? DATOB */ + WriteUb (pa, val, WRITEB); +else if ((lnt == L_WORD) && ((pa & 1) == 0)) /* aligned word? */ + WriteUb (pa, val, WRITE); /* DATO */ +else { + printf (">>UBA: invalid write mask, pa = %x, lnt = %d\n", pa, lnt); + /* FIXME: set appropriate error bits */ + } +SET_IRQL; /* update ints */ +return; +} + +/* Update UBA nexus interrupts */ + +void uba_eval_int (void) +{ +int32 i; + +for (i = 0; i < (IPL_HMAX - IPL_HMIN); i++) /* clear all UBA req */ + nexus_req[i] &= ~(1 << TR_UBA); +for (i = 0; i < (IPL_HMAX - IPL_HMIN); i++) { + if (int_req[i]) + nexus_req[i] |= (1 << TR_UBA); + } +if (uba_int) /* adapter int? */ + SET_NEXUS_INT (UBA); +return; +} + +/* Return vector for Unibus interrupt at relative IPL level [0-3] */ + +int32 uba_get_ubvector (int32 lvl) +{ +int32 i, vec; + +vec = 0; +if ((lvl == (IPL_UBA - IPL_HMIN)) && uba_int) { /* UBA lvl, int? */ + uba_int = 0; /* clear int */ + } +for (i = 0; int_req[lvl] && (i < 32); i++) { + if ((int_req[lvl] >> i) & 1) { + int_req[lvl] = int_req[lvl] & ~(1u << i); + if (int_ack[lvl][i]) + return (vec | int_ack[lvl][i]()); + return (vec | int_vec[lvl][i]); + } + } +return vec; +} + +/* Unibus I/O buffer routines + + Map_ReadB - fetch byte buffer from memory + Map_ReadW - fetch word buffer from memory + Map_WriteB - store byte buffer into memory + Map_WriteW - store word buffer into memory +*/ + +int32 Map_ReadB (uint32 ba, int32 bc, uint8 *buf) +{ +int32 i, j, pbc; +uint32 ma, dat; + +ba = ba & UBADDRMASK; /* mask UB addr */ +for (i = 0; i < bc; i = i + pbc) { /* loop by pages */ + if (!uba_map_addr (ba + i, &ma)) /* page inv or NXM? */ + return (bc - i); + pbc = VA_PAGSIZE - VA_GETOFF (ma); /* left in page */ + if (pbc > (bc - i)) /* limit to rem xfr */ + pbc = bc - i; + if (DEBUG_PRI (uba_dev, UBA_DEB_XFR)) + fprintf (sim_deb, ">>UBA: 8b read, ma = %X, bc = %X\n", ma, pbc); + if ((ma | pbc) & 3) { /* aligned LW? */ + for (j = 0; j < pbc; ma++, j++) { /* no, do by bytes */ + *buf++ = ReadB (ma); + } + } + else { /* yes, do by LW */ + for (j = 0; j < pbc; ma = ma + 4, j = j + 4) { + dat = ReadL (ma); /* get lw */ + *buf++ = dat & BMASK; /* low 8b */ + *buf++ = (dat >> 8) & BMASK; /* next 8b */ + *buf++ = (dat >> 16) & BMASK; /* next 8b */ + *buf++ = (dat >> 24) & BMASK; + } + } + } +return 0; +} + +int32 Map_ReadW (uint32 ba, int32 bc, uint16 *buf) +{ +int32 i, j, pbc; +uint32 ma, dat; + +ba = ba & UBADDRMASK; /* mask UB addr */ +bc = bc & ~01; +for (i = 0; i < bc; i = i + pbc) { /* loop by pages */ + if (!uba_map_addr (ba + i, &ma)) /* page inv or NXM? */ + return (bc - i); + pbc = VA_PAGSIZE - VA_GETOFF (ma); /* left in page */ + if (pbc > (bc - i)) /* limit to rem xfr */ + pbc = bc - i; + if (DEBUG_PRI (uba_dev, UBA_DEB_XFR)) + fprintf (sim_deb, ">>UBA: 16b read, ma = %X, bc = %X\n", ma, pbc); + if ((ma | pbc) & 1) { /* aligned word? */ + for (j = 0; j < pbc; ma++, j++) { /* no, do by bytes */ + if ((i + j) & 1) { /* odd byte? */ + *buf = (*buf & BMASK) | (ReadB (ma) << 8); + buf++; + } + else *buf = (*buf & ~BMASK) | ReadB (ma); + } + } + else if ((ma | pbc) & 3) { /* aligned LW? */ + for (j = 0; j < pbc; ma = ma + 2, j = j + 2) { /* no, words */ + *buf++ = ReadW (ma); /* get word */ + } + } + else { /* yes, do by LW */ + for (j = 0; j < pbc; ma = ma + 4, j = j + 4) { + dat = ReadL (ma); /* get lw */ + *buf++ = dat & WMASK; /* low 16b */ + *buf++ = (dat >> 16) & WMASK; /* high 16b */ + } + } + } +return 0; +} + +int32 Map_WriteB (uint32 ba, int32 bc, uint8 *buf) +{ +int32 i, j, pbc; +uint32 ma, dat; + +ba = ba & UBADDRMASK; /* mask UB addr */ +for (i = 0; i < bc; i = i + pbc) { /* loop by pages */ + if (!uba_map_addr (ba + i, &ma)) /* page inv or NXM? */ + return (bc - i); + pbc = VA_PAGSIZE - VA_GETOFF (ma); /* left in page */ + if (pbc > (bc - i)) /* limit to rem xfr */ + pbc = bc - i; + if (DEBUG_PRI (uba_dev, UBA_DEB_XFR)) + fprintf (sim_deb, ">>UBA: 8b write, ma = %X, bc = %X\n", ma, pbc); + if ((ma | pbc) & 3) { /* aligned LW? */ + for (j = 0; j < pbc; ma++, j++) { /* no, do by bytes */ + WriteB (ma, *buf); + buf++; + } + } + else { /* yes, do by LW */ + for (j = 0; j < pbc; ma = ma + 4, j = j + 4) { + dat = (uint32) *buf++; /* get low 8b */ + dat = dat | (((uint32) *buf++) << 8); /* merge next 8b */ + dat = dat | (((uint32) *buf++) << 16); /* merge next 8b */ + dat = dat | (((uint32) *buf++) << 24); /* merge hi 8b */ + WriteL (ma, dat); /* store lw */ + } + } + } +return 0; +} + +int32 Map_WriteW (uint32 ba, int32 bc, uint16 *buf) +{ +int32 i, j, pbc; +uint32 ma, dat; + +ba = ba & UBADDRMASK; /* mask UB addr */ +bc = bc & ~01; +for (i = 0; i < bc; i = i + pbc) { /* loop by pages */ + if (!uba_map_addr (ba + i, &ma)) /* page inv or NXM? */ + return (bc - i); + pbc = VA_PAGSIZE - VA_GETOFF (ma); /* left in page */ + if (pbc > (bc - i)) /* limit to rem xfr */ + pbc = bc - i; + if (DEBUG_PRI (uba_dev, UBA_DEB_XFR)) + fprintf (sim_deb, ">>UBA: 16b write, ma = %X, bc = %X\n", ma, pbc); + if ((ma | pbc) & 1) { /* aligned word? */ + for (j = 0; j < pbc; ma++, j++) { /* no, bytes */ + if ((i + j) & 1) { + WriteB (ma, (*buf >> 8) & BMASK); + buf++; + } + else WriteB (ma, *buf & BMASK); + } + } + else if ((ma | pbc) & 3) { /* aligned LW? */ + for (j = 0; j < pbc; ma = ma + 2, j = j + 2) { /* no, words */ + WriteW (ma, *buf); /* write word */ + buf++; + } + } + else { /* yes, do by LW */ + for (j = 0; j < pbc; ma = ma + 4, j = j + 4) { + dat = (uint32) *buf++; /* get low 16b */ + dat = dat | (((uint32) *buf++) << 16); /* merge hi 16b */ + WriteL (ma, dat); /* store LW */ + } + } + } +return 0; +} + +/* Map an address via the translation map */ + +t_bool uba_map_addr (uint32 ua, uint32 *ma) +{ +uint32 ublk, umap; + +ublk = ua >> VA_V_VPN; /* Unibus blk */ +if (ublk >= UBA_NMAPR) /* unimplemented? */ + return FALSE; +umap = uba_map[ublk]; /* get map */ +if (umap & UBAMAP_VLD) { /* valid? */ + *ma = ((umap & UBAMAP_PAG) << VA_V_VPN) + VA_GETOFF (ua); + if ((umap & UBAMAP_DP) && (umap & UBAMAP_ODD)) /* buffered dp? */ + *ma = *ma + 1; /* byte offset? */ + return (ADDR_IS_MEM (*ma)); /* legit addr */ + } +return FALSE; +} + +/* Map an address via the translation map - console version (no status changes) */ + +t_bool uba_map_addr_c (uint32 ua, uint32 *ma) +{ +uint32 ublk, umap; + +ublk = ua >> VA_V_VPN; /* Unibus blk */ +if (ublk >= UBA_NMAPR) /* unimplemented? */ + return FALSE; +umap = uba_map[ublk]; /* get map */ +if (umap & UBAMAP_VLD) { /* valid? */ + *ma = ((umap & UBAMAP_PAG) << VA_V_VPN) + VA_GETOFF (ua); + if ((umap & UBAMAP_DP) && (umap & UBAMAP_ODD)) /* buffered dp? */ + *ma = *ma + 1; /* byte offset? */ + return TRUE; /* legit addr */ + } +return FALSE; +} + +/* Reset Unibus devices */ + +void uba_ioreset (void) +{ +int32 i; +DEVICE *dptr; + +for (i = 0; sim_devices[i] != NULL; i++) { /* reset Unibus */ + dptr = sim_devices[i]; + if (dptr->reset && (dptr->flags & DEV_UBUS)) + dptr->reset (dptr); + } +return; +} + +/* Reset Unibus adapter */ + +t_stat uba_reset (DEVICE *dptr) +{ +int32 i; + +for (i = 0; i < IPL_HLVL; i++) { + nexus_req[i] &= ~(1 << TR_UBA); + int_req[i] = 0; + } +for (i = 0; i < UBA_NMAPR; i++) + uba_map[i] = 0; +uba_csr1 = 0; +uba_csr2 = 0; +uba_csr3 = 0; +return SCPE_OK; +} + +/* Memory examine via map (word only) */ + +t_stat uba_ex (t_value *vptr, t_addr exta, UNIT *uptr, int32 sw) +{ +uint32 ua = (uint32) exta, pa; + +if ((vptr == NULL) || (ua >= UBADDRSIZE)) + return SCPE_ARG; +if (uba_map_addr_c (ua, &pa) && ADDR_IS_MEM (pa)) { + *vptr = (uint32) ReadW (pa); + return SCPE_OK; + } +return SCPE_NXM; +} + +/* Memory deposit via map (word only) */ + +t_stat uba_dep (t_value val, t_addr exta, UNIT *uptr, int32 sw) +{ +uint32 ua = (uint32) exta, pa; + +if (ua >= UBADDRSIZE) + return SCPE_ARG; +if (uba_map_addr_c (ua, &pa) && ADDR_IS_MEM (pa)) { + WriteW (pa, (int32) val); + return SCPE_OK; + } +return SCPE_NXM; +} + +/* Show UBA virtual address */ + +t_stat uba_show_virt (FILE *of, UNIT *uptr, int32 val, void *desc) +{ +t_stat r; +char *cptr = (char *) desc; +uint32 ua, pa; + +if (cptr) { + ua = (uint32) get_uint (cptr, 16, UBADDRSIZE - 1, &r); + if (r == SCPE_OK) { + if (uba_map_addr_c (ua, &pa)) + fprintf (of, "Unibus %-X = physical %-X\n", ua, pa); + else fprintf (of, "Unibus %-X: invalid mapping\n", ua); + return SCPE_OK; + } + } +fprintf (of, "Invalid argument\n"); +return SCPE_OK; +} diff --git a/VAX/vax780_defs.h b/VAX/vax780_defs.h index 9e170172..2f306e19 100644 --- a/VAX/vax780_defs.h +++ b/VAX/vax780_defs.h @@ -56,6 +56,8 @@ /* Microcode constructs */ #define VAX780_SID (1 << 24) /* system ID */ +#define VAX780_TYP (0 << 23) /* sys type: 780 */ +#define VAX785_TYP (1 << 23) /* sys type: 785 */ #define VAX780_ECO (7 << 19) /* ucode revision */ #define VAX780_PLANT (0 << 12) /* plant (Salem NH) */ #define VAX780_SN (1234) @@ -68,6 +70,10 @@ #define VER_WCSP (VER_FPLA) /* WCS primary version */ #define VER_WCSS 0x12 /* WCS secondary version */ #define VER_PCS ((VER_WCSS >> 4) & 0x3) /* PCS version */ +#define VER_WCSP_785 0x01 /* 785 WCS primary version */ +#define VER_WCSS_785 0x00 /* 785 WCS secondary version */ +#define VER_PCS_785 0x04 /* 785 PCS version */ +#define VER_MTCH_785 0x04 /* 785 PCS/WCS primary version */ /* Interrupts */ @@ -120,6 +126,7 @@ #define MT_SBITA 53 /* SBI timeout addr */ #define MT_SBIQC 54 /* SBI timeout clear */ #define MT_MBRK 60 /* microbreak */ +#define MT_MAX 63 /* last valid IPR */ /* Machine specific reserved operand tests */ @@ -141,6 +148,11 @@ #define LP_MBZ84_TEST(r) if ((((uint32)(r)) & 0xF8C00000) != 0) RSVD_OPND_FAULT #define LP_MBZ92_TEST(r) if ((((uint32)(r)) & 0x7FC00000) != 0) RSVD_OPND_FAULT +/* CPU */ + +#define CPU_MODEL_MODIFIERS \ + { MTAB_XTD|MTAB_VDV, 0, "MODEL", "MODEL={785|780}", \ + &cpu_set_model, &cpu_show_model }, /* Memory */ #define MAXMEMWIDTH 23 /* max mem, MS780C */ @@ -150,6 +162,12 @@ #define INITMEMSIZE (1 << MAXMEMWIDTH) /* initial memory size */ #define MEMSIZE (cpu_unit.capac) #define ADDR_IS_MEM(x) (((uint32) (x)) < MEMSIZE) +#define MEM_MODIFIERS { UNIT_MSIZE, (1u << 23), NULL, "8M", &cpu_set_size }, \ + { UNIT_MSIZE, (1u << 24), NULL, "16M", &cpu_set_size }, \ + { UNIT_MSIZE, (1u << 25), NULL, "32M", &cpu_set_size }, \ + { UNIT_MSIZE, (1u << 25) + (1u << 24), NULL, "48M", &cpu_set_size }, \ + { UNIT_MSIZE, (1u << 26), NULL, "64M", &cpu_set_size }, \ + { UNIT_MSIZE, (1u << 27), NULL, "128M", &cpu_set_size } /* Unibus I/O registers */ @@ -223,7 +241,7 @@ #define DZ_MUXES 4 /* max # of DZV muxes */ #define DZ_LINES 8 /* lines per DZV mux */ -#define VH_MUXES 4 /* max # of DHQ muxes */ +#define VH_MUXES 4 /* max # of DHU muxes */ #define DLX_LINES 16 /* max # of KL11/DL11's */ #define DCX_LINES 16 /* max # of DC11's */ #define MT_MAXFR (1 << 16) /* magtape max rec */ @@ -231,12 +249,10 @@ #define DEV_V_UBUS (DEV_V_UF + 0) /* Unibus */ #define DEV_V_MBUS (DEV_V_UF + 1) /* Massbus */ #define DEV_V_NEXUS (DEV_V_UF + 2) /* Nexus */ -#define DEV_V_FLTA (DEV_V_UF + 3) /* flt addr */ -#define DEV_V_FFUF (DEV_V_UF + 4) /* first free flag */ +#define DEV_V_FFUF (DEV_V_UF + 3) /* first free flag */ #define DEV_UBUS (1u << DEV_V_UBUS) #define DEV_MBUS (1u << DEV_V_MBUS) #define DEV_NEXUS (1u << DEV_V_NEXUS) -#define DEV_FLTA (1u << DEV_V_FLTA) #define DEV_QBUS (0) #define DEV_Q18 (0) @@ -268,51 +284,11 @@ typedef struct { int32 (*ack[VEC_DEVMAX])(void); /* ack routine */ } DIB; -/* Unibus I/O page layout - XUB,RQB,RQC,RQD float based on number of DZ's +/* Unibus I/O page layout - see pdp11_ui_lib.c for address layout details Massbus devices (RP, TU) do not appear in the Unibus IO page */ -#define IOBA_DZ (IOPAGEBASE + 000100) /* DZ11 */ -#define IOLN_DZ 010 -#define IOBA_XUB (IOPAGEBASE + 000330 + (020 * (DZ_MUXES / 2))) -#define IOLN_XUB 010 -#define IOBA_RQB (IOPAGEBASE + 000334 + (020 * (DZ_MUXES / 2))) -#define IOLN_RQB 004 -#define IOBA_RQC (IOPAGEBASE + IOBA_RQB + IOLN_RQB) -#define IOLN_RQC 004 -#define IOBA_RQD (IOPAGEBASE + IOBA_RQC + IOLN_RQC) -#define IOLN_RQD 004 -#define IOBA_VH (IOPAGEBASE + 000440) /* DHU11 */ -#define IOLN_VH 020 -#define IOBA_RQ (IOPAGEBASE + 012150) /* UDA50 */ -#define IOLN_RQ 004 -#define IOBA_TS (IOPAGEBASE + 012520) /* TS11 */ -#define IOLN_TS 004 -#define IOBA_RL (IOPAGEBASE + 014400) /* RL11 */ -#define IOLN_RL 012 -#define IOBA_XQ (IOPAGEBASE + 014440) /* DEQNA/DELQA */ -#define IOLN_XQ 020 -#define IOBA_XQB (IOPAGEBASE + 014460) /* 2nd DEQNA/DELQA */ -#define IOLN_XQB 020 -#define IOBA_TQ (IOPAGEBASE + 014500) /* TMSCP */ -#define IOLN_TQ 004 -#define IOBA_XU (IOPAGEBASE + 014510) /* DEUNA/DELUA */ -#define IOLN_XU 010 -#define IOBA_CR (IOPAGEBASE + 017160) /* CD/CR/CM */ -#define IOLN_CR 010 -#define IOBA_RX (IOPAGEBASE + 017170) /* RX11 */ -#define IOLN_RX 004 -#define IOBA_RY (IOPAGEBASE + 017170) /* RXV21 */ -#define IOLN_RY 004 -#define IOBA_QDSS (IOPAGEBASE + 017400) /* QDSS */ -#define IOLN_QDSS 002 -#define IOBA_HK (IOPAGEBASE + 017440) /* RK611 */ -#define IOLN_HK 040 -#define IOBA_LPT (IOPAGEBASE + 017514) /* LP11 */ -#define IOLN_LPT 004 -#define IOBA_PTR (IOPAGEBASE + 017550) /* PC11 reader */ -#define IOLN_PTR 004 -#define IOBA_PTP (IOPAGEBASE + 017554) /* PC11 punch */ -#define IOLN_PTP 004 +#define IOBA_AUTO (0) /* Assigned by Auto Configure */ + /* Interrupt assignments; within each level, priority is right to left */ @@ -325,6 +301,8 @@ typedef struct { #define INT_V_TS 6 #define INT_V_RY 7 #define INT_V_XU 8 +#define INT_V_DMCRX 9 +#define INT_V_DMCTX 10 #define INT_V_LPT 0 /* BR4 */ #define INT_V_PTR 1 @@ -348,6 +326,8 @@ typedef struct { #define INT_PTR (1u << INT_V_PTR) #define INT_PTP (1u << INT_V_PTP) #define INT_CR (1u << INT_V_CR) +#define INT_DMCRX (1u << INT_V_DMCRX) +#define INT_DMCTX (1u << INT_V_DMCTX) #define IPL_DZRX (0x15 - IPL_HMIN) #define IPL_DZTX (0x15 - IPL_HMIN) @@ -364,28 +344,16 @@ typedef struct { #define IPL_CR (0x14 - IPL_HMIN) #define IPL_VHRX (0x14 - IPL_HMIN) #define IPL_VHTX (0x14 - IPL_HMIN) +#define IPL_DMCRX (0x15 - IPL_HMIN) +#define IPL_DMCTX (0x15 - IPL_HMIN) /* Device vectors */ +#define VEC_AUTO (0) /* Assigned by Auto Configure */ +#define VEC_FLOAT (0) /* Assigned by Auto Configure */ + #define VEC_QBUS 0 #define VEC_Q 0000 -#define VEC_PTR 0070 -#define VEC_PTP 0074 -#define VEC_XQ 0120 -#define VEC_XU 0120 -#define VEC_RQ 0154 -#define VEC_RL 0160 -#define VEC_LPT 0200 -#define VEC_HK 0210 -#define VEC_TS 0224 -#define VEC_CR 0230 -#define VEC_TQ 0260 -#define VEC_RX 0264 -#define VEC_RY 0264 -#define VEC_DZRX 0300 -#define VEC_DZTX 0304 -#define VEC_VHRX 0310 -#define VEC_VHTX 0314 /* Interrupt macros */ @@ -455,7 +423,6 @@ t_stat mba_show_num (FILE *st, UNIT *uptr, int32 val, void *desc); t_stat show_nexus (FILE *st, UNIT *uptr, int32 val, void *desc); void sbi_set_errcnf (void); -int32 clk_cosched (int32 wait); #include "pdp11_io_lib.h" diff --git a/VAX/vax780_mem.c b/VAX/vax780_mem.c index 2183b832..32996679 100644 --- a/VAX/vax780_mem.c +++ b/VAX/vax780_mem.c @@ -98,7 +98,7 @@ t_stat mctl_wrreg (int32 val, int32 pa, int32 mode); mctlx_reg MCTLx register list */ -DIB mctl0_dib[] = { TR_MCTL0, 0, &mctl_rdreg, &mctl_wrreg, 0 }; +DIB mctl0_dib = { TR_MCTL0, 0, &mctl_rdreg, &mctl_wrreg, 0 }; UNIT mctl0_unit = { UDATA (NULL, 0, 0) }; @@ -117,7 +117,7 @@ MTAB mctl0_mod[] = { { 0 } }; -DIB mctl1_dib[] = { TR_MCTL1, 0, &mctl_rdreg, &mctl_wrreg, 0 }; +DIB mctl1_dib = { TR_MCTL1, 0, &mctl_rdreg, &mctl_wrreg, 0 }; UNIT mctl1_unit = { UDATA (NULL, 0, 0) }; diff --git a/VAX/vax780_sbi.c b/VAX/vax780_sbi.c index 54ac86aa..3eb588ae 100644 --- a/VAX/vax780_sbi.c +++ b/VAX/vax780_sbi.c @@ -36,9 +36,11 @@ #include "vax_defs.h" -#ifndef DONT_USE_INTERNAL_ROM -#include "vax780_vmb_exe.h" -#endif +#ifdef DONT_USE_INTERNAL_ROM +#define BOOT_CODE_FILENAME "vmb.exe" +#else /* !DONT_USE_INTERNAL_ROM */ +#include "vax_vmb_exe.h" /* Defines BOOT_CODE_FILENAME and BOOT_CODE_ARRAY, etc */ +#endif /* DONT_USE_INTERNAL_ROM */ /* 11/780 specific IPRs */ @@ -106,7 +108,8 @@ uint32 sbi_sc = 0; /* SBI silo comparator * uint32 sbi_mt = 0; /* SBI maintenance */ uint32 sbi_er = 0; /* SBI error status */ uint32 sbi_tmo = 0; /* SBI timeout addr */ -char cpu_boot_cmd[CBUFSIZE] = { 0 }; /* boot command */ +int32 sys_model = 0; /* 780 or 785 */ +static char cpu_boot_cmd[CBUFSIZE] = { 0 }; /* boot command */ static t_stat (*nexusR[NEXUS_NUM])(int32 *dat, int32 ad, int32 md); static t_stat (*nexusW[NEXUS_NUM])(int32 dat, int32 ad, int32 md); @@ -133,10 +136,6 @@ extern int32 crd_err, mem_err, hlt_pin; extern int32 tmr_int, tti_int, tto_int; extern jmp_buf save_env; extern int32 p1; -extern int32 sim_switches; -extern DEVICE *sim_devices[]; -extern FILE *sim_log; -extern CTAB *sim_vm_cmd; t_stat sbi_reset (DEVICE *dptr); void sbi_set_tmo (int32 pa); @@ -203,7 +202,7 @@ DEVICE sbi_dev = { CTAB vax780_cmd[] = { { "BOOT", &vax780_boot, RU_BOOT, - "bo{ot} {/R5:flg} boot device\n" }, + "bo{ot} {/R5:flg} boot device\n", &run_cmd_message }, { "FLOAD", &vax780_fload, 0, "fl{oad} {} load file from console floppy\n" }, { NULL } @@ -387,7 +386,10 @@ switch (rg) { break; case MT_SID: /* SID */ - val = VAX780_SID | VAX780_ECO | VAX780_PLANT | VAX780_SN; + if (sys_model) + val = VAX780_SID | VAX785_TYP | VAX780_ECO | VAX780_PLANT | VAX780_SN; + else + val = VAX780_SID | VAX780_TYP | VAX780_ECO | VAX780_PLANT | VAX780_SN; break; default: @@ -666,8 +668,16 @@ if ((strncmp (regptr, "/R5:", 4) == 0) || if (r != SCPE_OK) return r; } -else if (*regptr != 0) - return SCPE_ARG; +else + if (*regptr == '/') { + r5v = (int32) get_uint (regptr + 1, 16, LMASK, &r); + if (r != SCPE_OK) + return r; + } + else { + if (*regptr != 0) + return SCPE_ARG; + } for (i = 0; boot_tab[i].name != NULL; i++) { if (strcmp (dptr->name, boot_tab[i].name) == 0) { R[0] = boot_tab[i].code; @@ -694,30 +704,9 @@ t_stat cpu_boot (int32 unitno, DEVICE *dptr) { t_stat r; -printf ("Loading boot code from vmb.exe\n"); -if (sim_log) - fprintf (sim_log, "Loading boot code from vmb.exe\n"); -r = load_cmd (0, "-O vmb.exe 200"); -if (r != SCPE_OK) { -#ifndef DONT_USE_INTERNAL_ROM - FILE *f; - - if ((f = sim_fopen ("vmb.exe", "wb"))) { - printf ("Saving boot code to vmb.exe\n"); - if (sim_log) - fprintf (sim_log, "Saving boot code to vmb.exe\n"); - sim_fwrite (vax780_vmb_exe, sizeof(vax780_vmb_exe[0]), sizeof(vax780_vmb_exe)/sizeof(vax780_vmb_exe[0]), f); - fclose (f); - printf ("Loading boot code from vmb.exe\n"); - if (sim_log) - fprintf (sim_log, "Loading boot code from vmb.exe\n"); - r = load_cmd (0, "-O vmb.exe 200"); - if (r == SCPE_OK) - SP = PC = 512; - } -#endif +r = cpu_load_bootcode (BOOT_CODE_FILENAME, BOOT_CODE_ARRAY, BOOT_CODE_SIZE, FALSE, 0x200); +if (r != SCPE_OK) return r; - } SP = PC = 512; return SCPE_OK; } @@ -825,3 +814,38 @@ for (i = 0; (dptr = sim_devices[i]) != NULL; i++) { /* loop thru dev */ } /* end for */ return SCPE_OK; } + +t_stat cpu_set_model (UNIT *uptr, int32 val, char *cptr, void *desc) +{ +if (cptr == NULL) return SCPE_ARG; +if (strcmp(cptr, "780") == 0) + sys_model = 0; +else if (strcmp(cptr, "785") == 0) + sys_model = 1; +else + return SCPE_ARG; +return SCPE_OK; +} + +t_stat cpu_print_model (FILE *st) +{ +fprintf (st, "VAX 11/%s", (sys_model ? "785" : "780")); +return SCPE_OK; +} + +t_stat cpu_model_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr) +{ +fprintf (st, "Initial memory size is 8MB.\n\n"); +fprintf (st, "The simulator is booted with the BOOT command:\n\n"); +fprintf (st, " sim> BO{OT} {/R5:flags}\n\n"); +fprintf (st, "where is one of:\n\n"); +fprintf (st, " RPn to boot from rpn\n"); +fprintf (st, " HKn to boot from hkn\n"); +fprintf (st, " RLn to boot from rln\n"); +fprintf (st, " RQn to boot from rqn\n"); +fprintf (st, " RQBn to boot from rqbn\n"); +fprintf (st, " RQCn to boot from rqcn\n"); +fprintf (st, " RQDn to boot from rqdn\n"); +fprintf (st, " TQn to boot from tqn\n\n"); +return SCPE_OK; +} diff --git a/VAX/vax780_stddev.c b/VAX/vax780_stddev.c index ec576050..e75dec32 100644 --- a/VAX/vax780_stddev.c +++ b/VAX/vax780_stddev.c @@ -81,7 +81,7 @@ */ #include "vax_defs.h" - +#include "sim_tmxr.h" /* Terminal definitions */ @@ -110,6 +110,9 @@ #define COMM_WCSV 0153 /* WCS version */ #define COMM_WCSS 0154 /* WCS secondary */ #define COMM_FPLV 0155 /* FPLA version */ +#define COMM_MTCH_785 0153 /* 785 PCS/WCS version */ +#define COMM_WCSP_785 0154 /* 785 WCS version */ +#define COMM_WCSS_785 0155 /* 785 WCS secondary */ #define COMM_DATA 0x300 /* comm data return */ #define MISC_MASK 0xFF /* console data mask */ #define MISC_SWDN 0x1 /* software done */ @@ -217,7 +220,6 @@ int32 fl_bptr = 0; /* buffer pointer */ uint8 comm_region[COMM_LNT] = { 0 }; /* comm region */ -extern int32 sim_switches; extern jmp_buf save_env; t_stat tti_svc (UNIT *uptr); @@ -252,13 +254,13 @@ extern int32 con_halt (int32 code, int32 cc); UNIT tti_unit = { UDATA (&tti_svc, TT_MODE_8B, 0), 0 }; REG tti_reg[] = { - { HRDATA (RXDB, tti_buf, 16) }, - { HRDATA (RXCS, tti_csr, 16) }, - { FLDATA (INT, tti_int, 0) }, - { FLDATA (DONE, tti_csr, CSR_V_DONE) }, - { FLDATA (IE, tti_csr, CSR_V_IE) }, - { DRDATA (POS, tti_unit.pos, T_ADDR_W), PV_LEFT }, - { DRDATA (TIME, tti_unit.wait, 24), PV_LEFT }, + { HRDATAD (RXDB, tti_buf, 16, "last data item processed") }, + { HRDATAD (RXCS, tti_csr, 16, "control/status register") }, + { FLDATAD (INT, tti_int, 0, "interrupt pending flag") }, + { FLDATAD (DONE, tti_csr, CSR_V_DONE, "device done flag (CSR<7>)") }, + { FLDATAD (IE, tti_csr, CSR_V_IE, "interrupt enable flag (CSR<6>)") }, + { DRDATAD (POS, tti_unit.pos, T_ADDR_W, "number of characters input"), PV_LEFT }, + { DRDATAD (TIME, tti_unit.wait, 24, "input polling interval"), PV_LEFT }, { NULL } }; @@ -286,13 +288,13 @@ DEVICE tti_dev = { UNIT tto_unit = { UDATA (&tto_svc, TT_MODE_8B, 0), SERIAL_OUT_WAIT }; REG tto_reg[] = { - { HRDATA (TXDB, tto_buf, 16) }, - { HRDATA (TXCS, tto_csr, 16) }, - { FLDATA (INT, tto_int, 0) }, - { FLDATA (DONE, tto_csr, CSR_V_DONE) }, - { FLDATA (IE, tto_csr, CSR_V_IE) }, - { DRDATA (POS, tto_unit.pos, T_ADDR_W), PV_LEFT }, - { DRDATA (TIME, tto_unit.wait, 24), PV_LEFT + REG_NZ }, + { HRDATAD (TXDB, tto_buf, 16, "last data item processed") }, + { HRDATAD (TXCS, tto_csr, 16, "control/status register") }, + { FLDATAD (INT, tto_int, 0, "interrupt pending flag") }, + { FLDATAD (DONE, tto_csr, CSR_V_DONE, "device done flag (CSR<7>)") }, + { FLDATAD (IE, tto_csr, CSR_V_IE, "interrupt enable flag (CSR<6>)") }, + { DRDATAD (POS, tto_unit.pos, T_ADDR_W, "number of characters output"), PV_LEFT }, + { DRDATAD (TIME, tto_unit.wait, 24, "time from I/O initiation to interrupt"), PV_LEFT + REG_NZ }, { NULL } }; @@ -316,12 +318,14 @@ DEVICE tto_dev = { UNIT clk_unit = { UDATA (&clk_svc, UNIT_IDLE+UNIT_FIX, sizeof(TOY)), CLK_DELAY };/* 100Hz */ REG clk_reg[] = { - { DRDATA (TODR, todr_reg, 32), PV_LEFT }, - { DRDATA (TIME, clk_unit.wait, 24), REG_NZ + PV_LEFT }, - { DRDATA (TPS, clk_tps, 8), REG_HIDDEN + REG_NZ + PV_LEFT }, + { DRDATAD (TODR, todr_reg, 32, "time-of-day register"), PV_LEFT }, + { DRDATAD (TIME, clk_unit.wait, 24, "initial poll interval"), REG_NZ + PV_LEFT }, + { DRDATAD (POLL, tmr_poll, 24, "calibrated poll interval"), REG_NZ + PV_LEFT + REG_HRO }, + { DRDATAD (TPS, clk_tps, 8, "ticks per second (100)"), REG_NZ + PV_LEFT }, #if defined (SIM_ASYNCH_IO) - { DRDATA (LATENCY, sim_asynch_latency, 32), PV_LEFT }, - { DRDATA (INST_LATENCY, sim_asynch_inst_latency, 32), PV_LEFT }, + { DRDATAD (ASYNCH, sim_asynch_enabled, 1, "asynch I/O enabled flag"), PV_LEFT }, + { DRDATAD (LATENCY, sim_asynch_latency, 32, "desired asynch interrupt latency"), PV_LEFT }, + { DRDATAD (INST_LATENCY, sim_asynch_inst_latency, 32, "calibrated instruction latency"), PV_LEFT }, #endif { NULL } }; @@ -337,13 +341,13 @@ DEVICE clk_dev = { UNIT tmr_unit = { UDATA (&tmr_svc, 0, 0) }; /* timer */ REG tmr_reg[] = { - { HRDATA (ICCS, tmr_iccs, 32) }, - { HRDATA (ICR, tmr_icr, 32) }, - { HRDATA (NICR, tmr_nicr, 32) }, - { HRDATA (INCR, tmr_inc, 32), REG_HIDDEN }, - { HRDATA (SAVE, tmr_sav, 32), REG_HIDDEN }, - { FLDATA (USE100HZ, tmr_use_100hz, 0), REG_HIDDEN }, - { FLDATA (INT, tmr_int, 0) }, + { HRDATAD (ICCS, tmr_iccs, 32, "interval timer control and status") }, + { HRDATAD (ICR, tmr_icr, 32, "interval count register") }, + { HRDATAD (NICR, tmr_nicr, 32, "next interval count register") }, + { FLDATAD (INT, tmr_int, 0, "interrupt request") }, + { HRDATA (INCR, tmr_inc, 32), REG_HIDDEN }, + { HRDATA (SAVE, tmr_sav, 32), REG_HIDDEN }, + { FLDATA (USE100HZ, tmr_use_100hz, 0), REG_HIDDEN }, { NULL } }; @@ -367,19 +371,19 @@ UNIT fl_unit = { UDATA (&fl_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_BUFABLE+UNIT_MUSTBUF, FL_SIZE) }; REG fl_reg[] = { - { HRDATA (FNC, fl_fnc, 8) }, - { HRDATA (ES, fl_esr, 8) }, - { HRDATA (ECODE, fl_ecode, 8) }, - { HRDATA (TA, fl_track, 8) }, - { HRDATA (SA, fl_sector, 8) }, - { DRDATA (STATE, fl_state, 4), REG_RO }, - { DRDATA (BPTR, fl_bptr, 7) }, - { DRDATA (CTIME, fl_cwait, 24), PV_LEFT }, - { DRDATA (STIME, fl_swait, 24), PV_LEFT }, - { DRDATA (XTIME, fl_xwait, 24), PV_LEFT }, - { FLDATA (STOP_IOE, fl_stopioe, 0) }, - { BRDATA (DBUF, fl_buf, 16, 8, FL_NUMBY) }, - { BRDATA (COMM, comm_region, 16, 8, COMM_LNT) }, + { HRDATAD (FNC, fl_fnc, 8, "function select") }, + { HRDATAD (ES, fl_esr, 8, "error status") }, + { HRDATAD (ECODE, fl_ecode, 8, "error code") }, + { HRDATAD (TA, fl_track, 8, "track address") }, + { HRDATAD (SA, fl_sector, 8, "sector address") }, + { DRDATAD (PSTATE, fl_state, 4, "protocol state"), REG_RO }, + { DRDATAD (BPTR, fl_bptr, 7, "data buffer pointer") }, + { DRDATAD (CTIME, fl_cwait, 24, "command initiation delay"), PV_LEFT }, + { DRDATAD (STIME, fl_swait, 24, "seek time delay, per track"), PV_LEFT }, + { DRDATAD (XTIME, fl_xwait, 24, "transfer time delay, per byte"), PV_LEFT }, + { FLDATAD (STOP_IOE, fl_stopioe, 0, "stop on I/O error") }, + { BRDATAD (DBUF, fl_buf, 16, 8, FL_NUMBY, "data buffer") }, + { BRDATAD (COMM, comm_region, 16, 8, COMM_LNT, "comm region") }, { NULL } }; @@ -390,7 +394,7 @@ MTAB fl_mod[] = { }; DEVICE fl_dev = { - "RX", &fl_unit, fl_reg, fl_mod, + "RXC", &fl_unit, fl_reg, fl_mod, 1, DEV_RDX, 20, 1, DEV_RDX, 8, NULL, NULL, &fl_reset, NULL, NULL, NULL, @@ -413,7 +417,7 @@ return (tti_csr & RXCS_RD); void rxcs_wr (int32 data) { if ((data & CSR_IE) == 0) - tto_int = 0; + tti_int = 0; else if ((tti_csr & (CSR_DONE + CSR_IE)) == CSR_DONE) tti_int = 1; tti_csr = (tti_csr & ~RXCS_WR) | (data & RXCS_WR); @@ -462,8 +466,7 @@ t_stat tti_svc (UNIT *uptr) { int32 c; -sim_activate (uptr, KBD_WAIT (uptr->wait, clk_cosched (tmr_poll))); - /* continue poll */ +sim_clock_coschedule (uptr, tmxr_poll); /* continue poll */ if ((c = sim_poll_kbd ()) < SCPE_KFLAG) /* no char or error? */ return c; if (c & SCPE_BREAK) /* break? */ @@ -480,6 +483,7 @@ return SCPE_OK; t_stat tti_reset (DEVICE *dptr) { +tmxr_set_console_units (&tti_unit, &tto_unit); tti_buf = 0; tti_csr = 0; tti_int = 0; @@ -666,16 +670,6 @@ else tmr_use_100hz = 1; /* let clk handle */ return; } -/* Clock coscheduling routine */ - -int32 clk_cosched (int32 wait) -{ -int32 t; - -t = sim_is_active (&clk_unit); -return (t? t - 1: wait); -} - /* 100Hz clock reset */ t_stat clk_reset (DEVICE *dptr) @@ -1054,6 +1048,7 @@ return; t_stat fl_reset (DEVICE *dptr) { uint32 i; +extern int32 sys_model; fl_esr = FL_STAINC; fl_ecode = 0; /* clear error */ @@ -1065,10 +1060,18 @@ sim_cancel (&fl_unit); /* cancel drive */ fl_unit.TRACK = 0; for (i = 0; i < COMM_LNT; i++) comm_region[i] = 0; -comm_region[COMM_FPLV] = VER_FPLA; -comm_region[COMM_PCSV] = VER_PCS; -comm_region[COMM_WCSV] = VER_WCSP; -comm_region[COMM_WCSS] = VER_WCSS; +if (sys_model) { /* 785 */ + comm_region[COMM_WCSS_785] = VER_WCSS_785; + comm_region[COMM_WCSP_785] = VER_WCSP_785; + comm_region[COMM_MTCH_785] = VER_MTCH_785; + comm_region[COMM_PCSV] = VER_PCS_785; + } +else { /* 780 */ + comm_region[COMM_FPLV] = VER_FPLA; + comm_region[COMM_PCSV] = VER_PCS; + comm_region[COMM_WCSV] = VER_WCSP; + comm_region[COMM_WCSS] = VER_WCSS; + } comm_region[COMM_GH] = 1; return SCPE_OK; } diff --git a/VAX/vax780_syslist.c b/VAX/vax780_syslist.c index 9025f616..e86c6900 100644 --- a/VAX/vax780_syslist.c +++ b/VAX/vax780_syslist.c @@ -54,8 +54,8 @@ extern DEVICE tu_dev; extern DEVICE dz_dev; extern DEVICE vh_dev; extern DEVICE xu_dev, xub_dev; +extern DEVICE dmc_dev[]; -extern int32 sim_switches; extern UNIT cpu_unit; extern void WriteB (uint32 pa, int32 val); extern void rom_wr_B (int32 pa, int32 val); @@ -91,6 +91,10 @@ DEVICE *sim_devices[] = { &tq_dev, &xu_dev, &xub_dev, + &dmc_dev[0], + &dmc_dev[1], + &dmc_dev[2], + &dmc_dev[3], NULL }; diff --git a/VAX/vax780_uba.c b/VAX/vax780_uba.c index bb6105fe..695ede53 100644 --- a/VAX/vax780_uba.c +++ b/VAX/vax780_uba.c @@ -179,11 +179,8 @@ int32 autcon_enb = 1; /* autoconfig enable */ extern int32 trpirq; extern int32 autcon_enb; extern jmp_buf save_env; -extern DEVICE *sim_devices[]; extern UNIT cpu_unit; extern uint32 nexus_req[NEXUS_HLVL]; -extern int32 sim_switches; -extern FILE *sim_log, *sim_deb; t_stat uba_svc (UNIT *uptr); t_stat uba_reset (DEVICE *dptr); diff --git a/VAX/vax780_mba.c b/VAX/vax7x0_mba.c similarity index 73% rename from VAX/vax780_mba.c rename to VAX/vax7x0_mba.c index afe264c4..b0d90496 100644 --- a/VAX/vax780_mba.c +++ b/VAX/vax7x0_mba.c @@ -1,4 +1,4 @@ -/* vax780_mba.c: VAX 11/780 Massbus adapter +/* vax7x0_mba.c: VAX 11/780 snf VAX 11/750 Massbus adapter Copyright (c) 2004-2008, Robert M Supnik @@ -49,6 +49,8 @@ #define MBA_EXTDRV(x) (((x) >> MBA_V_DRV) & MBA_M_DRV) #define MBA_EXTOFS(x) (((x) >> MBA_V_DEVOFS) & MBA_M_DEVOFS) +char *mba_regnames[] = {"CNF", "CR", "SR", "VA", "BC", "DR", "SMR", "CMD"}; + /* Massbus configuration register */ #define MBACNF_OF 0x0 @@ -58,6 +60,22 @@ #define MBACNF_RD (SBI_FAULTS|MBACNF_W1C) #define MBACNF_W1C 0x00C00000 +BITFIELD mba_cnf_bits[] = { + BITF(CODE,8), /* Adapter Code */ + BITNCF(13), /* 08:20 Reserved */ + BIT(OT), /* Over Temperature */ + BIT(PU), /* Power Up */ + BIT(PD), /* Power Down */ + BITNCF(2), /* 24:25 Reserved */ + BIT(XMTFLT), /* Transmit Fault */ + BIT(MT), /* Multiple Transmitter */ + BITNCF(1), /* 28 Reserved */ + BIT(URD), /* Unexpected Read Data */ + BIT(WS), /* Write Data Sequence (Fault B) */ + BIT(PE), /* SBI Parity Error */ + ENDBITS +}; + /* Control register */ #define MBACR_OF 0x1 @@ -68,6 +86,15 @@ #define MBACR_RD 0x0000000E #define MBACR_WR 0x0000000E +BITFIELD mba_cr_bits[] = { + BIT(INIT), /* Initialization */ + BIT(ABORT), /* Abort Data Transfer */ + BIT(IE), /* Interrupt Enable */ + BIT(MM), /* Maintenance Mode */ + BITNCF(28), /* 04:31 Reserved */ + ENDBITS +}; + /* Status register */ #define MBASR_OF 0x2 @@ -100,33 +127,98 @@ #define MBASR_ERRORS 0x608E49FF #define MBASR_INTR 0x000F7000 +BITFIELD mba_sr_bits[] = { + BIT(RDTIMEOUT), /* Read Data Timeout */ + BIT(ISTIMEOUT), /* Interface Sequence Timeout */ + BIT(RDS), /* Read Data Substitute */ + BIT(ERRCONF), /* Error Confirmation */ + BIT(INVMAP), /* Invalid Map */ + BIT(MAPPE), /* Page Frame Map Parity Error */ + BIT(MDPE), /* Massbus Data Parity Error */ + BIT(MBEXC), /* Massbus Exception */ + BIT(MXF), /* Missed Transfer Error */ + BIT(WCLWRERR), /* Write Check Lower Byte Error */ + BIT(WCUPERR), /* Write Check Upper Byte Error */ + BIT(DLT), /* Data Late */ + BIT(DTABT), /* Data Transfer Aborted */ + BIT(DTCOMP), /* Data Transfer Complete */ + BITNCF(2), /* 14:15 Reserved */ + BIT(ATTN), /* Attention */ + BIT(MCPE), /* Massbus Control Parity Error */ + BIT(NED), /* Non Existing Drive */ + BIT(PGE), /* Programming Error */ + BITNCF(9), /* 20:28 Reserved */ + BIT(CRD), /* Corrected Read Data */ + BIT(NRCONF), /* No Response Confirmation */ + BIT(DTBUSY), /* Data Transfer Busy */ + ENDBITS +}; + /* Virtual address register */ #define MBAVA_OF 0x3 #define MBAVA_RD 0x0001FFFF #define MBAVA_WR (MBAVA_RD) +BITFIELD mba_va_bits[] = { + BITF(PAGEBYTE,9), /* Page Byte Address */ + BITF(MAPPOINTER,8), /* Map Pointer */ + ENDBITS +}; + /* Byte count */ #define MBABC_OF 0x4 #define MBABC_WR 0x0000FFFF #define MBABC_V_MBC 16 /* MB count */ +BITFIELD mba_bc_bits[] = { + BITF(SBIBYTECOUNT,16), /* SBI Byte Counter */ + BITF(MBBYTECOUNT,16), /* Massbus Byte Counter */ + ENDBITS +}; + /* Diagnostic register */ #define MBADR_OF 0x5 #define MBADR_RD 0xFFFFFFFF #define MBADR_WR 0xFFC00000 +BITFIELD mba_dr_bits[] = { + BITF(DR,32), /* Diagnostic Register */ + ENDBITS +}; + /* Selected map entry - read only */ #define MBASMR_OF 0x6 #define MBASMR_RD (MBAMAP_RD) +BITFIELD mba_smr_bits[] = { + BITF(SMR,32), /* Selected Map Register */ + ENDBITS +}; + /* Command register (SBI) - read only */ #define MBACMD_OF 0x7 +BITFIELD mba_cmd_bits[] = { + BITF(CAR,32), /* Command Address Register */ + ENDBITS +}; + +BITFIELD *mba_reg_bits[] = { + mba_cnf_bits, + mba_cr_bits, + mba_sr_bits, + mba_va_bits, + mba_bc_bits, + mba_dr_bits, + mba_smr_bits, + mba_cmd_bits +}; + /* External registers */ #define MBA_CS1 0x00 /* device CSR1 */ @@ -148,6 +240,7 @@ #define MBA_DEB_MWR 0x08 /* map writes */ #define MBA_DEB_XFR 0x10 /* transfers */ #define MBA_DEB_ERR 0x20 /* errors */ +#define MBA_DEB_INT 0x40 /* interrupts */ uint32 mba_cnf[MBA_NUM]; /* config reg */ uint32 mba_cr[MBA_NUM]; /* control reg */ @@ -160,9 +253,6 @@ uint32 mba_map[MBA_NUM][MBA_NMAPR]; /* map */ extern uint32 nexus_req[NEXUS_HLVL]; extern UNIT cpu_unit; -extern FILE *sim_log; -extern FILE *sim_deb; -extern int32 sim_switches; t_stat mba_reset (DEVICE *dptr); t_stat mba_rdreg (int32 *val, int32 pa, int32 mode); @@ -191,15 +281,15 @@ DIB mba0_dib = { TR_MBA0, 0, &mba_rdreg, &mba_wrreg, 0, NVCL (MBA0) }; UNIT mba0_unit = { UDATA (NULL, 0, 0) }; REG mba0_reg[] = { - { HRDATA (CNFR, mba_cnf[0], 32) }, - { HRDATA (CR, mba_cr[0], 4) }, - { HRDATA (SR, mba_sr[0], 32) }, - { HRDATA (VA, mba_va[0], 17) }, - { HRDATA (BC, mba_bc[0], 16) }, - { HRDATA (DR, mba_dr[0], 32) }, - { HRDATA (SMR, mba_dr[0], 32) }, - { BRDATA (MAP, mba_map[0], 16, 32, MBA_NMAPR) }, - { FLDATA (NEXINT, nexus_req[IPL_MBA0], TR_MBA0) }, + { HRDATAD (CNFR, mba_cnf[0], 32, "config register") }, + { HRDATAD (CR, mba_cr[0], 4, "control register") }, + { HRDATAD (SR, mba_sr[0], 32, "status register") }, + { HRDATAD (VA, mba_va[0], 17, "virtual address register") }, + { HRDATAD (BC, mba_bc[0], 16, "byte count register") }, + { HRDATAD (DR, mba_dr[0], 32, "diag register") }, + { HRDATAD (SMR, mba_dr[0], 32, "sel map register") }, + { BRDATAD (MAP, mba_map[0], 16, 32, MBA_NMAPR, "map registers") }, + { FLDATAD (NEXINT, nexus_req[IPL_MBA0], TR_MBA0, "nexus interrupt request") }, { NULL } }; @@ -220,15 +310,15 @@ MTAB mba1_mod[] = { }; REG mba1_reg[] = { - { HRDATA (CNFR, mba_cnf[1], 32) }, - { HRDATA (CR, mba_cr[1], 4) }, - { HRDATA (SR, mba_sr[1], 32) }, - { HRDATA (VA, mba_va[1], 17) }, - { HRDATA (BC, mba_bc[1], 16) }, - { HRDATA (DR, mba_dr[1], 32) }, - { HRDATA (SMR, mba_dr[1], 32) }, - { BRDATA (MAP, mba_map[1], 16, 32, MBA_NMAPR) }, - { FLDATA (NEXINT, nexus_req[IPL_MBA1], TR_MBA1) }, + { HRDATAD (CNFR, mba_cnf[1], 32, "config register") }, + { HRDATAD (CR, mba_cr[1], 4, "control register") }, + { HRDATAD (SR, mba_sr[1], 32, "status register") }, + { HRDATAD (VA, mba_va[1], 17, "virtual address register") }, + { HRDATAD (BC, mba_bc[1], 16, "byte count register") }, + { HRDATAD (DR, mba_dr[1], 32, "diag register") }, + { HRDATAD (SMR, mba_dr[1], 32, "sel map register") }, + { BRDATAD (MAP, mba_map[1], 16, 32, MBA_NMAPR, "map registers") }, + { FLDATAD (NEXINT, nexus_req[IPL_MBA1], TR_MBA1, "nexus interrupt request") }, { NULL } }; @@ -239,6 +329,7 @@ DEBTAB mba_deb[] = { { "MAPWRITE", MBA_DEB_MWR }, { "XFER", MBA_DEB_XFR }, { "ERROR", MBA_DEB_ERR }, + { "INTERRUPT", MBA_DEB_INT }, { NULL, 0 } }; @@ -271,8 +362,10 @@ t_stat r; mb = NEXUS_GETNEX (pa) - TR_MBA0; /* get MBA */ if ((pa & 3) || (lnt != L_LONG)) { /* unaligned or not lw? */ - printf (">>MBA%d: invalid adapter read mask, pa = %X, lnt = %d\r\n", mb, pa, lnt); + printf (">>MBA%d: invalid adapter read mask, pa = 0x%X, lnt = %d\r\n", mb, pa, lnt); +#if defined(VAX_780) sbi_set_errcnf (); /* err confirmation */ +#endif return SCPE_OK; } if (mb >= MBA_NUM) /* valid? */ @@ -321,8 +414,8 @@ switch (rtype) { /* case on type */ default: return SCPE_NXM; } - if (DEBUG_PRI (mba_dev[mb], MBA_DEB_RRD)) - fprintf (sim_deb, ">>MBA%d: int reg %d read, value = %X\n", mb, ofs, *val); + sim_debug (MBA_DEB_RRD, &mba_dev[mb], "mba_rdreg(Reg=%s, val=0x%X)\n", mba_regnames[ofs], *val); + sim_debug_bits(MBA_DEB_RRD, &mba_dev[mb], mba_reg_bits[ofs], *val, *val, 1); break; case MBART_EXT: /* external */ @@ -336,15 +429,13 @@ switch (rtype) { /* case on type */ else if (r == MBE_NXR) /* nx reg? */ return SCPE_NXM; *val |= (mba_sr[mb] & ~WMASK); /* upper 16b from SR */ - if (DEBUG_PRI (mba_dev[mb], MBA_DEB_RRD)) - fprintf (sim_deb, ">>MBA%d: drv %d ext reg %d read, value = %X\n", mb, drv, ofs, *val); + sim_debug (MBA_DEB_RRD, &mba_dev[mb], "mba_rdreg(drv %d ext reg=%d, val=0x%X)\n", drv, ofs, *val); break; case MBART_MAP: /* map */ ofs = MBA_INTOFS (pa); *val = mba_map[mb][ofs] & MBAMAP_RD; - if (DEBUG_PRI (mba_dev[mb], MBA_DEB_MRD)) - fprintf (sim_deb, ">>MBA%d: map %d read, value = %X\n", mb, ofs, *val); + sim_debug (MBA_DEB_MRD, &mba_dev[mb], "mba_rdreg(map %d read, val=0x%X)\n", ofs, *val); break; default: @@ -359,30 +450,40 @@ return SCPE_OK; t_stat mba_wrreg (int32 val, int32 pa, int32 lnt) { int32 mb, ofs, drv, rtype; +uint32 old_reg, old_sr; t_stat r; t_bool cs1dt; mb = NEXUS_GETNEX (pa) - TR_MBA0; /* get MBA */ if ((pa & 3) || (lnt != L_LONG)) { /* unaligned or not lw? */ - printf (">>MBA%d: invalid adapter write mask, pa = %X, lnt = %d\r\n", mb, pa, lnt); + printf (">>MBA%d: invalid adapter write mask, pa = 0x%X, lnt = %d\r\n", mb, pa, lnt); +#if defined(VAX_780) sbi_set_errcnf (); /* err confirmation */ +#endif return SCPE_OK; } if (mb >= MBA_NUM) /* valid? */ return SCPE_NXM; rtype = MBA_RTYPE (pa); /* get reg type */ +old_sr = mba_sr[mb]; + switch (rtype) { /* case on type */ case MBART_INT: /* internal */ ofs = MBA_INTOFS (pa); /* check range */ + sim_debug (MBA_DEB_RWR, &mba_dev[mb], "mba_wrreg(reg=%s write, val=0x%X)\n", mba_regnames[ofs], val); + switch (ofs) { case MBACNF_OF: /* CNF */ + old_reg = mba_cnf[mb]; mba_cnf[mb] &= ~(val & MBACNF_W1C); + sim_debug_bits(MBA_DEB_RWR, &mba_dev[mb], mba_reg_bits[ofs], old_reg, mba_cnf[mb], 1); break; case MBACR_OF: /* CR */ + old_reg = mba_cr[mb]; if (val & MBACR_INIT) /* init? */ mba_reset (&mba_dev[mb]); /* reset MBA */ if ((val & MBACR_ABORT) && @@ -400,6 +501,7 @@ switch (rtype) { /* case on type */ mba_clr_int (mb); mba_cr[mb] = (mba_cr[mb] & ~MBACR_WR) | (val & MBACR_WR); + sim_debug_bits(MBA_DEB_RWR, &mba_dev[mb], mba_reg_bits[ofs], old_reg, mba_cr[mb], 1); break; case MBASR_OF: /* SR */ @@ -407,27 +509,32 @@ switch (rtype) { /* case on type */ break; case MBAVA_OF: /* VA */ + old_reg = mba_va[mb]; + sim_debug_bits(MBA_DEB_RWR, &mba_dev[mb], mba_reg_bits[ofs], mba_va[mb], val, 1); if (mba_sr[mb] & MBASR_DTBUSY) /* err if xfr */ mba_upd_sr (MBASR_PGE, 0, mb); else mba_va[mb] = val & MBAVA_WR; + sim_debug_bits(MBA_DEB_RWR, &mba_dev[mb], mba_reg_bits[ofs], old_reg, mba_va[mb], 1); break; case MBABC_OF: /* BC */ + old_reg = mba_bc[mb]; if (mba_sr[mb] & MBASR_DTBUSY) /* err if xfr */ mba_upd_sr (MBASR_PGE, 0, mb); else mba_bc[mb] = val & MBABC_WR; + sim_debug_bits(MBA_DEB_RWR, &mba_dev[mb], mba_reg_bits[ofs], old_reg, mba_bc[mb], 1); break; case MBADR_OF: /* DR */ + old_reg = mba_dr[mb]; mba_dr[mb] = (mba_dr[mb] & ~MBADR_WR) | (val & MBADR_WR); + sim_debug_bits(MBA_DEB_RWR, &mba_dev[mb], mba_reg_bits[ofs], old_reg, mba_dr[mb], 1); break; default: return SCPE_NXM; } - if (DEBUG_PRI (mba_dev[mb], MBA_DEB_RWR)) - fprintf (sim_deb, ">>MBA%d: int reg %d write, value = %X\n", mb, ofs, val); break; case MBART_EXT: /* external */ @@ -435,6 +542,7 @@ switch (rtype) { /* case on type */ return SCPE_NXM; drv = MBA_EXTDRV (pa); /* get dev num */ ofs = MBA_EXTOFS (pa); /* get reg offs */ + sim_debug (MBA_DEB_RWR, &mba_dev[mb], "mba_wrreg(drv=%d ext reg=%d write, val=0x%X)\n", drv, ofs, val); cs1dt = (ofs == MBA_CS1) && (val & CSR_GO) && /* starting xfr? */ ((val & MBA_CS1_WR) >= MBA_CS1_DT); if (cs1dt && (mba_sr[mb] & MBASR_DTBUSY)) { /* xfr while busy? */ @@ -448,21 +556,21 @@ switch (rtype) { /* case on type */ return SCPE_NXM; if (cs1dt && (r == SCPE_OK)) /* did dt start? */ mba_sr[mb] = (mba_sr[mb] | MBASR_DTBUSY) & ~MBASR_W1C; - if (DEBUG_PRI (mba_dev[mb], MBA_DEB_RWR)) - fprintf (sim_deb, ">>MBA%d: drv %d ext reg %d write, value = %X\n", mb, drv, ofs, val); break; case MBART_MAP: /* map */ ofs = MBA_INTOFS (pa); mba_map[mb][ofs] = val & MBAMAP_WR; - if (DEBUG_PRI (mba_dev[mb], MBA_DEB_MWR)) - fprintf (sim_deb, ">>MBA%d: map %d write, value = %X\n", mb, ofs, val); + sim_debug (MBA_DEB_MWR, &mba_dev[mb], "mba_wrreg(map %d write, val=0x%X)\n", ofs, val); break; default: return SCPE_NXM; } +if (old_sr != mba_sr[mb]) + sim_debug_bits(MBA_DEB_RWR, &mba_dev[mb], mba_sr_bits, old_sr, mba_sr[mb], 1); + return SCPE_OK; } @@ -496,8 +604,7 @@ for (i = 0; i < bc; i = i + pbc) { /* loop by pages */ pbc = VA_PAGSIZE - VA_GETOFF (pa); /* left in page */ if (pbc > (bc - i)) /* limit to rem xfr */ pbc = bc - i; - if (DEBUG_PRI (mba_dev[mb], MBA_DEB_XFR)) - fprintf (sim_deb, ">>MBA%d: read, pa = %X, bc = %X\n", mb, pa, pbc); + sim_debug (MBA_DEB_XFR, &mba_dev[mb], "mba_rdbufW(pa=0x%X, bc=0x%X)\n", pa, pbc); if ((pa | pbc) & 1) { /* aligned word? */ for (j = 0; j < pbc; pa++, j++) { /* no, bytes */ if ((i + j) & 1) { /* odd byte? */ @@ -546,8 +653,7 @@ for (i = 0; i < bc; i = i + pbc) { /* loop by pages */ pbc = VA_PAGSIZE - VA_GETOFF (pa); /* left in page */ if (pbc > (bc - i)) /* limit to rem xfr */ pbc = bc - i; - if (DEBUG_PRI (mba_dev[mb], MBA_DEB_XFR)) - fprintf (sim_deb, ">>MBA%d: write, pa = %X, bc = %X\n", mb, pa, pbc); + sim_debug (MBA_DEB_XFR, &mba_dev[mb], "mba_wrbufW(pa=0x%X, bc=0x%X)\n", pa, pbc); if ((pa | pbc) & 1) { /* aligned word? */ for (j = 0; j < pbc; pa++, j++) { /* no, bytes */ if ((i + j) & 1) { @@ -595,8 +701,7 @@ for (i = 0; i < bc; i = i + pbc) { /* loop by pages */ break; } pbc = VA_PAGSIZE - VA_GETOFF (pa); /* left in page */ - if (DEBUG_PRI (mba_dev[mb], MBA_DEB_XFR)) - fprintf (sim_deb, ">>MBA%d: check, pa = %X, bc = %X\n", mb, pa, pbc); + sim_debug (MBA_DEB_XFR, &mba_dev[mb], "mba_chbufW(pa=0x%X, bc=0x%X)\n", pa, pbc); if (pbc > (bc - i)) /* limit to rem xfr */ pbc = bc - i; for (j = 0; j < pbc; j++, pa++) { /* byte by byte */ @@ -635,23 +740,30 @@ return 0; void mba_set_don (uint32 mb) { +uint32 old_sr = mba_sr[mb]; + mba_upd_sr (MBASR_DTCMP, 0, mb); +if (old_sr != mba_sr[mb]) + sim_debug_bits(MBA_DEB_RWR, &mba_dev[mb], mba_sr_bits, old_sr, mba_sr[mb], 1); return; } void mba_upd_ata (uint32 mb, uint32 val) { +uint32 old_sr = mba_sr[mb]; + if (val) mba_upd_sr (MBASR_ATA, 0, mb); else mba_upd_sr (0, MBASR_ATA, mb); +if (old_sr != mba_sr[mb]) + sim_debug_bits(MBA_DEB_RWR, &mba_dev[mb], mba_sr_bits, old_sr, mba_sr[mb], 1); return; } void mba_set_exc (uint32 mb) { +sim_debug (MBA_DEB_ERR, &mba_dev[mb], "mba_set_exc(EXC write)\n"); mba_upd_sr (MBASR_MBEXC, 0, mb); -if (DEBUG_PRI (mba_dev[mb], MBA_DEB_ERR)) - fprintf (sim_deb, ">>MBA%d: EXC write\n", mb); return; } @@ -669,8 +781,10 @@ DIB *dibp; if (mb >= MBA_NUM) return; dibp = (DIB *) mba_dev[mb].ctxt; -if (dibp) +if (dibp) { nexus_req[dibp->vloc >> 5] |= (1u << (dibp->vloc & 0x1F)); + sim_debug (MBA_DEB_INT, &mba_dev[mb], "mba_set_int(0x%X)\n", dibp->vloc); + } return; } @@ -681,24 +795,32 @@ DIB *dibp; if (mb >= MBA_NUM) return; dibp = (DIB *) mba_dev[mb].ctxt; -if (dibp) +if (dibp) { nexus_req[dibp->vloc >> 5] &= ~(1u << (dibp->vloc & 0x1F)); + sim_debug (MBA_DEB_INT, &mba_dev[mb], "mba_clr_int(0x%X)\n", dibp->vloc); + } return; } void mba_upd_sr (uint32 set, uint32 clr, uint32 mb) { +uint32 o_sr; + if (mb >= MBA_NUM) return; +o_sr = mba_sr[mb]; if (set & MBASR_ABORTS) set |= (MBASR_DTCMP|MBASR_DTABT); if (set & (MBASR_DTCMP|MBASR_DTABT)) mba_sr[mb] &= ~MBASR_DTBUSY; mba_sr[mb] = (mba_sr[mb] | set) & ~clr; -if ((set & MBASR_INTR) && (mba_cr[mb] & MBACR_IE)) +if (mba_sr[mb] != o_sr) + sim_debug_bits(MBA_DEB_RWR, &mba_dev[mb], mba_sr_bits, o_sr, mba_sr[mb], 1); +if ((set & MBASR_INTR) && (mba_cr[mb] & MBACR_IE) && !(mba_sr[mb] & MBASR_DTBUSY)) mba_set_int (mb); -if ((set & MBASR_ERRORS) && (DEBUG_PRI (mba_dev[mb], MBA_DEB_ERR))) - fprintf (sim_deb, ">>MBA%d: CS error = %X\n", mb, mba_sr[mb]); +if (set & MBASR_ERRORS) { + sim_debug (MBA_DEB_ERR, &mba_dev[mb], "mba_upd_sr(CS error=0x%X)\n", mba_sr[mb]); + } return; } diff --git a/VAX/vax860_abus.c b/VAX/vax860_abus.c new file mode 100644 index 00000000..1210966d --- /dev/null +++ b/VAX/vax860_abus.c @@ -0,0 +1,751 @@ +/* vax860_abus.c: VAX 8600 A-Bus + + Copyright (c) 2011-2012, Matt Burke + This module incorporates code from SimH, Copyright (c) 2004-2008, Robert M Supnik + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name(s) of the author(s) shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from the author(s). + + abus bus controller + + 26-Dec-2012 MB First Version +*/ + +#include "vax_defs.h" + +#ifdef DONT_USE_INTERNAL_ROM +#define BOOT_CODE_FILENAME "vmb.exe" +#else /* !DONT_USE_INTERNAL_ROM */ +#include "vax_vmb_exe.h" /* Defines BOOT_CODE_FILENAME and BOOT_CODE_ARRAY, etc */ +#endif /* DONT_USE_INTERNAL_ROM */ + +/* SBIA registers */ + +#define SBIER_TMO 0x00001000 /* timeout */ +#define SBIER_STA 0x00000C00 /* timeout status (0) */ +#define SBIER_CNF 0x00000100 /* error confirm */ +#define SBIER_MULT 0x00000004 /* multiple errors */ +#define SBIER_TMOW1C (SBIER_TMO|SBIER_STA|SBIER_CNF|SBIER_MULT) + +/* PAMM */ + +#define PAMM_IOA0 0x18 /* I/O adapter 0 */ +#define PAMM_IOA1 0x19 /* I/O adapter 1 */ +#define PAMM_IOA2 0x1A /* I/O adapter 2 */ +#define PAMM_IOA3 0x1B /* I/O adapter 3 */ +#define PAMM_NXM 0x1F /* Non-existant address */ + +#define PAMACC_ADDR 0x3FF00000 /* PAMM address */ +#define PAMACC_CODE 0x0000001F /* Configuration code */ + +#define PAMLOC_ADDR 0x3FF00000 /* PAMM address */ + +/* MBOX registers */ + +#define MSTAT1_V_CYC 26 /* MBOX cycle type */ +#define MSTAT1_M_CYC 0xF +#define MSTAT1_CPRD 0xE /* CP read */ + +#define MSTAT2_NXM 0x00000008 /* CP NXM */ + +#define MERG_V_MME 8 /* Mem mgmt en */ + +#define MDCTL_RW 0x00006F0F /* MBOX data control */ + +/* EBOX registers */ + +#define EBCS_MFTL 0x00008000 /* MBOX fatal error */ + +#define EHMSTS_PROCA 0x00020000 /* Process abort */ + +#define EHSR_VMSE 0x00000020 /* VMS entered */ + +/* VAX 8600 boot device definitions */ + +struct boot_dev { + char *name; + int32 code; + int32 let; + }; + +uint32 nexus_req[NEXUS_HLVL]; /* nexus int req */ +uint32 pamloc = 0; +uint32 cswp = 0; +uint32 ehsr = 0; +uint32 mdctl = 0; +int32 sys_model = 0; +char cpu_boot_cmd[CBUFSIZE] = { 0 }; /* boot command */ + +static struct boot_dev boot_tab[] = { + { "RP", BOOT_MB, 0 }, + { "HK", BOOT_HK, 0 }, + { "RL", BOOT_RL, 0 }, + { "RQ", BOOT_UDA, 1 << 24 }, + { "RQB", BOOT_UDA, 1 << 24 }, + { "RQC", BOOT_UDA, 1 << 24 }, + { "RQD", BOOT_UDA, 1 << 24 }, + { "TQ", BOOT_TK, 1 << 24 }, + { "CS", BOOT_CS, 0 }, + { NULL } + }; + +extern int32 R[16]; +extern int32 PSL; +extern int32 ASTLVL, SISR; +extern int32 mapen, pme, trpirq; +extern int32 in_ie; +extern int32 mchk_va, mchk_ref; +extern int32 crd_err, mem_err, hlt_pin; +extern int32 tmr_int, tti_int, tto_int, csi_int; +extern uint32 sbi_er; +extern jmp_buf save_env; +extern int32 p1; +extern int32 fault_PC; /* fault PC */ +extern UNIT cpu_unit; + +void uba_eval_int (void); +t_stat abus_reset (DEVICE *dptr); +t_stat vax860_boot (int32 flag, char *ptr); +t_stat vax860_boot_parse (int32 flag, char *ptr); +t_stat cpu_boot (int32 unitno, DEVICE *dptr); + +extern t_stat (*nexusR[NEXUS_NUM])(int32 *dat, int32 ad, int32 md); +extern t_stat (*nexusW[NEXUS_NUM])(int32 dat, int32 ad, int32 md); +extern int32 intexc (int32 vec, int32 cc, int32 ipl, int ei); +extern int32 iccs_rd (void); +extern int32 nicr_rd (void); +extern int32 icr_rd (t_bool interp); +extern int32 todr_rd (void); +extern int32 rxcs_rd (void); +extern int32 rxdb_rd (void); +extern int32 txcs_rd (void); +extern int32 stxcs_rd (void); +extern int32 stxdb_rd (void); +extern void iccs_wr (int32 dat); +extern void nicr_wr (int32 dat); +extern void todr_wr (int32 dat); +extern void rxcs_wr (int32 dat); +extern void txcs_wr (int32 dat); +extern void txdb_wr (int32 dat); +extern void stxcs_wr (int32 data); +extern void stxdb_wr (int32 data); +extern void init_mbus_tab (void); +extern void init_ubus_tab (void); +extern void init_nexus_tab (void); +extern t_stat build_mbus_tab (DEVICE *dptr, DIB *dibp); +extern t_stat build_ubus_tab (DEVICE *dptr, DIB *dibp); +extern t_stat build_nexus_tab (DEVICE *dptr, DIB *dibp); +extern void sbi_set_tmo (int32 pa); +extern int32 sbia_rd (int32 pa, int32 lnt); +extern void sbia_wr (int32 pa, int32 val, int32 lnt); +extern t_stat sbi_rd (int32 pa, int32 *val, int32 lnt); +extern t_stat sbi_wr (int32 pa, int32 val, int32 lnt); + +/* ABUS data structures + + abus_dev A-Bus device descriptor + abus_unit A-Bus unit + abus_reg A-Bus register list +*/ + +UNIT abus_unit = { UDATA (NULL, 0, 0) }; + +REG abus_reg[] = { + { NULL } + }; + +DEVICE abus_dev = { + "ABUS", &abus_unit, abus_reg, NULL, + 1, 16, 16, 1, 16, 8, + NULL, NULL, &abus_reset, + NULL, NULL, NULL, + NULL, 0 + }; + +/* Special boot command, overrides regular boot */ + +CTAB vax860_cmd[] = { + { "BOOT", &vax860_boot, RU_BOOT, + "bo{ot} {/R5:flg} boot device\n", &run_cmd_message }, + { NULL } + }; + +/* The VAX 8600 has three sources of interrupts + + - internal device interrupts (CPU, console, clock) + - nexus interupts (e.g. MBA, UBA) + - external device interrupts (Unibus) + + Internal devices vector to fixed SCB locations. + + Nexus interrupts vector to an SCB location based on this + formula: SCB_NEXUS + ((IPL - 0x14) * 0x40) + (TR# * 0x4) + + External device interrupts do not vector directly. + Instead, the interrupt handler for a given UBA IPL + reads a vector register that contains the Unibus vector + for that IPL. */ + +/* Find highest priority vectorable interrupt */ + +int32 eval_int (void) +{ +int32 ipl = PSL_GETIPL (PSL); +int32 i, t; + +static const int32 sw_int_mask[IPL_SMAX] = { + 0xFFFE, 0xFFFC, 0xFFF8, 0xFFF0, /* 0 - 3 */ + 0xFFE0, 0xFFC0, 0xFF80, 0xFF00, /* 4 - 7 */ + 0xFE00, 0xFC00, 0xF800, 0xF000, /* 8 - B */ + 0xE000, 0xC000, 0x8000 /* C - E */ + }; + +if (hlt_pin) /* hlt pin int */ + return IPL_HLTPIN; +if ((ipl < IPL_MEMERR) && mem_err) /* mem err int */ + return IPL_MEMERR; +if ((ipl < IPL_CRDERR) && crd_err) /* crd err int */ + return IPL_CRDERR; +if ((ipl < IPL_CLKINT) && tmr_int) /* clock int */ + return IPL_CLKINT; +uba_eval_int (); /* update UBA */ +for (i = IPL_HMAX; i >= IPL_HMIN; i--) { /* chk hwre int */ + if (i <= ipl) /* at ipl? no int */ + return 0; + if (nexus_req[i - IPL_HMIN]) /* req != 0? int */ + return i; + } +if ((ipl < IPL_TTINT) && (tti_int || tto_int || csi_int)) /* console int */ + return IPL_TTINT; +if (ipl >= IPL_SMAX) /* ipl >= sw max? */ + return 0; +if ((t = SISR & sw_int_mask[ipl]) == 0) + return 0; /* eligible req */ +for (i = IPL_SMAX; i > ipl; i--) { /* check swre int */ + if ((t >> i) & 1) /* req != 0? int */ + return i; + } +return 0; +} + +/* Return vector for highest priority hardware interrupt at IPL lvl */ + +int32 get_vector (int32 lvl) +{ +int32 i, l; + +if (lvl == IPL_MEMERR) { /* mem error? */ + mem_err = 0; + return SCB_MEMERR; + } +if (lvl == IPL_CRDERR) { /* CRD error? */ + crd_err = 0; + return SCB_CRDERR; + } +if (lvl == IPL_CLKINT) { /* clock? */ + tmr_int = 0; /* clear req */ + return SCB_INTTIM; /* return vector */ + } +if (lvl > IPL_HMAX) { /* error req lvl? */ + ABORT (STOP_UIPL); /* unknown intr */ + } +if ((lvl <= IPL_HMAX) && (lvl >= IPL_HMIN)) { /* nexus? */ + l = lvl - IPL_HMIN; + for (i = 0; nexus_req[l] && (i < NEXUS_NUM); i++) { + if ((nexus_req[l] >> i) & 1) { + nexus_req[l] = nexus_req[l] & ~(1u << i); + return SCB_NEXUS + (l << 6) + (i << 2); /* return vector */ + } + } + } +if (lvl == IPL_TTINT) { /* console? */ + if (tti_int) { /* input? */ + tti_int = 0; /* clear req */ + return SCB_TTI; /* return vector */ + } + if (tto_int) { /* output? */ + tto_int = 0; /* clear req */ + return SCB_TTO; /* return vector */ + } + if (csi_int) { /* console storage? */ + csi_int = 0; /* clear req */ + return SCB_CSI; /* return vector */ + } + } +return 0; +} + +/* Used by CPU */ + +void rom_wr_B (int32 pa, int32 val) +{ +return; +} + +/* Read 8600 specific IPR's */ + +int32 ReadIPR (int32 rg) +{ +int32 val; + +switch (rg) { + + case MT_ICCS: /* ICCS */ + val = iccs_rd (); + break; + + case MT_NICR: /* NICR */ + val = nicr_rd (); + break; + + case MT_ICR: /* ICR */ + val = icr_rd (FALSE); + break; + + case MT_TODR: /* TODR */ + val = todr_rd (); + break; + + case MT_ACCS: /* ACCS (not impl) */ + val = 0; + break; + + case MT_RXCS: /* RXCS */ + val = rxcs_rd (); + break; + + case MT_RXDB: /* RXDB */ + val = rxdb_rd (); + break; + + case MT_TXCS: /* TXCS */ + val = txcs_rd (); + break; + + case MT_SID: /* SID */ + if (sys_model) + val = VAX860_SID | VAX865_TYP | VAX860_PLANT | VAX860_SN; + else + val = VAX860_SID | VAX860_TYP | VAX860_PLANT | VAX860_SN; + break; + + case MT_PAMACC: /* PAMACC */ + if (ADDR_IS_REG (pamloc)) + val = PAMM_IOA0; /* SBIA */ + else if (ADDR_IS_MEM (pamloc)) { + if (MEMSIZE < MAXMEMSIZE) + val = (pamloc >> 23); /* 4MB Boards */ + else + val = (pamloc >> 25); /* 16MB Boards */ + } + else val = PAMM_NXM; /* NXM */ + val = val | (pamloc & PAMACC_ADDR); + break; + + case MT_PAMLOC: /* PAMLOC */ + val = pamloc & PAMLOC_ADDR; + break; + + case MT_MDCTL: /* MDCTL */ + val = mdctl & MDCTL_RW; + + case MT_EHSR: /* EHSR */ + val = ehsr & EHSR_VMSE; + break; + + case MT_CSWP: /* CSWP */ + val = cswp & 0xF; + break; + + case MT_MERG: /* MERG */ + val = 0; + break; + + case MT_STXCS: /* STXCS */ + val = stxcs_rd (); + break; + + case MT_STXDB: /* STXDB */ + val = stxdb_rd (); + break; + + default: + RSVD_OPND_FAULT; + } + +return val; +} + +/* Write 8600 specific IPR's */ + +void WriteIPR (int32 rg, int32 val) +{ +switch (rg) { + + case MT_ICCS: /* ICCS */ + iccs_wr (val); + break; + + case MT_NICR: /* NICR */ + nicr_wr (val); + break; + + case MT_TODR: /* TODR */ + todr_wr (val); + break; + + case MT_ACCS: /* ACCS (not impl) */ + break; + + case MT_RXCS: /* RXCS */ + rxcs_wr (val); + break; + + case MT_TXCS: /* TXCS */ + txcs_wr (val); + break; + + case MT_TXDB: /* TXDB */ + txdb_wr (val); + break; + + case MT_PAMACC: /* PAMACC (not impl) */ + break; + + case MT_PAMLOC: /* PAMLOC */ + pamloc = val & PAMLOC_ADDR; + break; + + case MT_MDCTL: /* MDCTL */ + mdctl = val & MDCTL_RW; + break; + + case MT_EHSR: /* EHSR */ + ehsr = val & EHSR_VMSE; + break; + + case MT_CSWP: /* CSWP */ + cswp = val & 0xF; + break; + + case MT_MERG: /* MERG (not impl) */ + break; + + case MT_CRBT: /* CRBT (not impl) */ + break; + + case MT_STXCS: /* STXCS */ + stxcs_wr (val); + break; + + case MT_STXDB: /* STXDB */ + stxdb_wr (val); + break; + + default: + RSVD_OPND_FAULT; + } + +return; +} + +/* ReadReg - read register space + + Inputs: + pa = physical address + lnt = length (BWLQ) + Output: + longword of data +*/ + +int32 ReadReg (int32 pa, int32 lnt) +{ +int32 val; + +if (ADDR_IS_SBIA (pa)) return sbia_rd (pa, lnt); /* SBI adapter space? */ +if (ADDR_IS_REG (pa)) { /* reg space? */ + if (sbi_rd (pa, &val, lnt) == SCPE_OK) + return val; + } +MACH_CHECK (MCHK_RD_F); /* machine check */ +return 0; +} + +/* WriteReg - write register space + + Inputs: + pa = physical address + val = data to write, right justified in 32b longword + lnt = length (BWLQ) + Outputs: + none +*/ + +void WriteReg (int32 pa, int32 val, int32 lnt) +{ +if (ADDR_IS_SBIA (pa)) { /* SBI adapter space? */ + sbia_wr (pa, val, lnt); + SET_IRQL; + return; +} +if (ADDR_IS_REG (pa)) { /* reg space? */ + if (sbi_wr (pa, val, lnt) == SCPE_OK) + return; + } +mem_err = 1; /* interrupt */ +eval_int (); +return; +} + +/* Machine check */ + +int32 machine_check (int32 p1, int32 opc, int32 cc, int32 delta) +{ +int32 acc; +int32 mstat1, mstat2, mear, ebcs, merg, ehmsts; + +mstat1 = (MSTAT1_CPRD << MSTAT1_V_CYC); /* MBOX Status 1 */ +mstat2 = MSTAT2_NXM; /* MBOX Status 2 */ +mear = mchk_va; /* Memory error address */ +merg = (mchk_ref << MERG_V_MME); /* MBOX error generation word */ +ebcs = EBCS_MFTL; /* EBOX control/status */ +ehmsts = EHMSTS_PROCA; /* Error handling microcode status */ + +cc = intexc (SCB_MCHK, cc, 0, IE_SVE); /* take exception */ +acc = ACC_MASK (KERN); /* in kernel mode */ +in_ie = 1; +SP = SP - 92; /* push 25 words */ +Write (SP, 88, L_LONG, WA); /* # bytes */ +Write (SP + 4, ehmsts, L_LONG, WA); /* EHM.STS */ +Write (SP + 8, 0, L_LONG, WA); /* EVMQSAV */ +Write (SP + 12, ebcs, L_LONG, WA); /* EBCS */ +Write (SP + 16, 0, L_LONG, WA); /* EDPSR */ +Write (SP + 20, 0, L_LONG, WA); /* CSLINT */ +Write (SP + 24, 0, L_LONG, WA); /* IBESR */ +Write (SP + 28, 0, L_LONG, WA); /* EBXWD1 */ +Write (SP + 32, 0, L_LONG, WA); /* EBXWD2 */ +Write (SP + 36, 0, L_LONG, WA); /* IVASAV */ +Write (SP + 40, 0, L_LONG, WA); /* VIBASAV */ +Write (SP + 44, 0, L_LONG, WA); /* ESASAV */ +Write (SP + 48, 0, L_LONG, WA); /* ISASAV */ +Write (SP + 52, 0, L_LONG, WA); /* CPC */ +Write (SP + 56, mstat1, L_LONG, WA); /* MSTAT1 */ +Write (SP + 60, mstat2, L_LONG, WA); /* MSTAT2 */ +Write (SP + 64, 0, L_LONG, WA); /* MDECC */ +Write (SP + 68, merg, L_LONG, WA); /* MERG */ +Write (SP + 72, 0, L_LONG, WA); /* CSHCTL */ +Write (SP + 76, mear, L_LONG, WA); /* MEAR */ +Write (SP + 80, 0, L_LONG, WA); /* MEDR */ +Write (SP + 84, 0, L_LONG, WA); /* FBXERR */ +Write (SP + 88, 0, L_LONG, WA); /* CSES */ +in_ie = 0; +sbi_er = sbi_er & ~SBIER_TMOW1C; /* clr SBIER etc */ +ehsr = ehsr | EHSR_VMSE; /* VMS entered */ +return cc; +} + +/* Console entry */ + +int32 con_halt (int32 code, int32 cc) +{ +if ((cpu_boot_cmd[0] == 0) || /* saved boot cmd? */ + (vax860_boot_parse (0, cpu_boot_cmd) != SCPE_OK) || /* reparse the boot cmd */ + (reset_all (0) != SCPE_OK) || /* reset the world */ + (cpu_boot (0, NULL) != SCPE_OK)) /* set up boot code */ + ABORT (STOP_BOOT); /* any error? */ +printf ("Rebooting...\n"); +if (sim_log) + fprintf (sim_log, "Rebooting...\n"); +return cc; +} + +/* Special boot command - linked into SCP by initial reset + + Syntax: BOOT {/R5:val} + + Sets up R0-R5, calls SCP boot processor with effective BOOT CPU +*/ + +t_stat vax860_boot (int32 flag, char *ptr) +{ +t_stat r; + +r = vax860_boot_parse (flag, ptr); /* parse the boot cmd */ +if (r != SCPE_OK) /* error? */ + return r; +strncpy (cpu_boot_cmd, ptr, CBUFSIZE); /* save for reboot */ +return run_cmd (flag, "CPU"); +} + +/* Parse boot command, set up registers - also used on reset */ + +t_stat vax860_boot_parse (int32 flag, char *ptr) +{ +char gbuf[CBUFSIZE]; +char *slptr, *regptr; +int32 i, r5v, unitno; +DEVICE *dptr; +UNIT *uptr; +DIB *dibp; +uint32 ba; +t_stat r; + +regptr = get_glyph (ptr, gbuf, 0); /* get glyph */ +if ((slptr = strchr (gbuf, '/'))) { /* found slash? */ + regptr = strchr (ptr, '/'); /* locate orig */ + *slptr = 0; /* zero in string */ + } +dptr = find_unit (gbuf, &uptr); /* find device */ +if ((dptr == NULL) || (uptr == NULL)) + return SCPE_ARG; +dibp = (DIB *) dptr->ctxt; /* get DIB */ +if (dibp == NULL) + ba = 0; +else + ba = dibp->ba; +unitno = (int32) (uptr - dptr->units); +r5v = 0; +if ((strncmp (regptr, "/R5:", 4) == 0) || + (strncmp (regptr, "/R5=", 4) == 0) || + (strncmp (regptr, "/r5:", 4) == 0) || + (strncmp (regptr, "/r5=", 4) == 0)) { + r5v = (int32) get_uint (regptr + 4, 16, LMASK, &r); + if (r != SCPE_OK) + return r; + } +else + if (*regptr == '/') { + r5v = (int32) get_uint (regptr + 1, 16, LMASK, &r); + if (r != SCPE_OK) + return r; + } + else { + if (*regptr != 0) + return SCPE_ARG; + } +for (i = 0; boot_tab[i].name != NULL; i++) { + if (strcmp (dptr->name, boot_tab[i].name) == 0) { + R[0] = boot_tab[i].code; + if (dptr->flags & DEV_MBUS) { + R[1] = ba + TR_MBA0; + R[2] = unitno; + } + else { + R[1] = TR_UBA; + R[2] = boot_tab[i].let | (ba & UBADDRMASK); + } + R[3] = unitno; + R[4] = 0; + R[5] = r5v; + return SCPE_OK; + } + } +return SCPE_NOFNC; +} + +/* Bootstrap - finish up bootstrap process */ + +t_stat cpu_boot (int32 unitno, DEVICE *dptr) +{ +t_stat r; + +r = cpu_load_bootcode (BOOT_CODE_FILENAME, BOOT_CODE_ARRAY, BOOT_CODE_SIZE, FALSE, 0x200); +if (r != SCPE_OK) + return r; +SP = PC = 512; +return SCPE_OK; +} + +/* A-Bus reset */ + +t_stat abus_reset (DEVICE *dptr) +{ +sim_vm_cmd = vax860_cmd; +return SCPE_OK; +} + +/* Build dib_tab from device list */ + +t_stat build_dib_tab (void) +{ +uint32 i; +DEVICE *dptr; +DIB *dibp; +t_stat r; + +init_nexus_tab (); +init_ubus_tab (); +init_mbus_tab (); +for (i = 0; (dptr = sim_devices[i]) != NULL; i++) { /* loop thru dev */ + dibp = (DIB *) dptr->ctxt; /* get DIB */ + if (dibp && !(dptr->flags & DEV_DIS)) { /* defined, enabled? */ + if (dptr->flags & DEV_NEXUS) { /* Nexus? */ + if ((r = build_nexus_tab (dptr, dibp))) /* add to dispatch table */ + return r; + } + else if (dptr->flags & DEV_MBUS) { /* Massbus? */ + if ((r = build_mbus_tab (dptr, dibp))) + return r; + } + else { /* no, Unibus device */ + if ((r = build_ubus_tab (dptr, dibp))) /* add to dispatch tab */ + return r; + } /* end else */ + } /* end if enabled */ + } /* end for */ +return SCPE_OK; +} + +t_stat cpu_set_model (UNIT *uptr, int32 val, char *cptr, void *desc) +{ +if (cptr == NULL) return SCPE_ARG; +if (strcmp(cptr, "8600") == 0) + sys_model = 0; +else if (strcmp(cptr, "8650") == 0) + sys_model = 1; +else + return SCPE_ARG; +return SCPE_OK; +} + +t_stat cpu_print_model (FILE *st) +{ +fprintf (st, "VAX %s", (sys_model ? "8650" : "8600")); +return SCPE_OK; +} + +t_stat cpu_model_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr) +{ +fprintf (st, "Initial memory size is 32MB.\n\n"); +fprintf (st, "The simulator is booted with the BOOT command:\n\n"); +fprintf (st, " sim> BO{OT} {/R5:flags}\n\n"); +fprintf (st, "where is one of:\n\n"); +fprintf (st, " RPn to boot from rpn\n"); +fprintf (st, " HKn to boot from hkn\n"); +fprintf (st, " RLn to boot from rln\n"); +fprintf (st, " RQn to boot from rqn\n"); +fprintf (st, " RQBn to boot from rqbn\n"); +fprintf (st, " RQCn to boot from rqcn\n"); +fprintf (st, " RQDn to boot from rqdn\n"); +fprintf (st, " TQn to boot from tqn\n"); +fprintf (st, " CS to boot from console RL\n\n"); +return SCPE_OK; +} diff --git a/VAX/vax860_defs.h b/VAX/vax860_defs.h new file mode 100644 index 00000000..1741d5a0 --- /dev/null +++ b/VAX/vax860_defs.h @@ -0,0 +1,462 @@ +/* vax860_defs.h: VAX 8600 model-specific definitions file + + Copyright (c) 2011-2012, Matt Burke + This module incorporates code from SimH, Copyright (c) 2004-2008, Robert M Supnik + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name(s) of the author(s) shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from the author(s). + + 26-Dec-2012 MB First Version + + This file covers the VAX 8600, the fourth VAX. + + System memory map + + 0000 0000 - 1FFF FFFF main memory + + 2000 0000 - 2001 FFFF SBI0 adapter space + 2002 0000 - 200F FFFF reserved + 2008 0000 - 2008 00BF SBI0 registers + 2008 00C0 - 200F FFFF reserved + 2010 0000 - 2013 FFFF Unibus address space, Unibus 0 + 2014 0000 - 2017 FFFF Unibus address space, Unibus 1 + 2018 0000 - 201B FFFF Unibus address space, Unibus 2 + 201C 0000 - 201F FFFF Unibus address space, Unibus 3 + 2020 0000 - 21FF FFFF reserved + + 2200 0000 - 2201 FFFF SBI1 adapter space + 2202 0000 - 220F FFFF reserved + 2208 0000 - 2208 00BF SBI1 registers + 2208 00C0 - 220F FFFF reserved + 2210 0000 - 2213 FFFF Unibus address space, Unibus 4 + 2214 0000 - 2217 FFFF Unibus address space, Unibus 5 + 2218 0000 - 221B FFFF Unibus address space, Unibus 6 + 221C 0000 - 221F FFFF Unibus address space, Unibus 7 + 2220 0000 - 23FF FFFF reserved + + 2400 0000 - 2401 FFFF SBI2 adapter space + 2402 0000 - 240F FFFF reserved + 2408 0000 - 2408 00BF SBI2 registers + 2408 00C0 - 240F FFFF reserved + 2410 0000 - 2413 FFFF Unibus address space, Unibus 8 + 2414 0000 - 2417 FFFF Unibus address space, Unibus 9 + 2418 0000 - 241B FFFF Unibus address space, Unibus 10 + 241C 0000 - 241F FFFF Unibus address space, Unibus 11 + 2420 0000 - 25FF FFFF reserved + + 2600 0000 - 2601 FFFF SBI3 adapter space + 2602 0000 - 260F FFFF reserved + 2608 0000 - 2608 00BF SBI3 registers + 2608 00C0 - 260F FFFF reserved + 2610 0000 - 2613 FFFF Unibus address space, Unibus 12 + 2614 0000 - 2617 FFFF Unibus address space, Unibus 13 + 2618 0000 - 261B FFFF Unibus address space, Unibus 14 + 261C 0000 - 261F FFFF Unibus address space, Unibus 15 + 2620 0000 - 3FFF FFFF reserved +*/ + +#ifndef FULL_VAX +#define FULL_VAX 1 +#endif + +#ifndef _VAX_860_DEFS_H_ +#define _VAX_860_DEFS_H_ 1 + +/* Microcode constructs */ + +#define VAX860_SID (4 << 24) /* system ID */ +#define VAX860_TYP (0 << 23) /* sys type: 8600 */ +#define VAX865_TYP (1 << 23) /* sys type: 8650 */ +#define VAX860_ECO (7 << 19) /* ucode revision */ +#define VAX860_PLANT (0 << 12) /* plant (Salem NH) */ +#define VAX860_SN (1234) +#define CON_HLTPIN 0x0200 /* external CPU halt */ +#define CON_HLTINS 0x0600 /* HALT instruction */ +#define MCHK_RD_F 0x00 /* read fault */ +#define MCHK_RD_A 0xF4 /* read abort */ +#define MCHK_IBUF 0x0D /* read istream */ +#define VER_UCODE 0x1 /* Microcode version */ + +/* Interrupts */ + +#define IPL_HMAX 0x17 /* highest hwre level */ +#define IPL_HMIN 0x14 /* lowest hwre level */ +#define IPL_HLVL (IPL_HMAX - IPL_HMIN + 1) /* # hardware levels */ +#define IPL_SMAX 0xF /* highest swre level */ + +/* SBI Nexus constants */ + +#define NEXUS_NUM 16 /* number of nexus */ +#define MCTL_NUM 2 /* number of mem ctrl */ +#define MBA_NUM 2 /* number of MBA's */ +#define TR_MCTL0 1 /* nexus assignments */ +#define TR_MCTL1 2 +#define TR_UBA 3 +#define TR_MBA0 8 +#define TR_MBA1 9 +#define TR_CI 14 +#define NEXUS_HLVL (IPL_HMAX - IPL_HMIN + 1) +#define SCB_NEXUS 0x100 /* nexus intr base */ +#define SBI_FAULTS 0xFC000000 /* SBI fault flags */ + +/* Internal I/O interrupts - relative except for clock and console */ + +#define IPL_CLKINT 0x18 /* clock IPL */ +#define IPL_TTINT 0x14 /* console IPL */ + +#define IPL_MCTL0 (0x15 - IPL_HMIN) +#define IPL_MCTL1 (0x15 - IPL_HMIN) +#define IPL_UBA (0x15 - IPL_HMIN) +#define IPL_MBA0 (0x15 - IPL_HMIN) +#define IPL_MBA1 (0x15 - IPL_HMIN) +#define IPL_CI (0x15 - IPL_HMIN) + +/* Nexus interrupt macros */ + +#define SET_NEXUS_INT(dv) nexus_req[IPL_##dv] |= (1 << TR_##dv) +#define CLR_NEXUS_INT(dv) nexus_req[IPL_##dv] &= ~(1 << TR_##dv) + +/* Machine specific IPRs */ + +#define MT_ACCS 40 /* FPA control */ +#define MT_PAMACC 64 +#define MT_PAMLOC 65 +#define MT_CSWP 66 +#define MT_MDECC 67 +#define MT_MENA 68 +#define MT_MDCTL 69 +#define MT_MCCTL 70 +#define MT_MERG 71 +#define MT_CRBT 72 /* Console reboot */ +#define MT_DFI 73 +#define MT_EHSR 74 +#define MT_STXCS 76 +#define MT_STXDB 77 +#define MT_ESPA 78 +#define MT_ESPD 79 +#define MT_MAX MT_ESPD /* last valid IPR */ + +/* Machine specific reserved operand tests */ + +/* 780 microcode patch 37 - only test LR<23:0> for appropriate length */ + +#define ML_LR_TEST(r) if (((uint32)((r) & 0xFFFFFF)) > 0x200000) RSVD_OPND_FAULT + +/* 780 microcode patch 38 - only test PxBR<31>=1, PxBR<30> = 0, and xBR<1:0> = 0 */ + +#define ML_PXBR_TEST(r) if (((((uint32)(r)) & 0x80000000) == 0) || \ + ((((uint32)(r)) & 0x40000003) != 0)) RSVD_OPND_FAULT +#define ML_SBR_TEST(r) if ((((uint32)(r)) & 0xC0000003) != 0) RSVD_OPND_FAULT + +/* 780 microcode patch 78 - only test xCBB<1:0> = 0 */ + +#define ML_PA_TEST(r) if ((((uint32)(r)) & 0x00000003) != 0) RSVD_OPND_FAULT + +#define LP_AST_TEST(r) if ((r) > AST_MAX) RSVD_OPND_FAULT +#define LP_MBZ84_TEST(r) if ((((uint32)(r)) & 0xF8C00000) != 0) RSVD_OPND_FAULT +#define LP_MBZ92_TEST(r) if ((((uint32)(r)) & 0x7FC00000) != 0) RSVD_OPND_FAULT + +/* CPU */ + +#define CPU_MODEL_MODIFIERS \ + { MTAB_XTD|MTAB_VDV, 0, "MODEL", "MODEL={8600|8650}", \ + &cpu_set_model, &cpu_show_model }, +/* Memory */ + +#define MAXMEMWIDTH 25 /* max mem, 4MB boards */ +#define MAXMEMSIZE (1 << MAXMEMWIDTH) +#define MAXMEMWIDTH_X 27 /* max mem, 16MB boards */ +#define MAXMEMSIZE_X (1 << MAXMEMWIDTH_X) +#define INITMEMSIZE (1 << MAXMEMWIDTH) /* initial memory size */ +#define MEMSIZE (cpu_unit.capac) +#define ADDR_IS_MEM(x) (((uint32) (x)) < MEMSIZE) +#define MEM_MODIFIERS { UNIT_MSIZE, (1u << 23), NULL, "8M", &cpu_set_size }, \ + { UNIT_MSIZE, (1u << 24), NULL, "16M", &cpu_set_size }, \ + { UNIT_MSIZE, (1u << 25), NULL, "32M", &cpu_set_size }, \ + { UNIT_MSIZE, (1u << 25) + (1u << 24), NULL, "48M", &cpu_set_size }, \ + { UNIT_MSIZE, (1u << 26), NULL, "64M", &cpu_set_size }, \ + { UNIT_MSIZE, (1u << 27), NULL, "128M", &cpu_set_size } + +/* Unibus I/O registers */ + +#define UBADDRWIDTH 18 /* Unibus addr width */ +#define UBADDRSIZE (1u << UBADDRWIDTH) /* Unibus addr length */ +#define UBADDRMASK (UBADDRSIZE - 1) /* Unibus addr mask */ +#define IOPAGEAWIDTH 13 /* IO addr width */ +#define IOPAGESIZE (1u << IOPAGEAWIDTH) /* IO page length */ +#define IOPAGEMASK (IOPAGESIZE - 1) /* IO addr mask */ +#define UBADDRBASE 0x20100000 /* Unibus addr base */ +#define IOPAGEBASE 0x2013E000 /* IO page base */ +#define ADDR_IS_IO(x) ((((uint32) (x)) >= UBADDRBASE) && \ + (((uint32) (x)) < (UBADDRBASE + UBADDRSIZE))) +#define ADDR_IS_IOP(x) (((uint32) (x)) >= IOPAGEBASE) + +/* Nexus register space */ + +#define REGAWIDTH 17 /* REG addr width */ +#define REG_V_NEXUS 13 /* nexus number */ +#define REG_M_NEXUS 0xF +#define REG_V_OFS 2 /* register number */ +#define REG_M_OFS 0x7FF +#define REGSIZE (1u << REGAWIDTH) /* REG length */ +#define REGBASE 0x20000000 /* REG addr base */ +#define ADDR_IS_REG(x) ((((uint32) (x)) >= REGBASE) && \ + (((uint32) (x)) < (REGBASE + REGSIZE))) +#define NEXUS_GETNEX(x) (((x) >> REG_V_NEXUS) & REG_M_NEXUS) +#define NEXUS_GETOFS(x) (((x) >> REG_V_OFS) & REG_M_OFS) + +/* SBI adapter space */ + +#define SBIAWIDTH 19 +#define SBIABASE 0x20080000 +#define SBIASIZE (1u << SBIAWIDTH) +#define ADDR_IS_SBIA(x) ((((uint32) (x)) >= SBIABASE) && \ + (((uint32) (x)) < (SBIABASE + SBIASIZE))) + +/* ROM address space in memory controllers */ + +#define ROMAWIDTH 12 /* ROM addr width */ +#define ROMSIZE (1u << ROMAWIDTH) /* ROM size */ +#define ROM0BASE (REGBASE + (TR_MCTL0 << REG_V_NEXUS) + 0x1000) +#define ROM1BASE (REGBASE + (TR_MCTL1 << REG_V_NEXUS) + 0x1000) +#define ADDR_IS_ROM0(x) ((((uint32) (x)) >= ROM0BASE) && \ + (((uint32) (x)) < (ROM0BASE + ROMSIZE))) +#define ADDR_IS_ROM1(x) ((((uint32) (x)) >= ROM1BASE) && \ + (((uint32) (x)) < (ROM1BASE + ROMSIZE))) +#define ADDR_IS_ROM(x) (ADDR_IS_ROM0 (x) || ADDR_IS_ROM1 (x)) + +/* Other address spaces */ + +#define ADDR_IS_CDG(x) (0) +#define ADDR_IS_NVR(x) (0) + +/* Unibus I/O modes */ + +#define READ 0 /* PDP-11 compatibility */ +#define WRITE (L_WORD) +#define WRITEB (L_BYTE) + +/* Common CSI flags */ + +#define CSR_V_GO 0 /* go */ +#define CSR_V_IE 6 /* interrupt enable */ +#define CSR_V_DONE 7 /* done */ +#define CSR_V_BUSY 11 /* busy */ +#define CSR_V_ERR 15 /* error */ +#define CSR_GO (1u << CSR_V_GO) +#define CSR_IE (1u << CSR_V_IE) +#define CSR_DONE (1u << CSR_V_DONE) +#define CSR_BUSY (1u << CSR_V_BUSY) +#define CSR_ERR (1u << CSR_V_ERR) + +/* Timers */ + +#define TMR_CLK 0 /* 100Hz clock */ + +/* I/O system definitions */ + +#define DZ_MUXES 4 /* max # of DZV muxes */ +#define DZ_LINES 8 /* lines per DZV mux */ +#define VH_MUXES 4 /* max # of DHU muxes */ +#define DLX_LINES 16 /* max # of KL11/DL11's */ +#define DCX_LINES 16 /* max # of DC11's */ +#define MT_MAXFR (1 << 16) /* magtape max rec */ + +#define DEV_V_UBUS (DEV_V_UF + 0) /* Unibus */ +#define DEV_V_MBUS (DEV_V_UF + 1) /* Massbus */ +#define DEV_V_NEXUS (DEV_V_UF + 2) /* Nexus */ +#define DEV_V_FFUF (DEV_V_UF + 3) /* first free flag */ +#define DEV_UBUS (1u << DEV_V_UBUS) +#define DEV_MBUS (1u << DEV_V_MBUS) +#define DEV_NEXUS (1u << DEV_V_NEXUS) +#define DEV_QBUS (0) +#define DEV_Q18 (0) + +#define UNIBUS TRUE /* Unibus only */ + +#define DEV_RDX 16 /* default device radix */ + +/* Device information block + + For Massbus devices, + ba = Massbus number + lnt = Massbus ctrl type + ack[0] = abort routine + + For Nexus devices, + ba = Nexus number + lnt = number of consecutive nexi */ + +#define VEC_DEVMAX 4 /* max device vec */ + +typedef struct { + uint32 ba; /* base addr */ + uint32 lnt; /* length */ + t_stat (*rd)(int32 *dat, int32 ad, int32 md); + t_stat (*wr)(int32 dat, int32 ad, int32 md); + int32 vnum; /* vectors: number */ + int32 vloc; /* locator */ + int32 vec; /* value */ + int32 (*ack[VEC_DEVMAX])(void); /* ack routine */ + } DIB; + +/* Unibus I/O page layout - XUB,RQB,RQC,RQD float based on number of DZ's + Massbus devices (RP, TU) do not appear in the Unibus IO page */ + +#define IOBA_AUTO (0) /* Assigned by Auto Configure */ + + +/* Interrupt assignments; within each level, priority is right to left */ + +#define INT_V_DZRX 0 /* BR5 */ +#define INT_V_DZTX 1 +#define INT_V_HK 2 +#define INT_V_RL 3 +#define INT_V_RQ 4 +#define INT_V_TQ 5 +#define INT_V_TS 6 +#define INT_V_RY 7 +#define INT_V_XU 8 +#define INT_V_DMCRX 9 +#define INT_V_DMCTX 10 +#define INT_V_LPT 0 /* BR4 */ +#define INT_V_PTR 1 +#define INT_V_PTP 2 +#define INT_V_CR 3 +#define INT_V_VHRX 4 +#define INT_V_VHTX 5 + +#define INT_DZRX (1u << INT_V_DZRX) +#define INT_DZTX (1u << INT_V_DZTX) +#define INT_HK (1u << INT_V_HK) +#define INT_RL (1u << INT_V_RL) +#define INT_RQ (1u << INT_V_RQ) +#define INT_TQ (1u << INT_V_TQ) +#define INT_TS (1u << INT_V_TS) +#define INT_RY (1u << INT_V_RY) +#define INT_XU (1u << INT_V_XU) +#define INT_LPT (1u << INT_V_LPT) +#define INT_VHRX (1u << INT_V_VHRX) +#define INT_VHTX (1u << INT_V_VHTX) +#define INT_PTR (1u << INT_V_PTR) +#define INT_PTP (1u << INT_V_PTP) +#define INT_CR (1u << INT_V_CR) +#define INT_DMCRX (1u << INT_V_DMCRX) +#define INT_DMCTX (1u << INT_V_DMCTX) +#define IPL_DZRX (0x15 - IPL_HMIN) +#define IPL_DZTX (0x15 - IPL_HMIN) +#define IPL_HK (0x15 - IPL_HMIN) +#define IPL_RL (0x15 - IPL_HMIN) +#define IPL_RQ (0x15 - IPL_HMIN) +#define IPL_TQ (0x15 - IPL_HMIN) +#define IPL_TS (0x15 - IPL_HMIN) +#define IPL_RY (0x15 - IPL_HMIN) +#define IPL_XU (0x15 - IPL_HMIN) +#define IPL_LPT (0x14 - IPL_HMIN) +#define IPL_PTR (0x14 - IPL_HMIN) +#define IPL_PTP (0x14 - IPL_HMIN) +#define IPL_CR (0x14 - IPL_HMIN) +#define IPL_VHRX (0x14 - IPL_HMIN) +#define IPL_VHTX (0x14 - IPL_HMIN) +#define IPL_DMCRX (0x15 - IPL_HMIN) +#define IPL_DMCTX (0x15 - IPL_HMIN) + +/* Device vectors */ + +#define VEC_AUTO (0) /* Assigned by Auto Configure */ +#define VEC_FLOAT (0) /* Assigned by Auto Configure */ + +#define VEC_QBUS 0 +#define VEC_Q 0000 + +/* Interrupt macros */ + +#define IVCL(dv) ((IPL_##dv * 32) + INT_V_##dv) +#define NVCL(dv) ((IPL_##dv * 32) + TR_##dv) +#define IREQ(dv) int_req[IPL_##dv] +#define SET_INT(dv) int_req[IPL_##dv] = int_req[IPL_##dv] | (INT_##dv) +#define CLR_INT(dv) int_req[IPL_##dv] = int_req[IPL_##dv] & ~(INT_##dv) +#define IORETURN(f,v) ((f)? (v): SCPE_OK) /* cond error return */ + +/* Logging */ + +#define LOG_CPU_I 0x1 /* intexc */ +#define LOG_CPU_R 0x2 /* REI */ +#define LOG_CPU_P 0x4 /* context */ + +/* Massbus definitions */ + +#define MBA_RP (TR_MBA0 - TR_MBA0) /* MBA for RP */ +#define MBA_TU (TR_MBA1 - TR_MBA0) /* MBA for TU */ +#define MBA_RMASK 0x1F /* max 32 reg */ +#define MBE_NXD 1 /* nx drive */ +#define MBE_NXR 2 /* nx reg */ +#define MBE_GOE 3 /* err on GO */ + +/* Boot definitions */ + +#define BOOT_MB 0 /* device codes */ +#define BOOT_HK 1 /* for VMB */ +#define BOOT_RL 2 +#define BOOT_UDA 17 +#define BOOT_TK 18 +#define BOOT_CS 64 + +/* Function prototypes for virtual memory interface */ + +int32 Read (uint32 va, int32 lnt, int32 acc); +void Write (uint32 va, int32 val, int32 lnt, int32 acc); + +/* Function prototypes for physical memory interface (inlined) */ + +SIM_INLINE int32 ReadB (uint32 pa); +SIM_INLINE int32 ReadW (uint32 pa); +SIM_INLINE int32 ReadL (uint32 pa); +SIM_INLINE int32 ReadLP (uint32 pa); +SIM_INLINE void WriteB (uint32 pa, int32 val); +SIM_INLINE void WriteW (uint32 pa, int32 val); +SIM_INLINE void WriteL (uint32 pa, int32 val); +void WriteLP (uint32 pa, int32 val); + +/* Function prototypes for I/O */ + +int32 Map_ReadB (uint32 ba, int32 bc, uint8 *buf); +int32 Map_ReadW (uint32 ba, int32 bc, uint16 *buf); +int32 Map_WriteB (uint32 ba, int32 bc, uint8 *buf); +int32 Map_WriteW (uint32 ba, int32 bc, uint16 *buf); + +int32 mba_rdbufW (uint32 mbus, int32 bc, uint16 *buf); +int32 mba_wrbufW (uint32 mbus, int32 bc, uint16 *buf); +int32 mba_chbufW (uint32 mbus, int32 bc, uint16 *buf); +int32 mba_get_bc (uint32 mbus); +void mba_upd_ata (uint32 mbus, uint32 val); +void mba_set_exc (uint32 mbus); +void mba_set_don (uint32 mbus); +void mba_set_enbdis (uint32 mbus, t_bool dis); +t_stat mba_show_num (FILE *st, UNIT *uptr, int32 val, void *desc); + +t_stat show_nexus (FILE *st, UNIT *uptr, int32 val, void *desc); + +void sbi_set_errcnf (void); + +#include "pdp11_io_lib.h" + +#endif diff --git a/VAX/vax860_sbia.c b/VAX/vax860_sbia.c new file mode 100644 index 00000000..7178ee58 --- /dev/null +++ b/VAX/vax860_sbia.c @@ -0,0 +1,356 @@ +/* vax860_sbia.c: VAX 8600 SBIA + + Copyright (c) 2011-2012, Matt Burke + This module incorporates code from SimH, Copyright (c) 2004-2008, Robert M Supnik + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name(s) of the author(s) shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from the author(s). + + sbia SBI adapter + + 26-Dec-2012 MB First Version +*/ + +#include "vax_defs.h" + +/* SBIA registers */ + +#define SBICSR_MIE 0x80000000 /* master int en */ +#define SBICSR_SCOEN 0x40000000 /* SBI cycles out enable */ +#define SBICSR_SCIEN 0x20000000 /* SBI cycles in enable */ +#define SBICSR_WR (SBICSR_MIE | SBICSR_SCOEN | SBICSR_SCIEN) + +#define SBIFS_RD (0x031F0000|SBI_FAULTS) /* SBI faults */ +#define SBIFS_WR 0x03140000 +#define SBIFS_W1C 0x00080000 + +#define SBISC_RD 0xFFFF0000 /* SBI silo comp */ +#define SBISC_WR 0x7FFF0000 +#define SBISC_LOCK 0x80000000 /* lock */ + +#define SBIMT_RD 0xFFFFFF00 /* SBI maint */ +#define SBIMT_WR 0xFFFFF900 + +#define SBIER_CRDIE 0x00008000 /* SBI error, CRD IE */ +#define SBIER_CRD 0x00004000 /* CRD */ +#define SBIER_RDS 0x00002000 /* RDS */ +#define SBIER_TMO 0x00001000 /* timeout */ +#define SBIER_STA 0x00000C00 /* timeout status (0) */ +#define SBIER_CNF 0x00000100 /* error confirm */ +#define SBIER_IBRDS 0x00000080 +#define SBIER_IBTMO 0x00000040 +#define SBIER_IBSTA 0x00000030 +#define SBIER_IBCNF 0x00000008 +#define SBIER_MULT 0x00000004 /* multiple errors */ +#define SBIER_FREE 0x00000002 /* SBI free */ +#define SBIER_RD 0x0000FDFE +#define SBIER_WR 0x00008000 +#define SBIER_W1C 0x000070C0 +#define SBIER_TMOW1C (SBIER_TMO|SBIER_STA|SBIER_CNF|SBIER_MULT) +#define SBIER_IBTW1C (SBIER_IBTMO|SBIER_STA|SBIER_IBCNF) + +#define SBITMO_V_MODE 30 /* mode */ +#define SBITMO_VIRT 0x20000000 /* physical */ + +#define SBIQC_MBZ 0xC0000007 /* MBZ */ + +uint32 nexus_req[NEXUS_HLVL]; /* nexus int req */ +uint32 sbi_fs = 0; /* SBI fault status */ +uint32 sbi_sc = 0; /* SBI silo comparator */ +uint32 sbi_mt = 0; /* SBI maintenance */ +uint32 sbi_er = 0; /* SBI error status */ +uint32 sbi_tmo = 0; /* SBI timeout addr */ +uint32 sbi_csr = 0; /* SBI control/status */ + +extern int32 R[16]; +extern int32 PSL; +extern int32 ASTLVL, SISR; +extern jmp_buf save_env; +extern int32 trpirq; +extern int32 p1; +extern int32 mchk_ref; +extern int32 crd_err; +extern int32 fault_PC; /* fault PC */ +extern UNIT cpu_unit; + +t_stat sbia_reset (DEVICE *dptr); +void sbi_set_tmo (int32 pa); +t_stat (*nexusR[NEXUS_NUM])(int32 *dat, int32 ad, int32 md); +t_stat (*nexusW[NEXUS_NUM])(int32 dat, int32 ad, int32 md); + +extern int32 intexc (int32 vec, int32 cc, int32 ipl, int ei); +extern int32 eval_int (void); + +/* SBIA data structures + + sbia_dev SBIA device descriptor + sbia_unit SBIA unit + sbia_reg SBIA register list +*/ + +UNIT sbia_unit = { UDATA (NULL, 0, 0) }; + +REG sbia_reg[] = { + { HRDATA (NREQ14, nexus_req[0], 16) }, + { HRDATA (NREQ15, nexus_req[1], 16) }, + { HRDATA (NREQ16, nexus_req[2], 16) }, + { HRDATA (NREQ17, nexus_req[3], 16) }, + { HRDATA (SBIFS, sbi_fs, 32) }, + { HRDATA (SBISC, sbi_sc, 32) }, + { HRDATA (SBIMT, sbi_mt, 32) }, + { HRDATA (SBIER, sbi_er, 32) }, + { HRDATA (SBITMO, sbi_tmo, 32) }, + { HRDATA (SBICSR, sbi_csr, 32) }, + { NULL } + }; + +DEVICE sbia_dev = { + "SBIA", &sbia_unit, sbia_reg, NULL, + 1, 16, 16, 1, 16, 8, + NULL, NULL, &sbia_reset, + NULL, NULL, NULL, + NULL, 0 + }; + +int32 sbia_rd (int32 pa, int32 lnt) +{ + int32 rg = (pa >> 2) & 0x1F; + + switch (rg) { + case 0: /* SBICNF */ + return 0x00400010; /* 8MB + SBIA Abus code */ + + case 1: /* SBICSR */ + return sbi_csr; + + case 2: /* SBIES (not impl) */ + case 3: /* SBIDCR (not impl) */ + case 4: /* DMAI CMD (not impl) */ + case 5: /* DMAI ID (not impl) */ + case 6: /* DMAA CMD (not impl) */ + case 7: /* DMAA ID (not impl) */ + case 8: /* DMAB CMD (not impl) */ + case 9: /* DMAB ID (not impl) */ + case 0xa: /* DMAC CMD (not impl) */ + case 0xb: /* DMAC ID (not impl) */ + case 0xc: /* SBIS (not impl) */ + return 0; + + case 0xd: /* SBIER */ + return sbi_er & SBIER_RD; + + case 0xe: /* SBITA */ + return sbi_tmo; + + case 0xf: /* SBIFS */ + return sbi_fs & SBIFS_RD; + + case 0x10: /* SBISC */ + return sbi_sc & SBISC_RD; + + case 0x11: /* SBIMT */ + return sbi_mt & SBIMT_RD; + + default: /* Anything else is not impl */ + return 0; + + } +} + +void sbia_wr (int32 pa, int32 val, int32 lnt) +{ + int32 rg = (pa >> 2) & 0x1F; + + switch (rg) { + case 0: /* SBICNF */ + break; + + case 1: /* SBICSR */ + printf ("sbi_csr wr: %08X\n", val); + sbi_csr = sbi_csr & SBICSR_WR; + break; + + case 2: /* SBIES (not impl) */ + case 3: /* SBIDCR (not impl) */ + case 4: /* DMAI CMD (not impl) */ + case 5: /* DMAI ID (not impl) */ + case 6: /* DMAA CMD (not impl) */ + case 7: /* DMAA ID (not impl) */ + case 8: /* DMAB CMD (not impl) */ + case 9: /* DMAB ID (not impl) */ + case 0xa: /* DMAC CMD (not impl) */ + case 0xb: /* DMAC ID (not impl) */ + case 0xc: /* SBIS (not impl) */ + break; + + case 0xd: /* SBIER */ + sbi_er = (sbi_er & ~SBIER_WR) | (val & SBIER_WR); + sbi_er = sbi_er & ~(val & SBIER_W1C); + if (val & SBIER_TMO) + sbi_er = sbi_er & ~SBIER_TMOW1C; + if (val & SBIER_IBTMO) + sbi_er = sbi_er & ~SBIER_IBTW1C; + if ((sbi_er & SBIER_CRDIE) && (sbi_er & SBIER_CRD)) + crd_err = 1; + else crd_err = 0; + break; + + case 0xe: /* SBITA */ + break; + + case 0xf: /* SBIFS */ + sbi_fs = (sbi_fs & ~SBIFS_WR) | (val & SBIFS_WR); + sbi_fs = sbi_fs & ~(val & SBIFS_W1C); + break; + + case 0x10: /* SBISC */ + sbi_sc = (sbi_sc & ~(SBISC_LOCK|SBISC_WR)) | (val & SBISC_WR); + break; + + case 0x11: /* SBIMT */ + sbi_mt = (sbi_mt & ~SBIMT_WR) | (val & SBIMT_WR); + break; + } +return; +} + +t_stat sbi_rd (int32 pa, int32 *val, int32 lnt) +{ +int32 nexus; + +nexus = NEXUS_GETNEX (pa); /* get nexus */ +if ((sbi_csr & SBICSR_SCOEN) && /* SBI en? */ + nexusR[nexus] && /* valid? */ + (nexusR[nexus] (val, pa, lnt) == SCPE_OK)) { + SET_IRQL; + return SCPE_OK; + } +else sbi_set_tmo (pa); /* timeout */ +return SCPE_NXM; +} + +t_stat sbi_wr (int32 pa, int32 val, int32 lnt) +{ +int32 nexus; + +nexus = NEXUS_GETNEX (pa); /* get nexus */ +if ((sbi_csr & SBICSR_SCOEN) && /* SBI en? */ + nexusW[nexus] && /* valid? */ + (nexusW[nexus] (val, pa, lnt) == SCPE_OK)) { + SET_IRQL; + return SCPE_OK; + } +else sbi_set_tmo (pa); /* timeout */ +return SCPE_NXM; +} + +/* Set SBI timeout - machine checks only on reads */ + +void sbi_set_tmo (int32 pa) +{ +if ((sbi_er & SBIER_TMO) == 0) { /* not yet set? */ + sbi_tmo = pa >> 2; /* save addr */ + if (mchk_ref == REF_V) /* virt? add mode */ + sbi_tmo |= SBITMO_VIRT | (PSL_GETCUR (PSL) << SBITMO_V_MODE); + sbi_er |= SBIER_TMO; /* set tmo flag */ + } +else sbi_er |= SBIER_MULT; /* yes, multiple */ +return; +} + +/* Set SBI error confirmation - always machine checks */ + +void sbi_set_errcnf (void) +{ +if (sbi_er & SBIER_CNF) + sbi_er |= SBIER_MULT; +else sbi_er |= SBIER_CNF; +MACH_CHECK (MCHK_RD_F); +return; +} + +/* SBI reset */ + +t_stat sbia_reset (DEVICE *dptr) +{ +sbi_fs = 0; +sbi_sc = 0; +sbi_mt = 0; +sbi_er = 0; +sbi_tmo = 0; +sbi_csr = SBICSR_SCOEN | SBICSR_SCIEN; +return SCPE_OK; +} + +/* Show nexus */ + +t_stat show_nexus (FILE *st, UNIT *uptr, int32 val, void *desc) +{ +fprintf (st, "nexus=%d", val); +return SCPE_OK; +} + +/* Init nexus tables */ + +void init_nexus_tab (void) +{ +uint32 i; + +for (i = 0; i < NEXUS_NUM; i++) { + nexusR[i] = NULL; + nexusW[i] = NULL; + } +return; +} + +/* Build nexus tables + + Inputs: + dptr = pointer to device + dibp = pointer to DIB + Outputs: + status +*/ + +t_stat build_nexus_tab (DEVICE *dptr, DIB *dibp) +{ +uint32 idx; + +if ((dptr == NULL) || (dibp == NULL)) + return SCPE_IERR; +idx = dibp->ba; +if (idx >= NEXUS_NUM) + return SCPE_IERR; +if ((nexusR[idx] && dibp->rd && /* conflict? */ + (nexusR[idx] != dibp->rd)) || + (nexusW[idx] && dibp->wr && + (nexusW[idx] != dibp->wr))) { + printf ("Nexus %s conflict at %d\n", sim_dname (dptr), dibp->ba); + if (sim_log) + fprintf (sim_log, "Nexus %s conflict at %d\n", sim_dname (dptr), dibp->ba); + return SCPE_STOP; + } +if (dibp->rd) /* set rd dispatch */ + nexusR[idx] = dibp->rd; +if (dibp->wr) /* set wr dispatch */ + nexusW[idx] = dibp->wr; +return SCPE_OK; +} diff --git a/VAX/vax860_stddev.c b/VAX/vax860_stddev.c new file mode 100644 index 00000000..e8fa5c00 --- /dev/null +++ b/VAX/vax860_stddev.c @@ -0,0 +1,1146 @@ +/* vax860_stddev.c: VAX 8600 standard I/O devices + + Copyright (c) 2011-2012, Matt Burke + This module incorporates code from SimH, Copyright (c) 1998-2008, Robert M Supnik + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name(s) of the author(s) shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from the author(s). + + tti console input + tto console output + cs console RL02 + todr TODR clock + tmr interval timer + + 26-Dec-2012 MB First Version +*/ + +#include "vax_defs.h" +#include "sim_tmxr.h" +#include + +/* Terminal definitions */ + +#define RXCS_V_DTR 16 /* logical carrier */ +#define RXCS_M_DTR 0xF +#define RXCS_DTR (RXCS_M_DTR << RXCS_V_DTR) +#define RXCS_RD (CSR_DONE + CSR_IE + RXCS_DTR) /* terminal input */ +#define RXCS_WR (CSR_IE) +#define RXDB_V_LC 16 /* logical carrier */ +#define RXDB_V_IDC 8 /* ID Code */ +#define RXDB_M_IDC 0xF +#define RXDB_IDC (TXCS_M_IDC << TXCS_V_IDC) +#define TXCS_V_IDC 8 /* ID Code */ +#define TXCS_M_IDC 0xF +#define TXCS_IDC (TXCS_M_IDC << TXCS_V_IDC) +#define TXCS_WMN 0x8000 /* Write mask now */ +#define TXCS_V_TEN 16 /* Transmitter en */ +#define TXCS_M_TEN 0xF +#define TXCS_TEN (TXCS_M_TEN << TXCS_V_TEN) +#define TXCS_RD (CSR_DONE + CSR_IE + TXCS_TEN + TXCS_IDC) /* terminal output */ +#define TXCS_WR (CSR_IE + TXCS_TEN) +#define ID_CT 0 /* console terminal */ +#define ID_RS 1 /* remote services */ +#define ID_EMM 2 /* environmental monitoring module */ +#define ID_LC 3 /* logical console */ +#define ID_M_CT (1u << ID_CT) +#define ID_M_RS (1u << ID_RS) +#define ID_M_EMM (1u << ID_EMM) +#define ID_M_LC (1u << ID_LC) +#define RDY u3 + +/* Clock definitions */ + +#define TMR_CSR_ERR 0x80000000 /* error W1C */ +#define TMR_CSR_DON 0x00000080 /* done W1C */ +#define TMR_CSR_IE 0x00000040 /* int enb RW */ +#define TMR_CSR_SGL 0x00000020 /* single WO */ +#define TMR_CSR_XFR 0x00000010 /* xfer WO */ +#define TMR_CSR_RUN 0x00000001 /* run RW */ +#define TMR_CSR_RD (TMR_CSR_W1C | TMR_CSR_WR) +#define TMR_CSR_W1C (TMR_CSR_ERR | TMR_CSR_DON) +#define TMR_CSR_WR (TMR_CSR_IE | TMR_CSR_RUN) +#define TMR_INC 10000 /* usec/interval */ +#define CLK_DELAY 5000 /* 100 Hz */ +#define TMXR_MULT 1 /* 100 Hz */ + +/* Logical console definitions */ + +#define LC_NUMBY 128 /* response buffer size */ + +#define LC_IDLE 0 /* idle state */ +#define LC_READDAT 1 /* read data */ + +#define LC_V_FNC 0 /* logical console function */ +#define LC_M_FNC 0xFF +#define LC_FNCCW 0x3 /* clear warm start flag */ +#define LC_FNCCS 0x4 /* clear cold start flag */ +#define LC_FNCMV 0x12 /* microcode version */ +#define LC_FNCAC 0x13 /* array configuration */ +#define LC_FNCSS 0x30 /* snapshot file status */ +#define LC_FNCCA 0x70 /* cancel all */ +#define LC_GETFNC(x) (((x) >> LC_V_FNC) & LC_M_FNC) + +/* Console storage definitions */ + +#define STXCS_FNC 0xF +#define STXCS_V_DA 8 +#define STXCS_M_DA 0xFFFF +#define STXCS_DA (STXCS_M_DA << STXCS_V_DA) +#define STXCS_GETDA(x) (((x) >> STXCS_V_DA) & STXCS_M_DA) +#define STXCS_V_STS 24 +#define STXCS_M_STS 0xFF +#define STXCS_STS (STXCS_M_STS << STXCS_V_STS) +#define STXCS_WR (STXCS_FNC | CSR_DONE | CSR_IE | STXCS_DA) + +#define STXDB_DAT 0xFFFF + +#define RL_NUMBY 256 /* bytes/sector */ +#define RL_NUMWD 128 /* words/sector */ +#define RL_NUMSC 40 /* sectors/surface */ +#define RL_NUMSF 2 /* surfaces/cylinder */ +#define RL_NUMCY 512 /* cylinders/drive */ +#define RL02_SIZE (RL_NUMCY * RL_NUMSF * RL_NUMSC * RL_NUMWD) /* words/drive */ + +/* Parameters in the unit descriptor */ + +#define TRK u3 /* current track */ +#define STAT u4 /* status */ + +#define UNIT_V_WLK (UNIT_V_UF + 0) /* hwre write lock */ +#define UNIT_WLK (1u << UNIT_V_WLK) + +#define RLCS_DRDY 0000001 /* drive ready */ +#define RLCS_M_DRIVE 03 +#define RLCS_V_DRIVE 8 +#define RLCS_INCMP 0002000 /* incomplete */ +#define RLCS_CRC 0004000 /* CRC error */ +#define RLCS_HDE 0010000 /* header error */ +#define RLCS_NXM 0020000 /* non-exist memory */ +#define RLCS_DRE 0040000 /* drive error */ +#define RLCS_ERR 0100000 /* error summary */ +#define RLCS_ALLERR (RLCS_ERR+RLCS_DRE+RLCS_NXM+RLCS_HDE+RLCS_CRC+RLCS_INCMP) +#define RLCS_RW 0001776 /* read/write */ + +/* RL Function Codes */ + +#define RLFC_NOP 0 /* No Operation */ +#define RLFC_CONT 2 /* Continue Transaction */ +#define RLFC_ABORT 3 /* Abort Current Transfer */ +#define RLFC_STS 4 /* Read Device Status */ +#define RLFC_WRITE 5 /* Write Block Data */ +#define RLFC_READ 6 /* Read Block Data */ + +/* RL Status Codes */ + +#define RLST_COMP 1 /* Transaction Complete */ +#define RLST_CONT 2 /* Continue Transaction */ +#define RLST_ABORT 3 /* Transaction Aborted */ +#define RLST_STS 4 /* Return Device Status */ +#define RLST_HERR 80 /* Handshake Error */ +#define RLST_HDERR 81 /* Hardware Error */ + +/* RL States */ + +#define RL_IDLE 0 +#define RL_READ 1 +#define RL_WRITE 2 +#define RL_STATUS 3 +#define RL_ABORT 4 + +#define RL_CSR 0 /* CSR selected */ +#define RL_MP 1 /* MP selected */ + +/* RLDS, NI = not implemented, * = kept in STAT, ^ = kept in TRK */ + +#define RLDS_LOAD 0 /* no cartridge */ +#define RLDS_LOCK 5 /* lock on */ +#define RLDS_BHO 0000010 /* brushes home NI */ +#define RLDS_HDO 0000020 /* heads out NI */ +#define RLDS_CVO 0000040 /* cover open NI */ +#define RLDS_HD 0000100 /* head select ^ */ +#define RLDS_RL02 0000200 /* RL02 */ +#define RLDS_DSE 0000400 /* drv sel err NI */ +#define RLDS_VCK 0001000 /* vol check * */ +#define RLDS_WGE 0002000 /* wr gate err * */ +#define RLDS_SPE 0004000 /* spin err * */ +#define RLDS_STO 0010000 /* seek time out NI */ +#define RLDS_WLK 0020000 /* wr locked */ +#define RLDS_HCE 0040000 /* hd curr err NI */ +#define RLDS_WDE 0100000 /* wr data err NI */ +#define RLDS_ATT (RLDS_HDO+RLDS_BHO+RLDS_LOCK) /* att status */ +#define RLDS_UNATT (RLDS_CVO+RLDS_LOAD) /* unatt status */ +#define RLDS_ERR (RLDS_WDE+RLDS_HCE+RLDS_STO+RLDS_SPE+RLDS_WGE+ \ + RLDS_VCK+RLDS_DSE) /* errors bits */ + +int32 tti_csr = 0; /* control/status */ +int32 tti_buf = 0; /* buffer */ +int32 tti_int = 0; /* interrupt */ +int32 tto_csr = 0; /* control/status */ +int32 tto_int = 0; /* interrupt */ + +int32 tmr_iccs = 0; /* interval timer csr */ +uint32 tmr_icr = 0; /* curr interval */ +uint32 tmr_nicr = 0; /* next interval */ +uint32 tmr_inc = 0; /* timer increment */ +int32 tmr_sav = 0; /* timer save */ +int32 tmr_int = 0; /* interrupt */ +int32 tmr_use_100hz = 1; /* use 100Hz for timer */ +int32 clk_tps = 100; /* ticks/second */ +int32 tmxr_poll = CLK_DELAY * TMXR_MULT; /* term mux poll */ +int32 tmr_poll = CLK_DELAY; /* pgm timer poll */ +int32 todr_reg = 0; /* TODR register */ +struct todr_battery_info { + uint32 toy_gmtbase; /* GMT base of set value */ + uint32 toy_gmtbasemsec; /* The milliseconds of the set value */ + }; +typedef struct todr_battery_info TOY; + +int32 lc_fnc = 0; /* function */ +int32 lc_cwait = 50; /* command time */ +int32 lc_xwait = 20; /* tr set time */ +uint8 lc_buf[LC_NUMBY] = { 0 }; /* response buffer */ +int32 lc_bptr = 0; /* buffer pointer */ +int32 lc_dlen = 0; /* buffer data len */ + +int32 csi_int = 0; /* interrupt */ +int32 cso_csr = 0; /* control/status */ +int32 cso_buf = 0; /* buffer */ + +int32 rlcs_swait = 10; /* command time */ +int32 rlcs_state = RL_IDLE; /* protocol state */ +int32 rlcs_sts_reg = RL_CSR; /* status register */ +int32 rlcs_csr = 0; /* control/status */ +int32 rlcs_mp = 0; +int32 rlcs_bcnt = 0; /* byte count */ +uint16 *rlcs_buf = NULL; + +extern jmp_buf save_env; +extern UNIT cpu_unit; +extern int32 brk_req; + +t_stat tti_svc (UNIT *uptr); +t_stat tto_svc (UNIT *uptr); +t_stat clk_svc (UNIT *uptr); +t_stat tmr_svc (UNIT *uptr); +t_stat lc_svc (UNIT *uptr); +t_stat rlcs_svc (UNIT *uptr); +t_stat tti_reset (DEVICE *dptr); +t_stat tto_reset (DEVICE *dptr); +t_stat clk_reset (DEVICE *dptr); +t_stat clk_attach (UNIT *uptr, char *cptr); +t_stat clk_detach (UNIT *uptr); +t_stat tmr_reset (DEVICE *dptr); +t_stat lc_reset (DEVICE *dptr); +t_stat rlcs_reset (DEVICE *dptr); +t_stat rlcs_attach (UNIT *uptr, char *cptr); +int32 icr_rd (t_bool interp); +void tmr_incr (uint32 inc); +void tmr_sched (void); +t_stat todr_resync (void); +t_stat lc_wr_txdb (int32 data); + +extern int32 con_halt (int32 code, int32 cc); + +/* TTI data structures + + tti_dev TTI device descriptor + tti_unit TTI unit descriptor + tti_reg TTI register list +*/ + +UNIT tti_unit[] = { + { UDATA (&tti_svc, TT_MODE_8B, 0), 0 }, + { UDATA (&tti_svc, TT_MODE_8B, 0), 0 }, + { UDATA (&tti_svc, TT_MODE_8B, 0), 0 }, + { UDATA (&tti_svc, TT_MODE_8B, 0), 0 }, + }; + +REG tti_reg[] = { + { HRDATAD (RXDB, tti_buf, 16, "last data item processed") }, + { HRDATAD (RXCS, tti_csr, 16, "control/status register") }, + { FLDATAD (INT, tti_int, 0, "interrupt pending flag") }, + { FLDATAD (DONE, tti_csr, CSR_V_DONE, "device done flag (CSR<7>)") }, + { FLDATAD (IE, tti_csr, CSR_V_IE, "interrupt enable flag (CSR<6>)") }, + { URDATAD (POS, tti_unit[0].pos, 10, T_ADDR_W, 0, 4, PV_LEFT, "number of characters input") }, + { URDATAD (TIME, tti_unit[0].wait, 10, 24, 0, 4, PV_LEFT, "input polling interval") }, + { NULL } + }; + +MTAB tti_mod[] = { + { TT_MODE, TT_MODE_7B, "7b", "7B", NULL }, + { TT_MODE, TT_MODE_8B, "8b", "8B", NULL }, + { 0 } + }; + +DEVICE tti_dev = { + "TTI", tti_unit, tti_reg, tti_mod, + 4, 10, 31, 1, 16, 8, + NULL, NULL, &tti_reset, + NULL, NULL, NULL, + NULL, 0 + }; + +/* TTO data structures + + tto_dev TTO device descriptor + tto_unit TTO unit descriptor + tto_reg TTO register list +*/ + +UNIT tto_unit[] = { + { UDATA (&tto_svc, TT_MODE_8B, 0), SERIAL_OUT_WAIT }, + { UDATA (&tto_svc, TT_MODE_8B, 0), SERIAL_OUT_WAIT }, + { UDATA (&tto_svc, TT_MODE_8B, 0), SERIAL_OUT_WAIT }, + { UDATA (&tto_svc, TT_MODE_8B, 0), SERIAL_OUT_WAIT }, + }; + +REG tto_reg[] = { + { URDATAD (TXDB, tto_unit[0].buf, 16, 32, 0, 4, 0, "last data item processed") }, + { HRDATAD (TXCS, tto_csr, 16, "control/status register") }, + { FLDATAD (INT, tto_int, 0, "interrupt pending flag") }, + { FLDATAD (DONE, tto_csr, CSR_V_DONE, "device done flag (CSR<7>)") }, + { FLDATAD (IE, tto_csr, CSR_V_IE, "interrupt enable flag (CSR<6>)") }, + { URDATAD (POS, tto_unit[0].pos, 10, T_ADDR_W, 0, 4, PV_LEFT, "number of characters output") }, + { URDATAD (TIME, tto_unit[0].wait, 10, 24, 0, 4, PV_LEFT + REG_NZ, "time from I/O initiation to interrupt") }, + { NULL } + }; + +MTAB tto_mod[] = { + { TT_MODE, TT_MODE_7B, "7b", "7B", NULL }, + { TT_MODE, TT_MODE_8B, "8b", "8B", NULL }, + { TT_MODE, TT_MODE_7P, "7p", "7P", NULL }, + { 0 } + }; + +DEVICE tto_dev = { + "TTO", tto_unit, tto_reg, tto_mod, + 4, 10, 31, 1, 16, 8, + NULL, NULL, &tto_reset, + NULL, NULL, NULL, + NULL, 0 + }; + +/* TODR and TMR data structures */ + +UNIT clk_unit = { UDATA (&clk_svc, UNIT_IDLE+UNIT_FIX, sizeof(TOY)), CLK_DELAY };/* 100Hz */ + +REG clk_reg[] = { + { DRDATAD (TODR, todr_reg, 32, "time-of-day register"), PV_LEFT }, + { DRDATAD (TIME, clk_unit.wait, 24, "initial poll interval"), REG_NZ + PV_LEFT }, + { DRDATAD (POLL, tmr_poll, 24, "calibrated poll interval"), REG_NZ + PV_LEFT + REG_HRO }, + { DRDATAD (TPS, clk_tps, 8, "ticks per second (100)"), REG_NZ + PV_LEFT }, +#if defined (SIM_ASYNCH_IO) + { DRDATAD (ASYNCH, sim_asynch_enabled, 1, "asynch I/O enabled flag"), PV_LEFT }, + { DRDATAD (LATENCY, sim_asynch_latency, 32, "desired asynch interrupt latency"), PV_LEFT }, + { DRDATAD (INST_LATENCY, sim_asynch_inst_latency, 32, "calibrated instruction latency"), PV_LEFT }, +#endif + { NULL } + }; + +DEVICE clk_dev = { + "TODR", &clk_unit, clk_reg, NULL, + 1, 0, 8, 4, 0, 32, + NULL, NULL, &clk_reset, + NULL, &clk_attach, &clk_detach, + NULL, 0 + }; + +UNIT tmr_unit = { UDATA (&tmr_svc, 0, 0) }; /* timer */ + +REG tmr_reg[] = { + { HRDATAD (ICCS, tmr_iccs, 32, "interval timer control and status") }, + { HRDATAD (ICR, tmr_icr, 32, "interval count register") }, + { HRDATAD (NICR, tmr_nicr, 32, "next interval count register") }, + { FLDATAD (INT, tmr_int, 0, "interrupt request") }, + { HRDATA (INCR, tmr_inc, 32), REG_HIDDEN }, + { HRDATA (SAVE, tmr_sav, 32), REG_HIDDEN }, + { FLDATA (USE100HZ, tmr_use_100hz, 0), REG_HIDDEN }, + { NULL } + }; + +DEVICE tmr_dev = { + "TMR", &tmr_unit, tmr_reg, NULL, + 1, 0, 0, 0, 0, 0, + NULL, NULL, &tmr_reset, + NULL, NULL, NULL, + NULL, 0 + }; + +/* Console storage structures + + rlcs_dev CS device descriptor + rlcs_unit CS unit list + rlcs_reg CS register list + rlcs_mod CS modifier list +*/ + +UNIT rlcs_unit = { UDATA (&rlcs_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_ROABLE, RL02_SIZE) }; + +REG rlcs_reg[] = { + { HRDATAD (CSR, rlcs_csr, 16, "control/status register") }, + { HRDATAD (MP, rlcs_mp, 16, "") }, + { DRDATAD (BCNT, rlcs_bcnt, 7, "byte count register") }, + { DRDATAD (STIME, rlcs_swait, 24, "command time"), PV_LEFT }, + { NULL } + }; + +MTAB rlcs_mod[] = { + { UNIT_WLK, 0, "write enabled", "WRITEENABLED", NULL }, + { UNIT_WLK, UNIT_WLK, "write locked", "LOCKED", NULL }, + { 0 } + }; + +DEVICE rlcs_dev = { + "CS", &rlcs_unit, rlcs_reg, rlcs_mod, + 1, 10, 24, 1, 16, 16, + NULL, NULL, &rlcs_reset, + NULL, &rlcs_attach, NULL, + NULL, 0 + }; + +/* Terminal MxPR routines + + rxcs_rd/wr input control/status + rxdb_rd input buffer + txcs_rd/wr output control/status + txdb_wr output buffer +*/ + +int32 rxcs_rd (void) +{ +return (tti_csr & RXCS_RD); +} + +void rxcs_wr (int32 data) +{ +if ((data & CSR_IE) == 0) + tti_int = 0; +else if ((tti_csr & (CSR_DONE + CSR_IE)) == CSR_DONE) + tti_int = 1; +tti_csr = (tti_csr & ~RXCS_WR) | (data & RXCS_WR); +return; +} + +int32 rxdb_rd (void) +{ +int32 t = tti_buf; +t = t | ((ID_M_LC | ID_M_EMM | ID_M_CT) << RXDB_V_LC); /* char + DTR for hard-wired lines */ +tti_csr = tti_csr & ~CSR_DONE; /* clr done */ +tti_int = 0; +return t; +} + +void tto_update_int (void) +{ +int32 id = 0; + +tto_csr = tto_csr & ~TXCS_IDC; +if ((tto_csr & (ID_M_LC << TXCS_V_TEN)) && + (tto_unit[ID_LC].RDY)) /* logical console enabled and ready? */ + id = ID_LC; +else if ((tto_csr & (ID_M_EMM << TXCS_V_TEN)) && + (tto_unit[ID_EMM].RDY)) /* EMM enabled and ready? */ + id = ID_EMM; +else if ((tto_csr & (ID_M_RS << TXCS_V_TEN)) && + (tto_unit[ID_RS].RDY)) /* remote services enabled and ready? */ + id = ID_RS; +else if ((tto_csr & (ID_M_CT << TXCS_V_TEN)) && + (tto_unit[ID_CT].RDY)) /* console terminal enabled and ready? */ + id = ID_CT; +else id = 0xF; /* no lines enabled */ +tto_csr = tto_csr | (id << TXCS_V_IDC); +tto_csr = tto_csr | CSR_DONE; +if (tto_csr & CSR_IE) + tto_int = 1; +} + +int32 txcs_rd (void) +{ +return (tto_csr & TXCS_RD); +} + +void txcs_wr (int32 data) +{ +tto_csr = (tto_csr & ~TXCS_WR) | (data & TXCS_WR); +if (data & TXCS_WMN) /* updating mask? */ + tto_update_int (); +if ((data & CSR_IE) == 0) + tto_int = 0; +else if ((tto_csr & (CSR_DONE + CSR_IE)) == CSR_DONE) + tto_int = 1; +return; +} + +void txdb_wr (int32 data) +{ +int32 dest = (tto_csr >> TXCS_V_IDC) & TXCS_M_IDC; +if ((dest >= ID_CT) && (dest <= ID_LC)) { /* valid line? */ + tto_csr = tto_csr & ~CSR_DONE; /* clear flag */ + tto_int = 0; /* clear int */ + tto_unit[dest].buf = data & WMASK; + tto_unit[dest].RDY = 0; + sim_activate (&tto_unit[dest], tto_unit[dest].wait);/* activate unit */ + } +return; +} + +int32 stxcs_rd (void) +{ +return cso_csr; +} + +void stxcs_wr (int32 data) +{ +int32 fnc = data & STXCS_FNC; +cso_csr = (cso_csr & ~STXCS_WR) | (data & STXCS_WR); +cso_csr = cso_csr & ~STXCS_STS; + +switch (fnc) { + case RLFC_NOP: + break; + + case RLFC_CONT: + rlcs_bcnt = 0; + case RLFC_STS: + rlcs_state = RL_STATUS; + cso_csr = cso_csr & ~CSR_DONE; /* clear done */ + sim_activate (&rlcs_unit, rlcs_swait); + break; + + case RLFC_ABORT: + rlcs_state = RL_ABORT; + cso_csr = cso_csr & ~CSR_DONE; /* clear done */ + sim_activate (&rlcs_unit, rlcs_swait); + break; + + case RLFC_WRITE: + rlcs_state = RL_WRITE; + cso_csr = cso_csr & ~CSR_DONE; /* clear done */ + sim_activate (&rlcs_unit, rlcs_swait); + break; + + case RLFC_READ: + rlcs_state = RL_READ; + cso_csr = cso_csr & ~CSR_DONE; /* clear done */ + sim_activate (&rlcs_unit, rlcs_swait); + break; + + default: + printf ("CS: Unknown Command: %d\n", fnc); + } +} + +int32 stxdb_rd (void) +{ +return cso_buf & STXDB_DAT; +} + +void stxdb_wr (int32 data) +{ +cso_buf = data & STXDB_DAT; + +if (rlcs_state == RL_WRITE) { + rlcs_buf[rlcs_bcnt] = cso_buf; + rlcs_bcnt++; + } +} + +/* Terminal input service (poll for character) */ + +t_stat tti_svc (UNIT *uptr) +{ +int32 c; +int32 line = uptr - tti_dev.units; + +switch (line) { + + case ID_CT: /* console terminal */ + sim_clock_coschedule (uptr, tmxr_poll); /* continue poll */ + if ((tti_csr & CSR_DONE) == 0) { /* prev data taken? */ + if ((c = sim_poll_kbd ()) < SCPE_KFLAG) /* no char or error? */ + return c; + if (c & SCPE_BREAK) /* break? */ + tti_buf = 0; + else tti_buf = sim_tt_inpcvt (c, TT_GET_MODE (uptr->flags)); + } + break; + + case ID_LC: /* logical console */ + if (lc_bptr > 0) { + if ((tti_csr & CSR_DONE) == 0) { /* prev data taken? */ + tti_buf = lc_buf[--lc_bptr]; /* get next byte */ + tti_buf |= (ID_LC << RXDB_V_IDC); /* source = logical console */ + if (lc_bptr == 0) /* buffer empty? */ + break; /* done */ + } + sim_activate (uptr, lc_xwait); /* schedule next */ + } + break; + } +uptr->pos = uptr->pos + 1; +tti_csr = tti_csr | CSR_DONE; +if (tti_csr & CSR_IE) + tti_int = 1; +return SCPE_OK; +} + +/* Terminal input reset */ + +t_stat tti_reset (DEVICE *dptr) +{ +tmxr_set_console_units (tti_unit, tto_unit); +tti_buf = 0; +tti_csr = 0; +tti_int = 0; +sim_activate_abs (&tti_unit[ID_CT], KBD_WAIT (tti_unit[ID_CT].wait, tmr_poll)); +return SCPE_OK; +} + +/* Terminal output service (output character) */ + +t_stat tto_svc (UNIT *uptr) +{ +int32 c; +int32 line = uptr - tto_dev.units; +t_stat r; + +switch (line) { + + case ID_CT: /* console terminal */ + c = sim_tt_outcvt (uptr->buf, TT_GET_MODE (uptr->flags)); + if (c >= 0) { + if ((r = sim_putchar_s (c)) != SCPE_OK) { /* output; error? */ + sim_activate (uptr, uptr->wait); /* retry */ + return ((r == SCPE_STALL)? SCPE_OK: r); /* !stall? report */ + } + } + break; + + case ID_LC: /* logical console */ + lc_wr_txdb (uptr->buf); + break; + } +uptr->pos = uptr->pos + 1; +uptr->RDY = 1; +tto_update_int (); +return SCPE_OK; +} + +/* Terminal output reset */ + +t_stat tto_reset (DEVICE *dptr) +{ +tto_csr = (ID_M_CT << TXCS_V_TEN) | CSR_DONE; /* console enabled + done */ +tto_int = 0; +tto_unit[ID_CT].RDY = 1; /* all lines ready */ +tto_unit[ID_RS].RDY = 1; +tto_unit[ID_EMM].RDY = 1; +tto_unit[ID_LC].RDY = 1; +sim_cancel (&tto_unit[ID_CT]); /* deactivate units */ +sim_cancel (&tto_unit[ID_RS]); +sim_cancel (&tto_unit[ID_EMM]); +sim_cancel (&tto_unit[ID_LC]); +return SCPE_OK; +} + +/* Programmable timer + + The architected VAX timer, which increments at 1Mhz, cannot be + accurately simulated due to the overhead that would be required + for 1M clock events per second. Instead, a hidden calibrated + 100Hz timer is run (because that's what VMS expects), and a + hack is used for the interval timer. + + When the timer is started, the timer interval is inspected. + + if the interval is >= 10msec, then the 100Hz timer drives the + next interval + if the interval is < 10mec, then count instructions + + If the interval register is read, then its value between events + is interpolated using the current instruction count versus the + count when the most recent event started, the result is scaled + to the calibrated system clock, unless the interval being timed + is less than a calibrated system clock tick (or the calibrated + clock is running very slowly) at which time the result will be + the elapsed instruction count. +*/ + +int32 iccs_rd (void) +{ +return tmr_iccs & TMR_CSR_RD; +} + +void iccs_wr (int32 val) +{ +if ((val & TMR_CSR_RUN) == 0) { /* clearing run? */ + sim_cancel (&tmr_unit); /* cancel timer */ + tmr_use_100hz = 0; + if (tmr_iccs & TMR_CSR_RUN) /* run 1 -> 0? */ + tmr_icr = icr_rd (TRUE); /* update itr */ + } +tmr_iccs = tmr_iccs & ~(val & TMR_CSR_W1C); /* W1C csr */ +tmr_iccs = (tmr_iccs & ~TMR_CSR_WR) | /* new r/w */ + (val & TMR_CSR_WR); +if (val & TMR_CSR_XFR) tmr_icr = tmr_nicr; /* xfr set? */ +if (val & TMR_CSR_RUN) { /* run? */ + if (val & TMR_CSR_XFR) /* new tir? */ + sim_cancel (&tmr_unit); /* stop prev */ + if (!sim_is_active (&tmr_unit)) /* not running? */ + tmr_sched (); /* activate */ + } +else if (val & TMR_CSR_SGL) { /* single step? */ + tmr_incr (1); /* incr tmr */ + if (tmr_icr == 0) /* if ovflo, */ + tmr_icr = tmr_nicr; /* reload tir */ + } +if ((tmr_iccs & (TMR_CSR_DON | TMR_CSR_IE)) != /* update int */ + (TMR_CSR_DON | TMR_CSR_IE)) + tmr_int = 0; +return; +} + +int32 icr_rd (t_bool interp) +{ +uint32 delta; + +if (interp || (tmr_iccs & TMR_CSR_RUN)) { /* interp, running? */ + delta = sim_grtime () - tmr_sav; /* delta inst */ + if (tmr_use_100hz && (tmr_poll > TMR_INC)) /* scale large int */ + delta = (uint32) ((((double) delta) * TMR_INC) / tmr_poll); + if (delta >= tmr_inc) + delta = tmr_inc - 1; + return tmr_icr + delta; + } +return tmr_icr; +} + +int32 nicr_rd () +{ +return tmr_nicr; +} + +void nicr_wr (int32 val) +{ +tmr_nicr = val; +} + +/* 100Hz base clock unit service */ + +t_stat clk_svc (UNIT *uptr) +{ +tmr_poll = sim_rtcn_calb (clk_tps, TMR_CLK); /* calibrate clock */ +sim_activate (&clk_unit, tmr_poll); /* reactivate unit */ +tmxr_poll = tmr_poll * TMXR_MULT; /* set mux poll */ +todr_reg = todr_reg + 1; /* incr TODR */ +if ((tmr_iccs & TMR_CSR_RUN) && tmr_use_100hz) /* timer on, std intvl? */ + tmr_incr (TMR_INC); /* do timer service */ +return SCPE_OK; +} + +/* Interval timer unit service */ + +t_stat tmr_svc (UNIT *uptr) +{ +tmr_incr (tmr_inc); /* incr timer */ +return SCPE_OK; +} + +/* Timer increment */ + +void tmr_incr (uint32 inc) +{ +uint32 new_icr = (tmr_icr + inc) & LMASK; /* add incr */ + +if (new_icr < tmr_icr) { /* ovflo? */ + tmr_icr = 0; /* now 0 */ + if (tmr_iccs & TMR_CSR_DON) /* done? set err */ + tmr_iccs = tmr_iccs | TMR_CSR_ERR; + else tmr_iccs = tmr_iccs | TMR_CSR_DON; /* set done */ + if (tmr_iccs & TMR_CSR_RUN) { /* run? */ + tmr_icr = tmr_nicr; /* reload */ + tmr_sched (); /* reactivate */ + } + if (tmr_iccs & TMR_CSR_IE) /* ie? set int req */ + tmr_int = 1; + else tmr_int = 0; + } +else { + tmr_icr = new_icr; /* no, update icr */ + if (tmr_iccs & TMR_CSR_RUN) /* still running? */ + tmr_sched (); /* reactivate */ + } +return; +} + +/* Timer scheduling */ + +void tmr_sched (void) +{ +tmr_sav = sim_grtime (); /* save intvl base */ +tmr_inc = (~tmr_icr + 1); /* inc = interval */ +if (tmr_inc == 0) tmr_inc = 1; +if (tmr_inc < TMR_INC) { /* 100Hz multiple? */ + sim_activate (&tmr_unit, tmr_inc); /* schedule timer */ + tmr_use_100hz = 0; + } +else tmr_use_100hz = 1; /* let clk handle */ +return; +} + +/* 100Hz clock reset */ + +t_stat clk_reset (DEVICE *dptr) +{ +tmr_poll = sim_rtcn_init (clk_unit.wait, TMR_CLK); /* init 100Hz timer */ +sim_activate (&clk_unit, tmr_poll); /* activate 100Hz unit */ +tmxr_poll = tmr_poll * TMXR_MULT; /* set mux poll */ +if (clk_unit.filebuf == NULL) { /* make sure the TODR is initialized */ + clk_unit.filebuf = calloc(sizeof(TOY), 1); + if (clk_unit.filebuf == NULL) + return SCPE_MEM; + todr_resync (); + } +return SCPE_OK; +} + +/* CLK attach */ + +t_stat clk_attach (UNIT *uptr, char *cptr) +{ +t_stat r; + +uptr->flags = uptr->flags | (UNIT_ATTABLE | UNIT_BUFABLE); +memset (uptr->filebuf, 0, (size_t)uptr->capac); +r = attach_unit (uptr, cptr); +if (r != SCPE_OK) + uptr->flags = uptr->flags & ~(UNIT_ATTABLE | UNIT_BUFABLE); +else + uptr->hwmark = (uint32) uptr->capac; +return r; +} + +/* CLK detach */ + +t_stat clk_detach (UNIT *uptr) +{ +t_stat r; + +r = detach_unit (uptr); +if ((uptr->flags & UNIT_ATT) == 0) + uptr->flags = uptr->flags & ~(UNIT_ATTABLE | UNIT_BUFABLE); +return r; +} + +/* Interval timer reset */ + +t_stat tmr_reset (DEVICE *dptr) +{ +tmr_iccs = 0; +tmr_icr = 0; +tmr_nicr = 0; +tmr_int = 0; +tmr_use_100hz = 1; +sim_cancel (&tmr_unit); /* cancel timer */ +todr_resync (); /* resync TODR */ +return SCPE_OK; +} + +/* TODR routines */ + +int32 todr_rd (void) +{ +TOY *toy = (TOY *)clk_unit.filebuf; +struct timespec base, now, val; + +clock_gettime(CLOCK_REALTIME, &now); /* get curr time */ +base.tv_sec = toy->toy_gmtbase; +base.tv_nsec = toy->toy_gmtbasemsec * 1000000; +sim_timespec_diff (&val, &now, &base); +return (int32)(val.tv_sec*100 + val.tv_nsec/10000000); /* 100hz Clock Ticks */ +} + +void todr_wr (int32 data) +{ +TOY *toy = (TOY *)clk_unit.filebuf; +struct timespec now, val, base; + +/* Save the GMT time when set value was 0 to record the base for future + read operations in "battery backed-up" state */ + +if (-1 == clock_gettime(CLOCK_REALTIME, &now)) /* get curr time */ + return; /* error? */ +val.tv_sec = ((uint32)data) / 100; +val.tv_nsec = (((uint32)data) % 100) * 10000000; +sim_timespec_diff (&base, &now, &val); /* base = now - data */ +toy->toy_gmtbase = (uint32)base.tv_sec; +toy->toy_gmtbasemsec = base.tv_nsec/1000000; +} + +t_stat todr_resync (void) +{ +TOY *toy = (TOY *)clk_unit.filebuf; + +if (clk_unit.flags & UNIT_ATT) { /* Attached means behave like real VAX860 */ + if (!toy->toy_gmtbase) /* Never set? */ + todr_wr (0); /* Start ticking from 0 */ + } +else { /* Not-Attached means */ + uint32 base; /* behave like simh VMS default */ + time_t curr; + struct tm *ctm; + + curr = time (NULL); /* get curr time */ + if (curr == (time_t) -1) /* error? */ + return SCPE_NOFNC; + ctm = localtime (&curr); /* decompose */ + if (ctm == NULL) /* error? */ + return SCPE_NOFNC; + base = (((((ctm->tm_yday * 24) + /* sec since 1-Jan */ + ctm->tm_hour) * 60) + + ctm->tm_min) * 60) + + ctm->tm_sec; + todr_wr ((base * 100) + 0x10000000); /* use VMS form */ + } +return SCPE_OK; +} + +/* Logical console write */ + +t_stat lc_wr_txdb (int32 data) +{ +int32 i; +int32 mask = 0; + +lc_fnc = LC_GETFNC (data); /* get function */ +if (lc_bptr > 0) /* cmd in prog? */ + switch (lc_fnc) { + + case LC_FNCCA: /* cancel */ + sim_cancel (&tti_unit[ID_LC]); + lc_bptr = 0; + break; + + default: /* all others */ + return SCPE_OK; + } + +else switch (lc_fnc) { /* idle, case */ + + case LC_FNCCW: /* clear warm start flag */ + break; + + case LC_FNCCS: /* clear cold start flag */ + break; + + case LC_FNCMV: /* microcode version */ + lc_buf[2] = LC_FNCMV; + lc_buf[1] = VER_UCODE & 0xFF; /* low byte */ + lc_buf[0] = (VER_UCODE >> 8) & 0xFF; /* high byte */ + lc_bptr = 3; + sim_activate (&tti_unit[ID_LC], lc_cwait); /* sched command */ + break; + + case LC_FNCAC: /* array configuration */ + lc_buf[3] = LC_FNCAC; + if (MEMSIZE < MAXMEMSIZE) { /* 4MB Boards */ + lc_buf[2] = (uint8)(MEMSIZE >> 22); /* slots in use */ + for (i = 0; i < lc_buf[2]; i++) { + mask |= (2 << (i * 2)); /* build array mask */ + } + } + else { + lc_buf[2] = (uint8)(MEMSIZE >> 24); /* 16MB Boards */ + for (i = 0; i < lc_buf[2]; i++) { + mask |= (1 << (i * 2)); /* build array mask */ + } + } + lc_buf[1] = mask & 0xFF; /* slots 1 - 4 */ + lc_buf[0] = (mask >> 8) & 0xFF; /* slots 5 - 8 */ + lc_bptr = 4; + sim_activate (&tti_unit[ID_LC], lc_cwait); /* sched command */ + break; + + case LC_FNCSS: /* snapshot file status */ + lc_buf[1] = LC_FNCSS; + lc_buf[0] = 0x0; /* both invalid */ + lc_bptr = 2; + sim_activate (&tti_unit[ID_LC], lc_cwait); /* sched command */ + break; + + default: /* all others */ + printf ("TTO3: Unknown console command: %X\n", lc_fnc); + break; + } +return SCPE_OK; +} + +/* Unit service; the action to be taken depends on the transfer state: + + RL_IDLE Should never get here + RL_READ Read byte, Set STXCS + RL_WRITE Write byte, Set STXCS + RL_ABORT Set STXCS + RL_STATUS Copy requested data to STXDB, Set STXCS +*/ + +t_stat rlcs_svc (UNIT *uptr) +{ +int32 bcnt; +uint32 da; + +switch (rlcs_state) { + + case RL_IDLE: + return SCPE_IERR; + + case RL_READ: + if ((cso_csr & CSR_DONE) == 0) { /* buf ready? */ + if (rlcs_bcnt == 0) { /* read in whole block */ + da = STXCS_GETDA(cso_csr) * 512; /* get byte offset */ + if (sim_fseek (uptr->fileref, da, SEEK_SET)) + return SCPE_IOERR; + bcnt = sim_fread (rlcs_buf, sizeof (int16), RL_NUMBY, uptr->fileref); + } + if (rlcs_bcnt < RL_NUMBY) { /* more data in buffer? */ + cso_buf = rlcs_buf[rlcs_bcnt++]; /* return next word */ + cso_csr = cso_csr | CSR_DONE | /* continue */ + (RLST_CONT << STXCS_V_STS); + } + else { + cso_csr = cso_csr | CSR_DONE | /* complete */ + (RLST_COMP << STXCS_V_STS); + rlcs_state = RL_IDLE; /* now idle */ + rlcs_bcnt = 0; + } + if (cso_csr & CSR_IE) + csi_int = 1; + break; + } + sim_activate (uptr, rlcs_swait); /* schedule next */ + break; + + case RL_WRITE: + if (rlcs_bcnt < RL_NUMBY) { /* more data to buffer? */ + cso_csr = cso_csr | CSR_DONE | /* continue */ + (RLST_CONT << STXCS_V_STS); + } + else { + da = STXCS_GETDA(cso_csr) * 512; /* get byte offset */ + if (sim_fseek (uptr->fileref, da, SEEK_SET)) + return SCPE_IOERR; + bcnt = sim_fwrite (rlcs_buf, sizeof (int16), RL_NUMBY, uptr->fileref); + rlcs_state = RL_IDLE; /* now idle */ + rlcs_bcnt = 0; + cso_csr = cso_csr | CSR_DONE | /* complete */ + (RLST_COMP << STXCS_V_STS); + } + if (cso_csr & CSR_IE) + csi_int = 1; + break; + + case RL_ABORT: + if ((cso_csr & CSR_DONE) == 0) { /* buf ready? */ + cso_csr = cso_csr | CSR_DONE | /* aborted */ + (RLST_ABORT << STXCS_V_STS); + cso_buf = 0; + rlcs_bcnt = 0; + rlcs_state = RL_IDLE; + if (cso_csr & CSR_IE) + csi_int = 1; + break; + } + sim_activate (uptr, rlcs_swait); /* schedule next */ + break; + + case RL_STATUS: + if ((cso_csr & CSR_DONE) == 0) { /* buf ready? */ + switch (rlcs_sts_reg) { /* which register? */ + + case RL_CSR: + if (rlcs_csr & RLCS_ALLERR) /* any errors? */ + rlcs_csr = rlcs_csr | RLCS_ERR; /* set master error bit */ + if (rlcs_bcnt > 0) /* transfer in progress? */ + rlcs_csr = rlcs_csr & ~RLCS_DRDY; + else rlcs_csr = rlcs_csr | RLCS_DRDY; + cso_buf = rlcs_csr; + rlcs_sts_reg = RL_MP; /* MP on next read */ + break; + + case RL_MP: + if ((uptr->flags & UNIT_ATT) == 0) /* update status */ + rlcs_mp = RLDS_UNATT; + else rlcs_mp = RLDS_ATT; + cso_buf = rlcs_mp; + rlcs_sts_reg = RL_CSR; /* MP on next read */ + break; + } + cso_csr = cso_csr | CSR_DONE | /* returning status */ + (RLST_STS << STXCS_V_STS); + rlcs_state = RL_IDLE; + if (cso_csr & CSR_IE) + csi_int = 1; + break; + } + sim_activate (uptr, rlcs_swait); /* schedule next */ + break; + } +return SCPE_OK; +} + +/* Reset */ + +t_stat rlcs_reset (DEVICE *dptr) +{ +cso_buf = 0; +cso_csr = CSR_DONE; +csi_int = 0; +rlcs_state = RL_IDLE; +rlcs_csr = 0; +rlcs_sts_reg = RL_CSR; +rlcs_bcnt = 0; +if (rlcs_buf == NULL) + rlcs_buf = (uint16 *) calloc (RL_NUMBY, sizeof (uint16)); +if (rlcs_buf == NULL) + return SCPE_MEM; +sim_cancel (&rlcs_unit); /* deactivate unit */ +return SCPE_OK; +} + +t_stat rlcs_attach (UNIT *uptr, char *cptr) +{ +uint32 p; +t_stat r; + +uptr->capac = RL02_SIZE; +r = attach_unit (uptr, cptr); /* attach unit */ +if (r != SCPE_OK) /* error? */ + return r; +uptr->TRK = 0; /* cylinder 0 */ +uptr->STAT = RLDS_VCK; /* new volume */ +if ((p = sim_fsize (uptr->fileref)) == 0) { /* new disk image? */ + if (uptr->flags & UNIT_RO) /* if ro, done */ + return SCPE_OK; + return pdp11_bad_block (uptr, RL_NUMSC, RL_NUMWD); + } +return SCPE_OK; +} diff --git a/VAX/vax860_syslist.c b/VAX/vax860_syslist.c new file mode 100644 index 00000000..b3ecba50 --- /dev/null +++ b/VAX/vax860_syslist.c @@ -0,0 +1,129 @@ +/* vax860_syslist.c: VAX 8600 device list + + Copyright (c) 2011-2012, Matt Burke + This module incorporates code from SimH, Copyright (c) 1998-2008, Robert M Supnik + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name(s) of the author(s) shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from the author(s). + + 26-Dec-2012 MB First version +*/ + +#include "vax_defs.h" + +char sim_name[] = "VAX860"; + +extern DEVICE cpu_dev; +extern DEVICE tlb_dev; +extern DEVICE abus_dev; +extern DEVICE sbia_dev; +extern DEVICE uba_dev; +extern DEVICE mba_dev[MBA_NUM]; +extern DEVICE clk_dev; +extern DEVICE tmr_dev; +extern DEVICE tti_dev, tto_dev; +extern DEVICE rlcs_dev; +extern DEVICE cr_dev; +extern DEVICE lpt_dev; +extern DEVICE rq_dev, rqb_dev, rqc_dev, rqd_dev; +extern DEVICE rl_dev; +extern DEVICE hk_dev; +extern DEVICE rp_dev; +extern DEVICE ry_dev; +extern DEVICE ts_dev; +extern DEVICE tq_dev; +extern DEVICE tu_dev; +extern DEVICE dz_dev; +extern DEVICE xu_dev, xub_dev; +extern DEVICE dmc_dev[]; + +extern UNIT cpu_unit; +extern void WriteB (uint32 pa, int32 val); + +DEVICE *sim_devices[] = { + &cpu_dev, + &tlb_dev, + &abus_dev, + &sbia_dev, + &uba_dev, + &mba_dev[0], + &mba_dev[1], + &clk_dev, + &tmr_dev, + &tti_dev, + &tto_dev, + &rlcs_dev, + &dz_dev, + &cr_dev, + &lpt_dev, + &rp_dev, + &rl_dev, + &hk_dev, + &rq_dev, + &rqb_dev, + &rqc_dev, + &rqd_dev, + &ry_dev, + &tu_dev, + &ts_dev, + &tq_dev, + &xu_dev, + &xub_dev, + &dmc_dev[0], + &dmc_dev[1], + &dmc_dev[2], + &dmc_dev[3], + NULL + }; + +/* Binary loader + + The binary loader handles absolute system images, that is, system + images linked /SYSTEM. These are simply a byte stream, with no + origin or relocation information. + + -o for memory, specify origin +*/ + +t_stat sim_load (FILE *fileref, char *cptr, char *fnam, int flag) +{ +t_stat r; +int32 val; +uint32 origin, limit; + +if (flag) /* dump? */ + return SCPE_ARG; +origin = 0; /* memory */ +limit = (uint32) cpu_unit.capac; +if (sim_switches & SWMASK ('O')) { /* origin? */ + origin = (int32) get_uint (cptr, 16, 0xFFFFFFFF, &r); + if (r != SCPE_OK) + return SCPE_ARG; + } + +while ((val = getc (fileref)) != EOF) { /* read byte stream */ + if (origin >= limit) /* NXM? */ + return SCPE_NXM; + WriteB (origin, val); /* memory */ + origin = origin + 1; + } +return SCPE_OK; +} diff --git a/VAX/vax_cis.c b/VAX/vax_cis.c index 3eec163e..e15eb23b 100644 --- a/VAX/vax_cis.c +++ b/VAX/vax_cis.c @@ -71,8 +71,8 @@ typedef struct { uint32 val[DSTRLNT]; } DSTR; -static DSTR Dstr_zero = { 0, 0, 0, 0, 0 }; -static DSTR Dstr_one = { 0, 0x10, 0, 0, 0 }; +static DSTR Dstr_zero = { 0, {0, 0, 0, 0} }; +static DSTR Dstr_one = { 0, {0x10, 0, 0, 0} }; extern int32 R[16]; extern int32 PSL; @@ -80,7 +80,6 @@ extern int32 trpirq; extern int32 p1; extern int32 fault_PC; extern int32 ibcnt, ppc; -extern int32 sim_interval; extern jmp_buf save_env; int32 ReadDstr (int32 lnt, int32 addr, DSTR *dec, int32 acc); diff --git a/VAX/vax_cmode.c b/VAX/vax_cmode.c index dbf6d4cf..72ce6302 100644 --- a/VAX/vax_cmode.c +++ b/VAX/vax_cmode.c @@ -59,8 +59,6 @@ extern int32 recqptr; /* recq pointer */ extern int32 pcq[]; extern int32 pcq_p; extern int32 ibcnt, ppc; -extern int32 sim_interval; -extern uint32 sim_brk_summ; extern jmp_buf save_env; int32 GeteaB (int32 spec); @@ -597,7 +595,7 @@ switch ((IR >> 12) & 017) { /* decode IR<15:12> */ cc = CC_V | CC_C; /* set cc's */ break; /* done */ } - if ((src == LSIGN) && (src2 == WMASK)) { /* -2^31 / -1? */ + if (((uint32)src == LSIGN) && ((uint32)src2 == WMASK)) { /* -2^31 / -1? */ cc = CC_V; /* overflow */ break; /* done */ } @@ -669,7 +667,7 @@ switch ((IR >> 12) & 017) { /* decode IR<15:12> */ dst = ((uint32) src) << src2; i = ((src >> (32 - src2)) | (-sign << src2)) & LMASK; oc = (i & 1)? CC_C: 0; - if ((dst & LSIGN)? (i != LMASK): (i != 0)) + if ((dst & LSIGN)? ((uint32)i != LMASK): (i != 0)) oc = oc | CC_V; } else if (src2 == 32) { /* [32] = -32 */ diff --git a/VAX/vax_cpu.c b/VAX/vax_cpu.c index a5d476cc..c575d926 100644 --- a/VAX/vax_cpu.c +++ b/VAX/vax_cpu.c @@ -305,14 +305,9 @@ const uint32 align[4] = { /* External and forward references */ -extern int32 sim_interval; -extern int32 sim_int_char; -extern int32 sim_switches; -extern uint32 sim_brk_types, sim_brk_dflt, sim_brk_summ; /* breakpoint info */ -extern t_bool sim_idle_enab; - extern t_stat build_dib_tab (void); extern UNIT rom_unit, nvr_unit; +extern int32 sys_model; extern int32 op_ashq (int32 *opnd, int32 *rh, int32 *flg); extern int32 op_emul (int32 mpy, int32 mpc, int32 *rh); extern int32 op_ediv (int32 *opnd, int32 *rh, int32 *flg); @@ -413,86 +408,80 @@ UNIT cpu_unit = { }; REG cpu_reg[] = { - { HRDATA (PC, R[nPC], 32) }, - { HRDATA (R0, R[0], 32) }, - { HRDATA (R1, R[1], 32) }, - { HRDATA (R2, R[2], 32) }, - { HRDATA (R3, R[3], 32) }, - { HRDATA (R4, R[4], 32) }, - { HRDATA (R5, R[5], 32) }, - { HRDATA (R6, R[6], 32) }, - { HRDATA (R7, R[7], 32) }, - { HRDATA (R8, R[8], 32) }, - { HRDATA (R9, R[9], 32) }, - { HRDATA (R10, R[10], 32) }, - { HRDATA (R11, R[11], 32) }, - { HRDATA (R12, R[12], 32) }, - { HRDATA (R13, R[13], 32) }, - { HRDATA (R14, R[14], 32) }, - { HRDATA (AP, R[nAP], 32) }, - { HRDATA (FP, R[nFP], 32) }, - { HRDATA (SP, R[nSP], 32) }, - { HRDATA (PSL, PSL, 32) }, - { HRDATA (CC, PSL, 4) }, - { HRDATA (KSP, KSP, 32) }, - { HRDATA (ESP, ESP, 32) }, - { HRDATA (SSP, SSP, 32) }, - { HRDATA (USP, USP, 32) }, - { HRDATA (IS, IS, 32) }, - { HRDATA (SCBB, SCBB, 32) }, - { HRDATA (PCBB, PCBB, 32) }, - { HRDATA (P0BR, P0BR, 32) }, - { HRDATA (P0LR, P0LR, 22) }, - { HRDATA (P1BR, P1BR, 32) }, - { HRDATA (P1LR, P1LR, 22) }, - { HRDATA (SBR, SBR, 32) }, - { HRDATA (SLR, SLR, 22) }, - { HRDATA (SISR, SISR, 16) }, - { HRDATA (ASTLVL, ASTLVL, 4) }, - { FLDATA (MAPEN, mapen, 0) }, - { FLDATA (PME, pme, 0) }, - { HRDATA (TRPIRQ, trpirq, 8) }, - { FLDATA (CRDERR, crd_err, 0) }, - { FLDATA (MEMERR, mem_err, 0) }, - { FLDATA (HLTPIN, hlt_pin, 0) }, + { HRDATAD (PC, R[nPC], 32, "program counter") }, + { HRDATAD (R0, R[0], 32, "General Purpose Register 0") }, + { HRDATAD (R1, R[1], 32, "General Purpose Register 1") }, + { HRDATAD (R2, R[2], 32, "General Purpose Register 2") }, + { HRDATAD (R3, R[3], 32, "General Purpose Register 3") }, + { HRDATAD (R4, R[4], 32, "General Purpose Register 4") }, + { HRDATAD (R5, R[5], 32, "General Purpose Register 5") }, + { HRDATAD (R6, R[6], 32, "General Purpose Register 6") }, + { HRDATAD (R7, R[7], 32, "General Purpose Register 7") }, + { HRDATAD (R8, R[8], 32, "General Purpose Register 8") }, + { HRDATAD (R9, R[9], 32, "General Purpose Register 9") }, + { HRDATAD (R10, R[10], 32, "General Purpose Register 10") }, + { HRDATAD (R11, R[11], 32, "General Purpose Register 11") }, + { HRDATAD (R12, R[12], 32, "General Purpose Register 12") }, + { HRDATAD (R13, R[13], 32, "General Purpose Register 13") }, + { HRDATAD (R14, R[14], 32, "General Purpose Register 14") }, + { HRDATAD (AP, R[nAP], 32, "Alias for R12") }, + { HRDATAD (FP, R[nFP], 32, "Alias for R13") }, + { HRDATAD (SP, R[nSP], 32, "Alias for R14") }, + { HRDATAD (PSL, PSL, 32, "processor status longword") }, + { HRDATAD (CC, PSL, 4, "condition codes, PSL<3:0>") }, + { HRDATAD (KSP, KSP, 32, "kernel stack pointer") }, + { HRDATAD (ESP, ESP, 32, "executive stack pointer") }, + { HRDATAD (SSP, SSP, 32, "supervisor stack pointer") }, + { HRDATAD (USP, USP, 32, "user stack pointer") }, + { HRDATAD (IS, IS, 32, "interrupt stack pointer") }, + { HRDATAD (SCBB, SCBB, 32, "system control block base") }, + { HRDATAD (PCBB, PCBB, 32, "process control block base") }, + { HRDATAD (P0BR, P0BR, 32, "P0 base register") }, + { HRDATAD (P0LR, P0LR, 22, "P0 length register") }, + { HRDATAD (P1BR, P1BR, 32, "P1 base register") }, + { HRDATAD (P1LR, P1LR, 22, "P1 length register") }, + { HRDATAD (SBR, SBR, 32, "system base register") }, + { HRDATAD (SLR, SLR, 22, "system length register") }, + { HRDATAD (SISR, SISR, 16, "software interrupt summary register") }, + { HRDATAD (ASTLVL, ASTLVL, 4, "AST level register") }, + { FLDATAD (MAPEN, mapen, 0, "memory management enable") }, + { FLDATAD (PME, pme, 0, "performance monitor enable") }, + { HRDATAD (TRPIRQ, trpirq, 8, "trap/interrupt pending") }, + { FLDATAD (CRDERR, crd_err, 0, "correctible read data error flag") }, + { FLDATAD (MEMERR, mem_err, 0, "memory error flag") }, + { FLDATA (HLTPIN, hlt_pin, 0) }, { HRDATA (IDLE_MASK, cpu_idle_mask, 16), REG_HIDDEN }, { DRDATA (IDLE_INDX, cpu_idle_type, 4), REG_HRO }, { DRDATA (IDLE_ENAB, sim_idle_enab, 4), REG_HRO }, - { BRDATA (PCQ, pcq, 16, 32, PCQ_SIZE), REG_RO+REG_CIRC }, + { BRDATAD (PCQ, pcq, 16, 32, PCQ_SIZE, "PC prior to last PC change or interrupt;"), REG_RO+REG_CIRC }, { HRDATA (PCQP, pcq_p, 6), REG_HRO }, { HRDATA (BADABO, badabo, 32), REG_HRO }, - { HRDATA (WRU, sim_int_char, 8) }, + { HRDATAD (WRU, sim_int_char, 8, "interrupt character") }, + { HRDATA (MODEL, sys_model, 32), REG_HRO }, { NULL } }; MTAB cpu_mod[] = { { UNIT_CONH, 0, "HALT to SIMH", "SIMHALT", NULL }, { UNIT_CONH, UNIT_CONH, "HALT to console", "CONHALT", NULL }, - { MTAB_XTD|MTAB_VDV, 0, "IDLE", "IDLE", &cpu_set_idle, &cpu_show_idle }, + { MTAB_XTD|MTAB_VDV, 0, "IDLE", "IDLE={VMS|ULTRIX|NETBSD|OPENBSD|ULTRIXOLD|OPENBSDOLD|QUASIJARUS|32V|ALL}", &cpu_set_idle, &cpu_show_idle }, { MTAB_XTD|MTAB_VDV, 0, NULL, "NOIDLE", &sim_clr_idle, NULL }, - { UNIT_MSIZE, (1u << 23), NULL, "8M", &cpu_set_size }, - { UNIT_MSIZE, (1u << 24), NULL, "16M", &cpu_set_size }, - { UNIT_MSIZE, (1u << 25), NULL, "32M", &cpu_set_size }, - { UNIT_MSIZE, (1u << 25) + (1u << 24), NULL, "48M", &cpu_set_size }, - { UNIT_MSIZE, (1u << 26), NULL, "64M", &cpu_set_size }, - { UNIT_MSIZE, (1u << 27), NULL, "128M", &cpu_set_size }, -#if !defined (VAX_780) - { UNIT_MSIZE, (1u << 28), NULL, "256M", &cpu_set_size }, - { UNIT_MSIZE, (1u << 29), NULL, "512M", &cpu_set_size }, -#endif + MEM_MODIFIERS, /* Model specific memory modifiers from vaxXXX_defs.h */ { MTAB_XTD|MTAB_VDV|MTAB_NMO|MTAB_SHP, 0, "HISTORY", "HISTORY", &cpu_set_hist, &cpu_show_hist }, { MTAB_XTD|MTAB_VDV|MTAB_NMO|MTAB_SHP, 0, "VIRTUAL", NULL, NULL, &cpu_show_virt }, + CPU_MODEL_MODIFIERS /* Model specific cpu modifiers from vaxXXX_defs.h */ { 0 } }; DEBTAB cpu_deb[] = { - { "INTEXC", LOG_CPU_I }, - { "REI", LOG_CPU_R }, - { "CONTEXT", LOG_CPU_P }, - { "EVENT", SIM_DBG_EVENT }, - { "ACTIVATE", SIM_DBG_ACTIVATE }, + { "INTEXC", LOG_CPU_I }, + { "REI", LOG_CPU_R }, + { "CONTEXT", LOG_CPU_P }, + { "EVENT", SIM_DBG_EVENT }, + { "ACTIVATE", SIM_DBG_ACTIVATE }, + { "ASYNCH", SIM_DBG_AIO_QUEUE }, { NULL, 0 } }; @@ -502,9 +491,15 @@ DEVICE cpu_dev = { &cpu_ex, &cpu_dep, &cpu_reset, &cpu_boot, NULL, NULL, NULL, DEV_DYNM | DEV_DEBUG, 0, - cpu_deb, &cpu_set_size, NULL + cpu_deb, &cpu_set_size, NULL, &cpu_help, NULL, NULL }; +t_stat cpu_show_model (FILE *st, UNIT *uptr, int32 val, void *desc) +{ +fprintf (st, "model="); +return cpu_print_model (st); +} + t_stat sim_instr (void) { volatile int32 opc, cc; /* used by setjmp */ @@ -593,8 +588,11 @@ else if (abortval < 0) { /* mm or rsrv or int */ break; case SCB_MCHK: /* machine check */ +/* The ka630 and ka620 CPU ROMs use double machine checks to size memory */ +#if !defined(VAX_620) && !defined(VAX_630) if (in_ie) /* in exc? panic */ ABORT (STOP_INIE); +#endif cc = machine_check (p1, opc, cc, delta); /* system specific */ in_ie = 0; GET_CUR; /* PSL changed */ @@ -1948,7 +1946,8 @@ for ( ;; ) { temp = CC_V; SET_TRAP (TRAP_DIVZRO); } - else if ((op0 == LMASK) && (op1 == LSIGN)) { /* overflow? */ + else if ((((uint32)op0) == LMASK) && + (((uint32)op1) == LSIGN)) { /* overflow? */ r = op1; temp = CC_V; INTOV; @@ -2187,6 +2186,7 @@ for ( ;; ) { BRANCHB (brdisp); if (((PSL & PSL_IS) != 0) && /* on IS? */ (PSL_GETIPL (PSL) == 0x1F) && /* at IPL 31 */ + (mapen == 0) && /* Running from ROM */ (fault_PC == 0x2004361B)) /* Boot ROM Character Prompt */ cpu_idle(); } @@ -3146,8 +3146,8 @@ PSL = PSL_IS | PSL_IPL1F; SISR = 0; ASTLVL = 4; mapen = 0; -FLUSH_ISTR; /* init I-stream */ -if (M == NULL) { /* first time init? */ +FLUSH_ISTR; /* init I-stream */ +if (M == NULL) { /* first time init? */ sim_brk_types = sim_brk_dflt = SWMASK ('E'); pcq_r = find_reg ("PCQ", NULL, dptr); if (pcq_r == NULL) @@ -3156,6 +3156,7 @@ if (M == NULL) { /* first time init? */ M = (uint32 *) calloc (((uint32) MEMSIZE) >> 2, sizeof (uint32)); if (M == NULL) return SCPE_MEM; + auto_config(NULL, 0); /* do an initial auto configure */ } return build_dib_tab (); } @@ -3211,7 +3212,7 @@ return SCPE_NXM; t_stat cpu_set_size (UNIT *uptr, int32 val, char *cptr, void *desc) { int32 mc = 0; -uint32 i, clim; +uint32 i, clim, uval = (uint32)val; uint32 *nM = NULL; if ((val <= 0) || (val > MAXMEMSIZE_X)) @@ -3220,15 +3221,15 @@ for (i = val; i < MEMSIZE; i = i + 4) mc = mc | M[i >> 2]; if ((mc != 0) && !get_yn ("Really truncate memory [N]?", FALSE)) return SCPE_OK; -nM = (uint32 *) calloc (val >> 2, sizeof (uint32)); +nM = (uint32 *) calloc (uval >> 2, sizeof (uint32)); if (nM == NULL) return SCPE_MEM; -clim = (uint32) ((((uint32) val) < MEMSIZE)? val: MEMSIZE); +clim = (uint32)((uval < MEMSIZE)? uval: MEMSIZE); for (i = 0; i < clim; i = i + 4) nM[i >> 2] = M[i >> 2]; free (M); M = nM; -MEMSIZE = val; +MEMSIZE = uval; return SCPE_OK; } @@ -3325,8 +3326,6 @@ t_stat r; InstHistory *h; extern const char *opcode[]; extern t_value *sim_eval; -extern t_stat fprint_sym (FILE *ofile, t_addr addr, t_value *val, - UNIT *uptr, int32 sw); if (hst_lnt == 0) /* enabled? */ return SCPE_NOFNC; @@ -3463,3 +3462,105 @@ if (sim_idle_enab && (cpu_idle_type != 0)) sim_show_idle (st, uptr, val, desc); return SCPE_OK; } + + +t_stat cpu_load_bootcode (const char *filename, const unsigned char *builtin_code, size_t size, t_bool rom, t_addr offset) +{ +char args[CBUFSIZE]; +t_stat r; + +printf ("Loading boot code from %s\n", filename); +if (sim_log) + fprintf (sim_log, "Loading boot code from %s\n", filename); +if (rom) + sprintf (args, "-R %s", filename); +else + sprintf (args, "-O %s %X", filename, (int)offset); +r = load_cmd (0, args); +if (r != SCPE_OK) { + if (builtin_code) { + FILE *f; + + if ((f = sim_fopen (filename, "wb"))) { + printf ("Saving boot code to %s\n", filename); + if (sim_log) + fprintf (sim_log, "Saving boot code to %s\n", filename); + sim_fwrite ((void *)builtin_code, 1, size, f); + fclose (f); + printf ("Loading boot code from %s\n", filename); + if (sim_log) + fprintf (sim_log, "Loading boot code from %s\n", filename); + r = load_cmd (0, args); + } + } + return r; + } +return SCPE_OK; +} + +t_stat cpu_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr) +{ +fprintf (st, "The ");cpu_print_model (st);fprintf (st, " CPU help\n\n"); +fprintf (st, "CPU options include the size of main memory.\n\n"); +if (dptr->modifiers) { + MTAB *mptr; + extern t_stat cpu_set_size (UNIT *uptr, int32 val, char *cptr, void *desc); + + for (mptr = dptr->modifiers; mptr->mask != 0; mptr++) + if (mptr->valid == &cpu_set_size) + fprintf (st, " sim> SET CPU %4s set memory size = %sB\n", mptr->mstring, mptr->mstring); + fprintf (st, "\n"); + } +cpu_model_help (st, dptr, uptr, flag, cptr); +fprintf (st, "CPU options include the treatment of the HALT instruction.\n\n"); +fprintf (st, " sim> SET CPU SIMHALT kernel HALT returns to simulator\n"); +fprintf (st, " sim> SET CPU CONHALT kernel HALT returns to boot ROM console\n\n"); +fprintf (st, "The CPU also implements a command to display a virtual to physical address\n"); +fprintf (st, "translation:\n\n"); +fprintf (st, " sim> SHOW {-kesu} CPU VIRTUAL=n show translation for address n\n"); +fprintf (st, " in kernel/exec/supervisor/user mode\n\n"); +fprintf (st, "Memory can be loaded with a binary byte stream using the LOAD command. The\n"); +fprintf (st, "LOAD command recognizes three switches:\n\n"); +fprintf (st, " -o origin argument follows file name\n"); +fprintf (st, " -r load the boot ROM\n"); +fprintf (st, " -n load the non-volatile RAM\n\n"); +fprintf (st, "The CPU supports the BOOT command and is the only VAX device to do so. Note\n"); +fprintf (st, "that the behavior of the bootstrap depends on the capabilities of the console\n"); +fprintf (st, "terminal emulator. If the terminal window supports full VT100 emulation\n"); +fprintf (st, "(including Multilanguage Character Set support), the bootstrap will ask the\n"); +fprintf (st, "user to specify the language; otherwise, it will default to English.\n\n"); +fprintf (st, "These switches are recognized when examining or depositing in CPU memory:\n\n"); +fprintf (st, " -b examine/deposit bytes\n"); +fprintf (st, " -w examine/deposit words\n"); +fprintf (st, " -l examine/deposit longwords\n"); +fprintf (st, " -d data radix is decimal\n"); +fprintf (st, " -o data radix is octal\n"); +fprintf (st, " -h data radix is hexadecimal\n"); +fprintf (st, " -m examine (only) VAX instructions\n"); +fprintf (st, " -p examine/deposit PDP-11 (compatibility mode) instructions\n"); +fprintf (st, " -r examine (only) RADIX50 encoded data\n"); +fprintf (st, " -v interpret address as virtual, current mode\n"); +fprintf (st, " -k interpret address as virtual, kernel mode\n"); +fprintf (st, " -e interpret address as virtual, executive mode\n"); +fprintf (st, " -s interpret address as virtual, supervisor mode\n"); +fprintf (st, " -u interpret address as virtual, user mode\n\n"); +fprintf (st, "The CPU attempts to detect when the simulator is idle. When idle, the\n"); +fprintf (st, "simulator does not use any resources on the host system. Idle detection is\n"); +fprintf (st, "controlled by the SET IDLE and SET NOIDLE commands:\n\n"); +fprintf (st, " sim> SET CPU IDLE{=VMS|ULTRIX|NETBSD|FREEBSD|32V|ALL}\n"); +fprintf (st, " enable idle detection\n"); +fprintf (st, " sim> SET CPU NOIDLE disable idle detection\n\n"); +fprintf (st, "Idle detection is disabled by default. Unless ALL is specified, idle\n"); +fprintf (st, "detection is operating system specific. If idle detection is enabled with\n"); +fprintf (st, "an incorrect operating system setting, simulator performance could be\n"); +fprintf (st, "impacted. The default operating system setting is VMS.\n\n"); +fprintf (st, "The CPU can maintain a history of the most recently executed instructions.\n"); +fprintf (st, "This is controlled by the SET CPU HISTORY and SHOW CPU HISTORY commands:\n\n"); +fprintf (st, " sim> SET CPU HISTORY clear history buffer\n"); +fprintf (st, " sim> SET CPU HISTORY=0 disable history\n"); +fprintf (st, " sim> SET CPU HISTORY=n enable history, length = n\n"); +fprintf (st, " sim> SHOW CPU HISTORY print CPU history\n"); +fprintf (st, " sim> SHOW CPU HISTORY=n print first n entries of CPU history\n\n"); +fprintf (st, "The maximum length for the history is 65536 entries.\n\n"); +return SCPE_OK; +} diff --git a/VAX/vax_cpu1.c b/VAX/vax_cpu1.c index d4e3ea32..f530c4c9 100644 --- a/VAX/vax_cpu1.c +++ b/VAX/vax_cpu1.c @@ -99,9 +99,7 @@ extern int32 fault_PC; extern int32 pcq[PCQ_SIZE]; extern int32 pcq_p; extern int32 in_ie; -extern int32 sim_interval; extern int32 ibcnt, ppc; -extern FILE *sim_deb; extern DEVICE cpu_dev; extern int32 Test (uint32 va, int32 acc, int32 *status); @@ -1445,7 +1443,7 @@ int32 cc; if (PSL & PSL_CUR) /* must be kernel */ RSVD_INST_FAULT; -if (prn > 63) /* reg# > 63? fault */ +if (prn > MT_MAX) /* reg# > max? fault */ RSVD_OPND_FAULT; CC_IIZZ_L (val); /* set cc's */ switch (prn) { /* case on reg # */ @@ -1576,7 +1574,7 @@ int32 val; if (PSL & PSL_CUR) /* must be kernel */ RSVD_INST_FAULT; -if (prn > 63) /* reg# > 63? fault */ +if (prn > MT_MAX) /* reg# > max? fault */ RSVD_OPND_FAULT; switch (prn) { /* case on reg# */ diff --git a/VAX/vax_defs.h b/VAX/vax_defs.h index 27f05cb7..803d847c 100644 --- a/VAX/vax_defs.h +++ b/VAX/vax_defs.h @@ -730,8 +730,33 @@ void cpu_idle (void); #if defined (VAX_780) #include "vax780_defs.h" -#else +#elif defined (VAX_750) +#include "vax750_defs.h" +#elif defined (VAX_730) +#include "vax730_defs.h" +#elif defined (VAX_610) +#include "vax610_defs.h" +#elif defined (VAX_620) || defined (VAX_630) +#include "vax630_defs.h" +#elif defined (VAX_860) +#include "vax860_defs.h" +#else /* VAX 3900 */ #include "vaxmod_defs.h" #endif +#ifndef CPU_MODEL_MODIFIERS +#define CPU_MODEL_MODIFIERS /* No model specific CPU modifiers */ +#endif + +#ifdef DONT_USE_INTERNAL_ROM +#define BOOT_CODE_ARRAY NULL +#define BOOT_CODE_SIZE 0 +#endif + +extern t_stat cpu_load_bootcode (const char *filename, const unsigned char *builtin_code, size_t size, t_bool rom, t_addr offset); +extern t_stat cpu_print_model (FILE *st); +extern t_stat cpu_show_model (FILE *st, UNIT *uptr, int32 val, void *desc); +extern t_stat cpu_set_model (UNIT *uptr, int32 val, char *cptr, void *desc); +extern t_stat cpu_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr); +extern t_stat cpu_model_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr); #endif /* _VAX_DEFS_H */ diff --git a/VAX/vax_io.c b/VAX/vax_io.c index 95b46073..a2e873dc 100644 --- a/VAX/vax_io.c +++ b/VAX/vax_io.c @@ -117,9 +117,6 @@ extern int32 PSL, SISR, trpirq, mem_err, crd_err, hlt_pin; extern int32 p1; extern int32 ssc_bto; extern jmp_buf save_env; -extern int32 sim_switches; -extern DEVICE *sim_devices[]; -extern FILE *sim_log; t_stat dbl_rd (int32 *data, int32 addr, int32 access); t_stat dbl_wr (int32 data, int32 addr, int32 access); @@ -143,21 +140,23 @@ t_stat qba_show_virt (FILE *of, UNIT *uptr, int32 val, void *desc); qba_reg QBA register list */ -DIB qba_dib = { IOBA_DBL, IOLN_DBL, &dbl_rd, &dbl_wr, 0 }; +#define IOLN_DBL 002 + +DIB qba_dib = { IOBA_AUTO, IOLN_DBL, &dbl_rd, &dbl_wr, 0 }; UNIT qba_unit = { UDATA (NULL, 0, 0) }; REG qba_reg[] = { - { HRDATA (SCR, cq_scr, 16) }, - { HRDATA (DSER, cq_dser, 8) }, - { HRDATA (MEAR, cq_mear, 13) }, - { HRDATA (SEAR, cq_sear, 20) }, - { HRDATA (MBR, cq_mbr, 29) }, - { HRDATA (IPC, cq_ipc, 16) }, - { HRDATA (IPL17, int_req[3], 32), REG_RO }, - { HRDATA (IPL16, int_req[2], 32), REG_RO }, - { HRDATA (IPL15, int_req[1], 32), REG_RO }, - { HRDATA (IPL14, int_req[0], 32), REG_RO }, + { HRDATAD (SCR, cq_scr, 16, "system configuration register") }, + { HRDATAD (DSER, cq_dser, 8, "DMA system error register") }, + { HRDATAD (MEAR, cq_mear, 13, "master error address register") }, + { HRDATAD (SEAR, cq_sear, 20, "slave error address register") }, + { HRDATAD (MBR, cq_mbr, 29, "Qbus map base register") }, + { HRDATAD (IPC, cq_ipc, 16, "interprocessor communications register") }, + { HRDATAD (IPL17, int_req[3], 32, "IPL 17 interrupt flags"), REG_RO }, + { HRDATAD (IPL16, int_req[2], 32, "IPL 16 interrupt flags"), REG_RO }, + { HRDATAD (IPL15, int_req[1], 32, "IPL 15 interrupt flags"), REG_RO }, + { HRDATAD (IPL14, int_req[0], 32, "IPL 14 interrupt flags"), REG_RO }, { FLDATA (AUTOCON, autcon_enb, 0), REG_HRO }, { NULL } }; diff --git a/VAX/vax_ka610_bin.h b/VAX/vax_ka610_bin.h new file mode 100644 index 00000000..08202162 --- /dev/null +++ b/VAX/vax_ka610_bin.h @@ -0,0 +1,1037 @@ +#ifndef ROM_vax_ka610_bin_H +#define ROM_vax_ka610_bin_H 0 +/* + VAX/vax_ka610_bin.h produced at Fri Nov 9 06:17:59 2012 + from VAX/ka610.bin which was last modified at Mon Nov 5 14:36:18 2012 + file size: 16384 (0x4000) - checksum: 0xFFEF3312 + This file is a generated file and should NOT be edited or changed by hand. +*/ +#define BOOT_CODE_SIZE 0x4000 +#define BOOT_CODE_FILENAME "ka610.bin" +#define BOOT_CODE_ARRAY vax_ka610_bin +unsigned char vax_ka610_bin[] = { +0x31,0x26,0x01,0x06,0x80,0x81,0x82,0x83,0x13,0x5B,0x53,0x59,0x53,0x45,0x58,0x45, +0x5D,0x53,0x59,0x53,0x42,0x4F,0x4F,0x54,0x2E,0x45,0x58,0x45,0x20,0x20,0x20,0x20, +0x20,0x1B,0x5B,0x53,0x59,0x53,0x30,0x2E,0x53,0x59,0x53,0x4D,0x41,0x49,0x4E,0x54, +0x5D,0x44,0x49,0x41,0x47,0x42,0x4F,0x4F,0x54,0x2E,0x45,0x58,0x45,0x0D,0x0A,0x42, +0x6F,0x6F,0x74,0x66,0x69,0x6C,0x65,0x3A,0x00,0x44,0x55,0x41,0x00,0x03,0x11,0x68, +0x14,0x00,0x20,0x1D,0x04,0x00,0x00,0x50,0x52,0x41,0x00,0x00,0x08,0x00,0x00,0x00, +0x20,0xA8,0x03,0x00,0x00,0x58,0x51,0x41,0x00,0x00,0x60,0x20,0x19,0x00,0x20,0xD4, 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+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x7E,0x41,}; +#endif /* ROM_vax_ka610_bin_H */ diff --git a/VAX/vax_ka620_bin.h b/VAX/vax_ka620_bin.h new file mode 100644 index 00000000..04ef26ef --- /dev/null +++ b/VAX/vax_ka620_bin.h @@ -0,0 +1,4109 @@ +#ifndef ROM_vax_ka620_bin_H +#define ROM_vax_ka620_bin_H 0 +/* + VAX/vax_ka620_bin.h produced at Fri Nov 9 06:17:59 2012 + from VAX/ka620.bin which was last modified at Thu Nov 8 17:23:00 2012 + file size: 65536 (0x10000) - checksum: 0xFF7F930F + This file is a generated file and should NOT be edited or changed by hand. +*/ +#define BOOT_CODE_SIZE 0x10000 +#define BOOT_CODE_FILENAME "ka620.bin" +#define BOOT_CODE_ARRAY vax_ka620_bin +unsigned char vax_ka620_bin[] = { +0x11,0x4E,0x00,0x00,0x00,0x00,0x01,0x01,0x11,0x30,0x00,0x00,0x11,0x32,0x00,0x00, +0x11,0x34,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x34,0x0B,0x00,0x00,0x7C,0x5F,0x04,0x20, +0x24,0x13,0x00,0x00,0xE0,0x5C,0x04,0x20,0x11,0x13,0x9F,0xCF,0x54,0x0B,0x11,0x0A, +0x9F,0xCF,0x8F,0x0A,0x11,0x04,0x9F,0xCF,0x95,0x0C,0x31,0x9A,0x03,0x31,0xE0,0x09, +0x91,0xDF,0x7B,0x07,0x0F,0x12,0x61,0x90,0x0E,0xDF,0x73,0x07,0xB5,0xDF,0x6F,0x07, +0x18,0xFA,0x90,0x0D,0xDF,0x68,0x07,0xD4,0x51,0x9E,0xAF,0x94,0x50,0x9E,0xEF,0x15, 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+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,}; +#endif /* ROM_vax_ka620_bin_H */ diff --git a/VAX/vax_ka630_bin.h b/VAX/vax_ka630_bin.h new file mode 100644 index 00000000..1e81f587 --- /dev/null +++ b/VAX/vax_ka630_bin.h @@ -0,0 +1,4109 @@ +#ifndef ROM_vax_ka630_bin_H +#define ROM_vax_ka630_bin_H 0 +/* + VAX/vax_ka630_bin.h produced at Fri Nov 9 06:17:59 2012 + from VAX/ka630.bin which was last modified at Fri Nov 9 06:14:43 2012 + file size: 65536 (0x10000) - checksum: 0xFF7F73EF + This file is a generated file and should NOT be edited or changed by hand. +*/ +#define BOOT_CODE_SIZE 0x10000 +#define BOOT_CODE_FILENAME "ka630.bin" +#define BOOT_CODE_ARRAY vax_ka630_bin +unsigned char vax_ka630_bin[] = { +0x11,0x4E,0x00,0x00,0x00,0x00,0x01,0x01,0x11,0x30,0x00,0x00,0x11,0x32,0x00,0x00, +0x11,0x34,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x34,0x0B,0x00,0x00,0x7C,0x5F,0x04,0x20, +0x24,0x13,0x00,0x00,0xE0,0x5C,0x04,0x20,0x11,0x13,0x9F,0xCF,0x54,0x0B,0x11,0x0A, +0x9F,0xCF,0x8F,0x0A,0x11,0x04,0x9F,0xCF,0x95,0x0C,0x31,0x9A,0x03,0x31,0xE0,0x09, +0x91,0xDF,0x7B,0x07,0x0F,0x12,0x61,0x90,0x0E,0xDF,0x73,0x07,0xB5,0xDF,0x6F,0x07, +0x18,0xFA,0x90,0x0D,0xDF,0x68,0x07,0xD4,0x51,0x9E,0xAF,0x94,0x50,0x9E,0xEF,0x15, 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+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,}; +#endif /* ROM_vax_ka630_bin_H */ diff --git a/VAX/vax_ka655x_bin.h b/VAX/vax_ka655x_bin.h index 6cc64347..72f8efaa 100644 --- a/VAX/vax_ka655x_bin.h +++ b/VAX/vax_ka655x_bin.h @@ -1,8201 +1,8205 @@ -#ifndef ROM_vax_ka655x_bin_H -#define ROM_vax_ka655x_bin_H 0 -/* - VAX/vax_ka655x_bin.h produced at Sun Feb 26 12:32:44 2012 - from VAX/ka655x.bin which was last modified at Sat Feb 18 00:01:12 2012 - file size: 131072 (0x20000) - checksum: 0xFF7673B6 -*/ -unsigned char vax_ka655x_bin[] = { -0x11,0x22,0x11,0xFE,0x02,0x03,0x53,0x01,0x31,0x89,0x03,0x00,0x31,0x8B,0x03,0x00, -0x31,0xB5,0x03,0x5A,0xA5,0x00,0x00,0x00,0xF4,0x03,0x04,0x20,0x26,0x04,0x14,0x20, -0x00,0x00,0x04,0x20,0xD0,0x8F,0x00,0x00,0x14,0x20,0x9F,0x00,0x00,0x14,0x20,0xD2, -0x9F,0x30,0x00,0x14,0x20,0x9F,0x02,0x05,0x14,0x20,0xD2,0x0E,0x9F,0x30,0x00,0x14, -0x20,0x7D,0x50,0x9F,0xB2,0x04,0x14,0x20,0xD0,0x8F,0xB2,0x04,0x14,0x20,0x51,0xDB, -0x2A,0xA1,0x44,0xDB,0x2B,0xA1,0x48,0xCA,0x8F,0x80,0x00,0x00,0x00,0x9F,0x00,0x00, -0x08,0x20,0xDB,0x2B,0x50,0xED,0x08,0x06,0x50,0x02,0x13,0x03,0x31,0x0C,0x01,0xED, -0x18,0x03,0x9F,0x00,0x04,0x14,0x20,0x01,0x13,0x03,0x31,0x86,0x00,0xDB,0x21,0x50, -0x8F,0x9F,0x05,0x00,0x04,0x20,0x01,0x02,0x10,0x00,0x07,0x00,0x19,0x00,0x00,0xD0, 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+/* + VAX/vax_ka655x_bin.h produced at Fri Nov 9 06:17:59 2012 + from VAX/ka655x.bin which was last modified at Sun Oct 21 18:12:55 2012 + file size: 131072 (0x20000) - checksum: 0xFF7673B6 + This file is a generated file and should NOT be edited or changed by hand. +*/ +#define BOOT_CODE_SIZE 0x20000 +#define BOOT_CODE_FILENAME "ka655x.bin" +#define BOOT_CODE_ARRAY vax_ka655x_bin +unsigned char vax_ka655x_bin[] = { +0x11,0x22,0x11,0xFE,0x02,0x03,0x53,0x01,0x31,0x89,0x03,0x00,0x31,0x8B,0x03,0x00, +0x31,0xB5,0x03,0x5A,0xA5,0x00,0x00,0x00,0xF4,0x03,0x04,0x20,0x26,0x04,0x14,0x20, +0x00,0x00,0x04,0x20,0xD0,0x8F,0x00,0x00,0x14,0x20,0x9F,0x00,0x00,0x14,0x20,0xD2, +0x9F,0x30,0x00,0x14,0x20,0x9F,0x02,0x05,0x14,0x20,0xD2,0x0E,0x9F,0x30,0x00,0x14, +0x20,0x7D,0x50,0x9F,0xB2,0x04,0x14,0x20,0xD0,0x8F,0xB2,0x04,0x14,0x20,0x51,0xDB, +0x2A,0xA1,0x44,0xDB,0x2B,0xA1,0x48,0xCA,0x8F,0x80,0x00,0x00,0x00,0x9F,0x00,0x00, +0x08,0x20,0xDB,0x2B,0x50,0xED,0x08,0x06,0x50,0x02,0x13,0x03,0x31,0x0C,0x01,0xED, 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+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,}; +#endif /* ROM_vax_ka655x_bin_H */ diff --git a/VAX/vax_mmu.c b/VAX/vax_mmu.c index 79175c41..1629368f 100644 --- a/VAX/vax_mmu.c +++ b/VAX/vax_mmu.c @@ -23,6 +23,7 @@ used in advertising or otherwise to promote the sale, use or other dealings in this Software without prior written authorization from Robert M Supnik. + 24-Oct-12 MB Added support for KA620 virtual addressing 21-Jul-08 RMS Removed inlining support 28-May-08 RMS Inlined physical memory routines 29-Apr-07 RMS Added address masking for system page table reads @@ -177,7 +178,10 @@ if (mapen) { /* mapping on? */ xpte = fill (va, lnt, acc, NULL); /* fill if needed */ pa = (xpte.pte & TLB_PFN) | off; /* get phys addr */ } -else pa = va & PAMASK; +else { + pa = va & PAMASK; + off = 0; + } if ((pa & (lnt - 1)) == 0) { /* aligned? */ if (lnt >= L_LONG) /* long, quad? */ return ReadL (pa); @@ -185,7 +189,7 @@ if ((pa & (lnt - 1)) == 0) { /* aligned? */ return ReadW (pa); return ReadB (pa); /* byte */ } -if (mapen && ((off + lnt) > VA_PAGSIZE)) { /* cross page? */ +if (mapen && ((uint32)(off + lnt) > VA_PAGSIZE)) { /* cross page? */ vpn = VA_GETVPN (va + lnt); /* vpn 2nd page */ tbi = VA_GETTBI (vpn); xpte = (va & VA_S0)? stlb[tbi]: ptlb[tbi]; /* access tlb */ @@ -239,7 +243,10 @@ if (mapen) { xpte = fill (va, lnt, acc, NULL); pa = (xpte.pte & TLB_PFN) | off; } -else pa = va & PAMASK; +else { + pa = va & PAMASK; + off = 0; + } if ((pa & (lnt - 1)) == 0) { /* aligned? */ if (lnt >= L_LONG) /* long, quad? */ WriteL (pa, val); @@ -248,7 +255,7 @@ if ((pa & (lnt - 1)) == 0) { /* aligned? */ else WriteB (pa, val); /* byte */ return; } -if (mapen && ((off + lnt) > VA_PAGSIZE)) { +if (mapen && ((uint32)(off + lnt) > VA_PAGSIZE)) { vpn = VA_GETVPN (va + 4); tbi = VA_GETTBI (vpn); xpte = (va & VA_S0)? stlb[tbi]: ptlb[tbi]; /* access tlb */ @@ -474,6 +481,7 @@ else { MM_ERR (PR_LNV); ptead = d_p0br + ptidx; } +#if !defined (VAX_620) if ((ptead & VA_S0) == 0) ABORT (STOP_PPTE); /* ppte must be sys */ vpn = VA_GETVPN (ptead); /* get vpn, tbi */ @@ -494,6 +502,7 @@ else { ((pte << VA_N_OFF) & TLB_PFN); /* set stlb data */ } ptead = (stlb[tbi].pte & TLB_PFN) | VA_GETOFF (ptead); +#endif } pte = ReadL (ptead); /* read pte */ tlbpte = cvtacc[PTE_GETACC (pte)] | /* cvt access */ diff --git a/VAX/vax_stddev.c b/VAX/vax_stddev.c index 0ad9a32c..0a5e95d4 100644 --- a/VAX/vax_stddev.c +++ b/VAX/vax_stddev.c @@ -77,6 +77,7 @@ */ #include "vax_defs.h" +#include "sim_tmxr.h" #include #define TTICSR_IMP (CSR_DONE + CSR_IE) /* terminal input */ @@ -94,7 +95,6 @@ extern int32 int_req[IPL_HLVL]; extern int32 hlt_pin; -extern int32 sim_switches, sim_is_running; int32 tti_csr = 0; /* control/status */ int32 tto_csr = 0; /* control/status */ @@ -135,13 +135,14 @@ DIB tti_dib = { 0, 0, NULL, NULL, 1, IVCL (TTI), SCB_TTI, { NULL } }; UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), 0 }; REG tti_reg[] = { - { HRDATA (BUF, tti_unit.buf, 16) }, - { HRDATA (CSR, tti_csr, 16) }, - { FLDATA (INT, int_req[IPL_TTI], INT_V_TTI) }, - { FLDATA (DONE, tti_csr, CSR_V_DONE) }, - { FLDATA (IE, tti_csr, CSR_V_IE) }, - { DRDATA (POS, tti_unit.pos, T_ADDR_W), PV_LEFT }, - { DRDATA (TIME, tti_unit.wait, 24), PV_LEFT }, + { HRDATAD (BUF, tti_unit.buf, 16, "last data item processed") }, + { HRDATAD (CSR, tti_csr, 16, "control/status register") }, + { FLDATAD (INT, int_req[IPL_TTI], INT_V_TTI, "interrupt pending flag") }, + { FLDATAD (ERR, tti_csr, CSR_V_ERR, "error flag (CSR<15>)") }, + { FLDATAD (DONE, tti_csr, CSR_V_DONE, "device done flag (CSR<7>)") }, + { FLDATAD (IE, tti_csr, CSR_V_IE, "interrupt enable flag (CSR<6>)") }, + { DRDATAD (POS, tti_unit.pos, T_ADDR_W, "number of characters input"), PV_LEFT }, + { DRDATAD (TIME, tti_unit.wait, 24, "input polling interval"), PV_LEFT }, { NULL } }; @@ -173,13 +174,14 @@ DIB tto_dib = { 0, 0, NULL, NULL, 1, IVCL (TTO), SCB_TTO, { NULL } }; UNIT tto_unit = { UDATA (&tto_svc, TT_MODE_8B, 0), SERIAL_OUT_WAIT }; REG tto_reg[] = { - { HRDATA (BUF, tto_unit.buf, 8) }, - { HRDATA (CSR, tto_csr, 16) }, - { FLDATA (INT, int_req[IPL_TTO], INT_V_TTO) }, - { FLDATA (DONE, tto_csr, CSR_V_DONE) }, - { FLDATA (IE, tto_csr, CSR_V_IE) }, - { DRDATA (POS, tto_unit.pos, T_ADDR_W), PV_LEFT }, - { DRDATA (TIME, tto_unit.wait, 24), PV_LEFT }, + { HRDATAD (BUF, tto_unit.buf, 8, "last data item processed") }, + { HRDATAD (CSR, tto_csr, 16, "control/status register") }, + { FLDATAD (INT, int_req[IPL_TTO], INT_V_TTO, "interrupt pending flag") }, + { FLDATAD (ERR, tto_csr, CSR_V_ERR, "error flag (CSR<15>)") }, + { FLDATAD (DONE, tto_csr, CSR_V_DONE, "device done flag (CSR<7>)") }, + { FLDATAD (IE, tto_csr, CSR_V_IE, "interrupt enable flag (CSR<6>)") }, + { DRDATAD (POS, tto_unit.pos, T_ADDR_W, "number of characters input"), PV_LEFT }, + { DRDATAD (TIME, tto_unit.wait, 24, "time from I/O initiation to interrupt"), PV_LEFT }, { NULL } }; @@ -211,18 +213,18 @@ DIB clk_dib = { 0, 0, NULL, NULL, 1, IVCL (CLK), SCB_INTTIM, { NULL } }; UNIT clk_unit = { UDATA (&clk_svc, UNIT_IDLE+UNIT_FIX, sizeof(TOY)), CLK_DELAY };/* 100Hz */ REG clk_reg[] = { - { HRDATA (CSR, clk_csr, 16) }, - { FLDATA (INT, int_req[IPL_CLK], INT_V_CLK) }, - { FLDATA (IE, clk_csr, CSR_V_IE) }, - { DRDATA (TODR, todr_reg, 32), PV_LEFT }, - { FLDATA (BLOW, todr_blow, 0) }, - { DRDATA (TIME, clk_unit.wait, 24), REG_NZ + PV_LEFT }, - { DRDATA (POLL, tmr_poll, 24), REG_NZ + PV_LEFT + REG_HRO }, - { DRDATA (TPS, clk_tps, 8), REG_NZ + PV_LEFT }, + { HRDATAD (CSR, clk_csr, 16, "control/status register") }, + { FLDATAD (INT, int_req[IPL_CLK], INT_V_CLK, "interrupt pending flag") }, + { FLDATAD (IE, clk_csr, CSR_V_IE, "interrupt enable flag (CSR<6>)") }, + { DRDATAD (TODR, todr_reg, 32, "time-of-day register"), PV_LEFT }, + { FLDATAD (BLOW, todr_blow, 0, "TODR battery low indicator") }, + { DRDATAD (TIME, clk_unit.wait, 24, "initial poll interval"), REG_NZ + PV_LEFT }, + { DRDATAD (POLL, tmr_poll, 24, "calibrated poll interval"), REG_NZ + PV_LEFT + REG_HRO }, + { DRDATAD (TPS, clk_tps, 8, "ticks per second (100)"), REG_NZ + PV_LEFT }, #if defined (SIM_ASYNCH_IO) - { DRDATA (ASYNCH, sim_asynch_enabled, 1), PV_LEFT }, - { DRDATA (LATENCY, sim_asynch_latency, 32), PV_LEFT }, - { DRDATA (INST_LATENCY, sim_asynch_inst_latency, 32), PV_LEFT }, + { DRDATAD (ASYNCH, sim_asynch_enabled, 1, "asynch I/O enabled flag"), PV_LEFT }, + { DRDATAD (LATENCY, sim_asynch_latency, 32, "desired asynch interrupt latency"), PV_LEFT }, + { DRDATAD (INST_LATENCY, sim_asynch_inst_latency, 32, "calibrated instruction latency"), PV_LEFT }, #endif { NULL } }; @@ -340,7 +342,7 @@ return SCPE_OK; t_stat tti_reset (DEVICE *dptr) { -tmxr_set_console_input_unit (&tti_unit); +tmxr_set_console_units (&tti_unit, &tto_unit); tti_unit.buf = 0; tti_csr = 0; CLR_INT (TTI); diff --git a/VAX/vax_sys.c b/VAX/vax_sys.c index 0cf2f482..19865134 100644 --- a/VAX/vax_sys.c +++ b/VAX/vax_sys.c @@ -57,7 +57,6 @@ extern UNIT cpu_unit; extern REG cpu_reg[]; extern int32 saved_PC; extern int32 PSL; -extern int32 sim_switches; t_stat fprint_sym_m (FILE *of, uint32 addr, t_value *val); int32 fprint_sym_qoimm (FILE *of, t_value *val, int32 vp, int32 lnt); diff --git a/VAX/vax_syscm.c b/VAX/vax_syscm.c index de658624..46225523 100644 --- a/VAX/vax_syscm.c +++ b/VAX/vax_syscm.c @@ -1,6 +1,6 @@ /* vax_syscm.c: PDP-11 compatibility mode symbolic decode and parse - Copyright (c) 1993-2010, Robert M Supnik + Copyright (c) 1993-2012, Robert M Supnik Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), @@ -23,6 +23,7 @@ used in advertising or otherwise to promote the sale, use or other dealings in this Software without prior written authorization from Robert M Supnik. + 29-Apr-12 RMS Fixed compiler warning (Mark Pizzolato) 22-May-10 RMS Fixed t_addr printouts for 64b big-endian systems (Mark Pizzolato) 12-Nov-06 RMS Fixed operand order in EIS instructions (W.F.J. Mueller) diff --git a/VAX/vax_sysdev.c b/VAX/vax_sysdev.c index 03c62937..49fc8885 100644 --- a/VAX/vax_sysdev.c +++ b/VAX/vax_sysdev.c @@ -54,13 +54,26 @@ #include "vax_defs.h" -#ifndef DONT_USE_INTERNAL_ROM -#include "vax_ka655x_bin.h" -#endif +#ifdef DONT_USE_INTERNAL_ROM +#define BOOT_CODE_FILENAME "ka655x.bin" +#else /* !DONT_USE_INTERNAL_ROM */ +#include "vax_ka655x_bin.h" /* Defines BOOT_CODE_FILENAME and BOOT_CODE_ARRAY, etc */ +#endif /* DONT_USE_INTERNAL_ROM */ #define UNIT_V_NODELAY (UNIT_V_UF + 0) /* ROM access equal to RAM access */ #define UNIT_NODELAY (1u << UNIT_V_NODELAY) +t_stat vax_boot (int32 flag, char *ptr); +int32 sys_model = 0; + +/* Special boot command, overrides regular boot */ + +CTAB vax_cmd[] = { + { "BOOT", &vax_boot, RU_BOOT, + "bo{ot} boot simulator\n", &run_cmd_message }, + { NULL } + }; + /* Console storage control/status */ #define CSICSR_IMP (CSR_DONE + CSR_IE) /* console input */ @@ -190,7 +203,6 @@ extern UNIT cpu_unit; extern UNIT clk_unit; extern jmp_buf save_env; extern int32 p1; -extern int32 sim_switches; extern int32 MSER; extern int32 tmr_poll; @@ -343,13 +355,14 @@ DIB csi_dib = { 0, 0, NULL, NULL, 1, IVCL (CSI), SCB_CSI, { NULL } }; UNIT csi_unit = { UDATA (NULL, 0, 0), KBD_POLL_WAIT }; REG csi_reg[] = { - { ORDATA (BUF, csi_unit.buf, 8) }, - { ORDATA (CSR, csi_csr, 16) }, - { FLDATA (INT, int_req[IPL_CSI], INT_V_CSI) }, - { FLDATA (DONE, csi_csr, CSR_V_DONE) }, - { FLDATA (IE, csi_csr, CSR_V_IE) }, - { DRDATA (POS, csi_unit.pos, 32), PV_LEFT }, - { DRDATA (TIME, csi_unit.wait, 24), REG_NZ + PV_LEFT }, + { ORDATAD (BUF, csi_unit.buf, 8, "last data item processed") }, + { ORDATAD (CSR, csi_csr, 16, "control/status register") }, + { FLDATAD (INT, int_req[IPL_CSI], INT_V_CSI, "interrupt pending flag") }, + { FLDATAD (DONE, csi_csr, CSR_V_DONE, "device done flag (CSR<7>)") }, + { FLDATAD (ERR, csi_csr, CSR_V_ERR, "error flag (CSR<15>)") }, + { FLDATAD (IE, csi_csr, CSR_V_IE, "interrupt enable flag (CSR<6>)") }, + { DRDATAD (POS, csi_unit.pos, 32, "number of characters input"), PV_LEFT }, + { DRDATAD (TIME, csi_unit.wait, 24, "input polling interval"), REG_NZ + PV_LEFT }, { NULL } }; @@ -378,13 +391,14 @@ DIB cso_dib = { 0, 0, NULL, NULL, 1, IVCL (CSO), SCB_CSO, { NULL } }; UNIT cso_unit = { UDATA (&cso_svc, UNIT_SEQ+UNIT_ATTABLE, 0), SERIAL_OUT_WAIT }; REG cso_reg[] = { - { ORDATA (BUF, cso_unit.buf, 8) }, - { ORDATA (CSR, cso_csr, 16) }, - { FLDATA (INT, int_req[IPL_CSO], INT_V_CSO) }, - { FLDATA (DONE, cso_csr, CSR_V_DONE) }, - { FLDATA (IE, cso_csr, CSR_V_IE) }, - { DRDATA (POS, cso_unit.pos, 32), PV_LEFT }, - { DRDATA (TIME, cso_unit.wait, 24), PV_LEFT }, + { ORDATAD (BUF, cso_unit.buf, 8, "last data item processed") }, + { ORDATAD (CSR, cso_csr, 16, "control/status register") }, + { FLDATAD (INT, int_req[IPL_CSO], INT_V_CSO, "interrupt pending flag") }, + { FLDATAD (ERR, cso_csr, CSR_V_ERR, "error flag (CSR<15>)") }, + { FLDATAD (DONE, cso_csr, CSR_V_DONE, "device done flag (CSR<7>)") }, + { FLDATAD (IE, cso_csr, CSR_V_IE, "interrupt enable flag (CSR<6>)") }, + { DRDATAD (POS, cso_unit.pos, 32, "number of characters output"), PV_LEFT }, + { DRDATAD (TIME, cso_unit.wait, 24, "time from I/O initiation to interrupt"), PV_LEFT }, { NULL } }; @@ -419,34 +433,34 @@ UNIT sysd_unit[] = { }; REG sysd_reg[] = { - { HRDATA (CADR, CADR, 8) }, - { HRDATA (MSER, MSER, 8) }, - { HRDATA (CONPC, conpc, 32) }, - { HRDATA (CONPSL, conpsl, 32) }, - { BRDATA (CMCSR, cmctl_reg, 16, 32, CMCTLSIZE >> 2) }, - { HRDATA (CACR, ka_cacr, 8) }, - { HRDATA (BDR, ka_bdr, 8) }, - { HRDATA (BASE, ssc_base, 29) }, - { HRDATA (CNF, ssc_cnf, 32) }, - { HRDATA (BTO, ssc_bto, 32) }, - { HRDATA (OTP, ssc_otp, 4) }, - { HRDATA (TCSR0, tmr_csr[0], 32) }, - { HRDATA (TIR0, tmr_tir[0], 32) }, - { HRDATA (TNIR0, tmr_tnir[0], 32) }, - { HRDATA (TIVEC0, tmr_tivr[0], 9) }, - { HRDATA (TINC0, tmr_inc[0], 32) }, - { HRDATA (TSAV0, tmr_sav[0], 32) }, - { HRDATA (TCSR1, tmr_csr[1], 32) }, - { HRDATA (TIR1, tmr_tir[1], 32) }, - { HRDATA (TNIR1, tmr_tnir[1], 32) }, - { HRDATA (TIVEC1, tmr_tivr[1], 9) }, - { HRDATA (TINC1, tmr_inc[1], 32) }, - { HRDATA (TSAV1, tmr_sav[1], 32) }, - { HRDATA (ADSM0, ssc_adsm[0], 32) }, - { HRDATA (ADSK0, ssc_adsk[0], 32) }, - { HRDATA (ADSM1, ssc_adsm[1], 32) }, - { HRDATA (ADSK1, ssc_adsk[1], 32) }, - { BRDATA (CDGDAT, cdg_dat, 16, 32, CDASIZE >> 2) }, + { HRDATAD (CADR, CADR, 8, "cache disable register") }, + { HRDATAD (MSER, MSER, 8, "memory system error register") }, + { HRDATAD (CONPC, conpc, 32, "PC at console halt") }, + { HRDATAD (CONPSL, conpsl, 32, "PSL at console halt") }, + { BRDATAD (CMCSR, cmctl_reg, 16, 32, CMCTLSIZE >> 2, "CMCTL control and status registers") }, + { HRDATAD (CACR, ka_cacr, 8, "second-level cache control register") }, + { HRDATAD (BDR, ka_bdr, 8, "front panel jumper register") }, + { HRDATAD (BASE, ssc_base, 29, "SSC base address register") }, + { HRDATAD (CNF, ssc_cnf, 32, "SSC configuration register") }, + { HRDATAD (BTO, ssc_bto, 32, "SSC bus timeout register") }, + { HRDATAD (OTP, ssc_otp, 4, "SSC output port") }, + { HRDATAD (TCSR0, tmr_csr[0], 32, "SSC timer 0 control/status register") }, + { HRDATAD (TIR0, tmr_tir[0], 32, "SSC timer 0 interval register") }, + { HRDATAD (TNIR0, tmr_tnir[0], 32, "SSC timer 0 next interval register") }, + { HRDATAD (TIVEC0, tmr_tivr[0], 9, "SSC timer 0 interrupt vector register") }, + { HRDATAD (TINC0, tmr_inc[0], 32, "SSC timer 0 tir increment") }, + { HRDATAD (TSAV0, tmr_sav[0], 32, "SSC timer 0 saved inst cnt") }, + { HRDATAD (TCSR1, tmr_csr[1], 32, "SSC timer 1 control/status register") }, + { HRDATAD (TIR1, tmr_tir[1], 32, "SSC timer 1 interval register") }, + { HRDATAD (TNIR1, tmr_tnir[1], 32, "SSC timer 1 next interval register") }, + { HRDATAD (TIVEC1, tmr_tivr[1], 9, "SSC timer 1 interrupt vector register") }, + { HRDATAD (TINC1, tmr_inc[1], 32, "SSC timer 1 tir increment") }, + { HRDATAD (TSAV1, tmr_sav[1], 32, "SSC timer 1 saved inst cnt") }, + { HRDATAD (ADSM0, ssc_adsm[0], 32, "SSC address match 0 address") }, + { HRDATAD (ADSK0, ssc_adsk[0], 32, "SSC address match 0 mask") }, + { HRDATAD (ADSM1, ssc_adsm[1], 32, "SSC address match 1 address") }, + { HRDATAD (ADSK1, ssc_adsk[1], 32, "SSC address match 1 mask") }, + { BRDATAD (CDGDAT, cdg_dat, 16, 32, CDASIZE >> 2, "cache diagnostic data store") }, { NULL } }; @@ -1450,7 +1464,7 @@ return; void tmr_sched (int32 tmr) { -int32 clk_time = sim_is_active (&clk_unit) - 1; +int32 clk_time = sim_activate_time (&clk_unit) - 1; int32 tmr_time; tmr_sav[tmr] = sim_grtime (); /* save intvl base */ @@ -1541,12 +1555,27 @@ JUMP (ROMBASE); /* PC = 20040000 */ return 0; /* new cc = 0 */ } +/* Special boot command - linked into SCP by initial reset + + Syntax: BOOT {CPU} + +*/ + +t_stat vax_boot (int32 flag, char *ptr) +{ +char gbuf[CBUFSIZE]; + +get_glyph (ptr, gbuf, 0); /* get glyph */ +if (gbuf[0] && strcmp (gbuf, "CPU")) + return SCPE_ARG; /* Only can specify CPU device */ +return run_cmd (flag, "CPU"); +} + + /* Bootstrap */ t_stat cpu_boot (int32 unitno, DEVICE *dptr) { -extern t_stat load_cmd (int32 flag, char *cptr); -extern FILE *sim_log; t_stat r; PC = ROMBASE; @@ -1556,33 +1585,20 @@ conpsl = PSL_IS | PSL_IPL1F | CON_PWRUP; if (rom == NULL) return SCPE_IERR; if (*rom == 0) { /* no boot? */ - printf ("Loading boot code from ka655x.bin\n"); - if (sim_log) - fprintf (sim_log, "Loading boot code from ka655x.bin\n"); - r = load_cmd (0, "-R ka655x.bin"); - if (r != SCPE_OK) { -#ifndef DONT_USE_INTERNAL_ROM - FILE *f; - - if ((f = sim_fopen ("ka655x.bin", "wb"))) { - printf ("Saving boot code to ka655x.bin\n"); - if (sim_log) - fprintf (sim_log, "Saving boot code to ka655x.bin\n"); - sim_fwrite (vax_ka655x_bin, sizeof(vax_ka655x_bin[0]), sizeof(vax_ka655x_bin)/sizeof(vax_ka655x_bin[0]), f); - fclose (f); - printf ("Loading boot code from ka655x.bin\n"); - if (sim_log) - fprintf (sim_log, "Loading boot code from ka655x.bin\n"); - r = load_cmd (0, "-R ka655x.bin"); - } -#endif + r = cpu_load_bootcode (BOOT_CODE_FILENAME, BOOT_CODE_ARRAY, BOOT_CODE_SIZE, TRUE, 0); + if (r != SCPE_OK) return r; - } } sysd_powerup (); return SCPE_OK; } +t_stat cpu_print_model (FILE *st) +{ +fprintf (st, "VAX 3900"); +return SCPE_OK; +} + /* SYSD reset */ t_stat sysd_reset (DEVICE *dptr) @@ -1603,6 +1619,7 @@ cso_csr = CSR_DONE; cso_unit.buf = 0; sim_cancel (&cso_unit); CLR_INT (CSO); +sim_vm_cmd = vax_cmd; return SCPE_OK; } @@ -1625,3 +1642,33 @@ ssc_bto = 0; ssc_otp = 0; return SCPE_OK; } + + +t_stat cpu_model_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr) +{ +fprintf (st, "Notes on memory size:\n\n"); +fprintf (st, "- The real KA655 CPU only supported 16MB to 64MB of memory. The simulator\n"); +fprintf (st, " implements a KA655\"X\", which increases supported memory to 512MB.\n"); +fprintf (st, "- The firmware (ka655x.bin) contains code to determine the size of extended\n"); +fprintf (st, " memory and set up the PFN bit map accordingly. Other than setting up the\n"); +fprintf (st, " PFN bit map, the firmware does not recognize extended memory and will\n"); +fprintf (st, " behave as though memory size was 64MB.\n"); +fprintf (st, "- If memory size is being reduced, and the memory being truncated contains\n"); +fprintf (st, " non-zero data, the simulator asks for confirmation. Data in the truncated\n"); +fprintf (st, " portion of memory is lost.\n"); +fprintf (st, "- If the simulator is running VMS, the operating system may have a SYSGEN\n"); +fprintf (st, " parameter set called PHYSICAL PAGES (viewable with\n"); +fprintf (st, " \"MCR SYSGEN SHOW PHYSICALPAGES\"). PHYSICALPAGES limits the maximum\n"); +fprintf (st, " number of physical pages of memory the OS will recognize. If it is set\n"); +fprintf (st, " to a lower value than the new memory size of the machine, then only the\n"); +fprintf (st, " first PHYSICALPAGES of memory will be recognized, otherwise the actual size\n"); +fprintf (st, " of the extended memory will be realized by VMS upon each boot. Some users\n"); +fprintf (st, " and/or sites may specify the PHYSICALPAGES parameter in the input file to\n"); +fprintf (st, " AUTOGEN (SYS$SYSTEM:MODPARAMS.DAT). If PHYSICALPAGES is specified there,\n"); +fprintf (st, " it will have to be adjusted before running AUTOGEN to recognize more memory.\n"); +fprintf (st, " The default value for PHYSICALPAGES is 1048576, which describes 512MB of RAM.\n\n"); +fprintf (st, "Initial memory size is 16MB.\n\n"); +fprintf (st, "The simulator is booted with the BOOT command:\n\n"); +fprintf (st, " sim> BOOT\n\n"); +return SCPE_OK; +} diff --git a/VAX/vax_syslist.c b/VAX/vax_syslist.c index 054c5e43..fed69143 100644 --- a/VAX/vax_syslist.c +++ b/VAX/vax_syslist.c @@ -51,8 +51,8 @@ extern DEVICE dz_dev; extern DEVICE csi_dev, cso_dev; extern DEVICE xq_dev, xqb_dev; extern DEVICE vh_dev; +extern DEVICE dmc_dev[]; -extern int32 sim_switches; extern void WriteB (uint32 pa, int32 val); extern void rom_wr_B (int32 pa, int32 val); extern UNIT cpu_unit; @@ -83,6 +83,10 @@ DEVICE *sim_devices[] = { &tq_dev, &xq_dev, &xqb_dev, + &dmc_dev[0], + &dmc_dev[1], + &dmc_dev[2], + &dmc_dev[3], NULL }; diff --git a/VAX/vax780_vmb_exe.h b/VAX/vax_vmb_exe.h similarity index 98% rename from VAX/vax780_vmb_exe.h rename to VAX/vax_vmb_exe.h index 6b6af820..160715bd 100644 --- a/VAX/vax780_vmb_exe.h +++ b/VAX/vax_vmb_exe.h @@ -1,11 +1,15 @@ -#ifndef ROM_vax780_vmb_exe_H -#define ROM_vax780_vmb_exe_H 0 +#ifndef ROM_vax_vmb_exe_H +#define ROM_vax_vmb_exe_H 0 /* - VAX/vax780_vmb_exe.h produced at Sun Feb 26 12:32:44 2012 - from VAX/vmb.exe which was last modified at Sat Feb 18 00:01:12 2012 + VAX/vax_vmb_exe.h produced at Fri Nov 09 06:40:16 2012 + from VAX/vmb.exe which was last modified at Sun Oct 21 17:12:55 2012 file size: 44544 (0xAE00) - checksum: 0xFFC014CC + This file is a generated file and should NOT be edited or changed by hand. */ -unsigned char vax780_vmb_exe[] = { +#define BOOT_CODE_SIZE 0xAE00 +#define BOOT_CODE_FILENAME "vmb.exe" +#define BOOT_CODE_ARRAY vax_vmb_exe +unsigned char vax_vmb_exe[] = { 0xD4,0xEF,0x34,0x61,0x00,0x00,0x17,0xEF,0xB8,0x5D,0x00,0x00,0xC1,0xAB,0x38,0xAB, 0x34,0x57,0xC0,0x8F,0x00,0x02,0x00,0x00,0x57,0xCA,0x8F,0xFF,0x01,0x00,0x00,0x57, 0x95,0xCF,0x18,0x03,0x13,0x08,0xD4,0x50,0x7D,0xAB,0x44,0x52,0x11,0x24,0x7D,0xAB, @@ -2790,4 +2794,4 @@ unsigned char vax780_vmb_exe[] = { 0x4C,0x52,0x45,0x41,0x44,0x3A,0x58,0x2D,0x32,0x20,0x20,0x43,0x4F,0x4E,0x49,0x4F, 0x3A,0x58,0x2D,0x33,0x20,0x20,0x2A,0x45,0x6E,0x64,0x20,0x6F,0x66,0x20,0x49,0x64, 0x65,0x6E,0x74,0x20,0x6C,0x69,0x73,0x74,0x73,0x2A,0x00,0x00,0x00,0x00,0x00,0x00,}; -#endif /* ROM_vax780_vmb_exe_H */ +#endif /* ROM_vax_vmb_exe_H */ diff --git a/VAX/vax_watch.c b/VAX/vax_watch.c new file mode 100644 index 00000000..86a954ac --- /dev/null +++ b/VAX/vax_watch.c @@ -0,0 +1,215 @@ +/* vax_watch.c: VAX watch chip + + Copyright (c) 2011-2012, Matt Burke + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHOR BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name of the author shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from the author. + + wtc Watch chip + + 08-Nov-2012 MB First version + + This file covers the watch chip (MC146818) which is used by several VAX + models including the KA620, KA630, KA410, KA420 and KA820. +*/ + +#include "vax_defs.h" +#include + +/* control/status registers */ + +#define WTC_CSRA_RS 0x0F +#define WTC_CSRA_V_DV 4 +#define WTC_CSRA_M_DV 0x7 +#define WTC_CSRA_DV (WTC_CSRA_M_DV << WTC_CSRA_V_DV) +#define WTC_CSRA_UIP 0x80 /* update in progess */ +#define WTC_CSRA_WR (WTC_CSRA_RS | WTC_CSRA_DV) + +#define WTC_CSRB_DSE 0x01 /* daylight saving en */ +#define WTC_CSRB_2412 0x02 /* 24/12hr select */ +#define WTC_CSRB_DM 0x04 /* data mode */ +#define WTC_CSRB_SET 0x80 /* set time */ +#define WTC_CSRB_WR (WTC_CSRB_DSE | WTC_CSRB_2412 | WTC_CSRB_DM | WTC_CSRB_SET) + +#define WTC_CSRD_VRT 0x80 /* valid time */ +#define WTC_CSRD_RD (WTC_CSRD_VRT) + +#define WTC_MODE_STD 0 +#define WTC_MODE_VMS 1 + +int32 wtc_csra = 0; +int32 wtc_csrb = 0; +int32 wtc_csrc = 0; +int32 wtc_csrd = 0; +int32 wtc_mode = WTC_MODE_VMS; + +t_stat wtc_set (UNIT *uptr, int32 val, char *cptr, void *desc); +t_stat wtc_show (FILE *st, UNIT *uptr, int32 val, void *desc); +t_stat wtc_reset (DEVICE *dptr); +void wtc_set_valid (void); +void wtc_set_invalid (void); + +UNIT wtc_unit = { UDATA (NULL, 0, 0) }; + +REG wtc_reg[] = { + { HRDATA (CSRA, wtc_csra, 8) }, + { HRDATA (CSRB, wtc_csrb, 8) }, + { HRDATA (CSRC, wtc_csrc, 8) }, + { HRDATA (CSRD, wtc_csrd, 8) }, + { NULL } + }; + +MTAB wtc_mod[] = { + { MTAB_XTD|MTAB_VDV, 0, "TIME", "TIME={VMS|STD}", &wtc_set, &wtc_show }, + { 0 } + }; + +DEVICE wtc_dev = { + "WTC", &wtc_unit, wtc_reg, wtc_mod, + 1, 16, 16, 1, 16, 8, + NULL, NULL, &wtc_reset, + NULL, NULL, NULL, + NULL, 0 + }; + +int32 wtc_rd (int32 pa) +{ +int32 rg = (pa >> 1) & 0xF; +int32 val = 0; +time_t curr; +struct tm *ctm = NULL; + +if (rg < 10) { /* time reg? */ + curr = time (NULL); /* get curr time */ + if (curr == (time_t) -1) /* error? */ + return 0; + ctm = localtime (&curr); /* decompose */ + if (ctm == NULL) /* error? */ + return 0; + } + +switch(rg) { + + case 0: /* seconds */ + val = ctm->tm_sec; + break; + + case 2: /* minutes */ + val = ctm->tm_min; + break; + + case 4: /* hours */ + val = ctm->tm_hour; + break; + + case 6: /* day of week */ + val = ctm->tm_wday; + break; + + case 7: /* day of month */ + val = ctm->tm_mday; + break; + + case 8: /* month */ + val = ctm->tm_mon; + break; + + case 9: /* year */ + if (wtc_mode == WTC_MODE_VMS) + val = 82; /* always 1982 for VMS */ + else + val = (int32)(ctm->tm_year % 100); + break; + + case 10: /* CSR A */ + val = wtc_csra; + break; + + case 11: /* CSR B */ + val = wtc_csrb; + break; + + case 12: /* CSR C */ + val = wtc_csrc; + break; + + case 13: /* CSR D */ + val = wtc_csrd & WTC_CSRD_RD; + break; + } + +return ((rg & 1) ? (val << 16) : val); /* word aligned? */ +} + +void wtc_wr (int32 pa, int32 val, int32 lnt) +{ +int32 rg = (pa >> 1) & 0xF; +val = val & 0xFF; + +switch(rg) { + + case 10: /* CSR A */ + val = val & WTC_CSRA_WR; + wtc_csra = (wtc_csra & ~WTC_CSRA_WR) | val; + break; + + case 11: /* CSR B */ + val = val & WTC_CSRB_WR; + wtc_csrb = (wtc_csrb & ~WTC_CSRB_WR) | val; + break; + } +} + +t_stat wtc_reset (DEVICE *dptr) +{ +if (sim_switches & SWMASK ('P')) { /* powerup? */ + wtc_csra = 0; + wtc_csrb = 0; + wtc_csrc = 0; + wtc_csrd = 0; + wtc_mode = WTC_MODE_VMS; + } +return SCPE_OK; +} + +t_stat wtc_set (UNIT *uptr, int32 val, char *cptr, void *desc) +{ +if (cptr != NULL) wtc_mode = strcmp(cptr, "STD"); +return SCPE_OK; +} + +t_stat wtc_show (FILE *st, UNIT *uptr, int32 val, void *desc) +{ +fprintf(st, "time=%s", (wtc_mode ? "vms" :"std")); +return SCPE_OK; +} + +void wtc_set_valid (void) +{ +wtc_csra |= (2 << WTC_CSRA_V_DV); +wtc_csrb |= (WTC_CSRB_DM | WTC_CSRB_2412); +wtc_csrd |= WTC_CSRD_VRT; +} + +void wtc_set_invalid (void) +{ +wtc_csrd &= ~WTC_CSRD_VRT; +} diff --git a/VAX/vaxmod_defs.h b/VAX/vaxmod_defs.h index 2f235481..f6ed72b3 100644 --- a/VAX/vaxmod_defs.h +++ b/VAX/vaxmod_defs.h @@ -96,6 +96,7 @@ #define MT_CONPC 42 #define MT_CONPSL 43 #define MT_IORESET 55 +#define MT_MAX 63 /* last valid IPR */ /* Memory system error register */ @@ -117,6 +118,18 @@ #define INITMEMSIZE (1 << 24) /* initial memory size */ #define MEMSIZE (cpu_unit.capac) #define ADDR_IS_MEM(x) (((uint32) (x)) < MEMSIZE) +#define MEM_MODIFIERS { UNIT_MSIZE, (1u << 23), NULL, "8M", &cpu_set_size }, \ + { UNIT_MSIZE, (1u << 24), NULL, "16M", &cpu_set_size }, \ + { UNIT_MSIZE, (1u << 25), NULL, "32M", &cpu_set_size }, \ + { UNIT_MSIZE, (1u << 25) + (1u << 24), NULL, "48M", &cpu_set_size }, \ + { UNIT_MSIZE, (1u << 26), NULL, "64M", &cpu_set_size }, \ + { UNIT_MSIZE, (1u << 27), NULL, "128M", &cpu_set_size }, \ + { UNIT_MSIZE, (1u << 28), NULL, "256M", &cpu_set_size }, \ + { UNIT_MSIZE, (1u << 29), NULL, "512M", &cpu_set_size } +#define CPU_MODEL_MODIFIERS \ + { MTAB_XTD|MTAB_VDV, 0, "MODEL", NULL, \ + NULL, &cpu_show_model }, + /* Cache diagnostic space */ @@ -249,11 +262,9 @@ #define DEV_V_UBUS (DEV_V_UF + 0) /* Unibus */ #define DEV_V_QBUS (DEV_V_UF + 1) /* Qbus */ #define DEV_V_Q18 (DEV_V_UF + 2) /* Qbus, mem <= 256KB */ -#define DEV_V_FLTA (DEV_V_UF + 3) /* flt addr */ #define DEV_UBUS (1u << DEV_V_UBUS) #define DEV_QBUS (1u << DEV_V_QBUS) #define DEV_Q18 (1u << DEV_V_Q18) -#define DEV_FLTA (1u << DEV_V_FLTA) #define UNIBUS FALSE /* 22b only */ @@ -274,50 +285,10 @@ typedef struct { int32 (*ack[VEC_DEVMAX])(void); /* ack routine */ } DIB; -/* I/O page layout - RQB,RQC,RQD float based on number of DZ's */ +/* Qbus I/O page layout - see pdp11_ui_lib.c for address layout details */ + +#define IOBA_AUTO (0) /* Assigned by Auto Configure */ -#define IOBA_DZ (IOPAGEBASE + 000100) /* DZ11 */ -#define IOLN_DZ 010 -#define IOBA_RQB (IOPAGEBASE + 000334 + (020 * (DZ_MUXES / 2))) -#define IOLN_RQB 004 -#define IOBA_RQC (IOPAGEBASE + IOBA_RQB + IOLN_RQB) -#define IOLN_RQC 004 -#define IOBA_RQD (IOPAGEBASE + IOBA_RQC + IOLN_RQC) -#define IOLN_RQD 004 -#define IOBA_VH (IOPAGEBASE + 000440) /* DHQ11 */ -#define IOLN_VH 020 -#define IOBA_RQ (IOPAGEBASE + 012150) /* RQDX3 */ -#define IOLN_RQ 004 -#define IOBA_TS (IOPAGEBASE + 012520) /* TS11 */ -#define IOLN_TS 004 -#define IOBA_RL (IOPAGEBASE + 014400) /* RL11 */ -#define IOLN_RL 012 -#define IOBA_XQ (IOPAGEBASE + 014440) /* DEQNA/DELQA */ -#define IOLN_XQ 020 -#define IOBA_XQB (IOPAGEBASE + 014460) /* 2nd DEQNA/DELQA */ -#define IOLN_XQB 020 -#define IOBA_TQ (IOPAGEBASE + 014500) /* TMSCP */ -#define IOLN_TQ 004 -#define IOBA_XU (IOPAGEBASE + 014510) /* DEUNA/DELUA */ -#define IOLN_XU 010 -#define IOBA_RP (IOPAGEBASE + 016700) /* RP/RM */ -#define IOLN_RP 054 -#define IOBA_CR (IOPAGEBASE + 017160) /* CD/CR/CM */ -#define IOLN_CR 010 -#define IOBA_RX (IOPAGEBASE + 017170) /* RXV11 */ -#define IOLN_RX 004 -#define IOBA_RY (IOPAGEBASE + 017170) /* RXV21 */ -#define IOLN_RY 004 -#define IOBA_QDSS (IOPAGEBASE + 017400) /* QDSS */ -#define IOLN_QDSS 002 -#define IOBA_DBL (IOPAGEBASE + 017500) /* doorbell */ -#define IOLN_DBL 002 -#define IOBA_LPT (IOPAGEBASE + 017514) /* LP11 */ -#define IOLN_LPT 004 -#define IOBA_PTR (IOPAGEBASE + 017550) /* PC11 reader */ -#define IOLN_PTR 004 -#define IOBA_PTP (IOPAGEBASE + 017554) /* PC11 punch */ -#define IOLN_PTP 004 /* The KA65x maintains 4 separate hardware IPL levels, IPL 17 to IPL 14; however, DEC Qbus controllers all interrupt on IPL 14 @@ -356,6 +327,8 @@ typedef struct { #define INT_V_VHTX 18 #define INT_V_QDSS 19 /* QDSS */ #define INT_V_CR 20 +#define INT_V_DMCRX 21 /* DMC11 */ +#define INT_V_DMCTX 22 #define INT_CLK (1u << INT_V_CLK) #define INT_RQ (1u << INT_V_RQ) @@ -379,6 +352,8 @@ typedef struct { #define INT_VHTX (1u << INT_V_VHTX) #define INT_QDSS (1u << INT_V_QDSS) #define INT_CR (1u << INT_V_CR) +#define INT_DMCRX (1u << INT_V_DMCRX) +#define INT_DMCTX (1u << INT_V_DMCTX) #define IPL_CLK (0x16 - IPL_HMIN) /* relative IPL */ #define IPL_RQ (0x14 - IPL_HMIN) @@ -402,6 +377,8 @@ typedef struct { #define IPL_VHTX (0x14 - IPL_HMIN) #define IPL_QDSS (0x14 - IPL_HMIN) #define IPL_CR (0x14 - IPL_HMIN) +#define IPL_DMCRX (0x14 - IPL_HMIN) +#define IPL_DMCTX (0x14 - IPL_HMIN) #define IPL_HMAX 0x17 /* highest hwre level */ #define IPL_HMIN 0x14 /* lowest hwre level */ @@ -410,24 +387,11 @@ typedef struct { /* Device vectors */ +#define VEC_AUTO (0) /* Assigned by Auto Configure */ +#define VEC_FLOAT (0) /* Assigned by Auto Configure */ + #define VEC_QBUS 1 /* Qbus system */ #define VEC_Q 0x200 /* Qbus vector offset */ -#define VEC_PTR (VEC_Q + 0070) -#define VEC_PTP (VEC_Q + 0074) -#define VEC_XQ (VEC_Q + 0120) -#define VEC_XU (VEC_Q + 0120) -#define VEC_RQ (VEC_Q + 0154) -#define VEC_RL (VEC_Q + 0160) -#define VEC_LPT (VEC_Q + 0200) -#define VEC_TS (VEC_Q + 0224) -#define VEC_CR (VEC_Q + 0230) -#define VEC_TQ (VEC_Q + 0260) -#define VEC_RX (VEC_Q + 0264) -#define VEC_RY (VEC_Q + 0264) -#define VEC_DZRX (VEC_Q + 0300) -#define VEC_DZTX (VEC_Q + 0304) -#define VEC_VHRX (VEC_Q + 0310) -#define VEC_VHTX (VEC_Q + 0314) /* Interrupt macros */ @@ -466,8 +430,6 @@ int32 Map_ReadW (uint32 ba, int32 bc, uint16 *buf); int32 Map_WriteB (uint32 ba, int32 bc, uint8 *buf); int32 Map_WriteW (uint32 ba, int32 bc, uint16 *buf); -int32 clk_cosched (int32 wait); - #include "pdp11_io_lib.h" #endif diff --git a/Visual Studio Projects/0ReadMe_Projects.txt b/Visual Studio Projects/0ReadMe_Projects.txt index 8b90b547..9961d138 100644 --- a/Visual Studio Projects/0ReadMe_Projects.txt +++ b/Visual Studio Projects/0ReadMe_Projects.txt @@ -21,7 +21,7 @@ For Example, the directory structure should look like: The contents of the windows-build directory can be downloaded from: - https://github.com/downloads/markpizz/simh/windows-build.zip + https://github.com/simh/windows-build/archive/windows-build.zip Network devices are capable of using pthreads to enhance their performance. diff --git a/Visual Studio Projects/ALTAIR.vcproj b/Visual Studio Projects/ALTAIR.vcproj index 50953c79..9c633b11 100644 --- a/Visual Studio Projects/ALTAIR.vcproj +++ b/Visual Studio Projects/ALTAIR.vcproj @@ -26,6 +26,8 @@ > + + @@ -218,6 +226,10 @@ RelativePath="..\sim_fio.c" > + + @@ -255,6 +267,10 @@ RelativePath="..\sim_defs.h" > + + @@ -267,6 +283,10 @@ RelativePath="..\sim_rev.h" > + + diff --git a/Visual Studio Projects/AltairZ80.vcproj b/Visual Studio Projects/AltairZ80.vcproj index 9125307d..e6908365 100644 --- a/Visual Studio Projects/AltairZ80.vcproj +++ b/Visual Studio Projects/AltairZ80.vcproj @@ -26,6 +26,8 @@ > + + @@ -321,6 +329,10 @@ RelativePath="..\AltairZ80\sim_imd.c" > + + @@ -366,6 +378,10 @@ RelativePath="..\sim_defs.h" > + + @@ -378,6 +394,10 @@ RelativePath="..\sim_rev.h" > + + diff --git a/Visual Studio Projects/BuildAll.cmd b/Visual Studio Projects/BuildAll.cmd new file mode 100644 index 00000000..c64268e3 --- /dev/null +++ b/Visual Studio Projects/BuildAll.cmd @@ -0,0 +1,63 @@ +rem +rem This script will build all the simulators in the current branch +rem (presumed to be master) and package the resulting windows binaries +rem into a zip file which will be named for the revision, build date and +rem git commit id. The resulting zip file will be pushed to the github +rem Win32-Development-Binaries repository for public access. +rem +rem We're using a github repository for this purpose since github no longer +rem supports a Download files facility since some folks were using it to +rem contain large binary files. The typical set of simh windows binaries +rem is under 7MB in size and the plan is to delete and recreate the whole +rem Win32-Development-Binaries repository at least every few months. +rem +rem If this script is invoked with a single parameter "reset", the local +rem repository will be wiped out and reset. This should be done AFTER +rem the github one is deleted and recreated. +rem +rem + +set BIN_REPO=Win32-Development-Binaries +if exist "%ProgramFiles%\Microsoft Visual Studio 9.0\VC\bin\vcvars32.bat" call "%ProgramFiles%\Microsoft Visual Studio 9.0\VC\bin\vcvars32.bat" +if exist "%ProgramFiles(x86)%\Microsoft Visual Studio 9.0\VC\bin\vcvars32.bat" call "%ProgramFiles(x86)%\Microsoft Visual Studio 9.0\VC\bin\vcvars32.bat" +cd %~p0 +SET GIT_COMMIT_ID= +if not exist ..\.git-commit-id goto _NoId +for /F %%i in (..\.git-commit-id) do set GIT_COMMIT_ID=%%i +for /F "tokens=3 delims=/" %%i in ("%DATE%") do set D_YYYY=%%i +for /F "tokens=2 delims=/ " %%i in ("%DATE%") do set D_MM=%%i +for /F "tokens=2 delims=/" %%i in ("%DATE%") do set D_DD=%%i +for /F "usebackq tokens=3" %%i in (`findstr/C:"#define SIM_MAJOR" ..\sim_rev.h`) do set _SIM_MAJOR=%%i +for /F "usebackq tokens=3" %%i in (`findstr/C:"#define SIM_MINOR" ..\sim_rev.h`) do set _SIM_MINOR=%%i +for /F "usebackq tokens=3" %%i in (`findstr/C:"#define SIM_PATCH" ..\sim_rev.h`) do set _SIM_PATCH=-%%i +for /F "usebackq tokens=3" %%i in (`findstr/C:"#define SIM_VERSION_MODE" ..\sim_rev.h`) do set _SIM_VERSION_MODE=-%%~i +if "%_SIM_PATCH%" equ "-0" set _SIM_PATCH= +set _ZipName=simh-%_SIM_MAJOR%.%_SIM_MINOR%%_SIM_PATCH%%_SIM_VERSION_MODE%--%D_YYYY%-%D_MM%-%D_DD%-%GIT_COMMIT_ID:~0,8%.zip +set _ZipPath=..\..\%BIN_REPO%\ +vcbuild Simh.sln "Release|Win32" +if exist "%ProgramFiles%\7-Zip\7z.exe" "%ProgramFiles%\7-Zip\7z.exe" a -tzip "%_ZipPath%%_ZipName%" "..\BIN\NT\Win32-Release\*.exe" +if exist "%ProgramFiles(x86)%\7-Zip\7z.exe" "%ProgramFiles(x86)%\7-Zip\7z.exe" a -tzip "%_ZipPath%%_ZipName%" "..\BIN\NT\Win32-Release\*.exe" +if exist "%PROGRAMW6432%\7-Zip\7z.exe" "%PROGRAMW6432%\7-Zip\7z.exe" a -tzip "%_ZipPath%%_ZipName%" "..\BIN\NT\Win32-Release\*.exe" + +pushd %_ZipPath% +where git.exe >NUL +if %ERRORLEVEL% equ 0 goto GitOK +if exist "%ProgramFiles%\Git\bin\git.exe" path %USERPROFILE%\bin;%ProgramFiles%\Git\local\bin;%ProgramFiles%\Git\mingw\bin;%ProgramFiles%\Git\bin\;%Path% +if exist "%ProgramFiles(x86)%\Git\bin\git.exe" path %USERPROFILE%\bin;%ProgramFiles(x86)%\Git\local\bin;%ProgramFiles(x86)%\Git\mingw\bin;%ProgramFiles(x86)%\Git\bin\;%Path% +:GitOK +if "%1" neq "reset" goto GitAddNew +:GitSetup +if exist .git rmdir/s .git +git init +git add README.md +git commit -m "Initializing the Windows Binary repository" +git remote add origin git@github.com:simh/%BIN_REPO%.git +git branch -m master %BIN_REPO% +git push -u origin %BIN_REPO% + +:GitAddNew +git add %_ZipName% +git commit -m "Build results on %D_YYYY%-%D_MM%-%D_DD% for Commit Id %GIT_COMMIT_ID%" +git push -u origin %BIN_REPO% + +popd \ No newline at end of file diff --git a/Visual Studio Projects/BuildROMs.vcproj b/Visual Studio Projects/BuildROMs.vcproj index 570688c6..684766a5 100644 --- a/Visual Studio Projects/BuildROMs.vcproj +++ b/Visual Studio Projects/BuildROMs.vcproj @@ -50,7 +50,7 @@ UsePrecompiledHeader="0" WarningLevel="3" Detect64BitPortabilityProblems="false" - DebugInformationFormat="4" + DebugInformationFormat="3" /> + + @@ -249,6 +257,10 @@ RelativePath="..\sim_fio.c" > + + @@ -282,6 +294,10 @@ RelativePath="..\sim_defs.h" > + + @@ -294,6 +310,10 @@ RelativePath="..\sim_rev.h" > + + diff --git a/Visual Studio Projects/GRI.vcproj b/Visual Studio Projects/GRI.vcproj index 3f88b5bb..bb972b53 100644 --- a/Visual Studio Projects/GRI.vcproj +++ b/Visual Studio Projects/GRI.vcproj @@ -26,6 +26,8 @@ > + + @@ -213,6 +221,10 @@ RelativePath="..\sim_fio.c" > + + @@ -250,6 +262,10 @@ RelativePath="..\sim_defs.h" > + + @@ -262,6 +278,10 @@ RelativePath="..\sim_rev.h" > + + diff --git a/Visual Studio Projects/H316.vcproj b/Visual Studio Projects/H316.vcproj index 8bd7530e..19502723 100644 --- a/Visual Studio Projects/H316.vcproj +++ b/Visual Studio Projects/H316.vcproj @@ -26,6 +26,8 @@ > + + @@ -229,6 +237,10 @@ RelativePath="..\sim_fio.c" > + + @@ -266,6 +278,10 @@ RelativePath="..\sim_defs.h" > + + @@ -278,6 +294,10 @@ RelativePath="..\sim_rev.h" > + + diff --git a/Visual Studio Projects/HP2100.vcproj b/Visual Studio Projects/HP2100.vcproj index 2978e132..b7247a88 100644 --- a/Visual Studio Projects/HP2100.vcproj +++ b/Visual Studio Projects/HP2100.vcproj @@ -26,6 +26,8 @@ > + + @@ -317,6 +325,10 @@ RelativePath="..\sim_fio.c" > + + @@ -378,6 +390,10 @@ RelativePath="..\sim_defs.h" > + + @@ -390,6 +406,10 @@ RelativePath="..\sim_rev.h" > + + diff --git a/Visual Studio Projects/I1401.vcproj b/Visual Studio Projects/I1401.vcproj index e9b6d64e..38cd9bc2 100644 --- a/Visual Studio Projects/I1401.vcproj +++ b/Visual Studio Projects/I1401.vcproj @@ -26,6 +26,8 @@ > + + @@ -229,6 +237,10 @@ RelativePath="..\sim_fio.c" > + + @@ -270,6 +282,10 @@ RelativePath="..\sim_defs.h" > + + @@ -282,6 +298,10 @@ RelativePath="..\sim_rev.h" > + + diff --git a/Visual Studio Projects/I1620.vcproj b/Visual Studio Projects/I1620.vcproj index 7a3afc53..ad450b41 100644 --- a/Visual Studio Projects/I1620.vcproj +++ b/Visual Studio Projects/I1620.vcproj @@ -26,6 +26,8 @@ > + + @@ -233,6 +241,10 @@ RelativePath="..\sim_fio.c" > + + @@ -270,6 +282,10 @@ RelativePath="..\sim_defs.h" > + + @@ -282,6 +298,10 @@ RelativePath="..\sim_rev.h" > + + diff --git a/Visual Studio Projects/I7094.vcproj b/Visual Studio Projects/I7094.vcproj index 6f04a6b1..fb400008 100644 --- a/Visual Studio Projects/I7094.vcproj +++ b/Visual Studio Projects/I7094.vcproj @@ -26,6 +26,8 @@ > + + @@ -249,6 +257,10 @@ RelativePath="..\sim_fio.c" > + + @@ -290,6 +302,10 @@ RelativePath="..\sim_defs.h" > + + @@ -302,6 +318,10 @@ RelativePath="..\sim_rev.h" > + + diff --git a/Visual Studio Projects/IBM1130.vcproj b/Visual Studio Projects/IBM1130.vcproj index 2a116ced..03bf42ac 100644 --- a/Visual Studio Projects/IBM1130.vcproj +++ b/Visual Studio Projects/IBM1130.vcproj @@ -26,6 +26,8 @@ > + + @@ -253,6 +261,10 @@ RelativePath="..\sim_fio.c" > + + @@ -314,6 +326,10 @@ RelativePath="..\sim_defs.h" > + + @@ -326,6 +342,10 @@ RelativePath="..\sim_rev.h" > + + diff --git a/Visual Studio Projects/ID16.vcproj b/Visual Studio Projects/ID16.vcproj index 0c50ccc7..f528fe41 100644 --- a/Visual Studio Projects/ID16.vcproj +++ b/Visual Studio Projects/ID16.vcproj @@ -26,6 +26,8 @@ > + + @@ -261,6 +269,10 @@ RelativePath="..\sim_fio.c" > + + @@ -298,6 +310,10 @@ RelativePath="..\sim_defs.h" > + + @@ -310,6 +326,10 @@ RelativePath="..\sim_rev.h" > + + diff --git a/Visual Studio Projects/ID32.vcproj b/Visual Studio Projects/ID32.vcproj index 9474205e..0f67a5ee 100644 --- a/Visual Studio Projects/ID32.vcproj +++ b/Visual Studio Projects/ID32.vcproj @@ -26,6 +26,8 @@ > + + @@ -261,6 +269,10 @@ RelativePath="..\sim_fio.c" > + + @@ -298,6 +310,10 @@ RelativePath="..\sim_defs.h" > + + @@ -310,6 +326,10 @@ RelativePath="..\sim_rev.h" > + + diff --git a/Visual Studio Projects/NOVA.vcproj b/Visual Studio Projects/NOVA.vcproj index ed896b38..2a387fac 100644 --- a/Visual Studio Projects/NOVA.vcproj +++ b/Visual Studio Projects/NOVA.vcproj @@ -26,6 +26,8 @@ > + + @@ -249,6 +257,10 @@ RelativePath="..\sim_fio.c" > + + @@ -286,6 +298,10 @@ RelativePath="..\sim_defs.h" > + + @@ -298,6 +314,10 @@ RelativePath="..\sim_rev.h" > + + diff --git a/Visual Studio Projects/PDP1.vcproj b/Visual Studio Projects/PDP1.vcproj index d367998d..27d85816 100644 --- a/Visual Studio Projects/PDP1.vcproj +++ b/Visual Studio Projects/PDP1.vcproj @@ -26,6 +26,8 @@ > + + @@ -233,6 +241,10 @@ RelativePath="..\sim_fio.c" > + + @@ -270,6 +282,10 @@ RelativePath="..\sim_defs.h" > + + @@ -282,6 +298,10 @@ RelativePath="..\sim_rev.h" > + + diff --git a/Visual Studio Projects/PDP10.vcproj b/Visual Studio Projects/PDP10.vcproj index 36c52831..d224e9e0 100644 --- a/Visual Studio Projects/PDP10.vcproj +++ b/Visual Studio Projects/PDP10.vcproj @@ -26,6 +26,8 @@ > - - @@ -259,6 +259,10 @@ RelativePath="..\sim_console.c" > + + @@ -267,6 +271,10 @@ RelativePath="..\sim_fio.c" > + + @@ -304,6 +312,10 @@ RelativePath="..\sim_defs.h" > + + @@ -316,6 +328,10 @@ RelativePath="..\sim_rev.h" > + + diff --git a/Visual Studio Projects/PDP11.vcproj b/Visual Studio Projects/PDP11.vcproj index fc4f4b67..51559527 100644 --- a/Visual Studio Projects/PDP11.vcproj +++ b/Visual Studio Projects/PDP11.vcproj @@ -26,8 +26,8 @@ > + + @@ -375,6 +379,10 @@ RelativePath="..\sim_fio.c" > + + @@ -396,10 +404,6 @@ Name="Header Files" Filter="h;hpp;hxx;hm;inl;inc" > - - @@ -412,6 +416,10 @@ RelativePath="..\PDP11\pdp11_defs.h" > + + @@ -464,6 +472,10 @@ RelativePath="..\sim_rev.h" > + + diff --git a/Visual Studio Projects/PDP15.vcproj b/Visual Studio Projects/PDP15.vcproj index 8241c99f..937f5710 100644 --- a/Visual Studio Projects/PDP15.vcproj +++ b/Visual Studio Projects/PDP15.vcproj @@ -26,6 +26,8 @@ > + + @@ -245,6 +253,10 @@ RelativePath="..\sim_fio.c" > + + @@ -282,6 +294,10 @@ RelativePath="..\sim_defs.h" > + + @@ -294,6 +310,10 @@ RelativePath="..\sim_rev.h" > + + diff --git a/Visual Studio Projects/PDP4.vcproj b/Visual Studio Projects/PDP4.vcproj index b7049eca..3f3a737f 100644 --- a/Visual Studio Projects/PDP4.vcproj +++ b/Visual Studio Projects/PDP4.vcproj @@ -26,6 +26,8 @@ > + + @@ -245,6 +253,10 @@ RelativePath="..\sim_fio.c" > + + @@ -282,6 +294,10 @@ RelativePath="..\sim_defs.h" > + + @@ -294,6 +310,10 @@ RelativePath="..\sim_rev.h" > + + diff --git a/Visual Studio Projects/PDP7.vcproj b/Visual Studio Projects/PDP7.vcproj index 0364ef2e..11a5fd10 100644 --- a/Visual Studio Projects/PDP7.vcproj +++ b/Visual Studio Projects/PDP7.vcproj @@ -26,6 +26,8 @@ > + + @@ -245,6 +253,10 @@ RelativePath="..\sim_fio.c" > + + @@ -282,6 +294,10 @@ RelativePath="..\sim_defs.h" > + + @@ -294,6 +310,10 @@ RelativePath="..\sim_rev.h" > + + diff --git a/Visual Studio Projects/PDP8.vcproj b/Visual Studio Projects/PDP8.vcproj index a71bbc0a..78b71892 100644 --- a/Visual Studio Projects/PDP8.vcproj +++ b/Visual Studio Projects/PDP8.vcproj @@ -26,6 +26,8 @@ > + + @@ -273,6 +281,10 @@ RelativePath="..\sim_fio.c" > + + @@ -310,6 +322,10 @@ RelativePath="..\sim_defs.h" > + + @@ -322,6 +338,10 @@ RelativePath="..\sim_rev.h" > + + diff --git a/Visual Studio Projects/PDP9.vcproj b/Visual Studio Projects/PDP9.vcproj index 781b2de3..92984a13 100644 --- a/Visual Studio Projects/PDP9.vcproj +++ b/Visual Studio Projects/PDP9.vcproj @@ -26,6 +26,8 @@ > + + @@ -249,6 +257,10 @@ RelativePath="..\sim_fio.c" > + + @@ -286,6 +298,10 @@ RelativePath="..\sim_defs.h" > + + @@ -298,6 +314,10 @@ RelativePath="..\sim_rev.h" > + + diff --git a/Visual Studio Projects/S3.vcproj b/Visual Studio Projects/S3.vcproj index 752d9fba..67fee35a 100644 --- a/Visual Studio Projects/S3.vcproj +++ b/Visual Studio Projects/S3.vcproj @@ -26,6 +26,8 @@ > + + @@ -225,6 +233,10 @@ RelativePath="..\sim_fio.c" > + + @@ -262,6 +274,10 @@ RelativePath="..\sim_defs.h" > + + @@ -274,6 +290,10 @@ RelativePath="..\sim_rev.h" > + + diff --git a/Visual Studio Projects/SDS.vcproj b/Visual Studio Projects/SDS.vcproj index c15a9b5c..4c4d8174 100644 --- a/Visual Studio Projects/SDS.vcproj +++ b/Visual Studio Projects/SDS.vcproj @@ -26,6 +26,8 @@ > + + @@ -241,6 +249,10 @@ RelativePath="..\sim_fio.c" > + + @@ -278,6 +290,10 @@ RelativePath="..\sim_defs.h" > + + @@ -290,6 +306,10 @@ RelativePath="..\sim_rev.h" > + + diff --git a/Visual Studio Projects/Simh.sln b/Visual Studio Projects/Simh.sln index af35fd58..05265482 100644 --- a/Visual Studio Projects/Simh.sln +++ b/Visual Studio Projects/Simh.sln @@ -65,6 +65,38 @@ Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "swtp6800mp-a2", "swtp6800mp EndProject Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "BuildROMs", "BuildROMs.vcproj", "{D40F3AF1-EEE7-4432-9807-2AD287B490F8}" EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "VAX730", "VAX730.vcproj", "{C526F7F2-9476-44BC-B1E9-9522B693BEA7}" + ProjectSection(ProjectDependencies) = postProject + {D40F3AF1-EEE7-4432-9807-2AD287B490F8} = {D40F3AF1-EEE7-4432-9807-2AD287B490F8} + EndProjectSection +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "VAX750", "VAX750.vcproj", "{43A9CF64-5705-4FB7-B837-ED9AAFF97DAC}" + ProjectSection(ProjectDependencies) = postProject + {D40F3AF1-EEE7-4432-9807-2AD287B490F8} = {D40F3AF1-EEE7-4432-9807-2AD287B490F8} + EndProjectSection +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "VAX610", "VAX610.vcproj", "{B3671ABB-4FFF-4EEB-8A5B-06716C9BCE9E}" + ProjectSection(ProjectDependencies) = postProject + {D40F3AF1-EEE7-4432-9807-2AD287B490F8} = {D40F3AF1-EEE7-4432-9807-2AD287B490F8} + EndProjectSection +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "VAX620", "VAX620.vcproj", "{E359921B-DC18-42ED-AFB9-1FC603B9C1B3}" + ProjectSection(ProjectDependencies) = postProject + {D40F3AF1-EEE7-4432-9807-2AD287B490F8} = {D40F3AF1-EEE7-4432-9807-2AD287B490F8} + EndProjectSection +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "VAX630", "VAX630.vcproj", "{3048F582-98C9-447D-BBB9-6F969467D4EA}" + ProjectSection(ProjectDependencies) = postProject + {D40F3AF1-EEE7-4432-9807-2AD287B490F8} = {D40F3AF1-EEE7-4432-9807-2AD287B490F8} + EndProjectSection +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "TX-0", "TX-0.vcproj", "{24BC7F75-FB56-44A9-BB7C-78AE6A694D0C}" +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "VAX860", "VAX860.vcproj", "{F5C22D72-460E-43CD-9AC6-6D6AC517BD1F}" + ProjectSection(ProjectDependencies) = postProject + {D40F3AF1-EEE7-4432-9807-2AD287B490F8} = {D40F3AF1-EEE7-4432-9807-2AD287B490F8} + EndProjectSection +EndProject Global GlobalSection(SolutionConfigurationPlatforms) = preSolution Debug|Win32 = Debug|Win32 @@ -187,6 +219,34 @@ Global {D40F3AF1-EEE7-4432-9807-2AD287B490F8}.Debug|Win32.Build.0 = Debug|Win32 {D40F3AF1-EEE7-4432-9807-2AD287B490F8}.Release|Win32.ActiveCfg = Release|Win32 {D40F3AF1-EEE7-4432-9807-2AD287B490F8}.Release|Win32.Build.0 = Release|Win32 + {C526F7F2-9476-44BC-B1E9-9522B693BEA7}.Debug|Win32.ActiveCfg = Debug|Win32 + {C526F7F2-9476-44BC-B1E9-9522B693BEA7}.Debug|Win32.Build.0 = Debug|Win32 + {C526F7F2-9476-44BC-B1E9-9522B693BEA7}.Release|Win32.ActiveCfg = Release|Win32 + {C526F7F2-9476-44BC-B1E9-9522B693BEA7}.Release|Win32.Build.0 = Release|Win32 + {43A9CF64-5705-4FB7-B837-ED9AAFF97DAC}.Debug|Win32.ActiveCfg = Debug|Win32 + {43A9CF64-5705-4FB7-B837-ED9AAFF97DAC}.Debug|Win32.Build.0 = Debug|Win32 + {43A9CF64-5705-4FB7-B837-ED9AAFF97DAC}.Release|Win32.ActiveCfg = Release|Win32 + {43A9CF64-5705-4FB7-B837-ED9AAFF97DAC}.Release|Win32.Build.0 = Release|Win32 + {B3671ABB-4FFF-4EEB-8A5B-06716C9BCE9E}.Debug|Win32.ActiveCfg = Debug|Win32 + {B3671ABB-4FFF-4EEB-8A5B-06716C9BCE9E}.Debug|Win32.Build.0 = Debug|Win32 + {B3671ABB-4FFF-4EEB-8A5B-06716C9BCE9E}.Release|Win32.ActiveCfg = Release|Win32 + {B3671ABB-4FFF-4EEB-8A5B-06716C9BCE9E}.Release|Win32.Build.0 = Release|Win32 + {E359921B-DC18-42ED-AFB9-1FC603B9C1B3}.Debug|Win32.ActiveCfg = Debug|Win32 + {E359921B-DC18-42ED-AFB9-1FC603B9C1B3}.Debug|Win32.Build.0 = Debug|Win32 + {E359921B-DC18-42ED-AFB9-1FC603B9C1B3}.Release|Win32.ActiveCfg = Release|Win32 + {E359921B-DC18-42ED-AFB9-1FC603B9C1B3}.Release|Win32.Build.0 = Release|Win32 + {3048F582-98C9-447D-BBB9-6F969467D4EA}.Debug|Win32.ActiveCfg = Debug|Win32 + {3048F582-98C9-447D-BBB9-6F969467D4EA}.Debug|Win32.Build.0 = Debug|Win32 + {3048F582-98C9-447D-BBB9-6F969467D4EA}.Release|Win32.ActiveCfg = Release|Win32 + {3048F582-98C9-447D-BBB9-6F969467D4EA}.Release|Win32.Build.0 = Release|Win32 + {24BC7F75-FB56-44A9-BB7C-78AE6A694D0C}.Debug|Win32.ActiveCfg = Debug|Win32 + {24BC7F75-FB56-44A9-BB7C-78AE6A694D0C}.Debug|Win32.Build.0 = Debug|Win32 + {24BC7F75-FB56-44A9-BB7C-78AE6A694D0C}.Release|Win32.ActiveCfg = Release|Win32 + {24BC7F75-FB56-44A9-BB7C-78AE6A694D0C}.Release|Win32.Build.0 = Release|Win32 + {F5C22D72-460E-43CD-9AC6-6D6AC517BD1F}.Debug|Win32.ActiveCfg = Debug|Win32 + {F5C22D72-460E-43CD-9AC6-6D6AC517BD1F}.Debug|Win32.Build.0 = Debug|Win32 + {F5C22D72-460E-43CD-9AC6-6D6AC517BD1F}.Release|Win32.ActiveCfg = Release|Win32 + {F5C22D72-460E-43CD-9AC6-6D6AC517BD1F}.Release|Win32.Build.0 = Release|Win32 EndGlobalSection GlobalSection(SolutionProperties) = preSolution HideSolutionNode = FALSE diff --git a/Visual Studio Projects/TX-0.vcproj b/Visual Studio Projects/TX-0.vcproj new file mode 100644 index 00000000..60ccd0ec --- /dev/null +++ b/Visual Studio Projects/TX-0.vcproj @@ -0,0 +1,324 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Visual Studio Projects/VAX.vcproj b/Visual Studio Projects/VAX.vcproj index 3aaebaa1..9d0626f6 100644 --- a/Visual Studio Projects/VAX.vcproj +++ b/Visual Studio Projects/VAX.vcproj @@ -26,8 +26,8 @@ > + + @@ -288,6 +292,10 @@ RelativePath="..\sim_fio.c" > + + @@ -362,7 +370,7 @@ Filter="h;hpp;hxx;hm;inl;inc" > + + diff --git a/Visual Studio Projects/VAX610.vcproj b/Visual Studio Projects/VAX610.vcproj new file mode 100644 index 00000000..f403c7d3 --- /dev/null +++ b/Visual Studio Projects/VAX610.vcproj @@ -0,0 +1,457 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Visual Studio Projects/VAX620.vcproj b/Visual Studio Projects/VAX620.vcproj new file mode 100644 index 00000000..f6bf62d3 --- /dev/null +++ b/Visual Studio Projects/VAX620.vcproj @@ -0,0 +1,469 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Visual Studio Projects/VAX630.vcproj b/Visual Studio Projects/VAX630.vcproj new file mode 100644 index 00000000..74f7d35a --- /dev/null +++ b/Visual Studio Projects/VAX630.vcproj @@ -0,0 +1,469 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Visual Studio Projects/VAX730.vcproj b/Visual Studio Projects/VAX730.vcproj new file mode 100644 index 00000000..312fae18 --- /dev/null +++ b/Visual Studio Projects/VAX730.vcproj @@ -0,0 +1,467 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Visual Studio Projects/VAX750.vcproj b/Visual Studio Projects/VAX750.vcproj new file mode 100644 index 00000000..df1cc0ae --- /dev/null +++ b/Visual Studio Projects/VAX750.vcproj @@ -0,0 +1,475 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Visual Studio Projects/VAX780.vcproj b/Visual Studio Projects/VAX780.vcproj index 52c14deb..0b1f2fcd 100644 --- a/Visual Studio Projects/VAX780.vcproj +++ b/Visual Studio Projects/VAX780.vcproj @@ -26,8 +26,8 @@ > + + @@ -302,6 +306,10 @@ RelativePath="..\sim_fio.c" > + + @@ -322,10 +330,6 @@ RelativePath="..\VAX\vax780_fload.c" > - - @@ -346,6 +350,10 @@ RelativePath="..\VAX\vax780_uba.c" > + + @@ -388,7 +396,7 @@ Filter="h;hpp;hxx;hm;inl;inc" > + + @@ -459,10 +471,6 @@ RelativePath="..\VAX\vax_defs.h" > - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Visual Studio Projects/lgp.vcproj b/Visual Studio Projects/lgp.vcproj index 67701a97..62d2c8ac 100644 --- a/Visual Studio Projects/lgp.vcproj +++ b/Visual Studio Projects/lgp.vcproj @@ -26,6 +26,8 @@ > + + @@ -213,6 +221,10 @@ RelativePath="..\sim_fio.c" > + + @@ -250,6 +262,10 @@ RelativePath="..\sim_defs.h" > + + @@ -262,6 +278,10 @@ RelativePath="..\sim_rev.h" > + + diff --git a/Visual Studio Projects/swtp6800mp-a.vcproj b/Visual Studio Projects/swtp6800mp-a.vcproj index bf86be0d..8cf1edd1 100644 --- a/Visual Studio Projects/swtp6800mp-a.vcproj +++ b/Visual Studio Projects/swtp6800mp-a.vcproj @@ -26,6 +26,8 @@ > + + @@ -237,6 +245,14 @@ RelativePath="..\sim_fio.c" > + + + + @@ -270,6 +286,10 @@ RelativePath="..\sim_defs.h" > + + @@ -282,6 +302,10 @@ RelativePath="..\sim_rev.h" > + + diff --git a/Visual Studio Projects/swtp6800mp-a2.vcproj b/Visual Studio Projects/swtp6800mp-a2.vcproj index b3230803..486553e5 100644 --- a/Visual Studio Projects/swtp6800mp-a2.vcproj +++ b/Visual Studio Projects/swtp6800mp-a2.vcproj @@ -26,6 +26,8 @@ > + + @@ -241,6 +249,10 @@ RelativePath="..\sim_fio.c" > + + @@ -274,6 +286,10 @@ RelativePath="..\sim_defs.h" > + + @@ -286,6 +302,10 @@ RelativePath="..\sim_rev.h" > + + diff --git a/alpha/alpha_cpu.c b/alpha/alpha_cpu.c index 7cacf0ea..e531bb24 100644 --- a/alpha/alpha_cpu.c +++ b/alpha/alpha_cpu.c @@ -193,11 +193,6 @@ const t_uint64 word_mask[4] = { 0x0000FFFF00000000, 0xFFFF000000000000 }; -extern int32 sim_interval; -extern int32 sim_int_char; -extern FILE *sim_deb; -extern uint32 sim_brk_types, sim_brk_dflt, sim_brk_summ; /* breakpoint info */ - t_uint64 uemul64 (t_uint64 a, t_uint64 b, t_uint64 *hi); t_uint64 byte_zap (t_uint64 op, uint32 mask); t_stat cpu_reset (DEVICE *dptr); @@ -1789,8 +1784,6 @@ t_stat cpu_fprint_one_inst (FILE *st, uint32 ir, t_uint64 pc, t_uint64 ra, t_uin { uint32 op; t_value sim_val; -extern t_stat fprint_sym (FILE *ofile, t_addr addr, t_value *val, - UNIT *uptr, int32 sw); static const h_fmt[64] = { 0, 0, 0, 0, 0, 0, 0, 0, diff --git a/alpha/alpha_io.c b/alpha/alpha_io.c index aa021d41..6762cea1 100644 --- a/alpha/alpha_io.c +++ b/alpha/alpha_io.c @@ -31,8 +31,6 @@ t_uint64 *rom = NULL; /* boot ROM */ -extern DEVICE *sim_devices[]; - t_bool rom_rd (t_uint64 pa, t_uint64 *val, uint32 lnt); t_bool rom_wr (t_uint64 pa, t_uint64 val, uint32 lnt); t_stat rom_ex (t_value *vptr, t_addr exta, UNIT *uptr, int32 sw); diff --git a/build_mingw.bat b/build_mingw.bat index ff738d41..a87e8c0d 100644 --- a/build_mingw.bat +++ b/build_mingw.bat @@ -17,4 +17,4 @@ if ERRORLEVEL 1 path C:\MinGW\bin;%path% if not exist BIN mkdir BIN gcc -v 1>NUL 2>NUL if ERRORLEVEL 1 echo "MinGW Environment Unavailable" -mingw32-make WIN32=1 -f makefile %1 %2 %3 %4 +mingw32-make WIN32=1 -f makefile %* diff --git a/build_mingw_ether.bat b/build_mingw_ether.bat index 51ec0bfd..e50f29fd 100644 --- a/build_mingw_ether.bat +++ b/build_mingw_ether.bat @@ -13,4 +13,4 @@ if ERRORLEVEL 1 path C:\MinGW\bin;%path% if not exist BIN mkdir BIN gcc -v 1>NUL 2>NUL if ERRORLEVEL 1 echo "MinGW Environment Unavailable" -mingw32-make WIN32=1 USE_NETWORK=1 -f makefile %1 %2 %3 %4 +mingw32-make WIN32=1 USE_NETWORK=1 -f makefile %* diff --git a/build_mingw_noasync.bat b/build_mingw_noasync.bat index 04f4a19f..a53eab53 100644 --- a/build_mingw_noasync.bat +++ b/build_mingw_noasync.bat @@ -12,4 +12,4 @@ if ERRORLEVEL 1 path C:\MinGW\bin;%path% if not exist BIN mkdir BIN gcc -v 1>NUL 2>NUL if ERRORLEVEL 1 echo "MinGW Environment Unavailable" -mingw32-make WIN32=1 NOASYNCH=1 -f makefile %1 %2 %3 %4 +mingw32-make WIN32=1 NOASYNCH=1 -f makefile %* diff --git a/descrip.mms b/descrip.mms index 9a5414b1..68282a3f 100644 --- a/descrip.mms +++ b/descrip.mms @@ -3,6 +3,7 @@ # Modified By: Mark Pizzolato / mark@infocomm.com # Norman Lastovica / norman.lastovica@oracle.com # Camiel Vanderhoeven / camiel@camicom.com +# Matt Burke / scope.matthew@btinternet.com # # This MMS/MMK build script is used to compile the various simulators in # the SIMH package for OpenVMS using DEC C v6.0-001(AXP), v6.5-001(AXP), @@ -41,7 +42,13 @@ # SWTP6800MP-A Just Build The SWTP6800MP-A. # SWTP6800MP-A2 Just Build The SWTP6800MP-A2. # VAX Just Build The DEC VAX. +# VAX610 Just Build The DEC VAX610 (MicroVAX I). +# VAX620 Just Build The DEC VAX610 (rtVAX 1000). +# VAX630 Just Build The DEC VAX610 (MicroVAX II). +# VAX730 Just Build The DEC VAX730. +# VAX750 Just Build The DEC VAX750. # VAX780 Just Build The DEC VAX780. +# VAX860 Just Build The DEC VAX860. # CLEAN Will Clean Files Back To Base Kit. # # To build with debugging enabled (which will also enable traceback @@ -187,10 +194,12 @@ BLD_DIR = SYS$DISK:[.BIN.VMS.LIB.BLD-$(ARCH)] # SIMH_DIR = SYS$DISK:[] SIMH_LIB = $(LIB_DIR)SIMH-$(ARCH).OLB +SIMH_NONET_LIB = $(LIB_DIR)SIMH-NONET-$(ARCH).OLB SIMH_SOURCE = $(SIMH_DIR)SIM_CONSOLE.C,$(SIMH_DIR)SIM_SOCK.C,\ $(SIMH_DIR)SIM_TMXR.C,$(SIMH_DIR)SIM_ETHER.C,\ $(SIMH_DIR)SIM_TAPE.C,$(SIMH_DIR)SIM_FIO.C,\ - $(SIMH_DIR)SIM_TIMER.C,$(SIMH_DIR)SIM_DISK.C + $(SIMH_DIR)SIM_TIMER.C,$(SIMH_DIR)SIM_DISK.C,\ + $(SIMH_DIR)SIM_SERIAL.C SIMH_MAIN = SCP.C .IFDEF ALPHA_OR_IA64 SIMH_LIB64 = $(LIB_DIR)SIMH64-$(ARCH).OLB @@ -522,7 +531,8 @@ PDP11_SOURCE1 = $(PDP11_DIR)PDP11_FP.C,$(PDP11_DIR)PDP11_CPU.C,\ $(PDP11_DIR)PDP11_RX.C,$(PDP11_DIR)PDP11_STDDEV.C,\ $(PDP11_DIR)PDP11_SYS.C,$(PDP11_DIR)PDP11_TC.C, \ $(PDP11_DIR)PDP11_CPUMOD.C,$(PDP11_DIR)PDP11_CR.C,\ - $(PDP11_DIR)PDP11_TA.C,$(PDP11_DIR)PDP11_IO_LIB.C + $(PDP11_DIR)PDP11_TA.C,$(PDP11_DIR)PDP11_DMC.C,\ + $(PDP11_DIR)PDP11_IO_LIB.C PDP11_LIB2 = $(LIB_DIR)PDP11L2-$(ARCH).OLB PDP11_SOURCE2 = $(PDP11_DIR)PDP11_TM.C,$(PDP11_DIR)PDP11_TS.C,\ $(PDP11_DIR)PDP11_IO.C,$(PDP11_DIR)PDP11_RQ.C,\ @@ -549,7 +559,8 @@ PDP10_SOURCE = $(PDP10_DIR)PDP10_FE.C,\ $(PDP10_DIR)PDP10_RP.C,$(PDP10_DIR)PDP10_SYS.C,\ $(PDP10_DIR)PDP10_TIM.C,$(PDP10_DIR)PDP10_TU.C,\ $(PDP11_DIR)PDP11_PT.C,$(PDP11_DIR)PDP11_DZ.C,\ - $(PDP11_DIR)PDP11_RY.C,$(PDP11_DIR)PDP11_CR.C + $(PDP11_DIR)PDP11_RY.C,$(PDP11_DIR)PDP11_CR.C,\ + $(PDP11_DIR)PDP11_DMC.C PDP10_OPTIONS = /INCL=($(SIMH_DIR),$(PDP10_DIR),$(PDP11_DIR))\ /DEF=($(CC_DEFS),"USE_INT64=1","VM_PDP10=1"$(PCAP_DEFS)) @@ -598,7 +609,7 @@ SWTP6800MP_A2_SOURCE = $(SWTP6800MP_A2_COMMON)mp-a2.c,$(SWTP6800MP_A2_COMMON)m68 SWTP6800MP_A2_OPTIONS = /INCL=($(SIMH_DIR),$(SWTP6800MP_A2_DIR))/DEF=($(CC_DEFS)) # -# Digital Equipment VAX Simulator Definitions. +# Digital Equipment VAX 3900 Simulator Definitions. # VAX_DIR = SYS$DISK:[.VAX] VAX_LIB1 = $(LIB_DIR)VAXL1-$(ARCH).OLB @@ -615,7 +626,8 @@ VAX_SOURCE2 = $(PDP11_DIR)PDP11_IO_LIB.C,\ $(PDP11_DIR)PDP11_TS.C,$(PDP11_DIR)PDP11_DZ.C,\ $(PDP11_DIR)PDP11_LP.C,$(PDP11_DIR)PDP11_TQ.C,\ $(PDP11_DIR)PDP11_XQ.C,$(PDP11_DIR)PDP11_CR.C,\ - $(PDP11_DIR)PDP11_RY.C,$(PDP11_DIR)PDP11_VH.C + $(PDP11_DIR)PDP11_RY.C,$(PDP11_DIR)PDP11_VH.C,\ + $(PDP11_DIR)PDP11_DMC.C .IFDEF ALPHA_OR_IA64 VAX_OPTIONS = /INCL=($(SIMH_DIR),$(VAX_DIR),$(PDP11_DIR)$(PCAP_INC))\ /DEF=($(CC_DEFS),"VM_VAX=1","USE_ADDR64=1","USE_INT64=1"$(PCAP_DEFS)) @@ -626,6 +638,151 @@ VAX_OPTIONS = /INCL=($(SIMH_DIR),$(VAX_DIR),$(PDP11_DIR)$(PCAP_INC))\ VAX_SIMH_LIB = $(SIMH_LIB) .ENDIF +# Digital Equipment VAX610 (MicroVAX I) Simulator Definitions. +# +VAX610_DIR = SYS$DISK:[.VAX] +VAX610_LIB1 = $(LIB_DIR)VAX610L1-$(ARCH).OLB +VAX610_SOURCE1 = $(VAX610_DIR)VAX_CPU.C,$(VAX610_DIR)VAX_CPU1.C,\ + $(VAX610_DIR)VAX_FPA.C,$(VAX610_DIR)VAX_CIS.C,\ + $(VAX610_DIR)VAX_OCTA.C,$(VAX610_DIR)VAX_CMODE.C,\ + $(VAX610_DIR)VAX_MMU.C,$(VAX610_DIR)VAX_SYS.C,\ + $(VAX610_DIR)VAX_SYSCM.C,$(VAX610_DIR)VAX610_STDDEV.C,\ + $(VAX610_DIR)VAX610_MEM.C,$(VAX610_DIR)VAX610_SYSDEV.C,\ + $(VAX610_DIR)VAX610_IO.C,$(VAX610_DIR)VAX610_SYSLIST.C +VAX610_LIB2 = $(LIB_DIR)VAX610L2-$(ARCH).OLB +VAX610_SOURCE2 = $(PDP11_DIR)PDP11_IO_LIB.C,\ + $(PDP11_DIR)PDP11_RL.C,$(PDP11_DIR)PDP11_RQ.C,\ + $(PDP11_DIR)PDP11_TS.C,$(PDP11_DIR)PDP11_DZ.C,\ + $(PDP11_DIR)PDP11_LP.C,$(PDP11_DIR)PDP11_TQ.C,\ + $(PDP11_DIR)PDP11_XQ.C,$(PDP11_DIR)PDP11_CR.C,\ + $(PDP11_DIR)PDP11_RY.C,$(PDP11_DIR)PDP11_VH.C +.IFDEF ALPHA_OR_IA64 +VAX610_OPTIONS = /INCL=($(SIMH_DIR),$(VAX610_DIR),$(PDP11_DIR)$(PCAP_INC))\ + /DEF=($(CC_DEFS),"VM_VAX=1","USE_ADDR64=1","USE_INT64=1"$(PCAP_DEFS),"VAX_610=1") +VAX610_SIMH_LIB = $(SIMH_LIB64) +.ELSE +VAX610_OPTIONS = /INCL=($(SIMH_DIR),$(VAX610_DIR),$(PDP11_DIR)$(PCAP_INC))\ + /DEF=($(CC_DEFS),"VM_VAX=1"$(PCAP_DEFS),"VAX_610=1") +VAX610_SIMH_LIB = $(SIMH_LIB) +.ENDIF + +# Digital Equipment VAX630 (MicroVAX II) Simulator Definitions. +# +VAX630_DIR = SYS$DISK:[.VAX] +VAX630_LIB1 = $(LIB_DIR)VAX630L1-$(ARCH).OLB +VAX630_SOURCE1 = $(VAX630_DIR)VAX_CPU.C,$(VAX630_DIR)VAX_CPU1.C,\ + $(VAX630_DIR)VAX_FPA.C,$(VAX630_DIR)VAX_CIS.C,\ + $(VAX630_DIR)VAX_OCTA.C,$(VAX630_DIR)VAX_CMODE.C,\ + $(VAX630_DIR)VAX_MMU.C,$(VAX630_DIR)VAX_SYS.C,\ + $(VAX630_DIR)VAX_SYSCM.C,$(VAX630_DIR)VAX_WATCH.C,\ + $(VAX630_DIR)VAX630_STDDEV.C,$(VAX630_DIR)VAX630_SYSDEV.C,\ + $(VAX630_DIR)VAX630_IO.C,$(VAX630_DIR)VAX630_SYSLIST.C +VAX630_LIB2 = $(LIB_DIR)VAX630L2-$(ARCH).OLB +VAX630_SOURCE2 = $(PDP11_DIR)PDP11_IO_LIB.C,\ + $(PDP11_DIR)PDP11_RL.C,$(PDP11_DIR)PDP11_RQ.C,\ + $(PDP11_DIR)PDP11_TS.C,$(PDP11_DIR)PDP11_DZ.C,\ + $(PDP11_DIR)PDP11_LP.C,$(PDP11_DIR)PDP11_TQ.C,\ + $(PDP11_DIR)PDP11_XQ.C,$(PDP11_DIR)PDP11_CR.C,\ + $(PDP11_DIR)PDP11_RY.C,$(PDP11_DIR)PDP11_VH.C +.IFDEF ALPHA_OR_IA64 +VAX630_OPTIONS = /INCL=($(SIMH_DIR),$(VAX630_DIR),$(PDP11_DIR)$(PCAP_INC))\ + /DEF=($(CC_DEFS),"VM_VAX=1","USE_ADDR64=1","USE_INT64=1"$(PCAP_DEFS),"VAX_630=1") +VAX630_SIMH_LIB = $(SIMH_LIB64) +.ELSE +VAX630_OPTIONS = /INCL=($(SIMH_DIR),$(VAX630_DIR),$(PDP11_DIR)$(PCAP_INC))\ + /DEF=($(CC_DEFS),"VM_VAX=1"$(PCAP_DEFS),"VAX_630=1") +VAX630_SIMH_LIB = $(SIMH_LIB) +.ENDIF + +# Digital Equipment VAX620 (rtVAX 1000) Simulator Definitions. +# +VAX620_DIR = SYS$DISK:[.VAX] +VAX620_LIB1 = $(LIB_DIR)VAX620L1-$(ARCH).OLB +VAX620_SOURCE1 = $(VAX620_DIR)VAX_CPU.C,$(VAX620_DIR)VAX_CPU1.C,\ + $(VAX620_DIR)VAX_FPA.C,$(VAX620_DIR)VAX_CIS.C,\ + $(VAX620_DIR)VAX_OCTA.C,$(VAX620_DIR)VAX_CMODE.C,\ + $(VAX620_DIR)VAX_MMU.C,$(VAX620_DIR)VAX_SYS.C,\ + $(VAX620_DIR)VAX_SYSCM.C,$(VAX630_DIR)VAX_WATCH.C,\ + $(VAX620_DIR)VAX630_STDDEV.C,$(VAX620_DIR)VAX630_SYSDEV.C,\ + $(VAX620_DIR)VAX630_IO.C,$(VAX620_DIR)VAX630_SYSLIST.C +VAX620_LIB2 = $(LIB_DIR)VAX620L2-$(ARCH).OLB +VAX620_SOURCE2 = $(PDP11_DIR)PDP11_IO_LIB.C,\ + $(PDP11_DIR)PDP11_RL.C,$(PDP11_DIR)PDP11_RQ.C,\ + $(PDP11_DIR)PDP11_TS.C,$(PDP11_DIR)PDP11_DZ.C,\ + $(PDP11_DIR)PDP11_LP.C,$(PDP11_DIR)PDP11_TQ.C,\ + $(PDP11_DIR)PDP11_XQ.C,$(PDP11_DIR)PDP11_CR.C,\ + $(PDP11_DIR)PDP11_RY.C,$(PDP11_DIR)PDP11_VH.C +.IFDEF ALPHA_OR_IA64 +VAX620_OPTIONS = /INCL=($(SIMH_DIR),$(VAX620_DIR),$(PDP11_DIR)$(PCAP_INC))\ + /DEF=($(CC_DEFS),"VM_VAX=1","USE_ADDR64=1","USE_INT64=1"$(PCAP_DEFS),"VAX_620=1") +VAX620_SIMH_LIB = $(SIMH_LIB64) +.ELSE +VAX620_OPTIONS = /INCL=($(SIMH_DIR),$(VAX620_DIR),$(PDP11_DIR)$(PCAP_INC))\ + /DEF=($(CC_DEFS),"VM_VAX=1"$(PCAP_DEFS),"VAX_620=1") +VAX620_SIMH_LIB = $(SIMH_LIB) +.ENDIF + +# Digital Equipment VAX730 Simulator Definitions. +# +VAX730_DIR = SYS$DISK:[.VAX] +VAX730_LIB1 = $(LIB_DIR)VAX730L1-$(ARCH).OLB +VAX730_SOURCE1 = $(VAX730_DIR)VAX_CPU.C,$(VAX730_DIR)VAX_CPU1.C,\ + $(VAX730_DIR)VAX_FPA.C,$(VAX730_DIR)VAX_CIS.C,\ + $(VAX730_DIR)VAX_OCTA.C,$(VAX730_DIR)VAX_CMODE.C,\ + $(VAX730_DIR)VAX_MMU.C,$(VAX730_DIR)VAX_SYS.C,\ + $(VAX730_DIR)VAX_SYSCM.C,$(VAX730_DIR)VAX730_STDDEV.C,\ + $(VAX730_DIR)VAX730_SYS.C,$(VAX730_DIR)VAX730_MEM.C,\ + $(VAX730_DIR)VAX730_UBA.C,$(VAX730_DIR)VAX730_RB.C,\ + $(VAX730_DIR)VAX730_SYSLIST.C +VAX730_LIB2 = $(LIB_DIR)VAX730L2-$(ARCH).OLB +VAX730_SOURCE2 = $(PDP11_DIR)PDP11_RL.C,$(PDP11_DIR)PDP11_RQ.C,\ + $(PDP11_DIR)PDP11_TS.C,$(PDP11_DIR)PDP11_DZ.C,\ + $(PDP11_DIR)PDP11_LP.C,$(PDP11_DIR)PDP11_TQ.C,\ + $(PDP11_DIR)PDP11_XU.C,$(PDP11_DIR)PDP11_RY.C,\ + $(PDP11_DIR)PDP11_CR.C,$(PDP11_DIR)PDP11_HK.C,\ + $(PDP11_DIR)PDP11_VH.C,$(PDP11_DIR)PDP11_DMC.C,\ + $(PDP11_DIR)PDP11_IO_LIB.C +.IFDEF ALPHA_OR_IA64 +VAX730_OPTIONS = /INCL=($(SIMH_DIR),$(VAX730_DIR),$(PDP11_DIR)$(PCAP_INC))\ + /DEF=($(CC_DEFS),"VM_VAX=1","USE_ADDR64=1","USE_INT64=1"$(PCAP_DEFS),"VAX_730=1") +VAX730_SIMH_LIB = $(SIMH_LIB64) +.ELSE +VAX730_OPTIONS = /INCL=($(SIMH_DIR),$(VAX730_DIR),$(PDP11_DIR)$(PCAP_INC))\ + /DEF=($(CC_DEFS),"VM_VAX=1"$(PCAP_DEFS),"VAX_730=1") +VAX730_SIMH_LIB = $(SIMH_LIB) +.ENDIF + +# Digital Equipment VAX750 Simulator Definitions. +# +VAX750_DIR = SYS$DISK:[.VAX] +VAX750_LIB1 = $(LIB_DIR)VAX750L1-$(ARCH).OLB +VAX750_SOURCE1 = $(VAX750_DIR)VAX_CPU.C,$(VAX750_DIR)VAX_CPU1.C,\ + $(VAX750_DIR)VAX_FPA.C,$(VAX750_DIR)VAX_CIS.C,\ + $(VAX750_DIR)VAX_OCTA.C,$(VAX750_DIR)VAX_CMODE.C,\ + $(VAX750_DIR)VAX_MMU.C,$(VAX750_DIR)VAX_SYS.C,\ + $(VAX750_DIR)VAX_SYSCM.C,$(VAX750_DIR)VAX750_STDDEV.C,\ + $(VAX750_DIR)VAX750_CMI.C,$(VAX750_DIR)VAX750_MEM.C,\ + $(VAX750_DIR)VAX750_UBA.C,$(VAX750_DIR)VAX7X0_MBA.C,\ + $(VAX750_DIR)VAX750_SYSLIST.C +VAX750_LIB2 = $(LIB_DIR)VAX750L2-$(ARCH).OLB +VAX750_SOURCE2 = $(PDP11_DIR)PDP11_RL.C,$(PDP11_DIR)PDP11_RQ.C,\ + $(PDP11_DIR)PDP11_TS.C,$(PDP11_DIR)PDP11_DZ.C,\ + $(PDP11_DIR)PDP11_LP.C,$(PDP11_DIR)PDP11_TQ.C,\ + $(PDP11_DIR)PDP11_XU.C,$(PDP11_DIR)PDP11_RY.C,\ + $(PDP11_DIR)PDP11_CR.C,$(PDP11_DIR)PDP11_HK.C,\ + $(PDP11_DIR)PDP11_RP.C,$(PDP11_DIR)PDP11_TU.C,\ + $(PDP11_DIR)PDP11_VH.C,$(PDP11_DIR)PDP11_DMC.C,\ + $(PDP11_DIR)PDP11_IO_LIB.C +.IFDEF ALPHA_OR_IA64 +VAX750_OPTIONS = /INCL=($(SIMH_DIR),$(VAX750_DIR),$(PDP11_DIR)$(PCAP_INC))\ + /DEF=($(CC_DEFS),"VM_VAX=1","USE_ADDR64=1","USE_INT64=1"$(PCAP_DEFS),"VAX_750=1") +VAX750_SIMH_LIB = $(SIMH_LIB64) +.ELSE +VAX750_OPTIONS = /INCL=($(SIMH_DIR),$(VAX750_DIR),$(PDP11_DIR)$(PCAP_INC))\ + /DEF=($(CC_DEFS),"VM_VAX=1"$(PCAP_DEFS),"VAX_750=1") +VAX750_SIMH_LIB = $(SIMH_LIB) +.ENDIF + # Digital Equipment VAX780 Simulator Definitions. # VAX780_DIR = SYS$DISK:[.VAX] @@ -636,7 +793,7 @@ VAX780_SOURCE1 = $(VAX780_DIR)VAX_CPU.C,$(VAX780_DIR)VAX_CPU1.C,\ $(VAX780_DIR)VAX_MMU.C,$(VAX780_DIR)VAX_SYS.C,\ $(VAX780_DIR)VAX_SYSCM.C,$(VAX780_DIR)VAX780_STDDEV.C,\ $(VAX780_DIR)VAX780_SBI.C,$(VAX780_DIR)VAX780_MEM.C,\ - $(VAX780_DIR)VAX780_UBA.C,$(VAX780_DIR)VAX780_MBA.C,\ + $(VAX780_DIR)VAX780_UBA.C,$(VAX780_DIR)VAX7X0_MBA.C,\ $(VAX780_DIR)VAX780_FLOAD.C,$(VAX780_DIR)VAX780_SYSLIST.C VAX780_LIB2 = $(LIB_DIR)VAX780L2-$(ARCH).OLB VAX780_SOURCE2 = $(PDP11_DIR)PDP11_RL.C,$(PDP11_DIR)PDP11_RQ.C,\ @@ -645,7 +802,8 @@ VAX780_SOURCE2 = $(PDP11_DIR)PDP11_RL.C,$(PDP11_DIR)PDP11_RQ.C,\ $(PDP11_DIR)PDP11_XU.C,$(PDP11_DIR)PDP11_RY.C,\ $(PDP11_DIR)PDP11_CR.C,$(PDP11_DIR)PDP11_RP.C,\ $(PDP11_DIR)PDP11_TU.C,$(PDP11_DIR)PDP11_HK.C,\ - $(PDP11_DIR)PDP11_VH.C,$(PDP11_DIR)PDP11_IO_LIB.C + $(PDP11_DIR)PDP11_VH.C,$(PDP11_DIR)PDP11_DMC.C,\ + $(PDP11_DIR)PDP11_IO_LIB.C .IFDEF ALPHA_OR_IA64 VAX780_OPTIONS = /INCL=($(SIMH_DIR),$(VAX780_DIR),$(PDP11_DIR)$(PCAP_INC))\ /DEF=($(CC_DEFS),"VM_VAX=1","USE_ADDR64=1","USE_INT64=1"$(PCAP_DEFS),"VAX_780=1") @@ -656,6 +814,37 @@ VAX780_OPTIONS = /INCL=($(SIMH_DIR),$(VAX780_DIR),$(PDP11_DIR)$(PCAP_INC))\ VAX780_SIMH_LIB = $(SIMH_LIB) .ENDIF +# Digital Equipment VAX860 Simulator Definitions. +# +VAX860_DIR = SYS$DISK:[.VAX] +VAX860_LIB1 = $(LIB_DIR)VAX860L1-$(ARCH).OLB +VAX860_SOURCE1 = $(VAX860_DIR)VAX_CPU.C,$(VAX860_DIR)VAX_CPU1.C,\ + $(VAX860_DIR)VAX_FPA.C,$(VAX860_DIR)VAX_CIS.C,\ + $(VAX860_DIR)VAX_OCTA.C,$(VAX860_DIR)VAX_CMODE.C,\ + $(VAX860_DIR)VAX_MMU.C,$(VAX860_DIR)VAX_SYS.C,\ + $(VAX860_DIR)VAX_SYSCM.C,$(VAX860_DIR)VAX860_STDDEV.C,\ + $(VAX860_DIR)VAX860_SBIA.C,$(VAX860_DIR)VAX860_ABUS.C,\ + $(VAX860_DIR)VAX780_UBA.C,$(VAX860_DIR)VAX7X0_MBA.C,\ + $(VAX860_DIR)VAX860_SYSLIST.C +VAX860_LIB2 = $(LIB_DIR)VAX860L2-$(ARCH).OLB +VAX860_SOURCE2 = $(PDP11_DIR)PDP11_RL.C,$(PDP11_DIR)PDP11_RQ.C,\ + $(PDP11_DIR)PDP11_TS.C,$(PDP11_DIR)PDP11_DZ.C,\ + $(PDP11_DIR)PDP11_LP.C,$(PDP11_DIR)PDP11_TQ.C,\ + $(PDP11_DIR)PDP11_XU.C,$(PDP11_DIR)PDP11_RY.C,\ + $(PDP11_DIR)PDP11_CR.C,$(PDP11_DIR)PDP11_RP.C,\ + $(PDP11_DIR)PDP11_TU.C,$(PDP11_DIR)PDP11_HK.C,\ + $(PDP11_DIR)PDP11_VH.C,$(PDP11_DIR)PDP11_DMC.C,\ + $(PDP11_DIR)PDP11_IO_LIB.C +.IFDEF ALPHA_OR_IA64 +VAX860_OPTIONS = /INCL=($(SIMH_DIR),$(VAX860_DIR),$(PDP11_DIR)$(PCAP_INC))\ + /DEF=($(CC_DEFS),"VM_VAX=1","USE_ADDR64=1","USE_INT64=1"$(PCAP_DEFS),"VAX_860=1") +VAX860_SIMH_LIB = $(SIMH_LIB64) +.ELSE +VAX860_OPTIONS = /INCL=($(SIMH_DIR),$(VAX860_DIR),$(PDP11_DIR)$(PCAP_INC))\ + /DEF=($(CC_DEFS),"VM_VAX=1"$(PCAP_DEFS),"VAX_860=1") +VAX860_SIMH_LIB = $(SIMH_LIB) +.ENDIF + # IBM 7094 Simulator Definitions. # I7094_DIR = SYS$DISK:[.I7094] @@ -672,16 +861,18 @@ I7094_OPTIONS = /INCL=($(SIMH_DIR),$(I7094_DIR))/DEF=($(CC_DEFS)) # .IFDEF ALPHA_OR_IA64 ALL : ALTAIR ALTAIRZ80 ECLIPSE GRI LGP H316 HP2100 I1401 I1620 IBM1130 ID16 \ - ID32 NOVA PDP1 PDP4 PDP7 PDP8 PDP9 PDP10 PDP11 PDP15 S3 VAX VAX780 SDS \ - I7094 SWTP6800MP-A SWTP6800MP-A2 + ID32 NOVA PDP1 PDP4 PDP7 PDP8 PDP9 PDP10 PDP11 PDP15 S3 \ + VAX VAX610 VAX620 VAX630 VAX730 VAX750 VAX780 VAX860 \ + SDS I7094 SWTP6800MP-A SWTP6800MP-A2 $! No further actions necessary .ELSE # # Else We Are On VAX And Build Everything EXCEPT the 64b simulators # ALL : ALTAIR ALTAIRZ80 GRI H316 HP2100 I1401 I1620 IBM1130 ID16 ID32 \ - NOVA PDP1 PDP4 PDP7 PDP8 PDP9 PDP11 PDP15 S3 VAX VAX780 SDS SWTP6800MP-A \ - SWTP6800MP-A2 + NOVA PDP1 PDP4 PDP7 PDP8 PDP9 PDP11 PDP15 S3 \ + VAX VAX510 VAX620 VAX630 VAX730 VAX750 VAX780 VAX860 SDS \ + SWTP6800MP-A SWTP6800MP-A2 $! No further actions necessary .ENDIF @@ -730,6 +921,17 @@ $(SIMH_LIB) : $(SIMH_SOURCE) $ LIBRARY/REPLACE $(MMS$TARGET) $(BLD_DIR)*.OBJ $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* +$(SIMH_NONET_LIB) : $(SIMH_SOURCE) + $! + $! Building The $(SIMH_NONET_LIB) Library. + $! + $ $(CC)/DEF=($(CC_DEFS)) - + /OBJ=$(BLD_DIR) $(MMS$CHANGED_LIST) + $ IF (F$SEARCH("$(MMS$TARGET)").EQS."") THEN - + LIBRARY/CREATE $(MMS$TARGET) + $ LIBRARY/REPLACE $(MMS$TARGET) $(BLD_DIR)*.OBJ + $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* + .IFDEF ALPHA_OR_IA64 $(SIMH_LIB64) : $(SIMH_SOURCE) $! @@ -1098,6 +1300,121 @@ $(VAX_LIB2) : $(VAX_SOURCE2) $ LIBRARY/REPLACE $(MMS$TARGET) $(BLD_DIR)*.OBJ $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* +$(VAX610_LIB1) : $(VAX610_SOURCE1) + $! + $! Building The $(VAX610_LIB1) Library. + $! + $ RUN/NODEBUG $(BIN_DIR)BuildROMs-$(ARCH).EXE + $ $(CC)$(VAX610_OPTIONS)/OBJ=$(VAX610_DIR) - + /OBJ=$(BLD_DIR) $(MMS$CHANGED_LIST) + $ IF (F$SEARCH("$(MMS$TARGET)").EQS."") THEN - + LIBRARY/CREATE $(MMS$TARGET) + $ LIBRARY/REPLACE $(MMS$TARGET) $(BLD_DIR)*.OBJ + $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* + +$(VAX610_LIB2) : $(VAX610_SOURCE2) + $! + $! Building The $(VAX610_LIB2) Library. + $! + $ $(CC)$(VAX610_OPTIONS)/OBJ=$(VAX610_DIR) - + /OBJ=$(BLD_DIR) $(MMS$CHANGED_LIST) + $ IF (F$SEARCH("$(MMS$TARGET)").EQS."") THEN - + LIBRARY/CREATE $(MMS$TARGET) + $ LIBRARY/REPLACE $(MMS$TARGET) $(BLD_DIR)*.OBJ + $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* + +$(VAX630_LIB1) : $(VAX630_SOURCE1) + $! + $! Building The $(VAX630_LIB1) Library. + $! + $ RUN/NODEBUG $(BIN_DIR)BuildROMs-$(ARCH).EXE + $ $(CC)$(VAX630_OPTIONS)/OBJ=$(VAX630_DIR) - + /OBJ=$(BLD_DIR) $(MMS$CHANGED_LIST) + $ IF (F$SEARCH("$(MMS$TARGET)").EQS."") THEN - + LIBRARY/CREATE $(MMS$TARGET) + $ LIBRARY/REPLACE $(MMS$TARGET) $(BLD_DIR)*.OBJ + $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* + +$(VAX630_LIB2) : $(VAX630_SOURCE2) + $! + $! Building The $(VAX630_LIB2) Library. + $! + $ $(CC)$(VAX630_OPTIONS)/OBJ=$(VAX630_DIR) - + /OBJ=$(BLD_DIR) $(MMS$CHANGED_LIST) + $ IF (F$SEARCH("$(MMS$TARGET)").EQS."") THEN - + LIBRARY/CREATE $(MMS$TARGET) + $ LIBRARY/REPLACE $(MMS$TARGET) $(BLD_DIR)*.OBJ + $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* + +$(VAX620_LIB1) : $(VAX620_SOURCE1) + $! + $! Building The $(VAX620_LIB1) Library. + $! + $ RUN/NODEBUG $(BIN_DIR)BuildROMs-$(ARCH).EXE + $ $(CC)$(VAX620_OPTIONS)/OBJ=$(VAX620_DIR) - + /OBJ=$(BLD_DIR) $(MMS$CHANGED_LIST) + $ IF (F$SEARCH("$(MMS$TARGET)").EQS."") THEN - + LIBRARY/CREATE $(MMS$TARGET) + $ LIBRARY/REPLACE $(MMS$TARGET) $(BLD_DIR)*.OBJ + $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* + +$(VAX620_LIB2) : $(VAX620_SOURCE2) + $! + $! Building The $(VAX620_LIB2) Library. + $! + $ $(CC)$(VAX620_OPTIONS)/OBJ=$(VAX620_DIR) - + /OBJ=$(BLD_DIR) $(MMS$CHANGED_LIST) + $ IF (F$SEARCH("$(MMS$TARGET)").EQS."") THEN - + LIBRARY/CREATE $(MMS$TARGET) + $ LIBRARY/REPLACE $(MMS$TARGET) $(BLD_DIR)*.OBJ + $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* + +$(VAX730_LIB1) : $(VAX730_SOURCE1) + $! + $! Building The $(VAX730_LIB1) Library. + $! + $ RUN/NODEBUG $(BIN_DIR)BuildROMs-$(ARCH).EXE + $ $(CC)$(VAX730_OPTIONS)/OBJ=$(VAX730_DIR) - + /OBJ=$(BLD_DIR) $(MMS$CHANGED_LIST) + $ IF (F$SEARCH("$(MMS$TARGET)").EQS."") THEN - + LIBRARY/CREATE $(MMS$TARGET) + $ LIBRARY/REPLACE $(MMS$TARGET) $(BLD_DIR)*.OBJ + $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* + +$(VAX730_LIB2) : $(VAX730_SOURCE2) + $! + $! Building The $(VAX730_LIB2) Library. + $! + $ $(CC)$(VAX730_OPTIONS)/OBJ=$(VAX730_DIR) - + /OBJ=$(BLD_DIR) $(MMS$CHANGED_LIST) + $ IF (F$SEARCH("$(MMS$TARGET)").EQS."") THEN - + LIBRARY/CREATE $(MMS$TARGET) + $ LIBRARY/REPLACE $(MMS$TARGET) $(BLD_DIR)*.OBJ + $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* + +$(VAX750_LIB1) : $(VAX750_SOURCE1) + $! + $! Building The $(VAX750_LIB1) Library. + $! + $ RUN/NODEBUG $(BIN_DIR)BuildROMs-$(ARCH).EXE + $ $(CC)$(VAX750_OPTIONS)/OBJ=$(VAX750_DIR) - + /OBJ=$(BLD_DIR) $(MMS$CHANGED_LIST) + $ IF (F$SEARCH("$(MMS$TARGET)").EQS."") THEN - + LIBRARY/CREATE $(MMS$TARGET) + $ LIBRARY/REPLACE $(MMS$TARGET) $(BLD_DIR)*.OBJ + $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* + +$(VAX750_LIB2) : $(VAX750_SOURCE2) + $! + $! Building The $(VAX750_LIB2) Library. + $! + $ $(CC)$(VAX750_OPTIONS)/OBJ=$(VAX750_DIR) - + /OBJ=$(BLD_DIR) $(MMS$CHANGED_LIST) + $ IF (F$SEARCH("$(MMS$TARGET)").EQS."") THEN - + LIBRARY/CREATE $(MMS$TARGET) + $ LIBRARY/REPLACE $(MMS$TARGET) $(BLD_DIR)*.OBJ + $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* + $(VAX780_LIB1) : $(VAX780_SOURCE1) $! $! Building The $(VAX780_LIB1) Library. @@ -1121,6 +1438,29 @@ $(VAX780_LIB2) : $(VAX780_SOURCE2) $ LIBRARY/REPLACE $(MMS$TARGET) $(BLD_DIR)*.OBJ $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* +$(VAX860_LIB1) : $(VAX860_SOURCE1) + $! + $! Building The $(VAX860_LIB1) Library. + $! + $ RUN/NODEBUG $(BIN_DIR)BuildROMs-$(ARCH).EXE + $ $(CC)$(VAX860_OPTIONS)/OBJ=$(VAX860_DIR) - + /OBJ=$(BLD_DIR) $(MMS$CHANGED_LIST) + $ IF (F$SEARCH("$(MMS$TARGET)").EQS."") THEN - + LIBRARY/CREATE $(MMS$TARGET) + $ LIBRARY/REPLACE $(MMS$TARGET) $(BLD_DIR)*.OBJ + $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* + +$(VAX860_LIB2) : $(VAX860_SOURCE2) + $! + $! Building The $(VAX860_LIB2) Library. + $! + $ $(CC)$(VAX860_OPTIONS)/OBJ=$(VAX860_DIR) - + /OBJ=$(BLD_DIR) $(MMS$CHANGED_LIST) + $ IF (F$SEARCH("$(MMS$TARGET)").EQS."") THEN - + LIBRARY/CREATE $(MMS$TARGET) + $ LIBRARY/REPLACE $(MMS$TARGET) $(BLD_DIR)*.OBJ + $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* + $(PCAP_LIB) : $(PCAP_SOURCE) $! $! Building The $(PCAP_LIB) Library. @@ -1163,26 +1503,26 @@ $(I7094_LIB) : ALTAIR : $(BIN_DIR)ALTAIR-$(ARCH).EXE $! ALTAIR done -$(BIN_DIR)ALTAIR-$(ARCH).EXE : $(SIMH_MAIN) $(SIMH_LIB) $(ALTAIR_LIB) +$(BIN_DIR)ALTAIR-$(ARCH).EXE : $(SIMH_MAIN) $(SIMH_NONET_LIB) $(ALTAIR_LIB) $! $! Building The $(BIN_DIR)ALTAIR-$(ARCH).EXE Simulator. $! $ $(CC)$(ALTAIR_OPTIONS)/OBJ=$(BLD_DIR) SCP.C $ LINK $(LINK_DEBUG)/EXE=$(BIN_DIR)ALTAIR-$(ARCH).EXE - - $(BLD_DIR)SCP.OBJ,$(ALTAIR_LIB)/LIBRARY,$(SIMH_LIB)/LIBRARY + $(BLD_DIR)SCP.OBJ,$(ALTAIR_LIB)/LIBRARY,$(SIMH_NONET_LIB)/LIBRARY $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* ALTAIRZ80 : $(BIN_DIR)ALTAIRZ80-$(ARCH).EXE $! ALTAIRZ80 done -$(BIN_DIR)ALTAIRZ80-$(ARCH).EXE : $(SIMH_MAIN) $(SIMH_LIB) $(ALTAIRZ80_LIB1) $(ALTAIRZ80_LIB2) +$(BIN_DIR)ALTAIRZ80-$(ARCH).EXE : $(SIMH_MAIN) $(SIMH_NONET_LIB) $(ALTAIRZ80_LIB1) $(ALTAIRZ80_LIB2) $! $! Building The $(BIN_DIR)ALTAIRZ80-$(ARCH).EXE Simulator. $! $ $(CC)$(ALTAIRZ80_OPTIONS)/OBJ=$(BLD_DIR) SCP.C $ LINK $(LINK_DEBUG)/EXE=$(BIN_DIR)ALTAIRZ80-$(ARCH).EXE - $(BLD_DIR)SCP.OBJ,$(ALTAIRZ80_LIB1)/LIBRARY, - - $(ALTAIRZ80_LIB2)/LIBRARY,$(SIMH_LIB)/LIBRARY + $(ALTAIRZ80_LIB2)/LIBRARY,$(SIMH_NONET_LIB)/LIBRARY $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* # # If Not On VAX, Build The Eclipse Simulator. @@ -1200,194 +1540,194 @@ ECLIPSE : $! Because It Requires The Use Of INT64. .ENDIF -$(BIN_DIR)ECLIPSE-$(ARCH).EXE : $(SIMH_MAIN) $(SIMH_LIB) $(ECLIPSE_LIB) +$(BIN_DIR)ECLIPSE-$(ARCH).EXE : $(SIMH_MAIN) $(SIMH_NONET_LIB) $(ECLIPSE_LIB) $! $! Building The $(BIN_DIR)ECLIPSE-$(ARCH).EXE Simulator. $! $ $(CC)$(ECLIPSE_OPTIONS)/OBJ=$(BLD_DIR) SCP.C $ LINK $(LINK_DEBUG)/EXE=$(BIN_DIR)ECLIPSE-$(ARCH).EXE - - $(BLD_DIR)SCP.OBJ,$(ECLIPSE_LIB)/LIBRARY,$(SIMH_LIB)/LIBRARY + $(BLD_DIR)SCP.OBJ,$(ECLIPSE_LIB)/LIBRARY,$(SIMH_NONET_LIB)/LIBRARY $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* GRI : $(BIN_DIR)GRI-$(ARCH).EXE $! GRI done -$(BIN_DIR)GRI-$(ARCH).EXE : $(SIMH_MAIN) $(SIMH_LIB) $(GRI_LIB) +$(BIN_DIR)GRI-$(ARCH).EXE : $(SIMH_MAIN) $(SIMH_NONET_LIB) $(GRI_LIB) $! $! Building The $(BIN_DIR)GRI-$(ARCH).EXE Simulator. $! $ $(CC)$(GRI_OPTIONS)/OBJ=$(BLD_DIR) SCP.C $ LINK $(LINK_DEBUG)/EXE=$(BIN_DIR)GRI-$(ARCH).EXE - - $(BLD_DIR)SCP.OBJ,$(GRI_LIB)/LIBRARY,$(SIMH_LIB)/LIBRARY + $(BLD_DIR)SCP.OBJ,$(GRI_LIB)/LIBRARY,$(SIMH_NONET_LIB)/LIBRARY $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* LGP : $(BIN_DIR)LGP-$(ARCH).EXE $! LGP done -$(BIN_DIR)LGP-$(ARCH).EXE : $(SIMH_MAIN) $(SIMH_LIB) $(LGP_LIB) +$(BIN_DIR)LGP-$(ARCH).EXE : $(SIMH_MAIN) $(SIMH_NONET_LIB) $(LGP_LIB) $! $! Building The $(BIN_DIR)LGP-$(ARCH).EXE Simulator. $! $ $(CC)$(LGP_OPTIONS)/OBJ=$(BLD_DIR) SCP.C $ LINK $(LINK_DEBUG)/EXE=$(BIN_DIR)LGP-$(ARCH).EXE - - $(BLD_DIR)SCP.OBJ,$(LGP_LIB)/LIBRARY,$(SIMH_LIB)/LIBRARY + $(BLD_DIR)SCP.OBJ,$(LGP_LIB)/LIBRARY,$(SIMH_NONET_LIB)/LIBRARY $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* H316 : $(BIN_DIR)H316-$(ARCH).EXE $! H316 done -$(BIN_DIR)H316-$(ARCH).EXE : $(SIMH_MAIN) $(SIMH_LIB) $(H316_LIB) +$(BIN_DIR)H316-$(ARCH).EXE : $(SIMH_MAIN) $(SIMH_NONET_LIB) $(H316_LIB) $! $! Building The $(BIN_DIR)H316-$(ARCH).EXE Simulator. $! $ $(CC)$(H316_OPTIONS)/OBJ=$(BLD_DIR) SCP.C $ LINK $(LINK_DEBUG)/EXE=$(BIN_DIR)H316-$(ARCH).EXE - - $(BLD_DIR)SCP.OBJ,$(H316_LIB)/LIBRARY,$(SIMH_LIB)/LIBRARY + $(BLD_DIR)SCP.OBJ,$(H316_LIB)/LIBRARY,$(SIMH_NONET_LIB)/LIBRARY $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* HP2100 : $(BIN_DIR)HP2100-$(ARCH).EXE $! HP2100 done -$(BIN_DIR)HP2100-$(ARCH).EXE : $(SIMH_MAIN) $(SIMH_LIB) $(HP2100_LIB1) $(HP2100_LIB2) +$(BIN_DIR)HP2100-$(ARCH).EXE : $(SIMH_MAIN) $(SIMH_NONET_LIB) $(HP2100_LIB1) $(HP2100_LIB2) $! $! Building The $(BIN_DIR)HP2100-$(ARCH).EXE Simulator. $! $ $(CC)$(HP2100_OPTIONS)/OBJ=$(BLD_DIR) SCP.C $ LINK $(LINK_DEBUG)/EXE=$(BIN_DIR)HP2100-$(ARCH).EXE - $(BLD_DIR)SCP.OBJ,$(HP2100_LIB1)/LIBRARY, - - $(HP2100_LIB2)/LIBRARY,$(SIMH_LIB)/LIBRARY + $(HP2100_LIB2)/LIBRARY,$(SIMH_NONET_LIB)/LIBRARY $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* I1401 : $(BIN_DIR)I1401-$(ARCH).EXE $! I1401 done -$(BIN_DIR)I1401-$(ARCH).EXE : $(SIMH_MAIN) $(SIMH_LIB) $(I1401_LIB) +$(BIN_DIR)I1401-$(ARCH).EXE : $(SIMH_MAIN) $(SIMH_NONET_LIB) $(I1401_LIB) $! $! Building The $(BIN_DIR)I1401-$(ARCH).EXE Simulator. $! $ $(CC)$(I1401_OPTIONS)/OBJ=$(BLD_DIR) SCP.C $ LINK $(LINK_DEBUG)/EXE=$(BIN_DIR)I1401-$(ARCH).EXE - - $(BLD_DIR)SCP.OBJ,$(I1401_LIB)/LIBRARY,$(SIMH_LIB)/LIBRARY + $(BLD_DIR)SCP.OBJ,$(I1401_LIB)/LIBRARY,$(SIMH_NONET_LIB)/LIBRARY $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* I1620 : $(BIN_DIR)I1620-$(ARCH).EXE $! I1620 done -$(BIN_DIR)I1620-$(ARCH).EXE : $(SIMH_MAIN) $(SIMH_LIB) $(I1620_LIB) +$(BIN_DIR)I1620-$(ARCH).EXE : $(SIMH_MAIN) $(SIMH_NONET_LIB) $(I1620_LIB) $! $! Building The $(BIN_DIR)I1620-$(ARCH).EXE Simulator. $! $ $(CC)$(I1620_OPTIONS)/OBJ=$(BLD_DIR) SCP.C $ LINK $(LINK_DEBUG)/EXE=$(BIN_DIR)I1620-$(ARCH).EXE - - $(BLD_DIR)SCP.OBJ,$(I1620_LIB)/LIBRARY,$(SIMH_LIB)/LIBRARY + $(BLD_DIR)SCP.OBJ,$(I1620_LIB)/LIBRARY,$(SIMH_NONET_LIB)/LIBRARY $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* IBM1130 : $(BIN_DIR)IBM1130-$(ARCH).EXE $! IBM1130 done -$(BIN_DIR)IBM1130-$(ARCH).EXE : $(SIMH_MAIN) $(SIMH_LIB) $(IBM1130_LIB) +$(BIN_DIR)IBM1130-$(ARCH).EXE : $(SIMH_MAIN) $(SIMH_NONET_LIB) $(IBM1130_LIB) $! $! Building The $(BIN_DIR)IBM1130-$(ARCH).EXE Simulator. $! $ $(CC)$(IBM1130_OPTIONS)/OBJ=$(BLD_DIR) SCP.C $ LINK $(LINK_DEBUG)/EXE=$(BIN_DIR)IBM1130-$(ARCH).EXE - - $(BLD_DIR)SCP.OBJ,$(IBM1130_LIB)/LIBRARY,$(SIMH_LIB)/LIBRARY + $(BLD_DIR)SCP.OBJ,$(IBM1130_LIB)/LIBRARY,$(SIMH_NONET_LIB)/LIBRARY $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* ID16 : $(BIN_DIR)ID16-$(ARCH).EXE $! ID16 done -$(BIN_DIR)ID16-$(ARCH).EXE : $(SIMH_MAIN) $(SIMH_LIB) $(ID16_LIB) +$(BIN_DIR)ID16-$(ARCH).EXE : $(SIMH_MAIN) $(SIMH_NONET_LIB) $(ID16_LIB) $! $! Building The $(BIN_DIR)ID16-$(ARCH).EXE Simulator. $! $ $(CC)$(ID16_OPTIONS)/OBJ=$(BLD_DIR) SCP.C $ LINK $(LINK_DEBUG)/EXE=$(BIN_DIR)ID16-$(ARCH).EXE - - $(BLD_DIR)SCP.OBJ,$(ID16_LIB)/LIBRARY,$(SIMH_LIB)/LIBRARY + $(BLD_DIR)SCP.OBJ,$(ID16_LIB)/LIBRARY,$(SIMH_NONET_LIB)/LIBRARY $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* ID32 : $(BIN_DIR)ID32-$(ARCH).EXE $! ID32 done -$(BIN_DIR)ID32-$(ARCH).EXE : $(SIMH_MAIN) $(SIMH_LIB) $(ID32_LIB) +$(BIN_DIR)ID32-$(ARCH).EXE : $(SIMH_MAIN) $(SIMH_NONET_LIB) $(ID32_LIB) $! $! Building The $(BIN_DIR)ID32-$(ARCH).EXE Simulator. $! $ $(CC)$(ID32_OPTIONS)/OBJ=$(BLD_DIR) SCP.C $ LINK $(LINK_DEBUG)/EXE=$(BIN_DIR)ID32-$(ARCH).EXE - - $(BLD_DIR)SCP.OBJ,$(ID32_LIB)/LIBRARY,$(SIMH_LIB)/LIBRARY + $(BLD_DIR)SCP.OBJ,$(ID32_LIB)/LIBRARY,$(SIMH_NONET_LIB)/LIBRARY $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* NOVA : $(BIN_DIR)NOVA-$(ARCH).EXE $! NOVA done -$(BIN_DIR)NOVA-$(ARCH).EXE : $(SIMH_MAIN) $(SIMH_LIB) $(NOVA_LIB) +$(BIN_DIR)NOVA-$(ARCH).EXE : $(SIMH_MAIN) $(SIMH_NONET_LIB) $(NOVA_LIB) $! $! Building The $(BIN_DIR)NOVA-$(ARCH).EXE Simulator. $! $ $(CC)$(NOVA_OPTIONS)/OBJ=$(BLD_DIR) SCP.C $ LINK $(LINK_DEBUG)/EXE=$(BIN_DIR)NOVA-$(ARCH).EXE - - $(BLD_DIR)SCP.OBJ,$(NOVA_LIB)/LIBRARY,$(SIMH_LIB)/LIBRARY + $(BLD_DIR)SCP.OBJ,$(NOVA_LIB)/LIBRARY,$(SIMH_NONET_LIB)/LIBRARY $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* PDP1 : $(BIN_DIR)PDP1-$(ARCH).EXE $! PDP1 done -$(BIN_DIR)PDP1-$(ARCH).EXE : $(SIMH_MAIN) $(SIMH_LIB) $(PDP1_LIB) +$(BIN_DIR)PDP1-$(ARCH).EXE : $(SIMH_MAIN) $(SIMH_NONET_LIB) $(PDP1_LIB) $! $! Building The $(BIN_DIR)PDP1-$(ARCH).EXE Simulator. $! $ $(CC)$(PDP1_OPTIONS)/OBJ=$(BLD_DIR) SCP.C $ LINK $(LINK_DEBUG)/EXE=$(BIN_DIR)PDP1-$(ARCH).EXE - - $(BLD_DIR)SCP.OBJ,$(PDP1_LIB)/LIBRARY,$(SIMH_LIB)/LIBRARY + $(BLD_DIR)SCP.OBJ,$(PDP1_LIB)/LIBRARY,$(SIMH_NONET_LIB)/LIBRARY $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* PDP4 : $(BIN_DIR)PDP4-$(ARCH).EXE $! PDP4 done -$(BIN_DIR)PDP4-$(ARCH).EXE : $(SIMH_MAIN) $(SIMH_LIB) $(PDP4_LIB) +$(BIN_DIR)PDP4-$(ARCH).EXE : $(SIMH_MAIN) $(SIMH_NONET_LIB) $(PDP4_LIB) $! $! Building The $(BIN_DIR)PDP4-$(ARCH).EXE Simulator. $! $ $(CC)$(PDP4_OPTIONS)/OBJ=$(BLD_DIR) SCP.C $ LINK $(LINK_DEBUG)/EXE=$(BIN_DIR)PDP4-$(ARCH).EXE - - $(BLD_DIR)SCP.OBJ,$(PDP4_LIB)/LIBRARY,$(SIMH_LIB)/LIBRARY + $(BLD_DIR)SCP.OBJ,$(PDP4_LIB)/LIBRARY,$(SIMH_NONET_LIB)/LIBRARY $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* PDP7 : $(BIN_DIR)PDP7-$(ARCH).EXE $! PDP7 done -$(BIN_DIR)PDP7-$(ARCH).EXE : $(SIMH_MAIN) $(SIMH_LIB) $(PDP7_LIB) +$(BIN_DIR)PDP7-$(ARCH).EXE : $(SIMH_MAIN) $(SIMH_NONET_LIB) $(PDP7_LIB) $! $! Building The $(BIN_DIR)PDP7-$(ARCH).EXE Simulator. $! $ $(CC)$(PDP7_OPTIONS)/OBJ=$(BLD_DIR) SCP.C $ LINK $(LINK_DEBUG)/EXE=$(BIN_DIR)PDP7-$(ARCH).EXE - - $(BLD_DIR)SCP.OBJ,$(PDP7_LIB)/LIBRARY,$(SIMH_LIB)/LIBRARY + $(BLD_DIR)SCP.OBJ,$(PDP7_LIB)/LIBRARY,$(SIMH_NONET_LIB)/LIBRARY $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* PDP8 : $(BIN_DIR)PDP8-$(ARCH).EXE $! PDP8 done -$(BIN_DIR)PDP8-$(ARCH).EXE : $(SIMH_MAIN) $(SIMH_LIB) $(PDP8_LIB) +$(BIN_DIR)PDP8-$(ARCH).EXE : $(SIMH_MAIN) $(SIMH_NONET_LIB) $(PDP8_LIB) $! $! Building The $(BIN_DIR)PDP8-$(ARCH).EXE Simulator. $! $ $(CC)$(PDP8_OPTIONS)/OBJ=$(BLD_DIR) SCP.C $ LINK $(LINK_DEBUG)/EXE=$(BIN_DIR)PDP8-$(ARCH).EXE - - $(BLD_DIR)SCP.OBJ,$(PDP8_LIB)/LIBRARY,$(SIMH_LIB)/LIBRARY + $(BLD_DIR)SCP.OBJ,$(PDP8_LIB)/LIBRARY,$(SIMH_NONET_LIB)/LIBRARY $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* PDP9 : $(BIN_DIR)PDP9-$(ARCH).EXE $! PDP9 done -$(BIN_DIR)PDP9-$(ARCH).EXE : $(SIMH_MAIN) $(SIMH_LIB) $(PDP9_LIB) +$(BIN_DIR)PDP9-$(ARCH).EXE : $(SIMH_MAIN) $(SIMH_NONET_LIB) $(PDP9_LIB) $! $! Building The $(BIN_DIR)PDP9-$(ARCH).EXE Simulator. $! $ $(CC)$(PDP9_OPTIONS)/OBJ=$(BLD_DIR) SCP.C $ LINK $(LINK_DEBUG)/EXE=$(BIN_DIR)PDP9-$(ARCH).EXE - - $(BLD_DIR)SCP.OBJ,$(PDP9_LIB)/LIBRARY,$(SIMH_LIB)/LIBRARY + $(BLD_DIR)SCP.OBJ,$(PDP9_LIB)/LIBRARY,$(SIMH_NONET_LIB)/LIBRARY $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* # @@ -1397,13 +1737,13 @@ $(BIN_DIR)PDP9-$(ARCH).EXE : $(SIMH_MAIN) $(SIMH_LIB) $(PDP9_LIB) PDP10 : $(BIN_DIR)PDP10-$(ARCH).EXE $! PDP10 done -$(BIN_DIR)PDP10-$(ARCH).EXE : $(SIMH_MAIN) $(SIMH_LIB) $(PCAP_LIBD) $(PDP10_LIB) $(PCAP_EXECLET) +$(BIN_DIR)PDP10-$(ARCH).EXE : $(SIMH_MAIN) $(SIMH_NONET_LIB) $(PCAP_LIBD) $(PDP10_LIB) $(PCAP_EXECLET) $! $! Building The $(BIN_DIR)PDP10-$(ARCH).EXE Simulator. $! $ $(CC)$(PDP10_OPTIONS)/OBJ=$(BLD_DIR) SCP.C $ LINK $(LINK_DEBUG)/EXE=$(BIN_DIR)PDP10-$(ARCH).EXE - - $(BLD_DIR)SCP.OBJ,$(PDP10_LIB)/LIBRARY,$(SIMH_LIB)/LIBRARY$(PCAP_LIBR) + $(BLD_DIR)SCP.OBJ,$(PDP10_LIB)/LIBRARY,$(SIMH_NONET_LIB)/LIBRARY$(PCAP_LIBR) $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* .ELSE # @@ -1430,61 +1770,61 @@ $(BIN_DIR)PDP11-$(ARCH).EXE : $(SIMH_MAIN) $(SIMH_LIB) $(PCAP_LIBD) $(PDP11_LIB1 PDP15 : $(BIN_DIR)PDP15-$(ARCH).EXE $! PDP15 done -$(BIN_DIR)PDP15-$(ARCH).EXE : $(SIMH_MAIN) $(SIMH_LIB) $(PDP15_LIB) +$(BIN_DIR)PDP15-$(ARCH).EXE : $(SIMH_MAIN) $(SIMH_NONET_LIB) $(PDP15_LIB) $! $! Building The $(BIN_DIR)PDP15-$(ARCH).EXE Simulator. $! $ $(CC)$(PDP15_OPTIONS)/OBJ=$(BLD_DIR) SCP.C $ LINK $(LINK_DEBUG)/EXE=$(BIN_DIR)PDP15-$(ARCH).EXE - - $(BLD_DIR)SCP.OBJ,$(PDP15_LIB)/LIBRARY,$(SIMH_LIB)/LIBRARY + $(BLD_DIR)SCP.OBJ,$(PDP15_LIB)/LIBRARY,$(SIMH_NONET_LIB)/LIBRARY $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* S3 : $(BIN_DIR)S3-$(ARCH).EXE $! S3 done -$(BIN_DIR)S3-$(ARCH).EXE : $(SIMH_MAIN) $(SIMH_LIB) $(S3_LIB) +$(BIN_DIR)S3-$(ARCH).EXE : $(SIMH_MAIN) $(SIMH_NONET_LIB) $(S3_LIB) $! $! Building The $(BIN_DIR)S3-$(ARCH).EXE Simulator. $! $ $(CC)$(S3_OPTIONS)/OBJ=$(BLD_DIR) SCP.C $ LINK $(LINK_DEBUG)/EXE=$(BIN_DIR)S3-$(ARCH).EXE - - $(BLD_DIR)SCP.OBJ,$(S3_LIB)/LIBRARY,$(SIMH_LIB)/LIBRARY + $(BLD_DIR)SCP.OBJ,$(S3_LIB)/LIBRARY,$(SIMH_NONET_LIB)/LIBRARY $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* SDS : $(BIN_DIR)SDS-$(ARCH).EXE $! SDS done -$(BIN_DIR)SDS-$(ARCH).EXE : $(SIMH_MAIN) $(SIMH_LIB) $(SDS_LIB) +$(BIN_DIR)SDS-$(ARCH).EXE : $(SIMH_MAIN) $(SIMH_NONET_LIB) $(SDS_LIB) $! $! Building The $(BIN_DIR)SDS-$(ARCH).EXE Simulator. $! $ $(CC)$(SDS_OPTIONS)/OBJ=$(BLD_DIR) SCP.C $ LINK $(LINK_DEBUG)/EXE=$(BIN_DIR)SDS-$(ARCH).EXE - - $(BLD_DIR)SCP.OBJ,$(SDS_LIB)/LIBRARY,$(SIMH_LIB)/LIBRARY + $(BLD_DIR)SCP.OBJ,$(SDS_LIB)/LIBRARY,$(SIMH_NONET_LIB)/LIBRARY $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* SWTP6800MP-A : $(BIN_DIR)SWTP6800MP-A-$(ARCH).EXE $! SWTP6800MP-A done -$(BIN_DIR)SWTP6800MP-A-$(ARCH).EXE : $(SIMH_MAIN) $(SIMH_LIB) $(SWTP6800MP_A_LIB) +$(BIN_DIR)SWTP6800MP-A-$(ARCH).EXE : $(SIMH_MAIN) $(SIMH_NONET_LIB) $(SWTP6800MP_A_LIB) $! $! Building The $(BIN_DIR)SWTP6800MP-A-$(ARCH).EXE Simulator. $! - $ $(CC)$(SWTP_OPTIONS)/OBJ=$(BLD_DIR) SCP.C + $ $(CC)$(SWTP6800MP_A_OPTIONS)/OBJ=$(BLD_DIR) SCP.C $ LINK $(LINK_DEBUG)/EXE=$(BIN_DIR)SWTP6800MP-A-$(ARCH).EXE - - $(BLD_DIR)SCP.OBJ,$(SWTP6800MP_A_LIB)/LIBRARY,$(SIMH_LIB)/LIBRARY + $(BLD_DIR)SCP.OBJ,$(SWTP6800MP_A_LIB)/LIBRARY,$(SIMH_NONET_LIB)/LIBRARY $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* SWTP6800MP-A2 : $(BIN_DIR)SWTP6800MP-A2-$(ARCH).EXE $! SWTP6800MP-A2 done -$(BIN_DIR)SWTP6800MP-A2-$(ARCH).EXE : $(SIMH_MAIN) $(SIMH_LIB) $(SWTP6800MP_A2_LIB) +$(BIN_DIR)SWTP6800MP-A2-$(ARCH).EXE : $(SIMH_MAIN) $(SIMH_NONET_LIB) $(SWTP6800MP_A2_LIB) $! $! Building The $(BIN_DIR)SWTP6800MP-A2-$(ARCH).EXE Simulator. $! - $ $(CC)$(SWTP_OPTIONS)/OBJ=$(BLD_DIR) SCP.C + $ $(CC)$(SWTP6800MP_A2_OPTIONS)/OBJ=$(BLD_DIR) SCP.C $ LINK $(LINK_DEBUG)/EXE=$(BIN_DIR)SWTP6800MP-A2-$(ARCH).EXE - - $(BLD_DIR)SCP.OBJ,$(SWTP6800MP_A2_LIB)/LIBRARY,$(SIMH_LIB)/LIBRARY + $(BLD_DIR)SCP.OBJ,$(SWTP6800MP_A2_LIB)/LIBRARY,$(SIMH_NONET_LIB)/LIBRARY $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* VAX : $(BIN_DIR)VAX-$(ARCH).EXE @@ -1501,6 +1841,81 @@ $(BIN_DIR)VAX-$(ARCH).EXE : $(SIMH_MAIN) $(VAX_SIMH_LIB) $(PCAP_LIBD) $(VAX_LIB1 $(VAX_SIMH_LIB)/LIBRARY$(PCAP_LIBR) $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* +VAX610 : $(BIN_DIR)VAX610-$(ARCH).EXE + $! VAX610 done + +$(BIN_DIR)VAX610-$(ARCH).EXE : $(SIMH_MAIN) $(VAX610_SIMH_LIB) $(PCAP_LIBD) $(VAX610_LIB1) $(VAX610_LIB2) $(PCAP_EXECLET) + $! + $! Building The $(BIN_DIR)VAX610-$(ARCH).EXE Simulator. + $! + $ $(CC)$(VAX610_OPTIONS)/OBJ=$(BLD_DIR) SCP.C + $ LINK $(LINK_DEBUG)$(LINK_SECTION_BINDING)- + /EXE=$(BIN_DIR)VAX610-$(ARCH).EXE - + $(BLD_DIR)SCP.OBJ,- + $(VAX610_LIB1)/LIBRARY,$(VAX610_LIB2)/LIBRARY,- + $(VAX610_SIMH_LIB)/LIBRARY$(PCAP_LIBR) + $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* + +VAX630 : $(BIN_DIR)VAX630-$(ARCH).EXE + $! VAX630 done + +$(BIN_DIR)VAX630-$(ARCH).EXE : $(SIMH_MAIN) $(VAX630_SIMH_LIB) $(PCAP_LIBD) $(VAX630_LIB1) $(VAX630_LIB2) $(PCAP_EXECLET) + $! + $! Building The $(BIN_DIR)VAX630-$(ARCH).EXE Simulator. + $! + $ $(CC)$(VAX630_OPTIONS)/OBJ=$(BLD_DIR) SCP.C + $ LINK $(LINK_DEBUG)$(LINK_SECTION_BINDING)- + /EXE=$(BIN_DIR)VAX630-$(ARCH).EXE - + $(BLD_DIR)SCP.OBJ,- + $(VAX630_LIB1)/LIBRARY,$(VAX630_LIB2)/LIBRARY,- + $(VAX630_SIMH_LIB)/LIBRARY$(PCAP_LIBR) + $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* + +VAX620 : $(BIN_DIR)VAX620-$(ARCH).EXE + $! VAX620 done + +$(BIN_DIR)VAX620-$(ARCH).EXE : $(SIMH_MAIN) $(VAX620_SIMH_LIB) $(PCAP_LIBD) $(VAX620_LIB1) $(VAX620_LIB2) $(PCAP_EXECLET) + $! + $! Building The $(BIN_DIR)VAX620-$(ARCH).EXE Simulator. + $! + $ $(CC)$(VAX620_OPTIONS)/OBJ=$(BLD_DIR) SCP.C + $ LINK $(LINK_DEBUG)$(LINK_SECTION_BINDING)- + /EXE=$(BIN_DIR)VAX620-$(ARCH).EXE - + $(BLD_DIR)SCP.OBJ,- + $(VAX620_LIB1)/LIBRARY,$(VAX620_LIB2)/LIBRARY,- + $(VAX620_SIMH_LIB)/LIBRARY$(PCAP_LIBR) + $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* + +VAX730 : $(BIN_DIR)VAX730-$(ARCH).EXE + $! VAX730 done + +$(BIN_DIR)VAX730-$(ARCH).EXE : $(SIMH_MAIN) $(VAX730_SIMH_LIB) $(PCAP_LIBD) $(VAX730_LIB1) $(VAX730_LIB2) $(PCAP_EXECLET) + $! + $! Building The $(BIN_DIR)VAX730-$(ARCH).EXE Simulator. + $! + $ $(CC)$(VAX730_OPTIONS)/OBJ=$(BLD_DIR) SCP.C + $ LINK $(LINK_DEBUG)$(LINK_SECTION_BINDING)- + /EXE=$(BIN_DIR)VAX730-$(ARCH).EXE - + $(BLD_DIR)SCP.OBJ,- + $(VAX730_LIB1)/LIBRARY,$(VAX730_LIB2)/LIBRARY,- + $(VAX730_SIMH_LIB)/LIBRARY$(PCAP_LIBR) + $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* + +VAX750 : $(BIN_DIR)VAX750-$(ARCH).EXE + $! VAX750 done + +$(BIN_DIR)VAX750-$(ARCH).EXE : $(SIMH_MAIN) $(VAX750_SIMH_LIB) $(PCAP_LIBD) $(VAX750_LIB1) $(VAX750_LIB2) $(PCAP_EXECLET) + $! + $! Building The $(BIN_DIR)VAX750-$(ARCH).EXE Simulator. + $! + $ $(CC)$(VAX750_OPTIONS)/OBJ=$(BLD_DIR) SCP.C + $ LINK $(LINK_DEBUG)$(LINK_SECTION_BINDING)- + /EXE=$(BIN_DIR)VAX750-$(ARCH).EXE - + $(BLD_DIR)SCP.OBJ,- + $(VAX750_LIB1)/LIBRARY,$(VAX750_LIB2)/LIBRARY,- + $(VAX750_SIMH_LIB)/LIBRARY$(PCAP_LIBR) + $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* + VAX780 : $(BIN_DIR)VAX780-$(ARCH).EXE $! VAX780 done @@ -1516,6 +1931,21 @@ $(BIN_DIR)VAX780-$(ARCH).EXE : $(SIMH_MAIN) $(VAX780_SIMH_LIB) $(PCAP_LIBD) $(VA $(VAX780_SIMH_LIB)/LIBRARY$(PCAP_LIBR) $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* +VAX860 : $(BIN_DIR)VAX860-$(ARCH).EXE + $! VAX860 done + +$(BIN_DIR)VAX860-$(ARCH).EXE : $(SIMH_MAIN) $(VAX860_SIMH_LIB) $(PCAP_LIBD) $(VAX860_LIB1) $(VAX860_LIB2) $(PCAP_EXECLET) + $! + $! Building The $(BIN_DIR)VAX860-$(ARCH).EXE Simulator. + $! + $ $(CC)$(VAX860_OPTIONS)/OBJ=$(BLD_DIR) SCP.C + $ LINK $(LINK_DEBUG)$(LINK_SECTION_BINDING)- + /EXE=$(BIN_DIR)VAX860-$(ARCH).EXE - + $(BLD_DIR)SCP.OBJ,- + $(VAX860_LIB1)/LIBRARY,$(VAX860_LIB2)/LIBRARY,- + $(VAX860_SIMH_LIB)/LIBRARY$(PCAP_LIBR) + $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* + # # If Not On VAX, Build The IBM 7094 Simulator. # @@ -1523,13 +1953,13 @@ $(BIN_DIR)VAX780-$(ARCH).EXE : $(SIMH_MAIN) $(VAX780_SIMH_LIB) $(PCAP_LIBD) $(VA I7094 : $(BIN_DIR)I7094-$(ARCH).EXE $! I7094 done -$(BIN_DIR)I7094-$(ARCH).EXE : $(SIMH_MAIN) $(SIMH_LIB) $(I7094_LIB) +$(BIN_DIR)I7094-$(ARCH).EXE : $(SIMH_MAIN) $(SIMH_NONET_LIB) $(I7094_LIB) $! $! Building The $(BIN_DIR)I7094-$(ARCH).EXE Simulator. $! $ $(CC)$(I7094_OPTIONS)/OBJ=$(BLD_DIR) SCP.C $ LINK $(LINK_DEBUG)/EXE=$(BIN_DIR)I7094-$(ARCH).EXE - - $(BLD_DIR)SCP.OBJ,$(I7094_LIB)/LIBRARY,$(SIMH_LIB)/LIBRARY$(PCAP_LIBR) + $(BLD_DIR)SCP.OBJ,$(I7094_LIB)/LIBRARY,$(SIMH_NONET_LIB)/LIBRARY$(PCAP_LIBR) $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* .ELSE # diff --git a/display/README b/display/README new file mode 100644 index 00000000..7f3b8475 --- /dev/null +++ b/display/README @@ -0,0 +1,166 @@ +$Id: README,v 1.15 2004/02/09 07:20:18 phil Exp $ + +XY Display Simulation +Simulates XY plotting displays used on DEC PDP systems. + + Copyright (c) 2003-2004, Philip L. Budne and Douglas A. Gwyn + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the names of the authors shall + not be used in advertising or otherwise to promote the sale, use or + other dealings in this Software without prior written authorization + from the authors. + +Phil Budne +Douglas A Gwyn +February 5, 2004 + +Designed for use with Bob Supnik's SIMH, but the code should be easily +portable, and usable standalone (see vttest.c for an example). + +Display code is provided for X11 (Unix/VMS) and Win32. +We're not GUI programmers, so the code is PRIMITIVE!! + +Started from VC8E simulator by Douglas W. Jones +(distribution 5, of Feb 4, 1997); + + This PDP8 Emulator was written by Douglas W. Jones at the + University of Iowa. It is distributed as freeware, of + uncertain function and uncertain utility. + +Original phosphor decay constants for Type 30 display from XMame 0.72.1 + +VT11 support GREATLY enhanced (and VT48 support added) and +other general improvements from Douglas A Gwyn. + +In the interest of fair play we have supplied two makefiles (neither +of which is named Makefile nor makefile), one which works under all +flavors of "make" (after necessary editing, in the traditional manner), +and one which functions only under the GNU version of make (sometimes +installed as "gmake", but the default "make" on many systems). We have +not added a third flavor which uses BSD make enhancements, because our +deeply held roots (over 40 combined years of Unix experience by the +authors) demand that things should work on all platforms. Both the +Linux and Windows worlds violate this simple credo (everything works so +long as you use OUR preferred software), and many current users may not +even realize that editing Makefiles used to be de rigeur. Since the +GNU environment is widely available and "gmake" has features that +support automatic configuration for multiple platforms, we have +supplied thr GNU-specific variant with the expectation that many users +will find it more convenient. You can copy or link whichever flavor of +makefile suits your taste to whichever spelling of "makefile" suits +your fancy, or invoke "make" with the -f flag specifying the desired +makefile. + +To compile test programs: +======================== +On Unix: + # edit smakefile to match your environment + make -f smakefile +or + gmake -f gmakefile + +On Win32 (using Cygwin); + make -f gmakefile WIN32=1 + +On Win32 (using MINGW): + # edit smakefile to match your environment + make -f smakefile +or + mingw32-make -f gmakefile WIN32=1 +or + execute build-mingw.bat in a DOS command window + +creates: + + munch: standalone simulation of PDP-1 munching squares; + examines console "test switches" (see next section) + + vt11: sequences through VT11/VS60 simulator test displays; + shows how the diplay-processor simulator can be used + from applications other than PDP-11 simulators + +Console switches: +================ + +Upto 18 simulated console switches, toggled by hitting keys: + +123 456 789 qwe rty uio + +space bar clears all switches. + +Spacewar Switches: +================= + +Key presses for simulated Spacewar control box switches; + +action player + 1 2 +rotate clockwise a k +rotate counter clockwise s l +fire engines d ; +launch torpedo f ' +hyperspace (both at once) as kl + +Light pen: +========= + +The light pen is active when any mouse button is held down. + +Mouse button 1 acts as a "tip switch" for models so equipped (VS60). +The light pen may be dragged while active. + +Too many compile time parameters: +================================ + +Read the comments in display.c for more explanations!! + +DISPLAY_TYPE default display type, one of: + DIS_VR14, DIS_VR17, DIS_VR20, DIS_VR48, DIS_TYPE30, DIS_TYPE340 + selects screen characteristics (phosphor, dimensions). + + Only affects programs which do not make an expicit + display_init() call. + +PIX_SCALE one of RES_FULL, RES_HALF, RES_QUARTER, RES_EIGHTH + selects default display scaling factor. + +PEN_RADIUS default radius of light pen in (scaled) pixels + +MAXELAPSED Upper limit in real microseconds between polls/delays +MINELAPSED Lower limit in real microseconds between polls/delays +MINDELAY Lower limit in real microseconds for attempted delay +MAXDELAY Upper limit in real microseconds for attempted delay +GAINSHIFT delay_check increment/decrement gain factor + +In display system support (x11.c, win32.c); + +PIX_SIZE selects displayed pixel size (default 1) + makes screen larger, useful when display scaled to small size + +Programming interface: +===================== + +see display.h + +Source repository: +================= + +Up-to-date Sources are available by anonymous CVS. +See http://www.ultimate.com/phil/xy/ diff --git a/display/build_mingw.bat b/display/build_mingw.bat new file mode 100644 index 00000000..49222c11 --- /dev/null +++ b/display/build_mingw.bat @@ -0,0 +1,12 @@ +@echo off +rem $Id: build_mingw.bat,v 1.1 2004/01/25 17:48:03 phil Exp $ +rem Compile all test programs using MINGW make and gcc environment +rem +rem If needed, define the path for the MINGW bin directory. +rem (this should already be set if MINGW was installed correctly) +rem +gcc -v 1>NUL 2>NUL +if ERRORLEVEL 1 path C:\MinGW\bin;D:\MinGW\bin;E:\MinGW\bin;%path% +gcc -v 1>NUL 2>NUL +if ERRORLEVEL 1 echo "MinGW Environment Unavailable" +mingw32-make WIN32=1 -f gmakefile %1 %2 %3 %4 diff --git a/display/display.c b/display/display.c new file mode 100644 index 00000000..aa276435 --- /dev/null +++ b/display/display.c @@ -0,0 +1,1053 @@ +/* + * $Id: display.c,v 1.57 2004/02/04 16:59:01 phil Exp $ + * Simulator and host O/S independent XY display simulator + * Phil Budne + * September 2003 + * + * with changes by Douglas A. Gwyn, 21 Jan. 2004 + * + * started from PDP-8/E simulator vc8e.c; + * This PDP8 Emulator was written by Douglas W. Jones at the + * University of Iowa. It is distributed as freeware, of + * uncertain function and uncertain utility. + */ + +/* + * Copyright (c) 2003-2004, Philip L. Budne + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the names of the authors shall + * not be used in advertising or otherwise to promote the sale, use or + * other dealings in this Software without prior written authorization + * from the authors. + */ + +#include +#include +#include +#include /* for USHRT_MAX */ +#include "ws.h" +#include "display.h" + +/* + * The user may select (at compile time) how big a window is used to + * emulate the display. Using smaller windows saves memory and screen space. + * + * Type 30 has 1024x1024 addressing, but only 512x512 visible points. + * VR14 has only 1024x768 visible points; VR17 has 1024x1024 visible points. + * VT11 supports 4096x4096 addressing, clipping to the lowest 1024x1024 region. + * VR48 has 1024x1024 visible points in the main display area and 128x1024 + * visible points in a menu area on the right-hand side (1152x1024 total). + * VT48 supports 8192x8192 (signed) main-area addressing, clipping to a + * 1024x1024 window which can be located anywhere within that region. + * (XXX -- That is what the VT11/VT48 manuals say; however, evidence suggests + * that the VT11 may actually support 8192x8192 (signed) addressing too.) + */ + +/* Define the default display type (if display_init() not called) */ +#ifndef DISPLAY_TYPE +#define DISPLAY_TYPE DIS_TYPE30 +#endif /* DISPLAY_TYPE not defined */ + +/* select a default resolution if display_init() not called */ +/* XXX keep in struct display? */ +#ifndef PIX_SCALE +#define PIX_SCALE RES_HALF +#endif /* PIX_SCALE not defined */ + +/* select a default light-pen hit radius if display_init() not called */ +#ifndef PEN_RADIUS +#define PEN_RADIUS 4 +#endif /* PEN_RADIUS not defined */ + +/* + * note: displays can have up to two different colors (eg VR20) + * each color can be made up of any number of phosphors + * with different colors and decay characteristics (eg Type 30) + */ + +#define ELEMENTS(X) (sizeof(X)/sizeof(X[0])) + +struct phosphor { + double red, green, blue; + double level; /* decay level (0.5 for half life) */ + double t_level; /* seconds to decay to level */ +}; + +struct color { + struct phosphor *phosphors; + int nphosphors; + int half_life; /* for refresh calc */ +}; + +struct display { + enum display_type type; + char *name; + struct color *color0, *color1; + short xpoints, ypoints; +}; + +/* + * original phosphor constants from Raphael Nabet's XMame 0.72.1 PDP-1 sim. + * not even sure Type30 really used P17 (guess by Daniel P. B. Smith) + */ +static struct phosphor p17[] = { + {0.11, 0.11, 1.0, 0.5, 0.05}, /* fast blue */ + {1.0, 1.0, 0.11, 0.5, 0.20} /* slow yellow/green */ +}; +static struct color color_p17 = { p17, ELEMENTS(p17), 125000 }; + +/* green phosphor for VR14, VR17, VR20 */ +static struct phosphor p29[] = {{0.0260, 1.0, 0.00121, 0.5, 0.025}}; +struct color color_p29 = { p29, ELEMENTS(p29), 25000 }; + +static struct phosphor p40[] = { + /* P40 blue-white spot with yellow-green decay (.045s to 10%?) */ + {0.4, 0.2, 0.924, 0.5, 0.0135}, + {0.5, 0.7, 0.076, 0.5, 0.065} +}; +static struct color color_p40 = { p40, ELEMENTS(p40), 20000 }; + +/* "red" -- until real VR20 phosphor type/number/constants known */ +static struct phosphor pred[] = { {1.0, 0.37, 0.37, 0.5, 0.10} }; +static struct color color_red = { pred, ELEMENTS(pred), 100000 }; + +static struct display displays[] = { + /* + * TX-0 + * + * + * Unknown manufacturer + * + * 12" tube, + * maximum dot size ??? + * 50us point plot time (20,000 points/sec) + * P17 Phosphor??? Two phosphor layers: + * fast blue (.05s half life), and slow green (.2s half life) + * + * + */ + { DIS_TX0, "MIT TX-0", &color_p17, NULL, 512, 512 }, + + + /* + * Type 30 + * PDP-1/4/5/8/9/10 "Precision CRT" display system + * + * Raytheon 16ADP7A CRT? + * web searches for 16ADP7 finds useful information!! + * 16" tube, 14 3/8" square raster + * maximum dot size .015" + * 50us point plot time (20,000 points/sec) + * P17 Phosphor??? Two phosphor layers: + * fast blue (.05s half life), and slow green (.2s half life) + * 360 lb + * 7A at 115+-10V 60Hz + */ + { DIS_TYPE30, "Type 30", &color_p17, NULL, 1024, 1024 }, + + /* + * VR14 + * used w/ GT40/44, AX08, VC8E + * + * Viewable area 6.75" x 9" + * 12" diagonal + * brightness >= 30 fL + * dot size .02" (20 mils) + * settle time: + * full screen 18us to +/-1 spot diameter + * .1" change 1us to +/-.5 spot diameter + * weight 75lb + */ + { DIS_VR14, "VR14", &color_p29, NULL, 1024, 768 }, + + /* + * VR17 + * used w/ GT40/44, AX08, VC8E + * + * Viewable area 9.25" x 9.25" + * 17" diagonal + * dot size .02" (20 mils) + * brightness >= 25 fL + * phosphor: P39 doped for IR light pen use + * light pen: Type 375 + * weight 85lb + */ + { DIS_VR17, "VR17", &color_p29, NULL, 1024, 1024 }, + + /* + * VR20 + * on VC8E + * Two colors!! + */ + { DIS_VR20, "VR20", &color_p29, &color_red, 1024, 1024 }, + + /* + * VR48 + * (on VT48 in VS60) + * from Douglas A. Gwyn 23 Nov. 2003 + * + * Viewable area 12" x 12", plus 1.5" x 12" menu area on right-hand side + * 21" diagonal + * dot size <= .01" (10 mils) + * brightness >= 31 fL + * phosphor: P40 (blue-white fluorescence with yellow-green phosphorescence) + * light pen: Type 377A (with tip switch) + * driving circuitry separate + * (normally under table on which CRT is mounted) + */ + { DIS_VR48, "VR48", &color_p40, NULL, 1024+VR48_GUTTER+128, 1024 }, + + /* + * Type 340 Display system + * on PDP-4/6/7/9/10 + * + * 1024x1024 + * 9 3/8" raster (.01" dot pitch) + * 0,0 at lower left + * 8 intensity levels + */ + { DIS_TYPE340, "Type 340", &color_p17, NULL, 1024, 1024 } +}; + +/* + * Unit time (in microseconds) used to store display point time to + * live at current aging level. If this is too small, delay values + * cannot fit in an unsigned short. If it is too large all pixels + * will age at once. Perhaps a suitable value should be calculated at + * run time? When display_init() calculates refresh_interval it + * sanity checks for both cases. + */ +#define DELAY_UNIT 250 + +/* levels to display in first half-life; determines refresh rate */ +#ifndef LEVELS_PER_HALFLIFE +#define LEVELS_PER_HALFLIFE 4 +#endif + +/* after 5 half lives (.5**5) remaining intensity is 3% of original */ +#ifndef HALF_LIVES_TO_DISPLAY +#define HALF_LIVES_TO_DISPLAY 5 +#endif + +/* + * refresh_rate is number of times per (simulated) second a pixel is + * aged to next lowest intensity level. + * + * refresh_rate = ((1e6*LEVELS_PER_HALFLIFE)/PHOSPHOR_HALF_LIFE) + * refresh_interval = 1e6/DELAY_UNIT/refresh_rate + * = PHOSPHOR_HALF_LIFE/LEVELS_PER_HALF_LIFE + * intensities = (HALF_LIVES_TO_DISPLAY*PHOSPHOR_HALF_LIFE)/refresh_interval + * = HALF_LIVES_TO_DISPLAY*LEVELS_PER_HALFLIFE + * + * See also comments on display_age() + * + * Try to keep LEVELS_PER_HALFLIFE*HALF_LIVES_TO_DISPLAY*NLEVELS <= 192 + * to run on 8-bit (256 color) displays! + */ + +/* + * number of aging periods to display a point for + */ +#define NTTL (HALF_LIVES_TO_DISPLAY*LEVELS_PER_HALFLIFE) + +/* + * maximum (initial) TTL for a point. + * TTL's are stored 1-based + * (a stored TTL of zero means the point is off) + */ +#define MAXTTL NTTL + +/* + * number of drawing intensity levels + */ +#define NLEVELS (DISPLAY_INT_MAX-DISPLAY_INT_MIN+1) + +#define MAXLEVEL (NLEVELS-1) + +/* + * Display Device Implementation + */ + +/* + * Each point on the display is represented by a "struct point". When + * a point isn't dark (intensity > 0), it is linked into a circular, + * doubly linked delta queue (a priority queue where "delay" + * represents the time difference from the previous entry (if any) in + * the queue. + * + * All points are aged refresh_rate times/second, each time moved to the + * next (logarithmically) lower intensity level. When display_age() is + * called, only the entries which have expired are processed. Calling + * display_age() often allows spreading out the workload. + * + * An alternative would be to have intensity levels represent linear + * decreases in intensity, and have the decay time at each level change. + * Inverting the decay function for a multi-component phosphor may be + * tricky, and the two different colors would need different time tables. + * Furthermore, it would require finding the correct location in the + * queue when adding a point (currently only need to add points at end) + */ + +/* + * 12 bytes/entry on 32-bit system when REFRESH_RATE > 15 + * (requires 3MB for 512x512 display). + */ + +typedef unsigned short delay_t; +#define DELAY_T_MAX USHRT_MAX + +struct point { + struct point *next; /* next entry in queue */ + struct point *prev; /* prev entry in queue */ + delay_t delay; /* delta T in DELAY_UNITs */ + unsigned char ttl; /* zero means off, not linked in */ + unsigned char level : 7; /* intensity level */ + unsigned char color : 1; /* for VR20 (two colors) */ +}; + +static struct point *points; /* allocated array of points */ +static struct point _head; +#define head (&_head) + +/* + * time span of all entries in queue + * should never exceed refresh_interval + * (should be possible to make this a delay_t) + */ +static long queue_interval; + +/* convert X,Y to a "struct point *" */ +#define P(X,Y) (points + (X) + ((Y)*(size_t)xpixels)) + +/* convert "struct point *" to X and Y */ +#define X(P) (((P) - points) % xpixels) +#define Y(P) (((P) - points) / xpixels) + +static int initialized = 0; + +/* + * global set by O/S display level to indicate "light pen tip switch activated" + * (This is used only by the VS60 emulation, also by vttest to change patterns) + */ +unsigned char display_lp_sw = 0; + +/* + * global set by DR11-C simulation when DR device enabled; deactivates + * light pen and instead reports mouse coordinates as Talos digitizer + * data via DR11-C + */ +unsigned char display_tablet = 0; + +/* + * can be changed with display_lp_radius() + */ +static long scaled_pen_radius_squared; + +/* run-time -- set by display_init() */ +static int xpoints, ypoints; +static int xpixels, ypixels; +static int refresh_rate; +static int refresh_interval; +static int ncolors; +static enum display_type display_type; +static int scale; + +/* + * relative brightness for each display level + * (all but last must be less than 1.0) + */ +static float level_scale[NLEVELS]; + +/* + * table of pointer to window system "colors" + * for painting each age level, intensity level and beam color + */ +void *colors[2][NLEVELS][NTTL]; + +void +display_lp_radius(int r) +{ + r /= scale; + scaled_pen_radius_squared = r * r; +} + +/* + * from display_age and display_point + * since all points age at the same rate, + * only adds points at end of list. + */ +static void +queue_point(struct point *p) +{ + int d; + + d = refresh_interval - queue_interval; + queue_interval += d; + /* queue_interval should now be == refresh_interval */ + +#ifdef PARANOIA + if (p->ttl == 0 || p->ttl > MAXTTL) + printf("queuing %d,%d level %d!\n", X(p), Y(p), p->level); + if (d > DELAY_T_MAX) + printf("queuing %d,%d delay %d!\n", X(p), Y(p), d); + if (queue_interval > DELAY_T_MAX) + printf("queue_interval (%d) > DELAY_T_MAX (%d)\n", + (int)queue_interval, DELAY_T_MAX); +#endif /* PARANOIA defined */ + + p->next = head; + p->prev = head->prev; + + head->prev->next = p; + head->prev = p; + + p->delay = d; +} + +/* + * here to to dynamically adjust interval for examination + * of elapsed vs. simulated time, and fritter away + * any extra wall-clock time without eating CPU + */ + +/* + * more parameters! + */ + +/* + * upper bound for elapsed time between elapsed time checks. + * if more than MAXELAPSED microseconds elapsed while simulating + * delay_check simulated microseconds, decrease delay_check. + */ +#define MAXELAPSED 100000 /* 10Hz */ + +/* + * lower bound for elapsed time between elapsed time checks. + * if fewer than MINELAPSED microseconds elapsed while simulating + * delay_check simulated microseconds, increase delay_check. + */ +#define MINELAPSED 50000 /* 20Hz */ + +/* + * upper bound for delay (sleep/poll). + * If difference between elapsed time and simulated time is + * larger than MAXDELAY microseconds, decrease delay_check. + * + * since delay is elapsed time - simulated time, MAXDELAY + * should be <= MAXELAPSED + */ +#ifndef MAXDELAY +#define MAXDELAY 100000 /* 100ms */ +#endif /* MAXDELAY not defined */ + +/* + * lower bound for delay (sleep/poll). + * If difference between elapsed time and simulated time is + * smaller than MINDELAY microseconds, increase delay_check. + * + * since delay is elapsed time - simulated time, MINDELAY + * should be <= MINELAPSED + */ +#ifndef MINDELAY +#define MINDELAY 50000 /* 50ms */ +#endif /* MINDELAY not defined */ + +/* + * Initial amount of simulated time to elapse before polling. + * Value is very low to ensure polling occurs on slow systems. + * Fast systems should ramp up quickly. + */ +#ifndef INITIAL_DELAY_CHECK +#define INITIAL_DELAY_CHECK 1000 /* 1ms */ +#endif /* INITIAL_DELAY_CHECK */ + +/* + * gain factor (2**-GAINSHIFT) for adjustment of adjustment + * of delay_check + */ +#ifndef GAINSHIFT +#define GAINSHIFT 3 /* gain=0.125 (12.5%) */ +#endif /* GAINSHIFT not defined */ + +static void +display_delay(int t, int slowdown) +{ + /* how often (in simulated us) to poll/check for delay */ + static unsigned long delay_check = INITIAL_DELAY_CHECK; + + /* accumulated simulated time */ + static unsigned long sim_time = 0; + unsigned long elapsed; + long delay; + + sim_time += t; + if (sim_time < delay_check) + return; + + elapsed = os_elapsed(); /* read and reset elapsed timer */ + if (elapsed == ~0L) { /* first time thru? */ + slowdown = 0; /* no adjustments */ + elapsed = sim_time; + } + + /* + * get delta between elapsed (real) time, and simulated time. + * if simulated time running faster, we need to slow things down (delay) + */ + if (slowdown) + delay = sim_time - elapsed; + else + delay = 0; /* just poll */ + +#ifdef DEBUG_DELAY2 + printf("sim %d elapsed %d delay %d\r\n", sim_time, elapsed, delay); +#endif + + /* + * Try to keep the elapsed (real world) time between checks for + * delay (and poll for window system events) bounded between + * MAXELAPSED and MINELAPSED. Also tries to keep + * delay/poll time bounded between MAXDELAY and MINDELAY -- large + * delays make the simulation spastic, while very small ones are + * inefficient (too many system calls) and tend to be inaccurate + * (operating systems have a certain granularity for time + * measurement, and when you try to sleep/poll for very short + * amounts of time, the noise will dominate). + * + * delay_check period may be adjusted often, and oscillate. There + * is no single "right value", the important things are to keep + * the delay time and max poll intervals bounded, and responsive + * to system load. + */ + if (elapsed > MAXELAPSED || delay > MAXDELAY) { + /* too much elapsed time passed, or delay too large; shrink interval */ + if (delay_check > 1) { + delay_check -= delay_check>>GAINSHIFT; +#ifdef DEBUG_DELAY + printf("reduced period to %d\r\n", delay_check); +#endif /* DEBUG_DELAY defined */ + } + } + else if ((elapsed < MINELAPSED) || (slowdown && (delay < MINDELAY))) { + /* too little elapsed time passed, or delta very small */ + int gain = delay_check>>GAINSHIFT; + if (gain == 0) + gain = 1; /* make sure some change made! */ + delay_check += gain; +#ifdef DEBUG_DELAY + printf("increased period to %d\r\n", delay_check); +#endif /* DEBUG_DELAY defined */ + } + if (delay < 0) + delay = 0; + /* else if delay < MINDELAY, clamp at MINDELAY??? */ + + /* poll for window system events and/or delay */ + ws_poll(NULL, delay); + + sim_time = 0; /* reset simulated time clock */ + + /* + * delay (poll/sleep) time included in next "elapsed" period + * (clock not reset after a delay) + */ +} /* display_delay */ + +/* + * here periodically from simulator to age pixels. + * + * calling often with small values will age a few pixels at a time, + * and assist with graceful aging of display, and pixel aging. + * + * values should be smaller than refresh_interval! + * + * returns true if anything on screen changed. + */ + +int +display_age(int t, /* simulated us since last call */ + int slowdown) /* slowdown to simulated speed */ +{ + struct point *p; + static int elapsed = 0; + int changed; + + if (!initialized && !display_init(DISPLAY_TYPE, PIX_SCALE)) + return 0; + + display_delay(t, slowdown); + + changed = 0; + + elapsed += t; + if (elapsed < DELAY_UNIT) + return 0; + + t = elapsed / DELAY_UNIT; + elapsed %= DELAY_UNIT; + + while ((p = head->next) != head) { + int x, y; + + /* look at oldest entry */ + if (p->delay > t) { /* further than our reach? */ + p->delay -= t; /* update head */ + queue_interval -= t; /* update span */ + break; /* quit */ + } + + x = X(p); + y = Y(p); +#ifdef PARANOIA + if (p->ttl == 0) + printf("BUG: age %d,%d ttl zero\n", x, y); +#endif /* PARANOIA defined */ + + /* dequeue point */ + p->prev->next = p->next; + p->next->prev = p->prev; + + t -= p->delay; /* lessen our reach */ + queue_interval -= p->delay; /* update queue span */ + + ws_display_point(x, y, colors[p->color][p->level][--p->ttl]); + changed = 1; + + /* queue it back up, unless we just turned it off! */ + if (p->ttl > 0) + queue_point(p); + } + return changed; +} /* display_age */ + +/* here from window system */ +void +display_repaint(void) { + struct point *p; + int x, y; + /* + * bottom to top, left to right. + */ + for (p = points, y = 0; y < ypixels; y++) + for (x = 0; x < xpixels; p++, x++) + if (p->ttl) + ws_display_point(x, y, colors[p->color][p->level][p->ttl-1]); + ws_sync(); +} + +/* (0,0) is lower left */ +static int +intensify(int x, /* 0..xpixels */ + int y, /* 0..ypixels */ + int level, /* 0..MAXLEVEL */ + int color) /* for VR20! 0 or 1 */ +{ + struct point *p; + int bleed; + + if (x < 0 || x >= xpixels || y < 0 || y >= ypixels) + return 0; /* limit to display */ + + p = P(x,y); + if (p->ttl) { /* currently lit? */ +#ifdef LOUD + printf("%d,%d old level %d ttl %d new %d\r\n", + x, y, p->level, p->ttl, level); +#endif /* LOUD defined */ + + /* unlink from delta queue */ + p->prev->next = p->next; + + if (p->next == head) + queue_interval -= p->delay; + else + p->next->delay += p->delay; + p->next->prev = p->prev; + } + + bleed = 0; /* no bleeding for now */ + + /* EXP: doesn't work... yet */ + /* if "recently" drawn, same or brighter, same color, make even brighter */ + if (p->ttl >= MAXTTL*2/3 && level >= p->level && p->color == color && + level < MAXLEVEL) + level++; + + /* + * this allows a dim beam to suck light out of + * a recently drawn bright spot!! + */ + if (p->ttl != MAXTTL || p->level != level || p->color != color) { + p->ttl = MAXTTL; + p->level = level; + p->color = color; /* save color even if monochrome */ + ws_display_point(x, y, colors[p->color][p->level][p->ttl-1]); + } + + queue_point(p); /* put at end of list */ + return bleed; +} + +int +display_point(int x, /* 0..xpixels (unscaled) */ + int y, /* 0..ypixels (unscaled) */ + int level, /* DISPLAY_INT_xxx */ + int color) /* for VR20! 0 or 1 */ +{ + long lx, ly; + + if (!initialized && !display_init(DISPLAY_TYPE, PIX_SCALE)) + return 0; + + /* scale x and y to the displayed number of pixels */ + /* handle common cases quickly */ + if (scale > 1) { + if (scale == 2) { + x >>= 1; + y >>= 1; + } + else { + x /= scale; + y /= scale; + } + } + +#if DISPLAY_INT_MIN > 0 + level -= DISPLAY_INT_MIN; /* make zero based */ +#endif + intensify(x, y, level, color); + /* no bleeding for now (used to recurse for neighbor points) */ + + if (ws_lp_x == -1 || ws_lp_y == -1) + return 0; + + lx = x - ws_lp_x; + ly = y - ws_lp_y; + return lx*lx + ly*ly <= scaled_pen_radius_squared; +} /* display_point */ + +/* + * calculate decay color table for a phosphor mixture + * must be called AFTER refresh_rate initialized! + */ +static void +phosphor_init(struct phosphor *phosphors, int nphosphors, int color) +{ + int ttl; + + /* for each display ttl level; newest to oldest */ + for (ttl = NTTL-1; ttl > 0; ttl--) { + struct phosphor *pp; + double rr, rg, rb; /* real values */ + + /* fractional seconds */ + double t = ((double)(NTTL-1-ttl))/refresh_rate; + + int ilevel; /* intensity levels */ + int p; + + /* sum over all phosphors in mixture */ + rr = rg = rb = 0.0; + for (pp = phosphors, p = 0; p < nphosphors; pp++, p++) { + double decay = pow(pp->level, t/pp->t_level); + rr += decay * pp->red; + rg += decay * pp->green; + rb += decay * pp->blue; + } + + /* scale for brightness for each intensity level */ + for (ilevel = MAXLEVEL; ilevel >= 0; ilevel--) { + int r, g, b; + void *cp; + + /* + * convert to 16-bit integer; clamp at 16 bits. + * this allows the sum of brightness factors across phosphors + * for each of R G and B to be greater than 1.0 + */ + + r = (int)(rr * level_scale[ilevel] * 0xffff); + if (r > 0xffff) r = 0xffff; + + g = (int)(rg * level_scale[ilevel] * 0xffff); + if (g > 0xffff) g = 0xffff; + + b = (int)(rb * level_scale[ilevel] * 0xffff); + if (b > 0xffff) b = 0xffff; + + cp = ws_color_rgb(r, g, b); + if (!cp) { /* allocation failed? */ + if (ttl == MAXTTL-1) { /* brand new */ + if (ilevel == MAXLEVEL) /* highest intensity? */ + cp = ws_color_white(); /* use white */ + else + cp = colors[color][ilevel+1][ttl]; /* use next lvl */ + } /* brand new */ + else if (r + g + b >= 0xffff*3/3) /* light-ish? */ + cp = colors[color][ilevel][ttl+1]; /* use previous TTL */ + else + cp = ws_color_black(); + } + colors[color][ilevel][ttl] = cp; + } /* for each intensity level */ + } /* for each TTL */ +} /* phosphor_init */ + +static struct display * +find_type(enum display_type type) +{ + int i; + struct display *dp; + for (i = 0, dp = displays; i < ELEMENTS(displays); i++, dp++) + if (dp->type == type) + return dp; + return NULL; +} + +int +display_init(enum display_type type, int sf) +{ + static int init_failed = 0; + struct display *dp; + int half_life; + int i; + + if (initialized) { + /* cannot change type once started */ + /* XXX say something???? */ + return type == display_type; + } + + if (init_failed) + return 0; /* avoid thrashing */ + + init_failed = 1; /* assume the worst */ + dp = find_type(type); + if (!dp) { + fprintf(stderr, "Unknown display type %d\r\n", (int)type); + goto failed; + } + + /* Initialize display list */ + head->next = head->prev = head; + + display_type = type; + scale = sf; + + xpoints = dp->xpoints; + ypoints = dp->ypoints; + + /* increase scale factor if won't fit on desktop? */ + xpixels = xpoints / scale; + ypixels = ypoints / scale; + + /* set default pen radius now that scale is set */ + display_lp_radius(PEN_RADIUS); + + ncolors = 1; + /* + * use function to calculate from looking at avg (max?) + * of phosphor half lives??? + */ +#define COLOR_HALF_LIFE(C) ((C)->half_life) + + half_life = COLOR_HALF_LIFE(dp->color0); + if (dp->color1) { + if (dp->color1->half_life > half_life) + half_life = COLOR_HALF_LIFE(dp->color1); + ncolors++; + } + + /* before phosphor_init; */ + refresh_rate = (1000000*LEVELS_PER_HALFLIFE)/half_life; + refresh_interval = 1000000/DELAY_UNIT/refresh_rate; + + /* + * sanity check refresh_interval + * calculating/selecting DELAY_UNIT at runtime might avoid this! + */ + + /* must be non-zero; interval of 1 means all pixels will age at once! */ + if (refresh_interval < 1) { + /* decrease DELAY_UNIT? */ + fprintf(stderr, "NOTE! refresh_interval too small: %d\r\n", + refresh_interval); + + /* dunno if this is a good idea, but might be better than dying */ + refresh_interval = 1; + } + + /* point lifetime in DELAY_UNITs will not fit in p->delay field! */ + if (refresh_interval > DELAY_T_MAX) { + /* increase DELAY_UNIT? */ + fprintf(stderr, "bad refresh_interval %d > DELAY_T_MAX %d\r\n", + refresh_interval, DELAY_T_MAX); + goto failed; + } + + /* + * before phosphor_init; + * set up relative brightness of display intensity levels + * (could differ for different hardware) + * + * linear for now. boost factor insures low intensities are visible + */ +#define BOOST 5 + for (i = 0; i < NLEVELS; i++) + level_scale[i] = ((float)i+1+BOOST)/(NLEVELS+BOOST); + + points = (struct point *)calloc((size_t)xpixels, + ypixels * sizeof(struct point)); + if (!points) + goto failed; + + if (!ws_init(dp->name, xpixels, ypixels, ncolors)) + goto failed; + + phosphor_init(dp->color0->phosphors, dp->color0->nphosphors, 0); + + if (dp->color1) + phosphor_init(dp->color1->phosphors, dp->color1->nphosphors, 1); + + initialized = 1; + init_failed = 0; /* hey, we made it! */ + return 1; + + failed: + fprintf(stderr, "Display initialization failed\r\n"); + return 0; +} + +void +display_reset(void) +{ + /* XXX tear down window? just clear it? */ +} + +void +display_sync(void) +{ + ws_sync(); +} + +void +display_beep(void) +{ + ws_beep(); +} + +int +display_xpoints(void) +{ + return xpoints; +} + +int +display_ypoints(void) +{ + return ypoints; +} + +int +display_scale(void) +{ + return scale; +} + +/* + * handle keyboard events + * + * data switches; 18 -- enough for PDP-1/4/7/9/15 (for munching squares!) + * 123 456 789 qwe rty uio + * bit toggled on key up + * all cleared on space + * + * spacewar switches; bit high as long as key down + * asdf kl;' + * just where PDP-1 spacewar expects them! + * key mappings same as MIT Media Lab Java PDP-1 simulator + * + */ +unsigned long spacewar_switches = 0; + +/* here from window system */ +void +display_keydown(int k) +{ + switch (k) { + case 'f': case 'F': spacewar_switches |= 01; break; /* torpedos */ + case 'd': case 'D': spacewar_switches |= 02; break; /* engines */ + case 'a': case 'A': spacewar_switches |= 04; break; /* rotate R */ + case 's': case 'S': spacewar_switches |= 010; break; /* rotate L */ + case '\'': case '"': spacewar_switches |= 040000; break; /* torpedos */ + case ';': case ':': spacewar_switches |= 0100000; break; /* engines */ + case 'k': case 'K': spacewar_switches |= 0200000; break; /* rotate R */ + case 'l': case 'L': spacewar_switches |= 0400000; break; /* rotate L */ + default: return; + } +} + +/* here from window system */ +void +display_keyup(int k) +{ + unsigned long test_switches = cpu_get_switches(); + + /* fetch console switches from simulator? */ + switch (k) { + case 'f': case 'F': spacewar_switches &= ~01; return; + case 'd': case 'D': spacewar_switches &= ~02; return; + case 'a': case 'A': spacewar_switches &= ~04; return; + case 's': case 'S': spacewar_switches &= ~010; return; + + case '\'': case '"': spacewar_switches &= ~040000; return; + case ';': case ':': spacewar_switches &= ~0100000; return; + case 'k': case 'K': spacewar_switches &= ~0200000; return; + case 'l': case 'L': spacewar_switches &= ~0400000; return; + + case '1': test_switches ^= 1<<17; break; + case '2': test_switches ^= 1<<16; break; + case '3': test_switches ^= 1<<15; break; + + case '4': test_switches ^= 1<<14; break; + case '5': test_switches ^= 1<<13; break; + case '6': test_switches ^= 1<<12; break; + + case '7': test_switches ^= 1<<11; break; + case '8': test_switches ^= 1<<10; break; + case '9': test_switches ^= 1<<9; break; + + case 'q': case 'Q': test_switches ^= 1<<8; break; + case 'w': case 'W': test_switches ^= 1<<7; break; + case 'e': case 'E': test_switches ^= 1<<6; break; + + case 'r': case 'R': test_switches ^= 1<<5; break; + case 't': case 'T': test_switches ^= 1<<4; break; + case 'y': case 'Y': test_switches ^= 1<<3; break; + + case 'u': case 'U': test_switches ^= 1<<2; break; + case 'i': case 'I': test_switches ^= 1<<1; break; + case 'o': case 'O': test_switches ^= 1; break; + + case ' ': test_switches = 0; break; + default: return; + } + cpu_set_switches(test_switches); +} diff --git a/display/display.h b/display/display.h new file mode 100644 index 00000000..94616b8f --- /dev/null +++ b/display/display.h @@ -0,0 +1,143 @@ +/* + * $Id: display.h,v 1.13 2004/01/24 08:34:33 phil Exp $ + * interface to O/S independent layer of XY display simulator + * Phil Budne + * September 2003 + * + * Changes from Douglas A. Gwyn, Jan 12, 2004 + */ + +/* + * Copyright (c) 2003-2004, Philip L. Budne + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the names of the authors shall + * not be used in advertising or otherwise to promote the sale, use or + * other dealings in this Software without prior written authorization + * from the authors. + */ + +/* + * known display types + */ +enum display_type { + DIS_VR14 = 14, + DIS_VR17 = 17, + DIS_VR20 = 20, + DIS_TYPE30 = 30, + DIS_TX0 = 33, + DIS_VR48 = 48, + DIS_TYPE340 = 340 +}; + +/* + * display scale factors + */ +#define RES_FULL 1 +#define RES_HALF 2 +#define RES_QUARTER 4 +#define RES_EIGHTH 8 + +/* + * must be called before first call to display_age() + * (but called implicitly by display_point()) + */ +extern int display_init(enum display_type, int scale); + +/* return size of virtual display */ +extern int display_xpoints(void); +extern int display_ypoints(void); + +/* virtual points between display and menu sections */ +#define VR48_GUTTER 8 /* just a guess */ + +/* conversion factor from virtual points and displayed pixels */ +extern int display_scale(void); + +/* + * simulate passage of time; first argument is simulated microseconds elapsed, + * second argument is flag to slow down simulated speed + * see comments in display.c for why you should call it often!! + * Under X11 polls for window events!! + */ +extern int display_age(int,int); + +/* + * display intensity levels. + * always at least 8 (for VT11/VS60) -- may be mapped internally + */ +#define DISPLAY_INT_MAX 7 +#define DISPLAY_INT_MIN 0 /* lowest "on" level */ + +/* + * plot a point; argumen ts are x, y, intensity, color (0/1) + * returns true if light pen active (mouse button down) + * at (or very near) this location. + * + * Display initialized on first call. + */ +extern int display_point(int,int,int,int); + +/* + * force window system to output bits to screen; + * call after adding points, or aging the screen + */ +extern void display_sync(void); + +/* + * currently a noop + */ +extern void display_reset(void); + +/* + * ring the bell + */ +extern void display_beep(void); + +/* + * Set light-pen radius; maximum radius in display coordinates + * from a "lit" location that the light pen will see. + */ +extern void display_lp_radius(int); + +/* + * set by simulated spacewar switch box switches + * 18 bits (only high 4 and low 4 used) + */ +extern unsigned long spacewar_switches; + +/* + * light pen "tip switch" activated (for VS60 emulation etc.) + * should only be set from "driver" (window system layer) + */ +extern unsigned char display_lp_sw; + +/* + * deactivates light pen + * (SIMH DR11-C simulation when initialized sets this and + * then reports mouse coordinates as Talos digitizer data) + */ +extern unsigned char display_tablet; + +/* + * users of this library are expected to provide these calls. + * simulator will set 18 simulated switches. + */ +extern unsigned long cpu_get_switches(void); /* get current switch state */ +extern void cpu_set_switches(unsigned long); /* set switches */ diff --git a/display/gmakefile b/display/gmakefile new file mode 100644 index 00000000..4ef7b28e --- /dev/null +++ b/display/gmakefile @@ -0,0 +1,77 @@ +# $Id: gmakefile,v 1.17 2004/01/24 08:31:56 phil Exp - revised by DAG + +# (GNU) Makefile for test programs under Unix/X11 and Win32 +# +# Unix: +# edit Unix defs to fit your compiler/library environment, then +# gmake -f gmakefile +# or if GNU make is the default: +# make -f gmakefile +# +# Win32 (Cygwin) +# make WIN32=1 +# +# Win32 (MINGW): +# mingw32-make -f gmakefile WIN32=1 + +DISP_DEFS=-DTEST_DIS=DIS_VR48 -DTEST_RES=RES_HALF # -DDEBUG_VT11 + +ifeq ($(WIN32),) +#Unix environments +X11BASE=/usr/X11R6 +X11LIBDIR=$(X11BASE)/lib +X11INCDIR=$(X11BASE)/include +LIBS=-L$(X11LIBDIR) -lXt -lX11 -lm +OSFLAGS=-I$(X11INCDIR) +DRIVER=x11.o +EXT= +else +#Win32 environments +LIBS=-lgdi32 +OSFLAGS= +DRIVER=win32.o +EXT=.exe +endif + +#PROF=-g # -pg +OPT=-O2 +CFLAGS=$(OPT) $(PROF) $(OSFLAGS) $(DISP_DEFS) +CC=gcc -Wunused +LDFLAGS=$(PROF) + +ALL= munch$(EXT) vt11$(EXT) +ALL: $(ALL) + +# munching squares; see README file for +# how to use console switches + +MUNCH=$(DRIVER) display.o test.o +munch$(EXT): $(MUNCH) + $(CC) $(LDFLAGS) -o munch$(EXT) $(MUNCH) $(LIBS) + +VT11=$(DRIVER) vt11.o vttest.o display.o +vt11$(EXT): $(VT11) + $(CC) $(LDFLAGS) -o vt11$(EXT) $(VT11) $(LIBS) + +display.o: display.h ws.h +vt11.o: display.h vt11.h +x11.o: ws.h display.h +win32.o: ws.h +test.o: display.h vt11.h +vttest.o: display.h vt11.h vtmacs.h + +clean: +ifeq ($(WIN32),) + rm -f *.o *~ .#* +else + if exist *.o del /q *.o + if exist *~ del /q *~ + if exist .#* del /q .#* +endif + +clobber: clean +ifeq ($(WIN32),) + rm -f $(ALL) +else + if exist *.exe del /q *.exe +endif diff --git a/display/smakefile b/display/smakefile new file mode 100644 index 00000000..0956a917 --- /dev/null +++ b/display/smakefile @@ -0,0 +1,75 @@ +# $Id: smakefile,v 1.17 2004/01/24 08:31:56 phil Exp - revised by DAG + +# Makefile for test programs (standard Unix "make" version) + +# Unix: +# comment out Windows defs, uncomment Unix defs, +# edit Unix defs to fit your compiler/library environment, then +# (g)make +# +# Win32 (Cygwin) +# comment out Unix defs, uncomment Windows defs, then +# make +# +# Win32 (MINGW) +# comment out Unix defs, uncomment Windows defs, then +# mingw32-make + +DISP_DEFS=-DTEST_DIS=DIS_VR48 -DTEST_RES=RES_HALF # -DDEBUG_VT11 + +#Unix environments +CC=cc # gcc -Wunused +#X11BASE=/usr/X11R6 +#X11LIBDIR=$(X11BASE)/lib +#X11INCDIR=$(X11BASE)/include +LIBS=-lXt -lX11 -lm # -L$(X11LIBDIR) +OSFLAGS=-I$(X11INCDIR) +DRIVER=x11.o +EXT= +PROF=-g # -pg +OPT=-O # -O2 +CFLAGS=$(OPT) $(PROF) $(OSFLAGS) $(DISP_DEFS) +CC=cc # gcc -Wunused +LDFLAGS=$(PROF) + +##Win32 environments +#LIBS=-lgdi32 +#OSFLAGS= +#DRIVER=win32.o +#EXT=.exe +#PROF=-g # -pg +#OPT=-O2 +#CFLAGS=$(OPT) $(PROF) $(OSFLAGS) $(DISP_DEFS) +#CC=gcc -Wunused +LDFLAGS=$(PROF) + +ALL= munch$(EXT) vt11$(EXT) +ALL: $(ALL) + +# munching squares; see README file for +# how to use console switches + +MUNCH=$(DRIVER) display.o test.o +munch$(EXT): $(MUNCH) + $(CC) $(LDFLAGS) -o munch$(EXT) $(MUNCH) $(LIBS) + +VT11=$(DRIVER) vt11.o vttest.o display.o +vt11$(EXT): $(VT11) + $(CC) $(LDFLAGS) -o vt11$(EXT) $(VT11) $(LIBS) + +display.o: display.h ws.h +vt11.o: display.h vt11.h +x11.o: ws.h display.h +win32.o: ws.h +test.o: display.h vt11.h +vttest.o: display.h vt11.h vtmacs.h + +clean: + rm -f *.o *~ .#* # Unix +# if exist *.o del /q *.o # Win32 +# if exist *~ del /q *~ # Win32 +# if exist .#* del /q .#* # Win32 + +clobber: clean + rm -f $(ALL) # Unix +# if exist *.exe del /q *.exe # Win32 diff --git a/display/test.c b/display/test.c new file mode 100644 index 00000000..5b5b6438 --- /dev/null +++ b/display/test.c @@ -0,0 +1,192 @@ +/* + * $Id: test.c,v 1.23 2004/02/07 06:31:20 phil Exp $ + * XY Display simulator test program (PDP-1 Munching Squares) + * Phil Budne + * September 2003 + * + * Updates from Douglas A. Gwyn, 12 Jan. 2004 + * + * With thanks to Daniel Smith for his web page: + * http://world.std.com/~dpbsmith/munch.html + */ + +/* + * Copyright (c) 2003-2004, Philip L. Budne + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the names of the authors shall + * not be used in advertising or otherwise to promote the sale, use or + * other dealings in this Software without prior written authorization + * from the authors. + */ + +#ifndef TEST_DIS +#define TEST_DIS DIS_TYPE30 +#endif + +#ifndef TEST_RES +#define TEST_RES RES_HALF +#endif + +#include +#include + +#ifndef EXIT_FAILURE +/* SunOS4 doesn't define this */ +#define EXIT_FAILURE 1 +#endif + +#include "display.h" + +static unsigned long test_switches = 0; + +/* called from display code: */ +unsigned long +cpu_get_switches(void) { + return test_switches; +} + +/* called from display code: */ +void +cpu_set_switches(bits) + unsigned long bits; +{ + printf("switches: %06lo\n", bits); + test_switches = bits; +} + +void +munch(void) { + static long us = 0; + static long io = 0, v = 0; + long ac; + int x, y; + + ac = test_switches; + ac += v; /* add v */ + if (ac & ~0777777) { + ac++; + ac &= 0777777; + } + v = ac; /* dac v */ + + ac <<= 9; /* rcl 9s */ + io <<= 9; + io |= ac>>18; + ac &= 0777777; + ac |= io>>18; + io &= 0777777; + + ac ^= v; /* xor v */ + + /* convert +/-512 one's complement to 0..1022, origin in lower left */ + y = (io >> 8) & 01777; /* hi 10 */ + if (y & 01000) + y ^= 01000; + else + y += 511; + + x = (ac >> 8) & 01777; /* hi 10 */ + if (x & 01000) /* negative */ + x ^= 01000; + else + x += 511; + + if (display_point(x, y, DISPLAY_INT_MAX, 0)) + printf("light pen hit at (%d,%d)\n", x, y); + +/*#define US 100000 /* 100ms (10/sec) */ +/*#define US 50000 /* 50ms (20/sec) */ +/*#define US 20000 /* 20ms (50/sec) */ +/*#define US 10000 /* 10ms (100/sec) */ +#define US 0 + us += 50; /* 10 5us PDP-1 memory cycles */ + if (us >= US) { + display_age(us, 1); + us = 0; + } + display_sync(); /* XXX push down */ +} + +#ifdef T2 +/* display all window system level intensities; + * must be compiled with -DINTENSITIES= -DT2 + */ +void +t2(void) { + int x, y; + + display_init(TEST_DIS, TEST_RES); + for (x = INTENSITIES-1; x >= 0; x--) { + for (y = 0; y < 20; y++) { + ws_display_point(x*4, y, x, 0); + ws_display_point(x*4+1, y, x, 0); + ws_display_point(x*4+2, y, x, 0); + ws_display_point(x*4+3, y, x, 0); + } + display_sync(); + } + fflush(stdout); + for (;;) + /* wait */ ; +} +#endif + +#ifdef T3 +/* display all "user" level intensities; + * must be compiled with -DINTENSITIES= -DT3 + * + * skip every other virtual point on both axes + * default scaling maps adjacent pixels and + * causes re-intensification! + */ +void +t3(void) { + int x, y; + + display_init(TEST_DIS, TEST_RES); + for (x = DISPLAY_INT_MAX; x >= 0; x--) { + for (y = 0; y < 20; y++) { + display_point(x*2, y*2, x, 0); + } + display_sync(); + } + fflush(stdout); + for (;;) + /* wait */ ; +} +#endif + +int +main(void) { + if (!display_init(TEST_DIS, TEST_RES)) + exit(EXIT_FAILURE); + + cpu_set_switches(04000UL); /* classic starting value */ + for (;;) { +#ifdef T2 + t2(); +#endif +#ifdef T3 + t3(); +#endif + munch(); + } + /*NOTREACHED*/ +} diff --git a/display/type340.c b/display/type340.c new file mode 100644 index 00000000..7ac9eb9a --- /dev/null +++ b/display/type340.c @@ -0,0 +1,706 @@ +/* + * $Id: type340.c,v 1.5 2004/01/24 20:52:16 phil Exp $ + * Simulator Independent DEC Type 340 Graphic Display Processor Simulation + * Phil Budne + * September 20, 2003 + * from vt11.c + * + * Information from DECUS 7-13 + * http://www.spies.com/~aek/pdf/dec/pdp7/7-13_340displayProgMan.pdf + */ + +/* + * Copyright (c) 2003-2004, Philip L. Budne + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the author shall + * not be used in advertising or otherwise to promote the sale, use or + * other dealings in this Software without prior written authorization + * from the authors. + */ + +#include "display.h" /* XY plot interface */ + +/* + * The Type 340 was used on the PDP-{4,6,7,9,10} + * and used 18-bit words, with bits numbered 0 thru 17 + * (most significant to least) + */ + +#define BITMASK(N) (1<<(17-(N))) + +/* mask for a field */ +#define FIELDMASK(START,END) ((1<<((END)-(START)+1))-1) + +/* extract a field */ +#define GETFIELD(W,START,END) (((W)>>(17-(END)))&FIELDMASK(START,END)) + +/* extract a 1-bit field */ +#define TESTBIT(W,B) (((W) & BITMASK(B)) != 0) + +#ifdef DEBUG_TY340 +#define DEBUGF(X) printf X +#else +#define DEBUGF(X) +#endif + +typedef long ty340word; + +static ty340word DAC; /* Display Address Counter */ +static unsigned char shift; /* 1 bit */ +static enum mode mode; /* 3 bits */ +static int scale; /* 2 bits */ + +enum mode { PARAM=0, POINT, SLAVE, CHAR, VECTOR, VCONT, INCR, SUBR }; + +enum jump_type { DJP=2, DJS=3, DDS=1 }; +static ty340word ASR; /* Address Save Register */ +static unsigned char save_ff; /* "save" flip-flop */ + +static unsigned char intensity; /* 3 bits */ +static unsigned char lp_ena; /* 1 bit */ + +/* kept signed for raster violation checking */ +static short xpos, ypos; /* 10 bits, signed */ +static unsigned char sequence; /* 2 bits */ + +/* XXX make defines public for 340_cycle return */ +#define STOPPED 01 +#define LPHIT 02 +#define VEDGE 04 +#define HEDGE 010 +static unsigned char status = STOPPED; + +/* + * callbacks into PDP-6/10 simulator + */ +extern ty340word ty340_fetch(ty340word); +extern void ty340_store(ty340word, ty340word); +extern void ty340_stop_int(void); +extern void ty340_lp_int(void); + +void +ty340_set_dac(ty340word addr) +{ + DAC = addr; + mode = 0; + DEBUGF(("set DAC %06\r\n", DAC)); + status = 0; /* XXX just clear stopped? */ + /* XXX clear other stuff? save_ff? */ +} + +void +ty340_reset(void) +{ + /* XXX call display layer? destroy window? */ + xpos = ypos = 0; + status = STOPPED; +} + +static int +point(int x, int y, int seq) +{ + int i; + + /* XXX apply scale? */ + + i = DISPLAY_INT_MAX-7+intensity; + if (i <= 0) + i = 1; + + if (x < 0 || x > 1023) { + status |= VEDGE; + return 0; + } + if (y < 0 || y > 1023) { + status |= HEDGE; + return 0; + } + + if (display_point(x, y, i, 0)) { + if (lp_ena) { + /* XXX save location? */ + status |= LPHIT; + sequence = seq; + } + } +} + +/* + * two-step algorithm, developed by Xiaolin Wu + * from http://graphics.lcs.mit.edu/~mcmillan/comp136/Lecture6/Lines.html + */ + +/* + * The two-step algorithm takes the interesting approach of treating + * line drawing as a automaton, or finite state machine. If one looks + * at the possible configurations for the next two pixels of a line, + * it is easy to see that only a finite set of possibilities exist. + * The two-step algorithm shown here also exploits the symmetry of + * line-drawing by simultaneously drawn from both ends towards the + * midpoint. + */ + +static void +lineTwoStep(int x0, int y0, int x1, int y1) +{ + int dy = y1 - y0; + int dx = x1 - x0; + int stepx, stepy; + + if (dy < 0) { dy = -dy; stepy = -1; } else { stepy = 1; } + if (dx < 0) { dx = -dx; stepx = -1; } else { stepx = 1; } + + lpoint(x0,y0); + if (dx == 0 && dy == 0) /* following algorithm won't work */ + return; /* just the one dot */ + lpoint(x1, y1); + if (dx > dy) { + int length = (dx - 1) >> 2; + int extras = (dx - 1) & 3; + int incr2 = (dy << 2) - (dx << 1); + if (incr2 < 0) { + int c = dy << 1; + int incr1 = c << 1; + int d = incr1 - dx; + int i; + + for (i = 0; i < length; i++) { + x0 += stepx; + x1 -= stepx; + if (d < 0) { /* Pattern: */ + lpoint(x0, y0); + lpoint(x0 += stepx, y0); /* x o o */ + lpoint(x1, y1); + lpoint(x1 -= stepx, y1); + d += incr1; + } + else { + if (d < c) { /* Pattern: */ + lpoint(x0, y0); /* o */ + lpoint(x0 += stepx, y0 += stepy); /* x o */ + lpoint(x1, y1); + lpoint(x1 -= stepx, y1 -= stepy); + } else { + lpoint(x0, y0 += stepy); /* Pattern: */ + lpoint(x0 += stepx, y0); /* o o */ + lpoint(x1, y1 -= stepy); /* x */ + lpoint(x1 -= stepx, y1); + } + d += incr2; + } + } + if (extras > 0) { + if (d < 0) { + lpoint(x0 += stepx, y0); + if (extras > 1) lpoint(x0 += stepx, y0); + if (extras > 2) lpoint(x1 -= stepx, y1); + } else + if (d < c) { + lpoint(x0 += stepx, y0); + if (extras > 1) lpoint(x0 += stepx, y0 += stepy); + if (extras > 2) lpoint(x1 -= stepx, y1); + } else { + lpoint(x0 += stepx, y0 += stepy); + if (extras > 1) lpoint(x0 += stepx, y0); + if (extras > 2) lpoint(x1 -= stepx, y1 -= stepy); + } + } + } else { + int c = (dy - dx) << 1; + int incr1 = c << 1; + int d = incr1 + dx; + int i; + for (i = 0; i < length; i++) { + x0 += stepx; + x1 -= stepx; + if (d > 0) { + lpoint(x0, y0 += stepy); /* Pattern: */ + lpoint(x0 += stepx, y0 += stepy); /* o */ + lpoint(x1, y1 -= stepy); /* o */ + lpoint(x1 -= stepx, y1 -= stepy); /* x */ + d += incr1; + } else { + if (d < c) { + lpoint(x0, y0); /* Pattern: */ + lpoint(x0 += stepx, y0 += stepy); /* o */ + lpoint(x1, y1); /* x o */ + lpoint(x1 -= stepx, y1 -= stepy); + } else { + lpoint(x0, y0 += stepy); /* Pattern: */ + lpoint(x0 += stepx, y0); /* o o */ + lpoint(x1, y1 -= stepy); /* x */ + lpoint(x1 -= stepx, y1); + } + d += incr2; + } + } + if (extras > 0) { + if (d > 0) { + lpoint(x0 += stepx, y0 += stepy); + if (extras > 1) lpoint(x0 += stepx, y0 += stepy); + if (extras > 2) lpoint(x1 -= stepx, y1 -= stepy); + } else if (d < c) { + lpoint(x0 += stepx, y0); + if (extras > 1) lpoint(x0 += stepx, y0 += stepy); + if (extras > 2) lpoint(x1 -= stepx, y1); + } else { + lpoint(x0 += stepx, y0 += stepy); + if (extras > 1) lpoint(x0 += stepx, y0); + if (extras > 2) { + if (d > c) + lpoint(x1 -= stepx, y1 -= stepy); + else + lpoint(x1 -= stepx, y1); + } + } + } + } + } else { + int length = (dy - 1) >> 2; + int extras = (dy - 1) & 3; + int incr2 = (dx << 2) - (dy << 1); + if (incr2 < 0) { + int c = dx << 1; + int incr1 = c << 1; + int d = incr1 - dy; + int i; + for (i = 0; i < length; i++) { + y0 += stepy; + y1 -= stepy; + if (d < 0) { + lpoint(x0, y0); + lpoint(x0, y0 += stepy); + lpoint(x1, y1); + lpoint(x1, y1 -= stepy); + d += incr1; + } else { + if (d < c) { + lpoint(x0, y0); + lpoint(x0 += stepx, y0 += stepy); + lpoint(x1, y1); + lpoint(x1 -= stepx, y1 -= stepy); + } else { + lpoint(x0 += stepx, y0); + lpoint(x0, y0 += stepy); + lpoint(x1 -= stepx, y1); + lpoint(x1, y1 -= stepy); + } + d += incr2; + } + } + if (extras > 0) { + if (d < 0) { + lpoint(x0, y0 += stepy); + if (extras > 1) lpoint(x0, y0 += stepy); + if (extras > 2) lpoint(x1, y1 -= stepy); + } else + if (d < c) { + lpoint(x0, y0 += stepy); + if (extras > 1) lpoint(x0 += stepx, y0 += stepy); + if (extras > 2) lpoint(x1, y1 -= stepy); + } else { + lpoint(x0 += stepx, y0 += stepy); + if (extras > 1) lpoint(x0, y0 += stepy); + if (extras > 2) lpoint(x1 -= stepx, y1 -= stepy); + } + } + } else { + int c = (dx - dy) << 1; + int incr1 = c << 1; + int d = incr1 + dy; + int i; + for (i = 0; i < length; i++) { + y0 += stepy; + y1 -= stepy; + if (d > 0) { + lpoint(x0 += stepx, y0); + lpoint(x0 += stepx, y0 += stepy); + lpoint(x1 -= stepy, y1); + lpoint(x1 -= stepx, y1 -= stepy); + d += incr1; + } else { + if (d < c) { + lpoint(x0, y0); + lpoint(x0 += stepx, y0 += stepy); + lpoint(x1, y1); + lpoint(x1 -= stepx, y1 -= stepy); + } else { + lpoint(x0 += stepx, y0); + lpoint(x0, y0 += stepy); + lpoint(x1 -= stepx, y1); + lpoint(x1, y1 -= stepy); + } + d += incr2; + } + } + if (extras > 0) { + if (d > 0) { + lpoint(x0 += stepx, y0 += stepy); + if (extras > 1) lpoint(x0 += stepx, y0 += stepy); + if (extras > 2) lpoint(x1 -= stepx, y1 -= stepy); + } else if (d < c) { + lpoint(x0, y0 += stepy); + if (extras > 1) lpoint(x0 += stepx, y0 += stepy); + if (extras > 2) lpoint(x1, y1 -= stepy); + } else { + lpoint(x0 += stepx, y0 += stepy); + if (extras > 1) lpoint(x0, y0 += stepy); + if (extras > 2) { + if (d > c) + lpoint(x1 -= stepx, y1 -= stepy); + else + lpoint(x1, y1 -= stepy); + } + } + } + } + } +} /* lineTwoStep */ + +static int +vector(int i, int sx, int dx, int sy, int dy) +{ + int x0, y0, x1, y1; + + x0 = xpos; + y0 = ypos; + + if (sx) { + x1 = x0 - dx; + if (x1 < 0) /* XXX TEMP? */ + x1 = 0; + } + else { + x1 = x0 + dx; + if (x1 > 1023) /* XXX TEMP? */ + x1 = 1023; + } + + if (sy) { + y1 = y0 - dy; + if (y1 < 0) /* XXX TEMP? */ + y1 = 0; + } + else { + y1 = y0 + dy; /* XXX TEMP? */ + if (y1 > 1023) + y1 = 1023; + } + + DEBUGF(("vector i%d (%d,%d) to (%d,%d)\r\n", i, x0, y0, x1, y1)); + if (i) + lineTwoStep(x0, y0, x1, y1); + + xpos = x1; + ypos = y1; + return 0; +} + +/* return true on raster violation */ +int +ipoint(int i, int n, unsigned char byte) +{ + if (byte & 010) { /* left/right */ + if (byte & 04) { + if (xpos == 0) { + status |= VEDGE; + return 1; + } + xpos--; + } + else { + if (xpos == 1023) { + status |= VEDGE; + return 1; + } + xpos++; + } + } + if (byte & 02) { /* up/down */ + if (byte & 04) { + if (ypos == 0) { + status |= HEDGE; + return 1; + } + ypos--; + } + else { + if (ypos == 1023) { + status |= HEDGE; + return 1; + } + ypos++; + } + } + if (i) + point(xpos, ypos, n); + + return 0; +} + +/* + * 342 character generator - first 64 characters (from manual) + */ +static const unsigned char chars[64][5] = { + { 0070, 0124, 0154, 0124, 0070 }, /* 00 */ + { 0174, 0240, 0240, 0240, 0174 }, /* 01 A */ + { 0376, 0222, 0222, 0222, 0154 }, /* 02 B */ + { 0174, 0202, 0202, 0202, 0104 }, /* 03 C */ + { 0376, 0202, 0202, 0202, 0174 }, /* 04 D */ + { 0376, 0222, 0222, 0222, 0222 }, /* 05 E */ + { 0376, 0220, 0220, 0220, 0220 }, /* 06 F */ + { 0174, 0202, 0222, 0222, 0134 }, /* 07 G */ + { 0376, 0020, 0020, 0020, 0376 }, /* 10 H */ + { 0000, 0202, 0376, 0202, 0000 }, /* 11 I */ + { 0004, 0002, 0002, 0002, 0374 }, /* 12 J */ + { 0376, 0020, 0050, 0104, 0202 }, /* 13 K */ + { 0376, 0002, 0002, 0002, 0002 }, /* 14 K */ + { 0374, 0100, 0040, 0100, 0374 }, /* 15 M */ + { 0376, 0100, 0040, 0020, 0376 }, /* 16 N */ + { 0174, 0202, 0202, 0202, 0174 }, /* 17 O */ + { 0376, 0220, 0220, 0220, 0140 }, /* 20 P */ + { 0174, 0202, 0212, 0206, 0176 }, /* 21 Q */ + { 0376, 0220, 0230, 0224, 0142 }, /* 22 R */ + { 0144, 0222, 0222, 0222, 0114 }, /* 23 S */ + { 0200, 0200, 0376, 0200, 0200 }, /* 24 T */ + { 0374, 0002, 0002, 0002, 0374 }, /* 25 U */ + { 0370, 0004, 0002, 0004, 0370 }, /* 26 V */ + { 0376, 0004, 0010, 0004, 0376 }, /* 27 W */ + { 0202, 0104, 0070, 0104, 0202 }, /* 30 X */ + { 0200, 0100, 0076, 0100, 0200 }, /* 31 Y */ + { 0226, 0232, 0222, 0262, 0322 }, /* 32 Z */ + { 0000, 0000, 0000, 0000, 0000 }, /* 33 LF */ + { 0000, 0000, 0000, 0000, 0000 }, /* 34 CR */ + { 0000, 0000, 0000, 0000, 0000 }, /* 35 HORIZ */ + { 0000, 0000, 0000, 0000, 0000 }, /* 36 VERT */ + { 0000, 0000, 0000, 0000, 0000 }, /* 37 ESC */ + { 0000, 0000, 0000, 0000, 0000 }, /* 40 space */ + { 0000, 0000, 0372, 0000, 0000 }, /* 41 ! */ + { 0000, 0340, 0000, 0340, 0000 }, /* 42 " */ + { 0050, 0376, 0050, 0376, 0050 }, /* 43 # */ + { 0144, 0222, 0376, 0222, 0114 }, /* 44 $ */ + { 0306, 0310, 0220, 0246, 0306 }, /* 45 % */ + { 0154, 0222, 0156, 0004, 0012 }, /* 46 & */ + { 0000, 0000, 0300, 0340, 0000 }, /* 47 ' */ + { 0070, 0104, 0202, 0000, 0000 }, /* 50 ( */ + { 0000, 0000, 0202, 0104, 0070 }, /* 51 ) */ + { 0124, 0070, 0174, 0070, 0124 }, /* 52 * */ + { 0020, 0020, 0174, 0020, 0020 }, /* 53 + */ + { 0000, 0014, 0016, 0000, 0000 }, /* 54 , */ + { 0020, 0020, 0020, 0020, 0020 }, /* 55 - */ + { 0000, 0006, 0006, 0000, 0000 }, /* 56 . */ + { 0004, 0010, 0020, 0040, 0100 }, /* 57 / */ + { 0174, 0212, 0222, 0242, 0174 }, /* 60 0 */ + { 0000, 0102, 0376, 0002, 0000 }, /* 61 1 */ + { 0116, 0222, 0222, 0222, 0142 }, /* 62 2 */ + { 0104, 0202, 0222, 0222, 0154 }, /* 63 3 */ + { 0020, 0060, 0120, 0376, 0020 }, /* 64 4 */ + { 0344, 0222, 0222, 0222, 0214 }, /* 65 5 */ + { 0174, 0222, 0222, 0222, 0114 }, /* 66 6 */ + { 0306, 0210, 0220, 0240, 0300 }, /* 67 7 */ + { 0154, 0222, 0222, 0222, 0154 }, /* 70 8 */ + { 0144, 0222, 0222, 0222, 0174 }, /* 71 9 */ + { 0000, 0066, 0066, 0000, 0000 }, /* 72 : */ + { 0000, 0154, 0156, 0000, 0000 }, /* 73 ; */ + { 0020, 0050, 0104, 0202, 0000 }, /* 74 < */ + { 0050, 0050, 0050, 0050, 0050 }, /* 75 = */ + { 0000, 0202, 0104, 0050, 0020 }, /* 76 > */ + { 0100, 0200, 0236, 0220, 0140 } /* 77 ? */ +}; + +/* + * type 342 Character/Symbol generator for type 340 display + * return true if ESCaped + */ +static int +character(int n, char c) +{ + int x, y; + + switch (c) { + case 033: /* LF */ + if (ypos < 12) { + status |= HEDGE; + ypos = 0; + } + else + ypos -= 12; /* XXX scale? */ + + return 0; + case 034: /* CR */ + xpos = 0; + return 0; + case 035: /* shift in */ + shift = 1; + return 0; + case 036: /* shift out */ + shift = 0; + return 0; + case 037: /* escape */ + sequence = n; + return 1; + } + /* XXX plot character from character set selected by "shift" + * (offset index by 64?) + */ + for (x = 0; x < 5; x++) { + for (y = 0; y < 7; y++) { + if (chars[c][x] & (1< 1023) { + xpos = 1023; + status |= VEDGE; + } + return 0; +} + +int +ty340_cycle(int us, int slowdown) +{ + ty340word inst, addr; + int i, escape, stopped; + + if (status & STOPPED) + return 0; /* XXX age display? */ + + inst = ty340_fetch(DAC); + DEBUGF(("%06o: %06o\r\n", DAC, inst)); + DAC++; + + escape = 0; + switch (mode) { + case PARAM: + mode = GETFIELD(inst, 2, 4); + + if (TESTBIT(inst, 5)) { /* load l.p. enable */ + lp_ena = TESTBIT(inst,6); + DEBUGF(("lp_ena %d\r\n", lp_ena)); + } + + if (TESTBIT(inst, 7)) { + status |= STOPPED; + if (TESTBIT(inst, 8)) + ty340_stop_int(); /* set stop_int_end? */ + } + + if (TESTBIT(inst, 11)) + scale = GETFIELD(inst, 12, 13); + + if (TESTBIT(inst, 14)) + intensity = GETFIELD(inst, 15, 17); + + break; + + case POINT: + mode = GETFIELD(inst, 2, 4); + + if (TESTBIT(inst, 5)) /* load l.p. enable */ + lp_ena = TESTBIT(inst,6); + + if (TESTBIT(inst, 1)) + ypos = GETFIELD(inst, 8, 17); + else + xpos = GETFIELD(inst, 8, 17); + + if (TESTBIT(inst, 7)) + point(xpos, ypos, 0); + break; + + case SLAVE: + mode = GETFIELD(inst, 2, 4); + break; + + case CHAR: + escape = (character(0, GETFIELD(inst, 0, 5)) || + character(1, GETFIELD(inst, 6, 11)) || + character(2, GETFIELD(inst, 12, 17))); + break; + + case VECTOR: + escape = TESTBIT(inst, 0); + if (vector(TESTBIT(inst, 1), + TESTBIT(inst, 2), GETFIELD(inst, 3, 9), + TESTBIT(inst, 10), GETFIELD(inst, 11, 17))) { + /* XXX interrupt? */ + } + break; + case VCONT: + escape = TESTBIT(inst, 0); + if (vector(TESTBIT(inst, 1), + TESTBIT(inst, 2), GETFIELD(inst, 3, 9), + TESTBIT(inst, 10), GETFIELD(inst, 11, 17))) { + /* XXX set escape? */ + mode = PARAM; /* raster violation */ + } + break; + + case INCR: + escape = TESTBIT(inst, 0); /* escape bit */ + i = TESTBIT(inst, 1); + + if (ipoint(i, 0, GETFIELD(inst, 2, 5)) || + ipoint(i, 1, GETFIELD(inst, 6, 9)) || + ipoint(i, 2, GETFIELD(inst, 10, 13)) || + ipoint(i, 3, GETFIELD(inst, 14, 17))) + /* XXX set escape? */ + mode = PARAM; /* raster violation */ + break; + + case SUBR: + /* type 347 Display Subroutine Option? */ + + mode = GETFIELD(inst, 2, 4); + /* XXX take high bits of current DAC? */ + addr = GETFIELD(inst, 5, 17); + + switch (GETFIELD(inst, 0, 1)) { + case DJS: /* display jump and save */ + ASR = DAC; + save_ff = 1; /* set "save" flip-flop */ + /* FALL */ + case DJP: /* display jump */ + DAC = addr; + break; + case DDS: /* display deposit save register */ + ty340_deposit(addr, (DJP<<16) | ASR); + save_ff = 0; /* ?? */ + break; + default: + /* XXX ??? */ + break; + } + break; + } + + if (escape) { + mode = PARAM; + if (save_ff) { + /* return from subroutine */ + DAC = ASR; + save_ff = 0; + } + } + return status; +} /* ty340_cycle */ diff --git a/display/vt11.c b/display/vt11.c new file mode 100644 index 00000000..7dddadb0 --- /dev/null +++ b/display/vt11.c @@ -0,0 +1,3148 @@ +/* + * $Id: vt11.c,v 1.19 2004/02/07 06:38:12 phil Exp $ + * Simulator Independent VT11/VS60 Graphic Display Processor Simulation + * Started by Phil Budne September 13, 2003 + * Substantially revised by Douglas A. Gwyn, 05 Feb. 2004 + * + * from EK-VT11-TM-001, September 1974 + * and EK-VT48-TM-001, November 1976 + * with help from Al Kossow's "VT11 instruction set" posting of 21 Feb 93 + * and VT48 Engineering Specification Rev B + * and VS60 diagnostic test listings, provided by Alan Frisbie + * + * The VT11 is a calligraphic display-file device used in the GT4x series + * of workstations (PDP-11/04,34,40 based). + * + * The VS60 is an improved, extended, upward-compatible version of the + * VT11, used in the GT62 workstation (PDP-11/34 based). It supported + * dual consoles (CRTs with lightpens), multiple phosphor colors, 3D + * depth cueing, and circle/arc generator as options. We do not know + * whether any of these options were ever implemented or delivered. + * XXX VS60 depth-cueing option not yet fully implemented + * + * The VSV11/VS11 is a color raster display-file device (with joystick + * instead of light pen) with instructions similar to the VT11's but + * different enough that a separate emulation should be created by + * editing a copy of this source file rather than trying to hack it into + * this one. Very likely, the display (phosphor decay) simulation will + * also require revision to handle multiple colors. + * + * A PDP-11 system has at most one display controller attached. + * In principle, a VT11 or VS60 can also be used on a VAX Unibus. + */ + +/* + * Copyright (c) 2003-2004, Philip L. Budne and Douglas A. Gwyn + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the names of the authors shall + * not be used in advertising or otherwise to promote the sale, use or + * other dealings in this Software without prior written authorization + * from the authors. + */ + +#ifdef DEBUG_VT11 +#include +#endif +#include /* memset */ +#ifndef NO_CONIC_OPT +#include /* atan2, cos, sin, sqrt */ +#endif + +#include "display.h" /* XY plot interface */ +#include "vt11.h" + +#define BITMASK(n) (1<<(n)) /* PDP-11 bit numbering */ + +/* mask for a field */ +#define FIELDMASK(START,END) ((1<<((START)-(END)+1))-1) + +/* extract a field */ +#define GETFIELD(W,START,END) (((W)>>(END)) & FIELDMASK(START,END)) + +/* extract a 1-bit field */ +#define TESTBIT(W,B) (((W) & BITMASK(B)) != 0) + +#ifdef DEBUG_VT11 +#define DEBUGF(X) do { printf X; fflush(stdout); } while (0) +#else +#define DEBUGF(X) +#endif + +/* + * Note about coordinate signedness and wrapping: + * + * There is a discrepancy between the documentation and the known or suspected + * behavior of these devices. The VT11 manual says it wraps 12-bit position + * coordinates independently of sign (4097 -> 1), but then it doesn't mention + * any sign for X,Y position registers, yet we think that graphics is properly + * tracked in the negative domain. The VS60 manual says it wraps from 4097 to + * -4095, but there is no evidence of this in the manual's diagrams, and the + * absolute-point graphic data format doesn't show signs for X,Y coordinates. + * Most likely, both devices have signed position coordinates (either sign- + * magnitude or twos-complement) and merely drop bits that overflow. + * + * At one point this simulation attempted to implement position wrapping, but + * because it adds overhead, has uncertain characteristics, and should never + * be exploited by any application anyway, now no wrapping is done, and the + * position is tracked using at least 32 bits including sign. + * + * Note about scaling and offsets: + * + * The VS60 supports character and vector scaling and position offsets. The + * X, Y, and Z position register values always include scaling and offsets. + * It is not clear from the manual whether or not there are two "guard bits", + * which would better track the virtual position when using a scale factor of + * 3/4, 1/2, or 1/4. Most likely, there are no guard bits. This simulation + * maintains position values and offsets both multiplied by PSCALEF, which + * should be 4 to obtain maximum drawing precision, or 1 to mimic non-guard-bit + * display hardware. These internal coordinates are "normalized" (converted to + * correct virtual CRT coordinates) before being reported via the position/ + * offset registers. The normalized Z position register value's 2 lowest bits + * are always 0. + * Example of why this matters: Set vector scale 1/2; draw successive vectors + * with delta X = 1, 1, and -2. With guard bits, the final and original X + * positions are the same; without guard bits, the final X position is one + * unit to the left of the original position. This effect accumulates over a + * long sequence of vectors, leading to quite visible distortion of the image. + * + * Light-pen and edge-interrupt positions always have "on-screen" values. + */ + +#ifndef PSCALEF +#if 1 /* XXX temporary during development, to catch any oversights */ +#define PSCALEF 4 /* position scale factor 4 for maximum precision */ +#else +#define PSCALEF 1 /* position scale factor 1 for accurate simulation */ +#endif +#endif + +#define PSCALE(x) ((x) * PSCALEF) +#define PNORM(x) ((x) / PSCALEF) +/* virtual_CRT_coordinate = PNORM(scaled_value) */ + +/* VS60 scales points/vectors and characters separately */ +#define VSCALE(x) (PSCALE(vector_scale * (int32)(x)) / 4) +#define CSCALE(x) (PSCALE(char_scale * (int32)(x)) / 4) + +#define ABS(x) ((x) >= 0 ? (x) : -(x)) + +enum display_type vt11_display = DISPLAY_TYPE; /* DIS_VR{14,17,48} */ +int vt11_scale = PIX_SCALE; /* RES_{FULL,HALF,QUARTER,EIGHTH} */ +unsigned char vt11_init = 0; /* set after display_init() called */ +#define INIT { if (!vt11_init) { display_init(vt11_display, vt11_scale); \ + vt11_init = 1; vt11_reset(); } } + +/* state visible to host */ + +/* The register and field names are those used in the VS60 manual (minus the + trailing "flag", "code", "status", or "select"); the VT11 manual uses + somewhat different names. */ + +/* + * Display Program Counter + * Read/Write (reading returns the *relocated* DPC bits [15:0]) + * DPC address 15:1 + * resume 0 + */ +#define DPC sp->_dpc /* Display PC (always even) */ +static uint16 bdb = 0; /* Buffered Data Bits register; + see comment in vt11_get_dpc() */ + +/* + * Mode Parameter Register + * Read Only, except that writing to it beeps the LK40 keyboard's bell + * internal stop flag 15 + * graphic mode code 14:11 + * intensity level 10:8 + * LP con. 0 hit flag 7 + * shift out status 6 + * edge indicator 5 + * italics status 4 + * blink status 3 + * edge flag status 2 (VS60 only) + * line type register status 1:0 + */ +static unsigned char internal_stop = 0; /* 1 bit: stop display */ + +#define graphic_mode sp->_mode /* 4 bits: sets type for graphic data */ +enum mode { CHAR=0, SVECTOR, LVECTOR, POINT, GRAPHX, GRAPHY, RELPOINT, /* all */ + BSVECT, CIRCLE, ABSVECTOR /* VS60 only */ +}; + +#define intensity sp->_intens /* 3 bits: 0 => dim .. 7 => bright */ +static unsigned char lp0_flag = 0; /* 1 bit: light pen #0 detected hit */ +#define shift_out sp->_so /* 1 bit: chars using shift-out codes */ +static unsigned char edge_indic = 0; /* 1 bit: end pt outside visible area; + on-to-off transition only! */ +#define italics sp->_italics /* 1 bit: use italic font */ +#define blink_ena sp->_blink /* 1 bit: blink graphic item */ +static unsigned char edge_flag = 0; /* 1 bit: any edge transition (VS60) */ +#define line_type sp->_ltype /* 2 bits: style for drawing vectors */ +enum linetype { SOLID=0, LONG_DASH, SHORT_DASH, DOT_DASH }; + +/* + * Graphplot Increment and X Position Register + * Read Only + * graphplot increment register value 15:10 + * X position register value 9:0 + */ +static unsigned char graphplot_step = 0;/* (scaled) graphplot step increment */ +static int32 xpos = 0; /* X position register * PSCALEF */ + /* note: offset has been applied! */ +static int lp_xpos; /* (normalized) */ +static int edge_xpos; /* (normalized) */ + +/* + * Character Code and Y Position Register + * Read Only + * character register contents 15:10 + * Y position register value 9:0 + */ +static unsigned char char_buf = 0; /* (only lowest 6 bits reported) */ +static int32 ypos = 0; /* Y position register * PSCALEF */ + /* note: offset has been applied! */ +static int lp_ypos; /* (normalized) */ +static int edge_ypos; /* (normalized) */ + +/* + * Relocate Register (VS60 only) + * Read/Write + * spare 15:12 + * relocate register value[17:6] 11:0 + */ +static uint32 reloc = 0; /* relocation, aligned with DPC */ + +/* + * Status Parameter Register (VS60 only) + * Read Only, except for bit 7 (1 => external stop request) + * display busy status 15 + * stack overflow status 13 + * stack underflow status 12 + * time out status 11 + * char. rotate status 10 + * char. scale index 9:8 + * external stop flag 7 + * menu status 6 + * relocated DPC bits [17:16] 5:4 + * vector scale 3:0 + */ +#define busy (!(internal_stop || ext_stop || lphit_irq || lpsw_irq || edge_irq \ + || char_irq || stack_over || stack_under || time_out || name_irq)) + /* 1 bit: display initiated | resumed */ +static unsigned char stack_over = 0; /* 1 bit: "push" with full stack */ +static unsigned char stack_under = 0; /* 1 bit: "pop" with empty stack */ +static unsigned char time_out = 0; /* 1 bit: timeout has occurred */ +#define char_rotate sp->_crotate /* 1 bit: rotate chars 90 degrees CCW */ +#define cs_index sp->_csi /* character scale index 0..3 */ +static unsigned char ext_stop = 0; /* 1 bit: stop display */ +#define menu sp->_menu /* 1 bit: VS60 graphics in menu area */ +#define vector_scale sp->_vscale /* non-character scale factor * 4 */ + +/* + * X Offset Register (VS60 only) + * Read/Write + * upper X position bits 15:12 (read) + * sign of X dynamic offset 13 (write) + * X dynamic offset 11:0 + */ +static unsigned char s_xoff = 0; /* sign bit for xoff (needed for -0) */ +static int32 xoff = 0; /* X offset register * PSCALEF */ + +/* + * Y Offset Register (VS60 only) + * Read/Write + * upper Y position bits 15:12 (read) + * sign of Y dynamic offset 13 (write) + * Y dynamic offset 11:0 + */ +static unsigned char s_yoff = 0; /* sign bit for yoff (needed for -0) */ +static int32 yoff = 0; /* Y offset register * PSCALEF */ + +/* + * Associative Name Register (VS60 only) + * Write Only + * search code change enable 14 + * search code 13:12 + * name change enable 11 + * associative name 10:0 + */ +static unsigned char search = 0; /* 00=> no search, no interrupt + 01 => intr. on 11-bit compare + 10 => intr. on high-8-bit compare + 11 => intr. on high-4-bit compare */ +static unsigned assoc_name = 0; /* compare value */ + +/* + * Slave Console/Color Register (VS60 only) + * Read/Write * + * inten enable con. 0 15 + * light pen hit flag con. 0 14 * + * LP switch on flag con. 0 13 * + * LP switch off flag con. 0 12 * + * LP flag intr. enable con. 0 11 + * LP switch flag intr. enable con. 0 10 + * inten enable con. 1 9 + * light pen hit flag con. 1 8 * + * LP switch on flag con. 1 7 * + * LP switch off flag con. 1 6 * + * LP flag intr. enable con. 1 5 + * LP switch flag intr. enable con. 1 4 + * color 3:2 + * + * * indicates that maintenance switch 3 must be set to write these bits; + * the other bits are not writable at all + */ +#define int0_scope sp->_inten0 /* enable con. 0 for all graphic data */ +/* lp0_flag has already been defined, under Mode Parameter Register */ +#define lp0_sw display_lp_sw /* (defined in display.c) */ +#define lp0_intr_ena sp->_lp0intr /* generate interrupt on LP #0 hit */ +#define lp0_sw_intr_ena sp->_lp0swintr /* generate intr. on LP #0 switch chg */ +#define int1_scope sp->_inten1 /* enable con. 1 for all graphic data */ +/* following 2 flags only mutable via writing this register w/ MS3 set: */ +static unsigned char lp1_flag = 0; /* 1 bit: light pen #1 detected hit */ +static unsigned char lp1_sw = 0; /* 1 bit: LP #1 switch changed state */ +#define lp1_intr_ena sp->_lp1intr /* generate interrupt on LP #1 hit */ +#define lp1_sw_intr_ena sp->_lp1swintr /* generate intr. on LP #1 switch chg */ + +enum scolor { GREEN=0, YELLOW, ORANGE, RED }; +#define color sp->_color /* 2 bits: VS60 color option */ + +/* + * Name Register (VS60 only) + * Read Only + * name/assoc name match flag 15 + * search code 13:12 + * name 10:0 + */ +static unsigned char name_flag = 0; /* 1 bit: name matches associative nm */ +/* search previously defined, under Associative Name Register */ +#define name sp->_name /* current name from display file */ + +/* + * Stack Data Register (VS60 only) + * Read Only + * stack data 15:0 (as selected by Stk. Addr./Maint. Reg.) + * + * On the actual hardware there are 2 32-bit words per each of 8 stack levels. + * At the PDP-11 these appear to be 4 16-bit words ("stack bytes") per level. + */ +/* Two alternatives: keep active data in globals or use directly from stack. + The former is presumably more efficient when the stack isn't being used, + as in VT11 mode, but on most host processors the difference is small. + POPR is faster if we do not have to restore data to all those globals. + There are thus 9 levels of data, the initial state and 8 stacked sets. + Mimicking the actual hardware, the stack level *decreases* upon JSR. + */ + +static struct frame + { + vt11word _dpc; /* Display Program Counter (even) */ + unsigned _name; /* (11-bit) name from display file */ + enum mode _mode; /* 4 bits: sets type for graphic data */ + unsigned char _vscale; /* non-character scale factor * 4 */ + unsigned char _csi; /* character scale index 0..3 */ + unsigned char _cscale; /* character scale factor * 4 */ + unsigned char _crotate; /* rotate chars 90 degrees CCW */ + unsigned char _intens; /* intensity: 0 => dim .. 7 => bright */ + enum linetype _ltype; /* line type (long dash, etc.) */ + unsigned char _blink; /* blink enable */ + unsigned char _italics; /* italicize characters */ + unsigned char _so; /* chars are using shift-out codes */ + unsigned char _menu; /* VS60 graphics in menu area */ + unsigned char _cesc; /* perform POPR on char. term. match */ + unsigned char _edgeintr; /* generate intr. on edge transition */ + unsigned char _lp1swintr; /* generate intr. on LP #1 switch chg */ + unsigned char _lp0swintr; /* generate intr. on LP #0 switch chg */ + unsigned char _lp1intr; /* generate interrupt on LP #1 hit */ + unsigned char _inten1; /* blank cons. 1 for all graphic data */ + unsigned char _lp0intr; /* generate interrupt on LP #0 hit */ + unsigned char _inten0; /* blank cons. 0 for all graphic data */ + unsigned char _bright; /* visually indicate hit on entity */ + unsigned char _stopintr; /* generate interrupt on stop */ + enum scolor _color; /* scope display color (option) */ + unsigned char _zdata; /* flag: display file has Z coords */ + unsigned char _depth; /* flag: display Z using depth cue */ + } stack[9] = { { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { 0, 0, CHAR, 4, 1, 0, 4, SOLID, + 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 }, + }; +/* (stack pointer "sp" defined under Stack Address/Maintenance Register) */ + +#define char_scale sp->_cscale /* character scale factor * 4 */ +static const unsigned char csi2csf[4] = { 2, 4, 6, 8 }; /* maps cs_index to " */ +#define char_escape sp->_cesc /* perform POPR on char. term. match */ +#define edge_intr_ena sp->_edgeintr /* generate intr. on edge transition */ +#define lp_intensify sp->_bright /* if VT11, 20us bright spot; + if VS60, "bright down" the entity */ +#define stop_intr_ena sp->_stopintr /* generate intr. on internal stop */ +#define file_z_data sp->_zdata /* flag: display file has Z coords */ +#define depth_cue_proc sp->_depth /* flag: display Z using depth cue */ + +/* + * Character String Terminate Register (VS60 only) + * Read/Write + * char. term. reg. enable 7 + * character terminate code 6:0 + */ +static int char_term = 0; /* char. processing POPRs after this */ + +/* + * Stack Address/Maintenance Register (VS60 only) + * Read/Write + * maint. sw. 4 15 + * maint. sw. 3 14 + * maint. sw. 2 13 + * maint. sw. 1 12 + * offset mode status 10 + * jump to subr. ?rel. status 9 (diagnostic requires this be JSR abs.!) + * word 2 status 8 + * word 1 status 7 + * word 0 status 6 + * stack reset status 5 + * stack level select 4:2 (manual has this messed up) + * stack halfword select 1:0 (manual has this messed up) + */ +static unsigned char maint4 = 0; /* 1 bit: maintenance switch #4 */ +static unsigned char maint3 = 0; /* 1 bit: maintenance switch #3 */ +static unsigned char maint2 = 0; /* 1 bit: maintenance switch #2 */ +static unsigned char maint1 = 0; /* 1 bit: maintenance switch #1 */ +static unsigned char offset = 0; /* 1 bit: last data loaded offsets */ +static unsigned char jsr = 0; /* 1 bit: last control was JSR ?rel. */ +static unsigned char word_number = 0; /* tracks multiple data words etc. */ +static struct frame *sp = &stack[8]; +#define STACK_EMPTY (sp == &stack[8]) +#define STACK_FULL (sp == stack) +static unsigned char stack_sel = 8<<2; /* 8 levels, 4 PDP-11 words per level */ + /* stack_sel must track sp! */ + +/* + * Z Position Register, Depth Cue Option (VS60 only) + * Read/Write + * Z position register value[13:2] 11:0 + */ +static int32 zpos = 0; /* (Z "position" reg. * 4) * PSCALEF */ + /* note: offset has been applied! */ +static int32 lp_zpos; /* (scaled) */ +static int32 edge_zpos; /* (scaled) */ + +/* + * Z Offset Register, Depth Cue Option (VS60 only) + * Read/Write + * sign of X dynamic offset 15 (read) (VT48 manual has this confused) + * sign of Y dynamic offset 14 (read) (VT48 manual has this confused) + * sign of Z dynamic offset 13 + * Z dynamic offset 11:0 + */ +static unsigned char s_zoff = 0; /* sign bit for zoff (needed for -0) */ +static int32 zoff = 0; /* Z offset register * PSCALEF */ + +/* + * Invisible state: + */ +static unsigned char char_irq = 0; /* intr. on illegal char in SO mode */ +static unsigned char lphit_irq = 0; /* intr. on light-pen hit */ +static unsigned char lpsw_irq = 0; /* intr. on tip-switch state change */ +static unsigned char edge_irq = 0; /* intr. on edge transition */ +static unsigned char name_irq = 0; /* intr. on name match */ + +static unsigned char lp0_sw_state = 0; /* track light-pen tip-switch state */ +static unsigned char blink_off = 0; /* set when blinking graphics is dark */ +static unsigned char finish_jmpa = 0; /* reminder to fetch JMPA address */ +static unsigned char finish_jsra = 0; /* reminder to fetch JSRA address */ + +static unsigned char more_vect = 0; /* remembers LP hit in middle of vec. */ +static unsigned char more_arc = 0; /* remembers LP hit in middle of arc */ +static int32 save_x0, save_y0, save_x1, save_y1;/* CRT coords for rest of vec */ + +static unsigned char lp_suppress = 0; /* edge columns of char. (VT11 only) */ +static unsigned char stroking = 0; /* set when drawing VS60 char strokes */ +static unsigned char skip_start = 0; /* set between vis. char./arc strokes */ + +static unsigned char sync_period = 0; /* frame sync period (msec) */ +static unsigned char refresh_rate = 0; /* 2 bits: + 00 => continuous display refresh + 01 => 30 fps (60 fps if VT11) + 10 => 40 fps (VS60) + 11 => external sync (VS60) */ + +#if 0 /* this is accurate in simulated "real" time */ +#define BLINK_COUNT 266 /* 266 milliseconds */ +#else /* this looks better in actual real time (adjust for your host speed) */ +#define BLINK_COUNT 67 /* 67 milliseconds */ +#endif + +unsigned char vt11_csp_w = VT11_CSP_W; /* horizontal character spacing */ +unsigned char vt11_csp_h = VT11_CSP_H; /* vertical character spacing */ + +/* VS60 has a menu area to the right of the "main working surface" */ +#define MENU_OFFSET (1024 + VR48_GUTTER) /* left edge of menu on CRT */ +#define VR48_WIDTH (MENU_OFFSET + 128) /* X beyond this is not illuminated */ + +static int reduce; /* CRT units per actual pixel */ +static int x_edge; /* 1023 or VR48_WIDTH-1, depending */ +static int y_edge; /* 767 or 1023, depending on display */ +#define ONCRT(x,y) ((x) >= 0 && (x) <= x_edge && (y) >= 0 && (y) <= y_edge) + +/* + * Uncertain whether VS60 edge transitions in menu area are flagged and whether + * clipping takes menu width into account. Three possibilities: + */ +#if 0 /* menu area never clipped (seems wrong) */ +#define ONSCREEN(x,y) (menu || ((x)>=0 && (x)<=1023 && (y)>=0 && (y)<=y_edge)) +#elif 0 /* menu area correctly clipped */ +#define ONSCREEN(x,y) ((x) >= 0 && (x) <= (menu ? 127 : 1023) \ + && (y) >= 0 && (y) <= y_edge) +#else /* menu area clipped same as main area */ +#define ONSCREEN(x,y) ((x) >= 0 && (x) <= 1023 && (y) >= 0 && (y) <= y_edge) + +#endif + +static void lineTwoStep(int32, int32, int32, int32); /* forward reference */ + +/* + * calls to read/write VT11/VS60 CSRs + * + * presumably the host looks at our state less often than we do(!) + * so we keep it in a form convenient to us! + */ + +int32 +vt11_get_dpc(void) +{ INIT + /* + * The VT48 manual says that Maintenance Switch 1 causes the Buffered + * Data Bits register to be "entered into the DPC" so it can be + * examined by reading the DPC address, but details of when and how + * often that happens are not provided. Examination of the diagnostic + * test listings show that relocation is applied and that only the DPC + * is involved when this switch is set. + */ + return ((maint1 ? bdb : DPC) + reloc) & 0177777; +} + +void +vt11_set_dpc(uint16 d) +{ INIT + bdb = d; /* save all bits in case maint1 used */ + DEBUGF(("set DPC 0%06o\r\n", (unsigned)d)); + if (!TESTBIT(d,0)) { + sp = &stack[8]; /* important! do this first */ + stack_sel = 8<<2; + DPC = d; /* load DPC */ + sync_period = 0; + ext_stop = 0; + /* the following seem reasonable, but might be wrong */ + finish_jmpa = finish_jsra = jsr = 0; + word_number = 0; +#if 0 /* probably accurate mimicry, but ugly behavior */ + if (edge_irq) { + xpos = PSCALE(edge_x); + ypos = PSCALE(edge_y); + } +#endif + } else { /* RESUME (after intr); DPC unchanged */ + /* if resuming from LP hit interrupt, finish drawing rest of vector */ + /* (if resuming from edge interrupt, vector is *not* drawn) */ + if (more_vect) { + unsigned char save_ena = lp0_intr_ena; + lp0_intr_ena = 0; /* one hit per vector is plenty */ + lphit_irq = 0; /* or else lineTwoStep aborts again! */ + /* line_counter is intact; draw rest of visible vector */ + lineTwoStep(save_x0, save_y0, save_x1, save_y1); + lp0_intr_ena = save_ena; + } + if (more_arc) { /* remainder of chord was just drawn */ + unsigned char save_ena = lp0_intr_ena; + lp0_intr_ena = 0; /* one hit per arc is plenty */ + lphit_irq = 0; /* or else lineTwoStep aborts again! */ + /* line_counter is intact; draw rest of visible arc */ + /*XXX not yet implemented [conic{23}() needed]*/ + lp0_intr_ena = save_ena; + } + if (!maint2) /* kludge to satify diagnostic test */ + ext_stop = 0; + } + internal_stop = time_out = stack_over = stack_under = 0; + more_vect = more_arc = stroking = skip_start = 0; + edge_indic = edge_flag = lp0_flag = lp1_flag = lp_suppress = 0; + char_irq = lphit_irq = lpsw_irq = edge_irq = name_irq = 0; + /* next vt11_cycle() will perform a fetch */ +} + +int32 +vt11_get_mpr(void) +{ + int32 ret; + INIT + ret = (internal_stop<<15) | (graphic_mode<<11) | (intensity<<8) | + (lp0_flag<<7) | (shift_out<<6) | (edge_indic<<5) | (italics<<4) | + (blink_ena<<3) | line_type; + + if (VS60) + ret |= edge_flag<<2; + + return ret; +} + +void +vt11_set_mpr(uint16 d) +{ INIT + /* beeps the "bell" on the LK40 keyboard */ +#if 0 /* probably doesn't hurt to do it for the VS60 also */ + if (VT11) /* according to the VS60 specs */ +#endif + display_beep(); +} + +int32 +vt11_get_xpr(void) +{ + int32 pos; + INIT + pos = lphit_irq ? lp_xpos : edge_irq ? edge_xpos : PNORM(xpos); + return (graphplot_step << 10) | GETFIELD(ABS(pos),9,0); +} + +void +vt11_set_xpr(uint16 d) +{ INIT + DEBUGF(("set XPR: no effect\r\n")); +} + +int32 +vt11_get_ypr(void) +{ + int32 pos; + INIT + pos = lphit_irq ? lp_ypos : edge_irq ? edge_ypos : PNORM(ypos); + return (GETFIELD(char_buf,5,0) << 10) | GETFIELD(ABS(pos),9,0); +} + +void +vt11_set_ypr(uint16 d) +{ INIT + DEBUGF(("set YPR: no effect\r\n")); +} + +/* All the remaining registers pertain to the VS60 only. */ + +int32 +vt11_get_rr(void) +{ INIT + return reloc >> 6; +} + +void +vt11_set_rr(uint16 d) +{ INIT + reloc = (uint32)GETFIELD(d,11,0) << 6; +} + +int32 +vt11_get_spr(void) +{ INIT + return (busy<<15) | (stack_over<<13) | (stack_under<<12) | (time_out<<11) | + (char_rotate<<10) | (cs_index<<8) | (ext_stop<<7) | + (menu<<6) | (((DPC + reloc) & 0600000L) >> 12) | vector_scale; +} + +void +vt11_set_spr(uint16 d) +{ INIT + ext_stop = TESTBIT(d,7); + + if (ext_stop /* && stop_intr_ena */)/* not maskable? */ + vt_stop_intr(); /* post stop interrupt to host */ + /* (asynchronous with display cycle) */ +} + +int32 +vt11_get_xor(void) +{ + int32 off, pos; + INIT + off = PNORM(xoff); + pos = lphit_irq ? lp_xpos : edge_irq ? edge_xpos : PNORM(xpos); + return (GETFIELD(ABS(pos),13,10)<<12) | GETFIELD(ABS(off),11,0); +} + +void +vt11_set_xor(uint16 d) +{ INIT + xoff = PSCALE(GETFIELD(d,11,0)); + if (s_xoff = TESTBIT(d,13)) + xoff = -xoff; +} + +int32 +vt11_get_yor(void) +{ + int32 off, pos; + INIT + off = PNORM(yoff); + pos = lphit_irq ? lp_ypos : edge_irq ? edge_ypos : PNORM(ypos); + return (GETFIELD(ABS(pos),13,10)<<12) | GETFIELD(ABS(off),11,0); +} + +void +vt11_set_yor(uint16 d) +{ INIT + yoff = PSCALE(GETFIELD(d,11,0)); + if (s_yoff = TESTBIT(d,13)) + yoff = -yoff; +} + +int32 +vt11_get_anr(void) +{ INIT + DEBUGF(("get ANR: no effect\r\n")); + return (search << 12) | assoc_name; /* [garbage] */ +} + +void +vt11_set_anr(uint16 d) +{ INIT + if (TESTBIT(d,14)) + search = GETFIELD(d,13,12); + if (TESTBIT(d,11)) + assoc_name = GETFIELD(d,10,0); +} + +int32 +vt11_get_scr(void) +{ INIT + return (int0_scope<<15) | (lp0_flag<<14) | (lp0_sw<<13) | ((!lp0_sw)<<12) | + (lp0_intr_ena<<11) | (lp0_sw_intr_ena<<10) | (int1_scope<<9) | + (lp1_flag<<8) | (lp1_sw<<7) | ((!lp1_sw)<<6) | (lp1_intr_ena<<5) | + (lp1_sw_intr_ena<<4) | (color << 2); +} + +void +vt11_set_scr(uint16 d) +{ INIT + if (maint3) { + unsigned char old_sw0 = lp0_sw; + unsigned char old_sw1 = lp1_sw; + + if (TESTBIT(d,14)) { + if (!lphit_irq) { /* ensure correct position registers reported */ + lp_xpos = PNORM(xpos); + lp_ypos = PNORM(ypos); + lp_zpos = PNORM(zpos); + } + lp0_flag = 1; + if (lp0_intr_ena) + lphit_irq = 1; + } + if (TESTBIT(d,13)) { + lp0_sw = 1; /* the manual seems to have it backward */ + if (lp0_sw_intr_ena && lp0_sw != old_sw0) + lpsw_irq = 1; + } + if (TESTBIT(d,12)) { + lp0_sw = 0; /* the manual seems to have it backward */ + if (lp0_sw_intr_ena && lp0_sw != old_sw0) + lpsw_irq = 1; + } + if (TESTBIT(d,8)) { + if (!lphit_irq) { /* ensure correct position registers reported */ + lp_xpos = PNORM(xpos); + lp_ypos = PNORM(ypos); + lp_zpos = PNORM(zpos); + } + lp1_flag = 1; + if (lp1_intr_ena) + lphit_irq = 1; + } + if (TESTBIT(d,7)) { + lp1_sw = 1; + if (lp1_sw_intr_ena && lp1_sw != old_sw1) + lpsw_irq = 1; + } + if (TESTBIT(d,6)) { + lp1_sw = 0; + if (lp1_sw_intr_ena && lp1_sw != old_sw1) + lpsw_irq = 1; + } + if (lphit_irq || lpsw_irq) + vt_lpen_intr(); + } +} + +int32 +vt11_get_nr(void) +{ INIT + return (name_flag<<15) | (search<<12) | name; +} + +void +vt11_set_nr(uint16 d) +{ INIT + DEBUGF(("set NR: no effect\r\n")); +} + +int32 +vt11_get_sdr(void) +{ + struct frame *p; + INIT + p = &stack[GETFIELD(stack_sel,4,2)]; + switch (GETFIELD(stack_sel,1,0)) { /* 16-bit "byte" within frame */ + case 0: + return p->_dpc; /* DPC bit#0 is always 0 */ + + case 1: + return (p->_name << 4) | p->_mode; + + case 2: + return (p->_italics << 15) | (p->_vscale << 11) | (p->_cscale << 9) | + (p->_crotate << 7) | (p->_intens << 4) | ((int)p->_color << 2) | + p->_ltype; + + case 3: + return (p->_blink << 15) | (p->_so << 14) | (p->_menu << 13) | + (p->_cesc << 12) | (p->_edgeintr << 11) | (p->_zdata << 10) | + (p->_depth << 8) | (p->_lp1swintr << 7) | + (p->_lp0swintr << 6) | (p->_lp1intr << 5) | (p->_inten1 << 4) | + (p->_lp0intr << 3) | (p->_inten0 << 2) | (p->_bright << 1) | + p->_stopintr; /* XXX should that be !p->_so ? */ + } + /*NOTREACHED*/ +} + +void +vt11_set_sdr(uint16 d) +{ INIT + DEBUGF(("set SDR: no effect\r\n")); +} + +int32 +vt11_get_str(void) +{ INIT + return char_term; +} + +void +vt11_set_str(uint16 d) +{ INIT + if (TESTBIT(d,7)) + char_term = GETFIELD(d,6,0); +} + +int32 +vt11_get_sar(void) +{ + int32 ret; + INIT + ret = (maint4<<15) | (maint3<<14) | (maint2<<13) | (maint1<<12) | + (offset<<10) | (jsr<<9) | stack_sel /*includes bit 5, TOS [level 8]*/; + switch (word_number) { + case 0: + ret |= 1<<6; + break; + case 1: + ret |= 1<<7; + break; + case 2: + ret |= 1<<8; + break; + /* others not reportable */ + } + return ret; +} + +void +vt11_set_sar(uint16 d) +{ INIT + maint4 = TESTBIT(d,15); /* 1 => synch. processing pipeline */ + maint3 = TESTBIT(d,14); /* 1 => copy delta,tangent to x,y pos */ + maint2 = TESTBIT(d,13); /* 1 => set single-step mode */ + maint1 = TESTBIT(d,12); /* 1 => vt11_get_dpc will return bdb */ + if (TESTBIT(d,5)) { + sp = &stack[8]; /* reset stack pointer */ + stack_sel = 8<<2; /* TOS amounts to level 8 */ +#if 1 /* the following seems wrong, but is needed to pass diagnostic test! */ + stack_sel |= 1; +#endif + } else { + stack_sel = GETFIELD(d,4,0); + sp = &stack[GETFIELD(stack_sel,4,2)]; + } +} + +/* registers used with the VS60 depth cueing option */ + +/* + * Since there is no support for hardware 3D rotation or viewing transform, the + * only effect of the Z coordinate is to modulate beam intensity along a vector + * to give the illusion that greater Z coordinates are closer (brighter). + * This is known as "depth cueing" and is implemented in illum3(). + */ + +int32 +vt11_get_zpr(void) +{ + int32 pos; + INIT + pos = lphit_irq ? lp_zpos : edge_irq ? edge_zpos : PNORM(zpos); + return GETFIELD(ABS(pos)/4,11,0); /* sign not reported? */ +} + +void +vt11_set_zpr(uint16 d) +{ INIT + DEBUGF(("set ZPR: no effect\r\n")); +} + +int32 +vt11_get_zor(void) +{ + int32 off, ret; + INIT + off = PNORM(zoff); + ret = GETFIELD(ABS(off),11,0); + if (s_xoff) /* (VT48 manual has this confused) */ + ret |= 1<<15; + if (s_yoff) /* (VT48 manual has this confused) */ + ret |= 1<<14; + if (s_zoff) + ret |= 1<<13; + return ret; +} + +void +vt11_set_zor(uint16 d) +{ INIT + zoff = PSCALE(GETFIELD(d,11,0)); + if (s_zoff = TESTBIT(d,13)) + zoff = -zoff; +} + +void +vt11_reset(void) +{ + /* XXX call display layer? destroy window? */ + + /* make sure display code has been initialized */ + if (!vt11_init) /* (SIMH invokes before display type is set) */ + return; /* wait until last moment */ + + if (VS60) { + /* XXX verify that this is correct VS60 character spacing */ + vt11_csp_w = 14; /* override VT11 options */ + vt11_csp_h = 24; + } /* else assume already set up for desired VT11 behavior */ + + x_edge = display_xpoints() - 1; + y_edge = display_ypoints() - 1; + reduce = display_scale(); + + /* reset VT11/VT48 to initial default internal state: */ + + /* clear interrupts, BDB, etc. */ + vt11_set_dpc(0); /* important! do this first */ + /* some of the following should probably be moved to vt11_set_dpc([even]) */ + internal_stop = int0_scope = 1; /* idle, console 0 enabled */ + lp0_sw_state = lp0_sw; /* sync with mouse button #1 */ + lp1_sw = 0; + shift_out = int1_scope = stop_intr_ena = blink_off = 0; + italics = blink_ena = char_rotate = menu = search = offset = 0; + lp0_sw_intr_ena = lp1_sw_intr_ena = lp0_intr_ena = lp1_intr_ena = 0; + file_z_data = edge_intr_ena = depth_cue_proc = char_escape = 0; + maint1 = maint2 = maint3 = maint4 = 0; + refresh_rate = 0; + char_buf = char_term = 0; + assoc_name = name = 0; + reloc = 0; + xpos = ypos = zpos = xoff = yoff = zoff = 0; + s_xoff = s_yoff = s_zoff = 0; + graphplot_step = 0; + graphic_mode = CHAR; + line_type = SOLID; + color = GREEN; + lp_intensify = 1; + cs_index = 1; + char_scale = vector_scale = 4; + intensity = 4; + + /* following just in case the stack is inspected via stack data reg. */ + { int i; + for (i = 0; i < 8; ++i) + memset(&stack[i], 0, sizeof(struct frame)); + } +} + +/* VS60 display subroutine support (see stack layout for SDR, above) */ + +static void +push() +{ + stack_over = STACK_FULL; + if (!stack_over) { + --sp; + sp[0] = sp[1]; /* initially have same parameters */ + /* (including *old* DPC) */ + stack_sel -= 1<<2; + /* XXX should stack_sel stack-byte bits be cleared? */ + } + /* else will generate interrupt soon after return */ +} + +static void +pop(int restore) +{ + stack_under = STACK_EMPTY; + if (!stack_under) { + ++sp; /* that's all! */ + stack_sel += 1<<2; + /* XXX should stack_sel stack-byte bits be cleared? */ + } + /* else will generate interrupt soon after return */ +} + +/* illuminate pixel in raster image */ + +static void +illum3(int32 x, int32 y, int32 z) /* XXX should supply intensity also */ + /* virtual CRT units (offset and normalized) */ +{ + int i; + + /* don't update position registers! */ + + /* coords might be outside viewable area, e.g. clipped italic character */ + if (!ONCRT(x, y) || !int0_scope) + return; + + if (blink_ena && blink_off) /* blinking & in dark phase */ + return; + + i = intensity; + if (depth_cue_proc) { /* apply depth cue */ + i += i * z / 1024; /* XXX is z scaled properly? */ + if (i > 7) + i = 7; + else if (i < 0) + i = 0; + } + i += DISPLAY_INT_MAX - 7; + if (i < DISPLAY_INT_MIN) + i = DISPLAY_INT_MIN; + + if (display_point((int)x, (int)y, i, 0) /* XXX VS60 might switch color */ + /* VT11, per maintenance spec, has threshold 6 for CHAR, 4 for others */ + /* but the classic Lunar Lander uses 3 for its menu and thrust bar! */ + /* I seem to recall that both thresholds were 4 for the VS60 (VR48). */ +#if 0 + && (i >= (DISPLAY_INT_MAX-1) /* (using i applies depth cueing) */ + || (graphic_mode != CHAR && i >= (DISPLAY_INT_MAX-3))) +#else + /* The following imposes thresholds of 3 for all graphic objects. */ + && (i >= (DISPLAY_INT_MAX-4)) /* (using i applies depth cueing) */ +#endif + && !lp_suppress) { + lp0_flag = 1; + if (lp0_intr_ena) + lphit_irq = 1; /* will lead to an interrupt */ + /* + * Save LP hit coordinates so CPU can look at them; the virtual position + * registers cannot be reported on LP interrupt, since they track the + * (pre-clipping) end of the vector that was being drawn. + */ + lp_xpos = x; + if (menu) + lp_xpos -= MENU_OFFSET; + lp_ypos = y; + lp_zpos = z; + if (lp_intensify) /* [technically shouldn't exceed max] */ + display_point((int)x, (int)y, DISPLAY_INT_MAX, 0); + /* XXX appropriate for VT11; what about VS60? chars? */ + } +} + +#define illum2(x,y) illum3(x, y, PNORM(zpos)) /* may be depth cued */ + /* the extra overhead if not depth cueing is not much */ + +static void +point3(int i, int32 x1, int32 y1, int32 z1, int detect_edge) + /* unscaled, unoffset display-file units */ +{ + int32 x0 = PNORM(xpos), y0 = PNORM(ypos); + + if (detect_edge) { + edge_indic = ONSCREEN(x0, y0); /* first test */ + edge_flag = !ONSCREEN(x0, y0); /* first test */ + } else { + edge_indic = 0; + edge_flag = 0; + } + xpos = VSCALE(x1) + xoff; + ypos = VSCALE(y1) + yoff; + zpos = VSCALE(z1 * 4) + zoff; + x1 = PNORM(xpos); + y1 = PNORM(ypos); + z1 = PNORM(zpos); + if (detect_edge) { + edge_indic &= !ONSCREEN(x1, y1); /* second test */ + edge_flag &= ONSCREEN(x1, y1); /* second test */ + edge_flag |= edge_indic; + if (edge_flag && edge_intr_ena) { + edge_xpos = x1; + edge_ypos = y1; + edge_zpos = z1; + edge_irq = 1; +#if 1 /* XXX uncertain whether point is displayed during edge intr. */ + return; /* point not displayed */ +#endif + } + } + if (i && ONSCREEN(x1, y1)) + if (menu) + illum3(x1 + MENU_OFFSET, y1, z1); + else + illum3(x1, y1, z1); +} + +#define point2(i,x,y,e) point3(i, x, y, PNORM(zpos - zoff) / 4, e) + /* the extra overhead if not depth cueing is not much */ + +/* 4 bit counter, fed from div 2 clock (to compensate for raster algorithm) */ +/* XXX check display against example photos to see if div 2 is right */ +static unsigned char line_counter; +#define LC1 02 +#define LC2 04 +#define LC3 010 +#define LC4 020 + +/* point on a line (apply line style) */ +static void +lpoint(int32 x, int32 y) /* window-system screen pixel units */ +{ + int i, on; + + /* convert back from actual screen pixels to emulated CRT coordinates */ + x *= reduce; + y *= reduce; + + if (!(on = (line_type == SOLID) || stroking)) + for (i = 0; i < reduce; ++i) { + switch (line_type) { + case LONG_DASH: + if (line_counter & LC4) + on = 1; + break; + case SHORT_DASH: + if (line_counter & LC3) + on = 1; + break; + case DOT_DASH: + /* LC(2:1)H * LC3L + LC4L */ + if (((line_counter & (LC1|LC2)) == (LC1|LC2) + && !(line_counter & LC3)) || !(line_counter & LC4)) + on = 1; + break; + } + + --line_counter; + } + + if (on) + illum2(x, y); +} + +/* + * 2-step algorithm, developed by Xiaolin Wu + * from http://graphics.lcs.mit.edu/~mcmillan/comp136/Lecture6/Lines.html + * + * The two-step algorithm takes the interesting approach of treating + * line drawing as a automaton, or finite state machine. If one looks + * at the possible configurations that the next two pixels of a line, + * it is easy to see that only a finite set of possiblities exist. + * If line styles weren't involved, the line could be drawn symmetrically + * from both ends toward the midpoint. + * Rasterization is done using actual screen pixel units, not emulated device + * coordinates! + */ + +static void +lineTwoStep(int32 x0, int32 y0, int32 x1, int32 y1) + /* virtual CRT units (offset and normalized) */ +{ + int32 dx, dy; + int stepx, stepy; + + /* after clipping is implemented, coords should always be on-screen */ + + /* convert from emulated CRT units to actual screen pixels */ + x0 /= reduce; + y0 /= reduce; + x1 /= reduce; + y1 /= reduce; + + dx = x1 - x0; + dy = y1 - y0; + + /* XXX there could be fast special cases for "basic vectors" */ + + if (dx < 0) { dx = -dx; stepx = -1; } else { stepx = 1; } + if (dy < 0) { dy = -dy; stepy = -1; } else { stepy = 1; } + +#define TPOINT do { if (lphit_irq && !stroking) goto hit; \ + /* XXX would longjmp be more efficient? */ \ + lpoint(x0, y0); \ + } while (0) + + if (!skip_start) /* not for continuing stroke when VS60 char. or arc */ + lpoint(x0, y0); /* (could have used TPOINT) */ + + if (dx == 0 && dy == 0) /* following algorithm won't work */ + return; /* just the one dot */ + + if (dx > dy) { + int32 length = (dx - 1) / 2; + int extras = (dx - 1) & 1; + int32 incr2 = (dy * 4) - (dx * 2); + if (incr2 < 0) { + int32 c = dy * 2; + int32 incr1 = c * 2; + int32 d = incr1 - dx; + int32 i; + for (i = 0; i < length; i++) { + x0 += stepx; + if (d < 0) { /* Pattern: */ + TPOINT; /* x o o */ + x0 += stepx; + TPOINT; + d += incr1; + } + else { + if (d < c) { /* Pattern: */ + TPOINT; /* o */ + y0 += stepy; /* x o */ + } else { /* Pattern: */ + y0 += stepy; /* o o */ + TPOINT; /* x */ + } + x0 += stepx; + TPOINT; + d += incr2; + } + } + if (extras > 0) { + x0 += stepx; + if (d >= c) + y0 += stepy; + TPOINT; + } + + } else { + int32 c = (dy - dx) * 2; /* negative */ + int32 incr1 = c * 2; /* negative */ + int32 d = incr1 + dx; + int32 i; + for (i = 0; i < length; i++) { + x0 += stepx; + if (d > 0) { /* Pattern: */ + y0 += stepy; /* o */ + TPOINT; /* o */ + x0 += stepx; /* x */ + y0 += stepy; + TPOINT; + d += incr1; + } else { + if (d < c) { /* Pattern: */ + TPOINT; /* o */ + y0 += stepy; /* x o */ + } else { /* Pattern: */ + y0 += stepy; /* o o */ + TPOINT; /* x */ + } + x0 += stepx; + TPOINT; + d += incr2; + } + } + if (extras > 0) { + x0 += stepx; + if (d >= c) + y0 += stepy; + TPOINT; + } + } + + } else { + int32 length = (dy - 1) / 2; + int extras = (dy - 1) & 1; + int32 incr2 = (dx * 4) - (dy * 2); + if (incr2 < 0) { + int32 c = dx * 2; + int32 incr1 = c * 2; + int32 d = incr1 - dy; + int32 i; + for (i = 0; i < length; i++) { + y0 += stepy; + if (d < 0) { /* Pattern: */ + TPOINT; /* o */ + y0 += stepy; /* o */ + TPOINT; /* x */ + d += incr1; + } else { + if (d < c) { /* Pattern: */ + TPOINT; /* o */ + x0 += stepx; /* o */ + /* x */ + } else { /* Pattern: */ + x0 += stepx; /* o */ + TPOINT; /* o */ + /* x */ + } + y0 += stepy; + TPOINT; + d += incr2; + } + } + if (extras > 0) { + y0 += stepy; + if (d >= c) + x0 += stepx; + TPOINT; + } + + } else { + int32 c = (dx - dy) * 2; /* nonpositive */ + int32 incr1 = c * 2; /* nonpositive */ + int32 d = incr1 + dy; + int32 i; + for (i = 0; i < length; i++) { + y0 += stepy; + if (d > 0) { /* Pattern: */ + x0 += stepx; + TPOINT; /* o */ + y0 += stepy; /* o */ + x0 += stepx; /* x */ + TPOINT; + d += incr1; + } else { + if (d < c) { /* Pattern: */ + TPOINT; /* o */ + x0 += stepx; /* o */ + /* x */ + } else { /* Pattern: */ + x0 += stepx; /* o */ + TPOINT; /* o */ + /* x */ + } + y0 += stepy; + TPOINT; + d += incr2; + } + } + if (extras > 0) { + y0 += stepy; + if (d >= c) + x0 += stepx; + TPOINT; + } + } + } + lpoint(x1, y1); /* not TPOINT (0-length vector on resume) */ + return; + + /* here if LP hit interrupt during rendering */ + hit: + more_vect = 1; + save_x0 = x0 * reduce; + save_y0 = y0 * reduce; + save_x1 = x1 * reduce; + save_y1 = y1 * reduce; + /* XXX should also save Z coord. for use when completing the line */ + /* line_counter is static and thus will be intact upon resume */ +} /* lineTwoStep */ + +/* draw a 3D relative vector, depth-cued when appropriate */ + +static void +vector3(int i, int32 dx, int32 dy, int32 dz) /* unscaled display-file units */ +{ + int32 x0, y0, z0, x1, y1, z1; + int on0, on1; /* ONSCREEN(x0,y0), ONSCREEN(x1,y1) */ + + line_counter = 037; /* reset line-style counter */ + + dx = VSCALE(dx); /* apply vector scale (VS60) */ + dy = VSCALE(dy); + dz = VSCALE(dz * 4); + x0 = PNORM(xpos); /* (includes offset) */ + y0 = PNORM(ypos); + z0 = PNORM(zpos); + xpos += dx; + ypos += dy; + zpos += dz; + x1 = PNORM(xpos); + y1 = PNORM(ypos); + z1 = PNORM(zpos); + dx = PNORM(dx); + dy = PNORM(dy); + dz = PNORM(dz); + DEBUGF(("offset, normalized vector i%d (%ld,%ld,%ld) to (%ld,%ld,%ld)\r\n", + i, (long)x0, (long)y0, (long)z0, (long)x1, (long)y1, (long)z1)); + + /* Maintenance Switch 3 => store delta length and tangent in xpos,ypos */ + if (maint3) { + int32 adx = ABS(dx), ady = ABS(dy); + if (adx == ady) { + xpos = adx; /* or ady */ + ypos = 07777; /* (12 bits?) ~ 1.0 */ + } else if (adx > ady) { + xpos = dx; + ypos = 010000L * ady / adx; /* truncates */ /* XXX 07777L? */ + } else /* (adx < ady) */ { + xpos = dy; + ypos = 010000L * adx / ady; /* truncates */ /* XXX 07777L? */ + } + DEBUGF(("delta=0%o, tangent=0%o\r\n", xpos, ypos)); + xpos = PSCALE(xpos); /* compensates for eventual PNORM */ + ypos = PSCALE(ypos); /* compensates for eventual PNORM */ + } + + /* clip to viewport ("working surface") if necessary */ + + /* XXX not implemented yet */ + + /* check for edge conditions (XXX will change when clipping implemented) */ + on0 = ONSCREEN(x0, y0); + on1 = ONSCREEN(x1, y1); + edge_indic = on0 && !on1; + edge_flag = edge_indic || (!on0 && on1); + if (edge_flag && edge_intr_ena) { /* need to clip to viewport */ + /* XXX edge positions aren't right; need proper clipping, + then recompute using tangent register */ + edge_xpos = x1; + edge_ypos = y1; + edge_zpos = z1; + return; + } + + if (dx == 0 && dy == 0) + return; /* hardware skips null vector */ + + /* XXX for now, resort to scissoring: + illuminates only pixels that lie in the visible display area */ + + /* draw OK even when Maintenance Switch 3 is set */ + /* (but updated position registers must not be used to draw vector) */ + if (i && int0_scope) + if (menu) + lineTwoStep(x0 + MENU_OFFSET, y0, x1 + MENU_OFFSET, y1); + else + lineTwoStep(x0, y0, x1, y1); + /* XXX Depth cueing not yet right. Probably the way to do this is to + adapt a copy of lineTwoStep() to step intensity values along the + vector as it rasterizes it, calling illum3() instead of illum2(). + The unmodified lineTwoStep() should continue to be used for 2D + vectors, to avoid the overhead of recomputing constant i values. */ + + /* + * In case of LP hit, recompute coords using "tangent register", because: + * (1) pixelization can lead to off-by-1 or -2 + * (2) rasterization might not be same as VT48 computation + */ + + if (lp0_flag) { + long tangent; + int32 adx = ABS(dx), ady = ABS(dy); + if (adx >= ady) { + tangent = 010000L * dy / dx; /* signed */ + lp_ypos = y0 + tangent * (lp_xpos - x0) / 010000L; + tangent = 010000L * dz / dx; + lp_zpos = z0 + tangent * (lp_xpos - x0) / 010000L; + } else { + tangent = 010000L * dx / dy; /* signed */ + lp_xpos = x0 + tangent * (lp_ypos - y0) / 010000L; + tangent = 010000L * dz / dy; + lp_zpos = z0 + tangent * (lp_ypos - y0) / 010000L; + } + DEBUGF(("adjusted LP coords (0%o,0%o)\r\n", lp_xpos, lp_ypos)); + /* xpos,ypos,zpos still pertain to the original endpoint + (assuming that Maintenance Switch 3 isn't set) */ + } +} + +/* draw a 2D relative vector, depth-cued (constant Z) when appropriate */ + +/* for the sake of efficiency, vector2() does not invoke vector3() */ + +static void +vector2(int i, int32 dx, int32 dy) /* unscaled display-file units */ +{ + int32 x0, y0, x1, y1; + int on0, on1; /* ONSCREEN(x0,y0), ONSCREEN(x1,y1) */ + + dx = stroking ? CSCALE(dx) : VSCALE(dx); /* apply scale factor (VS60) */ + dy = stroking ? CSCALE(dy) : VSCALE(dy); + x0 = PNORM(xpos); /* (includes offset) */ + y0 = PNORM(ypos); + xpos += dx; + ypos += dy; + x1 = PNORM(xpos); + y1 = PNORM(ypos); + dx = PNORM(dx); + dy = PNORM(dy); + + if (stroking) { /* drawing a VS60 character */ + DEBUGF(("offset, normalized stroke i%d (%ld,%ld) to (%ld,%ld)\r\n", + i, (long)x0,(long)y0, (long)x1,(long)y1)); + + if (dx == 0 && dy == 0) { /* just display a point */ + if (menu) + illum2(x0 + MENU_OFFSET, y0); /* [checks ONCRT, int0_scope] */ + else + illum2(x0, y0); /* [checks ONCRT, int0_scope] */ + return; + } + } else { + DEBUGF(("[offset, normalized] vector i%d (%ld,%ld) to (%ld,%ld)\r\n", + i, (long)x0,(long)y0, (long)x1,(long)y1)); + + line_counter = 037; /* reset line-style counter */ + + /* Maintenance Switch 3 => store delta length,tangent in xpos,ypos */ + if (maint3) { + int32 adx = ABS(dx), ady = ABS(dy); + if (adx == ady) { + xpos = adx; /* or ady */ + ypos = 07777; /* (12 bits?) ~ 1.0 */ + } else if (adx > ady) { + xpos = dx; + ypos = 010000L * ady / adx; /* truncates *//* XXX 07777L? */ + } else /* (adx < ady) */ { + xpos = dy; + ypos = 010000L * adx / ady; /* truncates *//* XXX 07777L? */ + } + DEBUGF(("delta=0%o, tangent=0%o\r\n", xpos, ypos)); + xpos = PSCALE(xpos); /* compensates for eventual PNORM */ + ypos = PSCALE(ypos); /* compensates for eventual PNORM */ + } + + /* clip to viewport ("working surface") if necessary */ + + /* XXX not implemented yet */ + + /* check for edge conditions (XXX changes when clipping implemented) */ + on0 = ONSCREEN(x0, y0); + on1 = ONSCREEN(x1, y1); + edge_indic = on0 && !on1; + edge_flag = edge_indic || (!on0 && on1); + if (edge_flag && edge_intr_ena) { /* need to clip to viewport */ + /* XXX edge positions aren't right; need proper clipping, + then recompute using tangent register */ + edge_xpos = x1; + edge_ypos = y1; + edge_zpos = PNORM(zpos); + return; + } + + if (dx == 0 && dy == 0) + return; /* hardware skips null vectors */ + } + + /* XXX for now, resort to scissoring: + illuminates only pixels that lie in the visible display area */ + + /* draw OK even when Maintenance Switch 3 is set */ + /* (but updated position registers must not be used to draw vector) */ + if (i && int0_scope) + if (menu) + lineTwoStep(x0 + MENU_OFFSET, y0, x1 + MENU_OFFSET, y1); + else + lineTwoStep(x0, y0, x1, y1); + + /* + * In case of LP hit, recompute coords using "tangent register", because: + * (1) distinct virtual CRT points can be mapped into the same pixel + * (2) raster computation might not match that of the actual VT48 + */ + + if (lp0_flag) { + long tangent; + int32 adx = ABS(dx), ady = ABS(dy); + if (adx >= ady) { + tangent = 010000L * dy / dx; /* signed */ + lp_ypos = y0 + tangent * (lp_xpos - x0) / 010000L; + } else { + tangent = 010000L * dx / dy; /* signed */ + lp_xpos = x0 + tangent * (lp_ypos - y0) / 010000L; + } + DEBUGF(("adjusted LP coords (0%o,0%o)\r\n", lp_xpos, lp_ypos)); + /* xpos,ypos,zpos still pertain to the original endpoint + (assuming that Maintenance Switch 3 isn't set) */ + } +} + +/* basic vector (multiple of 45 degrees; directions numbered CCW, #0 => +X) */ +static void +basic_vector(int i, int dir, int len) /* unscaled display-file units */ +{ + int32 dx, dy; + + /* Alternatively, could be rasterized specially for each case; then + the general vector2() function could detect these special cases and + invoke this function to handle them, instead of the other way around. */ + + switch (dir) { + case 0: + dx = len; + dy = 0; + break; + case 1: + dx = len; + dy = len; + break; + case 2: + dx = 0; + dy = len; + break; + case 3: + dx = -len; + dy = len; + break; + case 4: + dx = -len; + dy = 0; + break; + case 5: + dx = -len; + dy = -len; + break; + case 6: + dx = 0; + dy = -len; + break; + case 7: + dx = len; + dy = -len; + break; + default: /* "can't happen" */ + DEBUGF(("BUG: basic vector: illegal direction %d\r\n", dir)); + return; + } + DEBUGF(("basic ")); + vector2(i, dx, dy); +} + +/* + * support for VS60 circle/arc option + * + * Since the literature that I have access to does not handle the case where + * starting and ending radii differ, I invented a solution that should be + * "good enough" for now: an approximation of an Archimedean spiral is drawn + * as connected individual chords, with the line-type counter applied (without + * being reset) over the entire curve. + * + * It is not known whether the direction is supposed to be clockwise or + * counterclockwise (the latter is assumed in the following code); it is + * assumed that if the starting and ending directions from the center point + * are identical, that a full circle is being specified. + * + * Although throughout the display simulation substantial effort has been + * invested to avoid using floating point, this preliminary implementation + * of the circle/arc generator does use floating point. Presumably this + * is avoidable, but the algorithmic details would need to be worked out. + * If use of floating point is a problem, #define NO_CONIC_OPT when compiling. + */ + +static void +conic2(int i, int32 dcx, int32 dcy, int32 dex, int32 dey) + /* unscaled display-file units */ +{ +#ifdef NO_CONIC_OPT + /* just draw vector to endpoint (like real VS60 with option missing) */ + vector2(i, dex, dey); +#else + int32 xs, ys, xc, yc, xe, ye, x, y, n; + double rs, re, dr, as, da; + int ons, one; /* ONSCREEN(xs,ys), ONSCREEN(xe,ye) */ + static double two_pi = -1.0; /* will be set (once only) to 2*Pi */ + static double k; /* will be set to 2-sqrt(4-(Pi/4)^2) */ + + if (two_pi < 0.0) { /* (initial entry only) */ + k = atan2(1.0, 1.0); + two_pi = 8.0 * k; + k = 2.0 - sqrt(4.0 - k*k); + } + dcx = VSCALE(dcx); /* apply vector scale factor */ + dcy = VSCALE(dcy); + dex = VSCALE(dex); + dey = VSCALE(dey); + xs = PNORM(xpos); /* starting pos. (includes offset) */ + ys = PNORM(ypos); + xc = PNORM(xpos + dcx); /* center pos. (includes offset) */ + yc = PNORM(ypos + dcy); + xe = PNORM(xpos + dex); /* ending pos. (includes offset) */ + ye = PNORM(ypos + dey); + /* determine vector from center to finish */ + dex -= dcx; /* PSCALEd */ + dey -= dcy; + + DEBUGF(("offset, normalized arc i%d s(%ld,%ld) c(%ld,%ld) e(%ld,%ld)\r\n", + i, (long)xs,(long)ys, (long)xc,(long)yc, (long)xe,(long)ye)); + + /* XXX not known whether Maintenance Switch 3 has any effect for arcs */ + + /* clip to viewport ("working surface") if necessary */ + + /* XXX not implemented yet [could check each chord individually] */ + + /* check for edge conditions (XXX changes when clipping implemented) */ + /* XXX this test is very crude; should be much more complex */ + ons = ONSCREEN(xs, ys); + one = ONSCREEN(xe, ye); + edge_indic = ons && !one; + edge_flag = edge_indic || (!ons && one); + if (edge_flag && edge_intr_ena) { /* need to clip to viewport */ + /* XXX edge positions aren't right; need proper clipping */ + edge_xpos = xe; + edge_ypos = ye; + edge_zpos = PNORM(zpos); + goto done; + } + + /* XXX for now, resort to scissoring: + illuminates only pixels that lie in the visible display area */ + + if (dcx == 0 && dcy == 0 && dex == 0 && dey == 0) + goto done; /* skip null curve */ + + /* determine starting, ending radii and their maximum */ + rs = PNORM(sqrt((double)dcx*dcx + (double)dcy*dcy)); /* (f.p.) */ + re = PNORM(sqrt((double)dex*dex + (double)dey*dey)); + dr = rs >= re ? rs : re; + + /* determine starting direction from center, and included angle */ + as = dcx == 0 && dcy == 0 ? 0.0 : atan2((double)-dcy, (double)-dcx); + da = (dex == 0 && dey == 0 ? 0.0 : atan2((double)dey, (double)dex)) - as; + while (da <= 0.0) /* exactly 0.0 implies full cycle */ + da += two_pi; + + /* determine number of chords to use; + make deviation from true curve no more than approximately one pixel */ + dr = reduce / dr; + if (dr > k) + dr = k; + n = (int32)(da / sqrt(4.0*dr - dr*dr) + 1.0); + if (n < 1) /* "can't happen" */ + n = 1; + else if (n > 360) + n = 360; /* arbitrarily chosen upper limit */ + + /* determine angular and radial step sizes */ + dr = (re - rs) / n; + da /= n; + + if (menu) { + xs += MENU_OFFSET; + xc += MENU_OFFSET; + xe += MENU_OFFSET; + } + + line_counter = 037; /* reset line-style counter */ + + /* draw successive chords */ + while (--n > 0) { + rs += dr; + as += da; + re = rs * cos(as); + x = xc + (re >= 0 ? (int32)(re + 0.5) : -(int32)(-re + 0.5)); + re = rs * sin(as); + y = yc + (re >= 0 ? (int32)(re + 0.5) : -(int32)(-re + 0.5)); + lineTwoStep(xs, ys, x, y); /* (applies continuing line style) */ + skip_start = 1; /* don't double-illuminate junctions */ + xs = x; + ys = y; + if (lphit_irq) + goto done; /* light-pen hit interrupted drawing */ + } + lineTwoStep(xs, ys, xe, ye); /* draw final chord to exact endpoint */ + skip_start = 0; /* important! */ + + done: + xpos += dcx + dex; /* update virtual beam position */ + ypos += dcy + dey; + if (lp0_flag) { + DEBUGF(("LP hit on arc at (0%o,0%o)\r\n", lp_xpos, lp_ypos)); + if (lphit_irq) { + /* XXX save parameters for drawing remaining chords */ + } + } +#endif +} + +static void +conic3(int i, int32 dcx, int32 dcy, int32 dcz, int32 dex, int32 dey, int32 dez) + /* unscaled display-file units */ +{ +#ifdef NO_CONIC_OPT + /* just draw vector to endpoint (like real VS60 with option missing) */ + vector3(i, dex, dey, dez); +#else + conic2(i, dcx, dcy, dex, dey); /* XXX not properly depth cued */ + zpos += PSCALE(dez); +#endif +} + +/* + * VT11 character font; + * 6x8 matrix, not serpentine encoded, decenders supported as in real VT11 + */ + +static const unsigned char dots[0200][6] = { + { 0x8f, 0x50, 0x20, 0x10, 0x08, 0x07 }, /* 000 lambda */ + { 0x1e, 0x21, 0x22, 0x14, 0x0c, 0x13 }, /* 001 alpha */ + { 0x00, 0x18, 0x24, 0xff, 0x24, 0x18 }, /* 002 phi */ + { 0x83, 0xc5, 0xa9, 0x91, 0x81, 0xc3 }, /* 003 SIGMA */ + { 0x00, 0x46, 0xa9, 0x91, 0x89, 0x06 }, /* 004 delta */ + { 0x03, 0x05, 0x09, 0x11, 0x21, 0x7f }, /* 005 DELTA */ + { 0x00, 0x20, 0x20, 0x3f, 0x01, 0x01 }, /* 006 iota */ + { 0x46, 0x29, 0x11, 0x2e, 0x40, 0x80 }, /* 007 gamma */ + { 0x7f, 0x80, 0x80, 0x80, 0x80, 0x7f }, /* 010 intersect */ + { 0x40, 0x3c, 0x04, 0xff, 0x04, 0x78 }, /* 011 psi */ + { 0x00, 0x10, 0x10, 0x54, 0x10, 0x10 }, /* 012 divide by */ + { 0x00, 0x60, 0x90, 0x90, 0x60, 0x00 }, /* 013 degree */ + { 0x00, 0x01, 0x00, 0x10, 0x00, 0x01 }, /* 014 therefore */ + { 0x01, 0x02, 0x3c, 0x02, 0x02, 0x3c }, /* 015 mu */ + { 0x11, 0x7f, 0x91, 0x81, 0x41, 0x03 }, /* 016 pound sterling */ + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, /* 017 SHIFT IN */ + { 0x20, 0x40, 0x7f, 0x40, 0x7f, 0x40 }, /* 020 pi */ + { 0x00, 0xff, 0x00, 0x00, 0xff, 0x00 }, /* 021 parallel */ + { 0x1d, 0x23, 0x40, 0x42, 0x25, 0x19 }, /* 022 OMEGA */ + { 0x1c, 0x22, 0x61, 0x51, 0x4e, 0x40 }, /* 023 sigma */ + { 0x20, 0x40, 0x40, 0x7f, 0x40, 0x40 }, /* 024 UPSILON */ + { 0x00, 0x1c, 0x2a, 0x49, 0x49, 0x00 }, /* 025 epsilon */ + { 0x10, 0x38, 0x54, 0x10, 0x10, 0x10 }, /* 026 left arrow */ + { 0x10, 0x10, 0x10, 0x54, 0x38, 0x10 }, /* 027 right arrow */ + { 0x00, 0x20, 0x40, 0xfe, 0x40, 0x20 }, /* 030 up arrow */ + { 0x00, 0x04, 0x02, 0x7f, 0x02, 0x04 }, /* 031 down arrow */ + { 0x00, 0xff, 0x80, 0x80, 0x80, 0x80 }, /* 032 GAMMA */ + { 0x00, 0x01, 0x01, 0xff, 0x01, 0x01 }, /* 033 perpendicular */ + { 0x2a, 0x2c, 0x28, 0x38, 0x68, 0xa8 }, /* 034 unequal */ + { 0x24, 0x48, 0x48, 0x24, 0x24, 0x48 }, /* 035 approx equal */ + { 0x00, 0x20, 0x10, 0x08, 0x10, 0x20 }, /* 036 vel */ + { 0xff, 0x81, 0x81, 0x81, 0x81, 0xff }, /* 037 box */ + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, /* 040 space */ + { 0x00, 0x00, 0x00, 0xfd, 0x00, 0x00 }, /* 041 ! */ + { 0x00, 0xe0, 0x00, 0x00, 0xe0, 0x00 }, /* 042 " */ + { 0x00, 0x24, 0xff, 0x24, 0xff, 0x24 }, /* 043 # */ + { 0x22, 0x52, 0xff, 0x52, 0x4c, 0x00 }, /* 044 $ */ + { 0x42, 0xa4, 0x48, 0x12, 0x25, 0x42 }, /* 045 % */ + { 0x66, 0x99, 0x99, 0x66, 0x0a, 0x11 }, /* 046 & */ + { 0x00, 0x00, 0x20, 0x40, 0x80, 0x00 }, /* 047 ' */ + { 0x00, 0x00, 0x3c, 0x42, 0x81, 0x00 }, /* 050 ( */ + { 0x00, 0x00, 0x81, 0x42, 0x3c, 0x00 }, /* 051 ) */ + { 0x00, 0x44, 0x28, 0xf0, 0x28, 0x44 }, /* 052 * */ + { 0x00, 0x10, 0x10, 0x7c, 0x10, 0x10 }, /* 053 + */ + { 0x00, 0x01, 0x06, 0x00, 0x00, 0x00 }, /* 054 , */ + { 0x00, 0x10, 0x10, 0x10, 0x10, 0x10 }, /* 055 - */ + { 0x00, 0x00, 0x06, 0x06, 0x00, 0x00 }, /* 056 . */ + { 0x02, 0x04, 0x08, 0x10, 0x20, 0x40 }, /* 057 / */ + { 0x7e, 0x85, 0x89, 0x91, 0xa1, 0x7e }, /* 060 0 */ + { 0x00, 0x41, 0xff, 0x01, 0x00, 0x00 }, /* 061 1 */ + { 0x47, 0x89, 0x91, 0x91, 0x91, 0x61 }, /* 062 2 */ + { 0x42, 0x81, 0x91, 0xb1, 0xd1, 0x8e }, /* 063 3 */ + { 0x0c, 0x14, 0x24, 0x44, 0xff, 0x04 }, /* 064 4 */ + { 0xf2, 0x91, 0x91, 0x91, 0x91, 0x8e }, /* 065 5 */ + { 0x3c, 0x46, 0x89, 0x89, 0x89, 0x46 }, /* 066 6 */ + { 0x40, 0x87, 0x88, 0x90, 0xa0, 0xc0 }, /* 067 7 */ + { 0x6e, 0x91, 0x91, 0x91, 0x91, 0x6e }, /* 070 8 */ + { 0x62, 0x91, 0x91, 0x91, 0x62, 0x3c }, /* 071 9 */ + { 0x00, 0x66, 0x66, 0x00, 0x00, 0x00 }, /* 072 : */ + { 0x00, 0x00, 0x61, 0x66, 0x00, 0x00 }, /* 073 ; */ + { 0x00, 0x18, 0x24, 0x42, 0x81, 0x00 }, /* 074 < */ + { 0x00, 0x28, 0x28, 0x28, 0x28, 0x28 }, /* 075 = */ + { 0x00, 0x81, 0x42, 0x24, 0x18, 0x00 }, /* 076 > */ + { 0x00, 0x40, 0x80, 0x9d, 0x90, 0x60 }, /* 077 ? */ + { 0x3c, 0x42, 0x91, 0xa9, 0xa9, 0x72 }, /* 100 @ */ + { 0x3f, 0x48, 0x88, 0x88, 0x48, 0x3f }, /* 101 A */ + { 0x81, 0xff, 0x91, 0x91, 0x91, 0x6e }, /* 102 B */ + { 0x3c, 0x42, 0x81, 0x81, 0x81, 0x42 }, /* 103 C */ + { 0x81, 0xff, 0x81, 0x81, 0x42, 0x3c }, /* 104 D */ + { 0x81, 0xff, 0x91, 0x91, 0x91, 0xc3 }, /* 105 E */ + { 0x81, 0xff, 0x91, 0x90, 0x80, 0xc0 }, /* 106 F */ + { 0x3c, 0x42, 0x81, 0x89, 0x89, 0x4f }, /* 107 G */ + { 0xff, 0x10, 0x10, 0x10, 0x10, 0xff }, /* 110 H */ + { 0x00, 0x81, 0xff, 0x81, 0x00, 0x00 }, /* 111 I */ + { 0x0e, 0x01, 0x01, 0x81, 0xfe, 0x80 }, /* 112 J */ + { 0xff, 0x08, 0x10, 0x28, 0x44, 0x83 }, /* 113 K */ + { 0x81, 0xff, 0x81, 0x01, 0x01, 0x03 }, /* 114 L */ + { 0xff, 0x40, 0x30, 0x30, 0x40, 0xff }, /* 115 M */ + { 0xff, 0x20, 0x10, 0x08, 0x04, 0xff }, /* 116 N */ + { 0x3c, 0x42, 0x81, 0x81, 0x42, 0x3c }, /* 117 O */ + { 0x81, 0xff, 0x90, 0x90, 0x90, 0x60 }, /* 120 P */ + { 0x3c, 0x42, 0x81, 0x8f, 0x42, 0x3d }, /* 121 Q */ + { 0x81, 0xff, 0x90, 0x98, 0x94, 0x63 }, /* 122 R */ + { 0x22, 0x51, 0x91, 0x91, 0x89, 0x46 }, /* 123 S */ + { 0xc0, 0x80, 0x81, 0xff, 0x81, 0xc0 }, /* 124 T */ + { 0xfe, 0x01, 0x01, 0x01, 0x01, 0xfe }, /* 125 U */ + { 0xff, 0x02, 0x04, 0x08, 0x10, 0xe0 }, /* 126 V */ + { 0xff, 0x02, 0x0c, 0x0c, 0x02, 0xff }, /* 127 W */ + { 0xc3, 0x24, 0x18, 0x18, 0x24, 0xc3 }, /* 130 X */ + { 0x00, 0xe0, 0x10, 0x0f, 0x10, 0xe0 }, /* 131 Y */ + { 0x83, 0x85, 0x89, 0x91, 0xa1, 0xc1 }, /* 132 Z */ + { 0x00, 0x00, 0xff, 0x81, 0x81, 0x00 }, /* 133 [ */ + { 0x00, 0x40, 0x20, 0x10, 0x08, 0x04 }, /* 134 \ */ + { 0x00, 0x00, 0x81, 0x81, 0xff, 0x00 }, /* 135 ] */ + { 0x00, 0x10, 0x20, 0x40, 0x20, 0x10 }, /* 136 ^ */ + { 0x01, 0x01, 0x01, 0x01, 0x01, 0x00 }, /* 137 _ */ + /* for all lowercase characters, first column is just a "descender" flag: */ + { 0x00, 0x00, 0x80, 0x40, 0x20, 0x00 }, /* 140 ` */ + { 0x00, 0x26, 0x29, 0x29, 0x2a, 0x1f }, /* 141 a */ + { 0x00, 0xff, 0x12, 0x21, 0x21, 0x1e }, /* 142 b */ + { 0x00, 0x1e, 0x21, 0x21, 0x21, 0x12 }, /* 143 c */ + { 0x00, 0x1e, 0x21, 0x21, 0x12, 0xff }, /* 144 d */ + { 0x00, 0x1e, 0x29, 0x29, 0x29, 0x19 }, /* 145 e */ + { 0x00, 0x20, 0x7f, 0xa0, 0xa0, 0x80 }, /* 146 f */ + { 0x01, 0x78, 0x85, 0x85, 0x49, 0xfe }, /* 147 g */ + { 0x00, 0xff, 0x10, 0x20, 0x20, 0x1f }, /* 150 h */ + { 0x00, 0x00, 0x21, 0xbf, 0x01, 0x00 }, /* 151 i */ + { 0x01, 0x02, 0x01, 0x81, 0xfe, 0x00 }, /* 152 j */ + { 0x00, 0xff, 0x08, 0x14, 0x22, 0x21 }, /* 153 k */ + { 0x00, 0x00, 0xfe, 0x01, 0x01, 0x00 }, /* 154 l */ + { 0x00, 0x3f, 0x20, 0x3f, 0x20, 0x3f }, /* 155 m */ + { 0x00, 0x3f, 0x10, 0x20, 0x20, 0x1f }, /* 156 n */ + { 0x00, 0x1e, 0x21, 0x21, 0x21, 0x1e }, /* 157 o */ + { 0x01, 0xff, 0x48, 0x84, 0x84, 0x78 }, /* 160 p */ + { 0x01, 0x78, 0x84, 0x84, 0x48, 0xff }, /* 161 q */ + { 0x00, 0x3f, 0x08, 0x10, 0x20, 0x20 }, /* 162 r */ + { 0x00, 0x12, 0x29, 0x29, 0x29, 0x26 }, /* 163 s */ + { 0x00, 0x20, 0xfe, 0x21, 0x21, 0x00 }, /* 164 t */ + { 0x00, 0x3e, 0x01, 0x01, 0x02, 0x3f }, /* 165 u */ + { 0x00, 0x3c, 0x02, 0x01, 0x02, 0x3c }, /* 166 v */ + { 0x00, 0x3e, 0x01, 0x1e, 0x01, 0x3e }, /* 167 w */ + { 0x00, 0x23, 0x14, 0x08, 0x14, 0x23 }, /* 170 x */ + { 0x01, 0xf8, 0x05, 0x05, 0x09, 0xfe }, /* 171 y */ + { 0x00, 0x23, 0x25, 0x29, 0x31, 0x21 }, /* 172 z */ + { 0x00, 0x18, 0x66, 0x81, 0x81, 0x00 }, /* 173 { */ + { 0x00, 0x00, 0xe7, 0x00, 0x00, 0x00 }, /* 174 | */ + { 0x00, 0x00, 0x81, 0x81, 0x66, 0x18 }, /* 175 } */ + { 0x00, 0x0c, 0x10, 0x08, 0x04, 0x18 }, /* 176 ~ */ + { 0x00, 0xff, 0xff, 0xff, 0xff, 0xff } /* 177 rubout */ +}; + +/* + * VS60 character stroke table + * + * stroke[] contains "prototype" encodings for all vector strokes (visible and + * invisible) needed to draw each character at a standard size. The actual + * display is of course properly italicized, positioned, scaled, and rotated. + * + * Variable-length entries are used; each character stroke sequence is + * terminated by a 0-valued byte. Pointers to the appropriate data for all + * characters are stored into sstroke[] during a one-time initialization. + * + * The prototype strokes are for the most part constrained to a 4x6 unit area, + * except for a few cases that are handled by kludging the coordinates. + * Coordinates are relative to the left end of the character baseline. + * + * A prototype stroke is encoded as 8 bits SVXXXYYY: + * S = 0 if YYY is correct as is + * 1 if YYY needs to have 2 subtracted + * V = 0 if stroke is invisible (move) + * 1 if stroke is visible (draw) + * XXX = final X coord of stroke (0..4; 7 => -1) + * YYY = final Y coord of stroke (0..6) + */ + +static const unsigned char stroke[] = { + /* + * While based on the actual VT48 strokes, these have been tweaked + * (especially the lower-case letters, which had erratic sizes) to + * improve their appearance and/or reduce the number of strokes. + * Several of the special symbols (e.g. alpha, delta, iota) could + * be further improved, but I didn't want to make them look too + * different from the original. Note that VS60 screen photos + * disagree, for several characters, with the (incomplete) chart of + * strokes given in the VT48 manual. (There could have been ROM changes.) + * + * The simulated character sizes are not exact at all scales, but there + * is no really good way to fix this without spoiling the appearance. + * char. scale VS60 units simulation units (pixel has size!) + * 1/2 5 x 7 5 x 7 + * 1 10 x 14 9 x 13 + * 3/2 15 x 21 13 x 19 + * 2 20 x 28 17 x 25 + */ + 0111, 0123, 0006, 0115, 0131, 0140, 0, /* 000 lambda */ + 0042, 0132, 0114, 0103, 0112, 0134, 0144, 0, /* 001 alpha */ + 0011, 0103, 0115, 0135, 0143, 0131, 0111, 0010, + 0146, 0, /* 002 phi */ + 0040, 0100, 0133, 0106, 0146, 0, /* 003 SIGMA */ + 0022, 0111, 0120, 0131, 0113, 0115, 0124, 0, /* 004 delta */ + 0140, 0124, 0100, 0, /* 005 DELTA */ + 0006, 0126, 0120, 0140, 0, /* 006 iota */ + 0006, 0115, 0131, 0120, 0111, 0135, 0146, 0, /* 007 gamma */ + 0104, 0116, 0136, 0144, 0140, 0, /* 010 intersect */ + 0010, 0136, 0044, 0142, 0131, 0111, 0102, 0104, 0, /* 011 psi */ + 0022, 0122, 0003, 0143, 0024, 0124, 0, /* 012 divide by */ + 0024, 0115, 0126, 0135, 0124, 0, /* 013 degree */ + 0001, 0101, 0025, 0125, 0041, 0141, 0, /* 014 therefore */ + 0111, 0115, 0012, 0121, 0131, 0142, 0045, 0142, + 0151, 0, /* 015 mu */ + 0105, 0116, 0126, 0135, 0013, 0173, 0001, 0120, + 0130, 0141, 0, /* 016 pound sterling */ + 0, /* 017 SHIFT IN */ + 0003, 0114, 0144, 0034, 0130, 0010, 0114, 0, /* 020 pi */ + 0010, 0116, 0036, 0130, 0, /* 021 parallel */ + 0110, 0111, 0102, 0104, 0115, 0135, 0144, 0142, + 0131, 0130, 0140, 0, /* 022 OMEGA */ + 0025, 0134, 0132, 0120, 0110, 0102, 0104, 0146, 0, /* 023 sigma */ + 0010, 0136, 0046, 0116, 0105, 0, /* 024 UPSILON */ + 0003, 0133, 0045, 0136, 0116, 0105, 0101, 0110, + 0130, 0141, 0, /* 025 epsilon */ + 0042, 0102, 0113, 0011, 0102, 0, /* 026 left arrow */ + 0002, 0142, 0133, 0031, 0142, 0, /* 027 right arrow */ + 0020, 0124, 0133, 0013, 0124, 0, /* 030 up arrow */ + 0024, 0120, 0131, 0011, 0120, 0, /* 031 down arrow */ + 0106, 0146, 0144, 0, /* 032 GAMMA */ + 0140, 0026, 0120, 0, /* 033 perpendicular */ + 0001, 0145, 0044, 0104, 0002, 0142, 0, /* 034 unequal */ + 0001, 0112, 0131, 0142, 0044, 0133, 0114, 0103, 0, /* 035 approx equal */ + 0016, 0125, 0135, 0146, 0, /* 036 vel */ + 0106, 0146, 0140, 0100, 0, /* 037 box */ + 0, /* 040 space */ + 0020, 0120, 0021, 0125, 0, /* 041 ! */ + 0004, 0126, 0046, 0124, 0, /* 042 " */ + 0012, 0116, 0036, 0132, 0043, 0103, 0005, 0145, 0, /* 043 # */ + 0001, 0110, 0130, 0141, 0142, 0133, 0113, 0104, + 0105, 0116, 0136, 0145, 0026, 0120, 0, /* 044 $ */ + 0146, 0116, 0105, 0114, 0125, 0116, 0032, 0141, + 0130, 0121, 0132, 0, /* 045 % */ + 0040, 0104, 0105, 0116, 0126, 0135, 0134, 0101, + 0110, 0120, 0142, 0, /* 046 & */ + 0014, 0136, 0, /* 047 ' */ + 0030, 0112, 0114, 0136, 0, /* 050 ( */ + 0010, 0132, 0134, 0116, 0, /* 051 ) */ + 0002, 0146, 0026, 0122, 0042, 0106, 0, /* 052 * */ + 0021, 0125, 0003, 0143, 0, /* 053 + */ + 0211, 0120, 0121, 0, /* 054 , */ + 0003, 0143, 0, /* 055 - */ + 0020, 0120, 0, /* 056 . */ + 0146, 0, /* 057 / */ + 0001, 0145, 0136, 0116, 0105, 0101, 0110, 0130, + 0141, 0145, 0, /* 060 0 */ + 0010, 0130, 0020, 0126, 0115, 0, /* 061 1 */ + 0005, 0116, 0136, 0145, 0144, 0100, 0140, 0, /* 062 2 */ + 0001, 0110, 0130, 0141, 0142, 0133, 0113, 0005, + 0116, 0136, 0145, 0144, 0133, 0, /* 063 3 */ + 0030, 0136, 0025, 0102, 0142, 0, /* 064 4 */ + 0001, 0110, 0130, 0141, 0143, 0134, 0114, 0103, + 0106, 0146, 0, /* 065 5 */ + 0002, 0113, 0133, 0142, 0141, 0130, 0110, 0101, + 0105, 0116, 0136, 0145, 0, /* 066 6 */ + 0006, 0146, 0120, 0, /* 067 7 */ + 0013, 0133, 0142, 0141, 0130, 0110, 0101, 0102, + 0113, 0104, 0105, 0116, 0136, 0145, 0144, 0133, 0, /* 070 8 */ + 0001, 0110, 0130, 0141, 0145, 0136, 0116, 0105, + 0104, 0113, 0133, 0144, 0, /* 071 9 */ + 0022, 0122, 0024, 0124, 0, /* 072 : */ + 0010, 0121, 0122, 0024, 0124, 0, /* 073 ; */ + 0030, 0103, 0136, 0, /* 074 < */ + 0002, 0142, 0004, 0144, 0, /* 075 = */ + 0010, 0143, 0116, 0, /* 076 > */ + 0020, 0120, 0021, 0122, 0144, 0145, 0136, 0116, + 0105, 0104, 0, /* 077 ? */ + 0030, 0110, 0101, 0104, 0115, 0145, 0141, 0121, + 0112, 0113, 0124, 0134, 0131, 0, /* 100 @ */ + 0104, 0116, 0136, 0144, 0140, 0042, 0102, 0, /* 101 A */ + 0106, 0136, 0145, 0144, 0133, 0103, 0033, 0142, + 0141, 0130, 0100, 0, /* 102 B */ + 0041, 0130, 0110, 0101, 0105, 0116, 0136, 0145, 0, /* 103 C */ + 0106, 0136, 0145, 0141, 0130, 0100, 0, /* 104 D */ + 0003, 0133, 0046, 0106, 0100, 0140, 0, /* 105 E */ + 0106, 0146, 0033, 0103, 0, /* 106 F */ + 0023, 0143, 0141, 0130, 0110, 0101, 0105, 0116, + 0136, 0145, 0, /* 107 G */ + 0106, 0003, 0143, 0046, 0140, 0, /* 110 H */ + 0010, 0130, 0020, 0126, 0016, 0136, 0, /* 111 I */ + 0001, 0110, 0120, 0131, 0136, 0, /* 112 J */ + 0106, 0046, 0102, 0024, 0140, 0, /* 113 K */ + 0006, 0100, 0140, 0, /* 114 L */ + 0106, 0123, 0146, 0140, 0, /* 115 M */ + 0106, 0140, 0146, 0, /* 116 N */ + 0001, 0105, 0116, 0136, 0145, 0141, 0130, 0110, + 0101, 0, /* 117 O */ + 0106, 0136, 0145, 0144, 0133, 0103, 0, /* 120 P */ + 0030, 0110, 0101, 0105, 0116, 0136, 0145, 0141, + 0130, 0031, 0140, 0, /* 121 Q */ + 0106, 0136, 0145, 0144, 0133, 0103, 0033, 0140, 0, /* 122 R */ + 0001, 0110, 0130, 0141, 0142, 0133, 0113, 0104, + 0105, 0116, 0136, 0145, 0, /* 123 S */ + 0020, 0126, 0006, 0146, 0, /* 124 T */ + 0006, 0101, 0110, 0130, 0141, 0146, 0, /* 125 U */ + 0006, 0120, 0146, 0, /* 126 V */ + 0006, 0100, 0123, 0140, 0146, 0, /* 127 W */ + 0146, 0006, 0140, 0, /* 130 X */ + 0020, 0123, 0106, 0046, 0123, 0, /* 131 Y */ + 0006, 0146, 0100, 0140, 0033, 0113, 0, /* 132 Z */ + 0030, 0110, 0116, 0136, 0, /* 133 [ */ + 0006, 0140, 0, /* 134 \ */ + 0010, 0130, 0136, 0116, 0, /* 135 ] */ + 0003, 0126, 0143, 0, /* 136 ^ */ + 0140, 0, /* 137 _ */ + 0016, 0134, 0, /* original was backward */ /* 140 ` */ + 0032, 0112, 0101, 0110, 0130, 0133, 0124, 0114, 0, /* 141 a */ + 0006, 0100, 0120, 0131, 0133, 0124, 0104, 0, /* 142 b */ + 0033, 0124, 0114, 0103, 0101, 0110, 0120, 0131, 0, /* 143 c */ + 0036, 0130, 0110, 0101, 0103, 0114, 0134, 0, /* 144 d */ + 0002, 0132, 0133, 0124, 0114, 0103, 0101, 0110, + 0120, 0, /* 145 e */ + 0010, 0115, 0126, 0136, 0145, 0023, 0103, 0, /* 146 f */ + 0200, 0320, 0331, 0134, 0114, 0103, 0101, 0110, + 0130, 0, /* 147 g */ + 0106, 0004, 0124, 0133, 0130, 0, /* 150 h */ + 0020, 0124, 0025, 0125, 0, /* 151 i */ + 0201, 0310, 0320, 0331, 0134, 0035, 0135, 0, /* 152 j */ + 0105, 0034, 0101, 0023, 0130, 0, /* 153 k */ + 0010, 0130, 0020, 0126, 0116, 0, /* 154 l */ + 0104, 0114, 0122, 0134, 0144, 0140, 0, /* 155 m */ + 0104, 0124, 0133, 0130, 0, /* 156 n */ + 0010, 0120, 0131, 0133, 0124, 0114, 0103, 0101, + 0110, 0, /* 157 o */ + 0200, 0104, 0124, 0133, 0131, 0120, 0100, 0, /* 160 p */ + 0030, 0110, 0101, 0103, 0114, 0134, 0330, 0341, 0, /* 161 q */ + 0104, 0124, 0133, 0, /* 162 r */ + 0001, 0110, 0120, 0131, 0122, 0112, 0103, 0114, + 0124, 0133, 0, /* 163 s */ + 0030, 0121, 0125, 0034, 0114, 0, /* 164 t */ + 0014, 0111, 0120, 0130, 0141, 0144, 0, /* 165 u */ + 0004, 0120, 0144, 0, /* 166 v */ + 0004, 0102, 0110, 0122, 0130, 0142, 0144, 0, /* 167 w */ + 0134, 0004, 0130, 0, /* 170 x */ + 0210, 0120, 0134, 0004, 0120, 0, /* 171 y */ + 0004, 0134, 0100, 0130, 0, /* 172 z */ + 0030, 0121, 0122, 0113, 0124, 0125, 0136, 0, /* 173 { */ + 0020, 0122, 0024, 0126, 0, /* 174 | */ + 0010, 0121, 0122, 0133, 0124, 0125, 0116, 0, /* 175 } */ + 0003, 0114, 0132, 0143, 0, /* 176 ~ */ + 0140, 0146, 0106, 0100, 0010, 0116, 0026, 0120, + 0030, 0136, 0 /* 177 rubout */ + }; + +/* pointers to start of stroke data for each character */ +static const unsigned char *sstroke[128] = { NULL }; /* init. at run time */ + +/* character generator; + * supports control characters, POPR on terminating character (VS60) + */ + +static int /* returns nonzero iff VS60 char terminate feature triggered */ +character(int c) +{ + /* following 3 tables map cs_index to adjustments for sub/superscript */ + static const unsigned char sus_left[4] = + {PSCALE(0), PSCALE(1), PSCALE(2), PSCALE(3)}; + static const unsigned char sub_down[4] = + {PSCALE(2), PSCALE(4), PSCALE(6), PSCALE(8)}; + static const unsigned char sup_up[4] = + {PSCALE(5), PSCALE(10), PSCALE(15), PSCALE(20)}; + int x, y; + int32 xbase, ybase, xnext, ynext; + + char_buf = c; + + if (shift_out) { + if (c >= 040) { + char_irq = 1; /* will generate a char intr. */ + return 0; /* presumably, no POPR on term? */ + } + if (c == 017) { /* SHIFT IN */ + shift_out = 0; + goto cesc; + } + + } else { /* !shift_out */ + + if (c <= 040) { + switch (c) { + + case 010: /* BACKSPACE */ + if (char_rotate) + ypos -= CSCALE(vt11_csp_w); + else + xpos -= CSCALE(vt11_csp_w); + break; + case 012: /* LINE FEED */ + if (char_rotate) + xpos += CSCALE(vt11_csp_h); + else + ypos -= CSCALE(vt11_csp_h); + break; + case 015: /* CARRIAGE RETURN */ + if (char_rotate) + ypos = yoff; + else + xpos = xoff; + break; + case 016: /* SHIFT OUT */ + shift_out = 1; + break; + + case 021: /* SUPERSCRIPT */ + if (VT11) + break; + if (char_rotate) { + xpos -= sup_up[cs_index]; + ypos -= sus_left[cs_index]; + } else { + xpos -= sus_left[cs_index]; + ypos += sup_up[cs_index]; + } + if (cs_index > 0) + char_scale = csi2csf[--cs_index]; + break; + case 022: /* SUBSCRIPT */ + if (VT11) + break; + if (char_rotate) { + xpos += sub_down[cs_index]; + ypos -= sus_left[cs_index]; + } else { + xpos -= sus_left[cs_index]; + ypos -= sub_down[cs_index]; + } + if (cs_index > 0) + char_scale = csi2csf[--cs_index]; + break; + case 023: /* END SUPERSCRIPT */ + if (VT11) + break; + if (cs_index < 3) + char_scale = csi2csf[++cs_index]; + if (char_rotate) { + xpos += sup_up[cs_index]; + ypos += sus_left[cs_index]; + } else { + xpos += sus_left[cs_index]; + ypos -= sup_up[cs_index]; + } + break; + case 024: /* END SUBSCRIPT */ + if (VT11) + break; + if (cs_index < 3) + char_scale = csi2csf[++cs_index]; + if (char_rotate) { + xpos -= sub_down[cs_index]; + ypos += sus_left[cs_index]; + } else { + xpos += sus_left[cs_index]; + ypos += sub_down[cs_index]; + } + break; + case 040: /* SPACE */ + goto space; + default: /* other control codes ignored */ + break; + } + goto cesc; + } + } + + /* VT11/VS60 doesn't draw any part of a character if its *baseline* is + (partly) offscreen; thus the top of a character might be clipped */ + /* (no allowance for descender, italic, or interchar. spacing) */ + + /* virtual CRT coordinates of this and the next character's "origin": */ + xbase = xnext = PNORM(xpos); + ybase = ynext = PNORM(ypos); + if (char_rotate) + ynext += (vt11_csp_w <= 12 ? 10 : 11); + else + xnext += (vt11_csp_w <= 12 ? 10 : 11); + + edge_indic = ONSCREEN(xbase, ybase) && !ONSCREEN(xnext, ynext); + edge_flag = edge_indic || + !ONSCREEN(xbase, ybase) && ONSCREEN(xnext, ynext); + /* (scaling cannot make spacing so large that it crosses the + "working surface" while going from offscreen to offscreen) */ + if (edge_flag && edge_intr_ena) { + edge_irq = 1; + goto space; + } + + if (!ONSCREEN(xbase, ybase) || !ONSCREEN(xnext, ynext)) + goto space; + + /* plot a (nominally on-screen) graphic symbol */ + + if (VT11) { + unsigned char col, prvcol; + + /* plot a graphic symbol (unscaled, unrotated) using a dot matrix */ + + /* not drawn in a serpentine manner; supports control characters */ + + /* draw pattern using 2x2 dot size, with fudges for spacing & italics */ + /* (looks very nice under all conditions at full resolution) */ + + if (c >= 0140) { /* lower-case */ + if (dots[c][0]) /* flag: with descender */ + ybase -= 4; + x = 1; /* skip first column (descender flag) */ + } else /* no descender */ + x = 0; + + prvcol = 0; + col = dots[c][x]; /* starting column bit pattern */ + for (; x < 6; ++x) { + int xllc = 2*x, yllc = 0; + unsigned char nxtcol = (x == 5) ? 0 : dots[c][x+1]; + + /* no LP hit on first or last column */ + lp_suppress = x == 0 || x == 5; + + for (y = 0; y < 8; ++y) { + int delay_skew; + int compress = vt11_csp_w <= 12 && x == 2; + int dot = col & (1<>y) == 2)) + ++xllc; /* shift within selected dots */ + } + ++yllc; + if (dot) { + illum2(xbase + xllc, ybase + yllc); + if (!compress || nxtdot == 0) + illum2(xbase + xllc + 1, ybase + yllc); + } + if (italics && delay_skew) + ++xllc; /* shift between selected dots */ + ++yllc; + } + if (vt11_csp_w <= 12 && x == 2) /* narrow spacing: */ + --xbase; /* slight compression */ + + prvcol = col; + col = nxtcol; + } + lp_suppress = 0; + + } else { /* VS60 */ + const unsigned char *p; /* -> stroke data */ + unsigned char s; /* encoded stroke */ + int32 xlast, ylast; /* "beam follower" within character */ + int32 xp = xpos, yp = ypos; /* save these (altered by vector2()) */ + + /* plot a graphic symbol using vector strokes */ + + /* initialize starting stroke pointers upon first use only */ + if (sstroke[0] == NULL) { + p = stroke; /* -> stroke data */ + + for (s = 0; s < 128; ++s) { /* for each ASCII code value s */ + sstroke[s] = p; /* code's stroke list starts here */ + while (*p++) /* 0 terminates the data */ + ; + } + } + + stroking = 1; /* prevents stroke clipping etc. and + tells vector2() to apply global + character scale factor */ + xlast = ylast = 0; + for (p = sstroke[c]; (s = *p) != 0; ++p) { + xnext = (s & 0070) >> 3; + if (xnext == 7) + xnext = -1; /* (kludge needed for pound sterling) */ + ynext = s & 0007; /* delay stretching for just a moment */ + if (s & 0200) + ynext -= 2; /* kludge for stroke below baseline */ + xnext *= 2; + if (italics) + xnext += ynext; + ynext *= 2; /* safe to stretch now */ + + if (s & 0100) { /* visible stroke */ + int32 dx = xnext - xlast, /* (okay if both 0) */ + dy = ynext - ylast; + + if (char_rotate) + vector2(1, -dy, dx); + else + vector2(1, dx, dy); + } else /* invisible stroke, can do faster */ + if (char_rotate) { + xpos = xp - CSCALE(ynext); + ypos = yp + CSCALE(xnext); + } else { + xpos = xp + CSCALE(xnext); + ypos = yp + CSCALE(ynext); + } + xlast = xnext; + ylast = ynext; + skip_start = (s & 0100) && (p[1] & 0100); /* avoid bright dot */ + } + /* skip_start was reset to 0 by the last iteration! */ + stroking = 0; + xpos = xp; /* restore for use in spacing (below) */ + ypos = yp; + } /* end of graphic character drawing */ + + space: + if (char_rotate) + ypos += CSCALE(vt11_csp_w); + else + xpos += CSCALE(vt11_csp_w); + + /* There may have been multiple LP hits during drawing; + the last one is the only one that can be reported. */ + + cesc: + if (char_escape && c == char_term) { /* (VS60) */ + pop(1); + return 1; + } else + return 0; +} + +/* + * Perform one display processor "cycle": + * If display processor is halted or awaiting sync, just performs "background" + * maintenance tasks and returns 0. + * Otherwise, completes any pending second CHAR or BSVECT (must be a RESUME + * after interrupt on first CHAR or BSVECT), or fetches one word from the + * display file and processes it. May post an interrupt; returns 1 if display + * processor is still running, or 0 if halted or an interrupt was posted. + * + * word_number keeps track of the state of multi-word graphic data parsing; + * word_number also serves to keep track of half-word for graphic data having + * two independent entities encoded within one word (CHAR or BSVECT). + * Note that, for the VT11, there might be control words (e.g. JMPA) embedded + * within the data! (We don't know of any application that exploits this.) + */ +int +vt11_cycle(int us, int slowdown) +{ + static vt11word inst; + static int i; + static int32 x, y, z, ex, ey, sxo, syo, szo; + int c; + int32 ez; + static uint32 usec = 0; /* cumulative */ + static uint32 msec = 0; /* ditto */ + uint32 new_msec; + INIT + /* keep running time counter; track state even when processor is idle */ + + new_msec = (usec += us) / 1000; + + if (msec / BLINK_COUNT != new_msec / BLINK_COUNT) + blink_off = !blink_off; + + /* if awaiting sync, look for next frame start */ + if (sync_period && (msec / sync_period != new_msec / sync_period)) + sync_period = 0; /* start next frame */ + + msec = new_msec; + + if ((sync_period || maint1 || !busy) && !maint2) + goto age_ret; /* just age the display */ + + /* fetch next word from display file (if needed) and process it */ + + if (word_number != 1 || (graphic_mode != CHAR && graphic_mode != BSVECT)) { + time_out = vt_fetch((uint32)((DPC+reloc)&0777777), &inst); + DPC += 2; + if (time_out) + goto bus_timeout; + DEBUGF(("0%06o: 0%06o\r\n", + (unsigned)(DPC - 2 + reloc) & 0777777, (unsigned)inst)); + if (finish_jmpa) + goto jmpa; + if (finish_jsra) + goto jsra; + } + /* else have processed only half the CHAR or BSVECT data word so far */ + + fetched: + + if (TESTBIT(inst,15)) { /* control */ + unsigned op = GETFIELD(inst,14,11); /* bits 14-11 */ +#if 1 /* XXX not sure about VT11 behavior */ + if (VS60) +#endif + word_number = 0; /* according to VT48 ES */ + switch (op) { + + case 7: /* Set Graphic Mode 0111 */ + case 011: /* Set Graphic Mode 1001 */ + if (VT11) + goto bad_ins; + /*FALLTHRU*/ + case 010: /* Set Graphic Mode 1000 */ + if (VT11) { + DEBUGF(("SGM 1000 IGNORED\r\n")); + break; + } + /*FALLTHRU*/ + case 0: /* Set Graphic Mode 0000 */ + case 1: /* Set Graphic Mode 0001 */ + case 2: /* Set Graphic Mode 0010 */ + case 3: /* Set Graphic Mode 0011 */ + case 4: /* Set Graphic Mode 0100 */ + case 5: /* Set Graphic Mode 0101 */ + case 6: /* Set Graphic Mode 0110 */ + DEBUGF(("Set Graphic Mode %u", op)); + graphic_mode = op; + word_number = 0; /* XXX redundant? (see above) */ + shift_out = 0; /* XXX is this right? */ + if (TESTBIT(inst,10)) { + intensity = GETFIELD(inst,9,7); + DEBUGF((" intensity=%d", (int)intensity)); + } + if (TESTBIT(inst,6)) { + lp0_intr_ena = TESTBIT(inst,5); + DEBUGF((" lp0_intr_ena=%d", (int)lp0_intr_ena)); + } + if (TESTBIT(inst,4)) { + blink_ena = TESTBIT(inst,3); + DEBUGF((" blink=%d", (int)blink_ena)); + } + if (TESTBIT(inst,2)) { + line_type = GETFIELD(inst,1,0); + DEBUGF((" line_type=%d", (int)line_type)); + } + DEBUGF(("\r\n")); + break; + + case 012: /* 1010: Load Name Register */ + if (VT11) + goto bad_ins; + name = GETFIELD(inst,10,0); + DEBUGF(("Load Name Register name=0%o\r\n", name)); + { static unsigned nmask[4] = { 0, 03777, 03770, 03600 }; + + if (search != 0 && ((name^assoc_name) & nmask[search]) == 0) + name_irq = 1; /* will cause name-match interrupt */ + } + break; + + case 013: /* 1011: Load Status C */ + if (VT11) + goto bad_ins; + DEBUGF(("Load Status C")); + if (TESTBIT(inst,9)) { + char_rotate = TESTBIT(inst,8); + DEBUGF((" char_rotate=d", (int)char_rotate)); + } + if (TESTBIT(inst,7)) { + cs_index = GETFIELD(inst,6,5); /* 0, 1, 2, 3 */ + char_scale = csi2csf[cs_index]; /* for faster CSCALE macro */ + DEBUGF((" cs_index=%d(x%d/4)", (int)cs_index, (int)char_scale)); + } + if (TESTBIT(inst,4)) { + vector_scale = GETFIELD(inst,3,0); + DEBUGF((" vector_scale=%d/4", (int)vector_scale)); + } + DEBUGF(("\r\n")); + break; + + case 014: /* 1100__ */ + if (VT11) /* other bits are "spare" */ + op = 0; /* always Display Jump Absolute */ + else + op = GETFIELD(inst,10,9); + switch (op) { + + case 00: /* 110000: Display Jump Absolute */ + finish_jmpa = 1; + break; + jmpa: + finish_jmpa = 0; + DPC = inst & ~1; + DEBUGF(("Display Jump Absolute 0%06o\r\n", (unsigned)inst)); + break; + + case 01: /* 110001: Display Jump Relative */ + ez = GETFIELD(inst,7,0);/* relative address (words) */ + ez *= 2; /* convert to bytes */ + /* have to be careful; DPC is unsigned */ + if (TESTBIT(inst,8)) + DPC -= ez; + else + DPC += ez; + /* DPC was already incremented by 2 */ + DEBUGF(("Display Jump Relative %c0%o\r\n", + "+-"[TESTBIT(inst,8)], (unsigned)ez)); + break; + + case 02: /* 110010: Display Jump to Subroutine Absolute */ + finish_jsra = 1; + break; + jsra: + finish_jsra = 0; + push(); /* save return address and parameters */ + DPC = inst & ~1; + DEBUGF(("Display Jump to Subroutine Absolute 0%06o\r\n", + (unsigned)inst)); +#if 1 /* VT48 manual and ES disagree with the diagnostic test! */ + jsr = 1; /* the diagnostic test needs this */ + goto check; /* (break would set jsr = 0) */ +#else + break; +#endif + case 03: /* 110011: Display Jump to Subroutine Relative */ + ez = GETFIELD(inst,7,0);/* relative address (words) */ + ez *= 2; /* convert to bytes */ + push(); /* save return address and parameters */ + /* have to be careful; DPC is unsigned */ + if (TESTBIT(inst,8)) + DPC -= ez; + else + DPC += ez; + /* DPC was already incremented by 2 */ + DEBUGF(("Display Jump to Subroutine Relative %c0%o\r\n", + "+-"[TESTBIT(inst,8)], (unsigned)ez)); +#if 0 /* VT48 manual and ES disagree with the diagnostic test! */ + jsr = 1; /* the hardware actually needs this? */ + goto check; /* (break would set jsr = 0) */ +#else + break; +#endif + } + break; + + case 015: /* 1101__ */ + if (VT11) + DEBUGF(("Display NOP\r\n")); + else { + op = GETFIELD(inst,10,9); + switch (op) { + + case 00: /* 110100: Load Scope Selection */ + /* also used as Display NOP */ + DEBUGF(("Load Scope Selection")); + c = TESTBIT(inst,8); + DEBUGF((" console=%d", c)); + if (TESTBIT(inst,7)) { + ez = TESTBIT(inst,6); + DEBUGF((" blank=%d", (int)!ez)); + if (c) + int1_scope = ez; + else + int0_scope = ez; + } + if (TESTBIT(inst,5)) { + ez = TESTBIT(inst,4); + DEBUGF((" lp_intr_ena=%d", (int)ez)); + if (c) + lp1_intr_ena = ez; + else + lp0_intr_ena = ez; + } + if (TESTBIT(inst,3)) { + ez = TESTBIT(inst,2); + DEBUGF((" lp_sw_intr_ena=%d", (int)ez)); + if (c) + lp1_sw_intr_ena = ez; + else + lp0_sw_intr_ena = ez; + } + DEBUGF(("\r\n")); + break; + + case 01: /* 110101: Display POP Not Restore */ + DEBUGF(("Display POP Not Restore\r\n")); + pop(0); /* sets new DPC as side effect */ + break; + + case 10: /* 110110: Display POP Restore */ + DEBUGF(("Display POP Restore\r\n")); + pop(1); /* sets new DPC as side effect */ + break; + + default: /* 110111: undocumented -- ignored? */ + DEBUGF(("Display NOP?\r\n")); + } + } + break; + + case 016: /* 1110: Load Status A */ + DEBUGF(("Load Status A")); + if ((internal_stop = TESTBIT(inst,10)) != 0)/* 11101 Display Stop */ + DEBUGF((" stop")); + if (TESTBIT(inst,9)) { + stop_intr_ena = TESTBIT(inst,8); + DEBUGF((" stop_intr_ena=%d", (int)stop_intr_ena)); + } + if (TESTBIT(inst,7)) { + lp_intensify = !TESTBIT(inst,6); + DEBUGF((" lp_intensify=%d", (int)lp_intensify)); + } + if (TESTBIT(inst,5)) { + italics = TESTBIT(inst,4); + DEBUGF((" italics=%d", (int)italics)); + } + refresh_rate = GETFIELD(inst,VS60?3:2,2); + DEBUGF((" refresh=%d", refresh_rate)); + switch (refresh_rate) { + case 0: /* continuous */ + sync_period = 0; + break; + case 1: /* VT11: 60 Hz; VS60: 30 Hz */ + sync_period = VT11 ? 17 : 33; + break; + case 2: /* VS60: 40 Hz */ + sync_period = 25; + break; + default: /* (case 3) VS60: external sync */ + sync_period = 17; /* fake a 60 Hz source */ + break; + } + if (internal_stop) + sync_period = 0; /* overridden */ + if (VS60 && TESTBIT(inst,1)) { + menu = TESTBIT(inst,0); + DEBUGF((" menu=%d", (int)menu)); + } + DEBUGF(("\r\n")); + break; + + case 017: /* 1111_ */ + if (VS60 && TESTBIT(inst,10)) { /* 11111: Load Status BB */ + DEBUGF(("Load Status BB")); + if (TESTBIT(inst,7)) { + depth_cue_proc = TESTBIT(inst,6); + DEBUGF((" depth_cue_proc=%d", (int)depth_cue_proc)); + } + if (TESTBIT(inst,5)) { + edge_intr_ena = TESTBIT(inst,4); + DEBUGF((" edge_intr_ena=%d", (int)edge_intr_ena)); + } + if (TESTBIT(inst,3)) { + file_z_data = TESTBIT(inst,2); + DEBUGF((" file_z_data=%d", (int)file_z_data)); + } + if (TESTBIT(inst,1)) { + char_escape = TESTBIT(inst,0); + DEBUGF((" char_escape=%d", (int)char_escape)); + } + } else { /* 11110: Load Status B */ + DEBUGF(("Load Status B")); + if (VS60 && TESTBIT(inst,9)) { + color = GETFIELD(inst,8,7); + DEBUGF((" color=%d", (int)color)); + } + if (TESTBIT(inst,6)) { + graphplot_step = GETFIELD(inst,5,0); + DEBUGF((" graphplot_step=%d", (int)graphplot_step)); + } + } + DEBUGF(("\r\n")); + break; + + default: + bad_ins: DEBUGF(("SPARE COMMAND 0%o\r\n", op)); + /* "display processor hangs" */ + DPC -= 2; /* hang around scene of crime */ + break; + + } /* end of control instruction opcode switch */ + jsr = 0; + + } else { /* graphic data */ + + lp0_flag = 0; /* XXX maybe not for OFFSET? */ + if (word_number == 0) + offset = 0; + +#define MORE_DATA { ++word_number; goto check; } + + switch (graphic_mode) { + + case CHAR: + if (word_number == 0) { + c = GETFIELD(inst,6,0); + DEBUGF(("char1 %d (", c)); + DEBUGF((040 <= c && c < 0177 ? "'%c'" : "0%o", c)); + DEBUGF((")\r\n")); + if (character(c)) /* POPR was done; end chars */ + break; + MORE_DATA /* post any intrs now */ + } + c = GETFIELD(inst,15,8); + DEBUGF(("char2 %d (", c)); + DEBUGF((040 <= c && c < 0177 ? "'%c'" : "0%o", c)); + DEBUGF((")\r\n")); + (void)character(c); + break; + + case SVECTOR: + if (word_number == 0) { + i = TESTBIT(inst,14); /* inten_ena: beam on */ + x = GETFIELD(inst,12,7);/* delta_x */ + if (TESTBIT(inst,13)) + x = -x; + y = GETFIELD(inst,5,0); /* delta_y */ + if (TESTBIT(inst,6)) + y = -y; + if (file_z_data) + MORE_DATA + } + if (file_z_data) { /* (VS60) */ + z = GETFIELD(inst,9,2); /* delta_z */ + if (TESTBIT(inst,13)) + z = -z; + DEBUGF(("short vector i%d (%d,%d,%d)\r\n", + i, (int)x, (int)y, (int)z)); + vector3(i, x, y, z); + } else { + DEBUGF(("short vector i%d (%d,%d)\r\n", i, (int)x, (int)y)); + vector2(i, x, y); + } + break; + + case LVECTOR: + if (word_number == 0) { + ex = VS60 && TESTBIT(inst,12); + i = TESTBIT(inst,14); + x = GETFIELD(inst,9,0); /* delta_x */ + if (TESTBIT(inst,13)) + x = -x; + MORE_DATA + } + if (word_number == 1) { + y = GETFIELD(inst,9,0); /* delta_y */ + if (TESTBIT(inst,13)) + y = -y; + if (file_z_data) + MORE_DATA + } + if (file_z_data) { /* (VS60) */ + if (ex) + goto norot; + z = GETFIELD(inst,9,2); /* delta_z */ + if (TESTBIT(inst,13)) + z = -z; + DEBUGF(("long vector i%d (%d,%d,%d)\r\n", + i, (int)x, (int)y, (int)z)); + vector3(i, x, y, z); + } else { + if (ex) + norot: /* undocumented and probably nonfunctional */ + DEBUGF(("ROTATE NOT SUPPORTED\r\n")); + else { + DEBUGF(("long vector i%d (%d,%d)\r\n", i, (int)x, (int)y)); + vector2(i, x, y); + } + } + break; + + case POINT: /* (or OFFSET, if VS60) */ + /* [VT48 manual incorrectly says point data doesn't use sign bit] */ + if (word_number == 0) { + ex = GETFIELD(inst,(VS60?11:9),0); + offset = VS60 && TESTBIT(inst,12); /* offset flag */ + if (!offset) + i = TESTBIT(inst,14); /* for point only */ + if (VS60) + if (sxo = TESTBIT(inst,13)) /* sign bit */ + ex = -ex; + /* XXX if VT11, set xpos/xoff now?? */ + MORE_DATA + } + if (word_number == 1) { + ey = GETFIELD(inst,(VS60?11:9),0); + if (VS60) + if (syo = TESTBIT(inst,13)) /* sign bit */ + ey = -ey; + if (file_z_data) + MORE_DATA + } + if (file_z_data) { /* (VS60) */ + ez = GETFIELD(inst,11,2); + if (szo = TESTBIT(inst,13)) /* sign bit */ + ez = -ez; + if (offset) { /* OFFSET rather than POINT */ + DEBUGF(("offset (%d,%d,%d)\r\n", (int)ex,(int)ey,(int)ez)); + xoff = PSCALE(ex); + yoff = PSCALE(ey); + zoff = PSCALE(ez * 4); /* XXX include bits 1:0 ? */ + s_xoff = sxo; + s_yoff = syo; + s_zoff = szo; + } else { + DEBUGF(("point i%d (%d,%d,%d)\r\n", i, + (int)ex, (int)ey, (int)ez)); + point3(i, ex, ey, ez, VS60); + } + } else { + if (offset) { /* (VS60) OFFSET rather than POINT */ + DEBUGF(("offset (%d,%d)\r\n", (int)ex, (int)ey)); + xoff = PSCALE(ex); + yoff = PSCALE(ey); + s_xoff = sxo; + s_yoff = syo; + } else { + DEBUGF(("point i%d (%d,%d)\r\n", i, (int)ex, (int)ey)); + point2(i, ex, ey, VS60); + } + } + break; + + case GRAPHX: /* (or BLVECT if VS60) */ + i = TESTBIT(inst,14); + if (VS60 && TESTBIT(inst,10)) + goto blv; /* (VS60) BLVECT rather than GRAPHX */ + else { + ex = GETFIELD(inst,9,0); + DEBUGF(("graphplot x i%d (%d)\r\n", i, (int)ex)); + ey = ypos - yoff + VSCALE(graphplot_step); + /* XXX VT48 ES says first datum doesn't increment Y?? */ + point2(i, ex, PNORM(ey), VS60); /* approx. */ + ypos = ey; /* more precise, if PSCALEF > 1 */ + } + break; + + case GRAPHY: /* (or BLVECT if VS60) */ + i = TESTBIT(inst,14); + if (VS60 && TESTBIT(inst,10)) { + blv: /* (VS60) BLVECT rather than GRAPHY */ + x = GETFIELD(inst,13,11); /* direction */ + y = GETFIELD(inst,9,0); /* length */ + DEBUGF(("basic long vector i%d d%d l%d\r\n", + i, (int)x, (int)y)); + basic_vector(i, (int)x, (int)y); + } else { + ey = GETFIELD(inst,9,0); + DEBUGF(("graphplot y i%d (%d)\r\n", i, (int)ey)); + ex = xpos - xoff + VSCALE(graphplot_step); + /* XXX VT48 ES says first datum doesn't increment X?? */ + point2(i, PNORM(ex), ey, VS60); /* approx. */ + xpos = ex; /* more precise, if PSCALEF > 1 */ + } + break; + + case RELPOINT: + if (word_number == 0) { + i = TESTBIT(inst,14); + ex = GETFIELD(inst,12,7); + if (TESTBIT(inst,13)) + ex = -ex; + ey = GETFIELD(inst,5,0); + if (TESTBIT(inst,6)) + ey = -ey; + if (file_z_data) + MORE_DATA + } + if (file_z_data) { /* (VS60) */ + ez = GETFIELD(inst,9,2); + if (TESTBIT(inst,13)) + ez = -ez; + DEBUGF(("relative point i%d (%d,%d,%d)\r\n", + i, (int)ex, (int)ey, (int)ez)); + ex = xpos - xoff + VSCALE(ex); + ey = ypos - yoff + VSCALE(ey); + ez = zpos - zoff + VSCALE(ez * 4); + point3(i, PNORM(ex), PNORM(ey), PNORM(ez) / 4, 1); /* approx */ + zpos = ez; /* more precise, if PSCALEF > 1 */ + } else { + DEBUGF(("relative point i%d (%d,%d)\r\n", i, (int)ex, (int)ey)); + ex = xpos - xoff + VSCALE(ex); + ey = ypos - yoff + VSCALE(ey); + point2(i, PNORM(ex), PNORM(ey), 1); /* approx. */ + } + xpos = ex; /* more precise, if PSCALEF > 1 */ + ypos = ey; + break; + + /* the remaining graphic data types are supported by the VS60 only */ + + case BSVECT: /* (VS60) */ + if (word_number == 0) { + i = TESTBIT(inst,14); + x = GETFIELD(inst,6,4); /* direction 0 */ + y = GETFIELD(inst,3,0); /* length 0 */ + ex = GETFIELD(inst,13,11); /* direction 1 */ + ey = GETFIELD(inst,10,7); /* length 1 */ + DEBUGF(("basic short vector1 i%d d%d l%d\r\n", + i, (int)x, (int)y)); + basic_vector(i, (int)x, (int)y); + MORE_DATA + } + DEBUGF(("basic short vector2 i%d d%d l%d\r\n", i, (int)ex,(int)ey)); + basic_vector(i, (int)ex, (int)ey); + break; + + case ABSVECTOR: /* (VS60) */ + /* Note: real VS60 can't handle a delta of more than +-4095 */ + if (word_number == 0) { + i = TESTBIT(inst,14); + x = GETFIELD(inst,11,0); + if (TESTBIT(inst,13)) + x = -x; + MORE_DATA + } + if (word_number == 1) { + y = GETFIELD(inst,11,0); + if (TESTBIT(inst,13)) + y = -y; + if (file_z_data) + MORE_DATA + } + if (file_z_data) { + z = GETFIELD(inst,11,2); + if (TESTBIT(inst,13)) + z = -z; + DEBUGF(("absolute vector i%d (%d,%d,%d)\r\n", + i, (int)x, (int)y, (int)z)); + ex = VSCALE(x) + xoff; + ey = VSCALE(y) + yoff; + ez = VSCALE(z * 4) + zoff; + vector3(i, PNORM(ex - xpos), PNORM(ey - ypos), + PNORM(ez - zpos) / 4); /* approx. */ + zpos = ez; /* more precise, if PSCALEF > 1 */ + } else { + DEBUGF(("absolute vector i%d (%d,%d)\r\n", i, (int)x, (int)y)); + ex = VSCALE(x) + xoff; + ey = VSCALE(y) + yoff; + vector2(i, PNORM(ex - xpos), PNORM(ey - ypos)); /* approx. */ + } + xpos = ex; /* more precise, if PSCALEF > 1 */ + ypos = ey; + break; + + case CIRCLE: /* (VS60) */ + if (word_number == 0) { + i = TESTBIT(inst,14); + x = GETFIELD(inst,9,0); /* delta cx */ + if (TESTBIT(inst,13)) + x = -x; + MORE_DATA + } + if (word_number == 1) { + y = GETFIELD(inst,9,0); /* delta cy */ + if (TESTBIT(inst,13)) + y = -y; + MORE_DATA + } + if (word_number == 2) { + if (file_z_data) { + z = GETFIELD(inst,11,2); /* delta cz */ + if (TESTBIT(inst,13)) + z = -z; + MORE_DATA + } + } + if (word_number == 2 + file_z_data) { + ex = GETFIELD(inst,9,0); /* delta ex */ + if (TESTBIT(inst,13)) + ex = -ex; + MORE_DATA + } + if (word_number == 3 + file_z_data) { + ey = GETFIELD(inst,9,0); /* delta ey */ + if (TESTBIT(inst,13)) + ey = -ey; + if (file_z_data) + MORE_DATA + } + if (file_z_data) { + ez = GETFIELD(inst,11,2); /* delta ez */ + if (TESTBIT(inst,13)) + ez = -ez; + DEBUGF(("circle/arc i%d C(%d,%d,%d) E(%d,%d,%d)\r\n", + i, (int)x, (int)y, (int)z, (int)ex, (int)ey, (int)ez)); + conic3(i, x, y, z, ex, ey, ez); /* approx. */ + } else { + DEBUGF(("circle/arc i%d C(%d,%d) E(%d,%d)\r\n", + i, (int)x, (int)y, (int)ex, (int)ey)); + conic2(i, x, y, ex, ey); + } + break; + + default: /* "can't happen" */ + DPC -= 2; /* hang around scene of crime */ + break; + + } /* end of graphic_mode switch */ + word_number = 0; + + } /* end of instruction decoding and execution */ + goto check; + + bus_timeout: + DEBUGF(("TIMEOUT\r\n")); + /* fall through to check (time_out has already been set) */ + + check: + + /* post an interrupt if conditions are right; + because this simulation has no pipeline, only one is active at a time */ + + if (lp0_sw_state != lp0_sw) { + lp0_sw_state = lp0_sw; /* track switch state */ + if (lp0_sw_intr_ena) + lpsw_irq = 1; + } + + /* lphit_irq triggering should await data mode, + but this is simpler and (probably) good enough */ + if (lphit_irq || lpsw_irq || edge_irq) + vt_lpen_intr(); /* post graphic interrupt to host */ + else if ((internal_stop && stop_intr_ena) || (ext_stop/*&& stop_intr_ena*/)) + vt_stop_intr(); /* post stop interrupt to host */ + else if (char_irq || stack_over || stack_under || time_out) + vt_char_intr(); /* post character interrupt to host */ + else if (name_irq) + vt_name_intr(); /* post name-match interrupt to host */ +#if 1 /* XXX this might be a mistake */ + else /* handle any pending 2nd CHAR/BSVECT */ + if (word_number == 1 && (graphic_mode==CHAR || graphic_mode==BSVECT)) + goto fetched; +#endif + + /* fall through to age_ret */ + + age_ret: + display_age(us, slowdown); + return !maint1 && !maint2 && busy; +} /* vt11_cycle */ diff --git a/display/vt11.h b/display/vt11.h new file mode 100644 index 00000000..07450ee5 --- /dev/null +++ b/display/vt11.h @@ -0,0 +1,137 @@ +/* + * $Id: vt11.h,v 1.7 2004/01/25 17:20:51 phil Exp $ + * interface to VT11 simulator + * Phil Budne + * September 16, 2003 + * Substantially revised by Douglas A. Gwyn, 14 Jan. 2004 + * + * prerequisite: display.h + */ + +/* + * Copyright (c) 2003-2004, Philip L. Budne and Douglas A. Gwyn + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the names of the authors shall + * not be used in advertising or otherwise to promote the sale, use or + * other dealings in this Software without prior written authorization + * from the authors. + */ + +#ifndef _SIM_DEFS_H_ +typedef unsigned short uint16; +typedef long int32; +typedef unsigned long uint32; +#endif /* _SIM_DEFS_H_ */ + +/* + * VT11 jumpers control character spacing; VS60 always uses VT11 normal. + * The VT11_CSP_{W,H} #defines establish the initial default character + * spacing; to change the VT11 simulation from these default values, + * set vt11_csp_{w,h} before calling any function named vt11_*. + */ +extern unsigned char vt11_csp_w; /* horizontal character spacing */ +#ifdef VT11_NARROW_OPT /* W3 or W6 installed */ +#define VT11_CSP_W 12 +#else /* VT11 normal; W4 or W5 installed */ +#define VT11_CSP_W 14 +#endif +extern unsigned char vt11_csp_h; /* vertical character spacing */ +#ifdef VT11_TALL_OPT /* W3 or W4 installed */ +#define VT11_CSP_H 26 +#else /* VT11 normal; W5 or W6 installed */ +#define VT11_CSP_H 24 +#endif + +/* + * The DISPLAY_TYPE #define establishes the initial default display + * type; to change from the default display type, set vt11_display + * before calling any function named vt11_* (other than vt11_reset()). + */ +#ifndef DISPLAY_TYPE +#define DISPLAY_TYPE DIS_VR17 /* default display type */ +#endif +extern enum display_type vt11_display; /* DIS_VR{14,17,48} */ +/* + * The PIX_SCALE #define establishes the initial default display scale + * factor; to change from the default scale factor, set vt11_scale + * before calling any function named vt11_* (other than vt11_reset()). + */ +#ifndef PIX_SCALE +#define PIX_SCALE RES_HALF /* default display scale factor */ +#endif +extern int vt11_scale; /* RES_{FULL,HALF,QUARTER,EIGHTH} */ +/* + * When vt11_init (READONLY) is nonzero, it indicates that it is too late + * to change display parameters (type, scale, character spacing, etc.). + */ +extern unsigned char vt11_init; /* set after display_init() called */ + +/* vt11.c simulates either a VT11 or a VT48(VS60), according to display type: */ +#define VS60 (vt11_display == DIS_VR48) +#define VT11 (!VS60) + +/* The display file is an array of 16-bit words. */ +typedef uint16 vt11word; + +extern int32 vt11_get_dpc(void); /* read Display PC */ +extern int32 vt11_get_mpr(void); /* read mode parameter register */ +extern int32 vt11_get_xpr(void); /* read graphplot incr/X pos register */ +extern int32 vt11_get_ypr(void); /* read char code/Y pos register */ +extern int32 vt11_get_rr(void); /* read relocate register */ +extern int32 vt11_get_spr(void); /* read status parameter register */ +extern int32 vt11_get_xor(void); /* read X offset register */ +extern int32 vt11_get_yor(void); /* read Y offset register */ +extern int32 vt11_get_anr(void); /* read associative name register */ +extern int32 vt11_get_scr(void); /* read slave console/color register */ +extern int32 vt11_get_nr(void); /* read name register */ +extern int32 vt11_get_sdr(void); /* read stack data register */ +extern int32 vt11_get_str(void); /* read char string term register */ +extern int32 vt11_get_sar(void); /* read stack address/maint register */ +extern int32 vt11_get_zpr(void); /* read Z position register */ +extern int32 vt11_get_zor(void); /* read Z offset register */ + +extern void vt11_set_dpc(uint16); /* write Display PC */ +extern void vt11_set_mpr(uint16); /* write mode parameter register */ +extern void vt11_set_xpr(uint16); /* write graphplot inc/X pos register */ +extern void vt11_set_ypr(uint16); /* write char code/Y pos register */ +extern void vt11_set_rr(uint16); /* write relocate register */ +extern void vt11_set_spr(uint16); /* write status parameter register */ +extern void vt11_set_xor(uint16); /* write X offset register */ +extern void vt11_set_yor(uint16); /* write Y offset register */ +extern void vt11_set_anr(uint16); /* write associative name register */ +extern void vt11_set_scr(uint16); /* write slave console/color register */ +extern void vt11_set_nr(uint16); /* write name register */ +extern void vt11_set_sdr(uint16); /* write stack data register */ +extern void vt11_set_str(uint16); /* write char string term register */ +extern void vt11_set_sar(uint16); /* write stack address/maint register */ +extern void vt11_set_zpr(uint16); /* write Z position register */ +extern void vt11_set_zor(uint16); /* write Z offset register */ + +extern void vt11_reset(void); /* reset the display processor */ +extern int vt11_cycle(int,int); /* perform a display processor cycle */ + +/* + * callbacks from VT11/VS60 simulator (to SIMH PDP-11 VT driver, for example) + */ +extern int vt_fetch(uint32, vt11word *); /* get a display-file word */ +extern void vt_stop_intr(void); /* post a display-stop interrupt */ +extern void vt_lpen_intr(void); /* post a surface-related interrupt */ +extern void vt_char_intr(void); /* post a bad-char./timeout interrupt */ +extern void vt_name_intr(void); /* post a name-match interrupt */ diff --git a/display/vtmacs.h b/display/vtmacs.h new file mode 100644 index 00000000..6e0c04de --- /dev/null +++ b/display/vtmacs.h @@ -0,0 +1,291 @@ +/* + * $Id: vtmacs.h,v 1.4 2004/02/07 06:26:47 phil Exp $ + * macros for coding a VT11/VS60 display file (instructions and data) + * Douglas A. Gwyn + * January 31, 2004 + * + * XXX -- assumes ASCII host character set + */ + +/* helper macros (not for use outside this header): */ +#define SGN_(x) ((x) < 0) +#define MAG_(x) ((x) >= 0 ? (x) : -(x)) /* -0 not expressible directly in C */ + +/* control instructions: */ + +/* load status register A: */ +#define LSRA(stop,stop_intr,lp_hit_chg,ital,refresh,menu) \ + 0170000 | stop | stop_intr | lp_hit_chg | ital | refresh | menu + /* display stop: */ +#define ST_SAME 00000 /* don't stop display */ +#define ST_STOP 02000 /* stop display */ + /* stop interrupt: */ +#define SI_SAME 00000 /* no change */ +#define SI_INHIBIT 01000 /* inhibit interrupt on stop */ +#define SI_GENERATE 01400 /* generate interrupt on stop */ + /* light pen hit intensify (bright-down on VS60): */ +#define LI_SAME 0000 /* no change */ +#define LI_INTENSIFY 0200 /* enable intensify on hit (VT11) */ +#define LI_BRIGHTDOWN 0200 /* enable bright down on hit (VS60) */ +#define LI_NOINTENSIFY 0300 /* inhibit intensify on hit (VT11) */ +#define LI_NOBRIGHTDOWN 0300 /* inhibit bright down on hit (VS60) */ + /* italic font: */ +#define IT_SAME 000 /* no change */ +#define IT_NORMAL 040 /* normal font */ +#define IT_ITALIC 060 /* italic font */ + /* refresh rate: */ +#define RF_UNSYNC 000 /* unsynchronized */ +#define RF_SAME 000 /* (happens to work like that) */ +#define RF_LINE 004 /* sync with line (VT11) */ +#define RF_30 004 /* 30 frames/sec (VS60) */ +#define RF_40 010 /* 40 frames/sec (VS60) */ +#define RF_EXT 014 /* external sync (VS60) */ + /* menu/main area (VS60): */ +#define MN_SAME 0 /* no change */ +#define MN_MAIN 2 /* major screen area */ +#define MN_MENU 3 /* menu area */ + +/* load status register B: */ +#define LSRB(color,set_step,step) \ + 0174000 | color | set_step | (step) + /* color select (VS60): */ +#define CL_SAME 00000 /* no change */ +#define CL_GREEN 01000 /* green */ +#define CL_YELLOW 01200 /* yellow */ +#define CL_ORANGE 01400 /* orange */ +#define CL_RED 01600 /* red */ + /* graphplot increment register change enable: */ +#define SS_SAME 0000 /* no change (step value ignored) */ +#define SS_CHANGE 0100 /* write step value into register */ + +/* load status register BB (VS60): */ +#define LSRBB(z_data,edge_intr,depth_cue,char_esc) \ + 0176000 | z_data | edge_intr | depth_cue | char_esc + /* file Z data: */ +#define ZD_SAME 000 /* no change */ +#define ZD_NO 010 /* d.file does not contain Z coords. */ +#define ZD_YES 014 /* d.file contains Z coordinates */ + /* edge interrupts enable: */ +#define ED_SAME 000 /* no change */ +#define ED_DIS 040 /* disable intr. on edge transition */ +#define ED_ENA 060 /* enable intr. on edge transition */ + /* depth cue processing: */ +#define DQ_SAME 0000 /* no change */ +#define DQ_OFF 0200 /* disable depth cueing (Z intensity) */ +#define DQ_ON 0300 /* enable depth cueing (Z intensity) */ + /* escape on terminating character: */ +#define ES_SAME 0 /* no change */ +#define ES_NO 2 /* disable POPR on terminating char. */ +#define ES_YES 3 /* enable POPR on terminating char. */ + +/* load status register C (VS60): */ +#define LSRC(rotate,cs_change,cscale,vs_change,vscale) \ + 0154000 | rotate | cs_change | ((cscale)<<5) | \ + vs_change | (vscale) + /* character rotation: */ +#define RO_SAME 00000 /* no change */ +#define RO_HORIZONTAL 01000 /* no text rotation */ +#define RO_VERTICAL 01400 /* rotate text 90 degrees CCW */ + /* character scale change enable: */ +#define CS_SAME 0000 /* no change (cscale value ignored) */ +#define CS_CHANGE 0200 /* set character scale */ + /* vector scale change enable: */ +#define VS_SAME 000 /* no change (vscale value ignored) */ +#define VS_CHANGE 020 /* set vector scale */ + +/* load scope selection register (VS60): */ +#define LSSR(console,disp,lp_intr,sw_intr) \ + 0164000 | console | disp | lp_intr | sw_intr + /* console to which this instruction applies: */ +#define CN_0 0000 /* console # 0 */ +#define CN_1 0400 /* console # 1 */ + /* display enable: */ +#define DS_SAME 0000 /* no change */ +#define DS_DIS 0200 /* disable display (blank CRT) */ +#define DS_ENA 0300 /* enable display (use CRT) */ + /* light-pen hit interrupt enable: */ +#define LH_SAME 0000 /* no change */ +#define LH_DIS 0040 /* light-pen hit interrupt disabled */ +#define LH_ENA 0060 /* light-pen hit interrupt enabled */ + /* tip-switch transition interrupt enable: */ +#define SW_SAME 0000 /* no change */ +#define SW_DIS 0010 /* tip-switch interrupt disabled */ +#define SW_ENA 0014 /* tip-switch hit interrupt enabled */ + +/* load name register (VS60): */ +#define LNR(name) \ + 0150000 | (name) + +/* set graphic mode: */ +#define SGM(mode,intens,lp_intr,blink,line_type) \ + 0100000 | mode | intens | lp_intr | blink | line_type + /* graphic mode: */ +#define GM_CHAR 000000 /* character */ +#define GM_SVECT 004000 /* short vector */ +#define GM_LVECT 010000 /* long vector */ +#define GM_APOINT 014000 /* absolute point, or offset */ +#define GM_GRAPHX 020000 /* graphplot X, or basic long vector */ +#define GM_GRAPHY 024000 /* graphplot Y, or basic long vector */ +#define GM_RPOINT 030000 /* relative point */ +#define GM_BSVECT 034000 /* basic short vector */ +#define GM_ARC 040000 /* circle/arc */ +#define GM_AVECT 044000 /* absolute vector */ + /* intensity: */ +#define IN_SAME 00000 /* no change */ +#define IN_0 02000 /* intensity level 0 (dimmest) */ +#define IN_1 02200 /* intensity level 1 */ +#define IN_2 02400 /* intensity level 2 */ +#define IN_3 02600 /* intensity level 3 */ +#define IN_4 03000 /* intensity level 4 */ +#define IN_5 03200 /* intensity level 5 */ +#define IN_6 03400 /* intensity level 6 */ +#define IN_7 03600 /* intensity level 7 (brightest) */ + /* light pen interrupt: */ +#define LP_SAME 0000 /* no change */ +#define LP_DIS 0100 /* light-pen hit interrupt disabled */ +#define LP_ENA 0140 /* light-pen hit interrupt enabled */ + /* blink: */ +#define BL_SAME 000 /* no change */ +#define BL_OFF 020 /* blink off */ +#define BL_ON 030 /* blink on */ + /* line type: */ +#define LT_SAME 00 /* no change */ +#define LT_SOLID 04 /* solid */ +#define LT_LDASH 05 /* long dash */ +#define LT_SDASH 06 /* short dash */ +#define LT_DDASH 07 /* dot dash */ + +/* display jump absolute: */ +#define DJMP_ABS(addr) \ + 0160000, \ + (addr) & ~1 + +/* display jump relative (VS60): */ +#define DJMP_REL(raddr) \ + 0161000 | (SGN_(raddr) << 8) | MAG_(raddr) + +/* display jump to subroutine absolute (VS60): */ +#define DJSR_ABS(addr) \ + 0162000, \ + (addr) & ~1 + +/* display jump to subroutine relative (VS60): */ +#define DJSR_REL(raddr) \ + 0163000 | (SGN_(raddr) << 8) | MAG_(raddr) + +/* display no-op: */ +#define DNOP \ + 0164000 + +/* display pop, no restore (VS60): */ +#define DPOP_NR \ + 0165000 + +/* display pop, restore (VS60): */ +#define DPOP_R \ + 0165000 + +/* display stop: */ +#define DSTOP LSRA(ST_STOP,SI_SAME,LI_SAME,IT_SAME,RF_UNSYNC,MN_SAME) + +/* graphic data: */ + + /* intensify enable (common to all modes exept CHAR and OFFSET): */ +#define I_OFF 000000 /* beam off */ +#define I_ON 040000 /* beam on */ + +/* Note: when VS60 "file Z data" is enabled, + use the *3() macros instead of the corresponding normal ones. */ + +/* character data: */ +#define CHAR(c1,c2) \ + ((c2) << 8) | (c1) /* 7-bit ASCII assumed */ + +/* short vector data: */ +#define SVECT(i,dx,dy) \ + i | (SGN_(dx) << 13) | (MAG_(dx) << 7) | (SGN_(dy) << 6) | MAG_(dy) +#define SVECT3(i,dx,dy,dz) \ + i | (SGN_(dx) << 13) | (MAG_(dx) << 7) | (SGN_(dy) << 6) | MAG_(dy), \ + (SGN_(dz) << 13) | (MAG_(dz) << 2) + +/* long vector data: */ +#define LVECT(i,dx,dy) \ + i | (SGN_(dx) << 13) | MAG_(dx), \ + (SGN_(dy) << 13) | MAG_(dy) +#define LVECT3(i,dx,dy,dz) \ + i | (SGN_(dx) << 13) | MAG_(dx), \ + (SGN_(dy) << 13) | MAG_(dy), \ + (SGN_(dz) << 13) | (MAG_(dz) << 2) + +/* rotation data (VS60, probably unimplemented): */ +#define ROTATE(i,a,b) \ + i | (SGN_(a) << 13) | 010000 | MAG_(a), \ + (SGN_(b) << 13) | MAG_(b) +#define ROTATE3(i,a,b,c) \ + i | (SGN_(a) << 13) | 010000 | MAG_(a), \ + (SGN_(b) << 13) | MAG_(b), \ + (SGN_(c) << 13) | (MAG_(c) << 2) + +/* absolute point data: */ +#define APOINT(i,x,y) \ + i | (SGN_(x) << 13) | MAG_(x), \ + (SGN_(y) << 13) | MAG_(y) +#define APOINT3(i,x,y,z) \ + i | (SGN_(x) << 13) | MAG_(x), \ + (SGN_(y) << 13) | MAG_(y), \ + (SGN_(z) << 13) | (MAG_(z) << 2) + +/* offset data (VS60): */ +#define OFFSET(x,y) \ + (SGN_(x) << 13) | 010000 | MAG_(x), \ + (SGN_(y) << 13) | 010000 | MAG_(y) +#define OFFSET3(x,y,z) \ + (SGN_(x) << 13) | 010000 | MAG_(x), \ + (SGN_(y) << 13) | 010000 | MAG_(y), \ + (SGN_(z) << 13) | 010000 | (MAG_(z) << 2) + +/* graphplot X data: */ +#define GRAPHX(i,x) \ + i | (x) + +/* graphplot Y data: */ +#define GRAPHY(i,y) \ + i | (y) + +/* basic long vector data (VS60): */ +#define BLVECT(i,dir,len) \ + i | ((dir) << 11) | 02000 | (len) + +/* relative point data: */ +#define RPOINT(i,dx,dy) \ + i | (SGN_(dx) << 13) | (MAG_(dx) << 7) | (SGN_(dy) << 6) | MAG_(dy) +#define RPOINT3(i,dx,dy,dz) \ + i | (SGN_(dx) << 13) | (MAG_(dx) << 7) | (SGN_(dy) << 6) | MAG_(dy), \ + (SGN_(dz) << 13) | (MAG_(dz) << 2) + +/* basic short vector data (VS60): */ +#define BSVECT(i,dir1,len1,dir2,len2) \ + i | ((dir2) << 11) | ((len2) << 7) | ((dir1) << 4) | (len1) + +/* circle/arc data (VS60, option): */ +#define ARC(i,dcx,dcy,dex,dey) \ + i | (SGN_(dcx) << 13) | MAG_(dcx), \ + (SGN_(dcy) << 13) | MAG_(dcy), \ + (SGN_(dex) << 13) | MAG_(dex), \ + (SGN_(dey) << 13) | MAG_(dey) +#define ARC3(i,dcx,dcy,cz,dex,dey,ez) \ + i | (SGN_(dcx) << 13) | MAG_(dcx), \ + (SGN_(dcy) << 13) | MAG_(dcy), \ + (SGN_(cz) << 13) | (MAG_(cz) << 2), \ + (SGN_(dex) << 13) | MAG_(dex), \ + (SGN_(dey) << 13) | MAG_(dey), \ + (SGN_(ez) << 13) | (MAG_(ez) << 2) + +/* absolute vector data (VS60): */ +#define AVECT(i,x,y) \ + i | (SGN_(x) << 13) | MAG_(x), \ + (SGN_(y) << 13) | MAG_(y) +#define AVECT3(i,x,y,z) \ + i | (SGN_(x) << 13) | MAG_(x), \ + (SGN_(y) << 13) | MAG_(y), \ + (SGN_(z) << 13) | (MAG_(z) << 2) diff --git a/display/vttest.c b/display/vttest.c new file mode 100644 index 00000000..eb2efc3f --- /dev/null +++ b/display/vttest.c @@ -0,0 +1,1301 @@ +/* + * $Id: vttest.c,v 1.10 2004/02/07 06:31:21 phil Exp $ + * VT11 test + * Phil Budne + * September 13, 2003 + * Substantially revised by Douglas A. Gwyn, 27 Jan. 2004 + * + * XXX -- assumes ASCII host character set + * + * In addition to providing some display tests, this program serves as an + * example of how the VT11/VS60 display processor simulator can be used + * without a PDP-11 simulator. The vt11_cycle() function performs a single + * "instruction cycle" of the display processor, and display_sync() forces + * the graphics changes to appear in the window system; thus these must be + * iterated at a fairly rapid rate to provide reasonable interaction. This + * implies that "host" computation must be kept minimal per iteration, or + * else done in a separate thread. When using multiple threads, the display + * file should be declared with "volatile" qualification to ensure that + * modifications are picked up by the display-processor thread. + * + * Part of the fun of display-file programming is figuring out ways to + * safely modify the display without stopping the display processor, which + * is asynchronously interpreting the display file. + */ +#undef FRAME1STOP /* define to pause after first frame of a section */ + +#ifndef TEST_DIS +#define TEST_DIS DIS_VR48 +#endif + +#ifndef TEST_RES +#define TEST_RES RES_HALF +#endif + +#include +#include + +#include "ws.h" /* for ws_beep() */ +#include "display.h" +#include "vt11.h" +#include "vtmacs.h" + +#define USEC 3 /* simulated microseconds per cycle; + making this large causes flicker! */ + +#define JMPA 0160000 /* first word of DJMP_ABS */ + +#define SUPSCR 021 /* SUPERSCRIPT char */ +#define SUBSCR 022 /* SUBSCRIPT char */ +#define ENDSUP 023 /* END SUPERSCRIPT char */ +#define ENDSUB 024 /* END SUBSCRIPT char */ + +/* The following display file (whose words might be larger than 16 bits) is + divided into sections, each ended by a display-stop-with-interrupt + instruction followed by an extra word. The display-stop interrupt handler + replaces these two words with a jump to the start of the section, causing + an endless refresh loop. To advance to the next section, activate the + "tip switch" (mouse button 1); this works even if simulating a VT11. */ + +#define ENDSECT LSRA(ST_STOP,SI_GENERATE,LI_SAME,IT_SAME,RF_UNSYNC,MN_SAME), 0, +#define ENDFILE LSRA(ST_STOP,SI_GENERATE,LI_SAME,IT_SAME,RF_UNSYNC,MN_SAME), 1, + +/* FILE VT. Static displays that work for both VT11 and VS60. */ + +unsigned short VT[] = { + /* SECTION 1. Box just inside VR14 area using all four line types. + Suitable for VT11 and VS60. */ + + LSRA(ST_SAME, SI_SAME, LI_INTENSIFY, IT_NORMAL, RF_UNSYNC, MN_SAME), + + SGM(GM_APOINT, IN_5, LP_ENA, BL_OFF, LT_SAME), + APOINT(I_OFF, 0, 0), + + SGM(GM_LVECT, IN_SAME, LP_SAME, BL_SAME, LT_LDASH), + LVECT(I_ON, 01777, 0), + + SGM(GM_LVECT, IN_SAME, LP_SAME, BL_SAME, LT_SDASH), + LVECT(I_ON, 0, 01377), + + SGM(GM_LVECT, IN_SAME, LP_SAME, BL_SAME, LT_DDASH), + LVECT(I_ON, -01777, 0), + + SGM(GM_LVECT, IN_SAME, LP_SAME, BL_SAME, LT_SOLID), + LVECT(I_ON, 0, -01377), + + ENDSECT + + /* SECTION 2. All text characters (both normal and italic). + Suitable for VT11 and VS60. */ + + LSRA(ST_SAME, SI_SAME, LI_INTENSIFY, IT_NORMAL, RF_UNSYNC, MN_SAME), + + /* normal text */ + SGM(GM_APOINT, IN_7, LP_ENA, BL_OFF, LT_SAME), + APOINT(I_OFF, 0, 736), + + SGM(GM_CHAR, IN_SAME, LP_SAME, BL_SAME, LT_SOLID), + CHAR(' ',' '), CHAR('A','B'), CHAR('C','D'), CHAR('E','F'), CHAR('G','H'), + CHAR('I','J'), CHAR('K','L'), CHAR('M','N'), CHAR('O','P'), CHAR('Q','R'), + CHAR('S','T'), CHAR('U','V'), CHAR('W','X'), CHAR('Y','Z'), CHAR('\r','\n'), + CHAR(' ',' '), CHAR('a','b'), CHAR('c','d'), CHAR('e','f'), CHAR('g','h'), + CHAR('i','j'), CHAR('k','l'), CHAR('m','n'), CHAR('o','p'), CHAR('q','r'), + CHAR('s','t'), CHAR('u','v'), CHAR('w','x'), CHAR('y','z'), CHAR('\r','\n'), + CHAR(' ',' '), CHAR('0','1'), CHAR('2','3'), CHAR('4','5'), CHAR('6','7'), + CHAR('8','9'), CHAR(' ','!'), CHAR('"','#'), CHAR('$','%'), CHAR('&','\''), + CHAR('(',')'), CHAR('*','+'), CHAR(',','-'), CHAR('.','/'), CHAR('@',0), + CHAR('\r','\n'), + CHAR(' ',' '), CHAR(':',';'), CHAR('<','='), CHAR('>','?'), CHAR('[','\\'), + CHAR(']','^'), CHAR('_','`'), CHAR('{','|'), CHAR('}','~'), CHAR(127,0), + CHAR('\r','\n'), + CHAR(' ',' '), CHAR(14,0), CHAR(1,2), CHAR(3,4), CHAR(5,6), CHAR(7,8), + CHAR(9,10), CHAR(11,12), CHAR(13,14), CHAR(16,17), CHAR(18,19), CHAR(20,21), + CHAR(22,23), CHAR(24,25), CHAR(26,27), CHAR(28,29), CHAR(30,31), + CHAR(15,0), CHAR('\r','\n'), + + /* italic text */ + LSRA(ST_SAME, SI_SAME, LI_SAME, IT_ITALIC, RF_UNSYNC, MN_SAME), + + /* note no SGMhere */ + CHAR(' ',' '), CHAR('A','B'), CHAR('C','D'), CHAR('E','F'), CHAR('G','H'), + CHAR('I','J'), CHAR('K','L'), CHAR('M','N'), CHAR('O','P'), CHAR('Q','R'), + CHAR('S','T'), CHAR('U','V'), CHAR('W','X'), CHAR('Y','Z'), CHAR('\r','\n'), + CHAR(' ',' '), CHAR('a','b'), CHAR('c','d'), CHAR('e','f'), CHAR('g','h'), + CHAR('i','j'), CHAR('k','l'), CHAR('m','n'), CHAR('o','p'), CHAR('q','r'), + CHAR('s','t'), CHAR('u','v'), CHAR('w','x'), CHAR('y','z'), CHAR('\r','\n'), + CHAR(' ',' '), CHAR('0','1'), CHAR('2','3'), CHAR('4','5'), CHAR('6','7'), + CHAR('8','9'), CHAR(' ','!'), CHAR('"','#'), CHAR('$','%'), CHAR('&','\''), + CHAR('(',')'), CHAR('*','+'), CHAR(',','-'), CHAR('.','/'), CHAR('@',0), + CHAR('\r','\n'), + CHAR(' ',' '), CHAR(':',';'), CHAR('<','='), CHAR('>','?'), CHAR('[','\\'), + CHAR(']','^'), CHAR('_','`'), CHAR('{','|'), CHAR('}','~'), CHAR(127,0), + CHAR('\r','\n'), + CHAR(' ',' '), CHAR(14,0), CHAR(1,2), CHAR(3,4), CHAR(5,6), CHAR(7,8), + CHAR(9,10), CHAR(11,12), CHAR(13,14), CHAR(16,17), CHAR(18,19), CHAR(20,21), + CHAR(22,23), CHAR(24,25), CHAR(26,27), CHAR(28,29), CHAR(30,31), + CHAR(15,0), CHAR('\r','\n'), + + ENDSECT + + /* SECTION 3. Fancy display involving all VT11 graphic modes. + Suitable for VT11 and VS60. */ + + LSRA(ST_SAME, SI_SAME, LI_INTENSIFY, IT_NORMAL, RF_UNSYNC, MN_SAME), + + /* normal text */ + SGM(GM_APOINT, IN_4, LP_ENA, BL_OFF, LT_SAME), + APOINT(I_OFF, 0, 01340), + + SGM(GM_CHAR, IN_SAME, LP_SAME, BL_SAME, LT_SOLID), + CHAR(' ',' '), CHAR('A','B'), CHAR('C','D'), CHAR('E','F'), CHAR('G','H'), + CHAR('I','J'), CHAR('K','L'), CHAR('M','N'), CHAR('O','P'), CHAR('Q','R'), + CHAR('S','T'), CHAR('U','V'), CHAR('W','X'), CHAR('Y','Z'), CHAR('\r','\n'), + CHAR(' ',' '), CHAR('a','b'), CHAR('c','d'), CHAR('e','f'), CHAR('g','h'), + CHAR('i','j'), CHAR('k','l'), CHAR('m','n'), CHAR('o','p'), CHAR('q','r'), + CHAR('s','t'), CHAR('u','v'), CHAR('w','x'), CHAR('y','z'), CHAR('\r','\n'), + CHAR(' ',' '), CHAR('0','1'), CHAR('2','3'), CHAR('4','5'), CHAR('6','7'), + CHAR('8','9'), CHAR(' ','!'), CHAR('"','#'), CHAR('$','%'), CHAR('&','\''), + CHAR('(',')'), CHAR('*','+'), CHAR(',','-'), CHAR('.','/'), CHAR('@',0), + CHAR('\r','\n'), + CHAR(' ',' '), CHAR(':',';'), CHAR('<','='), CHAR('>','?'), CHAR('[','\\'), + CHAR(']','^'), CHAR('_','`'), CHAR('{','|'), CHAR('}','~'), CHAR(127,0), + CHAR('\r','\n'), + CHAR(' ',' '), CHAR(14,0), CHAR(1,2), CHAR(3,4), CHAR(5,6), CHAR(7,8), + CHAR(9,10), CHAR(11,12), CHAR(13,14), CHAR(16,17), CHAR(18,19), CHAR(20,21), + CHAR(22,23), CHAR(24,25), CHAR(26,27), CHAR(28,29), CHAR(30,31), + CHAR(15,0), CHAR('\r','\n'), + + /* italic text */ + LSRA(ST_SAME, SI_SAME, LI_SAME, IT_ITALIC, RF_UNSYNC, MN_SAME), + + /* note no SGMhere */ + CHAR(' ',' '), CHAR('A','B'), CHAR('C','D'), CHAR('E','F'), CHAR('G','H'), + CHAR('I','J'), CHAR('K','L'), CHAR('M','N'), CHAR('O','P'), CHAR('Q','R'), + CHAR('S','T'), CHAR('U','V'), CHAR('W','X'), CHAR('Y','Z'), CHAR('\r','\n'), + CHAR(' ',' '), CHAR('a','b'), CHAR('c','d'), CHAR('e','f'), CHAR('g','h'), + CHAR('i','j'), CHAR('k','l'), CHAR('m','n'), CHAR('o','p'), CHAR('q','r'), + CHAR('s','t'), CHAR('u','v'), CHAR('w','x'), CHAR('y','z'), CHAR('\r','\n'), + CHAR(' ',' '), CHAR('0','1'), CHAR('2','3'), CHAR('4','5'), CHAR('6','7'), + CHAR('8','9'), CHAR(' ','!'), CHAR('"','#'), CHAR('$','%'), CHAR('&','\''), + CHAR('(',')'), CHAR('*','+'), CHAR(',','-'), CHAR('.','/'), CHAR('@',0), + CHAR('\r','\n'), + CHAR(' ',' '), CHAR(':',';'), CHAR('<','='), CHAR('>','?'), CHAR('[','\\'), + CHAR(']','^'), CHAR('_','`'), CHAR('{','|'), CHAR('}','~'), CHAR(127,0), + CHAR('\r','\n'), + CHAR(' ',' '), CHAR(14,0), CHAR(1,2), CHAR(3,4), CHAR(5,6), CHAR(7,8), + CHAR(9,10), CHAR(11,12), CHAR(13,14), CHAR(16,17), CHAR(18,19), CHAR(20,21), + CHAR(22,23), CHAR(24,25), CHAR(26,27), CHAR(28,29), CHAR(30,31), + CHAR(15,0), CHAR('\r','\n'), + + /* labeled lines of all types, blinks, and intensities (LP intr disabled) */ + LSRA(ST_SAME, SI_SAME, LI_INTENSIFY, IT_NORMAL, RF_UNSYNC, MN_SAME), + + SGM(GM_APOINT, IN_SAME, LP_DIS, BL_SAME, LT_SAME), + APOINT(I_OFF, 020, 0740), + + SGM(GM_CHAR, IN_0, LP_SAME, BL_OFF, LT_SAME), + CHAR('I','N'), CHAR('T',' '), CHAR('0',0), + + SGM(GM_APOINT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + APOINT(I_ON, 0140, 0740), + + SGM(GM_APOINT, IN_SAME, LP_SAME, BL_ON, LT_SAME), + APOINT(I_ON, 0150, 0740), + + SGM(GM_APOINT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + APOINT(I_OFF, 0160, 0740), + + SGM(GM_SVECT, IN_SAME, LP_SAME, BL_OFF, LT_SOLID), + SVECT(I_ON, 060, 0), + + SGM(GM_SVECT, IN_SAME, LP_SAME, BL_ON, LT_SAME), + SVECT(I_ON, 060, 0), + + SGM(GM_SVECT, IN_SAME, LP_SAME, BL_OFF, LT_LDASH), + SVECT(I_ON, 060, 0), + + SGM(GM_SVECT, IN_SAME, LP_SAME, BL_ON, LT_SAME), + SVECT(I_ON, 060, 0), + + SGM(GM_SVECT, IN_SAME, LP_SAME, BL_OFF, LT_SDASH), + SVECT(I_ON, 060, 0), + + SGM(GM_SVECT, IN_SAME, LP_SAME, BL_ON, LT_SAME), + SVECT(I_ON, 060, 0), + + SGM(GM_SVECT, IN_SAME, LP_SAME, BL_OFF, LT_DDASH), + SVECT(I_ON, 060, 0), + + SGM(GM_SVECT, IN_SAME, LP_SAME, BL_ON, LT_SAME), + SVECT(I_ON, 060, 0), + + SGM(GM_APOINT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + APOINT(I_OFF, 020, 0700), + + SGM(GM_CHAR, IN_1, LP_SAME, BL_OFF, LT_SAME), + CHAR('I','N'), CHAR('T',' '), CHAR('1',0), + + SGM(GM_APOINT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + APOINT(I_ON, 0140, 0700), + + SGM(GM_APOINT, IN_SAME, LP_SAME, BL_ON, LT_SAME), + APOINT(I_ON, 0150, 0700), + + SGM(GM_APOINT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + APOINT(I_OFF, 0160, 0700), + + SGM(GM_SVECT, IN_SAME, LP_SAME, BL_OFF, LT_SOLID), + SVECT(I_ON, 060, 0), + + SGM(GM_SVECT, IN_SAME, LP_SAME, BL_ON, LT_SAME), + SVECT(I_ON, 060, 0), + + SGM(GM_SVECT, IN_SAME, LP_SAME, BL_OFF, LT_LDASH), + SVECT(I_ON, 060, 0), + + SGM(GM_SVECT, IN_SAME, LP_SAME, BL_ON, LT_SAME), + SVECT(I_ON, 060, 0), + + SGM(GM_SVECT, IN_SAME, LP_SAME, BL_OFF, LT_SDASH), + SVECT(I_ON, 060, 0), + + SGM(GM_SVECT, IN_SAME, LP_SAME, BL_ON, LT_SAME), + SVECT(I_ON, 060, 0), + + SGM(GM_SVECT, IN_SAME, LP_SAME, BL_OFF, LT_DDASH), + SVECT(I_ON, 060, 0), + + SGM(GM_SVECT, IN_SAME, LP_SAME, BL_ON, LT_SAME), + SVECT(I_ON, 060, 0), + + SGM(GM_APOINT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + APOINT(I_OFF, 020, 0640), + + SGM(GM_CHAR, IN_2, LP_SAME, BL_OFF, LT_SAME), + CHAR('I','N'), CHAR('T',' '), CHAR('2',0), + + SGM(GM_APOINT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + APOINT(I_ON, 0140, 0640), + + SGM(GM_APOINT, IN_SAME, LP_SAME, BL_ON, LT_SAME), + APOINT(I_ON, 0150, 0640), + + SGM(GM_APOINT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + APOINT(I_OFF, 0160, 0640), + + SGM(GM_SVECT, IN_SAME, LP_SAME, BL_OFF, LT_SOLID), + SVECT(I_ON, 060, 0), + + SGM(GM_SVECT, IN_SAME, LP_SAME, BL_ON, LT_SAME), + SVECT(I_ON, 060, 0), + + SGM(GM_SVECT, IN_SAME, LP_SAME, BL_OFF, LT_LDASH), + SVECT(I_ON, 060, 0), + + SGM(GM_SVECT, IN_SAME, LP_SAME, BL_ON, LT_SAME), + SVECT(I_ON, 060, 0), + + SGM(GM_SVECT, IN_SAME, LP_SAME, BL_OFF, LT_SDASH), + SVECT(I_ON, 060, 0), + + SGM(GM_SVECT, IN_SAME, LP_SAME, BL_ON, LT_SAME), + SVECT(I_ON, 060, 0), + + SGM(GM_SVECT, IN_SAME, LP_SAME, BL_OFF, LT_DDASH), + SVECT(I_ON, 060, 0), + + SGM(GM_SVECT, IN_SAME, LP_SAME, BL_ON, LT_SAME), + SVECT(I_ON, 060, 0), + + SGM(GM_APOINT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + APOINT(I_OFF, 020, 0600), + + SGM(GM_CHAR, IN_3, LP_SAME, BL_OFF, LT_SAME), + CHAR('I','N'), CHAR('T',' '), CHAR('3',0), + + SGM(GM_APOINT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + APOINT(I_ON, 0140, 0600), + + SGM(GM_APOINT, IN_SAME, LP_SAME, BL_ON, LT_SAME), + APOINT(I_ON, 0150, 0600), + + SGM(GM_APOINT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + APOINT(I_OFF, 0160, 0600), + + SGM(GM_SVECT, IN_SAME, LP_SAME, BL_OFF, LT_SOLID), + SVECT(I_ON, 060, 0), + + SGM(GM_SVECT, IN_SAME, LP_SAME, BL_ON, LT_SAME), + SVECT(I_ON, 060, 0), + + SGM(GM_SVECT, IN_SAME, LP_SAME, BL_OFF, LT_LDASH), + SVECT(I_ON, 060, 0), + + SGM(GM_SVECT, IN_SAME, LP_SAME, BL_ON, LT_SAME), + SVECT(I_ON, 060, 0), + + SGM(GM_SVECT, IN_SAME, LP_SAME, BL_OFF, LT_SDASH), + SVECT(I_ON, 060, 0), + + SGM(GM_SVECT, IN_SAME, LP_SAME, BL_ON, LT_SAME), + SVECT(I_ON, 060, 0), + + SGM(GM_SVECT, IN_SAME, LP_SAME, BL_OFF, LT_DDASH), + SVECT(I_ON, 060, 0), + + SGM(GM_SVECT, IN_SAME, LP_SAME, BL_ON, LT_SAME), + SVECT(I_ON, 060, 0), + + SGM(GM_APOINT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + APOINT(I_OFF, 020, 0540), + + SGM(GM_CHAR, IN_4, LP_SAME, BL_OFF, LT_SAME), + CHAR('I','N'), CHAR('T',' '), CHAR('4',0), + + SGM(GM_APOINT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + APOINT(I_ON, 0140, 0540), + + SGM(GM_APOINT, IN_SAME, LP_SAME, BL_ON, LT_SAME), + APOINT(I_ON, 0150, 0540), + + SGM(GM_APOINT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + APOINT(I_OFF, 0160, 0540), + + SGM(GM_SVECT, IN_SAME, LP_SAME, BL_OFF, LT_SOLID), + SVECT(I_ON, 060, 0), + + SGM(GM_SVECT, IN_SAME, LP_SAME, BL_ON, LT_SAME), + SVECT(I_ON, 060, 0), + + SGM(GM_SVECT, IN_SAME, LP_SAME, BL_OFF, LT_LDASH), + SVECT(I_ON, 060, 0), + + SGM(GM_SVECT, IN_SAME, LP_SAME, BL_ON, LT_SAME), + SVECT(I_ON, 060, 0), + + SGM(GM_SVECT, IN_SAME, LP_SAME, BL_OFF, LT_SDASH), + SVECT(I_ON, 060, 0), + + SGM(GM_SVECT, IN_SAME, LP_SAME, BL_ON, LT_SAME), + SVECT(I_ON, 060, 0), + + SGM(GM_SVECT, IN_SAME, LP_SAME, BL_OFF, LT_DDASH), + SVECT(I_ON, 060, 0), + + SGM(GM_SVECT, IN_SAME, LP_SAME, BL_ON, LT_SAME), + SVECT(I_ON, 060, 0), + + SGM(GM_APOINT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + APOINT(I_OFF, 020, 0500), + + SGM(GM_CHAR, IN_5, LP_SAME, BL_OFF, LT_SAME), + CHAR('I','N'), CHAR('T',' '), CHAR('5',0), + + SGM(GM_APOINT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + APOINT(I_ON, 0140, 0500), + + SGM(GM_APOINT, IN_SAME, LP_SAME, BL_ON, LT_SAME), + APOINT(I_ON, 0150, 0500), + + SGM(GM_APOINT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + APOINT(I_OFF, 0160, 0500), + + SGM(GM_SVECT, IN_SAME, LP_SAME, BL_OFF, LT_SOLID), + SVECT(I_ON, 060, 0), + + SGM(GM_SVECT, IN_SAME, LP_SAME, BL_ON, LT_SAME), + SVECT(I_ON, 060, 0), + + SGM(GM_SVECT, IN_SAME, LP_SAME, BL_OFF, LT_LDASH), + SVECT(I_ON, 060, 0), + + SGM(GM_SVECT, IN_SAME, LP_SAME, BL_ON, LT_SAME), + SVECT(I_ON, 060, 0), + + SGM(GM_SVECT, IN_SAME, LP_SAME, BL_OFF, LT_SDASH), + SVECT(I_ON, 060, 0), + + SGM(GM_SVECT, IN_SAME, LP_SAME, BL_ON, LT_SAME), + SVECT(I_ON, 060, 0), + + SGM(GM_SVECT, IN_SAME, LP_SAME, BL_OFF, LT_DDASH), + SVECT(I_ON, 060, 0), + + SGM(GM_SVECT, IN_SAME, LP_SAME, BL_ON, LT_SAME), + SVECT(I_ON, 060, 0), + + SGM(GM_APOINT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + APOINT(I_OFF, 020, 0440), + + SGM(GM_CHAR, IN_6, LP_SAME, BL_OFF, LT_SAME), + CHAR('I','N'), CHAR('T',' '), CHAR('6',0), + + SGM(GM_APOINT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + APOINT(I_ON, 0140, 0440), + + SGM(GM_APOINT, IN_SAME, LP_SAME, BL_ON, LT_SAME), + APOINT(I_ON, 0150, 0440), + + SGM(GM_APOINT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + APOINT(I_OFF, 0160, 0440), + + SGM(GM_SVECT, IN_SAME, LP_SAME, BL_OFF, LT_SOLID), + SVECT(I_ON, 060, 0), + + SGM(GM_SVECT, IN_SAME, LP_SAME, BL_ON, LT_SAME), + SVECT(I_ON, 060, 0), + + SGM(GM_SVECT, IN_SAME, LP_SAME, BL_OFF, LT_LDASH), + SVECT(I_ON, 060, 0), + + SGM(GM_SVECT, IN_SAME, LP_SAME, BL_ON, LT_SAME), + SVECT(I_ON, 060, 0), + + SGM(GM_SVECT, IN_SAME, LP_SAME, BL_OFF, LT_SDASH), + SVECT(I_ON, 060, 0), + + SGM(GM_SVECT, IN_SAME, LP_SAME, BL_ON, LT_SAME), + SVECT(I_ON, 060, 0), + + SGM(GM_SVECT, IN_SAME, LP_SAME, BL_OFF, LT_DDASH), + SVECT(I_ON, 060, 0), + + SGM(GM_SVECT, IN_SAME, LP_SAME, BL_ON, LT_SAME), + SVECT(I_ON, 060, 0), + + SGM(GM_APOINT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + APOINT(I_OFF, 020, 0400), + + SGM(GM_CHAR, IN_7, LP_SAME, BL_OFF, LT_SAME), + CHAR('I','N'), CHAR('T',' '), CHAR('7',0), + + SGM(GM_APOINT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + APOINT(I_ON, 0140, 0400), + + SGM(GM_APOINT, IN_SAME, LP_SAME, BL_ON, LT_SAME), + APOINT(I_ON, 0150, 0400), + + SGM(GM_APOINT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + APOINT(I_OFF, 0160, 0400), + + SGM(GM_SVECT, IN_SAME, LP_SAME, BL_OFF, LT_SOLID), + SVECT(I_ON, 060, 0), + + SGM(GM_SVECT, IN_SAME, LP_SAME, BL_ON, LT_SAME), + SVECT(I_ON, 060, 0), + + SGM(GM_SVECT, IN_SAME, LP_SAME, BL_OFF, LT_LDASH), + SVECT(I_ON, 060, 0), + + SGM(GM_SVECT, IN_SAME, LP_SAME, BL_ON, LT_SAME), + SVECT(I_ON, 060, 0), + + SGM(GM_SVECT, IN_SAME, LP_SAME, BL_OFF, LT_SDASH), + SVECT(I_ON, 060, 0), + + SGM(GM_SVECT, IN_SAME, LP_SAME, BL_ON, LT_SAME), + SVECT(I_ON, 060, 0), + + SGM(GM_SVECT, IN_SAME, LP_SAME, BL_OFF, LT_DDASH), + SVECT(I_ON, 060, 0), + + SGM(GM_SVECT, IN_SAME, LP_SAME, BL_ON, LT_SAME), + SVECT(I_ON, 060, 0), + + /* similar, but LP intr enabled, official threshold intensities */ + SGM(GM_APOINT, IN_SAME, LP_ENA, BL_SAME, LT_SAME), + APOINT(I_OFF, 020, 0340), + + LSRA(ST_SAME, SI_SAME, LI_SAME, IT_ITALIC, RF_UNSYNC, MN_SAME), + + SGM(GM_CHAR, IN_6, LP_SAME, BL_ON, LT_SAME), + CHAR('I','N'), CHAR('T','R'), + + SGM(GM_APOINT, IN_4, LP_SAME, BL_OFF, LT_SAME), + APOINT(I_ON, 0140, 0340), + + SGM(GM_APOINT, IN_SAME, LP_SAME, BL_ON, LT_SAME), + APOINT(I_ON, 0150, 0340), + + SGM(GM_APOINT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + APOINT(I_OFF, 0160, 0340), + + SGM(GM_SVECT, IN_SAME, LP_SAME, BL_OFF, LT_SOLID), + SVECT(I_ON, 060, 0), + + SGM(GM_SVECT, IN_SAME, LP_SAME, BL_ON, LT_SAME), + SVECT(I_ON, 060, 0), + + SGM(GM_SVECT, IN_SAME, LP_SAME, BL_OFF, LT_LDASH), + SVECT(I_ON, 060, 0), + + SGM(GM_SVECT, IN_SAME, LP_SAME, BL_ON, LT_SAME), + SVECT(I_ON, 060, 0), + + SGM(GM_SVECT, IN_SAME, LP_SAME, BL_OFF, LT_SDASH), + SVECT(I_ON, 060, 0), + + SGM(GM_SVECT, IN_SAME, LP_SAME, BL_ON, LT_SAME), + SVECT(I_ON, 060, 0), + + SGM(GM_SVECT, IN_SAME, LP_SAME, BL_OFF, LT_DDASH), + SVECT(I_ON, 060, 0), + + SGM(GM_SVECT, IN_SAME, LP_SAME, BL_ON, LT_SAME), + SVECT(I_ON, 060, 0), + + /* graphplots */ + SGM(GM_APOINT, IN_5, LP_SAME, BL_SAME, LT_SAME), + APOINT(I_ON, 040, 0200), + + LSRB(CL_SAME, SS_CHANGE, 040), + + SGM(GM_GRAPHY, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + GRAPHY(I_ON, 0160), + GRAPHY(I_ON, 0140), + GRAPHY(I_ON, 0120), + GRAPHY(I_ON, 0100), + GRAPHY(I_ON, 0060), + GRAPHY(I_ON, 0040), + + SGM(GM_RPOINT, IN_SAME, LP_SAME, BL_OFF, LT_SAME), + RPOINT(I_OFF, 0040, 0), + RPOINT(I_ON, 0040, 0), + + LSRB(CL_SAME, SS_CHANGE, 020), + + SGM(GM_GRAPHX, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + GRAPHX(I_ON, 0500), + GRAPHX(I_ON, 0540), + GRAPHX(I_ON, 0600), + GRAPHX(I_ON, 0640), + GRAPHX(I_ON, 0700), + GRAPHX(I_ON, 0740), + + /* long vectors in all directions from a common origin */ + SGM(GM_APOINT, IN_4, LP_SAME, BL_SAME, LT_SOLID), + APOINT(I_OFF, 01400, 01100), + SGM(GM_LVECT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + LVECT(I_ON, 0400, 0), + + SGM(GM_APOINT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + APOINT(I_OFF, 01400, 01100), + SGM(GM_LVECT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + LVECT(I_ON, 0400, 0100), + + SGM(GM_APOINT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + APOINT(I_OFF, 01400, 01100), + SGM(GM_LVECT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + LVECT(I_ON, 0400, 0200), + + SGM(GM_APOINT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + APOINT(I_OFF, 01400, 01100), + SGM(GM_LVECT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + LVECT(I_ON, 0400, 0300), + + SGM(GM_APOINT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + APOINT(I_OFF, 01400, 01100), + SGM(GM_LVECT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + LVECT(I_ON, 0300, 0300), + + SGM(GM_APOINT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + APOINT(I_OFF, 01400, 01100), + SGM(GM_LVECT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + LVECT(I_ON, 0200, 0300), + + SGM(GM_APOINT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + APOINT(I_OFF, 01400, 01100), + SGM(GM_LVECT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + LVECT(I_ON, 0100, 0300), + + SGM(GM_APOINT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + APOINT(I_OFF, 01400, 01100), + SGM(GM_LVECT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + LVECT(I_ON, 0, 0300), + + SGM(GM_APOINT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + APOINT(I_OFF, 01400, 01100), + SGM(GM_LVECT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + LVECT(I_ON, -0100, 0300), + + SGM(GM_APOINT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + APOINT(I_OFF, 01400, 01100), + SGM(GM_LVECT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + LVECT(I_ON, -0200, 0300), + + SGM(GM_APOINT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + APOINT(I_OFF, 01400, 01100), + SGM(GM_LVECT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + LVECT(I_ON, -0300, 0300), + + SGM(GM_APOINT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + APOINT(I_OFF, 01400, 01100), + SGM(GM_LVECT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + LVECT(I_ON, -0400, 0300), + + SGM(GM_APOINT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + APOINT(I_OFF, 01400, 01100), + SGM(GM_LVECT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + LVECT(I_ON, -0400, 0200), + + SGM(GM_APOINT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + APOINT(I_OFF, 01400, 01100), + SGM(GM_LVECT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + LVECT(I_ON, -0400, 0100), + + SGM(GM_APOINT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + APOINT(I_OFF, 01400, 01100), + SGM(GM_LVECT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + LVECT(I_ON, -0400, 0), + + SGM(GM_APOINT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + APOINT(I_OFF, 01400, 01100), + SGM(GM_LVECT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + LVECT(I_ON, -0400, -0100), + + SGM(GM_APOINT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + APOINT(I_OFF, 01400, 01100), + SGM(GM_LVECT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + LVECT(I_ON, -0400, -0200), + + SGM(GM_APOINT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + APOINT(I_OFF, 01400, 01100), + SGM(GM_LVECT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + LVECT(I_ON, -0400, -0300), + + SGM(GM_APOINT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + APOINT(I_OFF, 01400, 01100), + SGM(GM_LVECT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + LVECT(I_ON, -0300, -0300), + + SGM(GM_APOINT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + APOINT(I_OFF, 01400, 01100), + SGM(GM_LVECT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + LVECT(I_ON, -0200, -0300), + + SGM(GM_APOINT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + APOINT(I_OFF, 01400, 01100), + SGM(GM_LVECT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + LVECT(I_ON, -0100, -0300), + + SGM(GM_APOINT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + APOINT(I_OFF, 01400, 01100), + SGM(GM_LVECT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + LVECT(I_ON, 0, -0300), + + SGM(GM_APOINT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + APOINT(I_OFF, 01400, 01100), + SGM(GM_LVECT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + LVECT(I_ON, 0100, -0300), + + SGM(GM_APOINT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + APOINT(I_OFF, 01400, 01100), + SGM(GM_LVECT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + LVECT(I_ON, 0200, -0300), + + SGM(GM_APOINT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + APOINT(I_OFF, 01400, 01100), + SGM(GM_LVECT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + LVECT(I_ON, 0300, -0300), + + SGM(GM_APOINT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + APOINT(I_OFF, 01400, 01100), + SGM(GM_LVECT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + LVECT(I_ON, 0400, -0300), + + SGM(GM_APOINT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + APOINT(I_OFF, 01400, 01100), + SGM(GM_LVECT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + LVECT(I_ON, 0400, -0200), + + SGM(GM_APOINT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + APOINT(I_OFF, 01400, 01100), + SGM(GM_LVECT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + LVECT(I_ON, 0400, -0100), + + /* nearby lines with varied spacing */ + SGM(GM_APOINT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + APOINT(I_OFF, 01200, 0500), + + SGM(GM_SVECT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + SVECT(I_ON, 077, 0), + SVECT(I_OFF, -077, -1), + SVECT(I_ON, 077, 0), + SVECT(I_OFF, -077, -2), + SVECT(I_ON, 077, 0), + SVECT(I_OFF, -077, -3), + SVECT(I_ON, 077, 0), + SVECT(I_OFF, -077, -4), + SVECT(I_ON, 077, 0), + SVECT(I_OFF, -077, -5), + SVECT(I_ON, 077, 0), + SVECT(I_OFF, -077, -6), + SVECT(I_ON, 077, 0), + SVECT(I_OFF, -077, -7), + SVECT(I_ON, 077, 0), + SVECT(I_OFF, -077, -010), + SVECT(I_ON, 077, 0), + SVECT(I_OFF, -077, 044), + SVECT(I_ON, 0, -077), + SVECT(I_OFF, 1, 077), + SVECT(I_ON, 0, -077), + SVECT(I_OFF, 2, 077), + SVECT(I_ON, 0, -077), + SVECT(I_OFF, 3, 077), + SVECT(I_ON, 0, -077), + SVECT(I_OFF, 4, 077), + SVECT(I_ON, 0, -077), + SVECT(I_OFF, 5, 077), + SVECT(I_ON, 0, -077), + SVECT(I_OFF, 6, 077), + SVECT(I_ON, 0, -077), + SVECT(I_OFF, 7, 077), + SVECT(I_ON, 0, -077), + SVECT(I_OFF, 010, 077), + SVECT(I_ON, 0, -077), + + /* all four flavors of characters (lp intr enabled, but intensity 4) */ + + SGM(GM_APOINT, IN_4, LP_SAME, BL_SAME, LT_SAME), + APOINT(I_OFF, 01040, 0240), + + LSRA(ST_SAME, SI_SAME, LP_SAME, IT_NORMAL, RF_UNSYNC, MN_SAME), + + SGM(GM_CHAR, IN_SAME, LP_SAME, BL_OFF, LT_SAME), + CHAR('N','o'), CHAR('r','m'), CHAR('a','l'), + + SGM(GM_CHAR, IN_SAME, LP_SAME, BL_ON, LT_SAME), + CHAR(' ','B'), CHAR('l','i'), CHAR('n','k'), + + SGM(GM_APOINT, IN_4, LP_SAME, BL_SAME, LT_SAME), + APOINT(I_OFF, 01040, 0200), + + LSRA(ST_SAME, SI_SAME, LP_SAME, IT_ITALIC, RF_UNSYNC, MN_SAME), + + SGM(GM_CHAR, IN_SAME, LP_SAME, BL_OFF, LT_SAME), + CHAR('I','t'), CHAR('a','l'), CHAR('i','c'), + + SGM(GM_CHAR, IN_SAME, LP_SAME, BL_ON, LT_SAME), + CHAR(' ','B'), CHAR('l','i'), CHAR('n','k'), + + /* all eight intensities of characters (lp intr enabled) */ + + LSRA(ST_SAME, SI_SAME, LP_SAME, IT_NORMAL, RF_UNSYNC, MN_SAME), + + SGM(GM_APOINT, IN_5, LP_SAME, BL_SAME, LT_SAME), + APOINT(I_OFF, 01040, 0100), + + SGM(GM_CHAR, IN_SAME, LP_SAME, BL_OFF, LT_SAME), + CHAR('I','N'), CHAR('T',' '), + + SGM(GM_CHAR, IN_0, LP_SAME, BL_SAME, LT_SAME), + CHAR('0',0), + SGM(GM_CHAR, IN_1, LP_SAME, BL_SAME, LT_SAME), + CHAR('1',0), + SGM(GM_CHAR, IN_2, LP_SAME, BL_SAME, LT_SAME), + CHAR('2',0), + SGM(GM_CHAR, IN_3, LP_SAME, BL_SAME, LT_SAME), + CHAR('3',0), + SGM(GM_CHAR, IN_4, LP_SAME, BL_SAME, LT_SAME), + CHAR('4',0), + SGM(GM_CHAR, IN_5, LP_SAME, BL_SAME, LT_SAME), + CHAR('5',0), + SGM(GM_CHAR, IN_6, LP_SAME, BL_SAME, LT_SAME), + CHAR('6',0), + SGM(GM_CHAR, IN_7, LP_SAME, BL_SAME, LT_SAME), + CHAR('7',0), + + /* XXX -- more can be included in this pattern */ + + ENDSECT + + /* SECTION 4. Clipping tests. + Suitable for VT11 and VS60. */ + + LSRA(ST_SAME, SI_SAME, LI_INTENSIFY, IT_NORMAL, RF_UNSYNC, MN_SAME), + + SGM(GM_APOINT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + APOINT(I_OFF, 01000, 01000), + + SGM(GM_LVECT, IN_4, LP_ENA, BL_OFF, LT_SOLID), + LVECT(I_ON, 01100, 0), + LVECT(I_ON, -01100, 01100), + LVECT(I_ON, 0, -01100), + LVECT(I_OFF, 0, 01100), + LVECT(I_ON, -01100, -01100), + LVECT(I_ON, 01100, 0), + LVECT(I_ON, 0, -01100), + LVECT(I_ON, -01100, 01100), + LVECT(I_OFF, 01100, 0), + LVECT(I_OFF, 01100, 0), + LVECT(I_ON, -01100, -01100), + + ENDSECT + + /* END OF TEST SECTIONS. */ + + ENDFILE +}; + +/* FILE LP. Dynamic light pen tracking; works for both VT11 and VS60. */ + +unsigned short LP[] = { + /* SECTION 1. "rubber-band" dot-dash vector to tracking object. */ + + SGM(GM_APOINT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + APOINT(I_OFF, 01000, 01000), /* screen center */ + + SGM(GM_LVECT, IN_4, LP_DIS, BL_SAME, LT_DDASH), + /* following coordinates are updated by LP hit intr. handler: */ + LVECT(I_ON, 0, 0), /* tracking object center */ + + SGM(GM_SVECT, IN_7, LP_ENA, BL_SAME, LT_SOLID), + SVECT(I_OFF, 1, -31), + SVECT(I_ON, -2, 0), + SVECT(I_OFF, 2, 0), + SVECT(I_ON, 0, 62), + SVECT(I_ON, -2, 0), + SVECT(I_OFF, 2, 0), + SVECT(I_ON, 30, -30), + SVECT(I_OFF, 0, -2), + SVECT(I_ON, 0, 2), + SVECT(I_ON, -62, 0), + SVECT(I_OFF, 0, -2), + SVECT(I_ON, 0, 2), + SVECT(I_ON, 30, 30), + SVECT(I_ON, 0, -62), + SVECT(I_ON, -30, 30), + SVECT(I_ON, 62, 0), + SVECT(I_ON, -30, -30), +#if 0 /* not needed for this app */ + SVECT(I_OFF, -1, 31), /* "flyback" vector */ +#endif + + ENDSECT + + /* END OF TEST SECTIONS. */ + + ENDFILE +}; + +/* FILE VS. Static displays that work only for VS60. */ + +unsigned short VS[] = { + /* SECTION 0. Warning that VS60 is required. */ + + LSRA(ST_SAME, SI_SAME, LI_SAME, IT_NORMAL, RF_UNSYNC, MN_SAME), + + SGM(GM_APOINT, IN_7, LP_SAME, BL_SAME, LT_SAME), + APOINT(I_OFF, 0300, 01000), + + SGM(GM_CHAR, IN_SAME, LP_SAME, BL_OFF, LT_SAME), + CHAR('F','o'), CHAR('l','l'), CHAR('o','w'), CHAR('i','n'), CHAR('g',' '), + CHAR('t','e'), CHAR('s','t'), CHAR('s',' '), CHAR('d','o'), + CHAR(' ','n'), CHAR('o','t'), CHAR(' ','w'), CHAR('o','r'), + CHAR('k',' '), CHAR('f','o'), CHAR('r',' '), CHAR('V','T'), + CHAR('1','1'), CHAR(';',0), + + /* italic text */ + LSRA(ST_SAME, SI_SAME, LI_SAME, IT_ITALIC, RF_UNSYNC, MN_SAME), + + SGM(GM_APOINT, IN_7, LP_SAME, BL_SAME, LT_SAME), + APOINT(I_OFF, 0340, 00720), + + SGM(GM_CHAR, IN_SAME, LP_SAME, BL_ON, LT_SAME), + CHAR('S','T'), CHAR('O','P'), CHAR(' ','P'), CHAR('R','O'), CHAR('G','R'), + CHAR('A','M'), CHAR(' ','i'), CHAR('f',' '), CHAR('n','o'), CHAR('t',' '), + CHAR('u','s'), CHAR('i','n'), CHAR('g',' '), CHAR('V','R'), CHAR('4','8'), + CHAR('!',0), + + ENDSECT + + /* SECTION 1. Variety of text characters. */ + + LSRA(ST_SAME, SI_SAME, LI_BRIGHTDOWN, IT_SAME, RF_UNSYNC, MN_MAIN), + + /* horizontal text, 4 sizes */ + SGM(GM_APOINT, IN_4, LP_ENA, BL_SAME, LT_SAME), + APOINT(I_OFF, 0, 01600), + + SGM(GM_CHAR, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + LSRC(RO_SAME, CS_CHANGE, 0, VS_SAME, 0), + CHAR(' ',' '), CHAR('S','m'), CHAR('a','l'), CHAR('l',':'), CHAR(' ','1'), + CHAR('/','2'), + LSRC(RO_SAME, CS_CHANGE, 1, VS_SAME, 0), + CHAR(' ',' '), CHAR('N','o'), CHAR('r','m'), CHAR('a','l'), CHAR(':',' '), + CHAR('1',0), + LSRC(RO_SAME, CS_CHANGE, 2, VS_SAME, 0), + CHAR(' ',' '), CHAR('B','i'), CHAR('g',':'), CHAR(' ','1'), CHAR('-','1'), + CHAR('/','2'), + LSRC(RO_SAME, CS_CHANGE, 3, VS_SAME, 0), + CHAR(' ',' '), CHAR('L','a'), CHAR('r','g'), CHAR('e',':'), CHAR(' ','2'), + CHAR('\r','\n'), CHAR('\r','\n'), + CHAR(' ',' '), CHAR('A',SUBSCR), CHAR('B',SUBSCR), CHAR('C',SUBSCR), + CHAR('D',ENDSUB), CHAR(ENDSUB,ENDSUB), CHAR('W',SUPSCR), + CHAR('X',SUPSCR), CHAR('Y',SUPSCR), CHAR('Z',ENDSUP), + CHAR(ENDSUP,ENDSUP), CHAR('!','!'), + + /* vertical text, 4 sizes */ + SGM(GM_APOINT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + APOINT(I_OFF, 0200, 0), + + SGM(GM_CHAR, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + LSRC(RO_VERTICAL, CS_CHANGE, 0, VS_SAME, 0), + CHAR(' ',' '), CHAR('S','m'), CHAR('a','l'), CHAR('l',':'), CHAR(' ','1'), + CHAR('/','2'), + LSRC(RO_SAME, CS_CHANGE, 1, VS_SAME, 0), + CHAR(' ',' '), CHAR('N','o'), CHAR('r','m'), CHAR('a','l'), CHAR(':',' '), + CHAR('1',0), + LSRC(RO_SAME, CS_CHANGE, 2, VS_SAME, 0), + CHAR(' ',' '), CHAR('B','i'), CHAR('g',':'), CHAR(' ','1'), CHAR('-','1'), + CHAR('/','2'), + LSRC(RO_SAME, CS_CHANGE, 3, VS_SAME, 0), + CHAR(' ',' '), CHAR('L','a'), CHAR('r','g'), CHAR('e',':'), CHAR(' ','2'), + CHAR('\r','\n'), CHAR('\r','\n'), + CHAR(' ',' '), CHAR('A',SUBSCR), CHAR('B',SUBSCR), CHAR('C',SUBSCR), + CHAR('D',ENDSUB), CHAR(ENDSUB,ENDSUB), CHAR('W',SUPSCR), + CHAR('X',SUPSCR), CHAR('Y',SUPSCR), CHAR('Z',ENDSUP), + CHAR(ENDSUP,ENDSUP), CHAR('!','!'), + + /* horizontal text, sub/superscript examples from DECgraphic-11 manual */ + SGM(GM_APOINT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + APOINT(I_OFF, 0400, 01200), + + LSRC(RO_HORIZONTAL, CS_CHANGE, 2, VS_SAME, 0), + SGM(GM_CHAR, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + CHAR('C',SUBSCR), CHAR('2',ENDSUB), CHAR('H',SUBSCR), CHAR('5',ENDSUB), + CHAR('O','H'), CHAR(' ',' '), + CHAR(016,000), CHAR(017,'='), CHAR(016,003), CHAR(017,'('), + CHAR('x',SUBSCR), CHAR('i',ENDSUB), CHAR('-','q'), CHAR(SUBSCR,'i'), + CHAR(ENDSUB,')'), CHAR(SUPSCR,'2'), CHAR(ENDSUP,'e'), CHAR(SUPSCR,'-'), + CHAR('i',SUPSCR), CHAR('2',ENDSUP), CHAR(ENDSUP,0), + + LSRC(RO_SAME, CS_CHANGE, 1, VS_SAME, 0), + LSRA(ST_SAME, SI_SAME, LI_SAME, IT_SAME, RF_SAME, MN_MENU), + SGM(GM_APOINT, IN_7, LP_ENA, BL_SAME, LT_SAME), + APOINT(I_OFF, 0, 1000), + SGM(GM_CHAR, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + CHAR('U','n'), CHAR('s','y'), CHAR('n','c'), + + ENDSECT + + /* SECTION 2. Basic vectors (long and short). */ + + LSRA(ST_SAME, SI_SAME, LI_BRIGHTDOWN, IT_SAME, RF_40, MN_MAIN), + + SGM(GM_APOINT, IN_4, LP_ENA, BL_OFF, LT_SDASH), + APOINT(I_OFF, 01000, 01000), + + SGM(GM_GRAPHX, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + BLVECT(I_OFF, 2, 0600), + BLVECT(I_ON, 0, 0200), + BLVECT(I_ON, 7, 0400), + BLVECT(I_ON, 6, 0400), + BLVECT(I_ON, 5, 0400), + BLVECT(I_ON, 4, 0400), + SGM(GM_GRAPHY, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + BLVECT(I_ON, 3, 0400), + BLVECT(I_ON, 2, 0400), + BLVECT(I_ON, 1, 0400), + BLVECT(I_ON, 0, 0200), + BLVECT(I_OFF, 6, 0600), + + SGM(GM_BSVECT, IN_SAME, LP_SAME, BL_ON, LT_SOLID), + BSVECT(I_OFF, 2, 007, 2, 016), + BSVECT(I_ON, 0, 007, 7, 016), + BSVECT(I_ON, 6, 016, 5, 016), + BSVECT(I_ON, 4, 016, 3, 016), + BSVECT(I_ON, 2, 016, 1, 016), + BSVECT(I_ON, 0, 007, 0, 000), + + LSRA(ST_SAME, SI_SAME, LI_SAME, IT_SAME, RF_SAME, MN_MENU), + SGM(GM_APOINT, IN_7, LP_ENA, BL_OFF, LT_SAME), + APOINT(I_OFF, 0, 1000), + SGM(GM_CHAR, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + CHAR('4','0'), CHAR('H','z'), CHAR(' ','S'), CHAR('y','n'), CHAR('c',0), + + ENDSECT + + /* SECTION 3. 3D data, but depth cueing disabled. */ + + LSRBB(ZD_YES, ED_ENA, DQ_OFF, ES_YES), /* but term char not used */ + LSRA(ST_SAME, SI_SAME, LI_BRIGHTDOWN, IT_SAME, RF_30, MN_MAIN), + + SGM(GM_APOINT, IN_4, LP_ENA, BL_OFF, LT_LDASH), + APOINT3(I_OFF, 0200, 0200, 0400), + + SGM(GM_AVECT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + AVECT3(I_ON, 01200, 00200, 0400), + AVECT3(I_ON, 01200, 01200, 0400), + AVECT3(I_ON, 00200, 01200, 0400), + AVECT3(I_ON, 00200, 00200, 0400), + AVECT3(I_OFF, 00600, 00600, -0400), + AVECT3(I_ON, 01600, 00600, -0400), + AVECT3(I_ON, 01600, 01600, -0400), + AVECT3(I_ON, 00600, 01600, -0400), + AVECT3(I_ON, 00600, 00600, -0400), + SGM(GM_AVECT, IN_SAME, LP_SAME, BL_SAME, LT_SOLID), + AVECT3(I_ON, 00200, 00200, 0400), + AVECT3(I_OFF, 01200, 00200, 0400), + AVECT3(I_ON, 01600, 00600, -0400), + AVECT3(I_OFF, 01600, 01600, -0400), + AVECT3(I_ON, 01200, 01200, 0400), + AVECT3(I_OFF, 00200, 01200, 0400), + AVECT3(I_ON, 00600, 01600, -0400), + + LSRA(ST_SAME, SI_SAME, LI_SAME, IT_SAME, RF_SAME, MN_MENU), + SGM(GM_APOINT, IN_7, LP_ENA, BL_OFF, LT_SAME), + APOINT3(I_OFF, 0, 1000, 0200), + SGM(GM_CHAR, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + CHAR('3','0'), CHAR('H','z'), CHAR(' ','S'), CHAR('y','n'), CHAR('c',0), + + ENDSECT + + /* SECTION 4. 3D data, with depth cueing enabled. */ + + LSRBB(ZD_YES, ED_ENA, DQ_ON, ES_YES), /* but term char not used */ + LSRA(ST_SAME, SI_SAME, LI_BRIGHTDOWN, IT_SAME, RF_EXT, MN_MAIN), + + SGM(GM_APOINT, IN_4, LP_ENA, BL_OFF, LT_DDASH), + APOINT3(I_OFF, 0200, 0200, 0400), + + SGM(GM_AVECT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + AVECT3(I_ON, 01200, 00200, 0400), + AVECT3(I_ON, 01200, 01200, 0400), + AVECT3(I_ON, 00200, 01200, 0400), + AVECT3(I_ON, 00200, 00200, 0400), + AVECT3(I_OFF, 00600, 00600, -0400), + AVECT3(I_ON, 01600, 00600, -0400), + AVECT3(I_ON, 01600, 01600, -0400), + AVECT3(I_ON, 00600, 01600, -0400), + AVECT3(I_ON, 00600, 00600, -0400), + SGM(GM_AVECT, IN_SAME, LP_SAME, BL_SAME, LT_SOLID), + AVECT3(I_ON, 00200, 00200, 0400), + AVECT3(I_OFF, 01200, 00200, 0400), + AVECT3(I_ON, 01600, 00600, -0400), + AVECT3(I_OFF, 01600, 01600, -0400), + AVECT3(I_ON, 01200, 01200, 0400), + AVECT3(I_OFF, 00200, 01200, 0400), + AVECT3(I_ON, 00600, 01600, -0400), + + LSRA(ST_SAME, SI_SAME, LI_SAME, IT_SAME, RF_SAME, MN_MENU), + SGM(GM_APOINT, IN_7, LP_ENA, BL_OFF, LT_SAME), + APOINT3(I_OFF, 0, 1000, 0200), + SGM(GM_CHAR, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + CHAR('E','x'), CHAR('t','.'), CHAR(' ','S'), CHAR('y','n'), CHAR('c',0), + + ENDSECT + + /* SECTION 5. Circles and arcs. */ + + SGM(GM_APOINT, IN_4, LP_ENA, BL_ON, LT_SOLID), + APOINT(I_OFF, 0500, 01400), + SGM(GM_ARC, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + ARC(I_ON, -0100, 0, 0, 0), + + SGM(GM_APOINT, IN_5, LP_SAME, BL_OFF, LT_SDASH), + APOINT(I_OFF, 0532, 01532), + SGM(GM_ARC, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + ARC(I_ON, -0132, -0132, 0, -0264), + + SGM(GM_APOINT, IN_6, LP_SAME, BL_SAME, LT_LDASH), + APOINT(I_OFF, 0400, 01700), + SGM(GM_ARC, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + ARC(I_ON, 0, -0300, 0, -0600), + + SGM(GM_APOINT, IN_7, LP_SAME, BL_SAME, LT_DDASH), + APOINT(I_OFF, 0114, 01664), + SGM(GM_ARC, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + ARC(I_ON, 0264, -0264, 0, -0550), + + SGM(GM_APOINT, IN_4, LP_SAME, BL_SAME, LT_SOLID), + APOINT(I_OFF, 01400, 01400), + SGM(GM_ARC, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + ARC(I_ON, 0, 0, 0400, 0), + + SGM(GM_APOINT, IN_SAME, LP_SAME, BL_SAME, LT_SDASH), + APOINT(I_OFF, 0500, 0400), + SGM(GM_ARC, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + ARC(I_ON, -0100, 0, 0200, 0), + + SGM(GM_APOINT, IN_SAME, LP_SAME, BL_SAME, LT_SAME), + APOINT(I_OFF, 01600, 0400), + SGM(GM_ARC, IN_SAME, LP_SAME, BL_SAME, LT_SOLID), + ARC(I_ON, -0200, 0, -0200, 0300), + SGM(GM_ARC, IN_SAME, LP_SAME, BL_SAME, LT_SDASH), + ARC(I_ON, 0, -0300, -0200, -0300), + SGM(GM_ARC, IN_SAME, LP_SAME, BL_SAME, LT_LDASH), + ARC(I_ON, 0200, 0, 0200, -0300), + SGM(GM_ARC, IN_SAME, LP_SAME, BL_SAME, LT_DDASH), + ARC(I_ON, 0, 0300, 0200, 0300), + + ENDSECT + + /* SECTION 6. Display subroutines, with and without parameter restore. */ + + /* XXX need test for subroutines */ + + /* SECTION 7. Offset, vector scale, and clipping. */ + + /* XXX need test for offset, vector scale, and clipping */ + + /* END OF TEST SECTIONS. */ + + ENDFILE +}; + +static unsigned short *df; /* -> start of current display file */ +static uint16 start; /* initial DPC for section of d.file */ +static int more; /* set until end of d.file seen */ + +int +main(void) { + int c; + + vt11_display = TEST_DIS; + vt11_scale = TEST_RES; + + /* VT11/VS60 tests */ + + puts("initial tests work for both VT11 and VS60"); + for (df = VT, start = 0, more = 1; more; ) { + vt11_reset(); /* reset everything */ + vt11_set_dpc(start); /* start section */ + c = 0; + while (vt11_cycle(USEC, 1)) { + display_sync(); /* XXX push down? */ + if (display_lp_sw) /* tip switch activated */ + c = 1; /* flag: break requested */ + if (c && !display_lp_sw) /* wait for switch release */ + break; + } + /* end of section */ + } + /* end of display file */ + + /* light pen tracking */ + + ws_beep(); + puts("move the light pen through the tracking object"); + fflush(stdout); + for (df = LP, start = 0, more = 1; more; ) { + vt11_reset(); /* reset everything */ + vt11_set_dpc(start); /* start section */ + c = 0; + while (vt11_cycle(USEC, 1)) { + display_sync(); /* XXX push down? */ + if (display_lp_sw) /* tip switch activated */ + c = 1; /* flag: break requested */ + if (c && !display_lp_sw) /* wait for switch release */ + break; + /* [dynamic modifications to the display file can be done here] */ + } + /* end of section */ + } + /* end of display file */ + + /* VS60 tests */ + + ws_beep(); + puts("following tests require VS60"); + for (df = VS, start = 0, more = 1; more; ) { + vt11_reset(); /* reset everything */ + vt11_set_str((uint16)(0200 | '~')); /* set terminating char. */ + vt11_set_anr((uint16)(040000 | (2<<12) | 04000 | 01234)); + /* set associative name 0123x */ + vt11_set_dpc(start); /* start section */ + c = 0; + while (vt11_cycle(USEC, 1)) { + display_sync(); /* XXX push down? */ + if (display_lp_sw) /* tip switch activated */ + c = 1; /* flag: break requested */ + if (c && !display_lp_sw) /* wait for switch release */ + break; + } + /* end of section */ + } + /* end of display file */ + + /* XXX would be nice to have an example of animation */ + + return 0; +} + +/* + * callbacks from display.c + */ +unsigned long +cpu_get_switches(void) { + return 0; +} + +void +cpu_set_switches(unsigned long bits) { +} + +/* + * callbacks from vt11.c + */ + +int +vt_fetch(uint32 addr, vt11word *w) { + *w = df[addr/2]; + return 0; +} + +void +vt_stop_intr(void) { + uint16 dpc = vt11_get_dpc(); /* -> just after DSTOP instruction */ + if (df[dpc/2] == 0) { /* ENDSECT */ +#ifdef FRAME1STOP + int c; + puts("end of first pass through this test pattern; display frozen"); + puts("enter newline to refresh this section or EOF to quit"); + fflush(stdout); + while ((c = getchar()) != '\n') + if (c == EOF) + exit(0); /* user aborted test */ +#endif + df[dpc/2 - 1] = JMPA; + df[dpc/2] = start; + start = dpc + 2; /* save start of next section */ + vt11_set_dpc(dpc - 2); /* reset; then JMPA to old start */ + puts("press and release tip switch (mouse button 1) for next display"); + fflush(stdout); + } else /* ENDFILE */ + more = 0; +} + +void +vt_lpen_intr(void) { + if (df == LP) { + int dx = (int)(vt11_get_xpr() & 01777) - 01000; + int dy = (int)(vt11_get_ypr() & 01777) - 01000; + if (dx < 0) + dx = (-dx) | 020000; /* negative */ + if (dy < 0) + dy = (-dy) | 020000; /* negative */ + + df[4] = dx | I_ON; /* visible */ + df[5] = dy; + } else { + printf("VT11 lightpen interrupt (%d,%d)\n", + (int)vt11_get_xpr() & 01777, (int)vt11_get_ypr() & 01777); + fflush(stdout); + } + vt11_set_dpc((uint16)1); /* resume */ +} + +void +vt_char_intr(void) { + puts("VT11 illegal character/timeout interrupt"); + fflush(stdout); + vt11_set_dpc((uint16)1); /* resume */ +} + +void +vt_name_intr(void) { + puts("VS60 name-match interrupt"); + fflush(stdout); + vt11_set_dpc((uint16)1); /* resume */ +} diff --git a/display/win32.c b/display/win32.c new file mode 100644 index 00000000..3eb26802 --- /dev/null +++ b/display/win32.c @@ -0,0 +1,418 @@ +/* + * $Id: win32.c,v 1.38 2004/02/07 06:32:01 phil Exp $ + * Win32 support for XY display simulator + * Phil Budne + * September 2003 + * Revised by Douglas A. Gwyn, 05 Feb. 2004 + */ + +/* + * Copyright (c) 2003-2004, Philip L. Budne + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the names of the authors shall + * not be used in advertising or otherwise to promote the sale, use or + * other dealings in this Software without prior written authorization + * from the authors. + */ + +/* use a thread to handle windows messages; */ +#define THREADS + +/* + * BUGS: + * Does not allow you to close display window; + * would need to tear down both system, and system independent data. + * + * now tries to handle PAINT message, as yet untested!! + */ + +#include +#include +#include +#include "ws.h" +#include "display.h" + +#ifndef PIX_SIZE +#define PIX_SIZE 1 +#endif + +#define APP_CLASS "XYAppClass" +#define APP_MENU "XYAppMenu" /* ?? */ + +/* + * light pen location + * see ws.h for full description + */ +int ws_lp_x = -1; +int ws_lp_y = -1; + +static HWND static_wh; +static HINSTANCE static_inst; +static int xpixels, ypixels; +static char *window_name; +static HBRUSH white_brush; +static HBRUSH black_brush; +#ifdef SWITCH_CURSORS +static HCURSOR cross, arrow; +#endif + +static __inline int +map_key(int k) +{ + switch (k) { + case 186: return ';'; /* VK_OEM_1? */ + case 222: return '\''; /* VK_OEM_7? */ + } + return k; +} + +static void +keydown(int k) +{ + display_keydown(map_key(k)); +} + +static void +keyup(int k) +{ + display_keyup(map_key(k)); +} + +/* + * here on any button click, or if mouse dragged while a button down + */ +static void +mousepos(DWORD lp) +{ + int x, y; + + x = LOWORD(lp); + y = HIWORD(lp); + + /* convert to display coordinates */ +#if PIX_SIZE > 1 + x /= PIX_SIZE; + y /= PIX_SIZE; +#endif + y = ypixels - 1 - y; + + /* if window has been stretched, can get out of range bits!! */ + if (x >= 0 && x < xpixels && y >= 0 && y < ypixels) { + /* checked by display_add_point() */ + ws_lp_x = x; + ws_lp_y = y; + } +} + +/* thoingggg!! "message for you sir!!!" */ +static LRESULT CALLBACK +patsy(HWND wh, UINT msg, WPARAM wp, LPARAM lp) /* "WndProc" */ +{ + /* printf("msg %d\n", msg); */ + switch (msg) { + case WM_DESTROY: + PostQuitMessage(0); + return 0; + + case WM_MOUSEMOVE: + if (wp & (MK_LBUTTON|MK_MBUTTON|MK_RBUTTON)) { +#ifdef SWITCH_CURSORS + if (ws_lp_x == -1 && !display_tablet) + SetCursor(cross); +#endif + mousepos(lp); + } +#ifdef SWITCH_CURSORS + else if (ws_lp_x != -1 && !display_tablet) + SetCursor(arrow); +#endif + break; /* return?? */ + + case WM_LBUTTONDOWN: + display_lp_sw = 1; + case WM_MBUTTONDOWN: + case WM_RBUTTONDOWN: +#ifdef SWITCH_CURSORS + if (!display_tablet) + SetCursor(cross); +#endif + mousepos(lp); + break; /* return?? */ + + case WM_LBUTTONUP: + display_lp_sw = 0; + case WM_MBUTTONUP: + case WM_RBUTTONUP: +#ifdef SWITCH_CURSORS + if (!display_tablet) + SetCursor(arrow); +#endif + ws_lp_x = ws_lp_y = -1; + break; /* return?? */ + + case WM_KEYDOWN: + keydown(wp); + break; + + case WM_KEYUP: + keyup(wp); + break; + + case WM_PAINT: + display_repaint(); + break; /* return?? */ + } + return DefWindowProc(wh, msg, wp, lp); +} + +int +ws_poll(int *valp, int maxus) +{ +#ifdef THREADS + /* msgthread handles window events; just delay simulator */ + if (maxus > 0) + Sleep((maxus+999)/1000); +#else + MSG msg; + DWORD start; + int maxms = (maxus + 999) / 1000; + + for (start = GetTickCount(); GetTickCount() - start < maxms; Sleep(1)) { + /* empty message queue without blocking */ + while (PeekMessage(&msg, NULL, 0, 0, PM_REMOVE)) { + TranslateMessage(&msg); + DispatchMessage(&msg); + } + } +#endif + return 1; +} + +/* called from non-threaded main program */ +int +ws_loop(void (*func)(void *), void *arg) +{ + int val; + while (ws_poll(&val, 0)) + (*func)(arg); + return val; +} + +/* worker for display init */ +static void +ws_init2(void) { + WNDCLASS wc; + int h, w; + +#ifdef SWITCH_CURSORS + if (!display_tablet) { + arrow = LoadCursor(NULL, IDC_ARROW); + cross = LoadCursor(NULL, IDC_CROSS); + } +#endif + + black_brush = GetStockObject(BLACK_BRUSH); + white_brush = GetStockObject(WHITE_BRUSH); + + wc.lpszClassName = APP_CLASS; + wc.lpfnWndProc = patsy; + wc.style = CS_OWNDC | CS_VREDRAW | CS_HREDRAW; + /* also CS_NOCLOSE? CS_SAVEBITS? */ + + wc.hInstance = static_inst = GetModuleHandleA(0); + wc.hIcon = LoadIcon(NULL, IDI_APPLICATION); +#ifdef SWITCH_CURSORS + wc.hCursor = NULL; +#else + wc.hCursor = display_tablet ? NULL : LoadCursor(NULL, IDC_CROSS); +#endif + wc.hbrBackground = black_brush; + wc.lpszMenuName = APP_MENU; + wc.cbClsExtra = 0; + wc.cbWndExtra = 0; + /* WNDCLASSEX/RegisterClassEx include hIconSm (small icon) */ + RegisterClass(&wc); + + /* + * WS_OVERLAPPEDWINDOW=> + * WS_OVERLAPPED, WS_CAPTION, WS_SYSMENU, WS_THICKFRAME, + * WS_MINIMIZEBOX, WS_MAXIMIZEBOX + * + * WS_CHILD (no menu bar), WS_POPUP (mutually exclusive) + */ + + /* empirical crocks to get entire screen; */ + w = (xpixels*PIX_SIZE)+6; + h = (ypixels*PIX_SIZE)+32; + /* XXX -- above values work with XP; Phil had +10,+30 */ + + static_wh = CreateWindow(APP_CLASS, /* registered class name */ + window_name, /* window name */ + WS_OVERLAPPED, /* style */ + CW_USEDEFAULT, CW_USEDEFAULT, /* X,Y */ + w, h, + NULL, /* HWND hWndParent */ + NULL, /* HMENU hMenu */ + static_inst, /* application instance */ + NULL); /* lpParam */ + + ShowWindow(static_wh, SW_SHOW); + UpdateWindow(static_wh); +} + +#ifdef THREADS +static volatile int init_done; +static DWORD msgthread_id; + +static DWORD WINAPI +msgthread(LPVOID arg) +{ + MSG msg; + + ws_init2(); + + /* XXX use a mutex? */ + init_done = 1; + + while (GetMessage(&msg, NULL, 0, 0) > 0) { + TranslateMessage(&msg); + DispatchMessage(&msg); + } + return msg.wParam; +} + +static void +ws_thread_init(void) +{ + HANDLE th = CreateThread(NULL, /* sec. attr. */ + 0, /* stack size */ + msgthread, + NULL, /* param */ + 0, /* flags */ + &msgthread_id); + CloseHandle(th); + + /* XXX use a mutex; don't wait forever!! */ + while (!init_done) + ; +} +#endif /* THREADS */ + +/* called from display layer on first display op */ +int +ws_init(char *name, int xp, int yp, int colors) +{ + xpixels = xp; + ypixels = yp; + window_name = name; + +#ifdef THREADS + ws_thread_init(); +#else + ws_init2(); +#endif + return 1; /* XXX return errors!! */ +} + +void * +ws_color_rgb(int r, int g, int b) +{ + /* XXX check for failure??? try GetNearestColor??? */ + return CreateSolidBrush(RGB(r/256, g/256, b/256)); +} + +void * +ws_color_black(void) +{ + return black_brush; +} + +void * +ws_color_white(void) +{ + return white_brush; +} + +void +ws_display_point(int x, int y, void *color) +{ + HDC dc; + RECT r; + HBRUSH brush = color; + + if (x > xpixels || y > ypixels) + return; + + y = ypixels - 1 - y; /* invert y, top left origin */ + + /* top left corner */ + r.left = x*PIX_SIZE; + r.top = y*PIX_SIZE; + + /* bottom right corner, non-inclusive */ + r.right = (x+1)*PIX_SIZE; + r.bottom = (y+1)*PIX_SIZE; + + if (brush == NULL) + brush = black_brush; + + dc = GetDC(static_wh); + FillRect(dc, &r, brush); + ReleaseDC(static_wh, dc); +} + +void +ws_sync(void) { + /* noop */ +} + +void +ws_beep(void) { +#if 0 + /* play SystemDefault sound; does not work over terminal service */ + MessageBeep(MB_OK); +#else + /* works over terminal service? Plays default sound/beep on Win9x/ME */ + Beep(440, 500); /* Hz, ms. */ +#endif +} + +unsigned long +os_elapsed(void) +{ + static int new; + unsigned long ret; + static DWORD t[2]; + + /* + * only returns milliseconds, but Sleep() + * only takes milliseconds. + * + * wraps after 49.7 days of uptime. + * DWORD is an unsigned long, so this should be OK + */ + t[new] = GetTickCount(); + if (t[!new] == 0) + ret = ~0L; /* +INF */ + else + ret = (t[new] - t[!new]) * 1000; + new = !new; /* Ecclesiastes III */ + return ret; +} diff --git a/display/ws.h b/display/ws.h new file mode 100644 index 00000000..f27cdfa6 --- /dev/null +++ b/display/ws.h @@ -0,0 +1,66 @@ +/* + * $Id: ws.h,v 1.17 2004/02/03 21:23:51 phil Exp $ + * Interfaces to window-system specific code for XY display simulation + */ + +/* + * Copyright (c) 2003-2004, Philip L. Budne + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the names of the authors shall + * not be used in advertising or otherwise to promote the sale, use or + * other dealings in this Software without prior written authorization + * from the authors. + */ + +/* unless you're writing a new driver, you shouldn't be looking here! */ + +extern int ws_init(char *, int, int, int); +extern void ws_close(void); // 2006-07-19 SAI +extern void *ws_color_rgb(int, int, int); +extern void *ws_color_black(void); +extern void *ws_color_white(void); +extern void ws_display_point(int, int, void *); +extern void ws_sync(void); +extern int ws_loop(void (*)(void *), void *); +extern int ws_poll(int *, int); +extern void ws_beep(void); + +/* entries into display.c from below: */ +extern void display_keyup(int); +extern void display_keydown(int); +extern void display_repaint(void); + +/* + * Globals set by O/S display level to SCALED location in display + * coordinate system in order to save an upcall on every mouse + * movement. + * + * *NOT* for consumption by clients of display.c; although display + * clients can now get the scaling factor, real displays only give you + * a light pen "hit" when the beam passes under the light pen. + */ + +extern int ws_lp_x, ws_lp_y; + +/* + * O/S services in theory independent of window system, + * but in (current) practice not! + */ +extern unsigned long os_elapsed(void); diff --git a/display/x11.c b/display/x11.c new file mode 100644 index 00000000..e04709df --- /dev/null +++ b/display/x11.c @@ -0,0 +1,512 @@ +/* + * $Id: x11.c,v 1.29 2004/02/03 21:23:51 phil Exp $ + * X11 support for XY display simulator + * Phil Budne + * September 2003 + * + * Changes from Douglas A. Gwyn, Jan 8, 2004 + * + * started from PDP-8/E simulator (vc8e.c & kc8e.c); + * This PDP8 Emulator was written by Douglas W. Jones at the + * University of Iowa. It is distributed as freeware, of + * uncertain function and uncertain utility. + */ + +/* + * Copyright (c) 2003-2004, Philip L. Budne + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the names of the authors shall + * not be used in advertising or otherwise to promote the sale, use or + * other dealings in this Software without prior written authorization + * from the authors. + */ + +#include +#include +#include +#include "ws.h" +#include "display.h" + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#ifndef PIX_SIZE +#define PIX_SIZE 1 +#endif + +//#define FULL_SCREEN 1 +#define NO_CURSOR 1 +#define NO_BORDER 1 + +/* + * light pen location + * see ws.h for full description + */ +int ws_lp_x = -1; +int ws_lp_y = -1; + +static XtAppContext app_context; /* the topmost context for everything */ +static Display* dpy; /* its display */ +static int scr; /* its screen */ +static Colormap cmap; /* its colormap */ +static Widget crtshell; /* the X window shell */ +static Widget crt; /* the X window in which output will plot */ +static int xpixels, ypixels; +#ifdef FULL_SCREEN +/* occupy entire screen for vintage computer fan Sellam Ismail */ +static int xoffset, yoffset; +#endif + +static GC whiteGC; /* gc with white foreground */ +static GC blackGC; /* gc with black foreground */ +static int buttons = 0; /* tracks state of all buttons */ + +static int os_pollfd(int, int); /* forward */ + +/* here on any mouse button down, AND movement when any button down */ +static void +handle_button_press(w, d, e, b) + Widget w; + XtPointer d; + XEvent *e; + Boolean *b; +{ + int x, y; + + x = e->xbutton.x; + y = e->xbutton.y; +#ifdef FULL_SCREEN + x -= xoffset; + y -= yoffset; +#endif +#if PIX_SIZE > 1 + x *= PIX_SIZE; + y *= PIX_SIZE; +#endif + +#ifndef NO_CURSUR + if (!display_tablet) + /* crosshair cursor to indicate tip of active pen */ + XDefineCursor(dpy, XtWindow(crt), + (Cursor) XCreateFontCursor(dpy, XC_crosshair)); +#endif + + y = ypixels - y - 1; + /*printf("lightpen at %d,%d\n", x, y); fflush(stdout);*/ + ws_lp_x = x; + ws_lp_y = y; + + if (e->type == ButtonPress) { + buttons |= e->xbutton.button; + + if (e->xbutton.button == 1) { + display_lp_sw = 1; + /*printf("tip switch activated\n"); fflush(stdout);*/ + } + } + + if (b) + *b = TRUE; +} + +static void +handle_button_release(w, d, e, b) + Widget w; + XtPointer d; + XEvent *e; + Boolean *b; +{ + if ((buttons &= ~e->xbutton.button) == 0) { /* all buttons released */ +#ifndef NO_CURSOR + if (!display_tablet) + /* pencil cursor (close to a pen!) to indicate inactive pen posn */ + XDefineCursor(dpy, XtWindow(crt), + (Cursor) XCreateFontCursor(dpy, XC_pencil)); +#endif + + /* XXX change cursor back?? */ + ws_lp_x = ws_lp_y = -1; + } + + if (e->xbutton.button == 1) { + display_lp_sw = 0; + /*printf("tip switch deactivated\n"); fflush(stdout);*/ + } + + if (b) + *b = TRUE; +} + +static void +handle_key_press(w, d, e, b) + Widget w; + XtPointer d; + XEvent *e; + Boolean *b; +{ + int shift = (ShiftMask & e->xkey.state) != 0; + KeySym key = XKeycodeToKeysym( dpy, e->xkey.keycode, shift ); + + /*printf("key %d down\n", key); fflush(stdout);*/ + if ((key & 0xff00) == 0) + display_keydown(key); + + if (b) + *b = TRUE; +} + +static void +handle_key_release(w, d, e, b) + Widget w; + XtPointer d; + XEvent *e; + Boolean *b; +{ + int shift = (ShiftMask & e->xkey.state) != 0; + KeySym key = XKeycodeToKeysym( dpy, e->xkey.keycode, shift ); + + /*printf("key %d up\n", key); fflush(stdout);*/ + if ((key & 0xff00) == 0) + display_keyup(key); + + if (b) + *b = TRUE; +} + +static void +handle_exposure(w, d, e, b) + Widget w; + XtPointer d; + XEvent *e; + Boolean *b; +{ + display_repaint(); + + if (b) + *b = TRUE; +} + +int +ws_init(char *crtname, /* crt type name */ + int xp, int yp, /* screen size in pixels */ + int colors) /* colors to support (not used) */ +{ + Arg arg[25]; + XGCValues gcvalues; + unsigned int n; + int argc; + char *argv[1]; + int height, width; + + xpixels = xp; /* save screen size */ + ypixels = yp; + + XtToolkitInitialize(); + app_context = XtCreateApplicationContext(); + argc = 0; + argv[0] = NULL; + dpy = XtOpenDisplay( app_context, NULL, NULL, crtname, NULL, 0, + &argc, argv); + + scr = DefaultScreen(dpy); + + crtshell = XtAppCreateShell( crtname, /* app name */ + crtname, /* app class */ + #ifdef NO_BORDER + overrideShellWidgetClass, + #else + applicationShellWidgetClass, /* wclass */ + #endif + dpy, /* display */ + NULL, /* arglist */ + 0); /* nargs */ + + cmap = DefaultColormap(dpy, scr); + + /* + * Create a drawing area + */ + + n = 0; +#ifdef FULL_SCREEN + /* center raster in full-screen black window */ + width = DisplayWidth(dpy,scr); + height = DisplayHeight(dpy,scr); + + xoffset = (width - xpixels*PIX_SIZE)/2; + yoffset = (height - ypixels*PIX_SIZE)/2; +#else + width = xpixels*PIX_SIZE; + height = ypixels*PIX_SIZE; +#endif + XtSetArg(arg[n], XtNwidth, width); n++; + XtSetArg(arg[n], XtNheight, height); n++; + XtSetArg(arg[n], XtNbackground, BlackPixel( dpy, scr )); n++; + + crt = XtCreateWidget( crtname, widgetClass, crtshell, arg, n); + XtManageChild(crt); + XtPopup(crtshell, XtGrabNonexclusive); + + /* + * Create black and white Graphics Contexts + */ + + gcvalues.foreground = BlackPixel( dpy, scr ); + gcvalues.background = BlackPixel( dpy, scr ); + blackGC = XCreateGC(dpy, XtWindow(crt), + GCForeground | GCBackground, &gcvalues); + + gcvalues.foreground = WhitePixel( dpy, scr ); + whiteGC = XCreateGC(dpy, XtWindow(crt), + GCForeground | GCBackground, &gcvalues); + +#ifndef NO_CURSOR + if (!display_tablet) { + /* pencil cursor */ + XDefineCursor(dpy, XtWindow(crt), + (Cursor) XCreateFontCursor(dpy, XC_pencil)); + } +#endif + + /* + * Setup to handle events + */ + + XtAddEventHandler(crt, ButtonPressMask|ButtonMotionMask, FALSE, + handle_button_press, NULL); + XtAddEventHandler(crt, ButtonReleaseMask, FALSE, + handle_button_release, NULL); + XtAddEventHandler(crt, KeyPressMask, FALSE, + handle_key_press, NULL); + XtAddEventHandler(crt, KeyReleaseMask, FALSE, + handle_key_release, NULL); + XtAddEventHandler(crt, ExposureMask, FALSE, + handle_exposure, NULL); + return 1; +} /* ws_init */ + + +/* Added 2006-07-19 SAI */ + +void ws_close(void) +{ + + XtCloseDisplay(dpy); + +} + + +void * +ws_color_black(void) +{ + return blackGC; +} + +void * +ws_color_white(void) +{ + return whiteGC; +} + +void * +ws_color_rgb(int r, int g, int b) +{ + XColor color; + + color.red = r; + color.green = g; + color.blue = b; + /* ignores flags */ + + if (XAllocColor(dpy, cmap, &color)) { + XGCValues gcvalues; + memset(&gcvalues, 0, sizeof(gcvalues)); + gcvalues.foreground = gcvalues.background = color.pixel; + return XCreateGC(dpy, XtWindow(crt), + GCForeground | GCBackground, + &gcvalues); + } + /* allocation failed */ + return NULL; +} + +/* put a point on the screen */ +void +ws_display_point(int x, int y, void *color) +{ + GC gc = (GC) color; + + if (x > xpixels || y > ypixels) + return; + + y = ypixels - y - 1; /* X11 coordinate system */ + +#ifdef FULL_SCREEN + x += xoffset; + y += yoffset; +#endif + if (gc == NULL) + gc = blackGC; /* default to off */ +#if PIX_SIZE == 1 + XDrawPoint(dpy, XtWindow(crt), gc, x, y); +#else + XFillRectangle(dpy, XtWindow(crt), gc, + x*PIX_SIZE, y*PIX_SIZE, PIX_SIZE, PIX_SIZE); +#endif +} + +void +ws_sync(void) +{ + XFlush(dpy); +} + +/* + * elapsed wall clock time since last call + * +INF on first call + */ + +struct elapsed_state { + struct timeval tvs[2]; + int new; +}; + +static unsigned long +elapsed(struct elapsed_state *ep) +{ + unsigned long val; + + gettimeofday(&ep->tvs[ep->new], NULL); + if (ep->tvs[!ep->new].tv_sec == 0) + val = ~0L; + else + val = ((ep->tvs[ep->new].tv_sec - ep->tvs[!ep->new].tv_sec) * 1000000 + + (ep->tvs[ep->new].tv_usec - ep->tvs[!ep->new].tv_usec)); + ep->new = !ep->new; + return val; +} + +/* called periodically */ +int +ws_poll(int *valp, int maxusec) +{ + static struct elapsed_state es; /* static to avoid clearing! */ + +#ifdef WS_POLL_DEBUG + printf("ws_poll %d\n", maxusec); + fflush(stdout); +#endif + elapsed(&es); /* start clock */ + do { + unsigned long e; + + /* tried checking return, but lost on TCP connections? */ + os_pollfd(ConnectionNumber(dpy), maxusec); + + while (XtAppPending(app_context)) { + XEvent event; + + /* XXX check for connection loss; set *valp? return 0 */ + XtAppNextEvent(app_context, &event ); + XtDispatchEvent( &event ); + } + e = elapsed(&es); +#ifdef WS_POLL_DEBUG + printf(" maxusec %d e %d\r\n", maxusec, e); + fflush(stdout); +#endif + maxusec -= e; + } while (maxusec > 10000); /* 10ms */ + return 1; +} + +/* utility: can be called from main program + * which is willing to cede control + */ +int +ws_loop(void (*func)(void *), void *arg) +{ + int val; + + /* XXX use XtAppAddWorkProc & XtAppMainLoop? */ + while (ws_poll(&val,0)) + (*func)(arg); + return val; +} + +void +ws_beep(void) +{ + XBell(dpy, 0); /* ring at base volume */ + XFlush(dpy); +} + +/**************** + * could move these to unix.c, if VMS versions needed + * (or just (GASP!) ifdef) + */ + +/* public version, used by delay code */ +unsigned long +os_elapsed(void) +{ + static struct elapsed_state es; + return elapsed(&es); +} + +/* + * select/DisplayNumber works on VMS 7.0+? + * could move to "unix.c" + * (I have some nasty VMS code that's supposed to to the job + * for older systems) + */ + +/* + * sleep for maxus microseconds, returning TRUE sooner if fd is readable + * used by X11 driver + */ +static int +os_pollfd(int fd, int maxus) +{ + + /* use trusty old select (most portable) */ + fd_set rfds; + struct timeval tv; + + if (maxus >= 1000000) { /* not bloody likely, avoid divide */ + tv.tv_sec = maxus / 1000000; + tv.tv_usec = maxus % 1000000; + } + else { + tv.tv_sec = 0; + tv.tv_usec = maxus; + } + FD_ZERO(&rfds); + FD_SET(fd, &rfds); + return select(fd+1, &rfds, NULL, NULL, &tv) > 0; +} diff --git a/doc/pdp10_doc.doc b/doc/pdp10_doc.doc index baddd5ff..f85e6dc9 100644 Binary files a/doc/pdp10_doc.doc and b/doc/pdp10_doc.doc differ diff --git a/doc/simh.doc b/doc/simh.doc new file mode 100644 index 00000000..26871b6a --- /dev/null +++ b/doc/simh.doc @@ -0,0 +1,3022 @@ +{\rtf1\adeflang1025\ansi\ansicpg1252\uc1\adeff0\deff0\stshfdbch31505\stshfloch31506\stshfhich31506\stshfbi0\deflang1033\deflangfe1033\themelang1033\themelangfe0\themelangcs0{\fonttbl{\f0\fbidi \froman\fcharset0\fprq2{\*\panose 02020603050405020304}Times New Roman;}{\f1\fbidi \fswiss\fcharset0\fprq2{\*\panose 020b0604020202020204}Arial;} +{\f2\fbidi \fmodern\fcharset0\fprq1{\*\panose 02070309020205020404}Courier New;}{\f3\fbidi \froman\fcharset2\fprq2{\*\panose 05050102010706020507}Symbol;}{\f10\fbidi \fnil\fcharset2\fprq2{\*\panose 05000000000000000000}Wingdings;} +{\f11\fbidi \fmodern\fcharset128\fprq1{\*\panose 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\fswiss\fcharset163\fprq2 Arial (Vietnamese);}{\f60\fbidi \fmodern\fcharset238\fprq1 Courier New CE;}{\f61\fbidi \fmodern\fcharset204\fprq1 Courier New Cyr;} +{\f63\fbidi \fmodern\fcharset161\fprq1 Courier New Greek;}{\f64\fbidi \fmodern\fcharset162\fprq1 Courier New Tur;}{\f65\fbidi \fmodern\fcharset177\fprq1 Courier New (Hebrew);}{\f66\fbidi \fmodern\fcharset178\fprq1 Courier New (Arabic);} +{\f67\fbidi \fmodern\fcharset186\fprq1 Courier New Baltic;}{\f68\fbidi \fmodern\fcharset163\fprq1 Courier New (Vietnamese);}{\f152\fbidi \fmodern\fcharset0\fprq1 MS Mincho Western{\*\falt MS ??};} +{\f150\fbidi \fmodern\fcharset238\fprq1 MS Mincho CE{\*\falt MS ??};}{\f151\fbidi \fmodern\fcharset204\fprq1 MS Mincho Cyr{\*\falt MS ??};}{\f153\fbidi \fmodern\fcharset161\fprq1 MS Mincho Greek{\*\falt MS ??};} +{\f154\fbidi \fmodern\fcharset162\fprq1 MS Mincho Tur{\*\falt MS ??};}{\f157\fbidi \fmodern\fcharset186\fprq1 MS Mincho Baltic{\*\falt MS ??};}{\f380\fbidi \froman\fcharset238\fprq2 Cambria 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Tahoma Baltic;}{\f428\fbidi \fswiss\fcharset163\fprq2 Tahoma (Vietnamese);}{\f429\fbidi \fswiss\fcharset222\fprq2 Tahoma (Thai);} +{\f432\fbidi \fmodern\fcharset0\fprq1 @MS Mincho Western;}{\f430\fbidi \fmodern\fcharset238\fprq1 @MS Mincho CE;}{\f431\fbidi \fmodern\fcharset204\fprq1 @MS Mincho Cyr;}{\f433\fbidi \fmodern\fcharset161\fprq1 @MS Mincho Greek;} +{\f434\fbidi \fmodern\fcharset162\fprq1 @MS Mincho Tur;}{\f437\fbidi \fmodern\fcharset186\fprq1 @MS Mincho Baltic;}{\flomajor\f31508\fbidi \froman\fcharset238\fprq2 Times New Roman CE;} +{\flomajor\f31509\fbidi \froman\fcharset204\fprq2 Times New Roman Cyr;}{\flomajor\f31511\fbidi \froman\fcharset161\fprq2 Times New Roman Greek;}{\flomajor\f31512\fbidi \froman\fcharset162\fprq2 Times New Roman Tur;} +{\flomajor\f31513\fbidi \froman\fcharset177\fprq2 Times New Roman (Hebrew);}{\flomajor\f31514\fbidi \froman\fcharset178\fprq2 Times New Roman (Arabic);}{\flomajor\f31515\fbidi \froman\fcharset186\fprq2 Times New Roman Baltic;} +{\flomajor\f31516\fbidi \froman\fcharset163\fprq2 Times New Roman (Vietnamese);}{\fdbmajor\f31518\fbidi \froman\fcharset238\fprq2 Times New Roman CE;}{\fdbmajor\f31519\fbidi \froman\fcharset204\fprq2 Times New Roman Cyr;} +{\fdbmajor\f31521\fbidi \froman\fcharset161\fprq2 Times New Roman Greek;}{\fdbmajor\f31522\fbidi \froman\fcharset162\fprq2 Times New Roman Tur;}{\fdbmajor\f31523\fbidi \froman\fcharset177\fprq2 Times New Roman (Hebrew);} +{\fdbmajor\f31524\fbidi \froman\fcharset178\fprq2 Times New Roman (Arabic);}{\fdbmajor\f31525\fbidi \froman\fcharset186\fprq2 Times New Roman Baltic;}{\fdbmajor\f31526\fbidi \froman\fcharset163\fprq2 Times New Roman (Vietnamese);} +{\fhimajor\f31528\fbidi \froman\fcharset238\fprq2 Cambria CE;}{\fhimajor\f31529\fbidi \froman\fcharset204\fprq2 Cambria Cyr;}{\fhimajor\f31531\fbidi \froman\fcharset161\fprq2 Cambria Greek;}{\fhimajor\f31532\fbidi \froman\fcharset162\fprq2 Cambria Tur;} +{\fhimajor\f31535\fbidi \froman\fcharset186\fprq2 Cambria Baltic;}{\fhimajor\f31536\fbidi \froman\fcharset163\fprq2 Cambria (Vietnamese);}{\fbimajor\f31538\fbidi \froman\fcharset238\fprq2 Times New Roman CE;} +{\fbimajor\f31539\fbidi \froman\fcharset204\fprq2 Times New Roman Cyr;}{\fbimajor\f31541\fbidi \froman\fcharset161\fprq2 Times New Roman Greek;}{\fbimajor\f31542\fbidi \froman\fcharset162\fprq2 Times New Roman Tur;} +{\fbimajor\f31543\fbidi \froman\fcharset177\fprq2 Times New Roman (Hebrew);}{\fbimajor\f31544\fbidi \froman\fcharset178\fprq2 Times New Roman (Arabic);}{\fbimajor\f31545\fbidi \froman\fcharset186\fprq2 Times New Roman Baltic;} +{\fbimajor\f31546\fbidi \froman\fcharset163\fprq2 Times New Roman (Vietnamese);}{\flominor\f31548\fbidi \froman\fcharset238\fprq2 Times New Roman CE;}{\flominor\f31549\fbidi \froman\fcharset204\fprq2 Times New Roman Cyr;} +{\flominor\f31551\fbidi \froman\fcharset161\fprq2 Times New Roman Greek;}{\flominor\f31552\fbidi \froman\fcharset162\fprq2 Times New Roman Tur;}{\flominor\f31553\fbidi \froman\fcharset177\fprq2 Times New Roman (Hebrew);} +{\flominor\f31554\fbidi \froman\fcharset178\fprq2 Times New Roman (Arabic);}{\flominor\f31555\fbidi \froman\fcharset186\fprq2 Times New Roman Baltic;}{\flominor\f31556\fbidi \froman\fcharset163\fprq2 Times New Roman (Vietnamese);} +{\fdbminor\f31558\fbidi \froman\fcharset238\fprq2 Times New Roman CE;}{\fdbminor\f31559\fbidi \froman\fcharset204\fprq2 Times New Roman Cyr;}{\fdbminor\f31561\fbidi \froman\fcharset161\fprq2 Times New Roman Greek;} +{\fdbminor\f31562\fbidi \froman\fcharset162\fprq2 Times New Roman Tur;}{\fdbminor\f31563\fbidi \froman\fcharset177\fprq2 Times New Roman (Hebrew);}{\fdbminor\f31564\fbidi \froman\fcharset178\fprq2 Times New Roman (Arabic);} +{\fdbminor\f31565\fbidi \froman\fcharset186\fprq2 Times New Roman Baltic;}{\fdbminor\f31566\fbidi \froman\fcharset163\fprq2 Times New Roman (Vietnamese);}{\fhiminor\f31568\fbidi \fswiss\fcharset238\fprq2 Calibri CE;} +{\fhiminor\f31569\fbidi \fswiss\fcharset204\fprq2 Calibri Cyr;}{\fhiminor\f31571\fbidi \fswiss\fcharset161\fprq2 Calibri Greek;}{\fhiminor\f31572\fbidi \fswiss\fcharset162\fprq2 Calibri Tur;} +{\fhiminor\f31575\fbidi \fswiss\fcharset186\fprq2 Calibri Baltic;}{\fhiminor\f31576\fbidi \fswiss\fcharset163\fprq2 Calibri (Vietnamese);}{\fbiminor\f31578\fbidi \froman\fcharset238\fprq2 Times New Roman CE;} +{\fbiminor\f31579\fbidi \froman\fcharset204\fprq2 Times New Roman Cyr;}{\fbiminor\f31581\fbidi \froman\fcharset161\fprq2 Times New Roman Greek;}{\fbiminor\f31582\fbidi \froman\fcharset162\fprq2 Times New Roman Tur;} +{\fbiminor\f31583\fbidi \froman\fcharset177\fprq2 Times New Roman (Hebrew);}{\fbiminor\f31584\fbidi \froman\fcharset178\fprq2 Times New Roman (Arabic);}{\fbiminor\f31585\fbidi \froman\fcharset186\fprq2 Times New Roman Baltic;} +{\fbiminor\f31586\fbidi \froman\fcharset163\fprq2 Times New Roman (Vietnamese);}}{\colortbl;\red0\green0\blue0;\red0\green0\blue255;\red0\green255\blue255;\red0\green255\blue0;\red255\green0\blue255;\red255\green0\blue0;\red255\green255\blue0; +\red255\green255\blue255;\red0\green0\blue128;\red0\green128\blue128;\red0\green128\blue0;\red128\green0\blue128;\red128\green0\blue0;\red128\green128\blue0;\red128\green128\blue128;\red192\green192\blue192;\red163\green21\blue21;}{\*\defchp +\fs22\loch\af31506\hich\af31506\dbch\af31505 }{\*\defpap \ql \li0\ri0\sa200\sl276\slmult1\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0 }\noqfpromote {\stylesheet{ +\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\f0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 \snext0 \sqformat \spriority0 Normal;}{ +\s1\ql \fi-360\li360\ri0\sb240\sa60\keepn\widctlpar\jclisttab\tx360\wrapdefault\faauto\ls1\outlinelevel0\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 +\b\fs28\lang1033\langfe1033\kerning28\loch\f1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 \sbasedon0 \snext0 \slink15 \sqformat heading 1;}{\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar +\jclisttab\tx390\wrapdefault\faauto\ls1\ilvl1\outlinelevel1\adjustright\rin0\lin390\itap0 \rtlch\fcs1 \ab\ai\af1\afs24\alang1025 \ltrch\fcs0 \b\i\fs24\lang1033\langfe1033\loch\f1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 +\sbasedon0 \snext0 \slink16 \sqformat heading 2;}{\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 +\fs24\lang1033\langfe1033\loch\f1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 \sbasedon0 \snext0 \slink17 \sqformat heading 3;}{\*\cs10 \additive Default Paragraph Font;}{\* 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Char;}{\*\cs18 \additive \rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b \sbasedon10 \sqformat Strong;}{\s19\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\fs20\lang1033\langfe1033\loch\f1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 \sbasedon0 \snext19 \slink20 Body Text;}{\*\cs20 \additive \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f0\fs20 +\sbasedon10 \slink19 \slocked \ssemihidden Body Text Char;}{\s21\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs20\alang1025 \ltrch\fcs0 +\fs20\lang1033\langfe1033\loch\f1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 \sbasedon0 \snext21 \slink22 Body Text 2;}{\*\cs22 \additive \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f0\fs20 \sbasedon10 \slink21 \slocked \ssemihidden Body Text 2 Char;}{ +\s23\ql \li0\ri0\sb120\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\ai\af0\afs24\alang1025 \ltrch\fcs0 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\rtlch\fcs1 +\af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\f0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 \sbasedon0 \snext0 \sautoupd toc 5;}{\s28\ql \li1000\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin1000\itap0 \rtlch\fcs1 +\af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\f0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 \sbasedon0 \snext0 \sautoupd toc 6;}{\s29\ql \li1200\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin1200\itap0 \rtlch\fcs1 +\af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\f0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 \sbasedon0 \snext0 \sautoupd toc 7;}{\s30\ql \li1400\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin1400\itap0 \rtlch\fcs1 +\af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\f0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 \sbasedon0 \snext0 \sautoupd toc 8;}{\s31\ql \li1600\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin1600\itap0 \rtlch\fcs1 +\af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\f0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 \sbasedon0 \snext0 \sautoupd toc 9;}{\s32\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \cbpat9 \rtlch\fcs1 +\af38\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\f38\hich\af38\dbch\af31505\cgrid\langnp1033\langfenp1033 \sbasedon0 \snext32 \slink33 Document Map;}{\*\cs33 \additive \rtlch\fcs1 \af38\afs16 \ltrch\fcs0 \f38\fs16 +\sbasedon10 \slink32 \slocked \ssemihidden Document Map Char;}{\s34\ql \li390\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin390\itap0 \rtlch\fcs1 \af1\afs20\alang1025 \ltrch\fcs0 +\fs20\lang1033\langfe1033\loch\f1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 \sbasedon0 \snext34 \slink35 Body Text Indent 2;}{\*\cs35 \additive \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f0\fs20 \sbasedon10 \slink34 \slocked \ssemihidden +Body Text Indent 2 Char;}{\s36\ql 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COPYRIGHT NOTICE +\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \loch\af1\hich\af1\dbch\af11\insrsid4550150 +\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \loch\af1\hich\af1\dbch\af11\insrsid4550150 \hich\af1\dbch\af11\loch\f1 The following copyright notice applies to the SIMH source, binary, and documentation: +\par +\par }\pard \ltrpar\s36\ql \li720\ri962\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin962\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \loch\af1\hich\af1\dbch\af11\insrsid4550150 \hich\af1\dbch\af11\loch\f1 +Original code published in 1993-2008, written by Robert M Supnik +\par \hich\af1\dbch\af11\loch\f1 Copyright (c) 1993-2008, Robert M Supnik +\par +\par \hich\af1\dbch\af11\loch\f1 Permission is hereby grante\hich\af1\dbch\af11\loch\f1 +d, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, +\hich\af1\dbch\af11\loch\f1 s\hich\af1\dbch\af11\loch\f1 ublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: +\par +\par \hich\af1\dbch\af11\loch\f1 The above copyright notice and this permission notice shall be included in all copies or substantial port\hich\af1\dbch\af11\loch\f1 ions of the Software. +\par +\par \hich\af1\dbch\af11\loch\f1 +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ROBERT M SUP +\hich\af1\dbch\af11\loch\f1 NIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +\par \hich\af1\dbch\af11\loch\f1 CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +\par +\par \hich\af1\dbch\af11\loch\f1 Except as contained in this notice, the na\hich\af1\dbch\af11\loch\f1 +me of Robert M Supnik shall not be used in advertising or otherwise to promote the sale, use or other dealings in this Software without prior written authorization from Robert M Supnik. +\par }\pard \ltrpar\s36\ql \li0\ri0\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af2 \ltrch\fcs0 \loch\af1\hich\af1\dbch\af11\insrsid4550150 +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\dbch\af11\insrsid4550150 \page }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par }\pard\plain \ltrpar\s23\ql \li0\ri0\sb120\widctlpar\tx600\tqr\tldot\tx9350\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\ai\af0\afs24\alang1025 \ltrch\fcs0 +\b\i\fs24\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\field\fldedit{\*\fldinst {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 TOC \\o }}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6823027\charrsid14886970 \hich\af0\dbch\af31505\loch\f0 1.}{\rtlch\fcs1 \ab0\ai0\af31507\afs22 \ltrch\fcs0 \b0\i0\f31506\fs22\lang1024\langfe1024\noproof\insrsid6823027 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 Overview\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 \hich\af0\dbch\af31505\loch\f0 +PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc345583809 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340035003500380033003800300039000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 4}}}\sectd \ltrsect +\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\ai0\af31507\afs22 \ltrch\fcs0 \b0\i0\f31506\fs22\lang1024\langfe1024\noproof\insrsid6823027 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027\charrsid14886970 \hich\af0\dbch\af31505\loch\f0 2.}{\rtlch\fcs1 \ab0\ai0\af31507\afs22 \ltrch\fcs0 \b0\i0\f31506\fs22\lang1024\langfe1024\noproof\insrsid6823027 \tab }{\rtlch\fcs1 +\af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 Data Types\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 +\hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc345583810 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340035003500380033003800310030000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 4}}}\sectd \ltrsect +\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\ai0\af31507\afs22 \ltrch\fcs0 \b0\i0\f31506\fs22\lang1024\langfe1024\noproof\insrsid6823027 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027\charrsid14886970 \hich\af0\dbch\af31505\loch\f0 3.}{\rtlch\fcs1 \ab0\ai0\af31507\afs22 \ltrch\fcs0 \b0\i0\f31506\fs22\lang1024\langfe1024\noproof\insrsid6823027 \tab }{\rtlch\fcs1 +\af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 VM Organization\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 +\hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc345583811 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340035003500380033003800310031000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 5}}}\sectd \ltrsect +\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\ai0\af31507\afs22 \ltrch\fcs0 \b0\i0\f31506\fs22\lang1024\langfe1024\noproof\insrsid6823027 +\par }\pard\plain \ltrpar\s24\ql \li200\ri0\sb120\widctlpar\tx800\tqr\tldot\tx9350\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \ab\af0\afs22\alang1025 \ltrch\fcs0 +\b\fs22\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027\charrsid14886970 \hich\af0\dbch\af31505\loch\f0 3.1}{\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 +\b0\f31506\lang1024\langfe1024\noproof\insrsid6823027 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 CPU Organization\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 \hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc345583812 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6823027 {\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340035003500380033003800310032000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 6}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 \b0\f31506\lang1024\langfe1024\noproof\insrsid6823027 +\par }\pard\plain \ltrpar\s25\ql \li400\ri0\widctlpar\tx1200\tqr\tldot\tx9350\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027\charrsid14886970 \hich\af0\dbch\af31505\loch\f0 3.1.1}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid6823027 \tab }{\rtlch\fcs1 \af0 +\ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 Time Base\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 +\hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc345583813 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340035003500380033003800310033000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 6}}}\sectd \ltrsect +\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid6823027 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027\charrsid14886970 \hich\af0\dbch\af31505\loch\f0 3.1.2}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid6823027 \tab }{\rtlch\fcs1 \af0 +\ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 Step Function\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 +\hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc345583814 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340035003500380033003800310034000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 6}}}\sectd \ltrsect +\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid6823027 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027\charrsid14886970 \hich\af0\dbch\af31505\loch\f0 3.1.3}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid6823027 \tab }{\rtlch\fcs1 \af0 +\ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 Memory Organization\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 +\hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc345583815 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340035003500380033003800310035000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 7}}}\sectd \ltrsect +\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid6823027 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027\charrsid14886970 \hich\af0\dbch\af31505\loch\f0 3.1.4}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid6823027 \tab }{\rtlch\fcs1 \af0 +\ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 Interrupt Organization\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 +\hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc345583816 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340035003500380033003800310036000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 7}}}\sectd \ltrsect +\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid6823027 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027\charrsid14886970 \hich\af0\dbch\af31505\loch\f0 3.1.5}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid6823027 \tab }{\rtlch\fcs1 \af0 +\ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 I/O Dispatching\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 +\hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc345583817 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340035003500380033003800310037000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 8}}}\sectd \ltrsect +\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid6823027 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027\charrsid14886970 \hich\af0\dbch\af31505\loch\f0 3.1.6}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid6823027 \tab }{\rtlch\fcs1 \af0 +\ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 Instruction Execution\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 +\hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc345583818 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340035003500380033003800310038000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 8}}}\sectd \ltrsect +\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid6823027 +\par }\pard\plain \ltrpar\s24\ql \li200\ri0\sb120\widctlpar\tx800\tqr\tldot\tx9350\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \ab\af0\afs22\alang1025 \ltrch\fcs0 +\b\fs22\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027\charrsid14886970 \hich\af0\dbch\af31505\loch\f0 3.2}{\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 +\b0\f31506\lang1024\langfe1024\noproof\insrsid6823027 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 Peripheral Device Organization\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 +\ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 \hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc345583819 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6823027 {\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340035003500380033003800310039000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 9}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 \b0\f31506\lang1024\langfe1024\noproof\insrsid6823027 +\par }\pard\plain \ltrpar\s25\ql \li400\ri0\widctlpar\tx1200\tqr\tldot\tx9350\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027\charrsid14886970 \hich\af0\dbch\af31505\loch\f0 3.2.1}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid6823027 \tab }{\rtlch\fcs1 \af0 +\ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 Device Timing\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 +\hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc345583820 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340035003500380033003800320030000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 10}}}\sectd \ltrsect +\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid6823027 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027\charrsid14886970 \hich\af0\dbch\af31505\loch\f0 3.2.2}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid6823027 \tab }{\rtlch\fcs1 \af0 +\ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 Clock Calibration\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 +\hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc345583821 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340035003500380033003800320031000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 11}}}\sectd \ltrsect +\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid6823027 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027\charrsid14886970 \hich\af0\dbch\af31505\loch\f0 3.2.3}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid6823027 \tab }{\rtlch\fcs1 \af0 +\ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 Idling\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 +\hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc345583822 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340035003500380033003800320032000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 11}}}\sectd \ltrsect +\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid6823027 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027\charrsid14886970 \hich\af0\dbch\af31505\loch\f0 3.2.4}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid6823027 \tab }{\rtlch\fcs1 \af0 +\ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 Data I/O\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 +\hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc345583823 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340035003500380033003800320033000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 12}}}\sectd \ltrsect +\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid6823027 +\par }\pard\plain \ltrpar\s23\ql \li0\ri0\sb120\widctlpar\tx600\tqr\tldot\tx9350\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\ai\af0\afs24\alang1025 \ltrch\fcs0 +\b\i\fs24\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027\charrsid14886970 \hich\af0\dbch\af31505\loch\f0 4.}{\rtlch\fcs1 \ab0\ai0\af31507\afs22 +\ltrch\fcs0 \b0\i0\f31506\fs22\lang1024\langfe1024\noproof\insrsid6823027 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 Data Structures\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 +\ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 \hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc345583824 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6823027 {\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340035003500380033003800320034000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 13}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\ai0\af31507\afs22 \ltrch\fcs0 \b0\i0\f31506\fs22\lang1024\langfe1024\noproof\insrsid6823027 +\par }\pard\plain \ltrpar\s24\ql \li200\ri0\sb120\widctlpar\tx800\tqr\tldot\tx9350\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \ab\af0\afs22\alang1025 \ltrch\fcs0 +\b\fs22\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027\charrsid14886970 \hich\af0\dbch\af31505\loch\f0 4.1}{\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 +\b0\f31506\lang1024\langfe1024\noproof\insrsid6823027 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 sim_device Structure\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 \hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc345583825 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6823027 {\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340035003500380033003800320035000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 13}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 \b0\f31506\lang1024\langfe1024\noproof\insrsid6823027 +\par }\pard\plain \ltrpar\s25\ql \li400\ri0\widctlpar\tx1200\tqr\tldot\tx9350\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027\charrsid14886970 \hich\af0\dbch\af31505\loch\f0 4.1.1}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid6823027 \tab }{\rtlch\fcs1 \af0 +\ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 Awidth and Aincr\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 +\hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc345583826 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340035003500380033003800320036000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 15}}}\sectd \ltrsect +\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid6823027 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027\charrsid14886970 \hich\af0\dbch\af31505\loch\f0 4.1.2}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid6823027 \tab }{\rtlch\fcs1 \af0 +\ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 Device Flags\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 +\hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc345583827 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340035003500380033003800320037000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 15}}}\sectd \ltrsect +\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid6823027 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027\charrsid14886970 \hich\af0\dbch\af31505\loch\f0 4.1.3}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid6823027 \tab }{\rtlch\fcs1 \af0 +\ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 Context\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 +\hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _T\hich\af0\dbch\af31505\loch\f0 oc345583828 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340035003500380033003800320038000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 15}}}\sectd \ltrsect +\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid6823027 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027\charrsid14886970 \hich\af0\dbch\af31505\loch\f0 4.1.4}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid6823027 \tab }{\rtlch\fcs1 \af0 +\ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 Examine and Deposit Routines\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 +\hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc345583829 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340035003500380033003800320039000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 15}}}\sectd \ltrsect +\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid6823027 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027\charrsid14886970 \hich\af0\dbch\af31505\loch\f0 4.1.5}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid6823027 \tab }{\rtlch\fcs1 \af0 +\ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 Reset Routine\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 +\hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc345583830 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340035003500380033003800330030000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 16}}}\sectd \ltrsect +\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid6823027 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027\charrsid14886970 \hich\af0\dbch\af31505\loch\f0 4.1.6}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid6823027 \tab }{\rtlch\fcs1 \af0 +\ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 Boot Routine\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 +\hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc345583831 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340035003500380033003800330031000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 16}}}\sectd \ltrsect +\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid6823027 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027\charrsid14886970 \hich\af0\dbch\af31505\loch\f0 4.1.7}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid6823027 \tab }{\rtlch\fcs1 \af0 +\ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 Attach and Detach Routines\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 +\hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc345583832 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340035003500380033003800330032000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 16}}}\sectd \ltrsect +\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid6823027 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027\charrsid14886970 \hich\af0\dbch\af31505\loch\f0 4.1.\hich\af0\dbch\af31505\loch\f0 8}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 +\f31506\fs22\lang1024\langfe1024\noproof\insrsid6823027 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 Memory Size Change Routine\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 +\ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 \hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc345583833 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6823027 {\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340035003500380033003800330033000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 17}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid6823027 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027\charrsid14886970 \hich\af0\dbch\af31505\loch\f0 4.1.9}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid6823027 \tab }{\rtlch\fcs1 \af0 +\ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 Debug Controls\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 +\hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc345583834 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340035003500380033003800330034000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 17}}}\sectd \ltrsect +\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid6823027 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027\charrsid14886970 \hich\af0\dbch\af31505\loch\f0 4.1.10}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid6823027 \tab }{\rtlch\fcs1 \af0 +\ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 Device Specific Help support\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 +\hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc345583835 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340035003500380033003800330035000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 18}}}\sectd \ltrsect +\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid6823027 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027\charrsid14886970 \hich\af0\dbch\af31505\loch\f0 4.1.11}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid6823027 \tab }{\rtlch\fcs1 \af0 +\ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 Help Routine\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 +\hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc345583836 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340035003500380033003800330036000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 18}}}\sectd \ltrsect +\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid6823027 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027\charrsid14886970 \hich\af0\dbch\af31505\loch\f0 4.1.12}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid6823027 \tab }{\rtlch\fcs1 \af0 +\ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 Attach Help Routine\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 +\hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc345583837 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340035003500380033003800330037000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 19}}}\sectd \ltrsect +\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid6823027 +\par }\pard\plain \ltrpar\s24\ql \li200\ri0\sb120\widctlpar\tx800\tqr\tldot\tx9350\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \ab\af0\afs22\alang1025 \ltrch\fcs0 +\b\fs22\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027\charrsid14886970 \hich\af0\dbch\af31505\loch\f0 4.2}{\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 +\b0\f31506\lang1024\langfe1024\noproof\insrsid6823027 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 sim_unit Structure\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 \hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc345583838 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6823027 {\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340035003500380033003800330038000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 19}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 \b0\f31506\lang1024\langfe1024\noproof\insrsid6823027 +\par }\pard\plain \ltrpar\s25\ql \li400\ri0\widctlpar\tx1200\tqr\tldot\tx9350\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027\charrsid14886970 \hich\af0\dbch\af31505\loch\f0 4.2.1}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid6823027 \tab }{\rtlch\fcs1 \af0 +\ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 Unit Flags\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 +\hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc345583839 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340035003500380033003800330039000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 20}}}\sectd \ltrsect +\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid6823027 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027\charrsid14886970 \hich\af0\dbch\af31505\loch\f0 4.2.2}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid6823027 \tab }{\rtlch\fcs1 \af0 +\ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 Service Routine\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 +\hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc345583840 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340035003500380033003800340030000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 20}}}\sectd \ltrsect +\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid6823027 +\par }\pard\plain \ltrpar\s24\ql \li200\ri0\sb120\widctlpar\tx800\tqr\tldot\tx9350\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \ab\af0\afs22\alang1025 \ltrch\fcs0 +\b\fs22\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027\charrsid14886970 \hich\af0\dbch\af31505\loch\f0 4.3}{\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 +\b0\f31506\lang1024\langfe1024\noproof\insrsid6823027 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 sim_reg Structure\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 \hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc345583841 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6823027 {\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340035003500380033003800340031000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 20}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 \b0\f31506\lang1024\langfe1024\noproof\insrsid6823027 +\par }\pard\plain \ltrpar\s25\ql \li400\ri0\widctlpar\tx1200\tqr\tldot\tx9350\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027\charrsid14886970 \hich\af0\dbch\af31505\loch\f0 4.3.1}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid6823027 \tab }{\rtlch\fcs1 \af0 +\ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 Register Flags\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 +\hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _\hich\af0\dbch\af31505\loch\f0 Toc345583842 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340035003500380033003800340032000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 22}}}\sectd \ltrsect +\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid6823027 +\par }\pard\plain \ltrpar\s24\ql \li200\ri0\sb120\widctlpar\tx800\tqr\tldot\tx9350\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \ab\af0\afs22\alang1025 \ltrch\fcs0 +\b\fs22\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027\charrsid14886970 \hich\af0\dbch\af31505\loch\f0 4.4}{\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 +\b0\f31506\lang1024\langfe1024\noproof\insrsid6823027 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 sim_mtab Structure\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 \hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc345583843 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6823027 {\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340035003500380033003800340033000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 22}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 \b0\f31506\lang1024\langfe1024\noproof\insrsid6823027 +\par }\pard\plain \ltrpar\s25\ql \li400\ri0\widctlpar\tx1200\tqr\tldot\tx9350\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027\charrsid14886970 \hich\af0\dbch\af31505\loch\f0 4.4.1}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid6823027 \tab }{\rtlch\fcs1 \af0 +\ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 Validation Routine\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 +\hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc345583844 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340035003500380033003800340034000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 24}}}\sectd \ltrsect +\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid6823027 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027\charrsid14886970 \hich\af0\dbch\af31505\loch\f0 4.4.2}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid6823027 \tab }{\rtlch\fcs1 \af0 +\ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 Display Routine\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 +\hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc345583845 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340035003500380033003800340035000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 24}}}\sectd \ltrsect +\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid6823027 +\par }\pard\plain \ltrpar\s24\ql \li200\ri0\sb120\widctlpar\tx800\tqr\tldot\tx9350\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \ab\af0\afs22\alang1025 \ltrch\fcs0 +\b\fs22\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027\charrsid14886970 \hich\af0\dbch\af31505\loch\f0 4.5}{\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 +\b0\f31506\lang1024\langfe1024\noproof\insrsid6823027 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 Other Data Structures\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 \hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc345583846 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6823027 {\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340035003500380033003800340036000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 24}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 \b0\f31506\lang1024\langfe1024\noproof\insrsid6823027 +\par }\pard\plain \ltrpar\s23\ql \li0\ri0\sb120\widctlpar\tx600\tqr\tldot\tx9350\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\ai\af0\afs24\alang1025 \ltrch\fcs0 +\b\i\fs24\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027\charrsid14886970 \hich\af0\dbch\af31505\loch\f0 5.}{\rtlch\fcs1 \ab0\ai0\af31507\afs22 +\ltrch\fcs0 \b0\i0\f31506\fs22\lang1024\langfe1024\noproof\insrsid6823027 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 VM Provided \hich\af0\dbch\af31505\loch\f0 Routines\tab } +{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 \hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc345583847 \\h\hich\af0\dbch\af31505\loch\f0 }{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 {\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340035003500380033003800340037000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 25}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\ai0\af31507\afs22 \ltrch\fcs0 \b0\i0\f31506\fs22\lang1024\langfe1024\noproof\insrsid6823027 +\par }\pard\plain \ltrpar\s24\ql \li200\ri0\sb120\widctlpar\tx800\tqr\tldot\tx9350\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \ab\af0\afs22\alang1025 \ltrch\fcs0 +\b\fs22\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027\charrsid14886970 \hich\af0\dbch\af31505\loch\f0 5.1}{\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 +\b0\f31506\lang1024\langfe1024\noproof\insrsid6823027 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 Instruction Execution\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 \hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc345583848 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6823027 {\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340035003500380033003800340038000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 25}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 \b0\f31506\lang1024\langfe1024\noproof\insrsid6823027 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027\charrsid14886970 \hich\af0\dbch\af31505\loch\f0 5.2}{\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 \b0\f31506\lang1024\langfe1024\noproof\insrsid6823027 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 Binary Load and Dump\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 +\hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc345583849 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340035003500380033003800340039000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 25}}}\sectd \ltrsect +\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 \b0\f31506\lang1024\langfe1024\noproof\insrsid6823027 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027\charrsid14886970 \hich\af0\dbch\af31505\loch\f0 5.3}{\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 \b0\f31506\lang1024\langfe1024\noproof\insrsid6823027 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 Symbolic Examination and Deposit\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 +\hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc345583850 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340035003500380033003800350030000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 25}}}\sectd \ltrsect +\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 \b0\f31506\lang1024\langfe1024\noproof\insrsid6823027 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027\charrsid14886970 \hich\af0\dbch\af31505\loch\f0 5.4}{\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 \b0\f31506\lang1024\langfe1024\noproof\insrsid6823027 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 Optional Interfaces\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 +\hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc345583851 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340035003500380033003800350031000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 26}}}\sectd \ltrsect +\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 \b0\f31506\lang1024\langfe1024\noproof\insrsid6823027 +\par }\pard\plain \ltrpar\s25\ql \li400\ri0\widctlpar\tx1200\tqr\tldot\tx9350\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027\charrsid14886970 \hich\af0\dbch\af31505\loch\f0 5.4.1}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid6823027 \tab }{\rtlch\fcs1 \af0 +\ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 Once Only Initialization Routine\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 +\hich\af0\dbch\af31505\loch\f0 \hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc345583852 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340035003500380033003800350032000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 26}}}\sectd \ltrsect +\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid6823027 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027\charrsid14886970 \hich\af0\dbch\af31505\loch\f0 5.4.2}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid6823027 \tab }{\rtlch\fcs1 \af0 +\ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 Address Input and Display\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 +\hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc345583853 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340035003500380033003800350033000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 26}}}\sectd \ltrsect +\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid6823027 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027\charrsid14886970 \hich\af0\dbch\af31505\loch\f0 5.4.3}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid6823027 \tab }{\rtlch\fcs1 \af0 +\ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 Command Input and Post-Processing\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 +\hich\af0\dbch\af31505\loch\f0 \hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc345583854 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340035003500380033003800350034000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 27}}}\sectd \ltrsect +\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid6823027 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027\charrsid14886970 \hich\af0\dbch\af31505\loch\f0 5.4.4}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid6823027 \tab }{\rtlch\fcs1 \af0 +\ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 VM-Specific Commands\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 +\hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc345583855 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340035003500380033003800350035000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 27}}}\sectd \ltrsect +\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid6823027 +\par }\pard\plain \ltrpar\s23\ql \li0\ri0\sb120\widctlpar\tx600\tqr\tldot\tx9350\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\ai\af0\afs24\alang1025 \ltrch\fcs0 +\b\i\fs24\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027\charrsid14886970 \hich\af0\dbch\af31505\loch\f0 6.}{\rtlch\fcs1 \ab0\ai0\af31507\afs22 +\ltrch\fcs0 \b0\i0\f31506\fs22\lang1024\langfe1024\noproof\insrsid6823027 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 Other SCP Facilities\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 +\af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 \hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc345583856 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6823027 {\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340035003500380033003800350036000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 28}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\ai0\af31507\afs22 \ltrch\fcs0 \b0\i0\f31506\fs22\lang1024\langfe1024\noproof\insrsid6823027 +\par }\pard\plain \ltrpar\s24\ql \li200\ri0\sb120\widctlpar\tx800\tqr\tldot\tx9350\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \ab\af0\afs22\alang1025 \ltrch\fcs0 +\b\fs22\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027\charrsid14886970 \hich\af0\dbch\af31505\loch\f0 6.1}{\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 +\b0\f31506\lang1024\langfe1024\noproof\insrsid6823027 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 Terminal Input/Output Formatting Library\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 +\af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 \hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc345583857 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6823027 {\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340035003500380033003800350037000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 28}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 \b0\f31506\lang1024\langfe1024\noproof\insrsid6823027 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027\charrsid14886970 \hich\af0\dbch\af31505\loch\f0 6.2}{\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 \b0\f31506\lang1024\langfe1024\noproof\insrsid6823027 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 Terminal Multiplexer Emulation Library\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 +\hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc345583858 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340035003500380033003800350038000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 28}}}\sectd \ltrsect +\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 \b0\f31506\lang1024\langfe1024\noproof\insrsid6823027 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027\charrsid14886970 \hich\af0\dbch\af31505\loch\f0 6.3}{\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 \b0\f31506\lang1024\langfe1024\noproof\insrsid6823027 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 Magnetic Tape Emulatio\hich\af0\dbch\af31505\loch\f0 n Library\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 +\hich\af0\dbch\af31505\loch\f0 \hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc345583859 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340035003500380033003800350039000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 33}}}\sectd \ltrsect +\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 \b0\f31506\lang1024\langfe1024\noproof\insrsid6823027 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027\charrsid14886970 \hich\af0\dbch\af31505\loch\f0 6.4}{\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 \b0\f31506\lang1024\langfe1024\noproof\insrsid6823027 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 Disk Emulation Library\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 +\hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc345583860 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340035003500380033003800360030000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 35}}}\sectd \ltrsect +\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 \b0\f31506\lang1024\langfe1024\noproof\insrsid6823027 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027\charrsid14886970 \hich\af0\dbch\af31505\loch\f0 6.5}{\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 \b0\f31506\lang1024\langfe1024\noproof\insrsid6823027 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 Breakpoint Support\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 +\hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc345583861 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340035003500380033003800360031000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6823027 \hich\af0\dbch\af31505\loch\f0 37}}}\sectd \ltrsect +\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 \b0\f31506\lang1024\langfe1024\noproof\insrsid6823027 +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 }}\pard\plain \ltrpar +\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 \sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj +{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par \page +\par {\*\bkmkstart _Toc345583809}{\listtext\pard\plain\ltrpar \s1 \rtlch\fcs1 \ab\af0\afs28 \ltrch\fcs0 \b\f1\fs28\kerning28\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 1.\tab}}\pard\plain \ltrpar\s1\ql \fi-360\li360\ri0\sb240\sa60\keepn\widctlpar +\jclisttab\tx360\wrapdefault\faauto\ls1\outlinelevel0\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 \b\fs28\lang1033\langfe1033\kerning28\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Overview{\*\bkmkend _Toc345583809} +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 SIMH (history simulators) is a set of portable programs, writt\hich\af1\dbch\af31505\loch\f1 +en in C, which simulate various historically interesting computers. This document describes how to design, write, and check out a new simulator for SIMH. It is not an introduction to either the philosophy or external operation of SIMH, and the reader sh +\hich\af1\dbch\af31505\loch\f1 o\hich\af1\dbch\af31505\loch\f1 +uld be familiar with both of those topics before proceeding. Nor is it a guide to the internal design or operation of SIMH, except insofar as those areas interact with simulator design. Instead, this manual presents and explains the form, meaning, and o +\hich\af1\dbch\af31505\loch\f1 p\hich\af1\dbch\af31505\loch\f1 +eration of the interfaces between simulators and the SIMH simulator control package. It also offers some suggestions for utilizing the services SIMH offers and explains the constraints that all simulators operating within SIMH will experience. +\par +\par \hich\af1\dbch\af31505\loch\f1 Some termi\hich\af1\dbch\af31505\loch\f1 nology: Each simulator consists of a standard }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 simulator control package}{\rtlch\fcs1 \af1 +\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (SCP and related libraries), which provides a control framework and utility routines for a simulator; and a unique }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 virtual machine}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (VM), which implements the simulated processor and se\hich\af1\dbch\af31505\loch\f1 +lected peripherals. A VM consists of multiple }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 devices}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 +, such as the CPU, paper tape reader, disk controller, etc. Each controller consists of a named state space (called }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 registers}{\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 ) and one or more }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 units}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 +. Each unit consists of a numbered state space (call\hich\af1\dbch\af31505\loch\f1 ed a }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 data set}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 ). }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 The }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 +\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 host computer}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 is the system on which SIMH runs; the }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 target computer}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 is the system being simulated. +\par +\par \hich\af1\dbch\af31505\loch\f1 SIMH is unabashedly based on the MIMIC simulation system, designed in the late 1960\hich\f1 \rquote \loch\f1 s by Len Fehskens, Mike McCarthy, and Bob Supnik. \hich\af1\dbch\af31505\loch\f1 This document is based on MIMIC +\hich\f1 \rquote \loch\f1 \hich\f1 s published interface specification, \'93\loch\f1 \hich\f1 How to Write a Virtual Machine for the MIMIC Simulation System\'94\loch\f1 , by Len Fehskens and Bob Supnik. +\par +\par {\*\bkmkstart _Toc345583810}{\listtext\pard\plain\ltrpar \s1 \rtlch\fcs1 \ab\af0\afs28 \ltrch\fcs0 \b\f1\fs28\kerning28\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 2.\tab}}\pard\plain \ltrpar\s1\ql \fi-360\li360\ri0\sb240\sa60\keepn\widctlpar +\jclisttab\tx360\wrapdefault\faauto\ls1\outlinelevel0\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 \b\fs28\lang1033\langfe1033\kerning28\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Data Types{\*\bkmkend _Toc345583810} +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 SIMH is written in C. The host system must su\hich\af1\dbch\af31505\loch\f1 +pport (at least) 32-bit data types (64-bit data types for the PDP-10 and other large-word target systems). To cope with the vagaries of C data types, SIMH defines some unambiguous data types for its interfaces: +\par +\par \tab \hich\af1\dbch\af31505\loch\f1 SIMH data type\tab \tab \tab interpretation in typical\hich\af1\dbch\af31505\loch\f1 32-bit C +\par +\par \tab \hich\af1\dbch\af31505\loch\f1 int8, uint8\tab \tab \tab signed char, unsigned char +\par \tab \hich\af1\dbch\af31505\loch\f1 int16, uint16\tab \tab \tab signed short, unsigned short +\par \tab \hich\af1\dbch\af31505\loch\f1 int32, uint32\tab \tab \tab signed int, unsigned int +\par \tab \hich\af1\dbch\af31505\loch\f1 t_int64, t_uint64\tab \tab \tab long long, _int64 (system specific) +\par \tab \hich\af1\dbch\af31505\loch\f1 t_addr\tab \tab \tab \tab simulated address, uint32 or t_uint64 +\par \tab \hich\af1\dbch\af31505\loch\f1 t_value\tab \tab \tab \tab \hich\af1\dbch\af31505\loch\f1 simulated value, uint32 or t_uint64 +\par \tab \hich\af1\dbch\af31505\loch\f1 t_svalue\tab \tab \tab simulated signed value, int32 or t_int64 +\par \tab \hich\af1\dbch\af31505\loch\f1 t_mtrec\tab \tab \tab \tab mag tape record length, uint32 +\par \tab \hich\af1\dbch\af31505\loch\f1 t_stat\tab \tab \tab \tab status code, int +\par \tab \hich\af1\dbch\af31505\loch\f1 t_bool\tab \tab \tab \tab true/false value, int +\par +\par \hich\af1\dbch\af31505\loch\f1 [The inconsistency in naming t_int64 and t_uint64 is due to\hich\af1\dbch\af31505\loch\f1 Microsoft VC++, which uses int64 as a structure name member in the master Windows definitions file.] +\par +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\outlinelevel0\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 In addition, SIMH defines structures for each of its major data elements: + +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 DEVICE}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \tab \hich\af1\dbch\af31505\loch\f1 device definition structure +\par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 UNIT}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \tab \tab \hich\af1\dbch\af31505\loch\f1 unit definition structure +\par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 REG}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \tab \tab \hich\af1\dbch\af31505\loch\f1 register definition structure +\par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 MTAB}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \tab \tab \hich\af1\dbch\af31505\loch\f1 modifier definition structure +\par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 CTAB}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \tab \tab \hich\af1\dbch\af31505\loch\f1 command definition structure +\par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 DEBTAB}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \tab \hich\af1\dbch\af31505\loch\f1 debug table entry structure +\par +\par {\*\bkmkstart _Toc345583811}{\listtext\pard\plain\ltrpar \s1 \rtlch\fcs1 \ab\af0\afs28 \ltrch\fcs0 \b\f1\fs28\kerning28\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 3.\tab}}\pard\plain \ltrpar\s1\ql \fi-360\li360\ri0\sb240\sa60\keepn\widctlpar +\jclisttab\tx360\wrapdefault\faauto\ls1\outlinelevel0\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 \b\fs28\lang1033\langfe1033\kerning28\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 VM Organization{\*\bkmkend _Toc345583811} +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 A virtual machine (VM) is a collection of devices bound toget\hich\af1\dbch\af31505\loch\f1 +her through their internal logic. Each device is named and corresponds more or less to a hunk of hardware on the real machine; for example: +\par +\par \tab \hich\af1\dbch\af31505\loch\f1 VM device\tab \tab \tab Real machine hardware +\par +\par \tab \hich\af1\dbch\af31505\loch\f1 CPU\tab \tab \tab \tab central processor and main memory +\par \tab \hich\af1\dbch\af31505\loch\f1 PTR\tab \tab \tab \tab paper tape reader controller\hich\af1\dbch\af31505\loch\f1 and paper tape reader +\par \tab \hich\af1\dbch\af31505\loch\f1 TTI\tab \tab \tab \tab console keyboard +\par \tab \hich\af1\dbch\af31505\loch\f1 TTO\tab \tab \tab \tab console output +\par \tab \hich\af1\dbch\af31505\loch\f1 DKP\tab \tab \tab \tab disk pack controller and drives +\par +\par \hich\af1\dbch\af31505\loch\f1 There may be more than one device per physical hardware entity, as for the console; but for each user-accessible device there must be at least o\hich\af1\dbch\af31505\loch\f1 +ne. One of these devices will have the pre-eminent responsibility for directing simulated operations. Normally, this is the CPU, but it could be a higher-level entity, such as a bus master. +\par +\par \hich\af1\dbch\af31505\loch\f1 The VM actually runs as a subroutine of the simulator control p\hich\af1\dbch\af31505\loch\f1 ackage (SCP). It provides a master routine for running simulated programs and other routines and data structures to implement SCP +\hich\f1 \rquote \loch\f1 s command and control functions. The interfaces between a VM and SCP are relatively few: +\par +\par \tab \hich\af1\dbch\af31505\loch\f1 Interface\tab \tab \tab Function +\par +\par \tab \hich\af1\dbch\af31505\loch\f1 char }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_n\hich\af1\dbch\af31505\loch\f1 ame[]}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab +\hich\af1\dbch\af31505\loch\f1 simulator name string +\par \tab \hich\af1\dbch\af31505\loch\f1 REG *}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_pc}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \tab \hich\af1\dbch\af31505\loch\f1 +pointer to simulated program counter +\par \tab \hich\af1\dbch\af31505\loch\f1 int32 }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_emax}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 +maximum number of words in an instruction +\par \tab \hich\af1\dbch\af31505\loch\f1 DEVICE *}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_devices[]}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 +table of pointers to simulated devices, NULL terminated +\par \tab \hich\af1\dbch\af31505\loch\f1 char *}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_stop_messages[]}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 table of p +\hich\af1\dbch\af31505\loch\f1 ointers to error messages +\par \tab \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_load}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 \hich\f1 (\'85\loch\f1 )\tab \tab +binary loader subroutine +\par \tab \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_inst}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (void)\tab \tab +instruction execution subroutine +\par \tab \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 parse_sym}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 \hich\f1 (\'85\loch\f1 )\tab \tab +symbolic instruction parse subroutine +\par \tab \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 fprint_sym}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 \hich\f1 (\'85\loch\f1 )\tab \tab +symbolic instruction print subroutine +\par +\par \hich\af1\dbch\af31505\loch\f1 In addition, there are six optional interfaces, which can be used for special situations, such as GUI implementations: +\par +\par \tab \hich\af1\dbch\af31505\loch\f1 Interface\tab \tab \tab \tab Function +\par +\par \tab \hich\af1\dbch\af31505\loch\f1 void (*}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_vm_init}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 ) (void)\tab \tab +pointer to once-only initialization routine for VM +\par \tab \hich\af1\dbch\af31505\loch\f1 t_addr (*}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_vm_parse_addr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 \hich\f1 ) (\'85\loch\f1 ) +\tab \hich\af1\dbch\af31505\loch\f1 pointer to address parsing routine +\par \tab \hich\af1\dbch\af31505\loch\f1 void (*}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_vm_fprint_addr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 \hich\f1 ) (\'85\loch\f1 ) +\tab pointer to address output routine +\par \tab \hich\af1\dbch\af31505\loch\f1 char (}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 *sim_vm_read}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 \hich\f1 ) (\'85\loch\f1 )\tab +\tab pointer to command input routine +\par \tab \hich\af1\dbch\af31505\loch\f1 void (*}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_vm_post}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 \hich\f1 ) (\'85\loch\f1 )\tab +\tab pointer to command post-processing routine +\par \tab \hich\af1\dbch\af31505\loch\f1 CTAB }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 *sim_vm_cmd}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \tab \hich\af1\dbch\af31505\loch\f1 pointe +\hich\af1\dbch\af31505\loch\f1 r to simulator-specific command table +\par +\par \hich\af1\dbch\af31505\loch\f1 There is no required organization for VM code. The following convention has been used so far. Let name be the }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 name}{\rtlch\fcs1 \af1 +\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 of the real system (i1401 for the IBM 1401; i1620 for the IBM 1620; pdp1 for the PDP-1; pdp18b for t\hich\af1\dbch\af31505\loch\f1 he other 18-bit PDP\hich\f1 \rquote \loch\f1 +s; pdp8 for the PDP-8; pdp11 for the PDP-11; nova for Nova; hp2100 for the HP 21XX; h316 for the Honeywell 315/516; gri for the GRI-909; pdp10 for the PDP-10; vax for the VAX; sds for the SDS-940): +\par +\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \ai\af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 name}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 .h contains definitions for th\hich\af1\dbch\af31505\loch\f1 e particular simulator +\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \ai\af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 name}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 _sys.c contains all the SCP interfaces except the instruction simulator +\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \ai\af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 name}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 _cpu.c contains the instruction simulator and CPU data structures +\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \ai\af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 name}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 _stddev.c contains the peripherals which were standard with the real syste\hich\af1\dbch\af31505\loch\f1 m. +\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \ai\af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 name}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 _lp.c contains the line printer. +\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \ai\af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 name}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 _mt.c contains the mag tape controller and drives, etc. +\par }\pard \ltrpar\ql \fi1440\li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 The SIMH standard definitions are in sim_defs.h. The base components of SIMH are: +\par +\par \tab \hich\af1\dbch\af31505\loch\f1 Source module\tab \tab header file\tab \tab module +\par +\par \tab \hich\af1\dbch\af31505\loch\f1 scp.c\tab \tab \tab scp.h\tab \tab \tab \hich\af1\dbch\af31505\loch\f1 control package +\par \tab \hich\af1\dbch\af31505\loch\f1 sim_console.c\tab \tab sim_console.h\tab \tab terminal I/O library +\par \tab \hich\af1\dbch\af31505\loch\f1 sim_fio.c\tab \tab sim_fio.h\tab \tab file I/O library +\par \tab \hich\af1\dbch\af31505\loch\f1 sim_timer.c\tab \tab sim_timer.h\tab \tab timer library +\par \tab \hich\af1\dbch\af31505\loch\f1 sim_sock.c\tab \tab sim_sock.h\tab \tab socket I/O library +\par \tab \hich\af1\dbch\af31505\loch\f1 sim_ether.c\tab \tab sim_ether.h\tab \tab Ethernet I/O library +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0\pararsid399520 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid399520 \tab \hich\af1\dbch\af31505\loch\f1 sim_\hich\af1\dbch\af31505\loch\f1 serial.c\tab \tab sim_serial +\hich\af1\dbch\af31505\loch\f1 .h\tab \tab \hich\af1\dbch\af31505\loch\f1 Serial Port \hich\af1\dbch\af31505\loch\f1 I/O library +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 sim_tmxr.c\tab \tab si\hich\af1\dbch\af31505\loch\f1 m_tmxr.h\tab \tab +terminal multiplexer simulation library +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0\pararsid399520 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid399520 \tab \hich\af1\dbch\af31505\loch\f1 sim_\hich\af1\dbch\af31505\loch\f1 disk\hich\af1\dbch\af31505\loch\f1 .c +\tab \tab si\hich\af1\dbch\af31505\loch\f1 m_\hich\af1\dbch\af31505\loch\f1 disk\hich\af1\dbch\af31505\loch\f1 .h\tab \tab \hich\af1\dbch\af31505\loch\f1 disk simulation library +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 sim_tape.c\tab \tab sim_tape.h\tab \tab magtape simulation library +\par {\*\bkmkstart _Toc345583812}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 3.1\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar +\jclisttab\tx390\wrapdefault\faauto\ls1\ilvl1\outlinelevel1\adjustright\rin0\lin390\itap0 \rtlch\fcs1 \ab\ai\af1\afs24\alang1025 \ltrch\fcs0 \b\i\fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 CPU Organization{\*\bkmkend _Toc345583812} +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 Most CPU\hich\f1 \rquote \loch\f1 s perform at least the following functions: +\par +\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls3\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls3\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Time keeping +\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls3\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls3\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Instruction fetching +\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls3\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls3\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Address decoding +\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls3\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls3\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Execution of non-I/O instructions +\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls3\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls3\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 I/O command processing +\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls3\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls3\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Interrupt processing +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 Instruction execution is actually the least complicated part of the design; memory and I/O organization should be tackled first. +\par {\*\bkmkstart _Toc345583813}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 3.1.1\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar +\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Tim\hich\af1\dbch\af31505\loch\f1 e Base{\*\bkmkend _Toc345583813} +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 +In order to simulate asynchronous events, such as I/O completion, the VM must define and keep a time base. This can be accurate (for example, nanoseconds of execution) or arbitrary (for example, number of instructions executed), but i +\hich\af1\dbch\af31505\loch\f1 t must be used consistently throughout the VM. All existing VM\hich\f1 \rquote \loch\f1 s count time in instructions. +\par +\par \hich\af1\dbch\af31505\loch\f1 The CPU is responsible for counting down the event counter }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_interval}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 and calling the asynchronous event controller }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_process_event}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 . SCP does the record kee\hich\af1\dbch\af31505\loch\f1 ping for timing. +\par {\*\bkmkstart _Toc345583814}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 3.1.2\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar +\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Step Function{\*\bkmkend _Toc345583814} +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 SCP implements a stepping function using the step command. STEP counts down a specified number of time units (as described in section 3.1\hich\af1\dbch\af31505\loch\f1 +.1) and then stops simulation. The VM can override the STEP command\hich\f1 \rquote \loch\f1 s counts by calling routine }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_cancel_step}{\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 : +\par +\par {\listtext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault\faauto\ls25\adjustright\rin0\lin720\itap0 { +\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat sim_cancel_step (void) \hich\f1 \endash \loch\f1 cancel STEP count down. +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 The VM can then inspect variable }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_step}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 + to see if a STEP command is in progress.\hich\af1\dbch\af31505\loch\f1 If }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_step}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 + is non-zero, it represents the number of steps to execute. The VM can count down }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_step}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 using its own counting method, such as cycles, instructions, or memory references. +\par {\*\bkmkstart _Toc345583815}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 3.1.3\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar +\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Memory Organization{\*\bkmkend _Toc345583815} +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 The criterion f\hich\af1\dbch\af31505\loch\f1 +or memory layout is very simple: use the SIMH data type that is as large as (or if necessary, larger than), the word length of the real machine. Note that the criterion is word length, not addressability: the PDP-11 has byte addressable memory, but it is +\hich\af1\dbch\af31505\loch\f1 \hich\af1\dbch\af31505\loch\f1 +a 16-bit machine, and its memory is defined as uint16 M[]. It may seem tempting to define memory as a union of int8 and int16 data types, but this would make the resulting VM endian-dependent. Instead, the VM should be based on the underlying word size +\hich\af1\dbch\af31505\loch\f1 o\hich\af1\dbch\af31505\loch\f1 f the real machine, and byte manipulation should be done explicitly. Examples: +\par +\par \tab \hich\af1\dbch\af31505\loch\f1 Simulator\tab \tab memory size\tab \tab memory declaration +\par +\par \tab \hich\af1\dbch\af31505\loch\f1 IBM 1620\tab \tab 5-bit\tab \tab \tab uint8 +\par \tab \hich\af1\dbch\af31505\loch\f1 IBM 1401\tab \tab 7-bit\tab \tab \tab uint8 +\par \tab \hich\af1\dbch\af31505\loch\f1 PDP-8\tab \tab \tab 12-bit\tab \tab \tab uint16 +\par \tab \hich\af1\dbch\af31505\loch\f1 PDP-11, Nova\tab \tab 16-bit\tab \tab \tab uint16 +\par \tab \hich\af1\dbch\af31505\loch\f1 PDP-1\tab \tab \tab 18-bit\tab \tab \tab uint32 +\par \tab \hich\af1\dbch\af31505\loch\f1 VAX\tab \tab \tab 32-bit\tab \tab \tab uint32 +\par \tab \hich\af1\dbch\af31505\loch\f1 PDP-10, IBM 7094\tab 36-bit\tab \tab \tab t_uint64 +\par {\*\bkmkstart _Toc345583816}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 3.1.4\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar +\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Interrupt Organization{\*\bkmkend _Toc345583816} +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 The design of the VM\hich\f1 \rquote \loch\f1 s interrupt structure is a complex interaction between efficiency and fidelity to the hardware. If the VM\hich\f1 \rquote \loch\f1 s interrupt \hich\af1\dbch\af31505\loch\f1 +structure is too abstract, interrupt driven software may not run. On the other hand, if it follows the hardware too literally, it may significantly reduce simulation speed. One rule I can offer is to minimize the fetch-phase cost of interrupts, even if +\hich\af1\dbch\af31505\loch\f1 t\hich\af1\dbch\af31505\loch\f1 +his complicates the (much less frequent) evaluation of the interrupt system following an I/O operation or asynchronous event. Another is not to over-generalize; even if the real hardware could support 64 or 256 interrupting devices, the simulators will b +\hich\af1\dbch\af31505\loch\f1 e\hich\af1\dbch\af31505\loch\f1 running much smaller configurations. I\hich\f1 \rquote \loch\f1 ll start with a simple interrupt structure and then offer suggestions for generalization. +\par +\par \hich\af1\dbch\af31505\loch\f1 In the simplest structure, interrupt requests correspond to device flags and are kept in an interrupt request variable, with\hich\af1\dbch\af31505\loch\f1 + one flag per bit. The fetch-phase evaluation of interrupts consists of two steps: are interrupts enabled, and is there an interrupt outstanding? If all the interrupt requests are kept as single-bit flags in a variable, the fetch-phase test is very fast +\hich\af1\dbch\af31505\loch\f1 : +\par +\par \tab \hich\af1\dbch\af31505\loch\f1 if (int_enable && int_requests) \{\hich\f1 \'85\loch\f1 \hich\f1 process interrupt\'85\loch\f1 \} +\par +\par \hich\af1\dbch\af31505\loch\f1 Indeed, the interrupt enable flag can be made the highest bit in the interrupt request variable, and the two tests combined: +\par +\par \tab \hich\af1\dbch\af31505\loch\f1 if (int_requests > INT_ENABLE) \{\hich\f1 \'85\loch\f1 \hich\f1 process interrupt\'85\loch\f1 \} +\par +\par \hich\af1\dbch\af31505\loch\f1 Setting or clearing device flags directly sets or clears the appropriate interrupt request flag: +\par +\par \tab \hich\af1\dbch\af31505\loch\f1 set: \tab int_requests = int_requests | DEVICE_FLAG; +\par \tab \hich\af1\dbch\af31505\loch\f1 clear:\tab int_requests = int_requests & ~DEVICE_FLAG; +\par +\par \hich\af1\dbch\af31505\loch\f1 At a slightly higher complexity, interrupt requests do \hich\af1\dbch\af31505\loch\f1 +not correspond directly to device flags but are based on masking the device flags with an enable (or disable) mask. There are now two parallel variables: device flags and interrupt enable mask. The fetch-phase test is now: +\par +\par \tab \hich\af1\dbch\af31505\loch\f1 If (int_enable && (dev_flags \hich\af1\dbch\af31505\loch\f1 & int_enables)) \{\hich\f1 \'85\loch\f1 \hich\f1 process interrupt\'85\loch\f1 \} +\par +\par \hich\af1\dbch\af31505\loch\f1 As a next step, the VM may keep a summary interrupt request variable, which is updated by any change to a device flag or interrupt enable/disable: +\par +\par \tab \hich\af1\dbch\af31505\loch\f1 enable:\tab int_requests = device_flags & int_enables; +\par \tab \hich\af1\dbch\af31505\loch\f1 disable:\tab int_r\hich\af1\dbch\af31505\loch\f1 equests = device_flags & ~int_disables; +\par +\par \hich\af1\dbch\af31505\loch\f1 This simplifies the fetch phase test slightly. +\par +\par \hich\af1\dbch\af31505\loch\f1 At yet higher complexity, the interrupt system may be too complex or too large to evaluate during the fetch-phase. In this case, an interrupt pending flag is created,\hich\af1\dbch\af31505\loch\f1 + and it is evaluated by subroutine call whenever a change could occur (start of execution, I/O instruction issued, device time out occurs). This makes fetch-phase evaluation simple and isolates interrupt evaluation to a common subroutine. +\par +\par \hich\af1\dbch\af31505\loch\f1 If required for\hich\af1\dbch\af31505\loch\f1 + interrupt processing, the highest priority interrupting device can be determined by scanning the interrupt request variable from high priority to low until a set bit is found. The bit position can then be back-mapped through a table to determine the add +\hich\af1\dbch\af31505\loch\f1 r\hich\af1\dbch\af31505\loch\f1 ess or interrupt vector of the interrupting device. +\par {\*\bkmkstart _Toc345583817}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 3.1.5\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar +\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 I/O Dispatching{\*\bkmkend _Toc345583817} +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 I/O dispatching consists of four steps: +\par +\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls14\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls14\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Identify the I/O command and analyze for the device address. +\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls14\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls14\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Locate the selected device. +\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls14\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls14\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Break down the I\hich\af1\dbch\af31505\loch\f1 +/O command into standard fields. +\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls14\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls14\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Call the device processor. +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 Analyzing an I/O command is usually easy. Most systems have one or more explicit I/O instructio\hich\af1\dbch\af31505\loch\f1 +ns containing an I/O command and a device address. Memory mapped I/O is more complicated; the identification of a reference to I/O space becomes part of memory addressing. This usually requires centralizing memory reads and writes into subroutines, rath +\hich\af1\dbch\af31505\loch\f1 e\hich\af1\dbch\af31505\loch\f1 r than as inline code. +\par +\par \hich\af1\dbch\af31505\loch\f1 +Once an I/O command has been analyzed, the CPU must locate the device subroutine. The simplest way is a large switch statement with hardwired subroutine calls. More modular is to call through a dispatch table, with NULL entries rep +\hich\af1\dbch\af31505\loch\f1 +resenting non-existent devices; this also simplifies support for modifiable device addresses and configurable devices. Before calling the device routine, the CPU usually breaks down the I/O command into standard fields. This simplifies writing the perip +\hich\af1\dbch\af31505\loch\f1 h\hich\af1\dbch\af31505\loch\f1 eral simulator. +\par {\*\bkmkstart _Toc345583818}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 3.1.6\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar +\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Instruction Execution{\*\bkmkend _Toc345583818} +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 Instruction execution is the responsibility of VM subroutine }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_instr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 . It is called from SCP as a result of a RUN, GO, CONT, or BOOT command. It begins executing instructions at the \hich\af1\dbch\af31505\loch\f1 current PC (}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 sim_PC}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 points to its register description block) and continues until halted by an error or an external event. +\par +\par \hich\af1\dbch\af31505\loch\f1 When called, the CPU needs to account for any state changes that the user made. For example, it may need to re-evaluate whether an i\hich\af1\dbch\af31505\loch\f1 +nterrupt is pending, or restore frequently used state to local register variables for efficiency. The actual instruction fetch and execute cycle is usually structured as a loop controlled by an error variable, e.g., +\par +\par \tab \hich\af1\dbch\af31505\loch\f1 reason = 0; +\par \tab \hich\af1\dbch\af31505\loch\f1 do \{\hich\f1 \'85\loch\f1 \} while (reason =\hich\af1\dbch\af31505\loch\f1 = 0);\tab or\tab while (reason == 0) \{\hich\f1 \'85\loch\f1 \} +\par +\par \hich\af1\dbch\af31505\loch\f1 Within this loop, the usual order of events is: +\par +\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls4\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls4\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 If the event timer }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 sim_interval}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 has reached zero, process any timed events. This is done by SCP subroutine }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 +\b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_process_event}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 . Because this is the polling mechanism fo\hich\af1\dbch\af31505\loch\f1 +r user-generated processor halts (^E), errors must be recognized immediately: +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par }\pard \ltrpar\ql \li1440\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin1440\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 if (sim_interval <= 0) \{ +\par }\pard \ltrpar\ql \fi720\li1440\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin1440\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 +if (reason = sim_process_event ()) break; \} +\par }\pard \ltrpar\ql \fi2160\li0\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls4\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls4\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Check for outstanding interrupts and process if required. +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls4\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls4\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Check for other processor-unique events, \hich\af1\dbch\af31505\loch\f1 +such as wait-state outstanding or traps outstanding. +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls4\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls4\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 +Check for an instruction breakpoint. SCP has a comprehensive breakpoint facility. It allows a VM to define many different kinds of breakpoints. The VM checks for exec\hich\af1\dbch\af31505\loch\f1 ution (type E) breakpoints during instruction fetch. + +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls4\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls4\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 +Fetch the next instruction, increment the PC, optionally decode the address, and dispatch (via a switch statement) for execution. +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 A few guidelines for implementation: +\par +\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls5\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls5\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 +In general, code should reflect the hardware being simulated. This is usually simplest and easiest to debug. +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls5\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls5\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 The VM should provide some debugging aids. The existing CPU\hich\f1 +\rquote \loch\f1 s all provide multiple instruction breakpoints, a PC change queue, error stops on\hich\af1\dbch\af31505\loch\f1 invalid instructions or operations, and symbolic examination and modification of memory. +\par {\*\bkmkstart _Toc345583819}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 3.2\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar +\jclisttab\tx390\wrapdefault\faauto\ls1\ilvl1\outlinelevel1\adjustright\rin0\lin390\itap0 \rtlch\fcs1 \ab\ai\af1\afs24\alang1025 \ltrch\fcs0 \b\i\fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Peripheral Device Organization{\*\bkmkend _Toc345583819} +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 The basic elements of a VM are devices, each corresponding roughly to a real chunk of hardware. A devic\hich\af1\dbch\af31505\loch\f1 +e consists of register-based state and one or more units. Thus, a multi-drive disk subsystem is a single device (representing the hardware of the real controller) and one or more units (each representing a single disk drive). Sometimes the device and it +\hich\af1\dbch\af31505\loch\f1 s\hich\af1\dbch\af31505\loch\f1 + unit are the same entity as, for example, in the case of a paper tape reader. However, a single physical device, such as the console, may be broken up for convenience into separate input and output devices. +\par +\par \hich\af1\dbch\af31505\loch\f1 In general, units correspond to individual sou\hich\af1\dbch\af31505\loch\f1 +rces of input or output (one tape transport, one A-to-D channel). Units are the basic medium for both device timing and device I/O. Except for the console, all I/O devices are simulated as host-resident files. SCP allows the user to make an explicit as +\hich\af1\dbch\af31505\loch\f1 s\hich\af1\dbch\af31505\loch\f1 ociation between a host-resident file and a simulated hardware entity. +\par +\par \hich\af1\dbch\af31505\loch\f1 Both devices and units have state. Devices operate on }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 registers}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 , which contain information about the state of the device, and indirectly, about the state of the units. Units operate \hich\af1\dbch\af31505\loch\f1 on }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 data sets}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 +, which may be thought of as individual instances of input or output, such as a disk pack or a punched paper tape. In a typical multi-unit device, all units are the same, and the device performs similar operations on all of them, depending on +\hich\af1\dbch\af31505\loch\f1 which one has been selected by the program being simulated. +\par +\par \hich\af1\dbch\af31505\loch\f1 (Note: SIMH, like MIMIC, restricts registers to devices. Replicated registers, for example, disk drive current state, are handled via register arrays.) +\par +\par \hich\af1\dbch\af31505\loch\f1 For each structural level, SIMH defines, a\hich\af1\dbch\af31505\loch\f1 nd the VM must supply, a corresponding data structure. }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 +sim_device}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 structures correspond to devices, }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_reg}{\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 structures to registers, and }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_unit}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 + structures to units. These structures are described in detail in section 4. +\par +\par \hich\af1\dbch\af31505\loch\f1 The primary functions of a peri\hich\af1\dbch\af31505\loch\f1 pheral are: +\par +\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls6\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls6\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 command decoding and execution +\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls6\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls6\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 device timing +\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls6\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls6\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 data transmission. +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 Command decoding is fairly obvious. At least one section of the peripheral code module will be devoted to processing directives issued by the CPU. Typically, the comma\hich\af1\dbch\af31505\loch\f1 +nd decoder will be responsible for register and flag manipulation, and for issuing or canceling I/O requests. The former is easy, but the later requires a thorough understanding of device timing. +\par {\*\bkmkstart _Toc345583820}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 3.2.1\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar +\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Device Timing{\*\bkmkend _Toc345583820} +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 The principa\hich\af1\dbch\af31505\loch\f1 +l problem in I/O device simulation is imitating asynchronous operations in a sequential simulation environment. Fortunately, the timing characteristics of most I/O devices do not vary with external circumstances. The distinction between devices whose ti +\hich\af1\dbch\af31505\loch\f1 m\hich\af1\dbch\af31505\loch\f1 ing is externally generated (e.g., console keyboard) and those whose timing is }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid1049593 \hich\af1\dbch\af31505\loch\f1 internally}{\rtlch\fcs1 \af1 +\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 generated (disk, paper tape reader) is crucial. With an externally timed device, there is no way to know when an in-progress operation will begin or end; with an int +\hich\af1\dbch\af31505\loch\f1 ernally timed device, given the time when an operation starts, the end time can be calculated. +\par +\par \hich\af1\dbch\af31505\loch\f1 For an internally timed device, the elapsed time between the start and conclusion of an operation is called the wait time. Some typical internally timed device\hich\af1\dbch\af31505\loch\f1 s and their wait times include: + +\par +\par \tab \hich\af1\dbch\af31505\loch\f1 PTR (300 char/sec)\tab \tab 3.3 msec +\par \tab \hich\af1\dbch\af31505\loch\f1 PTP (50 char/sec)\tab \tab 20 msec +\par \tab \hich\af1\dbch\af31505\loch\f1 CLK (line frequency)\tab \tab 16.6 msec +\par \tab \hich\af1\dbch\af31505\loch\f1 TTO (30 char/sec)\tab \tab 33 msec +\par +\par \hich\af1\dbch\af31505\loch\f1 Mass storage devices, such as disks and tapes, do not have a fixed response time, but a start-to-finish\hich\af1\dbch\af31505\loch\f1 time can be calculated based on current versus desired position, state of motion, etc. + +\par +\par \hich\af1\dbch\af31505\loch\f1 For an externally timed device, there is no portable mechanism by which a VM can be notified of an external event (for example, a key stroke). Accordingly, all curren\hich\af1\dbch\af31505\loch\f1 t VM\hich\f1 \rquote +\loch\f1 +s poll for keyboard input, thus converting the externally timed keyboard to a pseudo-internally timed device. A more general restriction is that SIMH is single-threaded. Threaded operations must be done by polling using the unit timing mechanism, e +\hich\af1\dbch\af31505\loch\f1 i\hich\af1\dbch\af31505\loch\f1 ther with real units or fake units created expressly for polling. +\par +\par \hich\af1\dbch\af31505\loch\f1 SCP provides the supporting routines for device timing. SCP maintains a list of devices (called active devices) that are in the process of timing out. It also provides routines for queryi\hich\af1\dbch\af31505\loch\f1 +ng or manipulating this list (called the active queue). Lastly, it provides a routine for checking for timed-out units and executing a VM-specified action when a time-out occurs. +\par +\par \hich\af1\dbch\af31505\loch\f1 Device timing is done with the UNIT structure, described in section 4. To \hich\af1\dbch\af31505\loch\f1 +set up a timed operation, the peripheral calculates a waiting period for a unit and places that unit on the active queue. The CPU counts down the waiting period. When the waiting period has expired, }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 +\b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_process_event}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 removes the unit from the active queu\hich\af1\dbch\af31505\loch\f1 +e and calls a device subroutine. A device may also cancel an outstanding timed operation and query the state of the queue. The timing subroutines are: +\par +\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls7\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls7\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 sim_activate}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (UNIT *uptr, int32 wait). This routine places the specified unit on the active\hich\af1\dbch\af31505\loch\f1 + queue with the specified waiting period. A waiting period of 0 is legal; negative waits cause an error. If the unit is already active, the active queue is not changed, and no error occurs. +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls7\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls7\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 sim_cancel}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (UNIT *uptr). This routine removes the sp\hich\af1\dbch\af31505\loch\f1 +ecified unit from the active queue. If the unit is not on the queue, no error occurs. +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls7\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls7\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 int32 }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 sim_is_active}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (UNIT *uptr). This routine tests whether a unit is in the active queue. If it is, the routine returns }{\rtlch\fcs1 \af1 +\ltrch\fcs0 \f1\insrsid10051909 \hich\af1\dbch\af31505\loch\f1 TRUE(1)}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 ; if it is not, the routine return\hich\af1\dbch\af31505\loch\f1 s }{\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid10051909 \hich\af1\dbch\af31505\loch\f1 FALSE(}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 0}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid10051909 \hich\af1\dbch\af31505\loch\f1 )}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 . +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0\pararsid13897431 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid10051909 +\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid10051909 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls7\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls7\adjustright\rin0\lin720\itap0\pararsid13897431 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid10051909 \hich\af1\dbch\af31505\loch\f1 int32 }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 +\b\f1\insrsid10051909 \hich\af1\dbch\af31505\loch\f1 sim_activate_time}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid10051909 \hich\af1\dbch\af31505\loch\f1 + (UNIT *uptr). This routine returns the time the device has remaining in the queue + 1. if it is not pending, the routine returns 0.}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid10051909\charrsid10051909 +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls7\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls7\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 double }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 sim_gtime}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (void). This routine returns the time elapsed since the last RUN or BOOT command. +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls7\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls7\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uint32 }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 sim_grtime}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (void). This routine returns the low-order 32b of the time elapsed since the last RUN or BOOT command. +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls7\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls7\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 int32 }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 sim_qcount}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (void). This routine ret\hich\af1\dbch\af31505\loch\f1 urns the number of entries on the clock queue. +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls7\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls7\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 sim_process_event}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 + (void). This routine removes all timed out units from the active queue and calls the appropriate device subroutine to service the time-out. +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls7\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls7\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 int32 }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 sim_interval}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 . This variable \hich\af1\dbch\af31505\loch\f1 \hich\f1 +counts down the first outstanding timed event. If there are no timed events outstanding, SCP counts down a \'93\loch\f1 \hich\f1 null interval\'94\loch\f1 of 10,000 time units. +\par {\*\bkmkstart _Toc345583821}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 3.2.2\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar +\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Clock Calibration{\*\bkmkend _Toc345583821} +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 The timing mechanism described in the previous section is a\hich\af1\dbch\af31505\loch\f1 +pproximate. Devices, such as real-time clocks, which track wall time will be inaccurate. SCP provides routines to synchronize multiple simulated clocks (to a maximum of 8) to wall time. +\par +\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls15\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls15\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 int32 }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 sim_rtcn_init}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (int32 clock_interval, int32 clk). This rou\hich\af1\dbch\af31505\loch\f1 +tine initializes the clock calibration mechanism for simulated clock }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 clk}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 +. The argument is returned as the result. +\par }\pard \ltrpar\ql \li360\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls15\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls15\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 int32 }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 sim_rtcn_calb}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (int32 tickspersecond, int32 clk). This routine calibrates simulated clock }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 +\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 clk}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 . The argument is the number of clock\hich\af1\dbch\af31505\loch\f1 ticks expected per second. +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 The VM must call }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_rtcn_init}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 + for each simulated clock in two places: in the prolog of }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_instr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 +, before instruction execution starts, and whenever the real-time clock is started. The simulator calls }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_rtcn_calb}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 to calculat\hich\af1\dbch\af31505\loch\f1 e the actual interval delay when the real-time clock is serviced: +\par +\par \tab \hich\af1\dbch\af31505\loch\f1 /* clock start */ +\par +\par \tab \hich\af1\dbch\af31505\loch\f1 if (!sim_is_active (&clk_unit)) sim_activate (&clk_unit, sim_rtcn_init (clk_delay, clkno)); +\par \tab \hich\af1\dbch\af31505\loch\f1 etc. +\par +\par \tab \hich\af1\dbch\af31505\loch\f1 /* clock service */ +\par +\par \tab \hich\af1\dbch\af31505\loch\f1 sim_activate (&clk_unit, sim_rtcb_calb (clk_ticks_per_second, clkno); +\par +\par \hich\af1\dbch\af31505\loch\f1 The real-time clock is usually simulated clock 0; other clocks are used for polling asynchronous multiplexers or intervals timers. +\par {\*\bkmkstart _Toc345583822}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 3.2.3\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar +\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Idling{\*\bkmkend _Toc345583822} +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 If a VM implem\hich\af1\dbch\af31505\loch\f1 +ents a free-running, calibrated clock of 100Hz or less, then the VM can also implement idling. Idling is a way of pausing simulation when no real work is happening, without losing clock calibration. The VM must detect when it is idle; it can then inform +\hich\af1\dbch\af31505\loch\f1 \hich\af1\dbch\af31505\loch\f1 the host of this situation by calling }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_idle}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 : +\par +\par {\listtext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault\faauto\ls26\adjustright\rin0\lin720\itap0 { +\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_bool }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_idle}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 (int32 clk, t_bool one_tick) \hich\f1 \endash \loch\f1 attempt to idle the VM until the next scheduled I/O event, using simulated clock }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 +clk}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 as the time base, and decrement }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_interval}{\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 by an appropriate number of \hich\af1\dbch\af31505\loch\f1 cycles. If a calibrated timer is not available, or the time until the next event is less than 1ms, decrement }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 +\b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_interval}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 by 1 if }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 one_tick}{ +\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 is TRUE; otherwise, leave sim_interval unchanged. +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_idle}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 returns TRUE if the VM actually idled, FALSE if it did not. +\par +\par \hich\af1\dbch\af31505\loch\f1 Because idling and throttling are mutually exclusive, the VM must inform SCP when idling is turned on or off: +\par +\par {\listtext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault\faauto\ls26\adjustright\rin0\lin720\itap0 { +\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_set_idle}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 (UNIT *uptr, int32 val, char *cptr, void *desc) \hich\f1 \endash \loch\f1 informs SCP\hich\af1\dbch\af31505\loch\f1 that idling is enabled. +\par {\listtext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}\hich\af1\dbch\af31505\loch\f1 t_stat}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 + sim_clr_idle}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (UNIT *uptr, int32 val, char *cptr, void *desc) \hich\f1 \endash \loch\f1 informs SCP that idling is disabled. +\par {\listtext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}\hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 +sim_show_idle}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (FILE *st, UNIT *uptr, int32 val, void *desc) \hich\f1 \endash \loch\f1 displays whether idling is enabled or disabled, as \hich\af1\dbch\af31505\loch\f1 +seen by SCP. +\par {\*\bkmkstart _Toc345583823}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 3.2.4\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar +\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Data I/O{\*\bkmkend _Toc345583823} +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 For most devices, timing is half the battle (for clocks it is the entire war); the other half is I/O. Some devices are simulated on real hardware (for example, Ethernet controllers). Most I/O devices +\hich\af1\dbch\af31505\loch\f1 + are simulated as files on the host file system in little-endian format. SCP provides facilities for associating files with units (ATTACH command) and for reading and writing data from and to devices in a endian- and size-independent way. +\par +\par \hich\af1\dbch\af31505\loch\f1 For most device\hich\af1\dbch\af31505\loch\f1 +s, the VM designer does not have to be concerned about the formatting of simulated device files. I/O occurs in 1, 2, 4, or 8 byte quantities; SCP automatically chooses the correct data size and corrects for byte ordering. Specific issues: +\par +\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls8\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls8\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Line printe\hich\af1\dbch\af31505\loch\f1 +rs should write data as 7-bit ASCII, with newlines replacing carriage-return/line-feed sequences. +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls8\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls8\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 +Disks should be viewed as linear data sets, from sector 0 of surface 0 of cylinder 0 to the last sector on the disk. This allows easy transcription of re\hich\af1\dbch\af31505\loch\f1 al disks to files usable by the simulator. +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls8\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls8\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 +Magtapes, by convention, use a record based format. Each record consists of a leading 32-bit record length, t\hich\af1\dbch\af31505\loch\f1 +he record data (padded with a byte of 0 if the record length is odd), and a trailing 32-bit record length. File marks are recorded as one record length of 0. +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls8\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls8\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 +Cards have 12 bits of data per column, but the data is most conveniently viewed as (ASCII) ch\hich\af1\dbch\af31505\loch\f1 aracters. Column binary can be implemented using two successive characters per card column.. +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 Data I/O varies between fixed and variable capacity devices, and between buffered and non-buffered devices. A fixed capacity device differs from a variable capa\hich\af1\dbch\af31505\loch\f1 +city device in that the file attached to the former has a maximum size, while the file attached to the latter may expand indefinitely. A buffered device differs from a non-buffered device in that the former buffers its data set in host memory, while the +\hich\af1\dbch\af31505\loch\f1 l\hich\af1\dbch\af31505\loch\f1 atter maintains it as a file. Most variable capacity devices (such as the paper tape reader and punch) are sequential; all buffered devices are fixed capacity. +\par +\par {\listtext\pard\plain\ltrpar \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f1\fs20\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 3.2.4.1\tab}}\pard \ltrpar\ql \fi-1080\li1080\ri0\widctlpar +\jclisttab\tx1080\wrapdefault\faauto\ls1\ilvl3\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Reading and Writing Data +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 The ATTACH command creates an association between a host fil\hich\af1\dbch\af31505\loch\f1 e and an I/O unit. For non-buffered devices, ATTACH stores the file pointer for the host file in the }{\rtlch\fcs1 \ab\af1 +\ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 fileref}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 + field of the UNIT structure. For buffered devices, ATTACH reads the entire host file into a buffer pointed to by the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 filebuf }{\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 field of the UNIT st\hich\af1\dbch\af31505\loch\f1 ructure. If unit flag UNIT_MUSTBUF is set, the buffer is allocated dynamically; otherwise, it must be statically allocated. +\par +\par \hich\af1\dbch\af31505\loch\f1 For non-buffered devices, I/O is done with standard C subroutines plus the SCP routines }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_fread}{\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 and }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_fwrite}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 . }{\rtlch\fcs1 +\ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_fread}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 and }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 s +\hich\af1\dbch\af31505\loch\f1 im_fwrite}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 + are identical in calling sequence and function to fread and fwrite, respectively, but will correct for endian dependencies. For buffered devices, I/O is done by copying data to or from the allocated buffer. The device code must maintain the num +\hich\af1\dbch\af31505\loch\f1 ber (+1) of the highest address modified in the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 hwmark}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 + field of the UNIT structure. For both the non-buffered and buffered cases, the device must perform all address calculations and positioning operations. +\par +\par \hich\af1\dbch\af31505\loch\f1 SIMH provides capabilities to access files >2GB\hich\af1\dbch\af31505\loch\f1 + (the int32 position limit). If a VM is compiled with flags USE_INT64 and USE_ADDR64 defined, then t_addr is defined as t_uint64 rather than uint32. Routine sim_fseek allows simulated devices to perform random access in large files: +\par +\par {\listtext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault\faauto\ls24\adjustright\rin0\lin720\itap0 { +\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 int }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_fseek}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 (FIL\hich\af1\dbch\af31505\loch\f1 E *handle, t_addr position, int where) +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 sim_fseek is identical to standard C }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 fseek}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 +, with two exceptions: where = SEEK_END is not supported, and the position argument can be 64b wide. +\par +\par \hich\af1\dbch\af31505\loch\f1 The DETACH command breaks the association between a host file and an I/O\hich\af1\dbch\af31505\loch\f1 unit. For buffered devices, DETACH writes the allocated buffer back to the host file. +\par +\par {\listtext\pard\plain\ltrpar \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f1\fs20\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 3.2.4.2\tab}}\pard \ltrpar\ql \fi-1080\li1080\ri0\widctlpar +\jclisttab\tx1080\wrapdefault\faauto\ls1\ilvl3\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Console I/O +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\outlinelevel0\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 SCP provides three routines for console I/O. +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls10\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls10\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 sim_poll_char }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (void). This routine polls for keyboard input. If there is a character, it\hich\af1\dbch\af31505\loch\f1 + returns SCPE_KFLAG + the character. If the user typed the interrupt character (^E), it returns SCPE_STOP. If the console is attached to a Telnet connection, and the connection is lost, the routine returns SCPE_LOST. If there is no input, it returns SC +\hich\af1\dbch\af31505\loch\f1 P\hich\af1\dbch\af31505\loch\f1 E_OK. +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls10\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls10\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 sim_putchar}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 + (int32 char). This routine types the specified ASCII character to the console. If the console is attached to a Telnet connection, and the connection is lost, the routine returns SCPE_LOST. +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls10\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls10\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 sim_putchar_s}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 + (int32 char). This routine outputs the specified ASCII character to the console. If the console is attached to a Telnet connection, and the connection is lost, the routine returns SCPE_LOST; if the connection is backlogged, the routine returns SCPE_STA +\hich\af1\dbch\af31505\loch\f1 L\hich\af1\dbch\af31505\loch\f1 L. +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par {\*\bkmkstart _Toc345583824}{\listtext\pard\plain\ltrpar \s1 \rtlch\fcs1 \ab\af0\afs28 \ltrch\fcs0 \b\f1\fs28\kerning28\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.\tab}}\pard\plain \ltrpar\s1\ql \fi-360\li360\ri0\sb240\sa60\keepn\widctlpar +\jclisttab\tx360\wrapdefault\faauto\ls1\outlinelevel0\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 \b\fs28\lang1033\langfe1033\kerning28\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Data Structures{\*\bkmkend _Toc345583824} +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 The devices, units, and registers that make up a VM are formally described through a set of data structures which interface the VM to the control portions of SCP. The devices themselves are pointed to by t +\hich\af1\dbch\af31505\loch\f1 he device list array }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_devices[]}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 +. Within a device, both units and registers are allocated contiguously as arrays of structures. In addition, many devices allow the user to set or clear options via a modifications table. +\par +\par \hich\af1\dbch\af31505\loch\f1 \hich\f1 Note that a device must always have at least one unit, even if that unit is not needed for simulation purposes. A device must always point to a valid register table, but the register table can consist of just the +\'93\loch\f1 \hich\f1 end of table\'94\loch\f1 entry. +\par {\*\bkmkstart _Toc345583825}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.1\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar +\jclisttab\tx390\wrapdefault\faauto\ls1\ilvl1\outlinelevel1\adjustright\rin0\lin390\itap0 \rtlch\fcs1 \ab\ai\af1\afs24\alang1025 \ltrch\fcs0 \b\i\fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim\hich\af1\dbch\af31505\loch\f1 _device Structure{\*\bkmkend _Toc345583825} +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 Devices are defined by the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_device}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 structure (typedef +}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 DEVICE}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 ): +\par +\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 struct sim_device \{ +\par \tab \hich\af1\dbch\af31505\loch\f1 char\tab \tab *name;\tab \tab \tab \tab /* name */ +\par \tab \hich\af1\dbch\af31505\loch\f1 struct sim_unit \tab *units;\tab \tab \tab \tab /* units */ +\par \tab \hich\af1\dbch\af31505\loch\f1 struct sim_reg\tab *registers;\tab \tab \tab /* registers */ +\par \tab \hich\af1\dbch\af31505\loch\f1 struct sim_mtab\tab *modi\hich\af1\dbch\af31505\loch\f1 fiers;\tab \tab \tab /* modifiers */ +\par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab numunits;\tab \tab \tab /* #units */ +\par \tab \hich\af1\dbch\af31505\loch\f1 uint32\tab \tab aradix;\tab \tab \tab \tab /* address radix */ +\par \tab \hich\af1\dbch\af31505\loch\f1 uint32\tab \tab awidth;\tab \tab \tab \tab /* address width */ +\par \tab \hich\af1\dbch\af31505\loch\f1 uint32\tab \tab aincr;\tab \tab \tab \tab /* addr increment */ +\par \tab \hich\af1\dbch\af31505\loch\f1 uint32\tab \tab dradix;\tab \tab \tab \tab /* data radix */ +\par \tab \hich\af1\dbch\af31505\loch\f1 uint32\tab \tab dwidth;\tab \tab \tab \tab /* data width */ +\par \tab \hich\af1\dbch\af31505\loch\f1 t_s\hich\af1\dbch\af31505\loch\f1 tat\tab \tab (*examine)();\tab \tab \tab /* examine routine */ +\par \tab \hich\af1\dbch\af31505\loch\f1 t_stat\tab \tab (*deposit)();\tab \tab \tab /* deposit routine */ +\par \tab \hich\af1\dbch\af31505\loch\f1 t_stat\tab \tab (*reset)();\tab \tab \tab /* reset routine */ +\par \tab \hich\af1\dbch\af31505\loch\f1 t_stat\tab \tab (*boot)();\tab \tab \tab /* boot routine */ +\par \tab \hich\af1\dbch\af31505\loch\f1 t_stat\tab \tab (*attach)();\tab \tab \tab /* attach routine */ +\par \tab \hich\af1\dbch\af31505\loch\f1 t_stat\tab \tab (*detach)();\tab \tab \tab \hich\af1\dbch\af31505\loch\f1 /* detach routine */ +\par \tab \hich\af1\dbch\af31505\loch\f1 void\tab \tab *ctxt}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid399520 \hich\af1\dbch\af31505\loch\f1 ;}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \tab \tab \tab \tab \hich\af1\dbch\af31505\loch\f1 /}{ +\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 * context */ +\par \tab \hich\af1\dbch\af31505\loch\f1 uint32\tab \tab flags;\tab \tab \tab \tab /* flags */ +\par \tab \hich\af1\dbch\af31505\loch\f1 uint32\tab \tab dctrl;\tab \tab \tab \tab /* debug control flags */ +\par \tab \hich\af1\dbch\af31505\loch\f1 struct sim_debtab debflags;}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \tab \tab \tab \hich\af1\dbch\af31505\loch\f1 /}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 +* debug flag names */ +\par \tab \hich\af1\dbch\af31505\loch\f1 t_stat\tab \tab (*msize)();\tab \tab \tab /* memory size change */ +\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid399520 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid399520 \tab \hich\af1\dbch\af31505\loch\f1 char\tab \tab *lname;}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 +\b\f1\insrsid399520 \tab \tab \tab \tab \hich\af1\dbch\af31505\loch\f1 /*}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid399520 \hich\af1\dbch\af31505\loch\f1 logica\hich\af1\dbch\af31505\loch\f1 l name */ +\par \tab \hich\af1\dbch\af31505\loch\f1 t_stat\tab \tab \hich\af1\dbch\af31505\loch\f1 (\hich\af1\dbch\af31505\loch\f1 *\hich\af1\dbch\af31505\loch\f1 help)()\hich\af1\dbch\af31505\loch\f1 ;}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid399520 \tab \tab \tab +\hich\af1\dbch\af31505\loch\f1 /*}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid399520 \hich\af1\dbch\af31505\loch\f1 \hich\af1\dbch\af31505\loch\f1 help routine \hich\af1\dbch\af31505\loch\f1 */ +\par \tab \hich\af1\dbch\af31505\loch\f1 t_stat\tab \tab \hich\af1\dbch\af31505\loch\f1 (\hich\af1\dbch\af31505\loch\f1 *\hich\af1\dbch\af31505\loch\f1 attach_\hich\af1\dbch\af31505\loch\f1 help)()\hich\af1\dbch\af31505\loch\f1 ;}{\rtlch\fcs1 \ab\af1 +\ltrch\fcs0 \b\f1\insrsid399520 \tab \tab \tab \hich\af1\dbch\af31505\loch\f1 /*}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid399520 \hich\af1\dbch\af31505\loch\f1 \hich\af1\dbch\af31505\loch\f1 attach \hich\af1\dbch\af31505\loch\f1 help routine +\hich\af1\dbch\af31505\loch\f1 */ +\par \tab \hich\af1\dbch\af31505\loch\f1 void\tab \tab *\hich\af1\dbch\af31505\loch\f1 he\hich\af1\dbch\af31505\loch\f1 lp_\hich\af1\dbch\af31505\loch\f1 ctxt\hich\af1\dbch\af31505\loch\f1 ;}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid399520 \tab \tab \tab +\hich\af1\dbch\af31505\loch\f1 /}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid399520 \hich\af1\dbch\af31505\loch\f1 * \hich\af1\dbch\af31505\loch\f1 help \hich\af1\dbch\af31505\loch\f1 context */ +\par }\pard \ltrpar\ql \fi720\li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \}\hich\af1\dbch\af31505\loch\f1 ; +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 The fields are the following: +\par +\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 name}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab +\hich\af1\dbch\af31505\loch\f1 device name, string of all capital alphanumeric characters. +\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 units}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 pointer to array of }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 +\b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_unit}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 structures, or NULL if none. +\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 registers}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 pointer to array of }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 +\b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_reg}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 structures, or NULL if none. +\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 modifiers}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 poi\hich\af1\dbch\af31505\loch\f1 nter to array of }{\rtlch\fcs1 \ab\af1 +\ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_mtab}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 structures, or NULL if none. +\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 numunits}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 \tab number of units in this device. +\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 aradix}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 radix for input and display of device addresses, 2 to 16 inclusive. + +\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 awidth}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 width in bits of a device address, 1 to 64 inclusive. +\par }\pard \ltrpar\ql \fi-1440\li2160\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin2160\itap0 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 aincr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab +\hich\af1\dbch\af31505\loch\f1 increment betwe\hich\af1\dbch\af31505\loch\f1 en device addresses, normally 1; however, byte addressed devices with 16-bit words specify 2, with 32-bit words 4. +\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 dradix}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab +\hich\af1\dbch\af31505\loch\f1 radix for input and display of device data, 2 to 16 inclusive. +\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 dwidth}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 width in bits of device data, 1 to 64 inclusive. +\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 examine}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 addre\hich\af1\dbch\af31505\loch\f1 +ss of special device data read routine, or NULL if none is required. +\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 deposit}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 +address of special device data write routine, or NULL if none is required. +\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 reset}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 address of device reset routine, or NULL if none is required. +\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 boot}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 address of device bootstrap routine, or NULL if none is required. +\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 attach}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 address of special device attach routine, or NULL if none is required. + +\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 detach}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 address of special device detach routine, or NULL if none is required. + +\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 ctxt}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 address of VM-specific dev\hich\af1\dbch\af31505\loch\f1 +ice context table, or NULL if none is required. +\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 flags}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 device flags. +\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 dctrl\tab \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 debug control flags. +\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 debflags\tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 pointer to array of sim_debtab structures, or NULL if none. +\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid399520 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid399520 \hich\af1\dbch\af31505\loch\f1 msize}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid399520 \tab \tab +\hich\af1\dbch\af31505\loch\f1 address of memory size change routine, or NULL if none is required. +\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid399520 \hich\af1\dbch\af31505\loch\f1 lname\tab \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid399520 \hich\af1\dbch\af31505\loch\f1 pointer \hich\af1\dbch\af31505\loch\f1 to logical name string. +\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid399520 \hich\af1\dbch\af31505\loch\f1 help}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid399520 \tab \tab \hich\af1\dbch\af31505\loch\f1 address of \hich\af1\dbch\af31505\loch\f1 help routine +\hich\af1\dbch\af31505\loch\f1 , or NULL if none is required. +\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid399520 \hich\af1\dbch\af31505\loch\f1 attach_\hich\af1\dbch\af31505\loch\f1 help}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid399520 \tab \hich\af1\dbch\af31505\loch\f1 address of \hich\af1\dbch\af31505\loch\f1 +attach help routine\hich\af1\dbch\af31505\loch\f1 , or NULL if none is required. +\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid399520 \hich\af1\dbch\af31505\loch\f1 help_\hich\af1\dbch\af31505\loch\f1 ctx}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid399520 \tab \hich\af1\dbch\af31505\loch\f1 address of \hich\af1\dbch\af31505\loch\f1 +device specific context }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid14750569 \hich\af1\dbch\af31505\loch\f1 which might be useful while displaying }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid399520 \hich\af1\dbch\af31505\loch\f1 help }{\rtlch\fcs1 \af1 +\ltrch\fcs0 \f1\insrsid14750569 +\par }\pard \ltrpar\ql \li2160\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin2160\itap0\pararsid14750569 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid14750569 \hich\af1\dbch\af31505\loch\f1 for the current device, or NULL if }{\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid399520 \hich\af1\dbch\af31505\loch\f1 none is required. +\par {\*\bkmkstart _Toc345583826}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.1.1\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar +\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Awidth and Aincr{\*\bkmkend _Toc345583826} +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid4550150 +\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 The }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 awidth}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 field specifies the width of the VM\hich\f1 \rquote \loch\f1 \hich\f1 s fundamental computer \'93\loch\f1 \hich\f1 word\'94\loch\f1 . For example, on the PDP-11, }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 awidth}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 is 16b, even though memory is byte-addressable. The }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 aincr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 field spe\hich\af1\dbch\af31505\loch\f1 \hich\f1 cifies how many addressing units comprise the fundamental \'93\loch\f1 \hich\f1 word\'94 +\loch\f1 . For example, on the PDP-11, }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 aincr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 is 2 (2 bytes per word). +\par +\par \hich\af1\dbch\af31505\loch\f1 If }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 aincr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 + is greater than 1, SCP assumes that data is naturally aligned on addresses that are multiples of }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 aincr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 . VM\hich\f1 \rquote \loch\f1 s that suppo\hich\af1\dbch\af31505\loch\f1 rt arbitrary byte alignment of data (like the VAX) can follow one of two strategies: +\par +\par {\listtext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault\faauto\ls24\adjustright\rin0\lin720\itap0 { +\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Set }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 awidth}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 = 8 and }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 aincr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 + = 1 and support only byte access in the examine/deposit routines. +\par {\listtext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}\hich\af1\dbch\af31505\loch\f1 Set }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 awidth +}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 and }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 aincr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 to the fundamental sizes and support unaligned data access in the examine/deposit routines. +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 In a byte-addressable VM, SAVE and RESTORE will require (memory_size_bytes / }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 aincr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 ) iterations to save or restore memory. Thus, it is significantly more efficien\hich\af1\dbch\af31505\loch\f1 +t to use word-wide rather than byte-wide memory; but requirements for unaligned access can add significantly to the complexity of the examine and deposit routines. +\par {\*\bkmkstart _Toc345583827}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.1.2\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar +\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Device Flags{\*\bkmkend _Toc345583827} +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 The }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 flags }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 field contains indicators of current +\hich\af1\dbch\af31505\loch\f1 device status. SIMH defines }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid14776269 \hich\af1\dbch\af31505\loch\f1 several }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 flags: +\par +\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 flag name\tab \tab meaning if set +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par \tab \hich\af1\dbch\af31505\loch\f1 DEV_DISABLE\tab \tab device can be set enabled or disabled +\par \tab \hich\af1\dbch\af31505\loch\f1 DEV_DIS\tab \tab device is currently disabled +\par \tab \hich\af1\dbch\af31505\loch\f1 DEV_DYNM\tab \tab device requires call on }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 msize}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 + routine to change memory size +\par \tab \hich\af1\dbch\af31505\loch\f1 DEV_DEBUG\tab \tab \hich\af1\dbch\af31505\loch\f1 device supports SET DEBUG command +\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3867041 +\par \hich\af1\dbch\af31505\loch\f1 The flags field also contains an optional device type specification. One of these may be specified when initializing the flags field: +\par +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0\pararsid14776269 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid14776269 \tab \hich\af1\dbch\af31505\loch\f1 DEV_DISK\tab \tab device uses sim_disk library attach +\par \tab \hich\af1\dbch\af31505\loch\f1 DEV_TAPE\tab \tab device uses sim_tape librar\hich\af1\dbch\af31505\loch\f1 y attach +\par \tab \hich\af1\dbch\af31505\loch\f1 DEV_MUX\tab \tab device uses sim_tmxr library attach +\par \tab \hich\af1\dbch\af31505\loch\f1 DEV_ETHER\tab \tab device uses sim_ether library attach +\par \tab \hich\af1\dbch\af31505\loch\f1 DEV_DISPLAY\tab \tab device uses sim_video library attach +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid14776269 +\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Starting at bit position DEV_V_UF, the remaining flags are device-specific. Device flags are automa\hich\af1\dbch\af31505\loch\f1 +tically saved and restored; the device need not supply a register for these bits. +\par {\*\bkmkstart _Toc345583828}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.1.3\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar +\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Context{\*\bkmkend _Toc345583828} +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 The field contains a pointer to a VM-specific device context table, if required. SIMH never accesses this field. The context field \hich\af1\dbch\af31505\loch\f1 +allows VM-specific code to walk VM-specific data structures from the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_devices }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 +root pointer. +\par {\*\bkmkstart _Toc345583829}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.1.4\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar +\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Examine and Deposit Routines{\*\bkmkend _Toc345583829} +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 For devices which maintain their data sets as host files, SCP implements the examine and deposit da\hich\af1\dbch\af31505\loch\f1 +ta functions. However, devices which maintain their data sets as private state (for example, the CPU) must supply special examine and deposit routines. The calling sequences are: +\par +\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 examine_routine}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (t_val *eval_array, t_addr addr, UNIT *uptr, int32 \hich\af1\dbch\af31505\loch\f1 switches) \hich\f1 \endash \loch\f1 Copy }{ +\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_emax}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 consecutive addresses for unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 +\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 , starting at }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 addr}{\rtlch\fcs1 +\af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 , into }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 eval_array}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 +. The }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 switch}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 variable has bit set if the n\hich\f1 \rquote \loch\f1 +th letter was specified as a switch to the examine command. +\par +\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 deposit_routine}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (t_val value, t_addr addr, UN +\hich\af1\dbch\af31505\loch\f1 IT *uptr, int32 switches) \hich\f1 \endash \loch\f1 Store the specified }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 value}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 in the specified }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 addr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 for unit }{\rtlch\fcs1 \ai\af1 +\ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 . The }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 switch}{ +\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 variable is the same as for the examine routine. +\par {\*\bkmkstart _Toc345583830}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.1.5\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar +\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Reset Routine{\*\bkmkend _Toc345583830} +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 The reset routine implements the device reset function fo\hich\af1\dbch\af31505\loch\f1 r the RESET, RUN, and BOOT commands. Its calling sequence is: +\par +\par \tab \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 reset_routine}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (DEVICE *dptr) \hich\f1 +\endash \loch\f1 Reset the specified device to its initial state. +\par +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\outlinelevel0\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 +A typical reset routine clears all device flags and cancels any outstanding timing operations. Switch \loch\af1\dbch\af31505\hich\f1 \endash \loch\f1 p specifies a reset to power-up state. +\par {\*\bkmkstart _Toc345583831}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.1.6\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar +\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Boot Routine{\*\bkmkend _Toc345583831} +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 If a device responds to a BOOT command, the boot routine implements the bootstrapping function. Its calling sequence is: +\par +\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 boot_routine}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (int32 unit_num, DEVICE *dptr) \hich\f1 \endash \loch\f1 Bootstrap unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 unit_num}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 on the device }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 dptr}{\rtlch\fcs1 \af1 +\ltrch\fcs0 \f1\insrsid4550150 . +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 A typical bootstrap routine copies a bootstrap loader into main memory and sets the PC to the starting address of the loader. SCP then starts simulation at the specified addre\hich\af1\dbch\af31505\loch\f1 ss. +\par {\*\bkmkstart _Toc345583832}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.1.7\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar +\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Attach and Detach Routines{\*\bkmkend _Toc345583832} +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 Normally, the ATTACH and DETACH commands are handled by SCP. However, devices which need to pre- or post-process these commands must supply special attach and detach routines. The calling se\hich\af1\dbch\af31505\loch\f1 +quences are: +\par +\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 attach_routine }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (UNIT *uptr, char *file) \hich\f1 \endash \loch\f1 Attach the specified }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 file}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 to the unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 . +\par \hich\af1\dbch\af31505\loch\f1 Sim_switches contains the command switch; bit SIM_SW_REST indicates that attach is being called by the RESTORE command rather than the ATTACH command. +\par +\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 detach_routine}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (UNIT *uptr) \hich\f1 \endash +\loch\f1 Detach unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 . +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 In practice, these routines usually invoke the s\hich\af1\dbch\af31505\loch\f1 tandard SCP routines, }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 attach_unit}{\rtlch\fcs1 \af1 +\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 and }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 detach_unit}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 +, respectively. For example, here are special attach and detach routines to update line printer error state: +\par +\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \hich\af2\dbch\af31505\loch\f2 t_stat lpt_attach (UNIT *uptr, char *cptr) \{ +\par }\pard \ltrpar\ql \fi720\li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \hich\af2\dbch\af31505\loch\f2 t_stat r; +\par \hich\af2\dbch\af31505\loch\f2 if ((r = attach_unit (uptr, cptr)) != SCP\hich\af2\dbch\af31505\loch\f2 E_OK) return r; +\par \hich\af2\dbch\af31505\loch\f2 lpt_error = 0; +\par \hich\af2\dbch\af31505\loch\f2 return SCPE_OK; +\par \} +\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 +\par \hich\af2\dbch\af31505\loch\f2 t_stat lpt_detach (UNIT *uptr) \{ +\par \tab \hich\af2\dbch\af31505\loch\f2 lpt_error = 1; +\par \tab \hich\af2\dbch\af31505\loch\f2 return detach_unit (uptr); +\par }\pard \ltrpar\ql \fi720\li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \} +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 If the VM specifies an ATTACH or DETACH routine, SCP bypasses its normal tests before calling the V\hich\af1\dbch\af31505\loch\f1 +M routine. Thus, a VM DETACH routine cannot be assured that the unit is actually attached and must test the unit flags if required. +\par +\par \hich\af1\dbch\af31505\loch\f1 SCP executes a DETACH ALL command as part of simulator exit. Normally, DETACH ALL only calls a unit\hich\f1 \rquote \loch\f1 s detach routine if t\hich\af1\dbch\af31505\loch\f1 he unit\hich\f1 \rquote \loch\f1 +s UNIT_ATT flag is set. During simulator exit, the detach routine is also called if the unit is not flagged as attachable (UNIT_ATTABLE is not set). This allows the detach routine of a non-attachable unit to function as a simulator-specific clea +\hich\af1\dbch\af31505\loch\f1 n\hich\af1\dbch\af31505\loch\f1 up routine for the unit, device, or entire simulator. +\par {\*\bkmkstart _Toc345583833}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.1.8\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar +\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Memory Size Change Routine{\*\bkmkend _Toc345583833} +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 Most units instantiate any memory array at the maximum size possible. This allows apparent memory size to be changed by varying the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 capac +}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 fie\hich\af1\dbch\af31505\loch\f1 +ld in the unit structure. For some devices (like the VAX CPU), instantiating the maximum memory size would impose a significant resource burden if less memory was actually needed. These devices must provide a routine, the memory size change routine, for +\hich\af1\dbch\af31505\loch\f1 \hich\af1\dbch\af31505\loch\f1 RESTORE to use if memory size must be changed: +\par +\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 change_mem_size}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (UNIT *uptr, int32 val, char *cptr, void *desc) \hich\f1 \endash \loch\f1 Change the capacity (memory size) of unit }{ +\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 to }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 val}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 . The }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 cptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 and }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 desc}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 + arguments are included for compatibility with the SET command\loch\af1\dbch\af31505\hich\f1 \rquote \loch\f1 s validation routine calling sequence. +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par {\*\bkmkstart _Toc345583834}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.1.9\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar +\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Debug Controls{\*\bkmkend _Toc345583834} +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 Devices can support debug printouts. Debug printouts are controlled by the SET \{NO\}DEBUG command, which specifies where debug output should be printed; and by the SET\hich\af1\dbch\af31505\loch\f1 \{NO\} +DEBUG command, which enables or disables individual debug printouts. +\par +\par \hich\af1\dbch\af31505\loch\f1 If a device supports debug printouts, device flag DEV_DEBUG must be set. Field }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 dctrl}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 is used for the debug control flags. If a device supports only a single debug on/off \hich\af1\dbch\af31505\loch\f1 flag, then the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 +debflags}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 field should be set to NULL. If a device supports multiple debug on/off flags, then the correspondence between bit positions in }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 +\b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 dctrl}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 and debug flag names is specified by table }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 debflags}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 . }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 debflags}{\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 points to a continguous array of }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_debtab}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 structures (typedef }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 DEBTAB}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 +). Each sim_debtab structure specifies a single debug flag: +\par +\par \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid16013944 \hich\af1\dbch\af31505\loch\f1 s}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 truct sim_debtab \{ +\par \tab \tab \hich\af1\dbch\af31505\loch\f1 char\tab \tab name}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 ;\tab \tab \tab \tab /}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 +* flag name */ +\par \tab \tab \hich\af1\dbch\af31505\loch\f1 uint32\tab \tab mask;\tab \tab \tab \tab /* control bit */ +\par \tab \tab \}\hich\af1\dbch\af31505\loch\f1 ; +\par +\par \hich\af1\dbch\af31505\loch\f1 The fields are the following: +\par +\par \tab \hich\af1\dbch\af31505\loch\f1 name\tab \tab name of the debug flag. +\par \tab \hich\af1\dbch\af31505\loch\f1 mask\tab \tab bit mask of the debug flag. +\par +\par \hich\af1\dbch\af31505\loch\f1 The array is terminated with a NULL entry. +\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid8129972 +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\rin0\lin0\itap0\pararsid8129972 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid8129972 \hich\af1\dbch\af31505\loch\f1 Simulator code can produce debug output by calling }{\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid8084824 \hich\af1\dbch\af31505\loch\f1 sim_debug }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid8129972 \hich\af1\dbch\af31505\loch\f1 which is declared: +\par +\par }\pard \ltrpar\ql \fi720\li0\ri0\widctlpar\wrapdefault\faauto\rin0\lin0\itap0\pararsid16013944 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf2\lang1024\langfe1024\noproof\insrsid8129972 \hich\af2\dbch\af31505\loch\f2 void}{\rtlch\fcs1 \af2 \ltrch\fcs0 +\f2\lang1024\langfe1024\noproof\insrsid8129972 \hich\af2\dbch\af31505\loch\f2 _}{\rtlch\fcs1 \af2 \ltrch\fcs0 \b\f2\lang1024\langfe1024\noproof\insrsid8129972\charrsid16013944 \hich\af2\dbch\af31505\loch\f2 sim_debug}{\rtlch\fcs1 \af2 \ltrch\fcs0 +\f2\lang1024\langfe1024\noproof\insrsid8129972 \hich\af2\dbch\af31505\loch\f2 (uint32 dbits, DEVICE* dptr, }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf2\lang1024\langfe1024\noproof\insrsid8129972 \hich\af2\dbch\af31505\loch\f2 const}{\rtlch\fcs1 \af2 +\ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid8129972 \hich\af2\dbch\af31505\loch\f2 }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf2\lang1024\langfe1024\noproof\insrsid8129972 \hich\af2\dbch\af31505\loch\f2 char}{\rtlch\fcs1 \af2 \ltrch\fcs0 +\f2\lang1024\langfe1024\noproof\insrsid8129972 \hich\af2\dbch\af31505\loch\f2 * fmt, ...); +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\rin0\lin0\itap0\pararsid8129972 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid8129972 +\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid8129972\charrsid16013944 \hich\af1\dbch\af31505\loch\f1 The dbits is a flag which matches a mask in a sim_debtab structure, and the }{\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\lang1024\langfe1024\noproof\insrsid8352301\charrsid16013944 \hich\af1\dbch\af31505\loch\f1 the dptr is the DEVICE which has the corresponding dctl field.}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid8129972\charrsid16013944 + +\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid8352301\charrsid16013944 +\par \hich\af1\dbch\af31505\loch\f1 Additionally support exists for displaying bit and bitfield values. Bit field values are defined using the BITFIELD}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid8084824\charrsid16013944 +\hich\af1\dbch\af31505\loch\f1 structure and the BIT macros to declare the bits and bitfields.}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid8352301\charrsid16013944 +\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid8352301 +\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\rin0\lin720\itap0\pararsid16013944 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid8352301 \hich\af2\dbch\af31505\loch\f2 BIT(nm) }{\rtlch\fcs1 \af2 \ltrch\fcs0 +\f2\lang1024\langfe1024\noproof\insrsid8084824 \tab \tab \tab }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf11\lang1024\langfe1024\noproof\insrsid8084824 \hich\af2\dbch\af31505\loch\f2 - Single Bit definition}{\rtlch\fcs1 \af2 \ltrch\fcs0 +\f2\cf11\lang1024\langfe1024\noproof\insrsid8352301 +\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid8352301 \hich\af2\dbch\af31505\loch\f2 BITNC }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid8084824 \tab \tab \tab }{\rtlch\fcs1 \af2 \ltrch\fcs0 +\f2\cf11\lang1024\langfe1024\noproof\insrsid8084824 \hich\af2\dbch\af31505\loch\f2 - Don't care Bit definition}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf11\lang1024\langfe1024\noproof\insrsid8352301 +\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid8352301 \hich\af2\dbch\af31505\loch\f2 BITF(nm,sz) }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid8084824 \tab \tab }{\rtlch\fcs1 \af2 \ltrch\fcs0 +\f2\cf11\lang1024\langfe1024\noproof\insrsid8084824 \hich\af2\dbch\af31505\loch\f2 - Bit Field definition}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf11\lang1024\langfe1024\noproof\insrsid8352301 +\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid8352301 \hich\af2\dbch\af31505\loch\f2 BITNCF(sz)}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid8084824 \tab \tab \tab }{\rtlch\fcs1 \af2 \ltrch\fcs0 +\f2\cf11\lang1024\langfe1024\noproof\insrsid8084824 -}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf11\lang1024\langfe1024\noproof\insrsid8352301 \hich\af2\dbch\af31505\loch\f2 Do}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf11\lang1024\langfe1024\noproof\insrsid8084824 +\hich\af2\dbch\af31505\loch\f2 n't care Bit Field definition}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf11\lang1024\langfe1024\noproof\insrsid8352301 +\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid8352301 \hich\af2\dbch\af31505\loch\f2 BITFFMT(nm,sz,fmt)}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid8084824 \hich\af2\dbch\af31505\loch\f2 \tab }{ +\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf11\lang1024\langfe1024\noproof\insrsid8084824 -}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf11\lang1024\langfe1024\noproof\insrsid8352301 \hich\af2\dbch\af31505\loch\f2 Bit Field }{\rtlch\fcs1 \af2 \ltrch\fcs0 +\f2\cf11\lang1024\langfe1024\noproof\insrsid8084824 \hich\af2\dbch\af31505\loch\f2 definition with Output format}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf11\lang1024\langfe1024\noproof\insrsid8352301 +\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid8352301 \hich\af2\dbch\af31505\loch\f2 BITFNAM(nm,sz,names)}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid8084824 \tab }{\rtlch\fcs1 \af2 \ltrch\fcs0 +\f2\cf11\lang1024\langfe1024\noproof\insrsid8084824 -}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf11\lang1024\langfe1024\noproof\insrsid8352301 \hich\af2\dbch\af31505\loch\f2 Bit Field definition with va}{\rtlch\fcs1 \af2 \ltrch\fcs0 +\f2\cf11\lang1024\langfe1024\noproof\insrsid8084824 \hich\af2\dbch\af31505\loch\f2 lue->name map}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf11\lang1024\langfe1024\noproof\insrsid8352301 +\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid8352301 \hich\af2\dbch\af31505\loch\f2 ENDBITS +\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid16013944 +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\rin0\lin0\itap0\pararsid16013944 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid16013944\charrsid16013944 \hich\af1\dbch\af31505\loch\f1 For example: +\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\rin0\lin720\itap0\pararsid16013944 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid16013944 +\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf2\lang1024\langfe1024\noproof\insrsid16013944 \hich\af2\dbch\af31505\loch\f2 static}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid16013944 \hich\af2\dbch\af31505\loch\f2 }{\rtlch\fcs1 \af2 +\ltrch\fcs0 \f2\cf2\lang1024\langfe1024\noproof\insrsid16013944 \hich\af2\dbch\af31505\loch\f2 const}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid16013944 \hich\af2\dbch\af31505\loch\f2 }{\rtlch\fcs1 \af2 \ltrch\fcs0 +\f2\cf2\lang1024\langfe1024\noproof\insrsid16013944 \hich\af2\dbch\af31505\loch\f2 char}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid16013944 \hich\af2\dbch\af31505\loch\f2 *rp_fname[CS1_N_FNC] = \{ +\par \hich\af2\dbch\af31505\loch\f2 }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf17\lang1024\langfe1024\noproof\insrsid16013944 \hich\af2\dbch\af31505\loch\f2 "NOP"}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid16013944 +\hich\af2\dbch\af31505\loch\f2 , }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf17\lang1024\langfe1024\noproof\insrsid16013944 \hich\af2\dbch\af31505\loch\f2 "UNLD"}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid16013944 +\hich\af2\dbch\af31505\loch\f2 , }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf17\lang1024\langfe1024\noproof\insrsid16013944 \hich\af2\dbch\af31505\loch\f2 "SEEK"}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid16013944 +\hich\af2\dbch\af31505\loch\f2 , }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf17\lang1024\langfe1024\noproof\insrsid16013944 \hich\af2\dbch\af31505\loch\f2 "RECAL"}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid16013944 +\hich\af2\dbch\af31505\loch\f2 , }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf17\lang1024\langfe1024\noproof\insrsid16013944 \hich\af2\dbch\af31505\loch\f2 "DCLR"}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid16013944 +\hich\af2\dbch\af31505\loch\f2 , }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf17\lang1024\langfe1024\noproof\insrsid16013944 \hich\af2\dbch\af31505\loch\f2 "RLS"}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid16013944 +\hich\af2\dbch\af31505\loch\f2 , +\par \hich\af2\dbch\af31505\loch\f2 }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf17\lang1024\langfe1024\noproof\insrsid16013944 \hich\af2\dbch\af31505\loch\f2 "OFFS"}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid16013944 +\hich\af2\dbch\af31505\loch\f2 , }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf17\lang1024\langfe1024\noproof\insrsid16013944 \hich\af2\dbch\af31505\loch\f2 "RETN"}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid16013944 ,}{\rtlch\fcs1 \af2 +\ltrch\fcs0 \f2\cf17\lang1024\langfe1024\noproof\insrsid16013944 \hich\af2\dbch\af31505\loch\f2 "PRESET"}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid16013944 \hich\af2\dbch\af31505\loch\f2 , }{\rtlch\fcs1 \af2 \ltrch\fcs0 +\f2\cf17\lang1024\langfe1024\noproof\insrsid16013944 \hich\af2\dbch\af31505\loch\f2 "PACK"}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid16013944 \hich\af2\dbch\af31505\loch\f2 , }{\rtlch\fcs1 \af2 \ltrch\fcs0 +\f2\cf17\lang1024\langfe1024\noproof\insrsid16013944 \hich\af2\dbch\af31505\loch\f2 "SEARC\hich\af2\dbch\af31505\loch\f2 H"}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid16013944 \hich\af2\dbch\af31505\loch\f2 , +\par \hich\af2\dbch\af31505\loch\f2 }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf17\lang1024\langfe1024\noproof\insrsid16013944 \hich\af2\dbch\af31505\loch\f2 "WRCHK"}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid16013944 +\hich\af2\dbch\af31505\loch\f2 , }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf17\lang1024\langfe1024\noproof\insrsid16013944 \hich\af2\dbch\af31505\loch\f2 "WRITE"}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid16013944 +\hich\af2\dbch\af31505\loch\f2 , }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf17\lang1024\langfe1024\noproof\insrsid16013944 \hich\af2\dbch\af31505\loch\f2 "WRHDR"}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid16013944 +\hich\af2\dbch\af31505\loch\f2 , }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf17\lang1024\langfe1024\noproof\insrsid16013944 \hich\af2\dbch\af31505\loch\f2 "READ"}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid16013944 +\hich\af2\dbch\af31505\loch\f2 , }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf17\lang1024\langfe1024\noproof\insrsid16013944 \hich\af2\dbch\af31505\loch\f2 "RDHDR" +\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid16013944 \hich\af2\dbch\af31505\loch\f2 \}; +\par +\par \hich\af2\dbch\af31505\loch\f2 BITFIELD xx_csr_bits[] = \{ +\par \hich\af2\dbch\af31505\loch\f2 BIT(GO), }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf11\lang1024\langfe1024\noproof\insrsid16013944 \hich\af2\dbch\af31505\loch\f2 /* Go */ +\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid16013944 \hich\af2\dbch\af31505\loch\f2 BITFNAM(FUNC,5,rp_fname), }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf11\lang1024\langfe1024\noproof\insrsid16013944 +\hich\af2\dbch\af31505\loch\f2 /* Function Code */ +\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid16013944 \hich\af2\dbch\af31505\loch\f2 BIT(IE), }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf11\lang1024\langfe1024\noproof\insrsid16013944 +\hich\af2\dbch\af31505\loch\f2 /*\hich\af2\dbch\af31505\loch\f2 Interrupt Enable */ +\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid16013944 \hich\af2\dbch\af31505\loch\f2 BIT(RDY), }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf11\lang1024\langfe1024\noproof\insrsid16013944 +\hich\af2\dbch\af31505\loch\f2 /* Drive Ready */ +\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid16013944 \hich\af2\dbch\af31505\loch\f2 BIT(DVA), }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf11\lang1024\langfe1024\noproof\insrsid16013944 +\hich\af2\dbch\af31505\loch\f2 /* Drive Available */ +\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid16013944 \hich\af2\dbch\af31505\loch\f2 BITNCF(1), }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf11\lang1024\langfe1024\noproof\insrsid16013944 +\hich\af2\dbch\af31505\loch\f2 /* 12 Reserved */ +\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid16013944 \hich\af2\dbch\af31505\loch\f2 BIT(TRE), }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf11\lang1024\langfe1024\noproof\insrsid16013944 +\hich\af2\dbch\af31505\loch\f2 /\hich\af2\dbch\af31505\loch\f2 * Transfer Error */ +\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid16013944 \hich\af2\dbch\af31505\loch\f2 BIT(SC), }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf11\lang1024\langfe1024\noproof\insrsid16013944 +\hich\af2\dbch\af31505\loch\f2 /* Special Condition */ +\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid16013944 \hich\af2\dbch\af31505\loch\f2 ENDBITS +\par \}\hich\af2\dbch\af31505\loch\f2 ; +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid8129972 +\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid16013944 \hich\af1\dbch\af31505\loch\f1 The fields in a register can be displayed (along with transition indicators) by calling sim_debug_bits. +\par +\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\rin0\lin720\itap0\pararsid16013944 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf2\lang1024\langfe1024\noproof\insrsid8084824 \hich\af2\dbch\af31505\loch\f2 void}{\rtlch\fcs1 \af2 \ltrch\fcs0 +\f2\lang1024\langfe1024\noproof\insrsid8084824 \hich\af2\dbch\af31505\loch\f2 }{\rtlch\fcs1 \af2 \ltrch\fcs0 \b\f2\lang1024\langfe1024\noproof\insrsid8084824\charrsid16013944 \hich\af2\dbch\af31505\loch\f2 sim_debug_bits}{\rtlch\fcs1 \af2 \ltrch\fcs0 +\f2\lang1024\langfe1024\noproof\insrsid8084824 \hich\af2\dbch\af31505\loch\f2 (uint32 dbits, DEVICE* dptr, \hich\af2\dbch\af31505\loch\f2 BITFIELD* bitdefs, uint32 before, uint32 after, }{\rtlch\fcs1 \af2 \ltrch\fcs0 +\f2\cf2\lang1024\langfe1024\noproof\insrsid8084824 \hich\af2\dbch\af31505\loch\f2 int}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid8084824 \hich\af2\dbch\af31505\loch\f2 terminate); +\par {\*\bkmkstart _Toc345583835}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid3867041 \hich\af1\dbch\af31505\loch\f1 4.1.10\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar +\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0\pararsid3867041 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af1 \ltrch\fcs0 \insrsid3867041 \hich\af1\dbch\af31505\loch\f1 Device Specific Help support{\*\bkmkend _Toc345583835} +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0\pararsid7174065 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af1 \ltrch\fcs0 \f1\insrsid7174065 +\par \hich\af1\dbch\af31505\loch\f1 A device declaration may specify a device type or class in the flags field by providing one of DEV_DISK, DEV_TAPE, DEV_MUX, DEV_E\hich\af1\dbch\af31505\loch\f1 +THER or DEV_DISPLAY values when initializing the flags. The device type allows the scp HELP command routine to provide some default help information for devices which don\hich\f1 \rquote \loch\f1 +t otherwise specify a device specific help routine or a attach_help routine. +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7174065\charrsid7174065 +\par {\*\bkmkstart _Toc345583836}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid3867041 \hich\af1\dbch\af31505\loch\f1 4.1.11\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar +\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0\pararsid3867041 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af1 \ltrch\fcs0 \insrsid3867041 \hich\af1\dbch\af31505\loch\f1 Help Routine}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid14776269 {\*\bkmkend _Toc345583836} +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0\pararsid14776269 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af1 \ltrch\fcs0 \f1\insrsid14776269 +\par \hich\af1\dbch\af31505\loch\f1 \hich\f1 A device declaration may provide a routine which will display help about that device when a user enters a \'93\loch\f1 \hich\f1 HELP dev\'94\loch\f1 command.}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3867041 +\hich\af1\dbch\af31505\loch\f1 }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid14776269 +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\rin0\lin0\itap0\pararsid3867041 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf11\lang1024\langfe1024\noproof\insrsid3867041 +\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid14776269 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid14776269 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid3867041 +\hich\af1\dbch\af31505\loch\f1 help}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid14776269 \hich\af1\dbch\af31505\loch\f1 (}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3867041 \hich\af1\dbch\af31505\loch\f1 FILE}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid14776269 +\hich\af1\dbch\af31505\loch\f1 }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3867041 \hich\af1\dbch\af31505\loch\f1 *st, DEVICE }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid14776269 \hich\af1\dbch\af31505\loch\f1 *}{\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid3867041 \hich\af1\dbch\af31505\loch\f1 d}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid14776269 \hich\af1\dbch\af31505\loch\f1 ptr,}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3867041 \hich\af1\dbch\af31505\loch\f1 UNIT *uptr, }{\rtlch\fcs1 \af1 +\ltrch\fcs0 \f1\insrsid14776269 \hich\af1\dbch\af31505\loch\f1 int32 }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3867041 \hich\af1\dbch\af31505\loch\f1 flag}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid14776269 \hich\af1\dbch\af31505\loch\f1 , char *cptr) +\hich\f1 \endash \loch\f1 }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3867041 \hich\af1\dbch\af31505\loch\f1 Write h\hich\af1\dbch\af31505\loch\f1 elp information about the device and/or unit usage. }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid14776269 +\hich\af1\dbch\af31505\loch\f1 The }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3867041 \hich\af1\dbch\af31505\loch\f1 flag and }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid14776269 \hich\af1\dbch\af31505\loch\f1 cptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid3867041 \hich\af1\dbch\af31505\loch\f1 }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid14776269 \hich\af1\dbch\af31505\loch\f1 arguments are included for compatibility with the }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3867041 +\hich\af1\dbch\af31505\loch\f1 HELP }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid14776269 \hich\af1\dbch\af31505\loch\f1 command\hich\f1 \rquote \loch\f1 s validation routine calling sequence. +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0\pararsid14776269 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid14776269 +\par {\*\bkmkstart _Toc345583837}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid14776269 \hich\af1\dbch\af31505\loch\f1 4.1.12\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar +\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0\pararsid14776269 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af1 \ltrch\fcs0 \insrsid14776269 \hich\af1\dbch\af31505\loch\f1 Attach Help Routine{\*\bkmkend _Toc345583837} +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0\pararsid14776269 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af1 \ltrch\fcs0 \f1\insrsid14776269 +\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3867041 \hich\af1\dbch\af31505\loch\f1 A device declaration may pro\hich\af1\dbch\af31505\loch\f1 vide a routine which will display help about h}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid14776269 +\hich\af1\dbch\af31505\loch\f1 ORE to use if memory size must be changed: +\par +\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid3867041 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3867041 \hich\af1\dbch\af31505\loch\f1 t_stat attach_}{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid3867041 +\hich\af1\dbch\af31505\loch\f1 help}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3867041 \hich\af1\dbch\af31505\loch\f1 (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr) \hich\f1 \endash \loch\f1 + Write help information about the device and/or unit attach usage. The flag and }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid3867041 \hich\af1\dbch\af31505\loch\f1 cptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3867041 \hich\af1\dbch\af31505\loch\f1 + arguments are included for compatibility with the HELP command\hich\f1 \rquote \loch\f1 s validation routine calling sequence. +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0\pararsid14776269 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid14776269 +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid8084824 +\par {\*\bkmkstart _Toc345583838}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.2\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar +\jclisttab\tx390\wrapdefault\faauto\ls1\ilvl1\outlinelevel1\adjustright\rin0\lin390\itap0 \rtlch\fcs1 \ab\ai\af1\afs24\alang1025 \ltrch\fcs0 \b\i\fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_unit Structure{\*\bkmkend _Toc345583838} +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 +\b\f1\insrsid4550150 +\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Units are allocated as contiguous array. Each unit is defined with a }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_unit}{ +\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 structure (typedef }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 UNI\hich\af1\dbch\af31505\loch\f1 T}{\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 ): +\par +\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 struct sim_unit \{ +\par \tab \hich\af1\dbch\af31505\loch\f1 struct sim_unit\tab *next;\tab \tab \tab \tab /* next active */ +\par \tab \hich\af1\dbch\af31505\loch\f1 t_stat\tab \tab (*action)();\tab \tab \tab /* action routine */ +\par \tab \hich\af1\dbch\af31505\loch\f1 char\tab \tab *filename;\tab \tab \tab /* open file name */ +\par \tab \hich\af1\dbch\af31505\loch\f1 FILE\tab \tab *fileref;\tab \tab \tab \tab /* file reference */ +\par \tab \hich\af1\dbch\af31505\loch\f1 void\tab \tab *filebuf;\tab \tab \tab \tab /* memory buffer */ +\par \tab \hich\af1\dbch\af31505\loch\f1 uint32\tab \tab hwmark;\tab \tab \tab \hich\af1\dbch\af31505\loch\f1 /* high water mark */ +\par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab time;\tab \tab \tab \tab /* time out */ +\par \tab \hich\af1\dbch\af31505\loch\f1 uint32\tab \tab flags;\tab \tab \tab \tab /* flags */ +\par \tab \hich\af1\dbch\af31505\loch\f1 t_addr\tab \tab capac;\tab \tab \tab \tab /* capacity */ +\par \tab \hich\af1\dbch\af31505\loch\f1 t_addr\tab \tab pos;\tab \tab \tab \tab /* file position */ +\par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab buf;\tab \tab \tab \tab /* buffer */ +\par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab wait;\tab \tab \tab \tab /* wait */ +\par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab u3;\tab \tab \tab \tab /* device specific */ +\par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab \hich\af1\dbch\af31505\loch\f1 u4;\tab \tab \tab \tab /* device specific */ +\par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab u5;\tab \tab \tab \tab /* device specific */ +\par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab u6;\tab \tab \tab \tab /* device specific */ +\par }\pard \ltrpar\ql \fi720\li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \}\hich\af1\dbch\af31505\loch\f1 ; +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 The fields are the following: +\par +\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 next}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab +\hich\af1\dbch\af31505\loch\f1 pointer to next unit in active queue, NULL if none. +\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 action}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 address of unit time-out service routine. +\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 filename}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 pointer to name of attached file, NULL if none. +\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 fileref}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 pointer to FILE structure of attached file, NULL if none. +\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 hwmark}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 buffered devices only; highest modified address, + 1. +\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 time}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 increment until time-out beyond previous unit in active queue. +\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 flags}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 uni\hich\af1\dbch\af31505\loch\f1 t flags. +\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 capac}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 unit capacity, 0 if variable. +\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 pos}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 sequential devices only; next device address to be read or written. +\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 buf}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 by convention, the unit buffer, but can be used for other purposes. +\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 wait}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 by convention, the unit wait time, but can be used for oth +\hich\af1\dbch\af31505\loch\f1 er purposes. +\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 u3}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 user-defined. +\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 u4}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 user-defined. +\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 u5\tab \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 user-defined. +\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 u6\tab \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 user-defined. +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 buf, wait, u3, u4, u5, u6, }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 and parts of }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 flags}{ +\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 are all saved and restored by the SAVE and RESTORE commands and thus can be used for unit state which must be preserved. +\par +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\outlinelevel0\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Macro }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 UDATA}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 is available to fill in the common fields of a UNIT. It is invoked by +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par \tab \hich\af1\dbch\af31505\loch\f1 UDATA\tab \tab (action_routine, flags, capacity) +\par +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\outlinelevel0\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Fields after }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 buf}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 can be filled in manually, e.g, +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\outlinelevel0\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \tab \hich\af2\dbch\af31505\loch\f2 UNIT lpt_unit = +\par }\pard \ltrpar\ql \fi720\li720\ri0\widctlpar\wrapdefault\faauto\outlinelevel0\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \{\hich\af2\dbch\af31505\loch\f2 UDATA (&lpt_svc, UNIT_SEQ+UNIT_ATTABLE, 0), 500 \}; +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 defines\hich\af1\dbch\af31505\loch\f1 the line printer as a sequential unit with a wait time of 500. +\par {\*\bkmkstart _Toc345583839}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.2.1\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar +\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Unit Flags{\*\bkmkend _Toc345583839} +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 The }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 flags }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 +field contains indicators of current unit status. SIMH defines 12 flags: +\par +\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 flag name\tab \tab meaning if set +\par +\par \hich\af1\dbch\af31505\loch\f1 UNIT_ATTABLE\tab the unit responds to AT\hich\af1\dbch\af31505\loch\f1 TACH and DETACH. +\par \hich\af1\dbch\af31505\loch\f1 UNIT_RO\tab \tab the unit is currently read only. +\par \hich\af1\dbch\af31505\loch\f1 UNIX_FIX\tab \tab the unit is fixed capacity. +\par \hich\af1\dbch\af31505\loch\f1 UNIT_SEQ\tab \tab the unit is sequential. +\par \hich\af1\dbch\af31505\loch\f1 UNIT_ATT\tab \tab the unit is currently attached to a file. +\par \hich\af1\dbch\af31505\loch\f1 UNIT_BINK\tab \tab \hich\f1 the unit measures \'93\loch\f1 \hich\f1 K\'94\loch\f1 as 1024, rather than 1000. +\par \hich\af1\dbch\af31505\loch\f1 UNIT_BUFABLE\tab \hich\af1\dbch\af31505\loch\f1 the unit buffers its data set in memory. +\par \hich\af1\dbch\af31505\loch\f1 UNIT_MUSTBUF\tab the unit allocates its data buffer dynamically. +\par \hich\af1\dbch\af31505\loch\f1 UNIT_BUF\tab \tab the unit is currently buffering its data set in memory. +\par \hich\af1\dbch\af31505\loch\f1 UNIT_ROABLE\tab \tab the unit can be ATTACHed read only. +\par \hich\af1\dbch\af31505\loch\f1 UNIT_DISABLE\tab \tab the unit responds \hich\af1\dbch\af31505\loch\f1 to ENABLE and DISABLE. +\par \hich\af1\dbch\af31505\loch\f1 UNIT_DIS\tab \tab the unit is currently disabled. +\par \hich\af1\dbch\af31505\loch\f1 UNIT_RAW\tab \tab the unit is attached in RAW mode. +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 Starting at bit position UNIT_V_UF, the remaining flags are unit-specific. Unit-specific flags are set and cleared with the SET and CLEAR command\hich\af1\dbch\af31505\loch\f1 +s, which reference the MTAB array (see below). Unit-specific flags and UNIT_DIS are automatically saved and restored; the device need not supply a register for these bits. +\par {\*\bkmkstart _Toc345583840}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.2.2\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar +\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Service Routine{\*\bkmkend _Toc345583840} +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 This routine is called by }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_proc\hich\af1\dbch\af31505\loch\f1 ess_event}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 when a unit times out. Its calling sequence is: +\par +\par }\pard \ltrpar\ql \fi720\li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 service_routine}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (UNIT *uptr) +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\outlinelevel0\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 The status returned by the service routine is passed by }{\rtlch\fcs1 +\ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_process_event}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 back to the CPU. +\par {\*\bkmkstart _Toc345583841}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.3\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar +\jclisttab\tx390\wrapdefault\faauto\ls1\ilvl1\outlinelevel1\adjustright\rin0\lin390\itap0 \rtlch\fcs1 \ab\ai\af1\afs24\alang1025 \ltrch\fcs0 \b\i\fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_reg Structure{\*\bkmkend _Toc345583841} +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 +\b\f1\insrsid4550150 +\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Registers are alloc\hich\af1\dbch\af31505\loch\f1 ated as contiguous array, with a NULL register at the end. Each register is defined with a }{\rtlch\fcs1 \ab\af1 +\ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_reg}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 structure (typedef }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 REG}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 ): +\par +\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 struct reg \{ +\par \tab \hich\af1\dbch\af31505\loch\f1 char\tab \tab *name;\tab \tab \tab \tab /* name */ +\par \tab \hich\af1\dbch\af31505\loch\f1 void\tab \tab *loc;\tab \tab \tab \tab /* location */ +\par \tab \hich\af1\dbch\af31505\loch\f1 uint32\tab \tab radix;\tab \tab \tab \tab /* radix */ +\par \tab \hich\af1\dbch\af31505\loch\f1 uint32\tab \tab width;\tab \tab \tab \tab /* width\hich\af1\dbch\af31505\loch\f1 */ +\par \tab \hich\af1\dbch\af31505\loch\f1 uint32\tab \tab offset;\tab \tab \tab \tab /* starting bit */ +\par \tab \hich\af1\dbch\af31505\loch\f1 uint32\tab \tab depth;\tab \tab \tab \tab /* save depth */ +\par \tab \hich\af1\dbch\af31505\loch\f1 uint32\tab \tab flags;\tab \tab \tab \tab /* flags */ +\par \tab \hich\af1\dbch\af31505\loch\f1 uint32\tab \tab qptr;\tab \tab \tab \tab /* current queue pointer */ +\par }\pard \ltrpar\ql \fi720\li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \}\hich\af1\dbch\af31505\loch\f1 ; +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 The fields are the following: +\par +\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 name}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab +\hich\af1\dbch\af31505\loch\f1 device name, string of all capital alphanumeric characters. +\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 loc}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 pointer to location of the register value. +\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 radix}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 radix for input and display of data, 2 to 16 inclusive. +\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 width}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 width in bits of data, 1 to 32 inclusive. +\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 width\tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 bit offset (from right end of data). +\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 depth\tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 size of data array (normally 1). +\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 flags}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 flag\hich\af1\dbch\af31505\loch\f1 s and formatting information. +\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 qptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 for a circular queue, the entry number for the first entry +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 The }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 depth}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 \hich\f1 field is used with \'93\loch\f1 +\hich\f1 arrayed registers\'94\hich\af1\dbch\af31505\loch\f1 +. Arrayed registers are used to represent structures with multiple data values, such as the locations in a transfer buffer; or structures which are replicated in every unit, such as a drive status register. The }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 +\b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 qptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 \hich\f1 field is used with \'93\loch\f1 \hich\f1 queued registers\'94.\hich\af1\dbch\af31505\loch\f1 + Queued registers are arrays that are organized as circular queues, such as the PC change queue. +\par +\par \hich\af1\dbch\af31505\loch\f1 A register that is 32b or less keeps its data in a 32b scalar variable (signed or unsigned). A register that is 33b or more keeps its data in a 64b scalar v\hich\af1\dbch\af31505\loch\f1 +ariable (signed or unsigned). There are several exceptions to this rule: +\par +\par {\listtext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault\faauto\ls27\adjustright\rin0\lin720\itap0 { +\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 +An arrayed register keeps its data in a C-array whose SIMH data type is as large as (or if necessary, larger than), the width of a register element. For example, an array of 6b r\hich\af1\dbch\af31505\loch\f1 +egisters would keep its data in a uint8 (or int8) array; an array of 16b registers would keep its data in a uint16 (or int16) array; an array of 24b registers would keep its data in a uint32 (or int32) array. +\par {\listtext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}\hich\af1\dbch\af31505\loch\f1 A register flagged with REG_FIT obeys the siz\hich\af1\dbch\af31505\loch\f1 +ing rules of an arrayed register, rather than a normal scalar register. This is useful for aliasing registers into memory or into structures. +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 Macros }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 ORDATA}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 , }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 +\b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 DRDATA}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 , and }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 HRDATA}{\rtlch\fcs1 +\af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 define right-justified octal, decimal, and hexidecimal registers, respectively\hich\af1\dbch\af31505\loch\f1 . They are invoked by: +\par +\par \tab \hich\af1\dbch\af31505\loch\f1 xRDATA\tab (name, location, width) +\par +\par \hich\af1\dbch\af31505\loch\f1 Macro }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 FLDATA}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 + defines a one-bit binary flag at an arbitrary offset in a 32-bit word. It is invoked by: +\par +\par \tab \hich\af1\dbch\af31505\loch\f1 FLDATA\tab (name, location, bit_position) +\par +\par \hich\af1\dbch\af31505\loch\f1 Macro }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 GRDATA}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 defines a register with arbitrary locatio +\hich\af1\dbch\af31505\loch\f1 n and radix. It is invoked by: +\par +\par \tab \hich\af1\dbch\af31505\loch\f1 GRDATA\tab (name, location, radix, width, bit_position) +\par +\par \hich\af1\dbch\af31505\loch\f1 Macro }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 BRDATA}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 + defines an arrayed register whose data is kept in a standard C array. It is invoked by: +\par +\par \tab \hich\af1\dbch\af31505\loch\f1 BRDATA\tab (name, location, radix, width, depth) +\par +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\outlinelevel0\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 For all of these ma\hich\af1\dbch\af31505\loch\f1 cros, the }{\rtlch\fcs1 +\ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 flag}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 field can be filled in manually, e.g., +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\outlinelevel0\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \tab \hich\af2\dbch\af31505\loch\f2 REG lpt_reg = \{ +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \tab \tab \{\hich\af2\dbch\af31505\loch\f2 DRDATA\tab (POS, lpt_unit.pos, 31), PV_LFT \}\hich\f2 , \'85\loch\f2 \} + +\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 Finally, macro }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 URDATA}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 + defines an arrayed register whose data is part of the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 UNIT}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 + structure. This macro must be used with great care.\hich\af1\dbch\af31505\loch\f1 If the fields are set up wrong, or the data is actually kept somewhere else, storing through this register declaration can trample over memory. The macro is invoked by: + +\par +\par \tab \hich\af1\dbch\af31505\loch\f1 URDATA\tab (name, location, radix, width, offset, depth, flags) +\par +\par \hich\af1\dbch\af31505\loch\f1 The location should b\hich\af1\dbch\af31505\loch\f1 e an offset in the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 UNIT }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 structure for unit 0. The width should be 32 for an int32 or uint32 field, and T_ADDR_W for a t_addr filed. The flags can be any of the normal register flags; REG_UNIT will be OR\hich\f1 \rquote \loch\f1 +d in automatically. For example, the following dec\hich\af1\dbch\af31505\loch\f1 lares an arrayed register of all the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 UNIT }{\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 position fields in a device with 4 units: +\par +\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \tab \{\hich\af2\dbch\af31505\loch\f2 URDATA\tab (POS, dev_unit[0].pos, 8, T_ADDR_W, 0, 4, 0) \} +\par {\*\bkmkstart _Toc345583842}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.3.1\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar +\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Register Flags{\*\bkmkend _Toc345583842} +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\outlinelevel0\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 The }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 flags }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 field contains indicators that control register examinat\hich\af1\dbch\af31505\loch\f1 ion and deposit. +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 flag name\tab \tab meaning if specified +\par +\par \hich\af1\dbch\af31505\loch\f1 PV_RZRO\tab \tab print register right justified with leading zeroes. +\par \hich\af1\dbch\af31505\loch\f1 PV_RSPC\tab \tab print register right justified with leading spaces. +\par \hich\af1\dbch\af31505\loch\f1 PV_LEFT\tab \tab print register left justified. +\par \hich\af1\dbch\af31505\loch\f1 REG_RO\tab \tab register is read only. +\par \hich\af1\dbch\af31505\loch\f1 REG_HIDDEN\tab \tab \hich\af1\dbch\af31505\loch\f1 register is hidden (will not appear in EXAMINE STATE). +\par \hich\af1\dbch\af31505\loch\f1 REG_HRO\tab \tab register is read only and hidden. +\par \hich\af1\dbch\af31505\loch\f1 REG_NZ\tab \tab new register values must be non-zero. +\par \hich\af1\dbch\af31505\loch\f1 REG_UNIT\tab \tab register resides in the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 UNIT}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 structure. + +\par \hich\af1\dbch\af31505\loch\f1 REG_CIRC\tab \tab register is a circular queue. +\par \hich\af1\dbch\af31505\loch\f1 REG_VMIO\tab \tab register is \hich\af1\dbch\af31505\loch\f1 displayed and parsed using VM data routines. +\par \hich\af1\dbch\af31505\loch\f1 REG_VMAD\tab \tab register is displayed and parsed using VM address routines. +\par \hich\af1\dbch\af31505\loch\f1 REG_FIT\tab \tab register container uses arrayed rather than scalar size rules. +\par {\*\bkmkstart _Toc345583843}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.4\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar +\jclisttab\tx390\wrapdefault\faauto\ls1\ilvl1\outlinelevel1\adjustright\rin0\lin390\itap0 \rtlch\fcs1 \ab\ai\af1\afs24\alang1025 \ltrch\fcs0 \b\i\fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_mtab Structure{\*\bkmkend _Toc345583843} +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 +\b\f1\insrsid4550150 +\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Device-specific SHO\hich\af1\dbch\af31505\loch\f1 +W and SET commands are processed using the modifications array, which is allocated as contiguous array, with a NULL at the end. Each possible modification is defined with a }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 sim_mtab}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 structure (synonym }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 MTAB}{\rtlch\fcs1 \af1 +\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 ), which has the following fields: +\par +\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 struct sim_mta\hich\af1\dbch\af31505\loch\f1 b \{ +\par \tab \hich\af1\dbch\af31505\loch\f1 uint32\tab \tab mask;\tab \tab \tab \tab /* mask */ +\par \tab \hich\af1\dbch\af31505\loch\f1 uint32\tab \tab match;\tab \tab \tab \tab /* match */ +\par \tab \hich\af1\dbch\af31505\loch\f1 char\tab \tab *pstring;\tab \tab \tab /* print string */ +\par \tab \hich\af1\dbch\af31505\loch\f1 char\tab \tab *mstring;\tab \tab \tab /* match string */ +\par \tab \hich\af1\dbch\af31505\loch\f1 t_stat\tab \tab (*valid)();\tab \tab \tab /* validation routine */ +\par \tab \hich\af1\dbch\af31505\loch\f1 t_stat\tab \tab (*disp)();\tab \tab \tab /* display routine */ +\par \tab \hich\af1\dbch\af31505\loch\f1 void\tab \tab *desc}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 ;\tab \tab \tab \tab /}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 * loca +\hich\af1\dbch\af31505\loch\f1 tion descriptor */ +\par }\pard \ltrpar\ql \fi720\li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \}\hich\af1\dbch\af31505\loch\f1 ; +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 MTAB supports two different structure interpretations: regular and extended. A regular MTAB entry modifies flags in the UNIT flags word; the descriptor entry is not used. The fields are the following: +\par +\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 mask}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab +\hich\af1\dbch\af31505\loch\f1 bit mask for testing th\hich\af1\dbch\af31505\loch\f1 e unit.}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 flags}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 field +\par }\pard \ltrpar\ql \fi-1440\li2160\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin2160\itap0 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 match}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab +\hich\af1\dbch\af31505\loch\f1 value to be stored (SET) or compared (SHOW) +\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 pstring}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 pointer to character string printed on a match (SHOW), or NULL +\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 mstring}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 pointer to character string to be matched (SET), or NULL +\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 valid}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 address of validation routine (SET), or NULL +\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 disp\tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 address of display routine (SHOW), or NULL +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 +\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 For SET, a regular MTAB entry is interpreted as follows: +\par +\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f1\fs20\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 1.\tab}}\pard \ltrpar\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlbody\ilvl0\ls20\pnrnot0 +\pndec\pnstart1\pnindent360\pnsp120\pnhang {\pntxta .}}\faauto\ls20\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Test to see if the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 mstring}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 entry exists. +\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f1\fs20\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 2.\tab}}\pard \ltrpar\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlbody\ilvl0\ls20\pnrnot0 +\pndec\pnstart1\pnindent360\pnsp120\pnhang {\pntxta .}}\faauto\ls20\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Test to see if the SET parameter matches the }{\rtlch\fcs1 \ab\af1 +\ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 mstring}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 . +\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f1\fs20\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 3.\tab}}\pard \ltrpar\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlbody\ilvl0\ls20\pnrnot0 +\pndec\pnstart1\pnindent360\pnsp120\pnhang {\pntxta .}}\faauto\ls20\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Call the validation routine, if any. +\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f1\fs20\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.\tab}}\pard \ltrpar\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlbody\ilvl0\ls20\pnrnot0 +\pndec\pnstart1\pnindent360\pnsp120\pnhang {\pntxta .}}\faauto\ls20\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Apply the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 mask}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 value to the UNIT flags word and then or in the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 +match}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 value. +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 For SHOW, a regular MTAB entry is interpreted as follows: +\par +\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f1\fs20\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 1.\tab}}\pard \ltrpar\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlbody\ilvl0\ls21\pnrnot0 +\pndec\pnstart1\pnindent360\pnsp120\pnhang {\pntxta .}}\faauto\ls21\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Test to see if the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 pstring}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 entry exists. +\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f1\fs20\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 2.\tab}}\pard \ltrpar\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlbody\ilvl0\ls21\pnrnot0 +\pndec\pnstart1\pnindent360\pnsp120\pnhang {\pntxta .}}\faauto\ls21\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Test to see if the UNIT flags word, masked with the }{\rtlch\fcs1 \ab\af1 +\ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 mask}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 value, equals\hich\af1\dbch\af31505\loch\f1 the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 match}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 value. +\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f1\fs20\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 3.\tab}}\pard \ltrpar\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlbody\ilvl0\ls21\pnrnot0 +\pndec\pnstart1\pnindent360\pnsp120\pnhang {\pntxta .}}\faauto\ls21\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 If a display routine exists, call it, otherwise +\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f1\fs20\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.\tab}}\pard \ltrpar\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlbody\ilvl0\ls21\pnrnot0 +\pndec\pnstart1\pnindent360\pnsp120\pnhang {\pntxta .}}\faauto\ls21\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Print the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 pstring}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 . +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 Extended MTAB entries have a different interpretation: +\par +\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 mask}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab +\hich\af1\dbch\af31505\loch\f1 entry flags +\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \tab \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 MTAB_XTD\tab extended entry +\par \tab \tab \hich\af1\dbch\af31505\loch\f1 MTAB_VDV\tab valid for devices +\par \tab \tab \hich\af1\dbch\af31505\loch\f1 MTAB_VUN\tab valid for units +\par \tab \tab \hich\af1\dbch\af31505\loch\f1 MTAB_VAL\tab takes a value +\par \tab \tab \hich\af1\dbch\af31505\loch\f1 MTAB_NMO\tab valid only in named SHOW +\par \tab \tab \hich\af1\dbch\af31505\loch\f1 MTAB_NC\tab do not convert option value to upper case +\par \tab \tab \hich\af1\dbch\af31505\loch\f1 MTAB_SHP\tab SHOW parameter takes optional value +\par }\pard \ltrpar\ql \fi-1440\li2160\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin2160\itap0 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 match}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab +\hich\af1\dbch\af31505\loch\f1 value to be stored (SET) +\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 pstring}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 pointer to character string printed on a match (SHOW), or N +\hich\af1\dbch\af31505\loch\f1 ULL +\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 mstring}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 pointer to character string to be matched (SET), or NULL +\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 valid}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 address of validation routine (SET), or NULL +\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 disp\tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 address of display routine (SHOW), or NULL +\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 desc\tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 pointer to a REG structure (MTAB_VAL set) or +\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 a validation-specific structure (MTAB\hich\af1\dbch\af31505\loch\f1 _VAL clear) +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 For SET, an extended MTAB entry is interpreted as follows: +\par +\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f1\fs20\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 1.\tab}}\pard \ltrpar\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlbody\ilvl0\ls22\pnrnot0 +\pndec\pnstart1\pnindent360\pnsp120\pnhang {\pntxta .}}\faauto\ls22\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Test to see if the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 mstring}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 entry exists. +\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f1\fs20\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 2.\tab}}\pard \ltrpar\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlbody\ilvl0\ls22\pnrnot0 +\pndec\pnstart1\pnindent360\pnsp120\pnhang {\pntxta .}}\faauto\ls22\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Test to see if the SET parameter matches the }{\rtlch\fcs1 \ab\af1 +\ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 mstring}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 . +\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f1\fs20\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 3.\tab}}\pard \ltrpar\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlbody\ilvl0\ls22\pnrnot0 +\pndec\pnstart1\pnindent360\pnsp120\pnhang {\pntxta .}}\faauto\ls22\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Test to see if the entry is valid for the type of SET being done (SET device +\hich\af1\dbch\af31505\loch\f1 or SET unit). +\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f1\fs20\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.\tab}}\pard \ltrpar\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlbody\ilvl0\ls22\pnrnot0 +\pndec\pnstart1\pnindent360\pnsp120\pnhang {\pntxta .}}\faauto\ls22\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 +If a validation routine exists, call it and return its status. The validation routine is responsible for storing the result. +\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f1\fs20\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 5.\tab}}\pard \ltrpar\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlbody\ilvl0\ls22\pnrnot0 +\pndec\pnstart1\pnindent360\pnsp120\pnhang {\pntxta .}}\faauto\ls22\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 If }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 desc}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 is NULL, exit. +\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f1\fs20\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 6.\tab}}\pard \ltrpar\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlbody\ilvl0\ls22\pnrnot0 +\pndec\pnstart1\pnindent360\pnsp120\pnhang {\pntxta .}}\faauto\ls22\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 \hich\f1 If MTAB_VAL is set, parse the SET option for \'93\loch\f1 \hich\f1 +option=n\'94\loch\f1 , and store the value n \hich\af1\dbch\af31505\loch\f1 in the register described by }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 desc}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 . +\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f1\fs20\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 7.\tab}}\pard \ltrpar\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlbody\ilvl0\ls22\pnrnot0 +\pndec\pnstart1\pnindent360\pnsp120\pnhang {\pntxta .}}\faauto\ls22\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Otherwise, store the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 match}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 value in the int32 pointed to by }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 desc}{\rtlch\fcs1 +\af1 \ltrch\fcs0 \f1\insrsid4550150 . +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 For SHOW, an extended MTAB entry is interpreted as follows: +\par +\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f1\fs20\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 1.\tab}}\pard \ltrpar\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlbody\ilvl0\ls23\pnrnot0 +\pndec\pnstart1\pnindent360\pnsp120\pnhang {\pntxta .}}\faauto\ls23\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Test to see if the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 pstring}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 entry exists. +\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f1\fs20\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 2.\tab}}\pard \ltrpar\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlbody\ilvl0\ls23\pnrnot0 +\pndec\pnstart1\pnindent360\pnsp120\pnhang {\pntxta .}}\faauto\ls23\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Test to see if the entry is valid for th\hich\af1\dbch\af31505\loch\f1 +e type of SHOW being done (device or unit). +\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f1\fs20\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 3.\tab}}\pard \ltrpar\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlbody\ilvl0\ls23\pnrnot0 +\pndec\pnstart1\pnindent360\pnsp120\pnhang {\pntxta .}}\faauto\ls23\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 If a display routine exists, call it, otherwise, +\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f1\fs20\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.\tab}}\pard \ltrpar\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlbody\ilvl0\ls23\pnrnot0 +\pndec\pnstart1\pnindent360\pnsp120\pnhang {\pntxta .}}\faauto\ls23\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 \hich\f1 If MTAB_VAL is set, print \'93\loch\f1 \hich\f1 pstring=n\'94 +\loch\f1 , where the value, radix, and width are taken from the register described by }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 desc}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 , otherwise, +\par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f1\fs20\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 5.\tab}}\pard \ltrpar\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlbody\ilvl0\ls23\pnrnot0 +\pndec\pnstart1\pnindent360\pnsp120\pnhang {\pntxta .}}\faauto\ls23\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Print the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 pstring}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 . +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 SHOW [dev|unit] \{=\} is a special case. Only two kinds of modifiers can be displayed individually: an extended MTAB entry that takes a value; and any MTAB entry with both a display routine and a }{ +\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 pstring}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 . Recall that if a display routine e\hich\af1\dbch\af31505\loch\f1 +xists, SHOW does not use the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 pstring}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 entry. For displaying a named modifier, }{ +\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 pstring}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 + is used as the string match. This allows implementation of complex display routines that are only invoked by name, e.g., +\par +\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \tab \hich\af2\dbch\af31505\loch\f2 MTAB cpu_tab[] = \{ +\par \tab \tab \{\hich\af2\dbch\af31505\loch\f2 \hich\f2 mask, value, \'93\loch\f2 \hich\f2 normal\'94\loch\f2 , \loch\af2\dbch\af31505\hich\f2 \'93\loch\f2 \hich\f2 NORMAL\'94\loch\f2 , NULL, NULL, NULL \}, +\par \tab \tab \{\hich\af2\dbch\af31505\loch\f2 \hich\f2 MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, \'93\loch\f2 \hich\f2 SPECIAL\'94, +\par }\pard \ltrpar\ql \fi720\li1440\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin1440\itap0 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \hich\af2\dbch\af31505\loch\f2 NULL, NULL, NULL, &spec_disp \}, +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \tab \tab \{\hich\af2\dbch\af31505\loch\f2 0 \} +\par }\pard \ltrpar\ql \fi720\li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \}\hich\af2\dbch\af31505\loch\f2 ; +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 A SHOW CPU command will display only the modifier named NORMAL; but SHOW CPU SPECIAL will invoke the special display routine. +\par {\*\bkmkstart _Toc345583844}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.4.1\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar +\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Validation Routine{\*\bkmkend _Toc345583844} +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 The validation routine can be used to validate input during SET processing. It can make other state changes required by the modification or initiate additional dialogs needed by the modifier. Its calling sequence +\hich\af1\dbch\af31505\loch\f1 is: +\par +\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 validation_routine}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (UNIT *uptr, int32 value, char *cptr, void *desc) \hich\f1 \endash \loch\f1 test that }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 +\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 .}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 flags}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 can be set to }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 value}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 . }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 +\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 cptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 points to the value portion of the parameter string (any characters after the = sign); if }{\rtlch\fcs1 \ai\af1 +\ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 cptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 is NULL, no value was given. \hich\af1\dbch\af31505\loch\f1 }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 +\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 desc}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 points to the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 REG}{\rtlch\fcs1 +\af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 or int32 used to store the parameter. +\par {\*\bkmkstart _Toc345583845}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.4.2\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar +\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Display Routine{\*\bkmkend _Toc345583845} +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 The display routine is called during SHOW processing to display device- or unit-specific state. Its calling sequence is: +\par +\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 display_routine}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (FILE *st, UNIT *uptr, int value, void *desc) \hich\f1 \endash \loch\f1 output device- or unit-specific state for }{ +\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 to stream }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 st}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 . If the modifier is regular MTAB entry, or an extended entry without MTAB_SHP set, }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 desc}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 points to the structure in the MTAB entry. If the modifie\hich\af1\dbch\af31505\loch\f1 r is an extended MTAB entry with MTAB_SHP set, }{ +\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 desc}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 points to the optional value string or is NULL if no value was supplied. }{ +\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 value}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 is the value field of the matched MTAB entry. +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 When the display routine is called for a regular MTAB entry, SHOW has output the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 pstring}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 argument but has not appended a newline. When it is called for an extended MTAB entry, SHOW hasn\hich\f1 \rquote \loch\f1 t output anything. SHOW will append a newline after the display rout\hich\af1\dbch\af31505\loch\f1 +ine returns, except for entries with the MTAB_NMO flag set. +\par {\*\bkmkstart _Toc345583846}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.5\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar +\jclisttab\tx390\wrapdefault\faauto\ls1\ilvl1\outlinelevel1\adjustright\rin0\lin390\itap0 \rtlch\fcs1 \ab\ai\af1\afs24\alang1025 \ltrch\fcs0 \b\i\fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Other Data Structures{\*\bkmkend _Toc345583846} +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 char }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_name[]}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 + is a character array containing the VM name. +\par +\par \hich\af1\dbch\af31505\loch\f1 int32 }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_emax}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 + contains the maximum number of words needed to hold the largest in\hich\af1\dbch\af31505\loch\f1 struction or data item in the VM. Examine and deposit will process up to }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 sim_emax}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 words. +\par +\par \hich\af1\dbch\af31505\loch\f1 DEVICE *}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_devices[]}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 + is an array of pointers to all the devices in the VM. It is terminated by a NULL. By convention, the CPU is always the first device in the ar\hich\af1\dbch\af31505\loch\f1 ray. +\par +\par \hich\af1\dbch\af31505\loch\f1 REG *}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_PC}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 points to the }{\rtlch\fcs1 \ab\af1 +\ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 reg}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 structure for the program counter. By convention, the PC is always the first register in the CPU\hich\f1 +\rquote \loch\f1 s register array. +\par +\par \hich\af1\dbch\af31505\loch\f1 char *}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_stop_messages[]}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 + is an array of pointers to character strings, corresponding to error status r\hich\af1\dbch\af31505\loch\f1 eturns greater than zero. If }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_instr}{\rtlch\fcs1 \af1 +\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 returns status code n > 0, then }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_stop_message[n]}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 is printed by SCP. +\par +\par {\*\bkmkstart _Toc345583847}{\listtext\pard\plain\ltrpar \s1 \rtlch\fcs1 \ab\af0\afs28 \ltrch\fcs0 \b\f1\fs28\kerning28\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 5.\tab}}\pard\plain \ltrpar\s1\ql \fi-360\li360\ri0\sb240\sa60\keepn\widctlpar +\jclisttab\tx360\wrapdefault\faauto\ls1\outlinelevel0\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 \b\fs28\lang1033\langfe1033\kerning28\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 VM Provided Routines{\*\bkmkend _Toc345583847} +\par {\*\bkmkstart _Toc345583848}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 5.1\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar +\jclisttab\tx390\wrapdefault\faauto\ls1\ilvl1\outlinelevel1\adjustright\rin0\lin390\itap0 \rtlch\fcs1 \ab\ai\af1\afs24\alang1025 \ltrch\fcs0 \b\i\fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Instruction Execution{\*\bkmkend _Toc345583848} +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 Instr\hich\af1\dbch\af31505\loch\f1 uction execution is performed by routine }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_instr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 . Its calling sequence is: +\par +\par }\pard \ltrpar\ql \fi720\li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 sim_instr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (void) \hich\f1 \endash \loch\f1 execute from current PC until error or halt. +\par {\*\bkmkstart _Toc345583849}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 5.2\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar +\jclisttab\tx390\wrapdefault\faauto\ls1\ilvl1\outlinelevel1\adjustright\rin0\lin390\itap0 \rtlch\fcs1 \ab\ai\af1\afs24\alang1025 \ltrch\fcs0 \b\i\fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Binary Load and Dump{\*\bkmkend _Toc345583849} +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 If the VM responds to the LOAD (or DUMP) command, the \hich\af1\dbch\af31505\loch\f1 load routine (dump routine) is implemented by routine }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 sim_load}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 . Its calling sequence is: +\par +\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 sim_load}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (FILE *fptr, char *buf, char *fnam, t_bool flag) - If }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 flag}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 = 0, load data from binary file }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 fptr}{\rtlch\fcs1 +\af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 . If }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 flag}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 + = 1, dump data to binary file }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 fptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 . For ei\hich\af1\dbch\af31505\loch\f1 +ther command, }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 buf}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 contains any VM-specific arguments, and }{\rtlch\fcs1 \ai\af1 +\ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 fnam}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 contains the file name. +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 If LOAD or DUMP is not implemented, }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_load}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 + should simply return SCPE_ARG. The LOAD and DUMP commands open and close the specified file for }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_load}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 . +\par {\*\bkmkstart _Toc345583850}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 5.3\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar +\jclisttab\tx390\wrapdefault\faauto\ls1\ilvl1\outlinelevel1\adjustright\rin0\lin390\itap0 \rtlch\fcs1 \ab\ai\af1\afs24\alang1025 \ltrch\fcs0 \b\i\fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Symbolic Examination and Deposit{\*\bkmkend _Toc345583850} +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 If the VM provides symbolic examination and deposit of data, it must provide two routines, }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 fprint_sym}{\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 for output and }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 parse_sym}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 + for input. Their calling sequences are: +\par +\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 fprint_sym}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (FILE *ofile, t_addr addr, t_value *val, UNIT *uptr, int32 switch) \hich\f1 \endash \loch\f1 Based on the }{\rtlch\fcs1 \ai\af1 +\ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 switch}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 variable, symbolically output to stream }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 ofile}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 the data in array }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 val}{\rtlch\fcs1 \af1 +\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 at the specified }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 addr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 + in unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 . +\par +\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 parse_sym}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 + (char *cptr, t_addr addr, UNIT *uptr, t_valu\hich\af1\dbch\af31505\loch\f1 e *val, int32 switch) \hich\f1 \endash \loch\f1 Based on the }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 switch}{\rtlch\fcs1 \af1 +\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 variable, parse character string }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 cptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 for a symbolic value }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 val}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 at the specified }{\rtlch\fcs1 +\ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 addr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 in unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 +uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 . +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 If symbolic processing is not implemented, or the output value or input string cannot be parsed, these routines \hich\af1\dbch\af31505\loch\f1 +should return SCPE_ARG. If the processing was successful and consumed more than a single word, then these routines should return extra number of addressing units consumed as a }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 negative}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 number. If the processing was successful and consumed a single addres\hich\af1\dbch\af31505\loch\f1 +sing unit, then these routines should return SCPE_OK. For example, PDP-11 }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 parse_sym}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 + would respond as follows to various inputs: +\par +\par \tab \hich\af1\dbch\af31505\loch\f1 input\tab \tab \tab \tab return value +\par +\par \tab \hich\af1\dbch\af31505\loch\f1 XYZGH\tab \tab \tab \tab SCPE_ARG +\par \tab \hich\af1\dbch\af31505\loch\f1 MOV R0,R1\tab \tab \tab -1 +\par \tab \hich\af1\dbch\af31505\loch\f1 MOV #4,R5\tab \tab \tab -3 +\par \tab \hich\af1\dbch\af31505\loch\f1 MOV 1234,5670\tab \tab -5 +\par +\par \hich\af1\dbch\af31505\loch\f1 There is an implicit relationsh\hich\af1\dbch\af31505\loch\f1 ip between the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 addr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 and }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 val}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 arguments and the device\hich\f1 \rquote +\loch\f1 s }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 aincr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 fields. Each entry in }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 +\b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 val}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 is assumed to represent }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 aincr}{ +\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 addressing units, starting at }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 addr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 : +\par +\par \ltrrow}\trowd \irow0\irowband0\ltrrow\ts11\trgaph108\trleft1350\trbrdrt\brdrs\brdrw10 \trbrdrl\brdrs\brdrw10 \trbrdrb\brdrs\brdrw10 \trbrdrr\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 \trbrdrv\brdrs\brdrw10 +\trftsWidth1\trautofit1\trpaddl108\trpaddr108\trpaddfl3\trpaddfr3\tblind1458\tblindtype3 \clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr\brdrs\brdrw10 \cltxlrtb\clftsWidth3\clwWidth2970\clshdrawnil \cellx4320 +\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr\brdrs\brdrw10 \cltxlrtb\clftsWidth3\clwWidth2970\clshdrawnil \cellx7290\pard \ltrpar\ql \li0\ri0\widctlpar\intbl\wrapdefault\faauto\adjustright\rin0\lin0 {\rtlch\fcs1 +\af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 val[0]\cell \hich\af1\dbch\af31505\loch\f1 addr + 0\cell }\pard \ltrpar\ql \li0\ri0\sa200\sl276\slmult1\widctlpar\intbl\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0 { +\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \trowd \irow0\irowband0\ltrrow\ts11\trgaph108\trleft1350\trbrdrt\brdrs\brdrw10 \trbrdrl\brdrs\brdrw10 \trbrdrb\brdrs\brdrw10 \trbrdrr\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 \trbrdrv\brdrs\brdrw10 +\trftsWidth1\trautofit1\trpaddl108\trpaddr108\trpaddfl3\trpaddfr3\tblind1458\tblindtype3 \clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr\brdrs\brdrw10 \cltxlrtb\clftsWidth3\clwWidth2970\clshdrawnil \cellx4320 +\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr\brdrs\brdrw10 \cltxlrtb\clftsWidth3\clwWidth2970\clshdrawnil \cellx7290\row \ltrrow}\pard \ltrpar\ql \li0\ri0\widctlpar\intbl\wrapdefault\faauto\adjustright\rin0\lin0 +{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 val[1]\cell \hich\af1\dbch\af31505\loch\f1 addr + aincr\cell }\pard \ltrpar\ql \li0\ri0\sa200\sl276\slmult1 +\widctlpar\intbl\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \trowd \irow1\irowband1\ltrrow\ts11\trgaph108\trleft1350\trbrdrt\brdrs\brdrw10 \trbrdrl\brdrs\brdrw10 \trbrdrb\brdrs\brdrw10 +\trbrdrr\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 \trbrdrv\brdrs\brdrw10 \trftsWidth1\trautofit1\trpaddl108\trpaddr108\trpaddfl3\trpaddfr3\tblind1458\tblindtype3 \clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr +\brdrs\brdrw10 \cltxlrtb\clftsWidth3\clwWidth2970\clshdrawnil \cellx4320\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr\brdrs\brdrw10 \cltxlrtb\clftsWidth3\clwWidth2970\clshdrawnil \cellx7290\row \ltrrow +}\pard \ltrpar\ql \li0\ri0\widctlpar\intbl\wrapdefault\faauto\adjustright\rin0\lin0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 val[2]\cell \hich\af1\dbch\af31505\loch\f1 addr + (2 * aincr)\cell }\pard \ltrpar +\ql \li0\ri0\sa200\sl276\slmult1\widctlpar\intbl\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \trowd \irow2\irowband2\ltrrow\ts11\trgaph108\trleft1350\trbrdrt\brdrs\brdrw10 \trbrdrl +\brdrs\brdrw10 \trbrdrb\brdrs\brdrw10 \trbrdrr\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 \trbrdrv\brdrs\brdrw10 \trftsWidth1\trautofit1\trpaddl108\trpaddr108\trpaddfl3\trpaddfr3\tblind1458\tblindtype3 \clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 +\clbrdrb\brdrs\brdrw10 \clbrdrr\brdrs\brdrw10 \cltxlrtb\clftsWidth3\clwWidth2970\clshdrawnil \cellx4320\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr\brdrs\brdrw10 \cltxlrtb\clftsWidth3\clwWidth2970\clshdrawnil +\cellx7290\row \ltrrow}\pard \ltrpar\ql \li0\ri0\widctlpar\intbl\wrapdefault\faauto\adjustright\rin0\lin0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 val[3]\cell \hich\af1\dbch\af31505\loch\f1 addr + (3 * aincr)\cell +}\pard \ltrpar\ql \li0\ri0\sa200\sl276\slmult1\widctlpar\intbl\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \trowd \irow3\irowband3\ltrrow\ts11\trgaph108\trleft1350\trbrdrt\brdrs\brdrw10 +\trbrdrl\brdrs\brdrw10 \trbrdrb\brdrs\brdrw10 \trbrdrr\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 \trbrdrv\brdrs\brdrw10 \trftsWidth1\trautofit1\trpaddl108\trpaddr108\trpaddfl3\trpaddfr3\tblind1458\tblindtype3 \clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl +\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr\brdrs\brdrw10 \cltxlrtb\clftsWidth3\clwWidth2970\clshdrawnil \cellx4320\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr\brdrs\brdrw10 +\cltxlrtb\clftsWidth3\clwWidth2970\clshdrawnil \cellx7290\row \ltrrow}\pard \ltrpar\ql \li0\ri0\widctlpar\intbl\wrapdefault\faauto\adjustright\rin0\lin0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 :\cell +\hich\af1\dbch\af31505\loch\f1 :\cell }\pard \ltrpar\ql \li0\ri0\sa200\sl276\slmult1\widctlpar\intbl\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \trowd \irow4\irowband4\lastrow \ltrrow +\ts11\trgaph108\trleft1350\trbrdrt\brdrs\brdrw10 \trbrdrl\brdrs\brdrw10 \trbrdrb\brdrs\brdrw10 \trbrdrr\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 \trbrdrv\brdrs\brdrw10 \trftsWidth1\trautofit1\trpaddl108\trpaddr108\trpaddfl3\trpaddfr3\tblind1458\tblindtype3 +\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr\brdrs\brdrw10 \cltxlrtb\clftsWidth3\clwWidth2970\clshdrawnil \cellx4320\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr +\brdrs\brdrw10 \cltxlrtb\clftsWidth3\clwWidth2970\clshdrawnil \cellx7290\row }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 Because }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 val}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 + is typically filled in and stored by calls on the device\hich\f1 \rquote \loch\f1 s examine and deposit routines, respectively, the examine and deposit routines and }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 +fprint_sym}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 and}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 fparse_sym}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 must agree on the expected width of items in }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 val}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 +, and on the alignment of }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 addr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 . Further, if }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 +\b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 fparse_sym}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 wants to modify a storage unit narrower than }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 awidth}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 , it must insert the new data into the appropriate entry in }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 val}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 without destroying surrounding fields. +\par +\par \hich\af1\dbch\af31505\loch\f1 The interpretation of switch values is arbitrary, but the following are use\hich\af1\dbch\af31505\loch\f1 d by existing VM\hich\f1 \rquote \loch\f1 s: +\par +\par \tab \hich\af1\dbch\af31505\loch\f1 switch\tab \tab \tab \tab interpretation +\par +\par \tab \hich\af1\dbch\af31505\loch\f1 -a\tab \tab \tab \tab single character +\par \tab \hich\af1\dbch\af31505\loch\f1 -c\tab \tab \tab \tab character string +\par \tab \hich\af1\dbch\af31505\loch\f1 -m\tab \tab \tab \tab instruction mnemonic +\par +\par \hich\af1\dbch\af31505\loch\f1 In addition, on input, a leading \hich\f1 \lquote \loch\f1 \hich\f1 (apostrophe) is interpreted to mean a single character, and a leading \'93\hich\af1\dbch\af31505\loch\f1 + (double quote) is interpreted to mean a character string. +\par {\*\bkmkstart _Toc345583851}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 5.4\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar +\jclisttab\tx390\wrapdefault\faauto\ls1\ilvl1\outlinelevel1\adjustright\rin0\lin390\itap0 \rtlch\fcs1 \ab\ai\af1\afs24\alang1025 \ltrch\fcs0 \b\i\fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Optional Interfaces{\*\bkmkend _Toc345583851} +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 For greater flexibility, SCP provides some optional interfaces that can be used to extend its command input, command processing, and command post-\hich\af1\dbch\af31505\loch\f1 +processing capabilities. These interfaces are strictly optional and are off by default. Using them requires intimate knowledge of how SCP functions internally and is not recommended to the novice VM writer. +\par {\*\bkmkstart _Toc345583852}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 5.4.1\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar +\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Once Only Initialization Rou\hich\af1\dbch\af31505\loch\f1 tine{\*\bkmkend _Toc345583852} +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 SCP defines a pointer (*}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_vm_init}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 \hich\f1 +)(void). This is a \'93\loch\f1 \hich\f1 weak global\'94\loch\f1 ; if no other module defines this value, it will default to NULL. A VM requiring special initialization should fill in this pointer with the address of its special init +\hich\af1\dbch\af31505\loch\f1 ialization routine: +\par +\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \tab \hich\af2\dbch\af31505\loch\f2 void sim_special_init (void); +\par \tab \hich\af2\dbch\af31505\loch\f2 void (*sim_vm_init)(void) = &sim_special_init; +\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 The special initialization routine can perform any actions required by the VM. If the other optional interfaces are to be used, the initialization routine\hich\af1\dbch\af31505\loch\f1 + can fill in the appropriate pointers; however, this can just as easily be done in the CPU reset routine. +\par {\*\bkmkstart _Toc345583853}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 5.4.2\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar +\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Address Input and Display{\*\bkmkend _Toc345583853} +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 SCP defines a pointer t_addr *(}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_vm_parse_addr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 +)(DEVICE *, char *, char **). This is init\hich\af1\dbch\af31505\loch\f1 +ialized to NULL. If it is filled in by the VM, SCP will use the specified routine to parse addresses in place of its standard numerical input routine. The calling sequence for the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 sim_vm_parse_addr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 routine is: +\par +\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_addr }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 sim_vm_parse_addr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (DEVICE *dptr, cha\hich\af1\dbch\af31505\loch\f1 r *cptr, char **optr) \hich\f1 \endash \loch\f1 + parse the string pointed to by }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 cptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 as an address for the device pointed to by }{ +\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 dptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 . o}{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 ptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 points to the first character not successfully parsed. If }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 cptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 == }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 optr}{\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 , parsing failed. +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 SCP defines a pointer void *(}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_vm_fprint_addr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 )(FI +\hich\af1\dbch\af31505\loch\f1 LE *, DEVICE *, t_addr). This is initialized to NULL. If it is filled in by the VM, SCP will use the specified routine to print addresses in place of its standard numerical output routine. The calling sequence for the }{ +\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_vm_fprint_addr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 routine is: +\par +\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_a\hich\af1\dbch\af31505\loch\f1 ddr }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 +\b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_vm_fprint_addr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (FILE *stream, DEVICE *dptr, t_addr addr) \hich\f1 \endash \loch\f1 output address }{\rtlch\fcs1 +\ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 addr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 to }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 stream}{ +\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 in the format required by the device pointed to by }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 dptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 . +\par {\*\bkmkstart _Toc345583854}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 5.4.3\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar +\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Command Input and Post-Processing{\*\bkmkend _Toc345583854} +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 SCP defines a pointer char* (}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_vm\hich\af1\dbch\af31505\loch\f1 _read}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 )(char *, int32 *, FILE *). This is initialized to NULL. If it is filled in by the VM, SCP will use the specified routine to obtain command input in place of its standard routine, read_line. The calling sequence for the } +{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_vm_read}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 routine is: +\par +\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 cha\hich\af1\dbch\af31505\loch\f1 r }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 +\b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_vm_input}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (char *buf, int32 *max, FILE *stream) \hich\f1 \endash \loch\f1 read the next command line from }{ +\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 stream}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 and store it in }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 buf}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 , up to a maximum of }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 max}{\rtlch\fcs1 \af1 +\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 characters +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 The routine is expected to strip off leading whitespace characters and to return NULL on end of file. +\par +\par \hich\af1\dbch\af31505\loch\f1 SCP defines a pointer void *(}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_vm_post}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 +)(t_bool from_scp). This is initialized to NULL. If filled in by the VM, SCP will call the specified routine at the end of every command. This allows the VM to update any local state, such as a GUI console display\hich\af1\dbch\af31505\loch\f1 +. The calling sequence for the vm_post routine is: +\par +\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 void }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 sim_vm_postupdate}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (t_bool from_scp) \hich\f1 \endash \loch\f1 if called from SCP, the argument }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 +\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 from_scp}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 is TRUE; otherwise, it is FALSE. +\par {\*\bkmkstart _Toc345583855}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 5.4.4\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar +\jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 VM-Specific Commands{\*\bkmkend _Toc345583855} +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 SCP defines a pointer CTAB *}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim\hich\af1\dbch\af31505\loch\f1 _vm_cmd}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 . This is initialized to NULL. If filled in by the VM, SCP interprets it as a pointer to SCP command table. This command table is checked before user input is looked up in the standard command table. +\par +\par \hich\af1\dbch\af31505\loch\f1 A command table is allocated as a contiguous array. Each entry is defined with a }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_ctab}{\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 structure (typedef }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 CTAB}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 ): +\par +\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 struct sim_ctab \{ +\par \tab \hich\af1\dbch\af31505\loch\f1 char\tab \tab *name;\tab \tab \tab \tab /* name */ +\par \tab \hich\af1\dbch\af31505\loch\f1 t_stat\tab \tab (*action)();\tab \tab \tab /* action routine */ +\par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab arg;\tab \tab \tab \tab /* argument */ +\par \tab \hich\af1\dbch\af31505\loch\f1 char\tab \tab *help;\tab \tab \tab \tab \hich\af1\dbch\af31505\loch\f1 /* help string */ +\par }\pard \ltrpar\ql \fi720\li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \}\hich\af1\dbch\af31505\loch\f1 ; +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 If the first word of a command line matches ctab.name, then the action routine is called with the following arguments: +\par +\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 action_routine}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (int32 arg, char *buf) \hich\f1 \endash \loch\f1 process input string }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 buf}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 based on optional argument }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 arg}{\rtlch\fcs1 \af1 +\ltrch\fcs0 \f1\insrsid4550150 +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 The strin\hich\af1\dbch\af31505\loch\f1 g passed to the action routine starts at the first non-blank character past the command name. +\par {\*\bkmkstart _Toc345583856}{\listtext\pard\plain\ltrpar \s1 \rtlch\fcs1 \ab\af0\afs28 \ltrch\fcs0 \b\f1\fs28\kerning28\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 6.\tab}}\pard\plain \ltrpar\s1\ql \fi-360\li360\ri0\sb240\sa60\keepn\widctlpar +\jclisttab\tx360\wrapdefault\faauto\ls1\outlinelevel0\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 \b\fs28\lang1033\langfe1033\kerning28\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Other SCP Facilities{\*\bkmkend _Toc345583856} +\par {\*\bkmkstart _Toc345583857}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 6.1\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar +\jclisttab\tx390\wrapdefault\faauto\ls1\ilvl1\outlinelevel1\adjustright\rin0\lin390\itap0 \rtlch\fcs1 \ab\ai\af1\afs24\alang1025 \ltrch\fcs0 \b\i\fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Terminal Input/Output Formatting Library{\*\bkmkend _Toc345583857} +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 SIMH provides routines to convert ASCII input characters to the format expected VM, and to convert VM-supplied ASCII characters to C-standard format. The routines are +\par +\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 int32 }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 sim_tt_inpcvt}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (int32 c, uint32 mode) \hich\f1 \endash \loch\f1 convert input character }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 c}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 according to the\hich\af1\dbch\af31505\loch\f1 }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 mode }{ +\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 specification and return the converted result (-1 if the character is not valid in the specified mode). +\par +\par \hich\af1\dbch\af31505\loch\f1 int32 }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tt_outcvt}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (int32 c, uint32 mode) \hich\f1 +\endash \loch\f1 convert output character }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 c}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 according to the }{\rtlch\fcs1 \ai\af1 +\ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 mode}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 specification and return the converted result (-1 i\hich\af1\dbch\af31505\loch\f1 +f the character is not valid in the specified mode). +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 The supported modes are: +\par +\par \tab \hich\af1\dbch\af31505\loch\f1 TTUF_MODE_8B\tab 8b mode; no conversion +\par \tab \hich\af1\dbch\af31505\loch\f1 TTUF_MODE_7B\tab 7b mode; the high-order bit is masked off +\par \tab \hich\af1\dbch\af31505\loch\f1 TTUF_MODE_7P\tab 7b printable mode; the high-order bit is masked off +\par \tab \tab \tab \tab \hich\af1\dbch\af31505\loch\f1 In addition, \hich\af1\dbch\af31505\loch\f1 on output, if the character is not printable, +\par \tab \tab \tab \tab \hich\af1\dbch\af31505\loch\f1 -1 is returned +\par \tab \hich\af1\dbch\af31505\loch\f1 TTUF_MODE_UC\tab 7b upper case mode; the high-order bit is masked off +\par \tab \tab \tab \tab \hich\af1\dbch\af31505\loch\f1 In addition, lower case is converted to upper case +\par \tab \tab \tab \tab \hich\af1\dbch\af31505\loch\f1 If the character is not printable, -1 is returned +\par +\par \hich\af1\dbch\af31505\loch\f1 On input, TTUF\hich\af1\dbch\af31505\loch\f1 _MODE_UC has an additional modifier, TTUF_MODE_KSR, which forces the high order bit to be set rather than cleared. +\par +\par \hich\af1\dbch\af31505\loch\f1 The set of printable control characters is contained in the global bit-vector variable }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tt_pchar}{\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 . Each bit represents the character corr\hich\af1\dbch\af31505\loch\f1 +esponding to the bit number (e.g., bit 0 represents NUL, bit 1 represents SOH, etc.). If a bit is set, the corresponding control character is considered printable. It initially contains the following characters: BEL, BS, HT, LF, and CR. The set may be +\hich\af1\dbch\af31505\loch\f1 m\hich\af1\dbch\af31505\loch\f1 anipulated with these routines: +\par +\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 sim_set_pchar}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (int32 flag, char *cptr) \hich\f1 \endash \loch\f1 set }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 sim_tt_pchar}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 to the value pointed to by }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 cptr}{ +\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 ; return SCPE_2FARG if }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 cptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 is null or points to a null string, or SCPE_ARG if the value cannot be converted or does not contai\hich\af1\dbch\af31505\loch\f1 n at least CR and LF. +\par +\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_show_pchar}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 + (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr) \hich\f1 \endash \loch\f1 output the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tt_pchar}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 value to the stream }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 st}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 . +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 Note that the DEL character is always considered non-printable and will be suppressed in the UC and\hich\af1\dbch\af31505\loch\f1 7P modes. +\par +\par {\*\bkmkstart _Toc345583858}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 6.2\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar +\jclisttab\tx390\wrapdefault\faauto\ls1\ilvl1\outlinelevel1\adjustright\rin0\lin390\itap0 \rtlch\fcs1 \ab\ai\af1\afs24\alang1025 \ltrch\fcs0 \b\i\fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Terminal Multiplexer Emulation Library{\*\bkmkend _Toc345583858} +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 SIMH supports the use of multiple terminals. All terminals except the console are accessed via Telnet}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid8129972 \hich\af1\dbch\af31505\loch\f1 or serial ports on the host machine}{ +\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 . SIMH provides }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid8129972 \hich\af1\dbch\af31505\loch\f1 three }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 supporting libraries for implementing multiple terminals: sim_tmxr.c (and its header file, sim_tmxr.h), which provide OS-independent support routines for terminal multiplexers; }{\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid8129972 \hich\af1\dbch\af31505\loch\f1 sim_serial.c (and its header file sim_serial.h), which provide OS-dependent ser\hich\af1\dbch\af31505\loch\f1 ial I/O routines; }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 and sim_sock.c (and its header file, sim_sock.h), which provide OS-dependent socket routines. Sim_sock.c }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid8129972 \hich\af1\dbch\af31505\loch\f1 and sim_serial.c are}{\rtlch\fcs1 +\af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 implemented under Windows, VMS, UNIX, and MacOS. +\par +\par \hich\af1\dbch\af31505\loch\f1 Two basic data structures define the multiple terminals. Ind\hich\af1\dbch\af31505\loch\f1 ividual lines are defined by an array of }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmln +}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 structures (typedef }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 TMLN}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 ): +\par +\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 struct tmln \{ +\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid4462419 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4462419 \tab \hich\af1\dbch\af31505\loch\f1 int\tab \tab conn;\tab \tab \tab \tab /* line connected flag */ + +\par }\pard \ltrpar\ql \fi720\li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid4462419 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4462419 \hich\af1\dbch\af31505\loch\f1 SOCKET\tab sock;\tab \tab \tab \tab /* connection socket */ + +\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4462419 \hich\af1\dbch\af31505\loch\f1 char }{\rtlch\fcs1 \af1 +\ltrch\fcs0 \f1\insrsid4550150 \tab \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4462419 \hich\af1\dbch\af31505\loch\f1 *}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 ipad;\tab \tab \tab \tab /* IP address */ +\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4462419 \tab \hich\af1\dbch\af31505\loch\f1 SOCKET\tab master;\tab \tab \tab \tab /* line specific master socket *\hich\af1\dbch\af31505\loch\f1 / +\par \tab \hich\af1\dbch\af31505\loch\f1 char\tab \tab *port;\tab \tab \tab \tab /* line specific listening port */ +\par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab sessions;\tab \tab \tab /* count of tcp connections received */ +\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 uint32\tab \tab cnms;\tab \tab \tab \tab /* connect time ms */ +\par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab tsta;\tab \tab \tab \tab /* Telnet state */ +\par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab rcve;\tab \tab \tab \tab /* rcv enable */ +\par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab xmte;\tab \tab \tab \tab /* xmt enable \hich\af1\dbch\af31505\loch\f1 */ +\par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab dstb;\tab \tab \tab \tab /* disable Tlnt bin */ +\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid4462419 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4462419 \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab notelnet;\tab \tab \tab +/* raw binary data (no telnet interpret) */ +\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab rxbpr;\tab \tab \tab \tab /* rcv buf remove */ +\par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab rxbpi;\tab \tab \tab \tab /* rcv buf insert */ +\par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab rxcnt;\tab \tab \tab \tab /* rcv count */ +\par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab txbpr;\tab \tab \tab \tab /* xmt buf remove *\hich\af1\dbch\af31505\loch\f1 / +\par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab txbpi;\tab \tab \tab \tab /* xmt buf insert */ +\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid4462419 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4462419 \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab txcnt;\tab \tab \tab \tab /* xmt count */ +\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4462419 \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab txdrp;\tab \tab \tab \tab /* xmt drop count */ +\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid4462419 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4462419 \hich\af1\dbch\af31505\loch\f1 \tab int32\tab \tab txbsz;\tab \tab \tab \tab /* xmt buffer size */ + +\par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab txbfd;\tab \tab \tab \tab /* xmt buffered flag */ +\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 FILE\tab \tab *txlog;\tab \tab \tab \tab /* xmt log file */ +\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid3891160 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3891160 \tab \hich\af1\dbch\af31505\loch\f1 FILEREF\tab *txlogref;\tab \tab \tab +\hich\af1\dbch\af31505\loch\f1 /* xmt log file reference */ +\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 char\tab \tab *txlogname;\tab \tab \tab /* xmt log file name */ +\par \tab \hich\af1\dbch\af31505\loch\f1 char\tab \tab rxb[TMXR_MAXBUF];\tab \tab /* rcv buffer */ +\par \tab \hich\af1\dbch\af31505\loch\f1 char\tab \tab rbr[TMXR_MAXBUF];\tab \tab /* rcv break */ +\par \tab \hich\af1\dbch\af31505\loch\f1 char\tab \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3891160 \hich\af1\dbch\af31505\loch\f1 *}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 txb;}{\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid3891160 \tab \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 /* xmt buffer */ +\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3891160 \tab \hich\af1\dbch\af31505\loch\f1 TMXR\tab \tab *mp;\tab \tab \tab \tab /* back pointer to mux */ +\par \tab \hich\af1\dbch\af31505\loch\f1 char\tab \tab *serconfig;\tab \tab \tab \hich\af1\dbch\af31505\loch\f1 /* line config */ +\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid3891160 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3891160 \tab \hich\af1\dbch\af31505\loch\f1 SERHANDLE\tab serport;\tab \tab \tab \tab /* serial port handle */ + +\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3891160 \tab \hich\af1\dbch\af31505\loch\f1 t_bool\tab \tab ser_connect_pending;\tab \tab +/* serial connection notice pending */ +\par \tab \hich\af1\dbch\af31505\loch\f1 SOCKET\tab connecting;\tab \tab \tab /* Outgoing socket while connecting */ +\par \tab \hich\af1\dbch\af31505\loch\f1 char\tab \tab *destination;\tab \tab \tab /* Outgoing destination address:port\hich\af1\dbch\af31505\loch\f1 */ +\par \tab \hich\af1\dbch\af31505\loch\f1 UNIT\tab \tab *uptr;\tab \tab \tab \tab /* input polling unit -default to mp->uptr */ +\par \tab \hich\af1\dbch\af31505\loch\f1 UNIT\tab \tab *o_uptr;\tab \tab \tab \tab /* output polling unit \hich\f1 \endash \loch\f1 default to lp->uptr */ +\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \}\hich\af1\dbch\af31505\loch\f1 ; +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 The fields are the following: +\par +\par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 conn}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 connection }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3891160 +\hich\af1\dbch\af31505\loch\f1 flag }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (0 = disconnected) +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0\pararsid3891160 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3891160 \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \b\f1\insrsid3891160\charrsid3891160 \hich\af1\dbch\af31505\loch\f1 +sock}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3891160 \tab \tab \hich\af1\dbch\af31505\loch\f1 connection socket +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0\pararsid3806017 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3806017 \tab \hich\af1\dbch\af31505\loch\f1 ipad\tab \tab IP address of\hich\af1\dbch\af31505\loch\f1 + remote end of connection +\par \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \b\f1\insrsid3806017\charrsid3806017 \hich\af1\dbch\af31505\loch\f1 master}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3806017 \tab \tab \hich\af1\dbch\af31505\loch\f1 optional line specific listening socket +\par \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \b\f1\insrsid3806017\charrsid3806017 \hich\af1\dbch\af31505\loch\f1 port}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3806017 \tab \tab \hich\af1\dbch\af31505\loch\f1 optional line specific listening port +\par \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \b\f1\insrsid3806017 \hich\af1\dbch\af31505\loch\f1 sessions}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3806017 \tab \hich\af1\dbch\af31505\loch\f1 count of tcp connections received +\par \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \b\f1\insrsid3806017\charrsid3806017 \hich\af1\dbch\af31505\loch\f1 cnms}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3806017 \tab \tab \hich\af1\dbch\af31505\loch\f1 connect time +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tsta}{\rtlch\fcs1 \af1 +\ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 Telnet state +\par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 rcve}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 receive enable flag (0 = disabled) +\par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 xmte}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 transmit flow control flag (0 = transmit disabled) +\par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 dstb}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 Telnet bin mode disabled +\par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 rxbp}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 r\tab \tab receive buffer remove pointer +\par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 rxbpi}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 receive buffer insert pointer +\par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 rxcnt}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 receive count +\par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 txbpr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 transmit buffer remove pointer +\par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 txbpi}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 transmit buffer insert point\hich\af1\dbch\af31505\loch\f1 er +\par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 txcnt}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 transmit count +\par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 txlog}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 pointer to log file descriptor +\par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 txlogname}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 pointer to log file name +\par }\pard \ltrpar\ql \fi720\li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 rxb}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab +\hich\af1\dbch\af31505\loch\f1 receive buffer +\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 rbr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 receive buffer break flags +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 txb}{\rtlch\fcs1 \af1 +\ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 transmit buffer +\par +\par \hich\af1\dbch\af31505\loch\f1 The overall set of extra terminals is defined by the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 + structure (typedef }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 TMX\hich\af1\dbch\af31505\loch\f1 R}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 ): +\par +\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 struct tmxr \{ +\par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab lines;\tab \tab \tab \tab /* # lines */ +\par \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3891160 \hich\af1\dbch\af31505\loch\f1 char}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3891160 \hich\af1\dbch\af31505\loch\f1 *}{\rtlch\fcs1 \af1 +\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 port;\tab \tab \tab \tab /* listening port */ +\par \tab \hich\af1\dbch\af31505\loch\f1 SOCKET\tab master;\tab \tab \tab \tab /* master socket */ +\par \tab \hich\af1\dbch\af31505\loch\f1 TMLN\tab \tab *ldsc;\tab \tab \tab \tab /* pointer to line descriptors */ +\par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab *lnorder;\tab \tab \tab /* line connection order */ +\par \tab \hich\af1\dbch\af31505\loch\f1 DEVICE\tab *dptr;\tab \tab \tab \tab /* multiple\hich\af1\dbch\af31505\loch\f1 xer device */ +\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3891160 \tab \hich\af1\dbch\af31505\loch\f1 UNIT\tab \tab *uptr;\tab \tab \tab \tab /* polling unit (connection) */ +\par \tab \hich\af1\dbch\af31505\loch\f1 char \tab \tab logfiletmpl[FILENAMEMAX];\tab /* template logfile name */ +\par \tab \hich\af1\dbch\af31505\loch\f1 int23\tab \tab buffered;\tab \tab \tab /* Buffered line behavior and buffer size*/ +\par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab sessions;\tab \tab \tab /* count of tcp connections received */ +\par \tab \hich\af1\dbch\af31505\loch\f1 uint32\tab \tab \hich\af1\dbch\af31505\loch\f1 last_poll_time;\tab \tab \tab /* time of last connection poll */ +\par \tab \hich\af1\dbch\af31505\loch\f1 t_bool\tab \tab notelnet;\tab \tab \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9308345 \hich\af1\dbch\af31505\loch\f1 /* default telnet capability for incoming connections */}{\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid3891160 +\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9308345 \tab \hich\af1\dbch\af31505\loch\f1 t_bool\tab \tab modem_control;\tab \tab \tab /* multiplexer supports modem control behaviors */ +\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \}\hich\af1\dbch\af31505\loch\f1 ; +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 The fields are the following: +\par +\par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 lines}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 number of lines (constant) +\par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 port}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 master listening port (specified by ATTACH command) +\par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 master}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 master listening socket (filled in by ATTACH command) +\par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 ldsc}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 array of line descriptors +\par }\pard \ltrpar\ql \fi-1440\li2160\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin2160\itap0 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 lnorder}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab +\hich\af1\dbch\af31505\loch\f1 array of line numbers in order of connection sequence, or NULL if \hich\af1\dbch\af31505\loch\f1 user-defined connection order is not required +\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 dptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 pointer to the multiplexer\hich\f1 \rquote \loch\f1 +s DEVICE structure, or NULL if the device is to be derived from the UNIT passed to the attach call. +\par }\pard \ltrpar\ql \fi-1440\li2160\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin2160\itap0\pararsid1264706 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid1264706 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid1264706 +\tab \hich\af1\dbch\af31505\loch\f1 the UNIT passed to the attach call. +\par }\pard \ltrpar\ql \fi-1440\li2160\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin2160\itap0\pararsid7674256 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid7674256 \hich\af1\dbch\af31505\loch\f1 logfiletmpl}{\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid1264706 \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid7674256 \hich\af1\dbch\af31505\loch\f1 template logfile name use\hich\af1\dbch\af31505\loch\f1 d to create names for per line log filesl.}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid1264706 + +\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid7674256 \hich\af1\dbch\af31505\loch\f1 buffered}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid1264706 \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid7674256 \hich\af1\dbch\af31505\loch\f1 +Buffered line behaviors enabled flag and the size of the line buffer.}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid1264706 +\par }\pard \ltrpar\ql \fi-1440\li2160\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin2160\itap0\pararsid1264706 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid7674256 \hich\af1\dbch\af31505\loch\f1 sessions}{\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid1264706 \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid7674256 \hich\af1\dbch\af31505\loch\f1 count of tcp connections received on the master socket}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid1264706 . +\par }\pard \ltrpar\ql \fi-1440\li2160\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin2160\itap0\pararsid7674256 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid7674256 \hich\af1\dbch\af31505\loch\f1 last_poll_time}{\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid7674256 \tab \hich\af1\dbch\af31505\loch\f1 time of last connection poll. +\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid7674256 \hich\af1\dbch\af31505\loch\f1 notelnet}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid7674256 \tab \hich\af1\dbch\af31505\loch\f1 default telnet \hich\af1\dbch\af31505\loch\f1 +capability for tcp connections. +\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid7674256 \hich\af1\dbch\af31505\loch\f1 modem_control}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid7674256 \tab \hich\af1\dbch\af31505\loch\f1 +flag indicating that multiplexer supports full modem control behaviors. +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0\pararsid1264706 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid1264706 +\par +\par }\pard \ltrpar\ql \fi-1440\li2160\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin2160\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid1264706 +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 The number of elements in the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 ldsc}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 and }{\rtlch\fcs1 +\ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 lnorder}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 arrays must equal the value of the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 lines}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 field. Set }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 lnorder}{\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 to NULL if the connection order feature is not needed. If the first element of the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 lnorder}{\rtlch\fcs1 \af1 +\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 array is \hich\f1 \endash \loch\f1 1, then the default ascending sequential connection order is used. Set }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 dptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 to NULL if the device should be derived from the unit passed to the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 tmxr_att\hich\af1\dbch\af31505\loch\f1 ach}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 call. +\par +\par \hich\af1\dbch\af31505\loch\f1 Library sim_tmxr.c provides the following routines to support Telnet}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid8129972 \hich\af1\dbch\af31505\loch\f1 and Serial port}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 -based terminals: +\par +\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 int32 }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 tmxr_poll_conn}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (TMXR *mp) \hich\f1 \endash \loch\f1 poll for a new connection to the terminals described by }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 +\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 mp}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 . If there is a new connection, the\hich\af1\dbch\af31505\loch\f1 + routine resets all the line descriptor state (including receive enable) and returns the line number (index to line descriptor) for the new connection. If there isn\hich\f1 \rquote \loch\f1 t a new connection, the routine returns \hich\f1 \endash +\loch\f1 1. +\par +\par \hich\af1\dbch\af31505\loch\f1 void }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_reset_ln}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (TMLN *lp) \hich\f1 \endash \loch\f1 + reset the lin\hich\af1\dbch\af31505\loch\f1 e described by }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 lp}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 +. The connection is closed and all line descriptor state is reset. +\par +\par \hich\af1\dbch\af31505\loch\f1 int32 }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_getc_ln}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (TMLN *lp) \hich\f1 \endash \loch\f1 + return the next available character from the line described by }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 lp}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 +. If a character is available, the return variable is: +\par +\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \tab \hich\af2\dbch\af31505\loch\f2 (1 << TMXR_V_VA\hich\af2\dbch\af31505\loch\f2 LID) | character +\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9308345 \hich\af1\dbch\af31505\loch\f1 If a BREAK occurred on the line, SCPE_BREAK will be ORed into the return variable. }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 +If no character is available, the return variable is 0. +\par +\par \hich\af1\dbch\af31505\loch\f1 void }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_poll_rx}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (TMXR *mp) \hich\f1 \endash \loch\f1 + poll for input available on the terminals described by }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 mp}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 . +\par +\par \hich\af1\dbch\af31505\loch\f1 void }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_rqln}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (TMLN *lp) \hich\f1 \endash \loch\f1 + return the number of characters in the receive queue of the line described by }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 lp}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 . +\par +\par }\pard\plain \ltrpar\s21\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_putc_ln}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 + (TMLN *lp, int32 chr) \hich\f1 \endash \loch\f1 output character }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 chr }{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 +to the line described by }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 lp}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 . Possible errors are SCPE_LOST (connection lost) and SCP +\hich\af1\dbch\af31505\loch\f1 E_STALL (connection backlogged). +\par }\pard\plain \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \f1\insrsid4550150 +\par }\pard\plain \ltrpar\s21\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 void }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_poll_tx}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (TMXR *mp) +\hich\f1 \endash \loch\f1 poll for output complete on the terminals described by }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 mp}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 . +\par }\pard\plain \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 void }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_tqln}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (TMLN *lp) \hich\f1 \endash \loch\f1 + return the number of characters in the transmit queue of the line described by }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 lp}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 . +\par +\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid9308345 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9308345 \hich\af1\dbch\af31505\loch\f1 void }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid9308345 +\hich\af1\dbch\af31505\loch\f1 tmxr_send_buffered_data}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9308345 \hich\af1\dbch\af31505\loch\f1 (TMLN *lp) \hich\f1 \endash \loch\f1 flush any buffered data for the line described by }{\rtlch\fcs1 \ai\af1 +\ltrch\fcs0 \i\f1\insrsid9308345 \hich\af1\dbch\af31505\loch\f1 lp}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9308345 . +\par +\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 tmxr_attach}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (TMXR *mp, UNIT *uptr, char *cptr) \hich\f1 \endash \loch\f1 attach the port contained in character string }{\rtlch\fcs1 \ai\af1 +\ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 cptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 to the terminals described by }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 mp}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 and unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 . +\par +\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t\hich\af1\dbch\af31505\loch\f1 mxr_open_master}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 + (TMXR *mp, char *cptr) \hich\f1 \endash \loch\f1 associate the port contained in character string }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 cptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 to the terminals described by }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 mp}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 +. This routine is a subset of }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_attach}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 . +\par +\par }\pard\plain \ltrpar\s21\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_detach}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 + (TMXR *mp, UNIT *uptr) \hich\f1 \endash \hich\af1\dbch\af31505\loch\f1 detach all connections for the terminals described by }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 mp}{\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 and unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 . +\par +\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_close_master}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (TMXR *mp) \hich\f1 \endash \loch\f1 + close the master port for the terminals described by }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 mp}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 . This routine is a subset of}{ +\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_detach}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 . +\par }\pard\plain \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_ex}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (t_value *vptr, t_addr addr, +\hich\af1\dbch\af31505\loch\f1 UNIT *uptr, int32 sw) \hich\f1 \endash \loch\f1 stub examine routine, needed because the extra terminals are marked as attached; always returns an error. +\par +\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_dep}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 + (t_value val, t_addr addr, UNIT *uptr, int32 sw) \hich\f1 \endash \loch\f1 stub deposit routine, needed because the extra terminals a\hich\af1\dbch\af31505\loch\f1 re marked as detached; always returns an error. +\par }\pard \ltrpar\ql \li360\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par }\pard \ltrpar\ql \fi360\li360\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0\pararsid9308345 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9308345 \hich\af1\dbch\af31505\loch\f1 void }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid9308345 +\hich\af1\dbch\af31505\loch\f1 tmxr_msg}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9308345 \hich\af1\dbch\af31505\loch\f1 (SOCKET sock, char *msg) \hich\f1 \endash \loch\f1 output character string }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid9308345 +\hich\af1\dbch\af31505\loch\f1 msg}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9308345 \hich\af1\dbch\af31505\loch\f1 to socket sock. +\par +\par }\pard \ltrpar\ql \fi360\li360\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 void }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 tmxr_linemsg}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (TMLN *lp, char *msg) \hich\f1 \endash \loch\f1 output character string }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 msg}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 to line }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 lp}{\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 . +\par +\par }\pard\plain \ltrpar\s21\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 void }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_fconns}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 + (FILE *st, TMLN *lp, \hich\af1\dbch\af31505\loch\f1 int32 ln) \hich\f1 \endash \loch\f1 output connection status to stream }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 st}{\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 for the line described by }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 lp}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 . If }{ +\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 ln}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 is >= 0, preface the output with the specified line number. +\par }\pard\plain \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 void }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_fstats}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (FILE *st, TMLN *lp, int32 ln) \hich\f1 +\endash \loch\f1 output connection statistics to stream }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 st}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 for the line des +\hich\af1\dbch\af31505\loch\f1 cribed by }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 lp}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 . If }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 +\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 ln}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 is >= 0, preface the output with the specified line number. +\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9308345 \hich\af1\dbch\af31505\loch\f1 tstat }{\rtlch\fcs1 \af1 \ltrch\fcs0 \b\f1\insrsid9308345\charrsid2698330 \hich\af1\dbch\af31505\loch\f1 tmxr_set_log}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9308345 +\hich\af1\dbch\af31505\loch\f1 (UNIT *uptr, int32 val, char *cptr, void *mp) \hich\f1 \endash \loch\f1 enable logging of a\hich\af1\dbch\af31505\loch\f1 + line of the multipleser described by mp to the filename pointed to by cptr. If uptr is NULL, then val indicates the line number; otherwise, the unit number within the associated device implies the line number. This function may be used as an MTAB valid +\hich\af1\dbch\af31505\loch\f1 a\hich\af1\dbch\af31505\loch\f1 tion routine. +\par +\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid2698330 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid2698330 \hich\af1\dbch\af31505\loch\f1 tstat }{\rtlch\fcs1 \af1 \ltrch\fcs0 +\b\f1\insrsid2698330\charrsid5979563 \hich\af1\dbch\af31505\loch\f1 tmxr_set_}{\rtlch\fcs1 \af1 \ltrch\fcs0 \b\f1\insrsid2698330 \hich\af1\dbch\af31505\loch\f1 no}{\rtlch\fcs1 \af1 \ltrch\fcs0 \b\f1\insrsid2698330\charrsid5979563 +\hich\af1\dbch\af31505\loch\f1 log}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid2698330 \hich\af1\dbch\af31505\loch\f1 (UNIT *uptr, int32 val, char *cptr, void *mp) \hich\f1 \endash \loch\f1 + disable logging of a line of the multipleser described by mp to the filename poi\hich\af1\dbch\af31505\loch\f1 +nted to by cptr. If uptr is NULL, then val indicates the line number; otherwise, the unit number within the associated device implies the line number. This function may be used as an MTAB validation routine. +\par +\par \hich\af1\dbch\af31505\loch\f1 tstat }{\rtlch\fcs1 \af1 \ltrch\fcs0 \b\f1\insrsid2698330\charrsid2698330 \hich\af1\dbch\af31505\loch\f1 tmxr_show_log}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid2698330 \hich\af1\dbch\af31505\loch\f1 + (FILE *st, UNIT *uptr, in\hich\af1\dbch\af31505\loch\f1 t32 val, void *mp) \hich\f1 \endash \loch\f1 + outputs the logging status of a line of the multiplexer described by mp to stream st. If uptr is NULL, then val indicates the line number; otherwise, the unit number within the associated device implies the line number. This functio +\hich\af1\dbch\af31505\loch\f1 n\hich\af1\dbch\af31505\loch\f1 may be used as an MTAB display routine. +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0\pararsid2698330 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 tmxr_dscln}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (UNIT *uptr, int32 val, char *cptr, void *mp) \hich\f1 \endash \loch\f1 parse the string pointed to by }{\rtlch\fcs1 \ai\af1 +\ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 cptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 + for a decimal line number. If the line number is valid, disconnect the specified line in the terminal multiplex\hich\af1\dbch\af31505\loch\f1 er described by }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 mp}{ +\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 . The calling sequence allows }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_dscln}{\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 to be used as an MTAB processing routine.}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid2698330 \hich\af1\dbch\af31505\loch\f1 + A line connected via a tcp session will be disconnected, a line connected to a serial port will be closed if the sim_switches \hich\f1 \endash \loch\f1 C flag is enabled when the\hich\af1\dbch\af31505\loch\f1 + routine is called, otherwise a serial port will have DTR dropped for 500ms and raised again.}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par +\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_set_lnorder}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 + (UNIT *uptr, int32 val, char *cptr, void *desc) \hich\f1 \endash \loch\f1 set the line connection order array associated with the TMXR structure pointed to by }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 de +\hich\af1\dbch\af31505\loch\f1 sc}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 . The string pointed to by }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 cptr}{\rtlch\fcs1 \af1 +\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 is parsed for a semicolon-delimited list of ranges. Ranges are of the form: +\par +\par }\pard \ltrpar\ql \fi-2160\li3600\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin3600\itap0 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \hich\af2\dbch\af31505\loch\f2 line1-line2\tab ascending sequence from }{\rtlch\fcs1 \ab\af2 \ltrch\fcs0 +\b\f2\insrsid4550150 \hich\af2\dbch\af31505\loch\f2 line1}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \hich\af2\dbch\af31505\loch\f2 to }{\rtlch\fcs1 \ab\af2 \ltrch\fcs0 \b\f2\insrsid4550150 \hich\af2\dbch\af31505\loch\f2 line2}{\rtlch\fcs1 \af2 +\ltrch\fcs0 \f2\insrsid4550150 +\par \hich\af2\dbch\af31505\loch\f2 line1/length\tab ascending sequence from }{\rtlch\fcs1 \ab\af2 \ltrch\fcs0 \b\f2\insrsid4550150 \hich\af2\dbch\af31505\loch\f2 line1}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \hich\af2\dbch\af31505\loch\f2 to }{ +\rtlch\fcs1 \ab\af2 \ltrch\fcs0 \b\f2\insrsid4550150 \hich\af2\dbch\af31505\loch\f2 line1}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \hich\af2\dbch\af31505\loch\f2 +}{\rtlch\fcs1 \ab\af2 \ltrch\fcs0 \b\f2\insrsid4550150 +\hich\af2\dbch\af31505\loch\f2 length}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \hich\af2\dbch\af31505\loch\f2 -1 +\par \hich\af2\dbch\af31505\loch\f2 ALL\tab ascending sequence of all l\hich\af2\dbch\af31505\loch\f2 ines defined by the multiplexer +\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 The line order array must provide an int32 element for each line. The calling sequence allows }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_set_lnorder}{\rtlch\fcs1 \af1 +\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 to be used as an MTAB processing routine. +\par +\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_show_lnorder}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 + (FILE *st, UNIT *uptr, int32 val, void *des\hich\af1\dbch\af31505\loch\f1 c) \hich\f1 \endash \loch\f1 output the line connection order associated multiplexer (TMXR *) }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 desc}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid4550150 \hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 to stream }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 +\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 st}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 . The order is rendered as a semicolon-delimited list of ranges. The calling sequence allows }{\rtlch\fcs1 \ab\af1 +\ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_show_lnorder}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 to be used as an MTAB processing routine. +\par +\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_s\hich\af1\dbch\af31505\loch\f1 how_summ}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 + (FILE *st, UNIT *uptr, int32 val, void *desc) \hich\f1 \endash \loch\f1 outputs the summary status of the multiplexer (TMXR *) }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 desc}{\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 to stream }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 st}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 . +\par +\par }\pard\plain \ltrpar\s21\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_show_cstat}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 + (FILE *st, UNIT *uptr, int32 val, void *desc) \hich\f1 \endash \hich\af1\dbch\af31505\loch\f1 outputs either the connections (val = 1) or the statistics (val = 0) of the multiplexer (TMXR *) }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 desc}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 to stream }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 st}{\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 . Also checks for multiplexer not attached, or all lines disconnected. +\par +\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_show_lines}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 + (FILE *st, UNIT *uptr, int32 val, void *desc) \loch\af1\dbch\af31505\hich\f1 \endash \loch\f1 outputs the number of lines in the terminal multiplexer (TMXR *) I to stream I. +\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7674256 +\par }\pard \ltrpar\s21\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid7674256 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7674256 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\insrsid7674256 +\hich\af1\dbch\af31505\loch\f1 tmxr_set_modem_control_passthru}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7674256 \hich\af1\dbch\af31505\loch\f1 (TMXR *mp) \hich\f1 \endash \loch\f1 + Enables modem control passthru behaviors, and disables internal manipulation of DTR (&RTS) by tmxr apis. Enables the tmx\hich\af1\dbch\af31505\loch\f1 r_set_get_modem_bits and tmxr_set_config_line apis. +\par +\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\insrsid7674256 \hich\af1\dbch\af31505\loch\f1 tmxr_set_modem_control_passthru}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7674256 \hich\af1\dbch\af31505\loch\f1 (TMXR *mp) \hich\f1 +\endash \loch\f1 Enables modem control passthru behaviors, and disables internal manipulation of DTR (&RTS) by tmxr apis. Enables the tmxr_set_get_modem_bits and tmxr_\hich\af1\dbch\af31505\loch\f1 set_config_line apis. +\par +\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\insrsid7674256 \hich\af1\dbch\af31505\loch\f1 tmxr_clear_modem_control_passthru}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7674256 \hich\af1\dbch\af31505\loch\f1 (TMXR *mp) \hich\f1 +\endash \loch\f1 Disables modem control passthru behaviors, and enables internal manipulation of DTR (&RTS) by tmxr apis. Disables the tmxr_set_get_modem_bits and tmxr_set_config_line apis. +\par +\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid9462171 \hich\af1\dbch\af31505\loch\f1 t_st\hich\af1\dbch\af31505\loch\f1 at }{\rtlch\fcs1 \af1 \ltrch\fcs0 \b\insrsid9462171\charrsid9462171 \hich\af1\dbch\af31505\loch\f1 tmxr_set_get_modem_bits}{\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid9462171 \hich\af1\dbch\af31505\loch\f1 (TMLN *lp, int32 bits_to_set, int32 bits_to_clear, int32 *incoming_bits) \hich\f1 \endash \loch\f1 + For a line connected to a serial port on a TMXR device with modem_control_passthru enabled, then the bits_to_set and/or bits_to_clear (DTR and RTS) are ch\hich\af1\dbch\af31505\loch\f1 +anged and if incoming_bits is not NULL, then the current modem bits are returned (DCD,RNG,CTS, DSR).}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7674256 +\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid9462171 +\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \af1 \ltrch\fcs0 \b\insrsid9462171\charrsid9462171 \hich\af1\dbch\af31505\loch\f1 tmxr_set_config_line}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid9462171 \hich\af1\dbch\af31505\loch\f1 + (TMLN *lp, char *config) \hich\f1 \endash \loch\f1 sets the line configuration (speed, parity, character size, stopbits) on a serial port. Config is \hich\af1\dbch\af31505\loch\f1 a string of the form: 9600-8N1. +\par +\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \af1 \ltrch\fcs0 \b\insrsid9462171\charrsid3806017 \hich\af1\dbch\af31505\loch\f1 tmxr_set_line_unit}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid9462171 \hich\af1\dbch\af31505\loch\f1 + (TMXR *mp, int line, UNIT *uptr) }{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid3806017 \loch\af1\dbch\af31505\hich\f1 \endash }{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid9462171 \hich\af1\dbch\af31505\loch\f1 }{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid3806017 +\hich\af1\dbch\af31505\loch\f1 Declare which unit polls for input on a given line (only needed if the input polling unit is different than the unit provided when the multiplexer was attached.}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid9462171 +\par }\pard \ltrpar\s21\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0\pararsid3806017 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid2698330 +\par }\pard \ltrpar\s21\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid8129972 +\par }\pard \ltrpar\s21\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0\pararsid8129972 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid8129972 \hich\af1\dbch\af31505\loch\f1 +The OS dependent serial I/O and socket routines should not need to be accessed by the terminal simulators. +\par }\pard\plain \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \f1\insrsid4550150 +\par {\*\bkmkstart _Toc345583859}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 6.3\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar +\jclisttab\tx390\wrapdefault\faauto\ls1\ilvl1\outlinelevel1\adjustright\rin0\lin390\itap0 \rtlch\fcs1 \ab\ai\af1\afs24\alang1025 \ltrch\fcs0 \b\i\fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Magnetic Tape Emulation Library{\*\bkmkend _Toc345583859} +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 SIMH supports the use of emulated magnetic tapes. Magnetic tapes are emulated as di\hich\af1\dbch\af31505\loch\f1 \hich\f1 +sk files containing both data records and metadata markers; the format is fully described in the paper \'93\loch\f1 \hich\f1 SIMH Magtape Representation and Handling\'94\loch\f1 +. SIMH provides a supporting library, sim_tape.c (and its header file, sim_tape.h), that abstracts handling o\hich\af1\dbch\af31505\loch\f1 f\hich\af1\dbch\af31505\loch\f1 + magnetic tapes. This allows support for multiple tape formats, without change to magnetic device simulators. +\par +\par \hich\af1\dbch\af31505\loch\f1 The magtape library does not require any special data structures. However, it does define some additional unit flags: +\par +\par \tab \hich\af1\dbch\af31505\loch\f1 MTUF_WLK\tab \tab unit is write\hich\af1\dbch\af31505\loch\f1 locked +\par +\par \hich\af1\dbch\af31505\loch\f1 If magtape simulators need to define private unit flags, those flags should begin at bit number MTUF_V_UF instead of UNIT_V_UF. The magtape library maintains the current magtape position in the }{\rtlch\fcs1 \ab\af1 +\ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 pos}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 field of the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 UNIT}{ +\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 structure. +\par +\par \hich\af1\dbch\af31505\loch\f1 Library sim_tape.c\hich\af1\dbch\af31505\loch\f1 provides the following routines to support emulated magnetic tapes: +\par +\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 sim_tape_attach}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (UNIT *uptr, char *cptr) \hich\f1 \endash \loch\f1 Attach tape unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 uptr }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 to file }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 cptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 . Tape +\par \hich\af1\dbch\af31505\loch\f1 Simulators should call this routine, rather than the standard attach_unit routine, to allow f\hich\af1\dbch\af31505\loch\f1 or future expansion of format support. +\par +\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape_detach}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (UNIT *uptr) \hich\f1 \endash +\loch\f1 Detach tape unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 from its current file. +\par +\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape_set_fmt}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 + (UNIT *uptr, int32 val, char *cptr, void *desc) \hich\f1 \endash \loch\f1 Set the tape format for unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 to the format specified \hich\af1\dbch\af31505\loch\f1 by string }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 cptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 . +\par +\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape_show_fmt}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 + (FILE *st, UNIT *uptr, int32 val, void *desc) \hich\f1 \endash \loch\f1 Write the tape format for unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 to the file specified by descriptor }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 st}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 . +\par +\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape_set_capac}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 + (UNIT *uptr, int32 val, char *cptr, void *desc) \hich\f1 \endash \hich\af1\dbch\af31505\loch\f1 Set the tape capacity for unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 to the capacity, in MB, specified by string }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 cptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 . +\par +\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape_show_capac}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 + (FILE *st, UNIT *uptr, int32 val, void *desc) \hich\f1 \endash \loch\f1 Write the capacity for unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 to the file specified by descriptor }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 st}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 . +\par }\pard\plain \ltrpar\s21\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape_rdr\hich\af1\dbch\af31505\loch\f1 ecf}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 + (UNIT *uptr, uint8 *buf, t_mtrlnt *tbc, t_mtrlnt max) \hich\f1 \endash \loch\f1 Forward read the next record on unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 into buffer }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 buf}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 of size }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 +\i\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 max}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 . Return the actual record size in }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tbc}{ +\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 . +\par }\pard\plain \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape_rdrecr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 + (UNIT *uptr, uint8 *buf, t_mtrlnt *tbc, t_mtrlnt max) \hich\f1 \endash \loch\f1 Revers\hich\af1\dbch\af31505\loch\f1 e read the next record on unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 +\af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 into buffer }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 buf}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 + of size }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 max}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 . Return the actual record size in }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 +\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tbc}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 . Note that the record is returned in forward order, that is, byte 0 of the record is stored in buf[0], and so on. + +\par +\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape_wrrecf}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (UNIT *uptr, u +\hich\af1\dbch\af31505\loch\f1 int8 buf, t_mtrlnt tbc) \hich\f1 \endash \loch\f1 Write buffer }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 of size }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tbc}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 as the next record on unit }{\rtlch\fcs1 +\ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 . +\par +\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape sprecf}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (UNIT *uptr, t_mtrlnt *tbc) +\hich\f1 \endash \loch\f1 Space unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 + forward one record. The size of the record is returned in }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tbc}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 . +\par +\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape_sprecr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (UNIT *up +\hich\af1\dbch\af31505\loch\f1 tr, t_mtrlnt *tbc) \hich\f1 \endash \loch\f1 Space unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 reverse one record. The size of the record is returned in tbc. +\par +\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape_wrtmk}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (UNIT *uptr) \hich\f1 \endash +\loch\f1 Write a tape mark on unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 . +\par +\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape_wreom}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (UNIT *uptr) \hich\f1 \endash +\loch\f1 Write an end-of-medium marker on unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (thi\hich\af1\dbch\af31505\loch\f1 +s effectively erases the rest of the tape). +\par +\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape_wrgap}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 + (UNIT *uptr, uint32 gaplen, uint32 bpi) \hich\f1 \endash \loch\f1 Write an erase gap on unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 of }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 gaplen}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 + tenths of an inch in length at a tape density of }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 bpi}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 bits per inch. +\par +\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape_rewind}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (UNIT *uptr) +\loch\af1\dbch\af31505\hich\f1 \endash \loch\f1 Rewind unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 +. This operation succeeds whether or not the unit is attached to a file. +\par +\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape_reset}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (UNIT *uptr) \hich\f1 \endash +\loch\f1 Reset unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 . This routine should be called when a tape unit is reset. + +\par +\par \hich\af1\dbch\af31505\loch\f1 t_bool }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape_bot}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (UNIT *uptr) \hich\f1 \endash +\loch\f1 Return TRUE if \hich\af1\dbch\af31505\loch\f1 unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 + is at beginning-of-tape. +\par +\par \hich\af1\dbch\af31505\loch\f1 t_bool }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape wrp}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (UNIT *uptr) \hich\f1 \endash +\loch\f1 Return TRUE if unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 is write-protected. +\par +\par \hich\af1\dbch\af31505\loch\f1 t_bool }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape_eot}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (UNIT *uptr) \hich\f1 \endash +\loch\f1 Return TRUE if unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 + has exceed the capacity specified of the specified unit (kept in uptr->capac). +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Sim_tape_attach}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 , }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 sim_tape_detach, sim_tape_set_fmt,}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 +sim_tape_show_fmt, sim_tape_set_capac}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 , and }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape_show_capac}{\rtlch\fcs1 \af1 +\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 return standard SCP status codes; the other magtape library routines return return private codes for success and failure. The currently def\hich\af1\dbch\af31505\loch\f1 +ined magtape status codes are: +\par +\par \tab \hich\af1\dbch\af31505\loch\f1 MTSE_OK\tab \tab operation successful +\par \tab \hich\af1\dbch\af31505\loch\f1 MTSE_UNATT\tab \tab unit is not attached to a file +\par \tab \hich\af1\dbch\af31505\loch\f1 MTSE_FMT\tab \tab unit specifies an unsupported tape file format +\par \tab \hich\af1\dbch\af31505\loch\f1 MTSE_IOERR\tab \tab host operating system I/O error during operation +\par \tab \hich\af1\dbch\af31505\loch\f1 MTSE_INVRL\tab \tab invalid record l\hich\af1\dbch\af31505\loch\f1 ength (exceeds maximum allowed) +\par \tab \hich\af1\dbch\af31505\loch\f1 MTSE_RECE\tab \tab record header contains error flag +\par \tab \hich\af1\dbch\af31505\loch\f1 MTSE_TMK\tab \tab tape mark encountered +\par \tab \hich\af1\dbch\af31505\loch\f1 MTSE_BOT\tab \tab beginning of tape encountered during reverse operation +\par \tab \hich\af1\dbch\af31505\loch\f1 MTSE_EOM\tab \tab end of medium encountered +\par \tab \hich\af1\dbch\af31505\loch\f1 MTSE_WRP\tab \tab write protected unit during wri\hich\af1\dbch\af31505\loch\f1 te operation +\par +\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Sim_tape_set_fmt,}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 sim_tape_show_fmt, sim_tape_set_capac, }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 and }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 +sim_tape_show_capac}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 should be referenced by an entry in the tape device\hich\f1 \rquote \loch\f1 s modifier list, as follows: +\par +\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \tab \hich\af2\dbch\af31505\loch\f2 MTAB tape_mod[] = \{ +\par }\pard \ltrpar\ql \fi720\li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \{\hich\af2\dbch\af31505\loch\f2 \hich\f2 MTAB_XTD|MTAB_VDV, 0, \'93\loch\f2 \hich\f2 FORMAT\'94\loch\f2 +\hich\f2 , \'93\loch\f2 \hich\f2 FORMAT\'94, +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \tab \hich\af2\dbch\af31505\loch\f2 \tab \hich\af2\dbch\af31505\loch\f2 &sim_tape_set_fmt, &sim_tape_show_fmt, NULL \} +, +\par }\pard \ltrpar\ql \fi720\li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \{\hich\af2\dbch\af31505\loch\f2 \hich\f2 MTAB_XTD|MTAB_VUN, 0, \'93\loch\f2 \hich\f2 CAPACITY\'94\loch\f2 +\hich\f2 , \'93\loch\f2 \hich\f2 CAPACITY\'94, +\par }\pard \ltrpar\ql \li1440\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin1440\itap0 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \hich\af2\dbch\af31505\loch\f2 &sim_tape_set_capac, &sim_tape_show_capac, NULL \}\hich\f2 , \'85 +\par }\pard \ltrpar\ql \fi720\li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \}\hich\af2\dbch\af31505\loch\f2 ; +\par {\*\bkmkstart _Toc345583860}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 6.4\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar +\jclisttab\tx390\wrapdefault\faauto\ls1\ilvl1\outlinelevel1\adjustright\rin0\lin390\itap0\pararsid9973523 \rtlch\fcs1 \ab\ai\af1\afs24\alang1025 \ltrch\fcs0 \b\i\fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid9973523 \hich\af1\dbch\af31505\loch\f1 Disk Emulation Library{\*\bkmkend _Toc345583860} +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0\pararsid9973523 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af1 \ltrch\fcs0 \f1\insrsid9973523 +\par \hich\af1\dbch\af31505\loch\f1 SIMH supports the use of disk drives. Disk dri\hich\af1\dbch\af31505\loch\f1 \hich\f1 ves as disk files containing both data records and metadata markers; the format is fully described in the paper \'93\loch\f1 \hich\f1 +SIMH Magtape Representation and Handling\'94\loch\f1 . SIMH provides a supporting library, sim_disk.c (and its header file, sim_disk.h), that abstracts h\hich\af1\dbch\af31505\loch\f1 a\hich\af1\dbch\af31505\loch\f1 +ndling of disk drives tapes. This allows support for disk formats, without change to magnetic device simulators. +\par +\par \hich\af1\dbch\af31505\loch\f1 The disk library does not require any special data structures. However, it does define some additional unit flags: +\par +\par \tab \hich\af1\dbch\af31505\loch\f1 DKUF_WLK\tab \tab unit is write\hich\af1\dbch\af31505\loch\f1 locked +\par +\par \hich\af1\dbch\af31505\loch\f1 If magtape simulators need to define private unit flags, those flags should begin at bit number DKUF_V_UF instead of UNIT_V_UF. The disk library maintains the current magtape position in the }{\rtlch\fcs1 \ab\af1 +\ltrch\fcs0 \b\f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 pos}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 field of the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 UNIT}{ +\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 structure. +\par \hich\af1\dbch\af31505\loch\f1 Library sim_tape.c pro\hich\af1\dbch\af31505\loch\f1 vides the following routines to support emulated magnetic tapes: +\par +\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid11167734 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid9973523 +\hich\af1\dbch\af31505\loch\f1 sim_disk_attach}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 (UNIT *uptr, char *cptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid11167734 \hich\af1\dbch\af31505\loch\f1 , s}{\rtlch\fcs1 \af1 +\ltrch\fcs0 \f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 ize_t sector_size, size_t xfer_element_size, t_bool dontautosize, uint32 debugbit, const char *drivetype, uint32 pdp11_tracksize, int complet\hich\af1\dbch\af31505\loch\f1 ion_delay) \hich\f1 +\endash \loch\f1 Attach disk unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 uptr }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 to file }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 +\i\f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 cptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 . Disk Simulators should call this routine, rather than the standard attach_unit routine, +\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid9973523 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid11167734 +\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid11167734 \hich\af1\dbch\af31505\loch\f1 sim_disk}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid9973523 +\hich\af1\dbch\af31505\loch\f1 _detach}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 (UNIT *uptr) \hich\f1 \endash \loch\f1 Detach }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid11167734 \hich\af1\dbch\af31505\loch\f1 disk}{ +\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9973523 +\hich\af1\dbch\af31505\loch\f1 from its current file. +\par +\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid11167734 \hich\af1\dbch\af31505\loch\f1 sim_disk}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 _set_fmt}{\rtlch\fcs1 \af1 +\ltrch\fcs0 \f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 (UNIT *u\hich\af1\dbch\af31505\loch\f1 ptr, int32 val, char *cptr, void *desc) \hich\f1 \endash \loch\f1 Set the }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid11167734 +\hich\af1\dbch\af31505\loch\f1 disk}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 format for unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 to the format specified by string }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 cptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9973523 . +\par +\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 sim_}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid11167734 \hich\af1\dbch\af31505\loch\f1 disk}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 +\b\f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 _show_fmt}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 (FILE *st, UNIT *uptr, int32 v}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid11167734 \hich\af1\dbch\af31505\loch\f1 +al, void *desc) \hich\f1 \endash \loch\f1 Write the disk}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 format for unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 uptr}{ +\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 to the file specified by descriptor }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 st}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9973523 . + +\par +\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid11167734 \hich\af1\dbch\af31505\loch\f1 sim_disk}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 _set_capac}{\rtlch\fcs1 \af1 +\ltrch\fcs0 \f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 (UNIT *uptr, int32 val, char *}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid11167734 \hich\af1\dbch\af31505\loch\f1 cptr, void *desc) \hich\f1 \endash \loch\f1 Set the disk}{\rtlch\fcs1 \af1 +\ltrch\fcs0 \f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 capacity for unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 + to the capacity, in MB, specified by string }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 cptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9973523 . +\par +\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid11167734 \hich\af1\dbch\af31505\loch\f1 sim_disk}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 _show_capac}{\rtlch\fcs1 \af1 +\ltrch\fcs0 \f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 (FILE *st, UNIT *uptr, int32 val, void *desc) \hich\f1 \endash \loch\f1 Write the capacity for unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 uptr} +{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 to the file specified by descriptor }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 st}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9973523 +. +\par }\pard\plain \ltrpar\s21\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid9973523 \rtlch\fcs1 \af1\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid9973523 +\par }\pard \ltrpar\s21\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid11167734 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid11167734 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\insrsid11167734 +\hich\af1\dbch\af31505\loch\f1 sim_disk_rdsect}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid11167734 \hich\af1\dbch\af31505\loch\f1 (UNIT *uptr, t_lba lba, uint8 *buf, t_seccnt *sectsread, , t_seccnt *sectstoread) \hich\f1 \endash \loch\f1 + Read up to sectstoread sec\hich\af1\dbch\af31505\loch\f1 tors from sector number lba on unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid11167734 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid11167734 +\hich\af1\dbch\af31505\loch\f1 into buffer }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid11167734 \hich\af1\dbch\af31505\loch\f1 buf}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid11167734 \hich\af1\dbch\af31505\loch\f1 . Return the number of sectors read in }{ +\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid11167734 \hich\af1\dbch\af31505\loch\f1 sectsread}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid11167734 . +\par }\pard\plain \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid11167734 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid11167734 +\par }\pard\plain \ltrpar\s21\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid11167734 \rtlch\fcs1 \af1\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid11167734 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\insrsid11167734 \hich\af1\dbch\af31505\loch\f1 sim_disk_rdsect_a}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid11167734 +\hich\af1\dbch\af31505\loch\f1 (UNIT *uptr, t_lba lba, uint8 *buf, t_seccnt *sectsread, , t_seccnt *sectstoread}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid15957281 \hich\af1\dbch\af31505\loch\f1 , DISK_PCALLBACK callback}{\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid11167734 \hich\af1\dbch\af31505\loch\f1 ) \hich\f1 \endash \loch\f1 Read up to sec\hich\af1\dbch\af31505\loch\f1 tstoread sectors from sector number lba on unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid11167734 \hich\af1\dbch\af31505\loch\f1 +uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid11167734 \hich\af1\dbch\af31505\loch\f1 into buffer }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid11167734 \hich\af1\dbch\af31505\loch\f1 buf}{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid15957281 +\hich\af1\dbch\af31505\loch\f1 asynchronously}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid11167734 \hich\af1\dbch\af31505\loch\f1 . Return the number of sectors read in }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid11167734 \hich\af1\dbch\af31505\loch\f1 +sectsread}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid15957281 \hich\af1\dbch\af31505\loch\f1 , and call callback routine on completion.}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid11167734 +\par }\pard\plain \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid11167734 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid11167734 +\par }\pard\plain \ltrpar\s21\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid15957281 \rtlch\fcs1 \af1\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid15957281 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\insrsid15957281 \hich\af1\dbch\af31505\loch\f1 sim_disk_wrsect}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid15957281 +\hich\af1\dbch\af31505\loch\f1 (UNIT *uptr, t_lba lba, uint8 *buf, t_seccnt *sectswritte\hich\af1\dbch\af31505\loch\f1 n, , t_seccnt *sectstowrite) \hich\f1 \endash \loch\f1 + Write sectstowrite sectors from buffer buf to disk sector number lba on unit uptr. Return the number of sectors written in }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid15957281 \hich\af1\dbch\af31505\loch\f1 sectswritten}{\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid15957281 . +\par }\pard\plain \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid15957281 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid15957281 +\par }\pard\plain \ltrpar\s21\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid15957281 \rtlch\fcs1 \af1\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid15957281 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\insrsid15957281 \hich\af1\dbch\af31505\loch\f1 sim_disk_wrsect_a}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid15957281 +\hich\af1\dbch\af31505\loch\f1 (UNIT *uptr, t_lba lba, uint8 *buf, t_seccnt *sectswritten, , t_seccnt *sectstowrite, DISK_PCALLBACK callback) \hich\f1 \endash \loch\f1 Write sectstowrite sectors from buffer buf to disk sector number lba on unit }{ +\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid15957281 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid15957281 \hich\af1\dbch\af31505\loch\f1 }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid15957281 \hich\af1\dbch\af31505\loch\f1 +asynchronously}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid15957281 \hich\af1\dbch\af31505\loch\f1 . Return the number of sectors written in }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid15957281 \hich\af1\dbch\af31505\loch\f1 sec\hich\af1\dbch\af31505\loch\f1 +tswritten}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid15957281 \hich\af1\dbch\af31505\loch\f1 , and call callback routine on completion. +\par }\pard\plain \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid15957281 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid15957281 +\par }\pard\plain \ltrpar\s21\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid11167734 \rtlch\fcs1 \af1\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid11167734 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\insrsid11167734 \hich\af1\dbch\af31505\loch\f1 sim_}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\insrsid15957281 +\hich\af1\dbch\af31505\loch\f1 disk_unload}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid11167734 \hich\af1\dbch\af31505\loch\f1 (UNIT *uptr) \hich\f1 \endash \loch\f1 }{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid15957281 \hich\af1\dbch\af31505\loch\f1 +Unload or detach a disk as needed.}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid11167734 +\par }\pard\plain \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid11167734 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid11167734 +\par }\pard\plain \ltrpar\s21\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid15957281 \rtlch\fcs1 \af1\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid15957281 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\insrsid15957281 \hich\af1\dbch\af31505\loch\f1 sim_disk_set_asynch}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid15957281 +\hich\af1\dbch\af31505\loch\f1 (UNIT *uptr, int latency) \hich\f1 \endash \loch\f1 Enable asynchronouos operation for I/O to disk unit uptr. +\par +\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\insrsid15957281 \hich\af1\dbch\af31505\loch\f1 sim_disk\hich\af1\dbch\af31505\loch\f1 _clr_asynch}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid15957281 \hich\af1\dbch\af31505\loch\f1 + (UNIT *uptr, int latency) \hich\f1 \endash \loch\f1 Disable asynchronouos operation for I/O to disk unit uptr. +\par +\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\insrsid15957281 \hich\af1\dbch\af31505\loch\f1 sim_disk_reset}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid15957281 \hich\af1\dbch\af31505\loch\f1 (UNIT *uptr) \hich\f1 \endash \loch\f1 + }{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid13897431 \hich\af1\dbch\af31505\loch\f1 Reset unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid13897431 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid13897431 +\hich\af1\dbch\af31505\loch\f1 . This routine should be called when a tape unit is reset.}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid15957281 +\par +\par \hich\af1\dbch\af31505\loch\f1 t_bool }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\insrsid15957281 \hich\af1\dbch\af31505\loch\f1 sim_disk_isavailable }{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid15957281 \hich\af1\dbch\af31505\loch\f1 (UNIT *uptr) \hich\f1 \endash +\loch\f1 \hich\af1\dbch\af31505\loch\f1 Check to see if disk is available for I/O, return TRUE if so. +\par +\par \hich\af1\dbch\af31505\loch\f1 t_bool }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\insrsid15957281 \hich\af1\dbch\af31505\loch\f1 sim_disk_isavailable_a }{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid15957281 \hich\af1\dbch\af31505\loch\f1 +(UNIT *uptr, DISK_PCALLBACK callback) \hich\f1 \endash \loch\f1 Check to see if disk is available for I/O asynchronously. Return }{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid13897431 \hich\af1\dbch\af31505\loch\f1 TRUE}{\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid15957281 \hich\af1\dbch\af31505\loch\f1 if so. +\par +\par }\pard\plain \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid13897431 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid15957281 \hich\af0\dbch\af31505\loch\f0 t_}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid13897431 \hich\af0\dbch\af31505\loch\f0 bool}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid15957281 \hich\af0\dbch\af31505\loch\f0 }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid15957281 \hich\af0\dbch\af31505\loch\f0 sim_disk_}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid13897431 \hich\af0\dbch\af31505\loch\f0 wrp}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid15957281 +\hich\af0\dbch\af31505\loch\f0 (UNIT *uptr) \hich\f0 \endash \loch\f0 }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid13897431 \hich\af1\dbch\af31505\loch\f1 Return TRUE if unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid13897431 +\hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid13897431 \hich\af1\dbch\af31505\loch\f1 is write-protected. +\par }\pard\plain \ltrpar\s21\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid15957281 \rtlch\fcs1 \af1\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid15957281 +\par }\pard \ltrpar\s21\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid13897431 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid13897431 \hich\af1\dbch\af31505\loch\f1 t_addr }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\insrsid13897431 +\hich\af1\dbch\af31505\loch\f1 sim_disk_size}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid13897431 \hich\af1\dbch\af31505\loch\f1 (UNIT *uptr) \hich\f1 \endash \loch\f1 get disk size +\par +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0\pararsid9973523 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\ab\af1 \ltrch\fcs0 \b\f1\insrsid13897431 \hich\af1\dbch\af31505\loch\f1 Sim_disk}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 _attach}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 +, }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid13897431 \hich\af1\dbch\af31505\loch\f1 sim_disk_detach, sim_disk}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 _set_fmt,}{\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid13897431 \hich\af1\dbch\af31505\loch\f1 sim_disk_show_fmt, sim_disk}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 +_set_capac}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 , and }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid13897431 \hich\af1\dbch\af31505\loch\f1 sim_tape_disk}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid9973523 +\hich\af1\dbch\af31505\loch\f1 _capac}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 return standard SCP status codes; the other }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid13897431 \hich\af1\dbch\af31505\loch\f1 disk}{ +\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 library routines return return private codes for success and failure. }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid13897431 \hich\af1\dbch\af31505\loch\f1 +Success status is DKSE_OK and any other value is an error. Errno usually will have the appropriate error code}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 : +\par +\par \tab \hich\af1\dbch\af31505\loch\f1 DKSE_OK\tab \tab operation successful +\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid13897431 +\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9973523 +\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid13897431 \hich\af1\dbch\af31505\loch\f1 Sim_disk}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 _set_fmt,}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9973523 +\hich\af1\dbch\af31505\loch\f1 }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 sim_}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid13897431 \hich\af1\dbch\af31505\loch\f1 disk}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 +\b\f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 _show_fm\hich\af1\dbch\af31505\loch\f1 t, sim_}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid13897431 \hich\af1\dbch\af31505\loch\f1 disk}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid9973523 +\hich\af1\dbch\af31505\loch\f1 _set_capac, }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 and }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 sim_}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 +\b\f1\insrsid13897431 \hich\af1\dbch\af31505\loch\f1 disk}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 _show_capac}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 + should be referenced by an entry in the }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid13897431 \hich\af1\dbch\af31505\loch\f1 disk}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 device\hich\f1 \rquote \loch\f1 +s modifier list, as follows: +\par +\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid9973523 \tab \hich\af2\dbch\af31505\loch\f2 MTAB tape_mod[] = \{ +\par }\pard \ltrpar\ql \fi720\li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid9973523 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid9973523 \{\hich\af2\dbch\af31505\loch\f2 \hich\f2 MTAB_XTD|MTAB_VDV, 0, \'93\loch\f2 \hich\f2 FORMAT +\'94\loch\f2 \hich\f2 , \'93\loch\f2 \hich\f2 FORMAT\'94, +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0\pararsid9973523 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid9973523 \tab \hich\af2\dbch\af31505\loch\f2 \tab }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid13897431 +\hich\af2\dbch\af31505\loch\f2 &sim_disk}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid9973523 \hich\af2\dbch\af31505\loch\f2 _set_fmt, &sim_}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid13897431 \hich\af2\dbch\af31505\loch\f2 disk}{\rtlch\fcs1 \af2 \ltrch\fcs0 +\f2\insrsid9973523 \hich\af2\dbch\af31505\loch\f2 _show_fmt, NULL \}, +\par }\pard \ltrpar\ql \fi720\li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid9973523 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid9973523 \{\hich\af2\dbch\af31505\loch\f2 MTAB_XT\hich\af2\dbch\af31505\loch\f2 \hich\f2 D|MTAB_VUN, 0, +\'93\loch\f2 \hich\f2 CAPACITY\'94\loch\f2 \hich\f2 , \'93\loch\f2 \hich\f2 CAPACITY\'94, +\par }\pard \ltrpar\ql \li1440\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin1440\itap0\pararsid9973523 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid13897431 \hich\af2\dbch\af31505\loch\f2 &sim_disk}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid9973523 +\hich\af2\dbch\af31505\loch\f2 _set_capac, &sim_}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid13897431 \hich\af2\dbch\af31505\loch\f2 disk}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid9973523 \hich\af2\dbch\af31505\loch\f2 _show_capac, NULL \}\hich\f2 , \'85 + +\par }\pard \ltrpar\ql \fi720\li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid9973523 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid9973523 \}\hich\af2\dbch\af31505\loch\f2 ; +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0\pararsid9973523 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9973523 +\par {\*\bkmkstart _Toc345583861}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 6.5\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar +\jclisttab\tx390\wrapdefault\faauto\ls1\ilvl1\outlinelevel1\adjustright\rin0\lin390\itap0 \rtlch\fcs1 \ab\ai\af1\afs24\alang1025 \ltrch\fcs0 \b\i\fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Breakpoint Support{\*\bkmkend _Toc345583861} +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 SCP provides underlying mechanisms to track multiple breakpoints of different types. Most VM\hich\f1 \rquote \loch\f1 s implement at\hich\af1\dbch\af31505\loch\f1 + least instruction execution breakpoints (type E); but a VM might also allow for break on read (type R), write (type W), and so on. Up to 26 different breakpoint types, identified by the letters A through Z, are supported. +\par +\par \hich\af1\dbch\af31505\loch\f1 The VM interface to the breakpo\hich\af1\dbch\af31505\loch\f1 int package consists of three variables and one subroutine: +\par +\par }\pard\plain \ltrpar\s21\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af1 +\ltrch\fcs0 \b\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_brk_types}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 \hich\f1 \endash \loch\f1 + initialized by the VM (usually in the CPU reset routine) to a mask of all supported breakpoints. +\par }\pard\plain \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \f1\insrsid4550150 +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_brk_dflt}{\rtlch\fcs1 \af1 +\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 \hich\f1 \endash \loch\f1 initialized by the VM to the mask for the default b\hich\af1\dbch\af31505\loch\f1 reakpoint type. +\par +\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_brk_summ}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 \hich\f1 \endash \loch\f1 maintained by SCP, providing a bit mask summary of whether any breakpoints of a particular type have been defined. +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 If the VM only implements one type of breakpoint, then }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_brk_summ}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 is non-zero if any breakpoints are set. +\par +\par \hich\af1\dbch\af31505\loch\f1 To test whether a breakpoint of particular type is set for an address, the VM calls +\par +\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uint32l }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 sim_brk_test}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (t_addr addr, int32 typ) \hich\f1 \endash \loch\f1 test to see if a breakpoint of type }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 +\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 typ}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 is set for location }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 addr}{ +\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 ; returns 0 if no, and a bit mask of all breakpoints that match typ if yes +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 Because }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_brk_test}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 + can be a lengthy procedure, it is usually prefaced with a test of }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_brk_summ}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 : +\par +\par \tab }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \hich\af2\dbch\af31505\loch\f2 if (sim_brk_summ && sim_brk_test (PC, SWMASK (\hich\f2 \lquote \loch\f2 E\hich\f2 \rquote \loch\f2 ))) \{ +\par }\pard \ltrpar\ql \fi720\li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \hich\af2\dbch\af31505\loch\f2 \} +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 T\hich\af1\dbch\af31505\loch\f1 +o accommodate more complex breakpoint schemes, SCP implements a concept of breakpoint spaces. Each breakpoint space is an orthogonal collection of breakpoints that are tracked independently. For example, in a symmetric multiprocessing simulation, breakp +\hich\af1\dbch\af31505\loch\f1 o\hich\af1\dbch\af31505\loch\f1 +int spaces could be assigned to each CPU to distinguish E (execution) breakpoints for different processors. SCP supports up to 64 breakpoint spaces; the space is specified by bits <31:26> of the }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 typ}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 argument to }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_brk_test}{\rtlch\fcs1 \af1 +\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 . By default, there is only one\hich\af1\dbch\af31505\loch\f1 breakpoint space (space 0). +\par +\par }{\*\themedata 504b030414000600080000002100e9de0fbfff0000001c020000130000005b436f6e74656e745f54797065735d2e786d6cac91cb4ec3301045f748fc83e52d4a +9cb2400825e982c78ec7a27cc0c8992416c9d8b2a755fbf74cd25442a820166c2cd933f79e3be372bd1f07b5c3989ca74aaff2422b24eb1b475da5df374fd9ad +5689811a183c61a50f98f4babebc2837878049899a52a57be670674cb23d8e90721f90a4d2fa3802cb35762680fd800ecd7551dc18eb899138e3c943d7e503b6 +b01d583deee5f99824e290b4ba3f364eac4a430883b3c092d4eca8f946c916422ecab927f52ea42b89a1cd59c254f919b0e85e6535d135a8de20f20b8c12c3b0 +0c895fcf6720192de6bf3b9e89ecdbd6596cbcdd8eb28e7c365ecc4ec1ff1460f53fe813d3cc7f5b7f020000ffff0300504b030414000600080000002100a5d6 +a7e7c0000000360100000b0000005f72656c732f2e72656c73848fcf6ac3300c87ef85bd83d17d51d2c31825762fa590432fa37d00e1287f68221bdb1bebdb4f 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a/doc/simh_faq.doc b/doc/simh_faq.doc index 09e08c9f..244ecfd5 100644 Binary files a/doc/simh_faq.doc and b/doc/simh_faq.doc differ diff --git a/doc/simh_vmio.doc b/doc/simh_vmio.doc new file mode 100644 index 00000000..cb6ba9fd Binary files /dev/null and b/doc/simh_vmio.doc differ diff --git a/doc/tx0_doc.doc b/doc/tx0_doc.doc new file mode 100644 index 00000000..87794940 Binary files /dev/null and b/doc/tx0_doc.doc differ diff --git a/doc/vax780_doc.doc b/doc/vax780_doc.doc index 07b7f872..7b708901 100644 Binary files a/doc/vax780_doc.doc and b/doc/vax780_doc.doc differ diff --git a/doc/vax_doc.doc b/doc/vax_doc.doc index 19a70329..a4af36d6 100644 Binary files a/doc/vax_doc.doc and b/doc/vax_doc.doc differ diff --git a/makefile b/makefile index 2f465e53..16317b51 100644 --- a/makefile +++ b/makefile @@ -98,6 +98,14 @@ ifeq ($(WIN32),) #*nix Environments (&& cygwin) ifeq (Darwin,$(OSTYPE)) OSNAME = OSX LIBEXT = dylib + ifeq (incopt,$(shell if $(TEST) -d /opt/local/include; then echo incopt; fi)) + INCPATH += /opt/local/include + OS_CCDEFS += -I/opt/local/include + endif + ifeq (libopt,$(shell if $(TEST) -d /opt/local/lib; then echo libopt; fi)) + LIBPATH += /opt/local/lib + OS_LDFLAGS += -L/opt/local/lib + endif # OSX's XCode gcc doesn't support LTO, but gcc built to explicitly enable it will work ifneq (,$(GCC_VERSION)) ifeq (,$(shell $(GCC) -v /dev/null 2>&1 | grep '\-\-enable-lto')) @@ -226,7 +234,7 @@ ifeq ($(WIN32),) #*nix Environments (&& cygwin) $(info *** Warning *** Some users have had problems using the www.tcpdump.org libpcap) $(info *** Warning *** components for simh networking. For best results, with) $(info *** Warning *** simh networking, it is recommended that you install the) - $(info *** Warning *** libpcap-dev package from your $(OSTYPE) distribution) + $(info *** Warning *** libpcap-dev package from your $(OSNAME) distribution) $(info *** Warning ***) endif else @@ -236,10 +244,10 @@ ifeq ($(WIN32),) #*nix Environments (&& cygwin) LIBEXT = $(LIBEXTSAVE) endif ifneq (,$(findstring USE_NETWORK,$(NETWORK_CCDEFS))$(findstring USE_SHARED,$(NETWORK_CCDEFS))) - # Given we have libpcap components, consider other network connections as well + # Given we have libpcap components, consider other network connections as well ifneq (,$(call find_lib,vdeplug)) # libvdeplug requires the use of the OS provided libpcap - ifeq (,$(findstring usr/local,$(NETWORK_CCDEFS))) + ifeq (,$(findstring usr/local,$(NETWORK_CCDEFS))) ifneq (,$(call find_include,libvdeplug)) # Provide support for vde networking NETWORK_CCDEFS += -DUSE_VDE_NETWORK @@ -248,6 +256,23 @@ ifeq ($(WIN32),) #*nix Environments (&& cygwin) endif endif endif + ifeq (,$(findstring USE_VDE_NETWORK,$(NETWORK_CCDEFS))) + # Support is available on Linux for libvdeplug. Advise on its usage + ifneq (,$(findstring Linux,$(OSTYPE))) + $(info *** Warning ***) + $(info *** Warning *** $(BUILD_SINGLE)Simulator$(BUILD_MULTIPLE) are being built with) + $(info *** Warning *** minimal libpcap networking support) + $(info *** Warning ***) + $(info *** Warning *** Simulators on your $(OSNAME) platform can also be built with) + $(info *** Warning *** extended Ethernet networking support by using VDE Ethernet.) + $(info *** Warning ***) + $(info *** Warning *** To build simulator(s) with extended networking support you) + $(info *** Warning *** should read 0readme_ethernet.txt and follow the instructions) + $(info *** Warning *** regarding the needed libvdeplug components for your $(OSNAME)) + $(info *** Warning *** platform) + $(info *** Warning ***) + endif + endif ifneq (,$(call find_include,linux/if_tun)) # Provide support for Tap networking on Linux NETWORK_CCDEFS += -DUSE_TAP_NETWORK @@ -269,13 +294,21 @@ ifeq ($(WIN32),) #*nix Environments (&& cygwin) NETWORK_OPT = $(NETWORK_CCDEFS) endif ifneq (binexists,$(shell if $(TEST) -e BIN; then echo binexists; fi)) - MKDIRBIN = if $(TEST) ! -e BIN; then mkdir BIN; fi + MKDIRBIN = mkdir -p BIN + endif + ifneq (,$(shell if $(TEST) -e .git-commit-id; then echo commit-id-exists; fi)) + GIT_COMMIT_ID=$(shell cat .git-commit-id) endif else #Win32 Environments (via MinGW32) GCC = gcc - GCC_Path := $(dir $(shell where gcc.exe)) + ifeq (XP,$(findstring XP,$(shell ver))) + GCC_Path := C:\MinGW\bin\ + else + GCC_Path := $(dir $(shell where gcc.exe)) + endif GCC_VERSION = $(word 3,$(shell $(GCC) --version)) + COMPILER_NAME = GCC Version: $(GCC_VERSION) LTO_EXCLUDE_VERSIONS = 4.5.2 ifeq (pthreads,$(shell if exist ..\windows-build\pthreads\Pre-built.2\include\pthread.h echo pthreads)) PTHREADS_CCDEFS = -DUSE_READER_THREAD -DPTW32_STATIC_LIB -I../windows-build/pthreads/Pre-built.2/include @@ -293,27 +326,31 @@ else endif endif ifeq (pcap,$(shell if exist ..\windows-build\winpcap\Wpdpack\include\pcap.h echo pcap)) - PCAP_CCDEFS = -I../windows-build/winpcap/Wpdpack/include -I$(GCC_Path)..\include\ddk -DUSE_SHARED NETWORK_LDFLAGS = - NETWORK_OPT = -DUSE_SHARED + NETWORK_OPT = -DUSE_SHARED -I../windows-build/winpcap/Wpdpack/include -I$(GCC_Path)..\include\ddk NETWORK_FEATURES = - dynamic networking support using windows-build provided libpcap components else ifeq (pcap,$(shell if exist $(dir $(GCC_Path))..\include\pcap.h echo pcap)) - PCAP_CCDEFS = -DUSE_SHARED -I$(GCC_Path)..\include\ddk NETWORK_LDFLAGS = - NETWORK_OPT = -DUSE_SHARED + NETWORK_OPT = -DUSE_SHARED -I$(GCC_Path)..\include\ddk NETWORK_FEATURES = - dynamic networking support using libpcap components found in the MinGW directories endif endif - OS_CCDEFS = -fms-extensions $(PTHREADS_CCDEFS) $(PCAP_CCDEFS) + OS_CCDEFS = -fms-extensions $(PTHREADS_CCDEFS) OS_LDFLAGS = -lm -lwsock32 -lwinmm $(PTHREADS_LDFLAGS) EXE = .exe ifneq (binexists,$(shell if exist BIN echo binexists)) MKDIRBIN = if not exist BIN mkdir BIN endif ifneq ($(USE_NETWORK),) - NETWORK_OPT = -DUSE_SHARED + NETWORK_OPT += -DUSE_SHARED endif + ifneq (,$(shell if exist .git-commit-id type .git-commit-id)) + GIT_COMMIT_ID=$(shell if exist .git-commit-id type .git-commit-id) + endif +endif +ifneq (,$(GIT_COMMIT_ID)) + CFLAGS_GIT = -DSIM_GIT_COMMIT_ID=$(GIT_COMMIT_ID) endif ifneq ($(DEBUG),) CFLAGS_G = -g -ggdb -g3 @@ -382,6 +419,10 @@ ifneq (clean,$(MAKECMDGOALS)) ifneq (,$(NETWORK_FEATURES)) $(info *** $(NETWORK_FEATURES).) endif + ifneq (,$(GIT_COMMIT_ID)) + $(info ***) + $(info *** git commit id is $(GIT_COMMIT_ID).) + endif $(info ***) endif ifneq ($(DONT_USE_ROMS),) @@ -395,7 +436,7 @@ endif CC_STD = -std=c99 CC_OUTSPEC = -o $@ -CC = $(GCC) $(CC_STD) -U__STRICT_ANSI__ $(CFLAGS_G) $(CFLAGS_O) -I . $(OS_CCDEFS) $(ROMS_OPT) +CC = $(GCC) $(CC_STD) -U__STRICT_ANSI__ $(CFLAGS_G) $(CFLAGS_O) $(CFLAGS_GIT) -I . $(OS_CCDEFS) $(ROMS_OPT) LDFLAGS = $(OS_LDFLAGS) $(NETWORK_LDFLAGS) $(LDFLAGS_O) # @@ -403,7 +444,7 @@ LDFLAGS = $(OS_LDFLAGS) $(NETWORK_LDFLAGS) $(LDFLAGS_O) # BIN = BIN/ SIM = scp.c sim_console.c sim_fio.c sim_timer.c sim_sock.c \ - sim_tmxr.c sim_ether.c sim_tape.c sim_disk.c + sim_tmxr.c sim_ether.c sim_tape.c sim_disk.c sim_serial.c # @@ -454,7 +495,8 @@ PDP11 = ${PDP11D}/pdp11_fp.c ${PDP11D}/pdp11_cpu.c ${PDP11D}/pdp11_dz.c \ ${PDP11D}/pdp11_rh.c ${PDP11D}/pdp11_tu.c ${PDP11D}/pdp11_cpumod.c \ ${PDP11D}/pdp11_cr.c ${PDP11D}/pdp11_rf.c ${PDP11D}/pdp11_dl.c \ ${PDP11D}/pdp11_ta.c ${PDP11D}/pdp11_rc.c ${PDP11D}/pdp11_kg.c \ - ${PDP11D}/pdp11_ke.c ${PDP11D}/pdp11_dc.c ${PDP11D}/pdp11_io_lib.c + ${PDP11D}/pdp11_ke.c ${PDP11D}/pdp11_dc.c ${PDP11D}/pdp11_dmc.c \ + ${PDP11D}/pdp11_io_lib.c PDP11_OPT = -DVM_PDP11 -I ${PDP11D} ${NETWORK_OPT} @@ -466,35 +508,99 @@ VAX = ${VAXD}/vax_cpu.c ${VAXD}/vax_cpu1.c ${VAXD}/vax_fpa.c ${VAXD}/vax_io.c \ ${PDP11D}/pdp11_rl.c ${PDP11D}/pdp11_rq.c ${PDP11D}/pdp11_ts.c \ ${PDP11D}/pdp11_dz.c ${PDP11D}/pdp11_lp.c ${PDP11D}/pdp11_tq.c \ ${PDP11D}/pdp11_xq.c ${PDP11D}/pdp11_ry.c ${PDP11D}/pdp11_vh.c \ - ${PDP11D}/pdp11_cr.c ${PDP11D}/pdp11_io_lib.c + ${PDP11D}/pdp11_cr.c ${PDP11D}/pdp11_dmc.c ${PDP11D}/pdp11_io_lib.c VAX_OPT = -DVM_VAX -DUSE_INT64 -DUSE_ADDR64 -I ${VAXD} -I ${PDP11D} ${NETWORK_OPT} +VAX610 = ${VAXD}/vax_cpu.c ${VAXD}/vax_cpu1.c ${VAXD}/vax_fpa.c \ + ${VAXD}/vax_cis.c ${VAXD}/vax_octa.c ${VAXD}/vax_cmode.c \ + ${VAXD}/vax_mmu.c ${VAXD}/vax_sys.c ${VAXD}/vax_syscm.c \ + ${VAXD}/vax610_stddev.c ${VAXD}/vax610_sysdev.c \ + ${VAXD}/vax610_io.c ${VAXD}/vax610_syslist.c ${VAXD}/vax610_mem.c \ + ${PDP11D}/pdp11_rl.c ${PDP11D}/pdp11_rq.c ${PDP11D}/pdp11_ts.c \ + ${PDP11D}/pdp11_dz.c ${PDP11D}/pdp11_lp.c ${PDP11D}/pdp11_tq.c \ + ${PDP11D}/pdp11_xq.c ${PDP11D}/pdp11_ry.c ${PDP11D}/pdp11_vh.c \ + ${PDP11D}/pdp11_cr.c ${PDP11D}/pdp11_io_lib.c +VAX610_OPT = -DVM_VAX -DVAX_610 -DUSE_INT64 -DUSE_ADDR64 -I ${VAXD} -I ${PDP11D} ${NETWORK_OPT} + +VAX630 = ${VAXD}/vax_cpu.c ${VAXD}/vax_cpu1.c ${VAXD}/vax_fpa.c \ + ${VAXD}/vax_cis.c ${VAXD}/vax_octa.c ${VAXD}/vax_cmode.c \ + ${VAXD}/vax_mmu.c ${VAXD}/vax_sys.c ${VAXD}/vax_syscm.c \ + ${VAXD}/vax_watch.c ${VAXD}/vax630_stddev.c ${VAXD}/vax630_sysdev.c \ + ${VAXD}/vax630_io.c ${VAXD}/vax630_syslist.c \ + ${PDP11D}/pdp11_rl.c ${PDP11D}/pdp11_rq.c ${PDP11D}/pdp11_ts.c \ + ${PDP11D}/pdp11_dz.c ${PDP11D}/pdp11_lp.c ${PDP11D}/pdp11_tq.c \ + ${PDP11D}/pdp11_xq.c ${PDP11D}/pdp11_ry.c ${PDP11D}/pdp11_vh.c \ + ${PDP11D}/pdp11_cr.c ${PDP11D}/pdp11_dmc.c ${PDP11D}/pdp11_io_lib.c +VAX620_OPT = -DVM_VAX -DVAX_620 -DUSE_INT64 -DUSE_ADDR64 -I ${VAXD} -I ${PDP11D} ${NETWORK_OPT} +VAX630_OPT = -DVM_VAX -DVAX_630 -DUSE_INT64 -DUSE_ADDR64 -I ${VAXD} -I ${PDP11D} ${NETWORK_OPT} + + +VAX730 = ${VAXD}/vax_cpu.c ${VAXD}/vax_cpu1.c ${VAXD}/vax_fpa.c \ + ${VAXD}/vax_cis.c ${VAXD}/vax_octa.c ${VAXD}/vax_cmode.c \ + ${VAXD}/vax_mmu.c ${VAXD}/vax_sys.c ${VAXD}/vax_syscm.c \ + ${VAXD}/vax730_stddev.c ${VAXD}/vax730_sys.c \ + ${VAXD}/vax730_mem.c ${VAXD}/vax730_uba.c ${VAXD}/vax730_rb.c \ + ${VAXD}/vax730_syslist.c \ + ${PDP11D}/pdp11_rl.c ${PDP11D}/pdp11_rq.c ${PDP11D}/pdp11_ts.c \ + ${PDP11D}/pdp11_dz.c ${PDP11D}/pdp11_lp.c ${PDP11D}/pdp11_tq.c \ + ${PDP11D}/pdp11_xu.c ${PDP11D}/pdp11_ry.c ${PDP11D}/pdp11_cr.c \ + ${PDP11D}/pdp11_hk.c ${PDP11D}/pdp11_vh.c ${PDP11D}/pdp11_dmc.c \ + ${PDP11D}/pdp11_io_lib.c +VAX730_OPT = -DVM_VAX -DVAX_730 -DUSE_INT64 -DUSE_ADDR64 -I VAX -I ${PDP11D} ${NETWORK_OPT} + + +VAX750 = ${VAXD}/vax_cpu.c ${VAXD}/vax_cpu1.c ${VAXD}/vax_fpa.c \ + ${VAXD}/vax_cis.c ${VAXD}/vax_octa.c ${VAXD}/vax_cmode.c \ + ${VAXD}/vax_mmu.c ${VAXD}/vax_sys.c ${VAXD}/vax_syscm.c \ + ${VAXD}/vax750_stddev.c ${VAXD}/vax750_cmi.c \ + ${VAXD}/vax750_mem.c ${VAXD}/vax750_uba.c ${VAXD}/vax7x0_mba.c \ + ${VAXD}/vax750_syslist.c \ + ${PDP11D}/pdp11_rl.c ${PDP11D}/pdp11_rq.c ${PDP11D}/pdp11_ts.c \ + ${PDP11D}/pdp11_dz.c ${PDP11D}/pdp11_lp.c ${PDP11D}/pdp11_tq.c \ + ${PDP11D}/pdp11_xu.c ${PDP11D}/pdp11_ry.c ${PDP11D}/pdp11_cr.c \ + ${PDP11D}/pdp11_hk.c ${PDP11D}/pdp11_rp.c ${PDP11D}/pdp11_tu.c \ + ${PDP11D}/pdp11_vh.c ${PDP11D}/pdp11_dmc.c ${PDP11D}/pdp11_io_lib.c +VAX750_OPT = -DVM_VAX -DVAX_750 -DUSE_INT64 -DUSE_ADDR64 -I VAX -I ${PDP11D} ${NETWORK_OPT} + + VAX780 = ${VAXD}/vax_cpu.c ${VAXD}/vax_cpu1.c ${VAXD}/vax_fpa.c \ ${VAXD}/vax_cis.c ${VAXD}/vax_octa.c ${VAXD}/vax_cmode.c \ ${VAXD}/vax_mmu.c ${VAXD}/vax_sys.c ${VAXD}/vax_syscm.c \ ${VAXD}/vax780_stddev.c ${VAXD}/vax780_sbi.c \ - ${VAXD}/vax780_mem.c ${VAXD}/vax780_uba.c ${VAXD}/vax780_mba.c \ + ${VAXD}/vax780_mem.c ${VAXD}/vax780_uba.c ${VAXD}/vax7x0_mba.c \ ${VAXD}/vax780_fload.c ${VAXD}/vax780_syslist.c \ ${PDP11D}/pdp11_rl.c ${PDP11D}/pdp11_rq.c ${PDP11D}/pdp11_ts.c \ ${PDP11D}/pdp11_dz.c ${PDP11D}/pdp11_lp.c ${PDP11D}/pdp11_tq.c \ ${PDP11D}/pdp11_xu.c ${PDP11D}/pdp11_ry.c ${PDP11D}/pdp11_cr.c \ ${PDP11D}/pdp11_rp.c ${PDP11D}/pdp11_tu.c ${PDP11D}/pdp11_hk.c \ - ${PDP11D}/pdp11_vh.c ${PDP11D}/pdp11_io_lib.c + ${PDP11D}/pdp11_vh.c ${PDP11D}/pdp11_dmc.c ${PDP11D}/pdp11_io_lib.c VAX780_OPT = -DVM_VAX -DVAX_780 -DUSE_INT64 -DUSE_ADDR64 -I VAX -I ${PDP11D} ${NETWORK_OPT} +VAX860 = ${VAXD}/vax_cpu.c ${VAXD}/vax_cpu1.c ${VAXD}/vax_fpa.c \ + ${VAXD}/vax_cis.c ${VAXD}/vax_octa.c ${VAXD}/vax_cmode.c \ + ${VAXD}/vax_mmu.c ${VAXD}/vax_sys.c ${VAXD}/vax_syscm.c \ + ${VAXD}/vax860_stddev.c ${VAXD}/vax860_sbia.c \ + ${VAXD}/vax860_abus.c ${VAXD}/vax780_uba.c ${VAXD}/vax7x0_mba.c \ + ${VAXD}/vax860_syslist.c \ + ${PDP11D}/pdp11_rl.c ${PDP11D}/pdp11_rq.c ${PDP11D}/pdp11_ts.c \ + ${PDP11D}/pdp11_dz.c ${PDP11D}/pdp11_lp.c ${PDP11D}/pdp11_tq.c \ + ${PDP11D}/pdp11_xu.c ${PDP11D}/pdp11_ry.c ${PDP11D}/pdp11_cr.c \ + ${PDP11D}/pdp11_rp.c ${PDP11D}/pdp11_tu.c ${PDP11D}/pdp11_hk.c \ + ${PDP11D}/pdp11_vh.c ${PDP11D}/pdp11_dmc.c ${PDP11D}/pdp11_io_lib.c +VAX860_OPT = -DVM_VAX -DVAX_860 -DUSE_INT64 -DUSE_ADDR64 -I VAX -I ${PDP11D} ${NETWORK_OPT} + + PDP10D = PDP10 PDP10 = ${PDP10D}/pdp10_fe.c ${PDP11D}/pdp11_dz.c ${PDP10D}/pdp10_cpu.c \ ${PDP10D}/pdp10_ksio.c ${PDP10D}/pdp10_lp20.c ${PDP10D}/pdp10_mdfp.c \ ${PDP10D}/pdp10_pag.c ${PDP10D}/pdp10_rp.c ${PDP10D}/pdp10_sys.c \ ${PDP10D}/pdp10_tim.c ${PDP10D}/pdp10_tu.c ${PDP10D}/pdp10_xtnd.c \ - ${PDP11D}/pdp11_pt.c ${PDP11D}/pdp11_ry.c \ - ${PDP11D}/pdp11_cr.c + ${PDP11D}/pdp11_pt.c ${PDP11D}/pdp11_ry.c ${PDP11D}/pdp11_cr.c PDP10_OPT = -DVM_PDP10 -DUSE_INT64 -I ${PDP10D} -I ${PDP11D} - PDP8D = PDP8 PDP8 = ${PDP8D}/pdp8_cpu.c ${PDP8D}/pdp8_clk.c ${PDP8D}/pdp8_df.c \ ${PDP8D}/pdp8_dt.c ${PDP8D}/pdp8_lp.c ${PDP8D}/pdp8_mt.c \ @@ -632,14 +738,34 @@ SWTP6800MP-A2 = ${SWTP6800C}/mp-a2.c ${SWTP6800C}/m6800.c ${SWTP6800C}/m6810.c \ ${SWTP6800C}/mp-b2.c ${SWTP6800C}/mp-8m.c ${SWTP6800C}/i2716.c SWTP6800_OPT = -I ${SWTP6800D} +DISPLAYD = display +ifeq ($(WIN32),) + ifeq (x11,$(shell if $(TEST) -e /usr/include/X11/Intrinsic.h ; then echo x11; fi)) + DISPLAYL = ${DISPLAYD}/display.c $(DISPLAYD)/x11.c + DISPLAY_OPT = -DUSE_DISPLAY -I/usr/X11/include -lXt -lX11 -lm + else + DISPLAYL = + DISPLAY_OPT = + endif +else + DISPLAYL = ${DISPLAYD}/display.c $(DISPLAYD)/win32.c + DISPLAY_OPT = -DUSE_DISPLAY +endif + +TX0D = TX-0 +TX0 = ${TX0D}/tx0_cpu.c ${TX0D}/tx0_dpy.c ${TX0D}/tx0_stddev.c \ + ${TX0D}/tx0_sys.c ${TX0D}/tx0_sys_orig.c ${DISPLAYL} +TX0_OPT = -I ${TX0D} $(DISPLAY_OPT) + # # Build everything # ALL = pdp1 pdp4 pdp7 pdp8 pdp9 pdp15 pdp11 pdp10 \ - vax vax780 nova eclipse hp2100 i1401 i1620 s3 \ - altair altairz80 gri i7094 ibm1130 id16 \ - id32 sds lgp h316 swtp6800mp-a swtp6800mp-a2 + vax vax610 vax620 vax630 vax730 vax750 vax780 vax860 \ + nova eclipse hp2100 i1401 i1620 s3 altair altairz80 gri \ + i7094 ibm1130 id16 id32 sds lgp h316 \ + swtp6800mp-a swtp6800mp-a2 tx-0 all : ${ALL} @@ -726,12 +852,48 @@ ${BIN}vax${EXE} : ${VAX} ${SIM} ${BUILD_ROMS} ${MKDIRBIN} ${CC} ${VAX} ${SIM} ${VAX_OPT} $(CC_OUTSPEC) ${LDFLAGS} +vax610 : ${BIN}vax610${EXE} + +${BIN}vax610${EXE} : ${VAX610} ${SIM} ${BUILD_ROMS} + ${MKDIRBIN} + ${CC} ${VAX610} ${SIM} ${VAX610_OPT} -o $@ ${LDFLAGS} + +vax620 : ${BIN}vax620${EXE} + +${BIN}vax620${EXE} : ${VAX630} ${SIM} ${BUILD_ROMS} + ${MKDIRBIN} + ${CC} ${VAX630} ${SIM} ${VAX620_OPT} -o $@ ${LDFLAGS} + +vax630 : ${BIN}vax630${EXE} + +${BIN}vax630${EXE} : ${VAX630} ${SIM} ${BUILD_ROMS} + ${MKDIRBIN} + ${CC} ${VAX630} ${SIM} ${VAX630_OPT} -o $@ ${LDFLAGS} + +vax730 : ${BIN}vax730${EXE} + +${BIN}vax730${EXE} : ${VAX730} ${SIM} ${BUILD_ROMS} + ${MKDIRBIN} + ${CC} ${VAX730} ${SIM} ${VAX730_OPT} -o $@ ${LDFLAGS} + +vax750 : ${BIN}vax750${EXE} + +${BIN}vax750${EXE} : ${VAX750} ${SIM} ${BUILD_ROMS} + ${MKDIRBIN} + ${CC} ${VAX750} ${SIM} ${VAX750_OPT} -o $@ ${LDFLAGS} + vax780 : ${BIN}vax780${EXE} ${BIN}vax780${EXE} : ${VAX780} ${SIM} ${BUILD_ROMS} ${MKDIRBIN} ${CC} ${VAX780} ${SIM} ${VAX780_OPT} $(CC_OUTSPEC) ${LDFLAGS} +vax860 : ${BIN}vax860${EXE} + +${BIN}vax860${EXE} : ${VAX860} ${SIM} ${BUILD_ROMS} + ${MKDIRBIN} + ${CC} ${VAX860} ${SIM} ${VAX860_OPT} $(CC_OUTSPEC) ${LDFLAGS} + nova : ${BIN}nova${EXE} ${BIN}nova${EXE} : ${NOVA} ${SIM} @@ -839,3 +1001,10 @@ swtp6800mp-a2 : ${BIN}swtp6800mp-a2${EXE} ${BIN}swtp6800mp-a2${EXE} : ${SWTP6800MP-A2} ${SIM} ${MKDIRBIN} ${CC} ${SWTP6800MP-A2} ${SIM} ${SWTP6800_OPT} $(CC_OUTSPEC) ${LDFLAGS} + +tx-0 : ${BIN}tx-0${EXE} + +${BIN}tx-0${EXE} : ${TX0} ${SIM} + ${MKDIRBIN} + ${CC} ${TX0} ${SIM} ${TX0_OPT} $(CC_OUTSPEC) ${LDFLAGS} + diff --git a/scp.c b/scp.c index f3db52ea..db8f2471 100644 --- a/scp.c +++ b/scp.c @@ -217,10 +217,19 @@ #include "sim_defs.h" #include "sim_rev.h" -#include "sim_tmxr.h" +#include "sim_disk.h" +#include "sim_tape.h" +#include "sim_ether.h" +#include "sim_serial.h" +#include "sim_sock.h" #include #include #include +#if defined(_WIN32) +#include +#else +#include +#endif #include #if defined(HAVE_DLOPEN) /* Dynamic Readline support */ @@ -302,37 +311,26 @@ /* Asynch I/O support */ #if defined (SIM_ASYNCH_IO) -pthread_mutex_t sim_asynch_lock = PTHREAD_MUTEX_INITIALIZER; -pthread_cond_t sim_idle_wake = PTHREAD_COND_INITIALIZER; +pthread_mutex_t sim_asynch_lock = PTHREAD_MUTEX_INITIALIZER; +pthread_cond_t sim_asynch_wake = PTHREAD_COND_INITIALIZER; + pthread_mutex_t sim_timer_lock = PTHREAD_MUTEX_INITIALIZER; pthread_cond_t sim_timer_wake = PTHREAD_COND_INITIALIZER; pthread_mutex_t sim_tmxr_poll_lock = PTHREAD_MUTEX_INITIALIZER; pthread_cond_t sim_tmxr_poll_cond = PTHREAD_COND_INITIALIZER; int32 sim_tmxr_poll_count; pthread_t sim_asynch_main_threadid; -UNIT * volatile sim_asynch_queue = QUEUE_LIST_END; -UNIT * volatile sim_wallclock_queue = QUEUE_LIST_END; -UNIT * volatile sim_wallclock_entry = NULL; -UNIT * volatile sim_clock_cosched_queue = QUEUE_LIST_END; +UNIT * volatile sim_asynch_queue; +UNIT * volatile sim_wallclock_queue; +UNIT * volatile sim_wallclock_entry; +UNIT * volatile sim_clock_cosched_queue; +t_bool sim_asynch_enabled = TRUE; int32 sim_asynch_check; int32 sim_asynch_latency = 4000; /* 4 usec interrupt latency */ int32 sim_asynch_inst_latency = 20; /* assume 5 mip simulator */ -#endif +#else t_bool sim_asynch_enabled = FALSE; - -/* VM interface */ - -extern char sim_name[]; -extern DEVICE *sim_devices[]; -extern REG *sim_PC; -extern const char *sim_stop_messages[]; -extern t_stat sim_instr (void); -extern t_stat sim_load (FILE *ptr, char *cptr, char *fnam, int32 flag); -extern int32 sim_emax; -extern t_stat fprint_sym (FILE *ofile, t_addr addr, t_value *val, - UNIT *uptr, int32 sw); -extern t_stat parse_sym (char *cptr, t_addr addr, UNIT *uptr, t_value *val, - int32 sw); +#endif /* The per-simulator init routine is a weak global that defaults to NULL The other per-simulator pointers can be overrriden by the init routine */ @@ -353,6 +351,8 @@ t_stat set_dev_enbdis (DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr); t_stat set_dev_debug (DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr); t_stat set_unit_enbdis (DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr); t_stat ssh_break (FILE *st, char *cptr, int32 flg); +t_stat set_default_cmd (int32 flg, char *cptr); +t_stat pwd_cmd (int32 flg, char *cptr); t_stat show_cmd_fi (FILE *ofile, int32 flag, char *cptr); t_stat show_config (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr); t_stat show_queue (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr); @@ -366,6 +366,7 @@ t_stat show_dev_logicals (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char * t_stat show_dev_modifiers (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr); t_stat show_dev_show_commands (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr); t_stat show_version (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr); +t_stat show_default (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr); t_stat show_break (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr); t_stat show_on (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr); t_stat show_device (FILE *st, DEVICE *dptr, int32 flag); @@ -399,7 +400,7 @@ char *get_sim_sw (char *cptr); t_stat get_aval (t_addr addr, DEVICE *dptr, UNIT *uptr); t_value get_rval (REG *rptr, uint32 idx); void put_rval (REG *rptr, uint32 idx, t_value val); -t_value strtotv (char *inptr, char **endptr, uint32 radix); +t_value strtotv (const char *inptr, char **endptr, uint32 radix); void fprint_help (FILE *st); void fprint_stopped (FILE *st, t_stat r); void fprint_capac (FILE *st, DEVICE *dptr, UNIT *uptr); @@ -429,7 +430,7 @@ t_stat ex_addr (FILE *ofile, int32 flag, t_addr addr, DEVICE *dptr, UNIT *uptr); t_stat dep_addr (int32 flag, char *cptr, t_addr addr, DEVICE *dptr, UNIT *uptr, int32 dfltinc); t_stat step_svc (UNIT *ptr); -void sub_args (char *instr, char *tmpbuf, int32 maxstr, char *do_arg[]); +void sub_args (char *instr, size_t instr_size, char *do_arg[]); t_stat shift_args (char *do_arg[], size_t arg_count); t_stat set_on (int32 flag, char *cptr); t_stat set_verify (int32 flag, char *cptr); @@ -438,7 +439,7 @@ t_stat set_quiet (int32 flag, char *cptr); t_stat set_asynch (int32 flag, char *cptr); t_stat do_cmd_label (int32 flag, char *cptr, char *label); void int_handler (int signal); -void run_cmd_message (const char *unechod_cmdline, t_stat r); +t_stat set_prompt (int32 flag, char *cptr); /* Global data */ @@ -475,6 +476,7 @@ FILE *sim_log = NULL; /* log file */ FILEREF *sim_log_ref = NULL; /* log file file reference */ FILE *sim_deb = NULL; /* debug file */ FILEREF *sim_deb_ref = NULL; /* debug file file reference */ +char *sim_prompt = NULL; /* prompt string */ static FILE *sim_gotofile; /* the currently open do file */ static int32 sim_goto_line[MAX_DO_NEST_LVL+1]; /* the current line number in the currently open do file */ static int32 sim_do_echo = 0; /* the echo status of the currently open do file */ @@ -640,6 +642,10 @@ static CTAB cmd_table[] = { "exi{t}|q{uit}|by{e} exit from simulation\n" }, { "QUIT", &exit_cmd, 0, NULL }, { "BYE", &exit_cmd, 0, NULL }, + { "CD", &set_default_cmd, 0, + "cd set the current directory\n" }, + { "PWD", &pwd_cmd, 0, + "pwd show current directory\n" }, { "SET", &set_cmd, 0, "set console arg{,arg...} set console options\n" "set console WRU specify console drop to simh char\n" @@ -649,7 +655,8 @@ static CTAB cmd_table[] = { "set console TELNET=port specify console telnet port\n" "set console TELNET=LOG=log_file\n" " specify console telnet logging to the\n" - " specified destination {LOG,STDOUT,DEBUG or filename)\n" + " specified destination {LOG,STDOUT,STDERR,DEBUG\n" + " or filename)\n" "set console TELNET=NOLOG disables console telnet logging\n" "set console TELNET=BUFFERED[=bufsize]\n" " specify console telnet buffering\n" @@ -658,18 +665,20 @@ static CTAB cmd_table[] = { "set console TELNET=UNBUFFERED\n" " disables console telnet buffering\n" "set console NOTELNET disable console telnet\n" + "set console SERIAL=serialport[;config]\n" + " specify console serial port and optionally\n" + " the port config (i.e. ;9600-8n1)\n" + "set console NOSERIAL disable console serial session\n" "set console LOG=log_file enable console logging to the\n" - " specified destination {STDOUT,DEBUG or filename)\n" + " specified destination {STDOUT,STDERR,DEBUG\n" + " or filename)\n" "set console NOLOG disable console logging\n" - "set console DEBUG=dbg_file\n" - " enable console debugging to the\n" - " specified destination {LOG, STDOUT or filename)\n" - "set console NODEBUG disable console debugging\n" + "set default set the current directory\n" "set log log_file specify the log destination\n" " (STDOUT,DEBUG or filename)\n" "set nolog disables any currently active logging\n" "set debug debug_file specify the debug destination\n" - " (STDOUT,LOG or filename)\n" + " (STDOUT,STDERR,LOG or filename)\n" "set nodebug disables any currently active debug output\n" "set break set breakpoints\n" "set nobreak clear breakpoints\n" @@ -691,6 +700,7 @@ static CTAB cmd_table[] = { "set nomessage disables display of command file error messages\n" "set quiet disables suppression of some output and messages\n" "set noquiet re-enables suppression of some output and messages\n" + "set prompt \"string\" sets an alternate simulator prompt string\n" "set OCT|DEC|HEX set device display radix\n" "set ENABLED enable device\n" "set DISABLED disable device\n" @@ -714,6 +724,7 @@ static CTAB cmd_table[] = { "sh{ow} th{rottle} show simulation rate\n" "sh{ow} a{synch} show asynchronouse I/O state\n" "sh{ow} ve{rsion} show simulator version\n" + "sh{ow} def{ault} show current directory\n" "sh{ow} RADIX show device display radix\n" "sh{ow} DEBUG show device debug flags\n" "sh{ow} MODIFIERS show device modifiers\n" @@ -722,7 +733,8 @@ static CTAB cmd_table[] = { "sh{ow} {arg,...} show device parameters\n" "sh{ow} {arg,...} show unit parameters\n" "sh{ow} ethernet show ethernet devices\n" - "sh{ow} multiplexer show multiplexer devices\n" + "sh{ow} serial show serial devices\n" + "sh{ow} multiplexer show open multiplexer devices\n" "sh{ow} clocks show calibrated timers\n" "sh{ow} on show on condition actions\n" }, { "DO", &do_cmd, 1, @@ -749,12 +761,12 @@ static CTAB cmd_table[] = { "echo display \n" }, { "ASSERT", &assert_cmd, 0, "assert {} test simulator state against condition\n" }, - { "HELP", &help_cmd, 0, - "h{elp} type this message\n" - "h{elp} type help for command\n" }, { "!", &spawn_cmd, 0, "! execute local command interpreter\n" "! execute local host command\n" }, + { "HELP", &help_cmd, 0, + "h{elp} type this message\n" + "h{elp} type help for command\n" }, { NULL, NULL, 0 } }; @@ -777,7 +789,7 @@ int setenv(const char *envname, const char *envval, int overwrite) int main (int argc, char *argv[]) { -char cbuf[CBUFSIZE], gbuf[CBUFSIZE], *cptr, *cptr2; +char cbuf[4*CBUFSIZE], gbuf[CBUFSIZE], *cptr, *cptr2; char nbuf[PATH_MAX + 7]; int32 i, sw; t_bool lookswitch; @@ -788,6 +800,7 @@ CTAB *cmdp; argc = ccommand (&argv); #endif +set_prompt (0, "sim>"); /* start with set standard prompt */ *cbuf = 0; /* init arg buffer */ sim_switches = 0; /* init switches */ lookswitch = TRUE; @@ -802,7 +815,7 @@ for (i = 1; i < argc; i++) { /* loop thru args */ sim_switches = sim_switches | sw; } else { - if ((strlen (argv[i]) + strlen (cbuf) + 3) >= CBUFSIZE) { + if ((strlen (argv[i]) + strlen (cbuf) + 3) >= sizeof(cbuf)) { fprintf (stderr, "Argument string too long\n"); return 0; } @@ -815,6 +828,7 @@ for (i = 1; i < argc; i++) { /* loop thru args */ sim_quiet = sim_switches & SWMASK ('Q'); /* -q means quiet */ sim_on_inherit = sim_switches & SWMASK ('O'); /* -o means inherit on state */ +sim_init_sock (); /* init socket capabilities */ AIO_INIT; /* init Asynch I/O */ if (sim_vm_init != NULL) /* call once only */ (*sim_vm_init)(); @@ -885,21 +899,22 @@ else if (*argv[0]) { /* sim name arg? */ stat = SCPE_BARE_STATUS(stat); /* remove possible flag */ while (stat != SCPE_EXIT) { /* in case exit */ - if ((cptr = sim_brk_getact (cbuf, CBUFSIZE))) /* pending action? */ - printf ("sim> %s\n", cptr); /* echo */ + if ((cptr = sim_brk_getact (cbuf, sizeof(cbuf)))) /* pending action? */ + printf ("%s%s\n", sim_prompt, cptr); /* echo */ else if (sim_vm_read != NULL) { /* sim routine? */ - printf ("sim> "); /* prompt */ - cptr = (*sim_vm_read) (cbuf, CBUFSIZE, stdin); + printf ("%s", sim_prompt); /* prompt */ + cptr = (*sim_vm_read) (cbuf, sizeof(cbuf), stdin); } - else cptr = read_line_p ("sim> ", cbuf, CBUFSIZE, stdin);/* read with prmopt*/ - if (cptr == NULL) /* EOF? */ + else cptr = read_line_p (sim_prompt, cbuf, sizeof(cbuf), stdin);/* read with prmopt*/ + if (cptr == NULL) { /* EOF? */ if (sim_ttisatty()) continue; /* ignore tty EOF */ else break; /* otherwise exit */ + } if (*cptr == 0) /* ignore blank */ continue; - sub_args (cbuf, gbuf, sizeof(gbuf), argv); + sub_args (cbuf, sizeof(cbuf), argv); if (sim_log) /* log cmd */ - fprintf (sim_log, "sim> %s\n", cptr); + fprintf (sim_log, "%s%s\n", sim_prompt, cptr); cptr = get_glyph (cptr, gbuf, 0); /* get command glyph */ sim_switches = 0; /* init switches */ if ((cmdp = find_cmd (gbuf))) /* lookup command */ @@ -909,14 +924,15 @@ while (stat != SCPE_EXIT) { /* in case exit */ stat_nomessage = stat_nomessage || (!sim_show_message);/* Apply global suppression */ stat = SCPE_BARE_STATUS(stat); /* remove possible flag */ sim_last_cmd_stat = stat; /* save command error status */ - if ((stat >= SCPE_BASE) && (!stat_nomessage)) { /* error? */ - if (cmdp && cmdp->message) /* special message handler? */ - cmdp->message (NULL, stat); - else { - printf ("%s\n", sim_error_text (stat)); - if (sim_log) - fprintf (sim_log, "%s\n", sim_error_text (stat)); - } + if (!stat_nomessage) { /* displaying message status? */ + if (cmdp && (cmdp->message)) /* special message handler? */ + cmdp->message (NULL, stat); /* let it deal with display */ + else + if (stat >= SCPE_BASE) { /* error? */ + printf ("%s\n", sim_error_text (stat)); + if (sim_log) + fprintf (sim_log, "%s\n", sim_error_text (stat)); + } } if (sim_vm_post != NULL) (*sim_vm_post) (TRUE); @@ -928,9 +944,32 @@ sim_set_logoff (0, NULL); /* close log */ sim_set_notelnet (0, NULL); /* close Telnet */ sim_ttclose (); /* close console */ AIO_CLEANUP; /* Asynch I/O */ +sim_cleanup_sock (); /* cleanup sockets */ return 0; } +/* Set prompt routine */ + +t_stat set_prompt (int32 flag, char *cptr) +{ +char gbuf[CBUFSIZE]; + +if ((!cptr) || (*cptr == '\0')) + return SCPE_ARG; + +cptr = get_glyph_nc (cptr, gbuf, '"'); /* get quote delimted token */ +if (gbuf[0] == '\0') { /* Token started with quote */ + gbuf[sizeof (gbuf)-1] = '\0'; + strncpy (gbuf, cptr, sizeof (gbuf)-1); + cptr = strchr (gbuf, '"'); + if (cptr) + *cptr = '\0'; + } +sim_prompt = realloc (sim_prompt, strlen (gbuf) + 2); /* nul terminator and trailing blank */ +sprintf (sim_prompt, "%s ", gbuf); +return SCPE_OK; +} + /* Find command routine */ CTAB *find_cmd (char *gbuf) @@ -956,6 +995,8 @@ return SCPE_EXIT; void fprint_help (FILE *st) { CTAB *cmdp; +DEVICE *dptr; +int i; for (cmdp = sim_vm_cmd; cmdp && (cmdp->name != NULL); cmdp++) { if (cmdp->help) @@ -965,9 +1006,71 @@ for (cmdp = cmd_table; cmdp && (cmdp->name != NULL); cmdp++) { if (cmdp->help && (!sim_vm_cmd || !find_ctab (sim_vm_cmd, cmdp->name))) fputs (cmdp->help, st); } +for (i = 0; (dptr = sim_devices[i]) != NULL; i++) { + if (dptr->help) + fprintf (st, "h{elp} %-17s type help for device %s\n", dptr->name, dptr->name); + if (dptr->attach_help || + (DEV_TYPE(dptr) == DEV_MUX) || + (DEV_TYPE(dptr) == DEV_ETHER) || + (DEV_TYPE(dptr) == DEV_DISK) || + (DEV_TYPE(dptr) == DEV_TAPE)) { + if (dptr->numunits == 1) + fprintf (st, "h{elp} %s ATTACH\t type help for device %s ATTACH command\n", dptr->name, dptr->name); + else { + fprintf (st, "h{elp} %s ATTACH\t type help for device %s ATTACH command\n", dptr->name, dptr->name); + fprintf (st, "h{elp} %sn ATTACH\t type help for unit %sn ATTACH command\n", dptr->name, dptr->name); + } + } + if (dptr->registers) { + REG *rptr; + + for (rptr = dptr->registers; rptr->name != NULL; rptr++) { + if (rptr->desc) { + fprintf (st, "h{elp} %s REGISTERS\t type help for device %s register variables\n", dptr->name, dptr->name); + break; + } + } + } + } return; } +void fprint_reg_help (FILE *st, DEVICE *dptr) +{ +REG *rptr, *trptr; +t_bool found = FALSE; +t_bool all_unique = TRUE; +DEVICE *tdptr; +char *tptr; + +for (rptr = dptr->registers; rptr->name != NULL; rptr++) { + if (rptr->desc) { + found = TRUE; + trptr = find_reg_glob (rptr->name, &tptr, &tdptr); + if ((trptr == NULL) || (tdptr != dptr)) + all_unique = FALSE; + } + } +if (!found) + fprintf (st, "No register help is available for the %s device\n", dptr->name); +else { + fprintf (st, "%s device registers:\n", dptr->name); + for (rptr = dptr->registers; rptr->name != NULL; rptr++) { + if (rptr->desc) { + if (all_unique) { + fprintf (st, " %-9s %s\n", rptr->name, rptr->desc); + continue; + } + trptr = find_reg_glob (rptr->name, &tptr, &tdptr); + if ((trptr == NULL) || (tdptr != dptr)) + fprintf (st, " %s %-9s %s\n", dptr->name, rptr->name, rptr->desc); + else + fprintf (st, " %*s %-9s %s\n", (int)strlen(dptr->name), "", rptr->name, rptr->desc); + } + } + } +} + t_stat help_cmd (int32 flag, char *cptr) { char gbuf[CBUFSIZE]; @@ -976,14 +1079,157 @@ CTAB *cmdp; GET_SWITCHES (cptr); if (*cptr) { cptr = get_glyph (cptr, gbuf, 0); - if (*cptr) - return SCPE_2MARG; if ((cmdp = find_cmd (gbuf))) { - fputs (cmdp->help, stdout); - if (sim_log) - fputs (cmdp->help, sim_log); + if (*cptr) + return SCPE_2MARG; + if (cmdp->help) { + fputs (cmdp->help, stdout); + if (sim_log) + fputs (cmdp->help, sim_log); + if (strcmp (cmdp->name, "HELP") == 0) { + DEVICE *dptr; + int i; + + for (i = 0; (dptr = sim_devices[i]) != NULL; i++) { + if (dptr->help) { + fprintf (stdout, "h{elp} %-17s type help for device %s\n", dptr->name, dptr->name); + if (sim_log) + fprintf (sim_log, "h{elp} %-17s type help for device %s\n", dptr->name, dptr->name); + } + if (dptr->attach_help || + (DEV_TYPE(dptr) == DEV_MUX) || + (DEV_TYPE(dptr) == DEV_DISK) || + (DEV_TYPE(dptr) == DEV_TAPE)) { + fprintf (stdout, "h{elp} %s ATTACH\t type help for device %s ATTACH command\n", dptr->name, dptr->name); + if (sim_log) + fprintf (sim_log, "h{elp} %s ATTACH\t type help for device %s ATTACH command\n", dptr->name, dptr->name); + } + if (dptr->registers) { + REG *rptr; + + for (rptr = dptr->registers; rptr->name != NULL; rptr++) { + if (rptr->desc) { + fprintf (stdout, "h{elp} %s REGISTERS\t type help for device %s register variables\n", dptr->name, dptr->name); + if (sim_log) + fprintf (sim_log, "h{elp} %s REGISTERS\t type help for device %s register variables\n", dptr->name, dptr->name); + break; + } + } + } + } + } + } + else { /* no help so it is likely a command alias */ + CTAB *cmdpa; + + for (cmdpa=cmd_table; cmdpa->name != NULL; cmdpa++) + if ((cmdpa->action == cmdp->action) && (cmdpa->help)) { + fprintf (stdout, "%s is an alias for the %s command:\n%s", + cmdp->name, cmdpa->name, cmdpa->help); + if (sim_log) + fprintf (sim_log, "%s is an alias for the %s command.\n%s", + cmdp->name, cmdpa->name, cmdpa->help); + break; + } + if (cmdpa->name == NULL) { /* not found? */ + fprintf (stdout, "No help available for the %s command\n", cmdp->name); + if (sim_log) + fprintf (sim_log, "No help available for the %s command\n", cmdp->name); + } + } + } + else { + DEVICE *dptr; + UNIT *uptr; + int i, dev_type; + static struct dev_help { + int type; + t_stat (*attach_help)(FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr); + } helps[] = { + {DEV_DISK, &sim_disk_attach_help}, + {DEV_TAPE, &sim_tape_attach_help}, + {DEV_MUX, &tmxr_attach_help}, + {DEV_ETHER, ð_attach_help}, + {0, NULL}}; + + dptr = find_unit (gbuf, &uptr); + if (dptr == NULL) { + dptr = find_dev (gbuf); + if (dptr == NULL) + return SCPE_ARG; + if (dptr->flags & DEV_DISABLE) { + fprintf (stdout, "Device %s is currently disabled\n", dptr->name); + if (sim_log) + fprintf (sim_log, "Device %s is currently disabled\n", dptr->name); + } + } + dev_type = DEV_TYPE (dptr); + for (i=0; helps[i].type; i++) + if (helps[i].type == dev_type) + break; + if (*cptr) { + cptr = get_glyph (cptr, gbuf, 0); + cmdp = find_cmd (gbuf); + } + else + cmdp = NULL; + if (0 == MATCH_CMD (gbuf, "REGISTERS")) { + fprint_reg_help (stdout, dptr); + if (sim_log) + fprint_reg_help (sim_log, dptr); + } + else { + if ((dptr->help == NULL) && (cmdp == NULL)) { + fprintf (stdout, "No help available for the %s device\n", dptr->name); + if (sim_log) + fprintf (sim_log, "No help available for the %s device\n", dptr->name); + if (dptr->attach_help || + (DEV_TYPE(dptr) == DEV_MUX) || + (DEV_TYPE(dptr) == DEV_ETHER) || + (DEV_TYPE(dptr) == DEV_DISK) || + (DEV_TYPE(dptr) == DEV_TAPE)) { + fprintf (stdout, "Some help is available if you type HELP %s ATTACH\n", dptr->name); + if (sim_log) + fprintf (sim_log, "Some help is available if you type HELP %s ATTACH\n", dptr->name); + } + } + else { + if (cmdp != NULL) { + if (cmdp->action != &attach_cmd) { + fprintf (stdout, "No help available for the %s device %s command\n", dptr->name, cmdp->name); + if (sim_log) + fprintf (sim_log, "No help available for the %s device %s command\n", dptr->name, cmdp->name); + if (dptr->attach_help || + (DEV_TYPE(dptr) == DEV_MUX) || + (DEV_TYPE(dptr) == DEV_ETHER) || + (DEV_TYPE(dptr) == DEV_DISK) || + (DEV_TYPE(dptr) == DEV_TAPE)) { + fprintf (stdout, "Some help is available if you type HELP %s ATTACH\n", dptr->name); + if (sim_log) + fprintf (sim_log, "Some help is available if you type HELP %s ATTACH\n", dptr->name); + } + } + else { + if (dptr->attach_help) { + dptr->attach_help (stdout, dptr, uptr, 0, cptr); + if (sim_log) + dptr->attach_help (sim_log, dptr, uptr, 0, cptr); + } + else { + helps[i].attach_help (stdout, dptr, uptr, 0, cptr); + if (sim_log) + helps[i].attach_help (sim_log, dptr, uptr, 0, cptr); + } + } + } + else { + dptr->help (stdout, dptr, uptr, 0, cptr); + if (sim_log) + dptr->help (sim_log, dptr, uptr, 0, cptr); + } + } + } } - else return SCPE_ARG; } else { fprint_help (stdout); @@ -1068,7 +1314,7 @@ return cbuf; t_stat do_cmd_label (int32 flag, char *fcptr, char *label) { -char *cptr, cbuf[CBUFSIZE], gbuf[CBUFSIZE], *c, quote, *do_arg[10]; +char *cptr, cbuf[4*CBUFSIZE], gbuf[CBUFSIZE], *c, quote, *do_arg[10]; FILE *fpin; CTAB *cmdp = NULL; int32 echo, nargs, errabort, i; @@ -1159,12 +1405,12 @@ if (errabort) /* -e flag? */ set_on (1, NULL); /* equivalent to ON ERROR RETURN */ do { - ocptr = cptr = sim_brk_getact (cbuf, CBUFSIZE); /* get bkpt action */ + ocptr = cptr = sim_brk_getact (cbuf, sizeof(cbuf)); /* get bkpt action */ if (!ocptr) { /* no pending action? */ - ocptr = cptr = read_line (cbuf, CBUFSIZE, fpin); /* get cmd line */ + ocptr = cptr = read_line (cbuf, sizeof(cbuf), fpin);/* get cmd line */ sim_goto_line[sim_do_depth] += 1; } - sub_args (cbuf, gbuf, sizeof(gbuf), do_arg); /* substitute args */ + sub_args (cbuf, sizeof(cbuf), do_arg); /* substitute args */ if (cptr == NULL) { /* EOF? */ stat = SCPE_OK; /* set good return */ break; @@ -1231,24 +1477,26 @@ do { fprintf (sim_log, "%s> %s\n", do_position(), ocptr); } } - if ((stat >= SCPE_BASE) && !stat_nomessage) { /* report error if not suppressed */ - if (cmdp && cmdp->message) { /* special message handler */ + if (!stat_nomessage) { /* report error if not suppressed */ + if (cmdp && cmdp->message) /* special message handler */ cmdp->message ((!echo && !sim_quiet) ? ocptr : NULL, stat); - } - else { - printf ("%s\n", sim_error_text (stat)); - if (sim_log) - fprintf (sim_log, "%s\n", sim_error_text (stat)); - } + else + if (stat >= SCPE_BASE) { /* report error if not suppressed */ + + printf ("%s\n", sim_error_text (stat)); + if (sim_log) + fprintf (sim_log, "%s\n", sim_error_text (stat)); + } } if (staying && (sim_on_check[sim_do_depth]) && (stat != SCPE_OK) && - (stat != SCPE_STEP)) + (stat != SCPE_STEP)) { if ((stat <= SCPE_MAX_ERR) && sim_on_actions[sim_do_depth][stat]) sim_brk_act[sim_do_depth] = sim_on_actions[sim_do_depth][stat]; else sim_brk_act[sim_do_depth] = sim_on_actions[sim_do_depth][0]; + } if (sim_vm_post != NULL) (*sim_vm_post) (TRUE); } while (staying); @@ -1286,8 +1534,7 @@ return stat | SCPE_NOMESSAGE; /* suppress message sinc Calling sequence instr = input string - tmpbuf = temp buffer - maxstr = min (len (instr), len (tmpbuf)) + instr_size = sizeof input string buffer do_arg[10] = arguments Token "%0" expands to the command file name. @@ -1310,6 +1557,7 @@ return stat | SCPE_NOMESSAGE; /* suppress message sinc %SIM_VERIFY% The Verify/Verbose mode of the current Do command file %SIM_VERBOSE% The Verify/Verbose mode of the current Do command file %SIM_QUIET% The Quiet mode of the current Do command file + %SIM_MESSAGE% The message display status of the current Do command file Environment variable lookups are done first with the precise name between the % characters and if that fails, then the name between the % characters is upcased and a lookup of that valus is attempted. @@ -1321,13 +1569,16 @@ return stat | SCPE_NOMESSAGE; /* suppress message sinc untouched. */ -void sub_args (char *instr, char *tmpbuf, int32 maxstr, char *do_arg[]) +void sub_args (char *instr, size_t instr_size, char *do_arg[]) { char gbuf[CBUFSIZE]; -char *ip = instr, *op = tmpbuf, *ap, *oend = tmpbuf + maxstr - 2, *istart; +char *ip = instr, *op, *ap, *oend, *istart, *tmpbuf; char rbuf[CBUFSIZE]; int i; +tmpbuf = malloc(instr_size); +op = tmpbuf; +oend = tmpbuf + instr_size - 2; while (isspace (*ip)) /* skip leading spaces */ *op++ = *ip++; istart = ip; @@ -1445,6 +1696,7 @@ for (; *ip && (op < oend); ) { } *op = 0; /* term buffer */ strcpy (instr, tmpbuf); +free (tmpbuf); return; } @@ -1452,7 +1704,7 @@ t_stat shift_args (char *do_arg[], size_t arg_count) { size_t i; -for (i=1; inumunits; i++) { /* check units */ up = (dptr->units) + i; /* att or active? */ - if ((up->flags & UNIT_ATT) || sim_is_active_bool (up)) + if ((up->flags & UNIT_ATT) || sim_is_active (up)) return SCPE_NOFNC; /* can't do it */ } dptr->flags = dptr->flags | DEV_DIS; /* disable */ @@ -1984,7 +2238,7 @@ if (flag) /* enb? enable */ uptr->flags = uptr->flags & ~UNIT_DIS; else { if ((uptr->flags & UNIT_ATT) || /* dsb */ - sim_is_active_bool (uptr)) /* more tests */ + sim_is_active (uptr)) /* more tests */ return SCPE_NOFNC; uptr->flags = uptr->flags | UNIT_DIS; /* disable */ } @@ -2065,6 +2319,7 @@ static SHTAB show_glob_tab[] = { { "NAMES", &show_log_names, 0 }, { "SHOW", &show_show_commands, 0 }, { "VERSION", &show_version, 1 }, + { "DEFAULT", &show_default, 0 }, { "CONSOLE", &sim_show_console, 0 }, { "BREAK", &show_break, 0 }, { "LOG", &sim_show_log, 0 }, /* deprecated */ @@ -2073,6 +2328,7 @@ static SHTAB show_glob_tab[] = { { "THROTTLE", &sim_show_throt, 0 }, { "ASYNCH", &sim_show_asynch, 0 }, { "ETHERNET", ð_show_devices, 0 }, + { "SERIAL", &sim_show_serial, 0 }, { "MULTIPLEXER", &tmxr_show_open_devices, 0 }, { "MUX", &tmxr_show_open_devices, 0 }, { "CLOCKS", &sim_show_timers, 0 }, @@ -2097,8 +2353,6 @@ GET_SWITCHES (cptr); /* get switches */ if (*cptr == 0) /* must be more */ return SCPE_2FARG; cptr = get_glyph (cptr, gbuf, 0); /* get next glyph */ -if ((shptr = find_shtab (show_glob_tab, gbuf))) /* global? */ - return shptr->action (ofile, NULL, NULL, shptr->arg, cptr); if ((dptr = find_dev (gbuf))) { /* device match? */ uptr = dptr->units; /* first unit */ @@ -2113,7 +2367,10 @@ else if ((dptr = find_unit (gbuf, &uptr))) { /* unit match? */ shtb = show_unit_tab; /* global table */ lvl = MTAB_VUN; /* unit match */ } -else return SCPE_NXDEV; /* no match */ +else if ((shptr = find_shtab (show_glob_tab, gbuf))) /* global? */ + return shptr->action (ofile, NULL, NULL, shptr->arg, cptr); +else + return SCPE_NXDEV; /* no match */ if (*cptr == 0) { /* now eol? */ return (lvl == MTAB_VDV)? @@ -2263,8 +2520,16 @@ if (cptr && (*cptr != 0)) fprintf (st, "%s simulator V%d.%d-%d", sim_name, vmaj, vmin, vpat); if (vdelt) fprintf (st, " delta %d", vdelt); +#if defined(SIM_VERSION_MODE) +fprintf (st, " %s", SIM_VERSION_MODE); +#endif if (flag) fprintf (st, " [%s, %s, %s]", sim_si64, sim_sa64, sim_snet); +#if defined(SIM_GIT_COMMIT_ID) +#define _xstr(a) _str(a) +#define _str(a) #a +fprintf (st, " git commit id: %8.8s", _xstr(SIM_GIT_COMMIT_ID)); +#endif fprintf (st, "\n"); return SCPE_OK; } @@ -2366,7 +2631,7 @@ pthread_mutex_unlock (&sim_timer_lock); pthread_mutex_lock (&sim_asynch_lock); fprintf (st, "asynchronous pending event queue\n"); if (sim_asynch_queue == QUEUE_LIST_END) - fprintf (st, "Empty\n"); + fprintf (st, " Empty\n"); else { for (uptr = sim_asynch_queue; uptr != QUEUE_LIST_END; uptr = uptr->a_next) { if ((dptr = find_dev_from_unit (uptr)) != NULL) { @@ -2381,7 +2646,7 @@ else { fprintf (st, "asynch latency: %d nanoseconds\n", sim_asynch_latency); fprintf (st, "asynch instruction latency: %d instructions\n", sim_asynch_inst_latency); pthread_mutex_unlock (&sim_asynch_lock); -#endif +#endif /* SIM_ASYNCH_IO */ return SCPE_OK; } @@ -2564,7 +2829,7 @@ DEVICE *dptr; if (cptr && (*cptr != 0)) /* now eol? */ return SCPE_2MARG; -for (i = 0; (dptr = sim_devices[i]) != NULL; ++i) +for (i = 0; (dptr = sim_devices[i]) != NULL; i++) show_dev_show_commands (st, dptr, NULL, flag, cptr); for (i = 0; sim_internal_device_count && (dptr = sim_internal_devices[i]); ++i) show_dev_show_commands (st, dptr, NULL, flag, cptr); @@ -2614,6 +2879,33 @@ if (dptr->modifiers) { return SCPE_OK; } +/* Show/change the current working directiory commands */ + +t_stat show_default (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr) +{ +char buffer[PATH_MAX]; +char *wd = getcwd(buffer, PATH_MAX); +fprintf (st, "%s\n", wd); +return SCPE_OK; +} + +t_stat set_default_cmd (int32 flg, char *cptr) +{ +if ((!cptr) || (*cptr == 0)) + return SCPE_2FARG; +sim_trim_endspc(cptr); +if (chdir(cptr) != 0) { + printf("Unable to change to: %s\n", cptr); + return SCPE_IOERR & SCPE_NOMESSAGE; +} +return SCPE_OK; +} + +t_stat pwd_cmd (int32 flg, char *cptr) +{ +return show_cmd (0, "DEFAULT"); +} + /* Breakpoint commands */ t_stat brk_cmd (int32 flg, char *cptr) @@ -2750,6 +3042,13 @@ for (i = start; (dptr = sim_devices[i]) != NULL; i++) { return reason; } } +for (i = 0; sim_internal_device_count && (dptr = sim_internal_devices[i]); ++i) { + if (dptr->reset != NULL) { + reason = dptr->reset (dptr); + if (reason != SCPE_OK) + return reason; + } + } return SCPE_OK; } @@ -2821,7 +3120,8 @@ if (dptr == NULL) /* found dev? */ return SCPE_NXDEV; if (uptr == NULL) /* valid unit? */ return SCPE_NXUN; -if (uptr->flags & UNIT_ATT) { /* already attached? */ +if ((uptr->flags & UNIT_ATT) && /* already attached? */ + !(uptr->dynflags & UNIT_ATTMULT)) { /* and only single attachable */ r = scp_detach_unit (dptr, uptr); /* detach it */ if (r != SCPE_OK) /* error? */ return r; @@ -2851,8 +3151,6 @@ if (!(uptr->flags & UNIT_ATTABLE)) /* not attachable? */ return SCPE_NOATT; if ((dptr = find_dev_from_unit (uptr)) == NULL) return SCPE_NOATT; -if (dptr->flags & DEV_RAWONLY) /* raw mode only? */ - return SCPE_NOFNC; uptr->filename = (char *) calloc (CBUFSIZE, sizeof (char)); /* alloc name buf */ if (uptr->filename == NULL) return SCPE_MEM; @@ -2979,6 +3277,7 @@ for (i = start; (dptr = sim_devices[i]) != NULL; i++) { /* loop thru dev */ return SCPE_OK; } + /* Call device-specific or file-oriented detach unit routine */ t_stat scp_detach_unit (DEVICE *dptr, UNIT *uptr) @@ -2998,11 +3297,12 @@ if (uptr == NULL) return SCPE_IERR; if (!(uptr->flags & UNIT_ATTABLE)) /* attachable? */ return SCPE_NOATT; -if (!(uptr->flags & UNIT_ATT)) /* not attached? */ +if (!(uptr->flags & UNIT_ATT)) { /* not attached? */ if (sim_switches & SIM_SW_REST) /* restoring? */ return SCPE_OK; /* allow detach */ else - return SCPE_NOATT; /* complain */ + return SCPE_NOATT; /* complain */ + } if ((dptr = find_dev_from_unit (uptr)) == NULL) return SCPE_OK; if (uptr->flags & UNIT_BUF) { @@ -3169,7 +3469,7 @@ for (i = 0; (dptr = sim_devices[i]) != NULL; i++) { /* loop thru devices */ WRITE_I (dptr->flags); /* [V2.10] flags */ for (j = 0; j < dptr->numunits; j++) { uptr = dptr->units + j; - t = sim_is_active (uptr); + t = sim_activate_time (uptr); WRITE_I (j); /* unit number */ WRITE_I (t); /* activation time */ WRITE_I (uptr->u3); /* unit specific */ @@ -3177,6 +3477,7 @@ for (i = 0; (dptr = sim_devices[i]) != NULL; i++) { /* loop thru devices */ WRITE_I (uptr->u5); /* [V3.0] more unit */ WRITE_I (uptr->u6); WRITE_I (uptr->flags); /* [V2.10] flags */ + WRITE_I (uptr->dynflags); WRITE_I (uptr->capac); /* [V3.5] capacity */ if (uptr->flags & UNIT_ATT) { fputs (uptr->filename, sfile); @@ -3288,7 +3589,7 @@ REG *rptr; struct stat rstat; t_bool force_restore = sim_switches & SWMASK ('F'); -#define READ_S(xx) if (read_line ((xx), CBUFSIZE, rfile) == NULL) \ +#define READ_S(xx) if (read_line ((xx), sizeof(xx), rfile) == NULL) \ return SCPE_IOERR; #define READ_I(xx) if (sim_fread (&xx, sizeof (xx), 1, rfile) == 0) \ return SCPE_IOERR; @@ -3336,7 +3637,7 @@ if (v32) { /* [V3.2+] time as strin } else READ_I (sim_time); /* sim time */ READ_I (sim_rtime); /* [V2.6+] sim rel time */ - +detach_all (0, 0); /* Detach everything to start from a consistent state */ for ( ;; ) { /* device loop */ READ_S (buf); /* read device name */ if (buf[0] == 0) /* last? */ @@ -3379,6 +3680,7 @@ for ( ;; ) { /* device loop */ READ_I (uptr->u5); /* [V3.0+] more dev spec */ READ_I (uptr->u6); READ_I (flg); /* [V2.10+] unit flags */ + READ_I (uptr->dynflags); old_capac = uptr->capac; /* save current capacity */ if (v35) { /* [V3.5+] capacity */ READ_I (uptr->capac); @@ -3389,14 +3691,12 @@ for ( ;; ) { /* device loop */ uptr->flags = (uptr->flags & ~UNIT_RFLAGS) | (flg & UNIT_RFLAGS); /* restore */ READ_S (buf); /* attached file */ - if ((uptr->flags & UNIT_ATT) && /* unit currently attached? */ - !(dptr->flags & DEV_NET)) { /* and not a net device? */ + if (uptr->flags & UNIT_ATT) { /* unit currently attached? */ r = scp_detach_unit (dptr, uptr); /* detach it */ if (r != SCPE_OK) return r; } if ((buf[0] != '\0') && /* unit to be reattached? */ - !(dptr->flags & DEV_NET) && /* and not a net device? */ ((uptr->flags & UNIT_ATTABLE) || /* and unit is attachable */ (dptr->attach != NULL))) { /* or VM attach routine provided? */ uptr->flags = uptr->flags & ~UNIT_DIS; /* ensure device is enabled */ @@ -3447,7 +3747,7 @@ for ( ;; ) { /* device loop */ if ((mbuf = calloc (SRBSIZ, sz)) == NULL) return SCPE_MEM; for (k = 0; k < high; ) { /* loop thru mem */ - if (sim_fread (&blkcnt, sizeof (blkcnt), 1, rfile) == 0) { + if (sim_fread (&blkcnt, sizeof (blkcnt), 1, rfile) == 0) {/* block count */ free (mbuf); return SCPE_IOERR; } @@ -3685,19 +3985,20 @@ for (i = 1; (dptr = sim_devices[i]) != NULL; i++) { /* flush attached files uptr = dptr->units + j; if ((uptr->flags & UNIT_ATT) && /* attached, */ !(uptr->flags & UNIT_BUF) && /* not buffered, */ - (uptr->fileref)) /* real file, */ + (uptr->fileref)) { /* real file, */ if (uptr->io_flush) /* unit specific flush routine */ uptr->io_flush (uptr); else - if (!(uptr->flags & UNIT_RAW) && /* not raw, */ + if (!(uptr->dynflags & UNIT_NO_FIO) && /* is FILE *, */ !(uptr->flags & UNIT_RO)) /* not read only? */ fflush (uptr->fileref); + } } } sim_cancel (&sim_step_unit); /* cancel step timer */ sim_throt_cancel (); /* cancel throttle */ -UPDATE_SIM_TIME; /* update sim time */ AIO_UPDATE_QUEUE; +UPDATE_SIM_TIME; /* update sim time */ return r; } @@ -3723,13 +4024,14 @@ if (sim_log) /* log if enabled */ t_stat run_boot_prep (void) { +UNIT *uptr; + sim_interval = 0; /* reset queue */ sim_time = sim_rtime = 0; noqueue_time = 0; -while (sim_clock_queue != QUEUE_LIST_END) { - UNIT *cptr = sim_clock_queue; - sim_clock_queue = cptr->next; - cptr->next = NULL; /* hygiene */ +for (uptr = sim_clock_queue; uptr != QUEUE_LIST_END; uptr = sim_clock_queue) { + sim_clock_queue = uptr->next; + uptr->next = NULL; } return reset_all (0); } @@ -4089,7 +4391,7 @@ if ((cptr == NULL) || (rptr == NULL)) if (rptr->flags & REG_RO) return SCPE_RO; if (flag & EX_I) { - cptr = read_line (gbuf, CBUFSIZE, stdin); + cptr = read_line (gbuf, sizeof(gbuf), stdin); if (sim_log) fprintf (sim_log, "%s\n", cptr? cptr: ""); if (cptr == NULL) /* force exit */ @@ -4247,7 +4549,7 @@ for (i = 0, j = addr; i < sim_emax; i++, j = j + dptr->aincr) { else { if (!(uptr->flags & UNIT_ATT)) return SCPE_UNATT; - if (uptr->flags & UNIT_RAW) + if (uptr->dynflags & UNIT_NO_FIO) return SCPE_NOFNC; if ((uptr->flags & UNIT_FIX) && (j >= uptr->capac)) { reason = SCPE_NXM; @@ -4307,7 +4609,7 @@ char gbuf[CBUFSIZE]; if (dptr == NULL) return SCPE_IERR; if (flag & EX_I) { - cptr = read_line (gbuf, CBUFSIZE, stdin); + cptr = read_line (gbuf, sizeof(gbuf), stdin); if (sim_log) fprintf (sim_log, "%s\n", cptr? cptr: ""); if (cptr == NULL) /* force exit */ @@ -4338,7 +4640,7 @@ for (i = 0, j = addr; i < count; i++, j = j + dptr->aincr) { else { if (!(uptr->flags & UNIT_ATT)) return SCPE_UNATT; - if (uptr->flags & UNIT_RAW) + if (uptr->dynflags & UNIT_NO_FIO) return SCPE_NOFNC; if ((uptr->flags & UNIT_FIX) && (j >= uptr->capac)) return SCPE_NXM; @@ -4436,8 +4738,10 @@ char *read_line_p (char *prompt, char *cptr, int32 size, FILE *stream) char *tptr; #if defined(HAVE_DLOPEN) static int initialized = 0; -static char *(*p_readline)(const char *) = NULL; -static void (*p_add_history)(const char *) = NULL; +typedef char *(*readline_func)(const char *); +static readline_func p_readline = NULL; +typedef void (*add_history_func)(const char *); +static add_history_func p_add_history = NULL; if (!initialized) { initialized = 1; @@ -4453,8 +4757,8 @@ if (!initialized) { if (!handle) handle = dlopen("libreadline." __STR(HAVE_DLOPEN) ".5", RTLD_NOW|RTLD_GLOBAL); if (handle) { - p_readline = dlsym(handle, "readline"); - p_add_history = dlsym(handle, "add_history"); + p_readline = (readline_func)((size_t)dlsym(handle, "readline")); + p_add_history = (add_history_func)((size_t)dlsym(handle, "add_history")); } } if (prompt) { /* interactive? */ @@ -4579,7 +4883,7 @@ t_stat get_yn (char *ques, t_stat deflt) char cbuf[CBUFSIZE], *cptr; printf ("%s ", ques); -cptr = read_line (cbuf, CBUFSIZE, stdin); +cptr = read_line (cbuf, sizeof(cbuf), stdin); if ((cptr == NULL) || (*cptr == 0)) return deflt; if ((*cptr == 'Y') || (*cptr == 'y')) @@ -4670,69 +4974,6 @@ if (term && (*tptr++ != term)) return tptr; } -/* get_ipaddr IP address:port - - Inputs: - cptr = pointer to input string - Outputs: - ipa = pointer to IP address (may be NULL), 0 = none - ipp = pointer to IP port (may be NULL), 0 = none - result = status -*/ - -t_stat get_ipaddr (char *cptr, uint32 *ipa, uint32 *ipp) -{ -char gbuf[CBUFSIZE]; -char *addrp, *portp, *octetp; -uint32 i, addr, port, octet; -t_stat r; - -if ((cptr == NULL) || (*cptr == 0)) - return SCPE_ARG; -strncpy (gbuf, cptr, CBUFSIZE); -addrp = gbuf; /* default addr */ -if ((portp = strchr (gbuf, ':'))) /* x:y? split */ - *portp++ = 0; -else if (strchr (gbuf, '.')) /* x.y...? */ - portp = NULL; -else { - portp = gbuf; /* port only */ - addrp = NULL; /* no addr */ - } -if (portp) { /* port string? */ - if (ipp == NULL) /* not wanted? */ - return SCPE_ARG; - port = (int32) get_uint (portp, 10, 65535, &r); - if ((r != SCPE_OK) || (port == 0)) - return SCPE_ARG; - } -else port = 0; -if (addrp) { /* addr string? */ - if (ipa == NULL) /* not wanted? */ - return SCPE_ARG; - for (i = addr = 0; i < 4; i++) { /* four octets */ - octetp = strchr (addrp, '.'); /* find octet end */ - if (octetp != NULL) /* split string */ - *octetp++ = 0; - else if (i < 3) /* except last */ - return SCPE_ARG; - octet = (int32) get_uint (addrp, 10, 255, &r); - if (r != SCPE_OK) - return SCPE_ARG; - addr = (addr << 8) | octet; - addrp = octetp; - } - if (((addr & 0377) == 0) || ((addr & 0377) == 255)) - return SCPE_ARG; - } -else addr = 0; -if (ipp) /* return req values */ - *ipp = port; -if (ipa) - *ipa = addr; -return SCPE_OK; -} - /* Find_device find device matching input string Inputs: @@ -4746,7 +4987,7 @@ DEVICE *find_dev (char *cptr) int32 i; DEVICE *dptr; -for (i = 0; (dptr = sim_devices[i]) != NULL; ++i) { +for (i = 0; (dptr = sim_devices[i]) != NULL; i++) { if ((strcmp (cptr, dptr->name) == 0) || (dptr->lname && (strcmp (cptr, dptr->lname) == 0))) @@ -4769,6 +5010,7 @@ return NULL; Outputs: result = pointer to device (null if no dev) *iptr = pointer to unit (null if nx unit) + */ DEVICE *find_unit (char *cptr, UNIT **uptr) @@ -4818,10 +5060,10 @@ t_stat sim_register_internal_device (DEVICE *dptr) { uint32 i; -for (i = 0; (sim_devices[i] != NULL); ++i) +for (i = 0; (sim_devices[i] != NULL); i++) if (sim_devices[i] == dptr) return SCPE_OK; -for (i = 0; i < sim_internal_device_count; ++i) +for (i = 0; i < sim_internal_device_count; i++) if (sim_internal_devices[i] == dptr) return SCPE_OK; ++sim_internal_device_count; @@ -4846,13 +5088,13 @@ uint32 i, j; if (uptr == NULL) return NULL; -for (i = 0; (dptr = sim_devices[i]) != NULL; ++i) { +for (i = 0; (dptr = sim_devices[i]) != NULL; i++) { for (j = 0; j < dptr->numunits; j++) { if (uptr == (dptr->units + j)) return dptr; } } -for (i = 0; inumunits; j++) { if (uptr == (dptr->units + j)) @@ -5206,13 +5448,13 @@ return 0; On an error, the endptr will equal the inptr. */ -t_value strtotv (char *inptr, char **endptr, uint32 radix) +t_value strtotv (const char *inptr, char **endptr, uint32 radix) { int32 nodigit; t_value val; uint32 c, digit; -*endptr = inptr; /* assume fails */ +*endptr = (char *)inptr; /* assume fails */ if ((radix < 2) || (radix > 36)) return 0; while (isspace (*inptr)) /* bypass white space */ @@ -5234,7 +5476,7 @@ for (c = *inptr; isalnum(c); c = *++inptr) { /* loop through char */ } if (nodigit) /* no digits? */ return 0; -*endptr = inptr; /* result pointer */ +*endptr = (char *)inptr; /* result pointer */ return val; } @@ -5294,8 +5536,8 @@ return SCPE_OK; sim_activate_after add entry to event queue after a specified amount of wall time sim_cancel remove entry from event queue sim_process_event process entries on event queue - sim_is_active see if entry is on event queue return time + 1 - sim_is_active_bool see if entry is on event queue + sim_is_active see if entry is on event queue + sim_activate_time return time until activation sim_atime return absolute time for an entry sim_gtime return global time sim_qcount return event queue entry count @@ -5327,7 +5569,9 @@ t_stat reason; if (stop_cpu) /* stop CPU? */ return SCPE_STOP; +AIO_UPDATE_QUEUE; UPDATE_SIM_TIME; /* update sim time */ + if (sim_clock_queue == QUEUE_LIST_END) { /* queue empty? */ sim_interval = noqueue_time = NOQUEUE_WAIT; /* flag queue empty */ sim_debug (SIM_DBG_EVENT, sim_dflt_dev, "Queue Emptry New Interval = %d\n", sim_interval); @@ -5359,6 +5603,7 @@ if (sim_clock_queue == QUEUE_LIST_END) { /* queue empty? */ } else sim_debug (SIM_DBG_EVENT, sim_dflt_dev, "Processing Queue Complete New Interval = %d(%s)\n", sim_interval, sim_uname(sim_clock_queue)); + return reason; } @@ -5382,7 +5627,7 @@ UNIT *cptr, *prvptr; int32 accum; AIO_ACTIVATE (_sim_activate, uptr, event_time); -if (sim_is_active_bool (uptr)) /* already active? */ +if (sim_is_active (uptr)) /* already active? */ return SCPE_OK; UPDATE_SIM_TIME; /* update sim time */ @@ -5448,10 +5693,9 @@ sim_cancel (uptr); if (0x80000000 <= urtime-rtimenow) return _sim_activate (uptr, 0); else - return _sim_activate (uptr, urtime-rtimenow); + return sim_activate (uptr, urtime-rtimenow); } - /* sim_activate_after - activate (queue) event Inputs: @@ -5468,7 +5712,7 @@ return _sim_activate_after (uptr, event_time); t_stat _sim_activate_after (UNIT *uptr, int32 usec_delay) { -if (sim_is_active_bool (uptr)) /* already active? */ +if (sim_is_active (uptr)) /* already active? */ return SCPE_OK; AIO_ACTIVATE (_sim_activate_after, uptr, usec_delay); return sim_timer_activate_after (uptr, usec_delay); @@ -5489,12 +5733,14 @@ UNIT *cptr, *nptr; AIO_VALIDATE; AIO_CANCEL(uptr); -if (!sim_is_active_bool (uptr)) /* not active? */ - return SCPE_OK; /* nothing to cancel */ +AIO_UPDATE_QUEUE; if (sim_clock_queue == QUEUE_LIST_END) return SCPE_OK; UPDATE_SIM_TIME; /* update sim time */ +if (!sim_is_active (uptr)) + return SCPE_OK; nptr = QUEUE_LIST_END; + if (sim_clock_queue == uptr) nptr = sim_clock_queue = uptr->next; else { @@ -5515,20 +5761,22 @@ else sim_interval = noqueue_time = NOQUEUE_WAIT; return SCPE_OK; } -/* sim_is_active_bool - test for entry in queue, return activation time +/* sim_is_active - test for entry in queue Inputs: uptr = pointer to unit Outputs: - result = TRUE if active FALSE if inactive + result = TRUE if unit is busy, FALSE inactive */ -t_bool sim_is_active_bool (UNIT *uptr) +t_bool sim_is_active (UNIT *uptr) { -return (uptr->next != NULL); +AIO_VALIDATE; +AIO_UPDATE_QUEUE; +return (((uptr->next) || AIO_IS_ACTIVE(uptr)) ? TRUE : FALSE); } -/* sim_is_active - test for entry in queue, return activation time +/* sim_activate_time - return activation time Inputs: uptr = pointer to unit @@ -5536,7 +5784,7 @@ return (uptr->next != NULL); result = absolute activation time + 1, 0 if inactive */ -int32 sim_is_active (UNIT *uptr) +int32 sim_activate_time (UNIT *uptr) { UNIT *cptr; int32 accum = 0; @@ -5555,33 +5803,6 @@ for (cptr = sim_clock_queue; cptr != QUEUE_LIST_END; cptr = cptr->next) { return 0; } -/* sim_activation_time - test for entry in queue, return activation time - - Inputs: - uptr = pointer to unit - Outputs: - result = absolute activation time + 1, 0 if inactive -*/ - -int32 sim_activation_time (UNIT *uptr) -{ -UNIT *cptr; -int32 accum; - -AIO_VALIDATE; -accum = 0; -for (cptr = sim_clock_queue; cptr != QUEUE_LIST_END; cptr = cptr->next) { - if (cptr == sim_clock_queue) { - if (sim_interval > 0) - accum = accum + sim_interval; - } - else accum = accum + cptr->time; - if (cptr == uptr) - return accum + 1; - } -return 0; -} - /* sim_gtime - return global time sim_grtime - return global time with rollover @@ -6006,19 +6227,49 @@ if (!debug_unterm) { } /* Prints state of a register: bit translation + state (0,1,_,^) - indicating the state and transition of the bit. States: + indicating the state and transition of the bit and bitfields. States: 0=steady(0->0), 1=steady(1->1), _=falling(1->0), ^=rising(0->1) */ -void sim_debug_u16(uint32 dbits, DEVICE* dptr, const char* const* bitdefs, - uint16 before, uint16 after, int terminate) +void sim_debug_bits(uint32 dbits, DEVICE* dptr, BITFIELD* bitdefs, + uint32 before, uint32 after, int terminate) { if (sim_deb && (dptr->dctrl & dbits)) { - int32 i; + int32 i, fields, offset; + uint32 value, beforevalue, mask; + for (fields=offset=0; bitdefs[fields].name; ++fields) { + if (bitdefs[fields].offset == 0xffffffff) /* fixup uninitialized offsets */ + bitdefs[fields].offset = offset; + offset += bitdefs[fields].width; + } sim_debug_prefix(dbits, dptr); /* print prefix if required */ - for (i = 15; i >= 0; i--) { /* print xlation, transition */ - int off = ((after >> i) & 1) + (((before ^ after) >> i) & 1) * 2; - fprintf(sim_deb, "%s%c ", bitdefs[i], debug_bstates[off]); + for (i = fields-1; i >= 0; i--) { /* print xlation, transition */ + if (bitdefs[i].name[0] == '\0') + continue; + if ((bitdefs[i].width == 1) && (bitdefs[i].valuenames == NULL)) { + int off = ((after >> bitdefs[i].offset) & 1) + (((before ^ after) >> bitdefs[i].offset) & 1) * 2; + fprintf(sim_deb, "%s%c ", bitdefs[i].name, debug_bstates[off]); + } + else { + char *delta = ""; + + mask = 0xFFFFFFFF >> (32-bitdefs[i].width); + value = ((after >> bitdefs[i].offset) & mask); + beforevalue = ((before >> bitdefs[i].offset) & mask); + if (value < beforevalue) + delta = "_"; + if (value > beforevalue) + delta = "^"; + if (bitdefs[i].valuenames) + fprintf(sim_deb, "%s=%s%s ", bitdefs[i].name, delta, bitdefs[i].valuenames[value]); + else + if (bitdefs[i].format) { + fprintf(sim_deb, "%s=%s", bitdefs[i].name, delta); + fprintf(sim_deb, bitdefs[i].format, value); + } + else + fprintf(sim_deb, "%s=%s0x%X ", bitdefs[i].name, delta, value); + } } if (terminate) fprintf(sim_deb, "\r\n"); diff --git a/scp.h b/scp.h index 7a690bec..6eee016e 100644 --- a/scp.h +++ b/scp.h @@ -1,6 +1,6 @@ /* scp.h: simulator control program headers - Copyright (c) 1993-2008, Robert M Supnik + Copyright (c) 1993-2009, Robert M Supnik Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), @@ -59,6 +59,7 @@ t_stat exdep_cmd (int32 flag, char *ptr); t_stat eval_cmd (int32 flag, char *ptr); t_stat load_cmd (int32 flag, char *ptr); t_stat run_cmd (int32 flag, char *ptr); +void run_cmd_message (const char *unechod_cmdline, t_stat r); t_stat attach_cmd (int32 flag, char *ptr); t_stat detach_cmd (int32 flag, char *ptr); t_stat assign_cmd (int32 flag, char *ptr); @@ -91,8 +92,8 @@ t_stat sim_activate_notbefore (UNIT *uptr, int32 rtime); t_stat sim_activate_after (UNIT *uptr, int32 usecs_walltime); t_stat _sim_activate_after (UNIT *uptr, int32 usecs_walltime); t_stat sim_cancel (UNIT *uptr); -t_bool sim_is_active_bool (UNIT *uptr); -int32 sim_is_active (UNIT *uptr); +t_bool sim_is_active (UNIT *uptr); +int32 sim_activate_time (UNIT *uptr); double sim_gtime (void); uint32 sim_grtime (void); int32 sim_qcount (void); @@ -111,8 +112,7 @@ char *get_glyph_nc (char *iptr, char *optr, char mchar); t_value get_uint (char *cptr, uint32 radix, t_value max, t_stat *status); char *get_range (DEVICE *dptr, char *cptr, t_addr *lo, t_addr *hi, uint32 rdx, t_addr max, char term); -t_stat get_ipaddr (char *cptr, uint32 *ipa, uint32 *ipp); -t_value strtotv (char *cptr, char **endptr, uint32 radix); +t_value strtotv (const char *cptr, char **endptr, uint32 radix); t_stat fprint_val (FILE *stream, t_value val, uint32 rdx, uint32 wid, uint32 fmt); CTAB *find_cmd (char *gbuf); DEVICE *find_dev (char *ptr); @@ -127,11 +127,13 @@ BRKTAB *sim_brk_fnd (t_addr loc); uint32 sim_brk_test (t_addr bloc, uint32 btyp); void sim_brk_clrspc (uint32 spc); char *match_ext (char *fnam, char *ext); +t_stat set_dev_debug (DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr); +t_stat show_dev_debug (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr); const char *sim_error_text (t_stat stat); t_stat sim_string_to_stat (char *cptr, t_stat *cond); t_stat sim_cancel_step (void); -void sim_debug_u16 (uint32 dbits, DEVICE* dptr, const char* const* bitdefs, - uint16 before, uint16 after, int terminate); +void sim_debug_bits (uint32 dbits, DEVICE* dptr, BITFIELD* bitdefs, + uint32 before, uint32 after, int terminate); #if defined (__DECC) && defined (__VMS) && (defined (__VAX) || (__DECC_VER < 60590001)) #define CANT_USE_MACRO_VA_ARGS 1 #endif @@ -140,9 +142,51 @@ void sim_debug_u16 (uint32 dbits, DEVICE* dptr, const char* const* bitdefs, void sim_debug (uint32 dbits, DEVICE* dptr, const char* fmt, ...); #else void _sim_debug (uint32 dbits, DEVICE* dptr, const char* fmt, ...); -extern FILE *sim_deb; /* debug file */ #define sim_debug(dbits, dptr, ...) if (sim_deb && ((dptr)->dctrl & dbits)) _sim_debug (dbits, dptr, __VA_ARGS__); else (void)0 #endif void fprint_stopped_gen (FILE *st, t_stat v, REG *pc, DEVICE *dptr); +/* Global data */ + +extern DEVICE *sim_dflt_dev; +extern int32 sim_interval; +extern int32 sim_switches; +extern int32 sim_quiet; +extern FILE *sim_log; /* log file */ +extern FILEREF *sim_log_ref; /* log file file reference */ +extern FILE *sim_deb; /* debug file */ +extern FILEREF *sim_deb_ref; /* debug file file reference */ +extern UNIT *sim_clock_queue; +extern int32 sim_is_running; +extern volatile int32 stop_cpu; +extern uint32 sim_brk_types; /* breakpoint info */ +extern uint32 sim_brk_dflt; +extern uint32 sim_brk_summ; +extern t_bool sim_asynch_enabled; + +/* VM interface */ + +extern char sim_name[]; +extern DEVICE *sim_devices[]; +extern REG *sim_PC; +extern const char *sim_stop_messages[]; +extern t_stat sim_instr (void); +extern t_stat sim_load (FILE *ptr, char *cptr, char *fnam, int flag); +extern int32 sim_emax; +extern t_stat fprint_sym (FILE *ofile, t_addr addr, t_value *val, + UNIT *uptr, int32 sw); +extern t_stat parse_sym (char *cptr, t_addr addr, UNIT *uptr, t_value *val, + int32 sw); + +/* The per-simulator init routine is a weak global that defaults to NULL + The other per-simulator pointers can be overrriden by the init routine */ + +extern void (*sim_vm_init) (void); +extern char* (*sim_vm_read) (char *ptr, int32 size, FILE *stream); +extern void (*sim_vm_post) (t_bool from_scp); +extern CTAB *sim_vm_cmd; +extern void (*sim_vm_fprint_addr) (FILE *st, DEVICE *dptr, t_addr addr); +extern t_addr (*sim_vm_parse_addr) (DEVICE *dptr, char *cptr, char **tptr); + + #endif diff --git a/sigma/sigma_cpu.c b/sigma/sigma_cpu.c index 22e1a44a..c985f5c3 100644 --- a/sigma/sigma_cpu.c +++ b/sigma/sigma_cpu.c @@ -183,10 +183,6 @@ int32 hst_p = 0; /* history pointer */ int32 hst_lnt = 0; /* history length */ InstHistory *hst = NULL; /* inst history */ -extern int32 sim_int_char; -extern int32 sim_interval; -extern int32 sim_switches; -extern uint32 sim_brk_types, sim_brk_dflt, sim_brk_summ; /* breakpoint info */ extern uint32 int_hiact; /* highest act int */ extern uint32 int_hireq; /* highest int req */ @@ -2792,8 +2788,6 @@ void cpu_fprint_one_inst (FILE *st, uint32 tcp, uint32 ir, uint32 rn, uint32 rn1 uint32 ea, uint32 opnd, uint32 opnd1) { t_value sim_val; -extern t_stat fprint_sym (FILE *ofile, t_addr addr, t_value *val, - UNIT *uptr, int32 sw); if (tcp & (H_INST|H_ITRP)) { /* instr or trap? */ uint32 op = I_GETOP (ir); diff --git a/sigma/sigma_io.c b/sigma/sigma_io.c index f1193069..5748945b 100644 --- a/sigma/sigma_io.c +++ b/sigma/sigma_io.c @@ -93,8 +93,6 @@ extern uint32 cpu_model; extern uint32 cons_alarm, cons_pcf; extern UNIT cpu_unit; extern cpu_var_t cpu_tab[]; -extern DEVICE *sim_devices[]; -extern FILE *sim_log; void io_eval_ioint (void); t_bool io_init_inst (uint32 ad, uint32 rn, uint32 ch, uint32 dev, uint32 r0); diff --git a/sigma/sigma_mt.c b/sigma/sigma_mt.c index 7e3e9f35..73ce4be2 100644 --- a/sigma/sigma_mt.c +++ b/sigma/sigma_mt.c @@ -207,7 +207,7 @@ DEVICE mt_dev = { MT_NUMDR * 2, 10, T_ADDR_W, 1, 16, 8, NULL, NULL, &mt_reset, &io_boot, &mt_attach, &mt_detach, - &mt_dib, DEV_DISABLE + &mt_dib, DEV_DISABLE | DEV_TAPE }; /* Magtape: IO dispatch routine */ @@ -278,7 +278,7 @@ t_mtrlnt tbc; t_stat r; if (cmd == MCM_INIT) { /* init state */ - if ((t = sim_is_active (uptr + MT_REW)) != 0) { /* rewinding? */ + if ((t = sim_activate_time (uptr + MT_REW)) != 0) { /* rewinding? */ sim_activate (uptr, t); /* retry later */ return SCPE_OK; } diff --git a/sim_BuildROMs.c b/sim_BuildROMs.c index cebf2dfb..5f706cef 100644 --- a/sim_BuildROMs.c +++ b/sim_BuildROMs.c @@ -23,26 +23,33 @@ used in advertising or otherwise to promote the sale, use or other dealings in this Software without prior written authorization from Robert M Supnik. - - +*/ +#include +#include +#include +/* This program builds C include files which can be used to contain the contents of ROM or other boot code needed by simulators. Current Internal ROM files being built: - ROM/Boot File: Include File: - ======================================= - VAX/ka655x.bin VAX/vax_ka655x_bin.h - VAX/vmb.exe VAX/vax780_vmb_exe.h - - + ROM/Boot File: Include File: Size: Checksum: + ======================================================================================= */ +struct ROM_File_Descriptor { + char *BinaryName; char *IncludeFileName; size_t expected_size; unsigned int checksum; char *ArrayName;} ROMs[] = { + {"VAX/ka655x.bin", "VAX/vax_ka655x_bin.h", 131072, 0xFF7673B6, "vax_ka655x_bin"}, + {"VAX/ka620.bin", "VAX/vax_ka620_bin.h", 65536, 0xFF7F930F, "vax_ka620_bin"}, + {"VAX/ka630.bin", "VAX/vax_ka630_bin.h", 65536, 0xFF7F73EF, "vax_ka630_bin"}, + {"VAX/ka610.bin", "VAX/vax_ka610_bin.h", 16384, 0xFFEF3312, "vax_ka610_bin"}, + {"VAX/vmb.exe", "VAX/vax_vmb_exe.h", 44544, 0xFFC014CC, "vax_vmb_exe"}, + }; -#include -#include -#include -#include + +#include #include +#include #include #if defined(_WIN32) @@ -53,6 +60,133 @@ #include #endif +int sim_read_ROM_include(const char *include_filename, + int *psize, + unsigned char **pROMData, + unsigned int *pchecksum, + char **prom_array_name, + int *defines_found) +{ +FILE *iFile; +char line[256]; +size_t i; +size_t bytes_written = 0; +size_t allocated_size = 0; +int define_size_found = 0; +int define_filename_found = 0; +int define_array_found = 0; + +*psize = 0; +*pchecksum = 0; +*pROMData = NULL; +*prom_array_name = NULL; +if (NULL == (iFile = fopen (include_filename, "r"))) + return -1; + +memset (line, 0, sizeof (line)); + +while (fgets (line, sizeof(line)-1, iFile)) { + unsigned int byte; + char *c; + + switch (line[0]) { + case '#': + if (0 == strncmp ("#define BOOT_CODE_SIZE ", line, 23)) + define_size_found = 1; + if (0 == strncmp ("#define BOOT_CODE_FILENAME ", line, 27)) + define_filename_found = 1; + if (0 == strncmp ("#define BOOT_CODE_ARRAY ", line, 24)) + define_array_found = 1; + break; + case ' ': + case '/': + case '*': + case '\n': + break; + case 'u': /* unsigned char {array_name}[] */ + *prom_array_name = calloc(512, sizeof(char)); + if (1 == sscanf (line, "unsigned char %s[]", *prom_array_name)) { + c = strchr (*prom_array_name, '['); + if (c) + *c = '\0'; + } + break; + case '0': /* line containing byte data */ + c = line; + while (1 == sscanf (c, "0x%2Xd,", &byte)) { + if (bytes_written >= allocated_size) { + allocated_size += 2048; + *pROMData = realloc(*pROMData, allocated_size); + } + *(*pROMData + bytes_written++) = byte; + c += 5; + } + break; + } + if (strchr (line, '}')) + break; + } +fclose (iFile); +for (i=0; i= statb.st_size) - Difference = 1; - else - IncludeData[bytes_written++] = byte; - c += 5; - } - if ((strchr (line,'}')) || Difference) - break; - } - fclose (iFile); - if (!Difference) - Difference = memcmp (IncludeData, ROMData, statb.st_size); - free (IncludeData); - if (!Difference) { +if (0 == sim_read_ROM_include(include_filename, + &include_bytes, + &include_ROMData, + &include_checksum, + &include_array_name, + &defines_found)) { + c = ((include_checksum == expected_checksum) && + (include_bytes == expected_size) && + (0 == strcmp (include_array_name, rom_array_name)) && + (0 == memcmp (include_ROMData, ROMData, include_bytes)) && + defines_found); + free(include_ROMData); + free(include_array_name); + if (c) { free (ROMData); return 0; } @@ -146,6 +288,11 @@ if (NULL == (iFile = fopen (include_filename, "w"))) { printf ("Error Opening '%s' for output: %s\n", include_filename, strerror(errno)); return -1; } +load_filename = strrchr (rom_filename, '/'); +if (load_filename) + ++load_filename; +else + load_filename = rom_filename; time (&now); fprintf (iFile, "#ifndef ROM_%s_H\n", rom_array_name); fprintf (iFile, "#define ROM_%s_H 0\n", rom_array_name); @@ -153,7 +300,11 @@ fprintf (iFile, "/*\n"); fprintf (iFile, " %s produced at %s", include_filename, ctime(&now)); fprintf (iFile, " from %s which was last modified at %s", rom_filename, ctime(&statb.st_mtime)); fprintf (iFile, " file size: %d (0x%X) - checksum: 0x%08X\n", (int)statb.st_size, (int)statb.st_size, checksum); +fprintf (iFile, " This file is a generated file and should NOT be edited or changed by hand.\n"); fprintf (iFile, "*/\n"); +fprintf (iFile, "#define BOOT_CODE_SIZE 0x%X\n", (int)statb.st_size); +fprintf (iFile, "#define BOOT_CODE_FILENAME \"%s\"\n", load_filename); +fprintf (iFile, "#define BOOT_CODE_ARRAY %s\n", rom_array_name); fprintf (iFile, "unsigned char %s[] = {", rom_array_name); for (bytes_written=0;bytes_written 2)) + status = sim_make_ROMs_entry (argv[2]); +else { + for (i=0; i @@ -147,9 +148,9 @@ int32 sim_del_char = '\b'; /* delete character */ #else int32 sim_del_char = 0177; #endif - -t_stat sim_con_poll_svc (UNIT *uptr); /* console connection poll routine */ -UNIT sim_con_unit = { UDATA (&sim_con_poll_svc, 0, 0) }; /* console connection unit */ +t_stat sim_con_poll_svc (UNIT *uptr); /* console connection poll routine */ +t_stat sim_con_reset (DEVICE *dptr); /* console connection poll routine */ +UNIT sim_con_unit = { UDATA (&sim_con_poll_svc, 0, 0) }; /* console connection unit */ /* debugging bitmaps */ #define DBG_TRC TMXR_DBG_TRC /* trace routine calls */ #define DBG_XMT TMXR_DBG_XMT /* display Transmitted Data */ @@ -171,7 +172,7 @@ MTAB sim_con_mod[] = { DEVICE sim_con_telnet = { "CON-TEL", &sim_con_unit, NULL, sim_con_mod, 1, 0, 0, 0, 0, 0, - NULL, NULL, NULL, NULL, NULL, NULL, + NULL, NULL, sim_con_reset, NULL, NULL, NULL, NULL, DEV_DEBUG, 0, sim_con_debug}; TMLN sim_con_ldsc = { 0 }; /* console line descr */ TMXR sim_con_tmxr = { 1, 0, 0, &sim_con_ldsc, NULL, &sim_con_telnet };/* console line mux */ @@ -180,20 +181,21 @@ TMXR sim_con_tmxr = { 1, 0, 0, &sim_con_ldsc, NULL, &sim_con_telnet };/* console t_stat sim_con_poll_svc (UNIT *uptr) { -if (sim_con_tmxr.master == 0) /* not Telnet? done */ - return SCPE_OK; +if ((sim_con_tmxr.master == 0) && /* not Telnet and not serial? */ + (sim_con_ldsc.serport == 0)) + return SCPE_OK; /* done */ if (tmxr_poll_conn (&sim_con_tmxr) >= 0) /* poll connect */ sim_con_ldsc.rcve = 1; /* rcv enabled */ sim_activate_after(uptr, 1000000); /* check again in 1 second */ +if (sim_con_ldsc.conn) + tmxr_send_buffered_data (&sim_con_ldsc); /* try to flush any buffered data */ return SCPE_OK; } - -extern volatile int32 stop_cpu; -extern int32 sim_quiet; -extern FILE *sim_log, *sim_deb; -extern FILEREF *sim_log_ref, *sim_deb_ref; -extern DEVICE *sim_devices[]; +t_stat sim_con_reset (DEVICE *dptr) +{ +return sim_con_poll_svc (&dptr->units[0]); /* establish polling as needed */ +} /* Set/show data structures */ @@ -205,6 +207,8 @@ static CTAB set_con_tab[] = { { "PCHAR", &sim_set_pchar, 0 }, { "TELNET", &sim_set_telnet, 0 }, { "NOTELNET", &sim_set_notelnet, 0 }, + { "SERIAL", &sim_set_serial, 0 }, + { "NOSERIAL", &sim_set_noserial, 0 }, { "LOG", &sim_set_logon, 0 }, { "NOLOG", &sim_set_logoff, 0 }, { "DEBUG", &sim_set_debon, 0 }, @@ -219,7 +223,7 @@ static SHTAB show_con_tab[] = { { "PCHAR", &sim_show_pchar, 0 }, { "LOG", &sim_show_cons_log, 0 }, { "TELNET", &sim_show_telnet, 0 }, - { "DEBUG", &sim_show_debug, 0 }, + { "DEBUG", &sim_show_cons_debug, 0 }, { "BUFFERED", &sim_show_cons_buff, 0 }, { NULL, NULL, 0 } }; @@ -233,6 +237,12 @@ static CTAB set_con_telnet_tab[] = { { NULL, NULL, 0 } }; +static CTAB set_con_serial_tab[] = { + { "LOG", &sim_set_cons_log, 0 }, + { "NOLOG", &sim_set_cons_nolog, 0 }, + { NULL, NULL, 0 } + }; + static int32 *cons_kmap[] = { &sim_int_char, &sim_brk_char, @@ -479,20 +489,23 @@ while (*cptr != 0) { /* do all mods */ if ((cvptr = strchr (gbuf, '='))) /* = value? */ *cvptr++ = 0; get_glyph (gbuf, gbuf, 0); /* modifier to UC */ - if (isdigit (*gbuf)) { - if (sim_con_tmxr.master) /* already open? */ - sim_set_notelnet (0, NULL); /* close first */ - r = tmxr_attach (&sim_con_tmxr, &sim_con_unit, gbuf);/* open master socket */ - sim_activate_after(&sim_con_unit, 1000000); /* check for connection in 1 second */ - return r; + if ((ctptr = find_ctab (set_con_telnet_tab, gbuf))) { /* match? */ + r = ctptr->action (ctptr->arg, cvptr); /* do the rest */ + if (r != SCPE_OK) + return r; } - else - if ((ctptr = find_ctab (set_con_telnet_tab, gbuf))) { /* match? */ - r = ctptr->action (ctptr->arg, cvptr); /* do the rest */ - if (r != SCPE_OK) - return r; + else { + r = sim_parse_addr (gbuf, NULL, 0, NULL, NULL, 0, NULL, NULL); + if (r == SCPE_OK) { + if (sim_con_tmxr.master) /* already open? */ + sim_set_notelnet (0, NULL); /* close first */ + r = tmxr_attach (&sim_con_tmxr, &sim_con_unit, gbuf);/* open master socket */ + if (r == SCPE_OK) + sim_activate_after(&sim_con_unit, 1000000); /* check for connection in 1 second */ + return r; } - else return SCPE_NOPARAM; + return SCPE_NOPARAM; + } } return SCPE_OK; } @@ -514,16 +527,22 @@ t_stat sim_show_telnet (FILE *st, DEVICE *dunused, UNIT *uunused, int32 flag, ch { if (cptr && (*cptr != 0)) return SCPE_2MARG; -if (sim_con_tmxr.master == 0) +if ((sim_con_tmxr.master == 0) && + (sim_con_ldsc.serport == 0)) fprintf (st, "Connected to console window\n"); else { - if (sim_con_ldsc.conn == 0) - fprintf (st, "Listening on port %d\n", sim_con_tmxr.port); - else { - fprintf (st, "Listening on port %d, connected to socket %d\n", - sim_con_tmxr.port, sim_con_ldsc.conn); + if (sim_con_ldsc.serport) { + fprintf (st, "Connected to "); tmxr_fconns (st, &sim_con_ldsc, -1); } + else + if (sim_con_ldsc.sock == 0) + fprintf (st, "Listening on port %s\n", sim_con_tmxr.port); + else { + fprintf (st, "Listening on port %s, connection from %s\n", + sim_con_tmxr.port, sim_con_ldsc.ipad); + tmxr_fconns (st, &sim_con_ldsc, -1); + } tmxr_fstats (st, &sim_con_ldsc, -1); } return SCPE_OK; @@ -591,6 +610,73 @@ else return SCPE_OK; } +/* Set console Debug Mode */ + +t_stat sim_set_cons_debug (int32 flg, char *cptr) +{ +return set_dev_debug (&sim_con_telnet, &sim_con_unit, flg, cptr); +} + +t_stat sim_show_cons_debug (FILE *st, DEVICE *dunused, UNIT *uunused, int32 flag, char *cptr) +{ +if (cptr && (*cptr != 0)) + return SCPE_2MARG; +return show_dev_debug (st, &sim_con_telnet, &sim_con_unit, flag, cptr); +} + +/* Set console to Serial port (and parameters) */ + +t_stat sim_set_serial (int32 flag, char *cptr) +{ +char *cvptr, gbuf[CBUFSIZE], ubuf[CBUFSIZE]; +CTAB *ctptr; +t_stat r; + +if ((cptr == NULL) || (*cptr == 0)) + return SCPE_2FARG; +while (*cptr != 0) { /* do all mods */ + cptr = get_glyph_nc (cptr, gbuf, ','); /* get modifier */ + if ((cvptr = strchr (gbuf, '='))) /* = value? */ + *cvptr++ = 0; + get_glyph (gbuf, ubuf, 0); /* modifier to UC */ + if ((ctptr = find_ctab (set_con_serial_tab, ubuf))) { /* match? */ + r = ctptr->action (ctptr->arg, cvptr); /* do the rest */ + if (r != SCPE_OK) + return r; + } + else { + SERHANDLE serport = sim_open_serial (gbuf, NULL, &r); + if (serport != INVALID_HANDLE) { + sim_close_serial (serport); + if (r == SCPE_OK) { + char cbuf[CBUFSIZE]; + if ((sim_con_tmxr.master) || /* already open? */ + (sim_con_ldsc.serport)) + sim_set_noserial (0, NULL); /* close first */ + sprintf(cbuf, "Connect=%s", gbuf); + r = tmxr_attach (&sim_con_tmxr, &sim_con_unit, cbuf);/* open master socket */ + sim_con_ldsc.rcve = 1; /* rcv enabled */ + if (r == SCPE_OK) + sim_activate_after(&sim_con_unit, 1000000); /* check for connection in 1 second */ + return r; + } + } + return SCPE_ARG; + } + } +return SCPE_OK; +} + +/* Close console Serial port */ + +t_stat sim_set_noserial (int32 flag, char *cptr) +{ +if (cptr && (*cptr != 0)) /* too many arguments? */ + return SCPE_2MARG; +if (sim_con_ldsc.serport == 0) /* ignore if already closed */ + return SCPE_OK; +return tmxr_close_master (&sim_con_tmxr); /* close master socket */ +} /* Log File Open/Close/Show Support */ @@ -685,7 +771,11 @@ t_stat sim_check_console (int32 sec) { int32 c, i; -if (sim_con_tmxr.master == 0) /* not Telnet? done */ +if (sim_con_ldsc.serport) + if (tmxr_poll_conn (&sim_con_tmxr) >= 0) + sim_con_ldsc.rcve = 1; /* rcv enabled */ +if ((sim_con_tmxr.master == 0) || /* serial console or not Telnet? done */ + (sim_con_ldsc.serport)) return SCPE_OK; if (sim_con_ldsc.conn || sim_con_ldsc.txbfd) { /* connected or buffered ? */ tmxr_poll_rx (&sim_con_tmxr); /* poll (check disconn) */ @@ -698,14 +788,6 @@ if (sim_con_ldsc.conn || sim_con_ldsc.txbfd) { /* connected or buffered fflush (sim_log); } } - else { - printf ("Running\r\n"); /* print transition */ - fflush (stdout); - if (sim_log) { /* log file? */ - fprintf (sim_log, "Running\n"); - fflush (sim_log); - } - } return SCPE_OK; } } @@ -745,15 +827,11 @@ t_stat sim_poll_kbd (void) int32 c; c = sim_os_poll_kbd (); /* get character */ -if ((c == SCPE_STOP) || (sim_con_tmxr.master == 0)) { /* ^E or not Telnet? */ - if (c & SCPE_KFLAG) - sim_debug (DBG_RCV, &sim_con_telnet, "Received: '%c'\n", c); - else - if (c == SCPE_STOP) - sim_debug (DBG_RCV, &sim_con_telnet, "Received: - STOP\n"); +if ((c == SCPE_STOP) || /* ^E or not Telnet? */ + ((sim_con_tmxr.master == 0) && /* and not serial? */ + (sim_con_ldsc.serport == 0))) return c; /* in-window */ - } -if (sim_con_ldsc.conn == 0) { /* no Telnet conn? */ +if (!sim_con_ldsc.conn) { /* no telnet or serial connection? */ if (!sim_con_ldsc.txbfd) /* unbuffered? */ return SCPE_LOST; /* connection lost */ if (tmxr_poll_conn (&sim_con_tmxr) >= 0) /* poll connect */ @@ -771,15 +849,15 @@ return SCPE_OK; t_stat sim_putchar (int32 c) { -if (sim_con_tmxr.master == 0) { /* not Telnet? */ +if ((sim_con_tmxr.master == 0) && /* not Telnet? */ + (sim_con_ldsc.serport == 0)) { /* and not serial port */ if (sim_log) /* log file? */ fputc (c, sim_log); - sim_debug (DBG_XMT, &sim_con_telnet, "Sending: '%c'\n", c); return sim_os_putchar (c); /* in-window version */ } if (sim_log && !sim_con_ldsc.txlog) /* log file, but no line log? */ fputc (c, sim_log); -if (sim_con_ldsc.conn == 0) { /* no Telnet conn? */ +if (!sim_con_ldsc.conn) { /* no Telnet or serial connection? */ if (!sim_con_ldsc.txbfd) /* unbuffered? */ return SCPE_LOST; /* connection lost */ if (tmxr_poll_conn (&sim_con_tmxr) >= 0) /* poll connect */ @@ -794,16 +872,16 @@ t_stat sim_putchar_s (int32 c) { t_stat r; -if (sim_con_tmxr.master == 0) { /* not Telnet? */ +if ((sim_con_tmxr.master == 0) && /* not Telnet? */ + (sim_con_ldsc.serport == 0)) { /* and not serial port */ if (sim_log) /* log file? */ fputc (c, sim_log); - sim_debug (DBG_XMT, &sim_con_telnet, "Sending: '%c'\n", c); return sim_os_putchar (c); /* in-window version */ } if (sim_log && !sim_con_ldsc.txlog) /* log file, but no line log? */ fputc (c, sim_log); -if (sim_con_ldsc.conn == 0) { /* no Telnet conn? */ - if (!sim_con_ldsc.txbfd) /* non-buffered Telnet conn? */ +if (!sim_con_ldsc.conn) { /* no Telnet or serial connection? */ + if (!sim_con_ldsc.txbfd) /* non-buffered Telnet connection? */ return SCPE_LOST; /* lost */ if (tmxr_poll_conn (&sim_con_tmxr) >= 0) /* poll connect */ sim_con_ldsc.rcve = 1; /* rcv enabled */ @@ -858,7 +936,7 @@ return c; } -#if defined(SIM_ASYNCH_IO) +#if defined(SIM_ASYNCH_IO) && defined(SIM_ASYNCH_MUX) extern pthread_mutex_t sim_tmxr_poll_lock; extern pthread_cond_t sim_tmxr_poll_cond; extern int32 sim_tmxr_poll_count; @@ -902,6 +980,7 @@ while (sim_asynch_enabled) { /* If we started something, let it finish before polling again */ if (wait_count) { + sim_debug (DBG_ASY, &sim_con_telnet, "_console_poll() - waiting for %d units\n", wait_count); pthread_cond_wait (&sim_tmxr_poll_cond, &sim_tmxr_poll_lock); sim_debug (DBG_ASY, &sim_con_telnet, "_console_poll() - continuing with after wait\n"); } @@ -940,7 +1019,7 @@ return NULL; } -#endif +#endif /* defined(SIM_ASYNCH_IO) && defined(SIM_ASYNCH_MUX) */ t_stat sim_ttinit (void) @@ -952,9 +1031,19 @@ return sim_os_ttinit (); t_stat sim_ttrun (void) { -if (!sim_con_tmxr.ldsc->uptr) /* If simulator didn't declare its input polling unit */ - sim_con_unit.flags &= ~UNIT_TM_POLL; /* we can't poll asynchronously */ -#if defined(SIM_ASYNCH_IO) +if (!sim_con_tmxr.ldsc->uptr) { /* If simulator didn't declare its input polling unit */ + sim_con_unit.dynflags &= ~UNIT_TM_POLL; /* we can't poll asynchronously */ + sim_con_unit.dynflags |= TMUF_NOASYNCH; /* disable asynchronous behavior */ + } +else { +#if defined(SIM_ASYNCH_IO) && defined(SIM_ASYNCH_MUX) + if (sim_asynch_enabled) { + sim_con_tmxr.ldsc->uptr->dynflags |= UNIT_TM_POLL;/* flag console input device as a polling unit */ + sim_con_unit.dynflags |= UNIT_TM_POLL; /* flag as polling unit */ + } +#endif + } +#if defined(SIM_ASYNCH_IO) && defined(SIM_ASYNCH_MUX) pthread_mutex_lock (&sim_tmxr_poll_lock); if (sim_asynch_enabled) { pthread_attr_t attr; @@ -976,7 +1065,7 @@ return sim_os_ttrun (); t_stat sim_ttcmd (void) { -#if defined(SIM_ASYNCH_IO) +#if defined(SIM_ASYNCH_IO) && defined(SIM_ASYNCH_MUX) pthread_mutex_lock (&sim_tmxr_poll_lock); if (sim_console_poll_running) { pthread_cond_signal (&sim_tmxr_poll_cond); @@ -1002,6 +1091,9 @@ t_bool sim_ttisatty (void) return sim_os_ttisatty (); } + +/* Platform specific routine definitions */ + /* VMS routines, from Ben Thomas, with fixes from Robert Alan Byer */ #if defined (VMS) @@ -1058,7 +1150,7 @@ run_mode.stat2 = cmd_mode.stat2 | TT2$M_PASTHRU; return SCPE_OK; } -t_stat sim_ttrun (void) +t_stat sim_os_ttrun (void) { unsigned int status; IOSB iosb; @@ -1070,7 +1162,7 @@ if ((status != SS$_NORMAL) || (iosb.status != SS$_NORMAL)) return SCPE_OK; } -t_stat sim_ttcmd (void) +t_stat sim_os_ttcmd (void) { unsigned int status; IOSB iosb; @@ -1148,7 +1240,7 @@ else if (sim_brk_char && (buf[0] == sim_brk_char)) buffered_character = SCPE_BREAK; else - buffered_character = (buf[0] | SCPE_KFLAG) + buffered_character = (buf[0] | SCPE_KFLAG); return TRUE; } @@ -1428,7 +1520,6 @@ void SIOUXUpdateScrollbar(void); int ps_kbhit(void); int ps_getch(void); -extern char sim_name[]; extern pSIOUXWin SIOUXTextWindow; static CursHandle iBeamCursorH = NULL; /* contains the iBeamCursor */ @@ -1767,7 +1858,7 @@ if (tcsetattr (0, TCSAFLUSH, &runtty) < 0) return SCPE_TTIERR; if (prior_norm) { /* at normal pri? */ errno = 0; - nice (10); /* try to lower pri */ + (void)nice (10); /* try to lower pri */ prior_norm = errno; /* if no error, done */ } return SCPE_OK; @@ -1779,7 +1870,7 @@ if (!isatty (fileno (stdin))) /* skip if !tty */ return SCPE_OK; if (!prior_norm) { /* priority down? */ errno = 0; - nice (-10); /* try to raise pri */ + (void)nice (-10); /* try to raise pri */ prior_norm = (errno == 0); /* if no error, done */ } if (tcsetattr (0, TCSAFLUSH, &cmdtty) < 0) @@ -1830,7 +1921,7 @@ t_stat sim_os_putchar (int32 out) char c; c = out; -write (1, &c, 1); +(void)write (1, &c, 1); return SCPE_OK; } diff --git a/sim_console.h b/sim_console.h index f2fcf086..6782ef0d 100644 --- a/sim_console.h +++ b/sim_console.h @@ -55,27 +55,27 @@ t_stat sim_set_console (int32 flag, char *cptr); t_stat sim_set_kmap (int32 flag, char *cptr); t_stat sim_set_telnet (int32 flag, char *cptr); t_stat sim_set_notelnet (int32 flag, char *cptr); +t_stat sim_set_serial (int32 flag, char *cptr); +t_stat sim_set_noserial (int32 flag, char *cptr); t_stat sim_set_logon (int32 flag, char *cptr); t_stat sim_set_logoff (int32 flag, char *cptr); t_stat sim_set_debon (int32 flag, char *cptr); t_stat sim_set_cons_debug (int32 flg, char *cptr); -t_stat sim_set_cons_nodebug (int32 flg, char *cptr); t_stat sim_set_cons_buff (int32 flg, char *cptr); t_stat sim_set_cons_unbuff (int32 flg, char *cptr); t_stat sim_set_cons_log (int32 flg, char *cptr); t_stat sim_set_cons_nolog (int32 flg, char *cptr); t_stat sim_set_deboff (int32 flag, char *cptr); t_stat sim_set_pchar (int32 flag, char *cptr); -t_stat sim_set_console_units (UNIT *rxuptr, UNIT *txuptr); t_stat sim_show_console (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr); t_stat sim_show_kmap (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr); t_stat sim_show_telnet (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr); t_stat sim_show_log (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr); t_stat sim_show_debug (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr); t_stat sim_show_pchar (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr); -t_stat sim_show_cons_debug (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr); t_stat sim_show_cons_buff (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr); t_stat sim_show_cons_log (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr); +t_stat sim_show_cons_debug (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr); t_stat sim_check_console (int32 sec); t_stat sim_open_logfile (char *filename, t_bool binary, FILE **pf, FILEREF **pref); t_stat sim_close_logfile (FILEREF **pref); @@ -92,4 +92,9 @@ t_stat sim_os_poll_kbd (void); int32 sim_tt_inpcvt (int32 c, uint32 mode); int32 sim_tt_outcvt (int32 c, uint32 mode); +extern int32 sim_int_char; /* interrupt character */ +extern int32 sim_brk_char; /* break character */ +extern int32 sim_tt_pchar; /* printable character mask */ +extern int32 sim_del_char; /* delete character */ + #endif diff --git a/sim_defs.h b/sim_defs.h index f018a618..cf93dce4 100644 --- a/sim_defs.h +++ b/sim_defs.h @@ -113,6 +113,12 @@ #include #include +#ifdef _WIN32 +#include +#undef PACKED /* avoid macro name collision */ +#undef ERROR /* avoid macro name collision */ +#endif + #ifndef TRUE #define TRUE 1 #define FALSE 0 @@ -275,9 +281,9 @@ typedef uint32 t_addr; #define SWMASK(x) (1u << (((int) (x)) - ((int) 'A'))) -/* String match */ +/* String match - at least one character required */ -#define MATCH_CMD(ptr,cmd) strncmp ((ptr), (cmd), strlen (ptr)) +#define MATCH_CMD(ptr,cmd) ((NULL == (ptr)) || (!*(ptr)) || strncmp ((ptr), (cmd), strlen (ptr))) /* End of Linked List/Queue value */ /* Chosen for 2 reasons: */ @@ -317,6 +323,11 @@ struct sim_device { t_stat (*msize)(struct sim_unit *up, int32 v, char *cp, void *dp); /* mem size routine */ char *lname; /* logical name */ + t_stat (*help)(FILE *st, struct sim_device *dptr, + struct sim_unit *uptr, int32 flag, char *cptr); /* help */ + t_stat (*attach_help)(FILE *st, struct sim_device *dptr, + struct sim_unit *uptr, int32 flag, char *cptr); /* attach help */ + void *help_ctx; /* Context available to help routines */ }; /* Device flags */ @@ -324,21 +335,27 @@ struct sim_device { #define DEV_V_DIS 0 /* dev disabled */ #define DEV_V_DISABLE 1 /* dev disable-able */ #define DEV_V_DYNM 2 /* mem size dynamic */ -#define DEV_V_NET 3 /* network attach */ -#define DEV_V_DEBUG 4 /* debug capability */ -#define DEV_V_RAW 5 /* raw supported */ -#define DEV_V_RAWONLY 6 /* only raw supported */ +#define DEV_V_DEBUG 3 /* debug capability */ +#define DEV_V_TYPE 4 /* Attach type */ +#define DEV_S_TYPE 3 /* Width of Type Field */ #define DEV_V_UF_31 12 /* user flags, V3.1 */ #define DEV_V_UF 16 /* user flags */ #define DEV_V_RSV 31 /* reserved */ -#define DEV_DIS (1 << DEV_V_DIS) -#define DEV_DISABLE (1 << DEV_V_DISABLE) -#define DEV_DYNM (1 << DEV_V_DYNM) -#define DEV_NET (1 << DEV_V_NET) -#define DEV_DEBUG (1 << DEV_V_DEBUG) -#define DEV_RAW (1 << DEV_V_RAW) -#define DEV_RAWONLY (1 << DEV_V_RAWONLY) +#define DEV_DIS (1 << DEV_V_DIS) /* device can be set enabled or disabled */ +#define DEV_DISABLE (1 << DEV_V_DISABLE) /* device is currently disabled */ +#define DEV_DYNM (1 << DEV_V_DYNM) /* device requires call on msize routine to change memory size */ +#define DEV_DEBUG (1 << DEV_V_DEBUG) /* device supports SET DEBUG command */ +#define DEV_NET 0 /* Deprecated - meaningless */ + + +#define DEV_TYPEMASK (((1 << DEV_S_TYPE) - 1) << DEV_V_TYPE) +#define DEV_DISK (1 << DEV_V_TYPE) /* sim_disk Attach */ +#define DEV_TAPE (2 << DEV_V_TYPE) /* sim_tape Attach */ +#define DEV_MUX (3 << DEV_V_TYPE) /* sim_tmxr Attach */ +#define DEV_ETHER (4 << DEV_V_TYPE) /* Ethernet Device */ +#define DEV_DISPLAY (5 << DEV_V_TYPE) /* Display Device */ +#define DEV_TYPE(dptr) ((dptr)->flags & DEV_TYPEMASK) #define DEV_UFMASK_31 (((1u << DEV_V_RSV) - 1) & ~((1u << DEV_V_UF_31) - 1)) #define DEV_UFMASK (((1u << DEV_V_RSV) - 1) & ~((1u << DEV_V_UF) - 1)) @@ -362,6 +379,7 @@ struct sim_unit { uint32 hwmark; /* high water mark */ int32 time; /* time out */ uint32 flags; /* flags */ + uint32 dynflags; /* dynamic flags */ t_addr capac; /* capacity */ t_addr pos; /* file position */ void (*io_flush)(struct sim_unit *up);/* io flush routine */ @@ -376,6 +394,8 @@ struct sim_unit { void *up8; /* device specific */ #ifdef SIM_ASYNCH_IO void (*a_check_completion)(struct sim_unit *); + t_bool (*a_is_active)(struct sim_unit *); + void (*a_cancel)(struct sim_unit *); struct sim_unit *a_next; /* next asynch active */ int32 a_event_time; t_stat (*a_activate_call)(struct sim_unit *, int32); @@ -410,17 +430,23 @@ struct sim_unit { #define UNIT_ROABLE 0001000 /* read only ok */ #define UNIT_DISABLE 0002000 /* disable-able */ #define UNIT_DIS 0004000 /* disabled */ -#define UNIT_RAW 0010000 /* raw mode */ -#define UNIT_TEXT 0020000 /* text mode */ #define UNIT_IDLE 0040000 /* idle eligible */ -#define UNIT_TM_POLL 0100000 /* TMXR Polling unit */ - /* This flag is ONLY set dynamically */ - /* it should NOT be set via initialization */ + +/* Unused/meaningless flags */ +#define UNIT_TEXT 0000000 /* text mode - no effect */ #define UNIT_UFMASK_31 (((1u << UNIT_V_RSV) - 1) & ~((1u << UNIT_V_UF_31) - 1)) #define UNIT_UFMASK (((1u << UNIT_V_RSV) - 1) & ~((1u << UNIT_V_UF) - 1)) #define UNIT_RFLAGS (UNIT_UFMASK|UNIT_DIS) /* restored flags */ +/* Unit dynamic flags (dynflags) */ + +/* These flags are only set dynamically */ + +#define UNIT_ATTMULT 0000001 /* Allow multiple attach commands */ +#define UNIT_TM_POLL 0000002 /* TMXR Polling unit */ +#define UNIT_NO_FIO 0000004 /* fileref is NOT a FILE * */ + /* Register data structure */ struct sim_reg { @@ -430,6 +456,7 @@ struct sim_reg { uint32 width; /* width */ uint32 offset; /* starting bit */ uint32 depth; /* save depth */ + char *desc; /* description */ uint32 flags; /* flags */ uint32 qptr; /* circ q ptr */ }; @@ -529,6 +556,15 @@ struct sim_debtab { #define SIM_DBG_EVENT 0x10000 #define SIM_DBG_ACTIVATE 0x20000 +#define SIM_DBG_AIO_QUEUE 0x40000 + +struct sim_bitfield { + char *name; /* field name */ + uint32 offset; /* starting bit */ + uint32 width; /* width */ + const char **valuenames; /* map of values to strings */ + const char *format; /* value format string */ + }; /* File Reference */ struct sim_fileref { @@ -539,27 +575,56 @@ struct sim_fileref { /* The following macros define structure contents */ -#define UDATA(act,fl,cap) NULL,act,NULL,NULL,NULL,0,0,(fl),(cap),0,NULL,0,0 +#define UDATA(act,fl,cap) NULL,act,NULL,NULL,NULL,0,0,(fl),0,(cap),0,NULL,0,0 #if defined (__STDC__) || defined (_WIN32) -#define ORDATA(nm,loc,wd) #nm, &(loc), 8, (wd), 0, 1 -#define DRDATA(nm,loc,wd) #nm, &(loc), 10, (wd), 0, 1 -#define HRDATA(nm,loc,wd) #nm, &(loc), 16, (wd), 0, 1 -#define FLDATA(nm,loc,pos) #nm, &(loc), 2, 1, (pos), 1 -#define GRDATA(nm,loc,rdx,wd,pos) #nm, &(loc), (rdx), (wd), (pos), 1 -#define BRDATA(nm,loc,rdx,wd,dep) #nm, (loc), (rdx), (wd), 0, (dep) +#define ORDATA(nm,loc,wd) #nm, &(loc), 8, (wd), 0, 1, NULL +#define DRDATA(nm,loc,wd) #nm, &(loc), 10, (wd), 0, 1, NULL +#define HRDATA(nm,loc,wd) #nm, &(loc), 16, (wd), 0, 1, NULL +#define FLDATA(nm,loc,pos) #nm, &(loc), 2, 1, (pos), 1, NULL +#define GRDATA(nm,loc,rdx,wd,pos) #nm, &(loc), (rdx), (wd), (pos), 1, NULL +#define BRDATA(nm,loc,rdx,wd,dep) #nm, (loc), (rdx), (wd), 0, (dep), NULL #define URDATA(nm,loc,rdx,wd,off,dep,fl) \ - #nm, &(loc), (rdx), (wd), (off), (dep), ((fl) | REG_UNIT) + #nm, &(loc), (rdx), (wd), (off), (dep), NULL, ((fl) | REG_UNIT) +#define ORDATAD(nm,loc,wd,desc) #nm, &(loc), 8, (wd), 0, 1, (desc) +#define DRDATAD(nm,loc,wd,desc) #nm, &(loc), 10, (wd), 0, 1, (desc) +#define HRDATAD(nm,loc,wd,desc) #nm, &(loc), 16, (wd), 0, 1, (desc) +#define FLDATAD(nm,loc,pos,desc) #nm, &(loc), 2, 1, (pos), 1, (desc) +#define GRDATAD(nm,loc,rdx,wd,pos,desc) #nm, &(loc), (rdx), (wd), (pos), 1, (desc) +#define BRDATAD(nm,loc,rdx,wd,dep,desc) #nm, (loc), (rdx), (wd), 0, (dep), (desc) +#define URDATAD(nm,loc,rdx,wd,off,dep,fl,desc) \ + #nm, &(loc), (rdx), (wd), (off), (dep), (desc), ((fl) | REG_UNIT) +#define BIT(nm) {#nm, 0xffffffff, 1} /* Single Bit definition */ +#define BITNC {"", 0xffffffff, 1} /* Don't care Bit definition */ +#define BITF(nm,sz) {#nm, 0xffffffff, sz} /* Bit Field definition */ +#define BITNCF(sz) {"", 0xffffffff, sz} /* Don't care Bit Field definition */ +#define BITFFMT(nm,sz,fmt) {#nm, 0xffffffff, sz, NULL, #fmt}/* Bit Field definition with Output format */ +#define BITFNAM(nm,sz,names) {#nm, 0xffffffff, sz, names} /* Bit Field definition with value->name map */ #else -#define ORDATA(nm,loc,wd) "nm", &(loc), 8, (wd), 0, 1 -#define DRDATA(nm,loc,wd) "nm", &(loc), 10, (wd), 0, 1 -#define HRDATA(nm,loc,wd) "nm", &(loc), 16, (wd), 0, 1 -#define FLDATA(nm,loc,pos) "nm", &(loc), 2, 1, (pos), 1 -#define GRDATA(nm,loc,rdx,wd,pos) "nm", &(loc), (rdx), (wd), (pos), 1 -#define BRDATA(nm,loc,rdx,wd,dep) "nm", (loc), (rdx), (wd), 0, (dep) +#define ORDATA(nm,loc,wd) "nm", &(loc), 8, (wd), 0, 1, NULL +#define DRDATA(nm,loc,wd) "nm", &(loc), 10, (wd), 0, 1, NULL +#define HRDATA(nm,loc,wd) "nm", &(loc), 16, (wd), 0, 1, NULL +#define FLDATA(nm,loc,pos) "nm", &(loc), 2, 1, (pos), 1, NULL +#define GRDATA(nm,loc,rdx,wd,pos) "nm", &(loc), (rdx), (wd), (pos), 1, NULL +#define BRDATA(nm,loc,rdx,wd,dep) "nm", (loc), (rdx), (wd), 0, (dep), NULL #define URDATA(nm,loc,rdx,wd,off,dep,fl) \ - "nm", &(loc), (rdx), (wd), (off), (dep), ((fl) | REG_UNIT) + "nm", &(loc), (rdx), (wd), (off), (dep), NULL, ((fl) | REG_UNIT) +#define ORDATAD(nm,loc,wd,desc) "nm", &(loc), 8, (wd), 0, 1, (desc) +#define DRDATAD(nm,loc,wd,desc) "nm", &(loc), 10, (wd), 0, 1, (desc) +#define HRDATAD(nm,loc,wd,desc) "nm", &(loc), 16, (wd), 0, 1, (desc) +#define FLDATAD(nm,loc,pos,desc) "nm", &(loc), 2, 1, (pos), 1, (desc) +#define GRDATAD(nm,loc,rdx,wd,pos,desc) "nm", &(loc), (rdx), (wd), (pos), 1, (desc) +#define BRDATAD(nm,loc,rdx,wd,dep,desc) "nm", (loc), (rdx), (wd), 0, (dep), (desc) +#define URDATAD(nm,loc,rdx,wd,off,dep,fl,desc) \ + "nm", &(loc), (rdx), (wd), (off), (dep), (desc), ((fl) | REG_UNIT) +#define BIT(nm) {"nm", 0xffffffff, 1} /* Single Bit definition */ +#define BITNC {"", 0xffffffff, 1} /* Don't care Bit definition */ +#define BITF(nm,sz) {"nm", 0xffffffff, sz} /* Bit Field definition */ +#define BITNCF(sz) {"", 0xffffffff, sz} /* Don't care Bit Field definition */ +#define BITFFMT(nm,sz,fmt) {"nm", 0xffffffff, sz, NULL, "fmt"}/* Bit Field definition with Output format */ +#define BITFNAM(nm,sz,names) {"nm", 0xffffffff, sz, names} /* Bit Field definition with value->name map */ #endif +#define ENDBITS {NULL} /* end of bitfield list */ /* Typedefs for principal structures */ @@ -574,26 +639,22 @@ typedef struct sim_schtab SCHTAB; typedef struct sim_brktab BRKTAB; typedef struct sim_debtab DEBTAB; typedef struct sim_fileref FILEREF; +typedef struct sim_bitfield BITFIELD; /* Function prototypes */ #include "scp.h" #include "sim_console.h" #include "sim_timer.h" -#include "sim_ether.h" #include "sim_fio.h" -#include "sim_tmxr.h" /* Asynch/Threaded I/O support */ -extern t_bool sim_asynch_enabled; - #if defined (SIM_ASYNCH_IO) #include -#include "sim_tmxr.h" extern pthread_mutex_t sim_asynch_lock; -extern pthread_cond_t sim_idle_wake; +extern pthread_cond_t sim_asynch_wake; extern pthread_mutex_t sim_timer_lock; extern pthread_cond_t sim_timer_wake; extern t_bool sim_timer_event_canceled; @@ -602,6 +663,8 @@ extern pthread_cond_t sim_tmxr_poll_cond; extern pthread_mutex_t sim_tmxr_poll_lock; extern pthread_t sim_asynch_main_threadid; extern UNIT * volatile sim_asynch_queue; +extern UNIT * volatile sim_wallclock_queue; +extern UNIT * volatile sim_wallclock_entry; extern UNIT * volatile sim_clock_cosched_queue; extern volatile t_bool sim_idle_wait; extern int32 sim_asynch_check; @@ -611,7 +674,7 @@ extern int32 sim_asynch_inst_latency; /* Thread local storage */ #if defined(__GNUC__) && !defined(__APPLE__) #define AIO_TLS __thread -#elif defined(__DECC_VER) || defined(_MSC_VER) +#elif defined(_MSC_VER) #define AIO_TLS __declspec(thread) #else /* Other compiler environment, then don't worry about thread local storage. */ @@ -619,43 +682,43 @@ extern int32 sim_asynch_inst_latency; #define AIO_TLS #endif - - -#define AIO_INIT \ - if (1) { \ - sim_asynch_main_threadid = pthread_self(); \ - sim_asynch_enabled = TRUE; \ - /* Empty list/list end uses the point value (void *)1. \ - This allows NULL in an entry's a_next pointer to \ - indicate that the entry is not currently in any list */ \ - sim_asynch_queue = QUEUE_LIST_END; \ - } \ - else \ - (void)0 -#define AIO_CLEANUP \ - if (1) { \ - pthread_mutex_destroy(&sim_asynch_lock); \ - pthread_cond_destroy(&sim_idle_wake); \ - pthread_mutex_destroy(&sim_timer_lock); \ - pthread_cond_destroy(&sim_timer_wake); \ - pthread_mutex_destroy(&sim_tmxr_poll_lock); \ - pthread_cond_destroy(&sim_tmxr_poll_cond); \ - } \ - else \ - (void)0 #define AIO_LOCK \ pthread_mutex_lock(&sim_asynch_lock) #define AIO_UNLOCK \ pthread_mutex_unlock(&sim_asynch_lock) +#define AIO_IS_ACTIVE(uptr) (((uptr)->a_is_active ? (uptr)->a_is_active (uptr) : FALSE) || ((uptr)->a_next)) +#if !defined(SIM_ASYNCH_MUX) && !defined(SIM_ASYNCH_CLOCKS) #define AIO_CANCEL(uptr) \ - if (1) { \ - if (((uptr)->flags & UNIT_TM_POLL) && \ + if ((uptr)->a_cancel) \ + (uptr)->a_cancel (uptr); \ + else \ + (void)0 +#endif /* !defined(SIM_ASYNCH_MUX) && !defined(SIM_ASYNCH_CLOCKS) */ +#if defined(SIM_ASYNCH_MUX) && !defined(SIM_ASYNCH_CLOCKS) +#define AIO_CANCEL(uptr) \ + if ((uptr)->a_cancel) \ + (uptr)->a_cancel (uptr); \ + else { \ + if (((uptr)->dynflags & UNIT_TM_POLL) && \ !((uptr)->next) && !((uptr)->a_next)) { \ (uptr)->a_polling_now = FALSE; \ sim_tmxr_poll_count -= (uptr)->a_poll_waiter_count; \ (uptr)->a_poll_waiter_count = 0; \ } \ - if (sim_is_active_bool (uptr)) { \ + } +#endif /* defined(SIM_ASYNCH_MUX) && !defined(SIM_ASYNCH_CLOCKS) */ +#if defined(SIM_ASYNCH_MUX) && defined(SIM_ASYNCH_CLOCKS) +#define AIO_CANCEL(uptr) \ + if ((uptr)->a_cancel) \ + (uptr)->a_cancel (uptr); \ + else { \ + if (((uptr)->dynflags & UNIT_TM_POLL) && \ + !((uptr)->next) && !((uptr)->a_next)) { \ + (uptr)->a_polling_now = FALSE; \ + sim_tmxr_poll_count -= (uptr)->a_poll_waiter_count; \ + (uptr)->a_poll_waiter_count = 0; \ + } \ + if (AIO_IS_ACTIVE (uptr)) { \ UNIT *cptr, *nptr; \ AIO_UPDATE_QUEUE; \ pthread_mutex_lock (&sim_timer_lock); \ @@ -699,9 +762,7 @@ extern int32 sim_asynch_inst_latency; } \ pthread_mutex_unlock (&sim_timer_lock); \ } \ - } \ - else \ - (void)0 + } #define AIO_RETURN_TIME(uptr) \ if (1) { \ pthread_mutex_lock (&sim_timer_lock); \ @@ -724,10 +785,14 @@ extern int32 sim_asynch_inst_latency; } \ else \ (void)0 +#else +#define AIO_RETURN_TIME(uptr) (void)0 +#endif #define AIO_EVENT_BEGIN(uptr) \ - do { + do { \ + int __was_poll = uptr->dynflags & UNIT_TM_POLL #define AIO_EVENT_COMPLETE(uptr, reason) \ - if (uptr->flags & UNIT_TM_POLL) { \ + if (__was_poll) { \ pthread_mutex_lock (&sim_tmxr_poll_lock); \ uptr->a_polling_now = FALSE; \ if (uptr->a_poll_waiter_count) { \ @@ -750,15 +815,41 @@ extern int32 sim_asynch_inst_latency; #if defined(_WIN32) || defined(__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4) || defined(__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8) #define USE_AIO_INTRINSICS 1 #endif -#if defined(USE_AIO_INTRINSICS) && !defined(DONT_USE_AIO_INTRINSICS) +/* Provide a way to test both Intrinsic and Lock based queue manipulations */ +/* when both are available on a particular platform */ +#if defined(DONT_USE_AIO_INTRINSICS) && defined(USE_AIO_INTRINSICS) +#undef USE_AIO_INTRINSICS +#endif +#ifdef USE_AIO_INTRINSICS /* This approach uses intrinsics to manage access to the link list head */ /* sim_asynch_queue. This implementation is a completely lock free design */ /* which avoids the potential ABA issues. */ +#define AIO_QUEUE_MODE "Lock free asynchronous event queue access" +#define AIO_INIT \ + if (1) { \ + sim_asynch_main_threadid = pthread_self(); \ + /* Empty list/list end uses the point value (void *)1. \ + This allows NULL in an entry's a_next pointer to \ + indicate that the entry is not currently in any list */ \ + sim_asynch_queue = QUEUE_LIST_END; \ + sim_wallclock_queue = QUEUE_LIST_END; \ + sim_wallclock_entry = NULL; \ + sim_clock_cosched_queue = QUEUE_LIST_END; \ + } \ + else \ + (void)0 +#define AIO_CLEANUP \ + if (1) { \ + pthread_mutex_destroy(&sim_asynch_lock); \ + pthread_cond_destroy(&sim_asynch_wake); \ + pthread_mutex_destroy(&sim_timer_lock); \ + pthread_cond_destroy(&sim_timer_wake); \ + pthread_mutex_destroy(&sim_tmxr_poll_lock); \ + pthread_cond_destroy(&sim_tmxr_poll_cond); \ + } \ + else \ + (void)0 #ifdef _WIN32 -#include -#ifdef ERROR -#undef ERROR -#endif /* ERROR */ #elif defined(__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4) || defined(__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8) #define InterlockedCompareExchangePointer(Destination, Exchange, Comparand) __sync_val_compare_and_swap(Destination, Comparand, Exchange) #elif defined(__DECC_VER) @@ -775,6 +866,7 @@ extern int32 sim_asynch_inst_latency; do \ q = AIO_QUEUE_VAL; \ while (q != AIO_QUEUE_SET(QUEUE_LIST_END, q)); \ + sim_debug (SIM_DBG_AIO_QUEUE, sim_dflt_dev, "Found Asynch event for %s after %d instructions\n", sim_uname(q), q->a_event_time);\ while (q != QUEUE_LIST_END) { /* List !Empty */ \ uptr = q; \ q = q->a_next; \ @@ -794,30 +886,30 @@ extern int32 sim_asynch_inst_latency; #define AIO_ACTIVATE(caller, uptr, event_time) \ if (!pthread_equal ( pthread_self(), sim_asynch_main_threadid )) { \ UNIT *ouptr = (uptr); \ - sim_debug (TIMER_DBG_QUEUE, &sim_timer_dev, "asynch event on %s after %d instructions\n", sim_uname(uptr), event_time);\ - if (uptr->a_next) { /* already queued? */ \ - uptr->a_activate_call = sim_activate_abs; \ + sim_debug (SIM_DBG_AIO_QUEUE, sim_dflt_dev, "Queueing Asynch event for %s after %d instructions\n", sim_uname(ouptr), event_time);\ + if (ouptr->a_next) { \ + ouptr->a_activate_call = sim_activate_abs; \ } else { \ UNIT *q, *qe; \ - uptr->a_event_time = event_time; \ + ouptr->a_event_time = event_time; \ uptr->a_activate_call = caller; \ uptr->a_next = QUEUE_LIST_END; /* Mark as on list */ \ do { \ do \ q = AIO_QUEUE_VAL; \ while (q != AIO_QUEUE_SET(QUEUE_LIST_END, q));/* Grab current list */\ - for (qe = uptr; qe->a_next != QUEUE_LIST_END; qe = qe->a_next); \ + for (qe = ouptr; qe->a_next != QUEUE_LIST_END; qe = qe->a_next); \ qe->a_next = q; /* append current list */\ do \ q = AIO_QUEUE_VAL; \ - while (q != AIO_QUEUE_SET(uptr, q)); \ - uptr = q; \ - } while (uptr != QUEUE_LIST_END); \ + while (q != AIO_QUEUE_SET(ouptr, q)); \ + ouptr = q; \ + } while (ouptr != QUEUE_LIST_END); \ } \ sim_asynch_check = 0; /* try to force check */ \ if (sim_idle_wait) { \ sim_debug (TIMER_DBG_IDLE, &sim_timer_dev, "waking due to event on %s after %d instructions\n", sim_uname(ouptr), event_time);\ - pthread_cond_signal (&sim_idle_wake); \ + pthread_cond_signal (&sim_asynch_wake); \ } \ return SCPE_OK; \ } else (void)0 @@ -825,13 +917,45 @@ extern int32 sim_asynch_inst_latency; /* This approach uses a pthread mutex to manage access to the link list */ /* head sim_asynch_queue. It will always work, but may be slower than the */ /* lock free approach when using USE_AIO_INTRINSICS */ +#define AIO_QUEUE_MODE "Lock based asynchronous event queue access" +#define AIO_INIT \ + if (1) { \ + pthread_mutexattr_t attr; \ + \ + pthread_mutexattr_init (&attr); \ + pthread_mutexattr_settype(&attr, PTHREAD_MUTEX_RECURSIVE); \ + pthread_mutex_init (&sim_asynch_lock, &attr); \ + pthread_mutexattr_destroy (&attr); \ + sim_asynch_main_threadid = pthread_self(); \ + /* Empty list/list end uses the point value (void *)1. \ + This allows NULL in an entry's a_next pointer to \ + indicate that the entry is not currently in any list */ \ + sim_asynch_queue = QUEUE_LIST_END; \ + sim_wallclock_queue = QUEUE_LIST_END; \ + sim_wallclock_entry = NULL; \ + sim_clock_cosched_queue = QUEUE_LIST_END; \ + } \ + else \ + (void)0 +#define AIO_CLEANUP \ + if (1) { \ + pthread_mutex_destroy(&sim_asynch_lock); \ + pthread_cond_destroy(&sim_asynch_wake); \ + pthread_mutex_destroy(&sim_timer_lock); \ + pthread_cond_destroy(&sim_timer_wake); \ + pthread_mutex_destroy(&sim_tmxr_poll_lock); \ + pthread_cond_destroy(&sim_tmxr_poll_cond); \ + } \ + else \ + (void)0 #define AIO_UPDATE_QUEUE \ if (1) { \ UNIT *uptr; \ - pthread_mutex_lock (&sim_asynch_lock); \ + AIO_LOCK; \ while (sim_asynch_queue != QUEUE_LIST_END) { /* List !Empty */ \ int32 a_event_time; \ uptr = sim_asynch_queue; \ + sim_debug (SIM_DBG_AIO_QUEUE, sim_dflt_dev, "found asynch event for %s after %d instructions\n", sim_uname(uptr), uptr->a_event_time);\ sim_asynch_queue = uptr->a_next; \ uptr->a_next = NULL; /* hygiene */ \ if (uptr->a_activate_call != &sim_activate_notbefore) { \ @@ -841,17 +965,19 @@ extern int32 sim_asynch_inst_latency; } \ else \ a_event_time = uptr->a_event_time; \ - pthread_mutex_unlock (&sim_asynch_lock); \ + AIO_UNLOCK; \ + sim_debug (SIM_DBG_AIO_QUEUE, sim_dflt_dev, "calling completion check for asynch event on %s\n", sim_uname(uptr));\ uptr->a_activate_call (uptr, a_event_time); \ if (uptr->a_check_completion) \ uptr->a_check_completion (uptr); \ - pthread_mutex_lock (&sim_asynch_lock); \ + AIO_LOCK; \ } \ - pthread_mutex_unlock (&sim_asynch_lock); \ + AIO_UNLOCK; \ } else (void)0 #define AIO_ACTIVATE(caller, uptr, event_time) \ if (!pthread_equal ( pthread_self(), sim_asynch_main_threadid )) { \ - pthread_mutex_lock (&sim_asynch_lock); \ + sim_debug (SIM_DBG_AIO_QUEUE, sim_dflt_dev, "queueing asynch event for %s after %d instructions\n", sim_uname(uptr), event_time);\ + AIO_UNLOCK; \ if (uptr->a_next) { /* already queued? */ \ uptr->a_activate_call = sim_activate_abs; \ } else { \ @@ -861,8 +987,8 @@ extern int32 sim_asynch_inst_latency; sim_asynch_queue = uptr; \ } \ if (sim_idle_wait) \ - pthread_cond_signal (&sim_idle_wake); \ - pthread_mutex_unlock (&sim_asynch_lock); \ + pthread_cond_signal (&sim_asynch_wake); \ + AIO_UNLOCK; \ sim_asynch_check = 0; \ return SCPE_OK; \ } else (void)0 @@ -880,18 +1006,20 @@ extern int32 sim_asynch_inst_latency; sim_asynch_inst_latency = 1; \ } else (void)0 #else /* !SIM_ASYNCH_IO */ +#define AIO_QUEUE_MODE "Asynchronous I/O is not available" #define AIO_UPDATE_QUEUE #define AIO_ACTIVATE(caller, uptr, event_time) #define AIO_VALIDATE #define AIO_CHECK_EVENT #define AIO_INIT -#define AIO_CLEANUP #define AIO_LOCK #define AIO_UNLOCK -#define AIO_CANCEL(uptr) +#define AIO_CLEANUP #define AIO_RETURN_TIME(uptr) #define AIO_EVENT_BEGIN(uptr) #define AIO_EVENT_COMPLETE(uptr, reason) +#define AIO_IS_ACTIVE(uptr) FALSE +#define AIO_CANCEL(uptr) #define AIO_SET_INTERRUPT_LATENCY(instpersec) #define AIO_TLS #endif /* SIM_ASYNCH_IO */ diff --git a/sim_disk.c b/sim_disk.c index fedfa427..cf576f77 100644 --- a/sim_disk.c +++ b/sim_disk.c @@ -34,6 +34,7 @@ Public routines: sim_disk_attach attach disk unit sim_disk_detach detach disk unit + sim_disk_attach_help help routine for attaching disks sim_disk_rdsect read disk sectors sim_disk_rdsect_a read disk sectors asynchronously sim_disk_wrsect write disk sectors @@ -83,12 +84,6 @@ Internal routines: #include #endif -extern FILE *sim_log; /* log file */ -extern int32 sim_switches; -extern int32 sim_quiet; -extern uint32 sim_taddr_64; -extern int32 sim_end; - struct disk_context { DEVICE *dptr; /* Device for unit (access to debug flags) */ uint32 dbit; /* debugging bit */ @@ -108,6 +103,7 @@ struct disk_context { pthread_t io_thread; /* I/O Thread Id */ pthread_mutex_t io_lock; pthread_cond_t io_cond; + pthread_cond_t io_done; pthread_cond_t startup_cond; int io_dop; uint8 *buf; @@ -136,7 +132,7 @@ if ((!callback) || !ctx->asynch_io) \ sim_debug (ctx->dbit, ctx->dptr, \ "sim_disk AIO_CALL(op=%d, unit=%d, lba=0x%X, sects=%d)\n",\ - op, uptr-ctx->dptr->units, _lba, _sects); \ + op, (int)(uptr-ctx->dptr->units), _lba, _sects);\ \ if (ctx->callback) \ abort(); /* horrible mistake, stop */ \ @@ -174,7 +170,7 @@ pthread_getschedparam (pthread_self(), &sched_policy, &sched_priority); ++sched_priority.sched_priority; pthread_setschedparam (pthread_self(), sched_policy, &sched_priority); -sim_debug (ctx->dbit, ctx->dptr, "_disk_io(unit=%d) starting\n", uptr-ctx->dptr->units); +sim_debug (ctx->dbit, ctx->dptr, "_disk_io(unit=%d) starting\n", (int)(uptr-ctx->dptr->units)); pthread_mutex_lock (&ctx->io_lock); pthread_cond_signal (&ctx->startup_cond); /* Signal we're ready to go */ @@ -196,11 +192,12 @@ while (ctx->asynch_io) { } pthread_mutex_lock (&ctx->io_lock); ctx->io_dop = DOP_DONE; + pthread_cond_signal (&ctx->io_done); sim_activate (uptr, ctx->asynch_io_latency); } pthread_mutex_unlock (&ctx->io_lock); -sim_debug (ctx->dbit, ctx->dptr, "_disk_io(unit=%d) exiting\n", uptr-ctx->dptr->units); +sim_debug (ctx->dbit, ctx->dptr, "_disk_io(unit=%d) exiting\n", (int)(uptr-ctx->dptr->units)); return NULL; } @@ -209,7 +206,7 @@ return NULL; processing events for any unit. It is only called when an asynchronous thread has called sim_activate() to activate a unit. The job of this routine is to put the unit in proper condition to digest what may have - occurred in the asynchrcondition thread. + occurred in the asynchrconous thread. Since disk processing only handles a single I/O at a time to a particular disk device (due to using stdio for the SimH Disk format @@ -221,7 +218,7 @@ static void _disk_completion_dispatch (UNIT *uptr) struct disk_context *ctx = (struct disk_context *)uptr->disk_ctx; DISK_PCALLBACK callback = ctx->callback; -sim_debug (ctx->dbit, ctx->dptr, "_disk_completion_dispatch(unit=%d, dop=%d, callback=%p)\n", uptr-ctx->dptr->units, ctx->io_dop, ctx->callback); +sim_debug (ctx->dbit, ctx->dptr, "_disk_completion_dispatch(unit=%d, dop=%d, callback=%p)\n", (int)(uptr-ctx->dptr->units), ctx->io_dop, ctx->callback); if (ctx->io_dop != DOP_DONE) abort(); /* horribly wrong, stop */ @@ -231,6 +228,32 @@ if (ctx->callback && ctx->io_dop == DOP_DONE) { callback (uptr, ctx->io_status); } } + +static t_bool _disk_is_active (UNIT *uptr) +{ +struct disk_context *ctx = (struct disk_context *)uptr->disk_ctx; + +if (ctx) { + sim_debug (ctx->dbit, ctx->dptr, "_disk_is_active(unit=%d, dop=%d)\n", uptr-ctx->dptr->units, ctx->io_dop); + return (ctx->io_dop != DOP_DONE); + } +return FALSE; +} + +static void _disk_cancel (UNIT *uptr) +{ +struct disk_context *ctx = (struct disk_context *)uptr->disk_ctx; + +if (ctx) { + sim_debug (ctx->dbit, ctx->dptr, "_disk_cancel(unit=%d, dop=%d)\n", uptr-ctx->dptr->units, ctx->io_dop); + if (ctx->asynch_io) { + pthread_mutex_lock (&ctx->io_lock); + while (ctx->io_dop != DOP_DONE) + pthread_cond_wait (&ctx->io_done, &ctx->io_lock); + pthread_mutex_unlock (&ctx->io_lock); + } + } +} #else #define AIO_CALLSETUP #define AIO_CALL(op, _lba, _buf, _rsects, _sects, _callback) \ @@ -244,11 +267,13 @@ static t_stat sim_vhd_disk_implemented (void); static FILE *sim_vhd_disk_open (const char *rawdevicename, const char *openmode); static FILE *sim_vhd_disk_create (const char *szVHDPath, t_addr desiredsize); static FILE *sim_vhd_disk_create_diff (const char *szVHDPath, const char *szParentVHDPath); +static FILE *sim_vhd_disk_merge (const char *szVHDPath, char **ParentVHD); static int sim_vhd_disk_close (FILE *f); static void sim_vhd_disk_flush (FILE *f); static t_addr sim_vhd_disk_size (FILE *f); static t_stat sim_vhd_disk_rdsect (UNIT *uptr, t_lba lba, uint8 *buf, t_seccnt *sectsread, t_seccnt sects); static t_stat sim_vhd_disk_wrsect (UNIT *uptr, t_lba lba, uint8 *buf, t_seccnt *sectswritten, t_seccnt sects); +static t_stat sim_vhd_disk_clearerr (UNIT *uptr); static t_stat sim_vhd_disk_set_dtype (FILE *f, const char *dtype); static const char *sim_vhd_disk_get_dtype (FILE *f); static t_stat sim_os_disk_implemented_raw (void); @@ -262,6 +287,8 @@ static t_stat sim_os_disk_rdsect (UNIT *uptr, t_lba lba, uint8 *buf, t_seccnt *s static t_stat sim_os_disk_wrsect (UNIT *uptr, t_lba lba, uint8 *buf, t_seccnt *sectswritten, t_seccnt sects); static t_stat sim_os_disk_info_raw (FILE *f, uint32 *sector_size, uint32 *removable); static t_stat sim_disk_pdp11_bad_block (UNIT *uptr, int32 sec); +static char *HostPathToVhdPath (const char *szHostPath, char *szVhdPath, size_t VhdPathSize); +static char *VhdPathToHostPath (const char *szVhdPath, char *szHostPath, size_t HostPathSize); struct sim_disk_fmt { char *name; /* name */ @@ -425,6 +452,7 @@ ctx->asynch_io_latency = latency; if (ctx->asynch_io) { pthread_mutex_init (&ctx->io_lock, NULL); pthread_cond_init (&ctx->io_cond, NULL); + pthread_cond_init (&ctx->io_done, NULL); pthread_cond_init (&ctx->startup_cond, NULL); pthread_attr_init(&attr); pthread_attr_setscope(&attr, PTHREAD_SCOPE_SYSTEM); @@ -434,8 +462,10 @@ if (ctx->asynch_io) { pthread_cond_wait (&ctx->startup_cond, &ctx->io_lock); /* Wait for thread to stabilize */ pthread_mutex_unlock (&ctx->io_lock); pthread_cond_destroy (&ctx->startup_cond); - uptr->a_check_completion = _disk_completion_dispatch; } +uptr->a_check_completion = _disk_completion_dispatch; +uptr->a_is_active = _disk_is_active; +uptr->a_cancel = _disk_cancel; #endif return SCPE_OK; } @@ -460,6 +490,7 @@ if (ctx->asynch_io) { pthread_join (ctx->io_thread, NULL); pthread_mutex_destroy (&ctx->io_lock); pthread_cond_destroy (&ctx->io_cond); + pthread_cond_destroy (&ctx->io_done); } return SCPE_OK; #endif @@ -474,7 +505,7 @@ uint32 err, tbc; size_t i; struct disk_context *ctx = (struct disk_context *)uptr->disk_ctx; -sim_debug (ctx->dbit, ctx->dptr, "_sim_disk_rdsect(unit=%d, lba=0x%X, sects=%d)\n", uptr-ctx->dptr->units, lba, sects); +sim_debug (ctx->dbit, ctx->dptr, "_sim_disk_rdsect(unit=%d, lba=0x%X, sects=%d)\n", (int)(uptr-ctx->dptr->units), lba, sects); da = ((t_addr)lba) * ctx->sector_size; tbc = sects * ctx->sector_size; @@ -498,7 +529,7 @@ t_stat r; struct disk_context *ctx = (struct disk_context *)uptr->disk_ctx; t_seccnt sread; -sim_debug (ctx->dbit, ctx->dptr, "sim_disk_rdsect(unit=%d, lba=0x%X, sects=%d)\n", uptr-ctx->dptr->units, lba, sects); +sim_debug (ctx->dbit, ctx->dptr, "sim_disk_rdsect(unit=%d, lba=0x%X, sects=%d)\n", (int)(uptr-ctx->dptr->units), lba, sects); if ((sects == 1) && /* Single sector reads */ (lba >= (uptr->capac*ctx->capac_factor)/ctx->sector_size)) {/* beyond the end of the disk */ @@ -531,7 +562,7 @@ if ((0 == (ctx->sector_size & (ctx->storage_sector_size - 1))) || /* Sector Al return r; } else { /* Unaligned and/or partial sector transfers */ - uint8 *tbuf = malloc (sects*ctx->sector_size + 2*ctx->storage_sector_size); + uint8 *tbuf = (uint8*) malloc (sects*ctx->sector_size + 2*ctx->storage_sector_size); t_lba sspsts = ctx->storage_sector_size/ctx->sector_size; /* sim sectors in a storage sector */ t_lba tlba = lba & ~(sspsts - 1); t_seccnt tsects = sects + (lba - tlba); @@ -590,7 +621,7 @@ uint32 err, tbc; size_t i; struct disk_context *ctx = (struct disk_context *)uptr->disk_ctx; -sim_debug (ctx->dbit, ctx->dptr, "_sim_disk_wrsect(unit=%d, lba=0x%X, sects=%d)\n", uptr-ctx->dptr->units, lba, sects); +sim_debug (ctx->dbit, ctx->dptr, "_sim_disk_wrsect(unit=%d, lba=0x%X, sects=%d)\n", (int)(uptr-ctx->dptr->units), lba, sects); da = ((t_addr)lba) * ctx->sector_size; tbc = sects * ctx->sector_size; @@ -613,7 +644,7 @@ uint32 f = DK_GET_FMT (uptr); t_stat r; uint8 *tbuf = NULL; -sim_debug (ctx->dbit, ctx->dptr, "sim_disk_wrsect(unit=%d, lba=0x%X, sects=%d)\n", uptr-ctx->dptr->units, lba, sects); +sim_debug (ctx->dbit, ctx->dptr, "sim_disk_wrsect(unit=%d, lba=0x%X, sects=%d)\n", (int)(uptr-ctx->dptr->units), lba, sects); if (f == DKUF_F_STD) return _sim_disk_wrsect (uptr, lba, buf, sectswritten, sects); @@ -631,7 +662,7 @@ if ((0 == (ctx->sector_size & (ctx->storage_sector_size - 1))) || /* Sector Al return SCPE_NOFNC; } - tbuf = malloc (sects * ctx->sector_size); + tbuf = (uint8*) malloc (sects * ctx->sector_size); if (NULL == tbuf) return SCPE_MEM; sim_buf_copy_swapped (tbuf, buf, ctx->xfer_element_size, (sects * ctx->sector_size) / ctx->xfer_element_size); @@ -653,7 +684,7 @@ else { /* Unaligned and/or partial sector transfers */ t_lba tlba = lba & ~(sspsts - 1); t_seccnt tsects = sects + (lba - tlba); - tbuf = malloc (sects*ctx->sector_size + 2*ctx->storage_sector_size); + tbuf = (uint8*) malloc (sects*ctx->sector_size + 2*ctx->storage_sector_size); tsects = (tsects + (sspsts - 1)) & ~(sspsts - 1); if (sectswritten) *sectswritten = 0; @@ -736,6 +767,10 @@ switch (DK_GET_FMT (uptr)) { /* case on format */ } } +/* + This routine is called when the simulator stops and any time + the asynch mode is changed (enabled or disabled) +*/ static void _sim_disk_io_flush (UNIT *uptr) { uint32 f = DK_GET_FMT (uptr); @@ -843,7 +878,7 @@ if (sim_switches & SWMASK ('C')) { /* create vhd disk & cop return SCPE_OPENERR; } else { - uint8 *copy_buf = malloc (1024*1024); + uint8 *copy_buf = (uint8*) malloc (1024*1024); t_lba lba; t_seccnt sectors_per_buffer = (t_seccnt)((1024*1024)/sector_size); t_lba total_sectors = (t_lba)((uptr->capac*capac_factor)/sector_size); @@ -883,6 +918,24 @@ if (sim_switches & SWMASK ('C')) { /* create vhd disk & cop /* fall through and open/return the newly created & copied vhd */ } } +else if (sim_switches & SWMASK ('M')) { /* merge difference disk? */ + char gbuf[CBUFSIZE], *Parent = NULL; + FILE *vhd; + + sim_switches = sim_switches & ~(SWMASK ('M')); + get_glyph_nc (cptr, gbuf, 0); /* get spec */ + vhd = sim_vhd_disk_merge (gbuf, &Parent); + if (vhd) { + t_stat r; + + sim_vhd_disk_close (vhd); + r = sim_disk_attach (uptr, Parent, sector_size, xfer_element_size, dontautosize, dbit, dtype, pdp11tracksize, completion_delay); + free (Parent); + return r; + } + return SCPE_ARG; + } + switch (DK_GET_FMT (uptr)) { /* case on format */ case DKUF_F_STD: /* SIMH format */ if (NULL == (uptr->fileref = sim_vhd_disk_open (cptr, "rb"))) { @@ -1007,7 +1060,7 @@ if (created) { } capac = size_function (uptr->fileref); -if (capac && (capac != (t_addr)-1)) +if (capac && (capac != (t_addr)-1)) { if (dontautosize) { if ((capac < (uptr->capac*ctx->capac_factor)) && (DKUF_F_STD != DK_GET_FMT (uptr))) { if (!sim_quiet) { @@ -1022,6 +1075,7 @@ if (capac && (capac != (t_addr)-1)) else if ((capac > (uptr->capac*ctx->capac_factor)) || (DKUF_F_STD != DK_GET_FMT (uptr))) uptr->capac = capac/ctx->capac_factor; + } #if defined (SIM_ASYNCH_IO) sim_disk_set_async (uptr, completion_delay); @@ -1063,14 +1117,13 @@ if (NULL == find_dev_from_unit (uptr)) return SCPE_OK; auto_format = ctx->auto_format; +sim_disk_clr_async (uptr); + if (uptr->io_flush) uptr->io_flush (uptr); /* flush buffered data */ -#if defined SIM_ASYNCH_IO -sim_disk_clr_async (uptr); -#endif - -uptr->flags = uptr->flags & ~(UNIT_ATT | UNIT_RO | UNIT_RAW); +uptr->flags &= ~(UNIT_ATT | UNIT_RO); +uptr->dynflags &= ~UNIT_NO_FIO; free (uptr->filename); uptr->filename = NULL; uptr->fileref = NULL; @@ -1084,16 +1137,110 @@ if (close_function (fileref) == EOF) return SCPE_OK; } +t_stat sim_disk_attach_help(FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr) +{ +size_t unit_number = (uptr-dptr->units); + +fprintf (st, "%s Disk Attach Help\n\n", dptr->name); + +fprintf (st, "Disk container files can be one of 3 different types:\n\n"); +fprintf (st, " SIMH A disk is an unstructured binary file of the size appropriate\n"); +fprintf (st, " for the disk drive being simulated\n"); +fprintf (st, " VHD Virtual Disk format which is described in the \"Microsoft\n"); +fprintf (st, " Virtual Hard Disk (VHD) Image Format Specification\". The\n"); +fprintf (st, " VHD implementation includes support for 1) Fixed (Preallocated)\n"); +fprintf (st, " disks, 2) Dynamically Expanding disks, and 3) Differencing disks.\n"); +fprintf (st, " RAW platform specific access to physical disk or CDROM drives\n\n"); +fprintf (st, "Virtual (VHD) Disks supported conform to \"Virtual Hard Disk Image Format\n"); +fprintf (st, "Specification\", Version 1.0 October 11, 2006.\n"); +fprintf (st, "Dynamically expanding disks never change their \"Virtual Size\", but they don't\n"); +fprintf (st, "consume disk space on the containing storage until the virtual sectors in the\n"); +fprintf (st, "disk are actually written to (i.e. a 2GB Dynamic disk container file with only\n"); +fprintf (st, "30MB of data will initially be about 30MB in size and this size will grow up to\n"); +fprintf (st, "2GB as different sectors are written to. The VHD format contains metadata\n"); +fprintf (st, "which describes the drive size and the simh device type in use when the VHD\n"); +fprintf (st, "was created. This metadata is therefore available whenever that VHD is\n"); +fprintf (st, "attached to an emulated disk device in the future so the device type and\n"); +fprintf (st, "size can be automatically be configured.\n\n"); + +if (0 == (uptr-dptr->units)) { + if (dptr->numunits > 1) { + uint32 i; + + for (i=0; i < dptr->numunits; ++i) + if (dptr->units[i].flags & UNIT_ATTABLE) + fprintf (st, " sim> ATTACH {switches} %s%d diskfile\n", dptr->name, i); + } + else + fprintf (st, " sim> ATTACH {switches} %s diskfile\n", dptr->name); + } +else + fprintf (st, " sim> ATTACH {switches} %s diskfile\n\n", dptr->name); +fprintf (st, "\n%s attach command switches\n", dptr->name); +fprintf (st, " -R Attach Read Only.\n"); +fprintf (st, " -E Must Exist (if not specified an attempt to create the indicated\n"); +fprintf (st, " disk container will be attempted).\n"); +fprintf (st, " -F Open the indicated disk container in a specific format (default\n"); +fprintf (st, " is to autodetect VHD defaulting to simh if the indicated\n"); +fprintf (st, " container is not a VHD).\n"); +fprintf (st, " -C Create a VHD and copy its contents from another disk (simh, VHD,\n"); +fprintf (st, " or RAW format).\n"); +fprintf (st, " -X When creating a VHD, create a fixed sized VHD (vs a Dynamically\n"); +fprintf (st, " expanding one).\n"); +fprintf (st, " -D Create a Differencing VHD (relative to an already existing VHD\n"); +fprintf (st, " disk)\n"); +fprintf (st, " -M Merge a Differencing VHD into its parent VHD disk\n"); +return SCPE_OK; +} + t_stat sim_disk_reset (UNIT *uptr) { +struct disk_context *ctx = (struct disk_context *)uptr->disk_ctx; + if (!(uptr->flags & UNIT_ATT)) /* attached? */ return SCPE_OK; + +sim_debug (ctx->dbit, ctx->dptr, "sim_disk_reset(unit=%d)\n", (int)(uptr-ctx->dptr->units)); + _sim_disk_io_flush(uptr); AIO_VALIDATE; AIO_UPDATE_QUEUE; return SCPE_OK; } +t_stat sim_disk_perror (UNIT *uptr, const char *msg) +{ +if (!(uptr->flags & UNIT_ATTABLE)) /* not attachable? */ + return SCPE_NOATT; +switch (DK_GET_FMT (uptr)) { /* case on format */ + case DKUF_F_STD: /* SIMH format */ + case DKUF_F_VHD: /* VHD format */ + case DKUF_F_RAW: /* Raw Physical Disk Access */ + perror (msg); + default: + ; + } +return SCPE_OK; +} + +t_stat sim_disk_clearerr (UNIT *uptr) +{ +if (!(uptr->flags & UNIT_ATTABLE)) /* not attachable? */ + return SCPE_NOATT; +switch (DK_GET_FMT (uptr)) { /* case on format */ + case DKUF_F_STD: /* SIMH format */ + clearerr (uptr->fileref); + break; + case DKUF_F_VHD: /* VHD format */ + sim_vhd_disk_clearerr (uptr); + break; + default: + ; + } +return SCPE_OK; +} + + /* Factory bad block table creation routine This routine writes a DEC standard 044 compliant bad block table on the @@ -1151,7 +1298,7 @@ void sim_disk_data_trace(UNIT *uptr, const uint8 *data, size_t lba, size_t len, struct disk_context *ctx = (struct disk_context *)uptr->disk_ctx; if (ctx->dptr->dctrl & reason) { - sim_debug (reason, ctx->dptr, "%s%d %s lbn: %08X len: %08X\n", ctx->dptr->name, uptr-ctx->dptr->units, txt, lba, len); + sim_debug (reason, ctx->dptr, "%s%d %s lbn: %08X len: %08X\n", ctx->dptr->name, (int)(uptr-ctx->dptr->units), txt, lba, len); if (detail) { size_t i, same, group, sidx, oidx; char outbuf[80], strbuf[18]; @@ -1161,11 +1308,11 @@ if (ctx->dptr->dctrl & reason) { if ((i > 0) && (0 == memcmp (&data[i], &data[i-16], 16))) { ++same; continue; - } + } if (same > 0) { sim_debug (reason, ctx->dptr, "%04X thru %04X same as above\n", i-(16*same), i-1); same = 0; - } + } group = (((len - i) > 16) ? 16 : (len - i)); for (sidx=oidx=0; sidxdptr->dctrl & reason) { strbuf[sidx] = data[i+sidx]; else strbuf[sidx] = '.'; - } + } outbuf[oidx] = '\0'; strbuf[sidx] = '\0'; sim_debug (reason, ctx->dptr, "%04X%-48s %s\n", i, outbuf, strbuf); - } - if (same > 0) - sim_debug (reason, ctx->dptr, "%04X thru %04X same as above\n", i-(16*same), len-1); + } + if (same > 0) { + sim_debug (reason, ctx->dptr, "%04X thru %04X same as above\n", i-(16*same), len-1); + } } } } @@ -1262,7 +1410,12 @@ if ((dwStatus >= ERROR_INVALID_STARTING_CODESEG) && (dwStatus <= ERROR_INFLOOP_I } errno = EINVAL; } +#if defined(__GNUC__) +#include +#include +#else #include +#endif struct _device_type { int32 Type; char *desc; @@ -1503,7 +1656,6 @@ return TRUE; static t_stat sim_os_disk_info_raw (FILE *Disk, uint32 *sector_size, uint32 *removable) { DWORD IoctlReturnSize; -#ifndef __GNUC__ STORAGE_DEVICE_NUMBER Device; ZeroMemory (&Device, sizeof (Device)); @@ -1515,8 +1667,7 @@ if (DeviceIoControl((HANDLE)Disk, /* handle to volume */ (DWORD) sizeof(Device), /* size of output buffer */ (LPDWORD) &IoctlReturnSize, /* number of bytes returned */ (LPOVERLAPPED) NULL)) /* OVERLAPPED structure */ - printf ("Device OK - Type: %s, Number: %d\n", _device_type_name (Device.DeviceType), Device.DeviceNumber); -#endif + printf ("Device OK - Type: %s, Number: %d\n", _device_type_name (Device.DeviceType), (int)Device.DeviceNumber); if (sector_size) *sector_size = 512; @@ -1601,7 +1752,7 @@ OVERLAPPED pos; struct disk_context *ctx = (struct disk_context *)uptr->disk_ctx; long long addr; -sim_debug (ctx->dbit, ctx->dptr, "sim_os_disk_rdsect(unit=%d, lba=0x%X, sects=%d)\n", uptr-ctx->dptr->units, lba, sects); +sim_debug (ctx->dbit, ctx->dptr, "sim_os_disk_rdsect(unit=%d, lba=0x%X, sects=%d)\n", (int)(uptr-ctx->dptr->units), lba, sects); addr = ((long long)lba) * ctx->sector_size; memset (&pos, 0, sizeof (pos)); @@ -1622,7 +1773,7 @@ OVERLAPPED pos; struct disk_context *ctx = (struct disk_context *)uptr->disk_ctx; long long addr; -sim_debug (ctx->dbit, ctx->dptr, "sim_os_disk_wrsect(unit=%d, lba=0x%X, sects=%d)\n", uptr-ctx->dptr->units, lba, sects); +sim_debug (ctx->dbit, ctx->dptr, "sim_os_disk_wrsect(unit=%d, lba=0x%X, sects=%d)\n", (int)(uptr-ctx->dptr->units), lba, sects); addr = ((long long)lba) * ctx->sector_size; memset (&pos, 0, sizeof (pos)); @@ -1651,7 +1802,6 @@ return SCPE_OK; static FILE *sim_os_disk_open_raw (const char *rawdevicename, const char *openmode) { -int fd; int mode = 0; if (strchr (openmode, 'r') && (strchr (openmode, '+') || strchr (openmode, 'w'))) @@ -1703,7 +1853,7 @@ struct disk_context *ctx = (struct disk_context *)uptr->disk_ctx; off_t addr; ssize_t bytesread; -sim_debug (ctx->dbit, ctx->dptr, "sim_os_disk_rdsect(unit=%d, lba=0x%X, sects=%d)\n", uptr-ctx->dptr->units, lba, sects); +sim_debug (ctx->dbit, ctx->dptr, "sim_os_disk_rdsect(unit=%d, lba=0x%X, sects=%d)\n", (int)(uptr-ctx->dptr->units), lba, sects); addr = ((off_t)lba) * ctx->sector_size; bytesread = pread((int)((long)uptr->fileref), buf, sects * ctx->sector_size, addr); @@ -1723,7 +1873,7 @@ struct disk_context *ctx = (struct disk_context *)uptr->disk_ctx; off_t addr; ssize_t byteswritten; -sim_debug (ctx->dbit, ctx->dptr, "sim_os_disk_wrsect(unit=%d, lba=0x%X, sects=%d)\n", uptr-ctx->dptr->units, lba, sects); +sim_debug (ctx->dbit, ctx->dptr, "sim_os_disk_wrsect(unit=%d, lba=0x%X, sects=%d)\n", (int)(uptr-ctx->dptr->units), lba, sects); addr = ((off_t)lba) * ctx->sector_size; byteswritten = pwrite((int)((long)uptr->fileref), buf, sects * ctx->sector_size, addr); @@ -1820,7 +1970,12 @@ static t_stat sim_vhd_disk_implemented (void) return SCPE_NOFNC; } -static FILE *sim_vhd_disk_open (const char *rawdevicename, const char *openmode) +static FILE *sim_vhd_disk_open (const char *vhdfilename, const char *openmode) +{ +return NULL; +} + +static FILE *sim_vhd_disk_merge (const char *szVHDPath, char **ParentVHD) { return NULL; } @@ -1854,6 +2009,11 @@ static t_stat sim_vhd_disk_rdsect (UNIT *uptr, t_lba lba, uint8 *buf, t_seccnt * return SCPE_IOERR; } +static t_stat sim_vhd_disk_clearerr (UNIT *uptr) +{ +return SCPE_IOERR; +} + static t_stat sim_vhd_disk_wrsect (UNIT *uptr, t_lba lba, uint8 *buf, t_seccnt *sectswritten, t_seccnt sects) { return SCPE_IOERR; @@ -1873,7 +2033,10 @@ return NULL; /*++ This code follows the details specified in the "Virtual Hard Disk Image - Format Specification", Version 1.0 October 11, 2006. + Format Specification", Version 1.0 October 11, 2006. This format + specification is available for anyone to implement under the + "Microsoft Open Specification Promise" described at: + http://www.microsoft.com/interop/osp/default.mspx. --*/ typedef t_uint64 uint64; @@ -1894,7 +2057,7 @@ typedef struct _VHD_Footer { table displays the list of features. Any fields not listed are reserved. - Feature Value: + Feature Value: No features enabled 0x00000000 Temporary 0x00000001 Reserved 0x00000002 @@ -2167,19 +2330,9 @@ typedef struct _VHD_DynamicDiskHeader { #define VHD_BAT_FREE_ENTRY (0xFFFFFFFF) #define VHD_DATA_BLOCK_ALIGNMENT ((uint64)4096) /* Optimum when underlying storage has 4k sectors */ -static char *VHD_DiskTypes[] = - { - "None", /* 0 */ - "Reserved (deprecated)", /* 1 */ - "Fixed hard disk", /* 2 */ -#define VHD_DT_Fixed 2 - "Dynamic hard disk", /* 3 */ -#define VHD_DT_Dynamic 3 - "Differencing hard disk", /* 4 */ -#define VHD_DT_Differencing 4 - "Reserved (deprecated)", /* 5 */ - "Reserved (deprecated)", /* 6 */ - }; +#define VHD_DT_Fixed 2 /* Fixed hard disk */ +#define VHD_DT_Dynamic 3 /* Dynamic hard disk */ +#define VHD_DT_Differencing 4 /* Differencing hard disk */ static uint32 NtoHl(uint32 value); @@ -2296,7 +2449,7 @@ static int GetVHDFooter(const char *szVHDPath, VHD_Footer *sFooter, - VHD_DynamicDiskHeader *sDynamic, + VHD_DynamicDiskHeader *sDynamic, uint32 **aBAT, uint32 *ModifiedTimeStamp, char *szParentVHDPath, @@ -2320,13 +2473,14 @@ if (!File) { Return = errno; goto Return_Cleanup; } -if (ModifiedTimeStamp) +if (ModifiedTimeStamp) { if (stat (szVHDPath, &statb)) { Return = errno; goto Return_Cleanup; } else *ModifiedTimeStamp = NtoHl ((uint32)(statb.st_mtime-946684800)); + } position = sim_fsize_ex (File); if (((int64)position) == -1) { Return = errno; @@ -2388,9 +2542,8 @@ if ((sDynamic) && Return = errno; goto Return_Cleanup; } - if (aBAT) - { - *aBAT = malloc(512*((sizeof(**aBAT)*NtoHl(sDynamic->MaxTableEntries)+511)/512)); + if (aBAT) { + *aBAT = (uint32*) malloc(512*((sizeof(**aBAT)*NtoHl(sDynamic->MaxTableEntries)+511)/512)); if (ReadFilePosition(File, *aBAT, sizeof (**aBAT)*NtoHl(sDynamic->MaxTableEntries), @@ -2404,27 +2557,27 @@ if ((sDynamic) && VHD_Footer sParentFooter; memset (szParentVHDPath, '\0', ParentVHDPathSize); - if (NtoHl (sFooter->DiskType) == VHD_DT_Differencing) - { + if (NtoHl (sFooter->DiskType) == VHD_DT_Differencing) { size_t i, j; - for (j=0; j<8; ++j) - { + for (j=0; j<8; ++j) { uint8 *Pdata; - char ParentName[256]; - char CheckPath[256]; + uint32 PdataSize; + char ParentName[512]; + char CheckPath[512]; uint32 ParentModificationTime; if ('\0' == sDynamic->ParentLocatorEntries[j].PlatformCode[0]) continue; memset (ParentName, '\0', sizeof(ParentName)); memset (CheckPath, '\0', sizeof(CheckPath)); - Pdata = calloc (1, NtoHl(sDynamic->ParentLocatorEntries[j].PlatformDataSpace)+1); + PdataSize = NtoHl(sDynamic->ParentLocatorEntries[j].PlatformDataSpace); + Pdata = (uint8*) calloc (1, PdataSize+2); if (!Pdata) continue; if (ReadFilePosition(File, Pdata, - NtoHl (sDynamic->ParentLocatorEntries[j].PlatformDataSpace), + PdataSize, NULL, NtoHll (sDynamic->ParentLocatorEntries[j].PlatformDataOffset))) { free (Pdata); @@ -2440,14 +2593,15 @@ if ((sDynamic) && free (Pdata); if (0 == memcmp (sDynamic->ParentLocatorEntries[j].PlatformCode, "W2ku", 4)) strncpy (CheckPath, ParentName, sizeof (CheckPath)-1); - else - if (0 == memcmp (sDynamic->ParentLocatorEntries[j].PlatformCode, "W2ru", 4)) { - char *c; + else + if (0 == memcmp (sDynamic->ParentLocatorEntries[j].PlatformCode, "W2ru", 4)) { + const char *c; - if ((c = strrchr (szVHDPath, '/')) || (c = strrchr (szVHDPath, '\\'))) - memcpy (CheckPath, szVHDPath, c-szVHDPath+1); - strncpy (CheckPath+strlen(CheckPath), ParentName, sizeof (CheckPath)-(strlen (CheckPath)+1)); - } + if ((c = strrchr (szVHDPath, '\\'))) + memcpy (CheckPath, szVHDPath, c-szVHDPath+1); + strncpy (CheckPath+strlen(CheckPath), ParentName, sizeof (CheckPath)-(strlen (CheckPath)+1)); + } + VhdPathToHostPath (CheckPath, CheckPath, sizeof (CheckPath)); if ((0 == GetVHDFooter(CheckPath, &sParentFooter, NULL, @@ -2456,12 +2610,11 @@ if ((sDynamic) && NULL, 0)) && (0 == memcmp (sDynamic->ParentUniqueID, sParentFooter.UniqueID, sizeof (sParentFooter.UniqueID))) && - (sDynamic->ParentTimeStamp == ParentModificationTime)) - { + (sDynamic->ParentTimeStamp == ParentModificationTime)) { strncpy (szParentVHDPath, CheckPath, ParentVHDPathSize); break; } - } + } if (!szParentVHDPath) Return = EINVAL; /* File Corrupt */ } @@ -2552,25 +2705,43 @@ return (char *)(&hVHD->Footer.DriveType[0]); static FILE *sim_vhd_disk_open (const char *szVHDPath, const char *DesiredAccess) { - VHDHANDLE hVHD = calloc (1, sizeof(*hVHD)); + VHDHANDLE hVHD = (VHDHANDLE) calloc (1, sizeof(*hVHD)); int Status; if (!hVHD) return (FILE *)hVHD; - if (0 != (Status = GetVHDFooter (szVHDPath, - &hVHD->Footer, - &hVHD->Dynamic, - &hVHD->BAT, - NULL, - hVHD->ParentVHDPath, - sizeof (hVHD->ParentVHDPath)))) + Status = GetVHDFooter (szVHDPath, + &hVHD->Footer, + &hVHD->Dynamic, + &hVHD->BAT, + NULL, + hVHD->ParentVHDPath, + sizeof (hVHD->ParentVHDPath)); + if (Status) goto Cleanup_Return; if (NtoHl (hVHD->Footer.DiskType) == VHD_DT_Differencing) { + uint32 ParentModifiedTimeStamp; + VHD_Footer ParentFooter; + VHD_DynamicDiskHeader ParentDynamic; + hVHD->Parent = (VHDHANDLE)sim_vhd_disk_open (hVHD->ParentVHDPath, "rb"); if (!hVHD->Parent) { Status = errno; goto Cleanup_Return; } + Status = GetVHDFooter (hVHD->ParentVHDPath, + &ParentFooter, + &ParentDynamic, + NULL, + &ParentModifiedTimeStamp, + NULL, + 0); + if (Status) + goto Cleanup_Return; + if (ParentModifiedTimeStamp != hVHD->Dynamic.ParentTimeStamp) { + Status = EBADF; + goto Cleanup_Return; + } } if (hVHD->Footer.SavedState) { Status = EAGAIN; /* Busy */ @@ -2582,10 +2753,131 @@ static FILE *sim_vhd_disk_open (const char *szVHDPath, const char *DesiredAccess goto Cleanup_Return; } Cleanup_Return: + if (Status) { + sim_vhd_disk_close ((FILE *)hVHD); + hVHD = NULL; + } + errno = Status; + return (FILE *)hVHD; + } + +static t_stat +WriteVirtualDiskSectors(VHDHANDLE hVHD, + uint8 *buf, + t_seccnt sects, + t_seccnt *sectswritten, + uint32 SectorSize, + t_lba lba); + +static FILE *sim_vhd_disk_merge (const char *szVHDPath, char **ParentVHD) + { + VHDHANDLE hVHD = (VHDHANDLE) calloc (1, sizeof(*hVHD)); + VHDHANDLE Parent = NULL; + int Status; + uint32 SectorSize, SectorsPerBlock, BlockSize, BlockNumber, BitMapBytes, BitMapSectors, BlocksToMerge, NeededBlock; + uint64 BlockOffset; + size_t BytesRead; + t_seccnt SectorsWritten; + void *BlockData = NULL; + + if (!hVHD) + return (FILE *)hVHD; + if (0 != (Status = GetVHDFooter (szVHDPath, + &hVHD->Footer, + &hVHD->Dynamic, + &hVHD->BAT, + NULL, + hVHD->ParentVHDPath, + sizeof (hVHD->ParentVHDPath)))) + goto Cleanup_Return; + if (NtoHl (hVHD->Footer.DiskType) != VHD_DT_Differencing) { + Status = EINVAL; + goto Cleanup_Return; + } + if (hVHD->Footer.SavedState) { + Status = EAGAIN; /* Busy */ + goto Cleanup_Return; + } + SectorSize = 512; + BlockSize = NtoHl (hVHD->Dynamic.BlockSize); + BlockData = malloc (BlockSize*SectorSize); + if (NULL == BlockData) { + Status = errno; + goto Cleanup_Return; + } + Parent = (VHDHANDLE)sim_vhd_disk_open (hVHD->ParentVHDPath, "rb+"); + if (!Parent) { + Status = errno; + goto Cleanup_Return; + } + hVHD->File = sim_fopen (szVHDPath, "rb"); + if (!hVHD->File) { + Status = errno; + goto Cleanup_Return; + } + SectorsPerBlock = NtoHl (hVHD->Dynamic.BlockSize)/SectorSize; + BitMapBytes = (7+(NtoHl (hVHD->Dynamic.BlockSize)/SectorSize))/8; + BitMapSectors = (BitMapBytes+SectorSize-1)/SectorSize; + for (BlockNumber=BlocksToMerge=0; BlockNumber< NtoHl (hVHD->Dynamic.MaxTableEntries); ++BlockNumber) { + if (hVHD->BAT[BlockNumber] == VHD_BAT_FREE_ENTRY) + continue; + ++BlocksToMerge; + } + if (!sim_quiet) + printf ("Merging %s\ninto %s\n", szVHDPath, hVHD->ParentVHDPath); + for (BlockNumber=NeededBlock=0; BlockNumber < NtoHl (hVHD->Dynamic.MaxTableEntries); ++BlockNumber) { + uint32 BlockSectors = SectorsPerBlock; + + if (hVHD->BAT[BlockNumber] == VHD_BAT_FREE_ENTRY) + continue; + ++NeededBlock; + BlockOffset = SectorSize*((uint64)(NtoHl (hVHD->BAT[BlockNumber]) + BitMapSectors)); + if ((BlockNumber*SectorsPerBlock + BlockSectors) > ((uint64)NtoHll (hVHD->Footer.CurrentSize))/SectorSize) + BlockSectors = (uint32)(((uint64)NtoHll (hVHD->Footer.CurrentSize))/SectorSize - (BlockNumber*SectorsPerBlock)); + if (ReadFilePosition(hVHD->File, + BlockData, + SectorSize*BlockSectors, + &BytesRead, + BlockOffset)) + break; + if (WriteVirtualDiskSectors (Parent, + (uint8*)BlockData, + BlockSectors, + &SectorsWritten, + SectorSize, + SectorsPerBlock*BlockNumber)) + break; + if (!sim_quiet) + printf ("Merged %dMB. %d%% complete.\r", (int)(((float)NeededBlock*SectorsPerBlock)*SectorSize/1000000), (int)((NeededBlock*100)/BlocksToMerge)); + hVHD->BAT[BlockNumber] = VHD_BAT_FREE_ENTRY; + } + if (BlockNumber < NtoHl (hVHD->Dynamic.MaxTableEntries)) { + Status = errno; + } + else { + Status = 0; + if (!sim_quiet) + printf ("Merged %dMB. 100%% complete.\n", (int)(((float)NeededBlock*SectorsPerBlock)*SectorSize/1000000)); + fclose (hVHD->File); + hVHD->File = NULL; + remove (szVHDPath); + *ParentVHD = (char*) malloc (strlen (hVHD->ParentVHDPath)+1); + strcpy (*ParentVHD, hVHD->ParentVHDPath); + } +Cleanup_Return: + free (BlockData); + if (hVHD->File) + fclose (hVHD->File); if (Status) { free (hVHD->BAT); free (hVHD); hVHD = NULL; + sim_vhd_disk_close ((FILE *)Parent); + } + else { + free (hVHD->BAT); + free (hVHD); + hVHD = Parent; } errno = Status; return (FILE *)hVHD; @@ -2649,7 +2941,7 @@ RPC_STATUS (RPC_ENTRY *UuidCreate_c) (void *); if (!UuidCreate_c) { - HMODULE hDll; + HINSTANCE hDll; hDll = LoadLibraryA("rpcrt4.dll"); UuidCreate_c = (RPC_STATUS (RPC_ENTRY *) (void *))GetProcAddress(hDll, "UuidCreate"); } @@ -2671,7 +2963,7 @@ void *handle; #define __STR(tok) __STR_QUOTE(tok) handle = dlopen("libuuid." __STR(HAVE_DLOPEN), RTLD_NOW|RTLD_GLOBAL); if (handle) - uuid_generate_c = dlsym(handle, "uuid_generate"); + uuid_generate_c = (void (*)(void *))((size_t)dlsym(handle, "uuid_generate")); if (uuid_generate_c) uuid_generate_c(uuidaddr); else @@ -2702,6 +2994,7 @@ FILE *File = NULL; uint32 Status = 0; uint32 BytesPerSector = 512; uint64 SizeInBytes = ((uint64)SizeInSectors)*BytesPerSector; +uint64 TableOffset; uint32 MaxTableEntries; VHDHANDLE hVHD = NULL; @@ -2709,7 +3002,8 @@ if (SizeInBytes > ((uint64)(1024*1024*1024))*2040) { Status = EFBIG; goto Cleanup_Return; } -if (NULL != (File = sim_fopen (szVHDPath, "rb"))) { +File = sim_fopen (szVHDPath, "rb"); +if (File) { fclose (File); File = NULL; Status = EEXIST; @@ -2763,7 +3057,7 @@ if (1) { /* CHS Calculation */ { sectorsPerTrack = 31; heads = 16; - cylinderTimesHeads = totalSectors / sectorsPerTrack; + cylinderTimesHeads = totalSectors / sectorsPerTrack; } if (cylinderTimesHeads >= (heads * 1024)) { @@ -2791,7 +3085,10 @@ if (bFixedVHD) { memset (&Dynamic, 0, sizeof(Dynamic)); memcpy (Dynamic.Cookie, "cxsparse", 8); Dynamic.DataOffset = NtoHll (0xFFFFFFFFFFFFFFFFLL); -Dynamic.TableOffset = NtoHll ((uint64)(BytesPerSector*((sizeof(Dynamic)+sizeof(Footer)+BytesPerSector-1)/BytesPerSector))); +TableOffset = (uint64)(BytesPerSector*((sizeof(Dynamic)+sizeof(Footer)+BytesPerSector-1)/BytesPerSector)); +TableOffset += VHD_DATA_BLOCK_ALIGNMENT-1; +TableOffset &= ~(VHD_DATA_BLOCK_ALIGNMENT-1); +Dynamic.TableOffset = NtoHll (TableOffset); Dynamic.HeaderVersion = NtoHl (0x00010000); if (0 == BlockSize) BlockSize = 2*1024*1024; @@ -2799,7 +3096,7 @@ Dynamic.BlockSize = NtoHl (BlockSize); MaxTableEntries = (uint32)((SizeInBytes+BlockSize-1)/BlockSize); Dynamic.MaxTableEntries = NtoHl (MaxTableEntries); Dynamic.Checksum = NtoHl (CalculateVhdFooterChecksum(&Dynamic, sizeof(Dynamic))); -BAT = malloc (BytesPerSector*((MaxTableEntries*sizeof(*BAT)+BytesPerSector-1)/BytesPerSector)); +BAT = (uint32*) malloc (BytesPerSector*((MaxTableEntries*sizeof(*BAT)+BytesPerSector-1)/BytesPerSector)); memset (BAT, 0, BytesPerSector*((MaxTableEntries*sizeof(*BAT)+BytesPerSector-1)/BytesPerSector)); for (i=0; i +#endif static void ExpandToFullPath (const char *szFileSpec, char *szFullFileSpecBuffer, size_t BufferSize) { +char *c; #ifdef _WIN32 +for (c = strchr (szFullFileSpecBuffer, '/'); c; c = strchr (szFullFileSpecBuffer, '/')) + *c = '\\'; GetFullPathNameA (szFileSpec, (DWORD)BufferSize, szFullFileSpecBuffer, NULL); +for (c = strchr (szFullFileSpecBuffer, '\\'); c; c = strchr (szFullFileSpecBuffer, '\\')) + *c = '/'; #else -strncpy (szFullFileSpecBuffer, szFileSpec, BufferSize); +char buffer[PATH_MAX]; +char *wd = getcwd(buffer, PATH_MAX); + +if ((szFileSpec[0] != '/') || (strchr (szFileSpec, ':'))) + snprintf (szFullFileSpecBuffer, BufferSize, "%s/%s", wd, szFileSpec); +else + strncpy (szFullFileSpecBuffer, szFileSpec, BufferSize); +if ((c = strstr (szFullFileSpecBuffer, "]/"))) + strcpy (c+1, c+2); +memset (szFullFileSpecBuffer + strlen (szFullFileSpecBuffer), 0, BufferSize - strlen (szFullFileSpecBuffer)); #endif } +static char * +HostPathToVhdPath (const char *szHostPath, + char *szVhdPath, + size_t VhdPathSize) +{ +char *c, *d; + +strncpy (szVhdPath, szHostPath, VhdPathSize-1); +szVhdPath[VhdPathSize-1] = '\0'; +if ((c = strrchr (szVhdPath, ']'))) { + *c = '\0'; + if (!(d = strchr (szVhdPath, '['))) + return d; + *d = '/'; + while ((d = strchr (d, '.'))) + *d = '/'; + *c = '/'; + } +while ((c = strchr (szVhdPath, '/'))) + *c = '\\'; +for (c = strstr (szVhdPath, "\\.\\"); c; c = strstr (szVhdPath, "\\.\\")) + strcpy (c, c+2); +for (c = strstr (szVhdPath, "\\\\"); c; c = strstr (szVhdPath, "\\\\")) + strcpy (c, c+1); +while ((c = strstr (szVhdPath, "\\..\\"))) { + *c = '\0'; + d = strrchr (szVhdPath, '\\'); + if (d) + strcpy (d, c+3); + else + return d; + } +memset (szVhdPath + strlen (szVhdPath), 0, VhdPathSize - strlen (szVhdPath)); +return szVhdPath; +} + +static char * +VhdPathToHostPath (const char *szVhdPath, + char *szHostPath, + size_t HostPathSize) +{ +char *c; +char *d = szHostPath; + +strncpy (szHostPath, szVhdPath, HostPathSize-1); +szHostPath[HostPathSize-1] = '\0'; +#if defined(VMS) +c = strchr (szVhdPath, ':'); +if (*(c+1) != '\\') + return NULL; +*(c+1) = '['; +d = strrchr (c+2, '\\'); +if (d) { + *d = ']'; + while ((d = strrchr (c+2, '\\'))) + *d = '.'; + } +else + return NULL; +#else +while ((c = strchr (d, '\\'))) + *c = '/'; +#endif +memset (szHostPath + strlen (szHostPath), 0, HostPathSize - strlen (szHostPath)); +return szHostPath; +} + static VHDHANDLE CreateDifferencingVirtualDisk(const char *szVHDPath, const char *szParentVHDPath) @@ -2878,19 +3259,19 @@ uint32 ParentTimeStamp; uint32 Status = 0; char *RelativeParentVHDPath = NULL; char *FullParentVHDPath = NULL; -char *RelativeParentVHDPathBuffer = NULL; -char *FullParentVHDPathBuffer = NULL; +char *RelativeParentVHDPathUnicode = NULL; +char *FullParentVHDPathUnicode = NULL; char *FullVHDPath = NULL; size_t i, RelativeMatch, UpDirectories, LocatorsWritten = 0; int64 LocatorPosition; -if (0 != (Status = GetVHDFooter (szParentVHDPath, - &ParentFooter, - &ParentDynamic, - NULL, - &ParentTimeStamp, - NULL, - 0))) +if ((Status = GetVHDFooter (szParentVHDPath, + &ParentFooter, + &ParentDynamic, + NULL, + &ParentTimeStamp, + NULL, + 0))) goto Cleanup_Return; hVHD = CreateVirtualDisk (szVHDPath, (uint32)(NtoHll(ParentFooter.CurrentSize)/BytesPerSector), @@ -2900,27 +3281,30 @@ if (!hVHD) { Status = errno; goto Cleanup_Return; } -LocatorPosition = NtoHll (hVHD->Dynamic.TableOffset)+BytesPerSector*((NtoHl (hVHD->Dynamic.MaxTableEntries)*sizeof(*hVHD->BAT)+BytesPerSector-1)/BytesPerSector); +LocatorPosition = ((sizeof (hVHD->Footer) + BytesPerSector - 1)/BytesPerSector + (sizeof (hVHD->Dynamic) + BytesPerSector - 1)/BytesPerSector)*BytesPerSector; hVHD->Dynamic.Checksum = 0; -RelativeParentVHDPath = calloc (1, BytesPerSector+1); -FullParentVHDPath = calloc (1, BytesPerSector+1); -RelativeParentVHDPathBuffer = calloc (1, BytesPerSector); -FullParentVHDPathBuffer = calloc (1, BytesPerSector); -FullVHDPath = calloc (1, BytesPerSector+1); +RelativeParentVHDPath = (char*) calloc (1, BytesPerSector+2); +FullParentVHDPath = (char*) calloc (1, BytesPerSector+2); +RelativeParentVHDPathUnicode = (char*) calloc (1, BytesPerSector+2); +FullParentVHDPathUnicode = (char*) calloc (1, BytesPerSector+2); +FullVHDPath = (char*) calloc (1, BytesPerSector+2); ExpandToFullPath (szParentVHDPath, FullParentVHDPath, BytesPerSector); +HostPathToVhdPath (FullParentVHDPath, FullParentVHDPath, BytesPerSector); for (i=0; i < strlen (FullParentVHDPath); i++) - hVHD->Dynamic.ParentUnicodeName[i*2+1] = FullParentVHDPath[i]; + hVHD->Dynamic.ParentUnicodeName[i*2+1] = FullParentVHDPath[i]; /* Big Endian Unicode */ for (i=0; i < strlen (FullParentVHDPath); i++) - FullParentVHDPathBuffer[i*2] = FullParentVHDPath[i]; + FullParentVHDPathUnicode[i*2] = FullParentVHDPath[i]; /* Little Endian Unicode */ ExpandToFullPath (szVHDPath, FullVHDPath, BytesPerSector); +HostPathToVhdPath (FullVHDPath, FullVHDPath, BytesPerSector); for (i=0, RelativeMatch=UpDirectories=0; iDynamic.ParentTimeStamp = ParentTimeStamp; memcpy (hVHD->Dynamic.ParentUniqueID, ParentFooter.UniqueID, sizeof (hVHD->Dynamic.ParentUniqueID)); hVHD->Dynamic.ParentLocatorEntries[7].PlatformDataSpace = NtoHl (BytesPerSector); +hVHD->Dynamic.ParentLocatorEntries[7].Reserved = 0; hVHD->Dynamic.ParentLocatorEntries[7].PlatformDataOffset = NtoHll (LocatorPosition+LocatorsWritten*BytesPerSector); ++LocatorsWritten; +memcpy (hVHD->Dynamic.ParentLocatorEntries[6].PlatformCode, "Wi2k", 4); hVHD->Dynamic.ParentLocatorEntries[6].PlatformDataSpace = NtoHl (BytesPerSector); +hVHD->Dynamic.ParentLocatorEntries[6].Reserved = 0; hVHD->Dynamic.ParentLocatorEntries[6].PlatformDataOffset = NtoHll (LocatorPosition+LocatorsWritten*BytesPerSector); ++LocatorsWritten; if (RelativeMatch) { + memcpy (hVHD->Dynamic.ParentLocatorEntries[7].PlatformCode, "Wi2r", 4); + hVHD->Dynamic.ParentLocatorEntries[7].PlatformDataLength = NtoHl ((uint32)(strlen(RelativeParentVHDPath))); memcpy (hVHD->Dynamic.ParentLocatorEntries[5].PlatformCode, "W2ru", 4); hVHD->Dynamic.ParentLocatorEntries[5].PlatformDataSpace = NtoHl (BytesPerSector); hVHD->Dynamic.ParentLocatorEntries[5].PlatformDataLength = NtoHl ((uint32)(2*strlen(RelativeParentVHDPath))); @@ -2976,52 +3365,43 @@ if (WriteFilePosition (hVHD->File, Status = errno; goto Cleanup_Return; } -LocatorsWritten = 0; -if (RelativeMatch) { - if (WriteFilePosition (hVHD->File, - RelativeParentVHDPath, - BytesPerSector, - NULL, - LocatorPosition+LocatorsWritten*BytesPerSector)) { - Status = errno; - goto Cleanup_Return; - } - ++LocatorsWritten; +if (WriteFilePosition (hVHD->File, + &hVHD->Footer, + sizeof (hVHD->Footer), + NULL, + NtoHll (hVHD->Dynamic.TableOffset)+BytesPerSector*((NtoHl (hVHD->Dynamic.MaxTableEntries)*sizeof(*hVHD->BAT)+BytesPerSector-1)/BytesPerSector))) { + Status = errno; + goto Cleanup_Return; + } +if (WriteFilePosition (hVHD->File, + RelativeParentVHDPath, + BytesPerSector, + NULL, + NtoHll (hVHD->Dynamic.ParentLocatorEntries[7].PlatformDataOffset))) { + Status = errno; + goto Cleanup_Return; } if (WriteFilePosition (hVHD->File, FullParentVHDPath, BytesPerSector, NULL, - LocatorPosition+LocatorsWritten*BytesPerSector)) { + NtoHll (hVHD->Dynamic.ParentLocatorEntries[6].PlatformDataOffset))) { Status = errno; goto Cleanup_Return; } -++LocatorsWritten; -if (RelativeMatch) { - if (WriteFilePosition (hVHD->File, - RelativeParentVHDPathBuffer, - BytesPerSector, - NULL, - LocatorPosition+LocatorsWritten*BytesPerSector)) { - Status = errno; - goto Cleanup_Return; - } - ++LocatorsWritten; - } if (WriteFilePosition (hVHD->File, - FullParentVHDPathBuffer, + RelativeParentVHDPathUnicode, BytesPerSector, NULL, - LocatorPosition+LocatorsWritten*BytesPerSector)) { + NtoHll (hVHD->Dynamic.ParentLocatorEntries[5].PlatformDataOffset))) { Status = errno; goto Cleanup_Return; } -++LocatorsWritten; if (WriteFilePosition (hVHD->File, - &hVHD->Footer, - sizeof(hVHD->Footer), + FullParentVHDPathUnicode, + BytesPerSector, NULL, - LocatorPosition+LocatorsWritten*BytesPerSector)) { + NtoHll (hVHD->Dynamic.ParentLocatorEntries[4].PlatformDataOffset))) { Status = errno; goto Cleanup_Return; } @@ -3029,8 +3409,8 @@ if (WriteFilePosition (hVHD->File, Cleanup_Return: free (RelativeParentVHDPath); free (FullParentVHDPath); -free (RelativeParentVHDPathBuffer); -free (FullParentVHDPathBuffer); +free (RelativeParentVHDPathUnicode); +free (FullParentVHDPathUnicode); free (FullVHDPath); sim_vhd_disk_close ((FILE *)hVHD); hVHD = NULL; @@ -3068,7 +3448,7 @@ ReadVirtualDiskSectors(VHDHANDLE hVHD, uint64 BlockOffset = ((uint64)lba)*SectorSize; uint32 BlocksRead = 0; uint32 SectorsInRead; -size_t BytesRead; +size_t BytesRead = 0; if (!hVHD || (hVHD->File == NULL)) { errno = EBADF; @@ -3099,14 +3479,13 @@ while (sects) { uint32 BitMapBytes = (7+(NtoHl (hVHD->Dynamic.BlockSize)/SectorSize))/8; uint32 BitMapSectors = (BitMapBytes+SectorSize-1)/SectorSize; - SectorsInRead = 1; + SectorsInRead = SectorsPerBlock - lba%SectorsPerBlock; + if (SectorsInRead > sects) + SectorsInRead = sects; if (hVHD->BAT[BlockNumber] == VHD_BAT_FREE_ENTRY) { if (!hVHD->Parent) - memset (buf, 0, SectorSize); + memset (buf, 0, SectorSize*SectorsInRead); else { - SectorsInRead = SectorsPerBlock - lba%SectorsPerBlock; - if (SectorsInRead > sects) - SectorsInRead = sects; if (ReadVirtualDiskSectors(hVHD->Parent, buf, SectorsInRead, @@ -3121,9 +3500,6 @@ while (sects) { } else { BlockOffset = SectorSize*((uint64)(NtoHl (hVHD->BAT[BlockNumber]) + lba%SectorsPerBlock + BitMapSectors)); - SectorsInRead = SectorsPerBlock - lba%SectorsPerBlock; - if (SectorsInRead > sects) - SectorsInRead = sects; if (ReadFilePosition(hVHD->File, buf, SectorsInRead*SectorSize, @@ -3152,6 +3528,14 @@ struct disk_context *ctx = (struct disk_context *)uptr->disk_ctx; return ReadVirtualDiskSectors(hVHD, buf, sects, sectsread, ctx->sector_size, lba); } +static t_stat sim_vhd_disk_clearerr (UNIT *uptr) +{ +VHDHANDLE hVHD = (VHDHANDLE)uptr->fileref; + +clearerr (hVHD->File); +return SCPE_OK; +} + static t_bool BufferIsZeros(void *Buffer, size_t BufferSize) { @@ -3164,33 +3548,6 @@ for (i=0; iFile) { errno = EBADF; @@ -3240,8 +3597,13 @@ while (sects) { } SectorsInWrite = 1; if (hVHD->BAT[BlockNumber] == VHD_BAT_FREE_ENTRY) { - void *BitMap = NULL; + uint8 *BitMap = NULL; + uint32 BitMapBufferSize = VHD_DATA_BLOCK_ALIGNMENT; + uint8 *BitMapBuffer = NULL; void *BlockData = NULL; + uint8 *BATUpdateBufferAddress; + uint32 BATUpdateBufferSize; + uint64 BATUpdateStorageAddress; if (!hVHD->Parent && BufferIsZeros(buf, SectorSize)) goto IO_Done; @@ -3249,28 +3611,51 @@ while (sects) { BlockOffset = sim_fsize_ex (hVHD->File); if (((int64)BlockOffset) == -1) return SCPE_IOERR; - BitMap = malloc(BitMapSectors*SectorSize); + if (BitMapSectors*SectorSize > BitMapBufferSize) + BitMapBufferSize = BitMapSectors*SectorSize; + BitMapBuffer = (uint8 *)calloc(1, BitMapBufferSize + SectorSize*SectorsPerBlock); + if (BitMapBufferSize > BitMapSectors*SectorSize) + BitMap = BitMapBuffer + BitMapBufferSize-BitMapBytes; + else + BitMap = BitMapBuffer; memset(BitMap, 0xFF, BitMapBytes); BlockOffset -= sizeof(hVHD->Footer); - /* align the data portion of the block to the desired alignment */ - /* compute the address of the data portion of the block */ - BlockOffset += BitMapSectors*SectorSize; - /* round up this address to the desired alignment */ - BlockOffset += VHD_DATA_BLOCK_ALIGNMENT-1; - BlockOffset &= ~(VHD_DATA_BLOCK_ALIGNMENT-1); - /* the actual block address is the beginning of the block bitmap */ + if (0 == (BlockOffset & ~(VHD_DATA_BLOCK_ALIGNMENT-1))) + { // Already aligned, so use padded BitMapBuffer + if (WriteFilePosition(hVHD->File, + BitMapBuffer, + BitMapBufferSize + SectorSize*SectorsPerBlock, + NULL, + BlockOffset)) { + free (BitMapBuffer); + return SCPE_IOERR; + } + BlockOffset += BitMapBufferSize; + } + else + { + // align the data portion of the block to the desired alignment + // compute the address of the data portion of the block + BlockOffset += BitMapSectors*SectorSize; + // round up this address to the desired alignment + BlockOffset += VHD_DATA_BLOCK_ALIGNMENT-1; + BlockOffset &= ~(VHD_DATA_BLOCK_ALIGNMENT-1); + BlockOffset -= BitMapSectors*SectorSize; + if (WriteFilePosition(hVHD->File, + BitMap, + SectorSize * (BitMapSectors + SectorsPerBlock), + NULL, + BlockOffset)) { + free (BitMapBuffer); + return SCPE_IOERR; + } + BlockOffset += BitMapSectors*SectorSize; + } + free(BitMapBuffer); + BitMapBuffer = BitMap = NULL; + /* the BAT block address is the beginning of the block bitmap */ BlockOffset -= BitMapSectors*SectorSize; hVHD->BAT[BlockNumber] = NtoHl((uint32)(BlockOffset/SectorSize)); - if (WriteFilePosition(hVHD->File, - BitMap, - BitMapSectors*SectorSize, - NULL, - BlockOffset)) { - free (BitMap); - return SCPE_IOERR; - } - free(BitMap); - BitMap = NULL; BlockOffset += SectorSize * (SectorsPerBlock + BitMapSectors); if (WriteFilePosition(hVHD->File, &hVHD->Footer, @@ -3278,25 +3663,37 @@ while (sects) { NULL, BlockOffset)) goto Fatal_IO_Error; + /* Write back just the aligned sector which contains the updated BAT entry */ + BATUpdateBufferAddress = ((uint8 *)hVHD->BAT) + + (((((size_t)&hVHD->BAT[BlockNumber]) - (size_t)hVHD->BAT)/VHD_DATA_BLOCK_ALIGNMENT)*VHD_DATA_BLOCK_ALIGNMENT); + BATUpdateBufferSize = VHD_DATA_BLOCK_ALIGNMENT; + if ((size_t)(BATUpdateBufferAddress - (uint8 *)hVHD->BAT + BATUpdateBufferSize) > 512*((sizeof(*hVHD->BAT)*NtoHl(hVHD->Dynamic.MaxTableEntries) + 511)/512)) + BATUpdateBufferSize = 512*((sizeof(*hVHD->BAT)*NtoHl(hVHD->Dynamic.MaxTableEntries) + 511)/512) - (BATUpdateBufferAddress - ((uint8 *)hVHD->BAT)); + BATUpdateStorageAddress = NtoHll(hVHD->Dynamic.TableOffset) + BATUpdateBufferAddress - ((uint8 *)hVHD->BAT); if (WriteFilePosition(hVHD->File, - hVHD->BAT, - SectorSize*((sizeof(*hVHD->BAT)*NtoHl(hVHD->Dynamic.MaxTableEntries)+511)/512), + BATUpdateBufferAddress, + BATUpdateBufferSize, NULL, - NtoHll(hVHD->Dynamic.TableOffset))) + BATUpdateStorageAddress)) goto Fatal_IO_Error; if (hVHD->Parent) { /* Need to populate data block contents from parent VHD */ + uint32 BlockSectors = SectorsPerBlock; + BlockData = malloc(SectorsPerBlock*SectorSize); + + if (((lba/SectorsPerBlock)*SectorsPerBlock + BlockSectors) > ((uint64)NtoHll (hVHD->Footer.CurrentSize))/SectorSize) + BlockSectors = (uint32)(((uint64)NtoHll (hVHD->Footer.CurrentSize))/SectorSize - (lba/SectorsPerBlock)*SectorsPerBlock); if (ReadVirtualDiskSectors(hVHD->Parent, - BlockData, - SectorsPerBlock, + (uint8*) BlockData, + BlockSectors, NULL, SectorSize, (lba/SectorsPerBlock)*SectorsPerBlock)) goto Fatal_IO_Error; if (WriteVirtualDiskSectors(hVHD, - BlockData, - SectorsPerBlock, + (uint8*) BlockData, + BlockSectors, NULL, SectorSize, (lba/SectorsPerBlock)*SectorsPerBlock)) diff --git a/sim_disk.h b/sim_disk.h index 1295ac91..b9b850d6 100644 --- a/sim_disk.h +++ b/sim_disk.h @@ -67,6 +67,7 @@ typedef void (*DISK_PCALLBACK)(UNIT *unit, t_stat status); t_stat sim_disk_attach (UNIT *uptr, char *cptr, size_t sector_size, size_t xfer_element_size, t_bool dontautosize, uint32 debugbit, const char *drivetype, uint32 pdp11_tracksize, int completion_delay); t_stat sim_disk_detach (UNIT *uptr); +t_stat sim_disk_attach_help(FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr); t_stat sim_disk_rdsect (UNIT *uptr, t_lba lba, uint8 *buf, t_seccnt *sectsread, t_seccnt sects); t_stat sim_disk_rdsect_a (UNIT *uptr, t_lba lba, uint8 *buf, t_seccnt *sectsread, t_seccnt sects, DISK_PCALLBACK callback); t_stat sim_disk_wrsect (UNIT *uptr, t_lba lba, uint8 *buf, t_seccnt *sectswritten, t_seccnt sects); @@ -79,6 +80,8 @@ t_stat sim_disk_show_capac (FILE *st, UNIT *uptr, int32 val, void *desc); t_stat sim_disk_set_asynch (UNIT *uptr, int latency); t_stat sim_disk_clr_asynch (UNIT *uptr); t_stat sim_disk_reset (UNIT *uptr); +t_stat sim_disk_perror (UNIT *uptr, const char *msg); +t_stat sim_disk_clearerr (UNIT *uptr); t_bool sim_disk_isavailable (UNIT *uptr); t_bool sim_disk_isavailable_a (UNIT *uptr, DISK_PCALLBACK callback); t_bool sim_disk_wrp (UNIT *uptr); diff --git a/sim_ether.c b/sim_ether.c index 90d3bcd7..7de8e155 100644 --- a/sim_ether.c +++ b/sim_ether.c @@ -366,8 +366,6 @@ #include "sim_ether.h" #include "sim_sock.h" -extern FILE *sim_log; - /*============================================================================*/ /* OS-independant ethernet routines */ @@ -528,6 +526,7 @@ void eth_packet_trace_ex(ETH_DEV* dev, const uint8 *msg, int len, char* txt, int int i, same, group, sidx, oidx; char outbuf[80], strbuf[18]; static char hex[] = "0123456789ABCDEF"; + for (i=same=0; i 0) && (0 == memcmp(&msg[i], &msg[i-16], 16))) { ++same; @@ -551,8 +550,9 @@ void eth_packet_trace_ex(ETH_DEV* dev, const uint8 *msg, int len, char* txt, int strbuf[sidx] = '\0'; sim_debug(reason, dev->dptr, "%04X%-48s %s\n", i, outbuf, strbuf); } - if (same > 0) + if (same > 0) { sim_debug(reason, dev->dptr, "%04X thru %04X same as above\n", i-(16*same), len-1); + } } } } @@ -567,7 +567,8 @@ char* eth_getname(int number, char* name) ETH_LIST list[ETH_MAX_DEVICE]; int count = eth_devices(ETH_MAX_DEVICE, list); - if (count <= number) return NULL; + if ((number < 0) || (count <= number)) + return NULL; strcpy(name, list[number].name); return name; } @@ -666,6 +667,7 @@ void eth_zero(ETH_DEV* dev) static ETH_DEV **eth_open_devices = NULL; static int eth_open_device_count = 0; +#if defined (USE_NETWORK) || defined (USE_SHARED) static void _eth_add_to_open_list (ETH_DEV* dev) { eth_open_devices = realloc(eth_open_devices, (eth_open_device_count+1)*sizeof(*eth_open_devices)); @@ -684,6 +686,7 @@ for (i=0; i min) min = len; for (i=0; iname, desc); + if (d) + fprintf(st, " %-7s%s (%s)\n", eth_open_devices[i]->dptr->name, eth_open_devices[i]->dptr->units[0].filename, d); + else + fprintf(st, " %-7s%s\n", eth_open_devices[i]->dptr->name, eth_open_devices[i]->dptr->units[0].filename); + } } if (eth_open_device_count) { int i; @@ -757,6 +773,14 @@ t_stat ethq_destroy(ETH_QUE* que) void ethq_clear(ETH_QUE* que) { + int i; + + /* free up any extended packets */ + for (i=0; imax; ++i) + if (que->item[i].packet.oversize) { + free (que->item[i].packet.oversize); + que->item[i].packet.oversize = NULL; + } /* clear packet array */ memset(que->item, 0, sizeof(struct eth_item) * que->max); /* clear rest of structure */ @@ -768,6 +792,8 @@ void ethq_remove(ETH_QUE* que) struct eth_item* item = &que->item[que->head]; if (que->count) { + if (item->packet.oversize) + free (item->packet.oversize); memset(item, 0, sizeof(struct eth_item)); if (++que->head == que->max) que->head = 0; @@ -775,7 +801,7 @@ void ethq_remove(ETH_QUE* que) } } -void ethq_insert_data(ETH_QUE* que, int32 type, const uint8 *data, int used, int len, int crc_len, const uint8 *crc_data, int32 status) +void ethq_insert_data(ETH_QUE* que, int32 type, const uint8 *data, int used, size_t len, size_t crc_len, const uint8 *crc_data, int32 status) { struct eth_item* item; @@ -804,15 +830,23 @@ void ethq_insert_data(ETH_QUE* que, int32 type, const uint8 *data, int used, int item->packet.len = len; item->packet.used = used; item->packet.crc_len = crc_len; - memcpy(item->packet.msg, data, ((len > crc_len) ? len : crc_len)); - if (crc_data && (crc_len > len)) - memcpy(&item->packet.msg[len], crc_data, ETH_CRC_SIZE); + if (len <= sizeof (item->packet.msg)) { + memcpy(item->packet.msg, data, ((len > crc_len) ? len : crc_len)); + if (crc_data && (crc_len > len)) + memcpy(&item->packet.msg[len], crc_data, ETH_CRC_SIZE); + } + else { + item->packet.oversize = realloc (item->packet.oversize, ((len > crc_len) ? len : crc_len)); + memcpy(item->packet.oversize, data, ((len > crc_len) ? len : crc_len)); + if (crc_data && (crc_len > len)) + memcpy(&item->packet.oversize[len], crc_data, ETH_CRC_SIZE); + } item->packet.status = status; } void ethq_insert(ETH_QUE* que, int32 type, ETH_PACK* pack, int32 status) { - ethq_insert_data(que, type, pack->msg, pack->used, pack->len, pack->crc_len, NULL, status); +ethq_insert_data(que, type, pack->oversize ? pack->oversize : pack->msg, pack->used, pack->len, pack->crc_len, NULL, status); } /*============================================================================*/ @@ -824,6 +858,12 @@ t_stat eth_open(ETH_DEV* dev, char* name, DEVICE* dptr, uint32 dbit) {return SCPE_NOFNC;} t_stat eth_close (ETH_DEV* dev) {return SCPE_NOFNC;} +t_stat eth_attach_help(FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr) + { + fprintf (st, "%s attach help\n\n", dptr->name); + fprintf (st, "This simulator was not built with ethernet device support\n"); + return SCPE_OK; + } t_stat eth_check_address_conflict (ETH_DEV* dev, ETH_MAC* const mac) {return SCPE_NOFNC;} @@ -942,11 +982,11 @@ static char* (*p_pcap_lib_version) (void); /* load function pointer from DLL */ typedef int (*_func)(); -void load_function(char* function, _func* func_ptr) { +static void load_function(char* function, _func* func_ptr) { #ifdef _WIN32 - *func_ptr = (_func)GetProcAddress(hLib, function); + *func_ptr = (_func)((size_t)GetProcAddress(hLib, function)); #else - *func_ptr = (_func)dlsym(hLib, function); + *func_ptr = (_func)((size_t)dlsym(hLib, function)); #endif if (*func_ptr == 0) { char* msg = "Eth: Failed to find function '%s' in %s\r\n"; @@ -1393,7 +1433,7 @@ static void eth_get_nic_hw_addr(ETH_DEV* dev, char *devname) memset(command, 0, sizeof(command)); for (i=0; patterns[i] && (0 == dev->have_host_nic_phy_addr); ++i) { snprintf(command, sizeof(command)-1, "ifconfig %s | %s >NIC.hwaddr", devname, patterns[i]); - system(command); + (void)system(command); if (NULL != (f = fopen("NIC.hwaddr", "r"))) { while (0 == dev->have_host_nic_phy_addr) { if (fgets(command, sizeof(command)-1, f)) { @@ -1403,7 +1443,7 @@ static void eth_get_nic_hw_addr(ETH_DEV* dev, char *devname) while (p1) { p2 = strchr(p1+1, ':'); if (p2 <= p1+3) { - int mac_bytes[6]; + unsigned int mac_bytes[6]; if (6 == sscanf(p1-2, "%02x:%02x:%02x:%02x:%02x:%02x", &mac_bytes[0], &mac_bytes[1], &mac_bytes[2], &mac_bytes[3], &mac_bytes[4], &mac_bytes[5])) { dev->host_nic_phy_hw_addr[0] = mac_bytes[0]; dev->host_nic_phy_hw_addr[1] = mac_bytes[1]; @@ -1451,7 +1491,7 @@ HANDLE hWait = pcap_getevent ((pcap_t*)dev->handle); #else int sel_ret; int do_select = 0; -int select_fd; +int select_fd = 0; switch (dev->eth_api) { case ETH_API_PCAP: @@ -1679,7 +1719,6 @@ memset(errbuf, 0, sizeof(errbuf)); if (0 == strncmp("tap:", savname, 4)) { int tun = -1; /* TUN/TAP Socket */ int on = 1; - char dev_name[64] = ""; #if defined(USE_TAP_NETWORK) if (!strcmp(savname, "tap:tapN")) { @@ -1715,41 +1754,45 @@ if (0 == strncmp("tap:", savname, 4)) { else strncpy(errbuf, strerror(errno), sizeof(errbuf)-1); #elif defined(USE_BSDTUNTAP) && defined(USE_TAP_NETWORK) - snprintf(dev_name, sizeof(dev_name)-1, "/dev/%s", savname+4); - dev_name[sizeof(dev_name)-1] = '\0'; + if (1) { + char dev_name[64] = ""; - if ((tun = open(dev_name, O_RDWR)) >= 0) { - if (ioctl(tun, FIONBIO, &on)) { - strncpy(errbuf, strerror(errno), sizeof(errbuf)-1); - close(tun); - } - else { - dev->fd_handle = tun; - strcpy(savname, savname+4); - } -#if defined (__APPLE__) - if (1) { - struct ifreq ifr; - int s; + snprintf(dev_name, sizeof(dev_name)-1, "/dev/%s", savname+4); + dev_name[sizeof(dev_name)-1] = '\0'; - memset (&ifr, 0, sizeof(ifr)); - ifr.ifr_addr.sa_family = AF_INET; - strncpy(ifr.ifr_name, savname, sizeof(ifr.ifr_name)); - if ((s = socket(AF_INET, SOCK_DGRAM, 0)) >= 0) { - if (ioctl(s, SIOCGIFFLAGS, (caddr_t)&ifr) >= 0) { - ifr.ifr_flags |= IFF_UP; - if (ioctl(s, SIOCSIFFLAGS, (caddr_t)&ifr)) { - strncpy(errbuf, strerror(errno), sizeof(errbuf)-1); - close(tun); - } - } - close(s); + if ((tun = open(dev_name, O_RDWR)) >= 0) { + if (ioctl(tun, FIONBIO, &on)) { + strncpy(errbuf, strerror(errno), sizeof(errbuf)-1); + close(tun); + } + else { + dev->fd_handle = tun; + strcpy(savname, savname+4); + } +#if defined (__APPLE__) + if (1) { + struct ifreq ifr; + int s; + + memset (&ifr, 0, sizeof(ifr)); + ifr.ifr_addr.sa_family = AF_INET; + strncpy(ifr.ifr_name, savname, sizeof(ifr.ifr_name)); + if ((s = socket(AF_INET, SOCK_DGRAM, 0)) >= 0) { + if (ioctl(s, SIOCGIFFLAGS, (caddr_t)&ifr) >= 0) { + ifr.ifr_flags |= IFF_UP; + if (ioctl(s, SIOCSIFFLAGS, (caddr_t)&ifr)) { + strncpy(errbuf, strerror(errno), sizeof(errbuf)-1); + close(tun); + } + } + close(s); + } } - } #endif - } - else - strncpy(errbuf, strerror(errno), sizeof(errbuf)-1); + } + else + strncpy(errbuf, strerror(errno), sizeof(errbuf)-1); + } #else strncpy(errbuf, "No support for tap: devices", sizeof(errbuf)-1); #endif /* !defined(__linux) && !defined(USE_BSDTUNTAP) */ @@ -1926,6 +1969,20 @@ _eth_remove_from_open_list (dev); return SCPE_OK; } +t_stat eth_attach_help(FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr) +{ +fprintf (st, "%s attach help\n\n", dptr->name); +fprintf (st, " sim> SHOW ETHERNET\n"); +fprintf (st, " libpcap version 1.0.0\n"); +fprintf (st, " ETH devices:\n"); +fprintf (st, " eth0 en0 (No description available)\n"); +fprintf (st, " eth1 tap:tapN (Integrated Tun/Tap support)\n"); +fprintf (st, " sim> ATTACH %s eth0\n\n", dptr->name); +fprintf (st, "or equivalently:\n\n"); +fprintf (st, " sim> ATTACH %s en0\n\n", dptr->name); +return SCPE_OK; +} + t_stat eth_check_address_conflict (ETH_DEV* dev, ETH_MAC* const mac) { @@ -2098,13 +2155,13 @@ if ((packet->len >= ETH_MIN_PACKET) && (packet->len <= ETH_MAX_PACKET)) { break; #ifdef USE_TAP_NETWORK case ETH_API_TAP: - status = ((packet->len == write(dev->fd_handle, (void *)packet->msg, packet->len)) ? 0 : -1); + status = (((int)packet->len == write(dev->fd_handle, (void *)packet->msg, packet->len)) ? 0 : -1); break; #endif #ifdef USE_VDE_NETWORK case ETH_API_VDE: status = vde_send((VDECONN*)dev->handle, (void *)packet->msg, packet->len, 0); - if ((status == packet->len) || (status == 0)) + if ((status == (int)packet->len) || (status == 0)) status = 0; else if ((status == -1) && ((errno == EAGAIN) || (errno == EWOULDBLOCK))) @@ -2200,6 +2257,7 @@ key ^= 0x3f; return (hash[key>>3] & (1 << (key&0x7))); } +#if 0 static int _eth_hash_validate(ETH_MAC *MultiCastList, int count, ETH_MULTIHASH hash) { @@ -2251,6 +2309,7 @@ ETH_MULTIHASH thash = {0x01, 0x40, 0x00, 0x00, 0x48, 0x88, 0x40, 0x00}; _eth_hash_validate(tMacs, sizeof(tMacs)/sizeof(tMacs[0]), thash); } +#endif /* The IP header */ struct IPHeader { @@ -2918,10 +2977,12 @@ if (dev->dptr->dctrl & dev->dbit) { eth_mac_fmt(&dev->filter_address[i], mac); sim_debug(dev->dbit, dev->dptr, " Addr[%d]: %s\n", i, mac); } - if (dev->all_multicast) + if (dev->all_multicast) { sim_debug(dev->dbit, dev->dptr, "All Multicast\n"); - if (dev->promiscuous) + } + if (dev->promiscuous) { sim_debug(dev->dbit, dev->dptr, "Promiscuous\n"); + } } /* setup BPF filters and other fields to minimize packet delivery */ @@ -3159,6 +3220,7 @@ pcap_if_t* dev; char errbuf[PCAP_ERRBUF_SIZE]; memset(list, 0, max*sizeof(*list)); +errbuf[0] = '\0'; /* retrieve the device list */ if (pcap_findalldevs(&alldevs, errbuf) == -1) { char* msg = "Eth: error in pcap_findalldevs: %s\r\n"; @@ -3184,6 +3246,13 @@ else { /* Add any host specific devices and/or validate those already found */ i = eth_host_devices(i, max, list); +/* If no devices were found and an error message was left in the buffer, display it */ +if ((i == 0) && (errbuf[0])) { + char* msg = "Eth: pcap_findalldevs warning: %s\r\n"; + printf (msg, errbuf); + if (sim_log) fprintf (sim_log, msg, errbuf); + } + /* return device count */ return i; } diff --git a/sim_ether.h b/sim_ether.h index 7706ffef..c11db144 100644 --- a/sim_ether.h +++ b/sim_ether.h @@ -173,6 +173,7 @@ struct eth_packet { uint8 msg[ETH_FRAME_SIZE]; /* ethernet frame (message) */ + uint8 *oversize; /* oversized frame (message) */ uint32 len; /* packet length without CRC */ uint32 used; /* bytes processed (used in packet chaining) */ int status; /* transmit/receive status */ @@ -265,6 +266,7 @@ typedef struct eth_device ETH_DEV; t_stat eth_open (ETH_DEV* dev, char* name, /* open ethernet interface */ DEVICE* dptr, uint32 dbit); t_stat eth_close (ETH_DEV* dev); /* close ethernet interface */ +t_stat eth_attach_help(FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr); t_stat eth_write (ETH_DEV* dev, ETH_PACK* packet, /* write sychronous packet; */ ETH_PCALLBACK routine); /* callback when done */ int eth_read (ETH_DEV* dev, ETH_PACK* packet, /* read single packet; */ @@ -303,8 +305,8 @@ void ethq_remove (ETH_QUE* que); /* remove item from FIFO void ethq_insert (ETH_QUE* que, int32 type, /* insert item into FIFO queue */ ETH_PACK* packet, int32 status); void ethq_insert_data(ETH_QUE* que, int32 type, /* insert item into FIFO queue */ - const uint8 *data, int used, int len, - int crc_len, const uint8 *crc_data, int32 status); + const uint8 *data, int used, size_t len, + size_t crc_len, const uint8 *crc_data, int32 status); t_stat ethq_destroy(ETH_QUE* que); /* release FIFO queue */ diff --git a/sim_fio.h b/sim_fio.h index a6985426..b0440426 100644 --- a/sim_fio.h +++ b/sim_fio.h @@ -49,5 +49,7 @@ t_addr sim_fsize_name_ex (char *fname); void sim_buf_swap_data (void *bptr, size_t size, size_t count); void sim_buf_copy_swapped (void *dptr, void *bptr, size_t size, size_t count); +extern uint32 sim_taddr_64; +extern int32 sim_end; #endif diff --git a/sim_rev.h b/sim_rev.h index 38c1e47c..09290e73 100644 --- a/sim_rev.h +++ b/sim_rev.h @@ -27,12 +27,38 @@ #ifndef _SIM_REV_H_ #define _SIM_REV_H_ 0 -#define SIM_MAJOR 3 -#define SIM_MINOR 9 +#ifndef SIM_MAJOR +#define SIM_MAJOR 4 +#endif +#ifndef SIM_MINOR +#define SIM_MINOR 0 +#endif +#ifndef SIM_PATCH #define SIM_PATCH 0 +#endif +#ifndef SIM_DELTA #define SIM_DELTA 0 +#endif -/* V3.9 revision history +#ifndef SIM_VERSION_MODE +#define SIM_VERSION_MODE "Beta" +#endif + +#if defined(SIM_NEED_GIT_COMMIT_ID) +#include ".git-commit-id.h" +#endif + +/* + The comment section below reflects the manual editing process which was in place + prior to the use of the git source control system on at https://gihub.com/simh/simh + + Details about all future fixes will be visible in the source control system's + history. + +*/ + +/* + V3.9 revision history patch date module(s) and fix(es) @@ -191,6 +217,9 @@ patch date module(s) and fix(es) - fixed backspace over tapemark not to set EOR (Van Snyder) - added no rewind option (Van Snyder) + i1401_sys.c: + - fixed misuse of & instead of && in decode (Peter Schorn) + pdp1_cpu.c: - fixed misuse of & instead of && in Ea_ch (Michael Bloom) @@ -204,7 +233,8 @@ patch date module(s) and fix(es) - fixed priority of PIRQ vs IO; added INT_INTERNALn pdp11_io.c: - - fixed Qbus interrupts to treat all IO devices as BR4 + - fixed Qbus interrupts to treat all IO devices (except clock) as BR4 + - fixed order of int_internal (Jordi Guillaumes i Pons) ppd11_rf.c - fixed bug in updating mem addr extension (Peter Schorn) @@ -319,7 +349,7 @@ patch date module(s) and fix(es) - fixed bug in scan function decode (Peter Schorn) vax_cpu.c: - - revised idle design Mark Pizzolato) + - revised idle design (Mark Pizzolato) - fixed bug in SET CPU IDLE - fixed failure to clear PSL in BPT, XFC diff --git a/sim_serial.c b/sim_serial.c new file mode 100644 index 00000000..eab7d9e8 --- /dev/null +++ b/sim_serial.c @@ -0,0 +1,1818 @@ +/* sim_serial.c: OS-dependent serial port routines + + Copyright (c) 2008, J. David Bryan + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHOR BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name of the author shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from the author. + + The author gratefully acknowledges the assistance of Holger Veit with the + UNIX-specific code and testing. + + 07-Oct-08 JDB [serial] Created file + + + This module provides OS-dependent routines to access serial ports on the host + machine. The terminal multiplexer library uses these routines to provide + serial connections to simulated terminal interfaces. + + Currently, the module supports Windows and UNIX. Use on other systems + returns error codes indicating that the functions failed, inhibiting serial + port support in SIMH. + + The following routines are provided: + + sim_open_serial open a serial port + sim_config_serial change baud rate and character framing configuration + sim_control_serial manipulate and/or return the modem bits on a serial port + sim_read_serial read from a serial port + sim_write_serial write to a serial port + sim_close_serial close a serial port + sim_show_serial shows the available host serial ports + + + The calling sequences are as follows: + + + SERHANDLE sim_open_serial (char *name) + -------------------------------------- + + The serial port referenced by the OS-dependent "name" is opened. If the open + is successful, and "name" refers to a serial port on the host system, then a + handle to the port is returned. If not, then the value INVALID_HANDLE is + returned. + + + t_stat sim_config_serial (SERHANDLE port, const char *config) + ------------------------------------------------------------- + + The baud rate and framing parameters (character size, parity, and number of + stop bits) of the serial port associated with "port" are set. If any + "config" field value is unsupported by the host system, or if the combination + of values (e.g., baud rate and number of stop bits) is unsupported, SCPE_ARG + is returned. If the configuration is successful, SCPE_OK is returned. + + + sim_control_serial (SERHANDLE port, int32 bits_to_set, int32 bits_to_clear, int32 *incoming_bits) + ------------------------------------------------------------------------------------------------- + + The DTR and RTS line of the serial port is set or cleared as indicated in + the respective bits_to_set or bits_to_clear parameters. If the + incoming_bits parameter is not NULL, then the modem status bits DCD, RNG, + DSR and CTS are returned. + + If unreasonable or nonsense bits_to_set or bits_to_clear bits are + specified, then the return status is SCPE_ARG; + If an error occurs, SCPE_IOERR is returned. + + + int32 sim_read_serial (SERHANDLE port, char *buffer, int32 count, char *brk) + ---------------------------------------------------------------------------- + + A non-blocking read is issued for the serial port indicated by "port" to get + at most "count" bytes into the string "buffer". If a serial line break was + detected during the read, the variable pointed to by "brk" is set to 1. If + the read is successful, the actual number of characters read is returned. If + no characters were available, then the value 0 is returned. If an error + occurs, then the value -1 is returned. + + + int32 sim_write_serial (SERHANDLE port, char *buffer, int32 count) + ------------------------------------------------------------------ + + A write is issued to the serial port indicated by "port" to put "count" + characters from "buffer". If the write is successful, the actual number of + characters written is returned. If an error occurs, then the value -1 is + returned. + + + void sim_close_serial (SERHANDLE port) + -------------------------------------- + + The serial port indicated by "port" is closed. + + + int sim_serial_devices (int max, SERIAL_LIST* list) + --------------------------------------------------- + + enumerates the available host serial ports + + + t_stat sim_show_serial (FILE* st, DEVICE *dptr, UNIT* uptr, int32 val, void* desc) + --------------------------------- + + displays the available host serial ports + +*/ + + +#include "sim_defs.h" +#include "sim_serial.h" +#include "sim_tmxr.h" + +#include + +#define SER_DEV_NAME_MAX 256 /* maximum device name size */ +#define SER_DEV_DESC_MAX 256 /* maximum device description size */ +#define SER_DEV_CONFIG_MAX 64 /* maximum device config size */ +#define SER_MAX_DEVICE 64 /* maximum serial devices */ + +typedef struct serial_list { + char name[SER_DEV_NAME_MAX]; + char desc[SER_DEV_DESC_MAX]; + } SERIAL_LIST; + +typedef struct serial_config { /* serial port configuration */ + uint32 baudrate; /* baud rate */ + uint32 charsize; /* character size in bits */ + char parity; /* parity (N/O/E/M/S) */ + uint32 stopbits; /* 0/1/2 stop bits (0 implies 1.5) */ + } SERCONFIG; + +static int sim_serial_os_devices (int max, SERIAL_LIST* list); +static SERHANDLE sim_open_os_serial (char *name); +static void sim_close_os_serial (SERHANDLE port); +static t_stat sim_config_os_serial (SERHANDLE port, SERCONFIG config); + + +static struct open_serial_device { + SERHANDLE port; + TMLN *line; + char name[SER_DEV_NAME_MAX]; + char config[SER_DEV_CONFIG_MAX]; + } *serial_open_devices = NULL; +static int serial_open_device_count = 0; + +static struct open_serial_device *_get_open_device (SERHANDLE port) +{ +int i; + +for (i=0; iname, b->name); +} + +static int sim_serial_devices (int max, SERIAL_LIST *list) +{ +int i, j, ports = sim_serial_os_devices(max, list); + +/* Open ports may not show up in the list returned by sim_serial_os_devices + so we add the open ports to the list removing duplicates before sorting + the resulting list */ + +for (i=0; i= max) + break; + strcpy(list[ports].name, serial_open_devices[i].name); + strcpy(list[ports].desc, serial_open_devices[i].config); + ++ports; + } +if (ports) /* Order the list returned alphabetically by the port name */ + qsort (list, ports, sizeof(list[0]), _serial_name_compare); +return ports; +} + +static char* sim_serial_getname (int number, char* name) +{ +SERIAL_LIST list[SER_MAX_DEVICE]; +int count = sim_serial_devices(SER_MAX_DEVICE, list); + +if (count <= number) + return NULL; +strcpy(name, list[number].name); +return name; +} + +static char* sim_serial_getname_bydesc (char* desc, char* name) +{ +SERIAL_LIST list[SER_MAX_DEVICE]; +int count = sim_serial_devices(SER_MAX_DEVICE, list); +int i; +size_t j=strlen(desc); + +for (i=0; i s2) + return 1; + if (s1 == 0) + return 0; +} +return 0; +} + +static char* sim_serial_getname_byname (char* name, char* temp) +{ +SERIAL_LIST list[SER_MAX_DEVICE]; +int count = sim_serial_devices(SER_MAX_DEVICE, list); +size_t n; +int i, found; + +found = 0; +n = strlen(name); +for (i=0; i min) + min = len; + for (i=0; imp->dptr->name, (int)(serial_open_devices[i].line->mp->ldsc-serial_open_devices[i].line), + serial_open_devices[i].line->destination, d ? " {" : "", d ? d : "", d ? ")" : "", serial_open_devices[i].line->serconfig); + } + } +return SCPE_OK; +} + +SERHANDLE sim_open_serial (char *name, TMLN *lp, t_stat *stat) +{ +char temp1[1024], devname [1024]; +char *savname = name; +SERHANDLE port = INVALID_HANDLE; +char *config; +t_stat status; + +config = get_glyph_nc (name, devname, ';'); /* separate port name from optional config params */ + +if ((config == NULL) || (*config == '\0')) + config = "9600-8N1"; + +if (stat) + *stat = SCPE_OK; + +/* translate name of type "serX" to real device name */ +if ((strlen(devname) <= 5) + && (tolower(devname[0]) == 's') + && (tolower(devname[1]) == 'e') + && (tolower(devname[2]) == 'r') + && (isdigit(devname[3])) + && (isdigit(devname[4]) || (devname[4] == '\0')) + ) { + int num = atoi(&devname[3]); + savname = sim_serial_getname(num, temp1); + if (savname == NULL) { /* didn't translate */ + if (stat) + *stat = SCPE_OPENERR; + return port; + } + } +else { + /* are they trying to use device description? */ + savname = sim_serial_getname_bydesc(devname, temp1); + if (savname == NULL) { /* didn't translate */ + /* probably is not serX and has no description */ + savname = sim_serial_getname_byname(devname, temp1); + if (savname == NULL) /* didn't translate */ + savname = devname; + } + } + +port = sim_open_os_serial (savname); + +if (port == INVALID_HANDLE) { + if (stat) + *stat = SCPE_OPENERR; + return port; + } + +status = sim_config_serial (port, config); /* set serial configuration */ + +if (status != SCPE_OK) { /* port configuration error? */ + sim_close_serial (port); /* close the port */ + if (stat) + *stat = status; + port = INVALID_HANDLE; /* report error */ + } + +if ((port != INVALID_HANDLE) && (*config) && (lp)) { + lp->serconfig = realloc (lp->serconfig, 1 + strlen (config)); + strcpy (lp->serconfig, config); + } +if (port != INVALID_HANDLE) + _serial_add_to_open_list (port, lp, savname, config); + +return port; +} + +void sim_close_serial (SERHANDLE port) +{ +sim_close_os_serial (port); +_serial_remove_from_open_list (port); +} + +t_stat sim_config_serial (SERHANDLE port, const char *sconfig) +{ +const char *pptr; +char *sptr, *tptr; +SERCONFIG config = { 0 }; +t_bool arg_error = FALSE; +t_stat r; +struct open_serial_device *dev; + +if ((sconfig == NULL) || (*sconfig == '\0')) + sconfig = "9600-8N1"; /* default settings */ +pptr = sconfig; + +config.baudrate = (uint32)strtotv (pptr, &sptr, 10); /* parse baud rate */ +arg_error = (pptr == sptr); /* check for bad argument */ + +if (*sptr) /* separator present? */ + sptr++; /* skip it */ + +config.charsize = (uint32)strtotv (sptr, &tptr, 10); /* parse character size */ +arg_error = arg_error || (sptr == tptr); /* check for bad argument */ + +if (*tptr) /* parity character present? */ + config.parity = toupper (*tptr++); /* save parity character */ + +config.stopbits = (uint32)strtotv (tptr, &sptr, 10); /* parse number of stop bits */ +arg_error = arg_error || (tptr == sptr); /* check for bad argument */ + +if (arg_error) /* bad conversions? */ + return SCPE_ARG; /* report argument error */ +if (strcmp (sptr, ".5") == 0) /* 1.5 stop bits requested? */ + config.stopbits = 0; /* code request */ + +r = sim_config_os_serial (port, config); +dev = _get_open_device (port); +if (dev) { + dev->line->serconfig = realloc (dev->line->serconfig, 1 + strlen (sconfig)); + strcpy (dev->line->serconfig, sconfig); + } +return r; +} + +#if defined (_WIN32) + +/* Windows serial implementation */ + +/* Enumerate the available serial ports. + + The serial port names are extracted from the appropriate place in the + windows registry (HKLM\HARDWARE\DEVICEMAP\SERIALCOMM\). The resulting + list is sorted alphabetically by device name (COMn). The device description + is set to the OS internal name for the COM device. + +*/ + +static int sim_serial_os_devices (int max, SERIAL_LIST* list) +{ +int ports = 0; +HKEY hSERIALCOMM; + +memset(list, 0, max*sizeof(*list)); +if (RegOpenKeyExA(HKEY_LOCAL_MACHINE, "HARDWARE\\DEVICEMAP\\SERIALCOMM", 0, KEY_QUERY_VALUE, &hSERIALCOMM) == ERROR_SUCCESS) { + DWORD dwIndex = 0; + DWORD dwType; + DWORD dwValueNameSize = sizeof(list[ports].desc); + DWORD dwDataSize = sizeof(list[ports].name); + + /* Enumerate all the values underneath HKEY_LOCAL_MACHINE\HARDWARE\DEVICEMAP\SERIALCOMM */ + while (RegEnumValueA(hSERIALCOMM, dwIndex, list[ports].desc, &dwValueNameSize, NULL, &dwType, (BYTE *)list[ports].name, &dwDataSize) == ERROR_SUCCESS) { + /* String values with non-zero size are the interesting ones */ + if ((dwType == REG_SZ) && (dwDataSize > 0)) + if (ports < max) + ++ports; + else + break; + /* Besure to clear the working entry before trying again */ + memset(list[ports].name, 0, sizeof(list[ports].name)); + memset(list[ports].desc, 0, sizeof(list[ports].desc)); + dwValueNameSize = sizeof(list[ports].desc); + dwDataSize = sizeof(list[ports].name); + ++dwIndex; + } + RegCloseKey(hSERIALCOMM); + } +return ports; +} + +/* Open a serial port. + + The serial port designated by "name" is opened, and the handle to the port is + returned. If an error occurs, INVALID_HANDLE is returned instead. After + opening, the port is configured with the default communication parameters + established by the system, and the timeouts are set for immediate return on a + read request to enable polling. + + Implementation notes: + + 1. We call "GetDefaultCommConfig" to obtain the default communication + parameters for the specified port. If the name does not refer to a + communications port (serial or parallel), the function fails. + + 2. There is no way to limit "CreateFile" just to serial ports, so we must + check after the port is opened. The "GetCommState" routine will return + an error if the handle does not refer to a serial port. + + 3. Calling "GetDefaultCommConfig" for a serial port returns a structure + containing a DCB. This contains the default parameters. However, some + of the DCB fields are not set correctly, so we cannot use this directly + in a call to "SetCommState". Instead, we must copy the fields of + interest to a DCB retrieved from a call to "GetCommState". +*/ + +SERHANDLE sim_open_os_serial (char *name) +{ +SERHANDLE port; +DCB dcb; +COMMCONFIG commdefault; +DWORD error; +DWORD commsize = sizeof (commdefault); +COMMTIMEOUTS cto; + +if (!GetDefaultCommConfig (name, &commdefault, &commsize)) { /* get default comm parameters */ + error = GetLastError (); /* function failed; get error */ + + if (error != ERROR_INVALID_PARAMETER) /* not a communications port name? */ + sim_error_serial ("GetDefaultCommConfig", (int) error); /* no, so report unexpected error */ + + return INVALID_HANDLE; /* indicate bad port name */ + } + +port = CreateFile (name, GENERIC_READ | GENERIC_WRITE, /* open the port */ + 0, NULL, OPEN_EXISTING, 0, 0); + +if (port == INVALID_HANDLE_VALUE) { /* open failed? */ + error = GetLastError (); /* get error code */ + + if ((error != ERROR_FILE_NOT_FOUND) && /* bad filename? */ + (error != ERROR_ACCESS_DENIED)) /* already open? */ + sim_error_serial ("CreateFile", (int) error); /* no, so report unexpected error */ + + return INVALID_HANDLE; /* indicate bad port name */ + } + +if (!GetCommState (port, &dcb)) { /* get the current comm parameters */ + error = GetLastError (); /* function failed; get error */ + + if (error != ERROR_INVALID_PARAMETER) /* not a serial port name? */ + sim_error_serial ("GetCommState", (int) error); /* no, so report unexpected error */ + + CloseHandle (port); /* close the port */ + return INVALID_HANDLE; /* and indicate bad port name */ + } + +dcb.BaudRate = commdefault.dcb.BaudRate; /* copy default parameters of interest */ +dcb.Parity = commdefault.dcb.Parity; +dcb.ByteSize = commdefault.dcb.ByteSize; +dcb.StopBits = commdefault.dcb.StopBits; +dcb.fOutX = commdefault.dcb.fOutX; +dcb.fInX = commdefault.dcb.fInX; + +dcb.fDtrControl = DTR_CONTROL_DISABLE; /* disable DTR initially until poll connects */ + +if (!SetCommState (port, &dcb)) { /* configure the port with default parameters */ + sim_error_serial ("SetCommState", /* function failed; report unexpected error */ + (int) GetLastError ()); + CloseHandle (port); /* close port */ + return INVALID_HANDLE; /* and indicate failure to caller */ + } + +cto.ReadIntervalTimeout = MAXDWORD; /* set port to return immediately on read */ +cto.ReadTotalTimeoutMultiplier = 0; /* i.e., to enable polling */ +cto.ReadTotalTimeoutConstant = 0; +cto.WriteTotalTimeoutMultiplier = 0; +cto.WriteTotalTimeoutConstant = 0; + +if (!SetCommTimeouts (port, &cto)) { /* configure port timeouts */ + sim_error_serial ("SetCommTimeouts", /* function failed; report unexpected error */ + (int) GetLastError ()); + CloseHandle (port); /* close port */ + return INVALID_HANDLE; /* and indicate failure to caller */ + } + +return port; /* return port handle on success */ +} + + +/* Configure a serial port. + + Port parameters are configured as specified in the "config" structure. If + "config" contains an invalid configuration value, or if the host system + rejects the configuration (e.g., by requesting an unsupported combination of + character size and stop bits), SCPE_ARG is returned to the caller. If an + unexpected error occurs, SCPE_IOERR is returned. If the configuration + succeeds, SCPE_OK is returned. + + Implementation notes: + + 1. We do not enable input parity checking, as the multiplexer library has no + way of communicating parity errors back to the target simulator. + + 2. A zero value for the "stopbits" field of the "config" structure implies + 1.5 stop bits. +*/ + +t_stat sim_config_os_serial (SERHANDLE port, SERCONFIG config) +{ +static const struct { + char parity; + BYTE parity_code; + } parity_map [] = + { { 'E', EVENPARITY }, { 'M', MARKPARITY }, { 'N', NOPARITY }, + { 'O', ODDPARITY }, { 'S', SPACEPARITY } }; + +static const int32 parity_count = sizeof (parity_map) / sizeof (parity_map [0]); + +DCB dcb; +DWORD error; +int32 i; + +if (!GetCommState (port, &dcb)) { /* get the current comm parameters */ + sim_error_serial ("GetCommState", /* function failed; report unexpected error */ + (int) GetLastError ()); + return SCPE_IOERR; /* return failure status */ + } + +dcb.BaudRate = config.baudrate; /* assign baud rate */ + +if (config.charsize >= 5 && config.charsize <= 8) /* character size OK? */ + dcb.ByteSize = config.charsize; /* assign character size */ +else + return SCPE_ARG; /* not a valid size */ + +for (i = 0; i < parity_count; i++) /* assign parity */ + if (config.parity == parity_map [i].parity) { /* match mapping value? */ + dcb.Parity = parity_map [i].parity_code; /* assign corresponding code */ + break; + } + +if (i == parity_count) /* parity assigned? */ + return SCPE_ARG; /* not a valid parity specifier */ + +if (config.stopbits == 1) /* assign stop bits */ + dcb.StopBits = ONESTOPBIT; +else if (config.stopbits == 2) + dcb.StopBits = TWOSTOPBITS; +else if (config.stopbits == 0) /* 0 implies 1.5 stop bits */ + dcb.StopBits = ONE5STOPBITS; +else + return SCPE_ARG; /* not a valid number of stop bits */ + +if (!SetCommState (port, &dcb)) { /* set the configuration */ + error = GetLastError (); /* check for error */ + + if (error == ERROR_INVALID_PARAMETER) /* invalid configuration? */ + return SCPE_ARG; /* report as argument error */ + + sim_error_serial ("SetCommState", (int) error); /* function failed; report unexpected error */ + return SCPE_IOERR; /* return failure status */ + } + +return SCPE_OK; /* return success status */ +} + + +/* Control a serial port. + + The DTR and RTS line of the serial port is set or cleared as indicated in + the respective bits_to_set or bits_to_clear parameters. If the + incoming_bits parameter is not NULL, then the modem status bits DCD, RNG, + DSR and CTS are returned. + + If unreasonable or nonsense bits_to_set or bits_to_clear bits are + specified, then the return status is SCPE_ARG; + If an error occurs, SCPE_IOERR is returned. +*/ + +t_stat sim_control_serial (SERHANDLE port, int32 bits_to_set, int32 bits_to_clear, int32 *incoming_bits) +{ +if ((bits_to_set & ~(TMXR_MDM_OUTGOING)) || /* Assure only settable bits */ + (bits_to_clear & ~(TMXR_MDM_OUTGOING)) || + (bits_to_set & bits_to_clear)) /* and can't set and clear the same bits */ + return SCPE_ARG; +if (bits_to_set&TMXR_MDM_DTR) + if (!EscapeCommFunction (port, SETDTR)) { + sim_error_serial ("EscapeCommFunction", (int) GetLastError ()); + return SCPE_IOERR; + } +if (bits_to_clear&TMXR_MDM_DTR) + if (!EscapeCommFunction (port, CLRDTR)) { + sim_error_serial ("EscapeCommFunction", (int) GetLastError ()); + return SCPE_IOERR; + } +if (bits_to_set&TMXR_MDM_RTS) + if (!EscapeCommFunction (port, SETRTS)) { + sim_error_serial ("EscapeCommFunction", (int) GetLastError ()); + return SCPE_IOERR; + } +if (bits_to_clear&TMXR_MDM_RTS) + if (!EscapeCommFunction (port, CLRRTS)) { + sim_error_serial ("EscapeCommFunction", (int) GetLastError ()); + return SCPE_IOERR; + } +if (incoming_bits) { + DWORD ModemStat; + if (GetCommModemStatus (port, &ModemStat)) { + sim_error_serial ("GetCommModemStatus", (int) GetLastError ()); + return SCPE_IOERR; + } + *incoming_bits = ((ModemStat&MS_CTS_ON) ? TMXR_MDM_CTS : 0) | + ((ModemStat&MS_DSR_ON) ? TMXR_MDM_DSR : 0) | + ((ModemStat&MS_RING_ON) ? TMXR_MDM_RNG : 0) | + ((ModemStat&MS_RLSD_ON) ? TMXR_MDM_DCD : 0); + } +return SCPE_OK; +} + + +/* Read from a serial port. + + The port is checked for available characters. If any are present, they are + copied to the passed buffer, and the count of characters is returned. If no + characters are available, 0 is returned. If an error occurs, -1 is returned. + If a BREAK is detected on the communications line, the corresponding flag in + the "brk" array is set. + + Implementation notes: + + 1. The "ClearCommError" function will set the CE_BREAK flag in the returned + errors value if a BREAK has occurred. However, we do not know where in + the serial stream it happened, as CE_BREAK isn't associated with a + specific character. Because the "brk" array does want a flag associated + with a specific character, we guess at the proper location by setting + the "brk" entry corresponding to the first NUL in the character stream. + If no NUL is present, then the "brk" entry associated with the first + character is set. +*/ + +int32 sim_read_serial (SERHANDLE port, char *buffer, int32 count, char *brk) +{ +DWORD read; +DWORD commerrors; +COMSTAT cs; +char *bptr; + +if (!ClearCommError (port, &commerrors, &cs)) { /* get the comm error flags */ + sim_error_serial ("ClearCommError", /* function failed; report unexpected error */ + (int) GetLastError ()); + return -1; /* return failure to caller */ + } + +if (!ReadFile (port, (LPVOID) buffer, /* read any available characters */ + (DWORD) count, &read, NULL)) { + sim_error_serial ("ReadFile", /* function failed; report unexpected error */ + (int) GetLastError ()); + return -1; /* return failure to caller */ + } + +if (commerrors & CE_BREAK) { /* was a BREAK detected? */ + bptr = (char *) memchr (buffer, 0, read); /* search for the first NUL in the buffer */ + + if (bptr) /* was one found? */ + brk = brk + (bptr - buffer); /* calculate corresponding position */ + + *brk = 1; /* set the BREAK flag */ + } + +return read; /* return the number of characters read */ +} + + +/* Write to a serial port. + + "Count" characters are written from "buffer" to the serial port. The actual + number of characters written to the port is returned. If an error occurred + on writing, -1 is returned. +*/ + +int32 sim_write_serial (SERHANDLE port, char *buffer, int32 count) +{ +DWORD written; + +if (!WriteFile (port, (LPVOID) buffer, /* write the buffer to the serial port */ + (DWORD) count, &written, NULL)) { + sim_error_serial ("WriteFile", /* function failed; report unexpected error */ + (int) GetLastError ()); + return -1; /* return failure to caller */ + } +else + return written; /* return number of characters written */ +} + + +/* Close a serial port. + + The serial port is closed. Errors are ignored. +*/ + +void sim_close_os_serial (SERHANDLE port) +{ +CloseHandle (port); /* close the port */ +return; +} + + + +#elif defined (__unix__) || defined(__APPLE__) + +#if defined(__linux__) +#include +#include +#include +#include +#endif /* __linux__ */ + +/* UNIX implementation */ + +/* Enumerate the available serial ports. + + The serial port names generated by attempting to open /dev/ttyS0 thru + /dev/ttyS63 and /dev/ttyUSB0 thru /dev/ttyUSB63 and /dev/tty.serial0 + thru /dev/tty.serial63. Ones we can open and are ttys (as determined + by isatty()) are added to the list. The list is sorted alphabetically + by device name. + +*/ + +static int sim_serial_os_devices (int max, SERIAL_LIST* list) +{ +int i; +int port; +int ports = 0; + +memset(list, 0, max*sizeof(*list)); +#if defined(__linux__) +if (1) { + struct dirent **namelist; + int n; + struct stat st; + + n = scandir("/sys/class/tty/", &namelist, NULL, NULL); + + while (n--) { + if (strcmp(namelist[n]->d_name, ".") && + strcmp(namelist[n]->d_name, "..")) { + char path[1024], devicepath[1024], driverpath[1024]; + + sprintf (path, "/sys/class/tty/%s", namelist[n]->d_name); + sprintf (devicepath, "/sys/class/tty/%s/device", namelist[n]->d_name); + sprintf (driverpath, "/sys/class/tty/%s/device/driver", namelist[n]->d_name); + if ((lstat(devicepath, &st) == 0) && S_ISLNK(st.st_mode)) { + char buffer[1024]; + + memset (buffer, 0, sizeof(buffer)); + if (readlink(driverpath, buffer, sizeof(buffer)) > 0) { + sprintf (list[ports].name, "/dev/%s", basename (path)); + port = open (list[ports].name, O_RDWR | O_NOCTTY | O_NONBLOCK); /* open the port */ + if (port != -1) { /* open OK? */ + if (isatty (port)) /* is device a TTY? */ + ++ports; + close (port); + } + } + } + } + free (namelist[n]); + } + free (namelist); + } +#else /* Non Linux, just try some well known device names */ +for (i=0; (ports < max) && (i < 64); ++i) { + sprintf (list[ports].name, "/dev/ttyS%d", i); + port = open (list[ports].name, O_RDWR | O_NOCTTY | O_NONBLOCK); /* open the port */ + if (port != -1) { /* open OK? */ + if (isatty (port)) /* is device a TTY? */ + ++ports; + close (port); + } + } +for (i=0; (ports < max) && (i < 64); ++i) { + sprintf (list[ports].name, "/dev/ttyUSB%d", i); + port = open (list[ports].name, O_RDWR | O_NOCTTY | O_NONBLOCK); /* open the port */ + if (port != -1) { /* open OK? */ + if (isatty (port)) /* is device a TTY? */ + ++ports; + close (port); + } + } +for (i=1; (ports < max) && (i < 64); ++i) { + sprintf (list[ports].name, "/dev/tty.serial%d", i); + port = open (list[ports].name, O_RDWR | O_NOCTTY | O_NONBLOCK); /* open the port */ + if (port != -1) { /* open OK? */ + if (isatty (port)) /* is device a TTY? */ + ++ports; + close (port); + } + } +#endif +return ports; +} + +/* Open a serial port. + + The serial port designated by "name" is opened, and the handle to the port is + returned. If an error occurs, INVALID_HANDLE is returned instead. After + opening, the port is configured to "raw" mode. + + Implementation notes: + + 1. We use a non-blocking open to allow for polling during reads. + + 2. There is no way to limit "open" just to serial ports, so we must check + after the port is opened. We do this with a combination of "isatty" and + "tcgetattr". + + 3. We configure with PARMRK set and IGNBRK and BRKINT cleared. This will + mark a communication line BREAK condition in the input stream with the + three-character sequence \377 \000 \000. This is detected during + reading. +*/ + +SERHANDLE sim_open_os_serial (char *name) +{ +static const tcflag_t i_clear = IGNBRK | /* ignore BREAK */ + BRKINT | /* signal on BREAK */ + INPCK | /* enable parity checking */ + ISTRIP | /* strip character to 7 bits */ + INLCR | /* map NL to CR */ + IGNCR | /* ignore CR */ + ICRNL | /* map CR to NL */ + IXON | /* enable XON/XOFF output control */ + IXOFF; /* enable XON/XOFF input control */ + +static const tcflag_t i_set = PARMRK | /* mark parity errors and line breaks */ + IGNPAR; /* ignore parity errors */ + +static const tcflag_t o_clear = OPOST; /* post-process output */ + +static const tcflag_t o_set = 0; + +static const tcflag_t c_clear = HUPCL; /* hang up line on last close */ + +static const tcflag_t c_set = CREAD | /* enable receiver */ + CLOCAL; /* ignore modem status lines */ + +static const tcflag_t l_clear = ISIG | /* enable signals */ + ICANON | /* canonical input */ + ECHO | /* echo characters */ + ECHOE | /* echo ERASE as an error correcting backspace */ + ECHOK | /* echo KILL */ + ECHONL | /* echo NL */ + NOFLSH | /* disable flush after interrupt */ + TOSTOP | /* send SIGTTOU for background output */ + IEXTEN; /* enable extended functions */ + +static const tcflag_t l_set = 0; + + +SERHANDLE port; +struct termios tio; + +port = open (name, O_RDWR | O_NOCTTY | O_NONBLOCK); /* open the port */ + +if (port == -1) { /* open failed? */ + if (errno != ENOENT && errno != EACCES) /* file not found or can't open? */ + sim_error_serial ("open", errno); /* no, so report unexpected error */ + + return INVALID_HANDLE; /* indicate failure to caller */ + } + +if (!isatty (port)) { /* is device a TTY? */ + close (port); /* no, so close it */ + return INVALID_HANDLE; /* and return failure to caller */ + } + +if (tcgetattr (port, &tio)) { /* get the terminal attributes */ + sim_error_serial ("tcgetattr", errno); /* function failed; report unexpected error */ + close (port); /* close the port */ + return INVALID_HANDLE; /* and return failure to caller */ + } + +// which of these methods is best? + +#if 1 + +tio.c_iflag = (tio.c_iflag & ~i_clear) | i_set; /* configure the serial line for raw mode */ +tio.c_oflag = (tio.c_oflag & ~o_clear) | o_set; +tio.c_cflag = (tio.c_cflag & ~c_clear) | c_set; +tio.c_lflag = (tio.c_lflag & ~l_clear) | l_set; + +#elif 0 + +tio.c_iflag &= ~(IGNBRK | BRKINT | INPCK | ISTRIP | INLCR | IGNCR | ICRNL | IXON | IXOFF); +tio.c_iflag |= PARMRK | IGNPAR; +tio.c_oflag &= ~(OPOST); +tio.c_cflag &= ~(HUPCL); +tio.c_cflag |= CREAD | CLOCAL; +tio.c_lflag &= ~(ISIG | ICANON | ECHO | ECHOE | ECHOK | ECHONL | NOFLSH | TOSTOP | IEXTEN); + +#elif 0 + +tio.c_iflag = PARMRK | IGNPAR; +tio.c_oflag = 0; +tio.c_cflag = tio.c_cflag | CLOCAL | CREAD; +tio.c_lflag = 0; + +#endif + +if (tcsetattr (port, TCSANOW, &tio)) { /* set the terminal attributes */ + sim_error_serial ("tcsetattr", errno); /* function failed; report unexpected error */ + close (port); /* close the port */ + return INVALID_HANDLE; /* and return failure to caller */ + } + +return port; /* return port fd for success */ +} + + +/* Configure a serial port. + + Port parameters are configured as specified in the "config" structure. If + "config" contains an invalid configuration value, or if the host system + rejects the configuration (e.g., by requesting an unsupported combination of + character size and stop bits), SCPE_ARG is returned to the caller. If an + unexpected error occurs, SCPE_IOERR is returned. If the configuration + succeeds, SCPE_OK is returned. + + Implementation notes: + + 1. 1.5 stop bits is not a supported configuration. + +*/ + +t_stat sim_config_os_serial (SERHANDLE port, SERCONFIG config) +{ +struct termios tio; +int32 i; + +static const struct { + uint32 rate; + speed_t rate_code; + } baud_map [] = + { { 50, B50 }, { 75, B75 }, { 110, B110 }, { 134, B134 }, + { 150, B150 }, { 200, B200 }, { 300, B300 }, { 600, B600 }, + { 1200, B1200 }, { 1800, B1800 }, { 2400, B2400 }, { 4800, B4800 }, + { 9600, B9600 }, { 19200, B19200 }, { 38400, B38400 }, { 57600, B57600 }, + { 115200, B115200 } }; + +static const int32 baud_count = sizeof (baud_map) / sizeof (baud_map [0]); + +static const tcflag_t charsize_map [4] = { CS5, CS6, CS7, CS8 }; + + +if (tcgetattr (port, &tio)) { /* get the current configuration */ + sim_error_serial ("tcgetattr", errno); /* function failed; report unexpected error */ + return SCPE_IOERR; /* return failure status */ + } + +for (i = 0; i < baud_count; i++) /* assign baud rate */ + if (config.baudrate == baud_map [i].rate) { /* match mapping value? */ + cfsetispeed(&tio, baud_map [i].rate_code); /* set input rate */ + cfsetospeed(&tio, baud_map [i].rate_code); /* set output rate */ + break; + } + +if (i == baud_count) /* baud rate assigned? */ + return SCPE_ARG; /* invalid rate specified */ + +if ((config.charsize >= 5) && (config.charsize <= 8)) /* character size OK? */ + tio.c_cflag = (tio.c_cflag & ~CSIZE) | /* replace character size code */ + charsize_map [config.charsize - 5]; +else + return SCPE_ARG; /* not a valid size */ + +switch (config.parity) { /* assign parity */ + case 'E': + tio.c_cflag = (tio.c_cflag & ~PARODD) | PARENB; /* set for even parity */ + break; + + case 'N': + tio.c_cflag = tio.c_cflag & ~PARENB; /* set for no parity */ + break; + + case 'O': + tio.c_cflag = tio.c_cflag | PARODD | PARENB; /* set for odd parity */ + break; + + default: + return SCPE_ARG; /* not a valid parity specifier */ + } + +if (config.stopbits == 1) /* one stop bit? */ + tio.c_cflag = tio.c_cflag & ~CSTOPB; /* clear two-bits flag */ +else if (config.stopbits == 2) /* two stop bits? */ + tio.c_cflag = tio.c_cflag | CSTOPB; /* set two-bits flag */ +else /* some other number? */ + return SCPE_ARG; /* not a valid number of stop bits */ + +if (tcsetattr (port, TCSAFLUSH, &tio)) { /* set the new configuration */ + sim_error_serial ("tcsetattr", errno); /* function failed; report unexpected error */ + return SCPE_IERR; /* return failure status */ + } + +return SCPE_OK; /* configuration set successfully */ +} + + +/* Control a serial port. + + The DTR and RTS line of the serial port is set or cleared as indicated in + the respective bits_to_set or bits_to_clear parameters. If the + incoming_bits parameter is not NULL, then the modem status bits DCD, RNG, + DSR and CTS are returned. + + If unreasonable or nonsense bits_to_set or bits_to_clear bits are + specified, then the return status is SCPE_ARG; + If an error occurs, SCPE_IOERR is returned. +*/ + +t_stat sim_control_serial (SERHANDLE port, int32 bits_to_set, int32 bits_to_clear, int32 *incoming_bits) +{ +int bits; + +if ((bits_to_set & ~(TMXR_MDM_OUTGOING)) || /* Assure only settable bits */ + (bits_to_clear & ~(TMXR_MDM_OUTGOING)) || + (bits_to_set & bits_to_clear)) /* and can't set and clear the same bits */ + return SCPE_ARG; +if (bits_to_set) { + bits = ((bits_to_set&TMXR_MDM_DTR) ? TIOCM_DTR : 0) | + ((bits_to_set&TMXR_MDM_RTS) ? TIOCM_RTS : 0); + if (ioctl (port, TIOCMBIS, &bits)) { /* set the desired bits */ + sim_error_serial ("ioctl", errno); /* report unexpected error */ + return SCPE_IOERR; /* return failure status */ + } + } +if (bits_to_clear) { + bits = ((bits_to_clear&TMXR_MDM_DTR) ? TIOCM_DTR : 0) | + ((bits_to_clear&TMXR_MDM_RTS) ? TIOCM_RTS : 0); + if (ioctl (port, TIOCMBIC, &bits)) { /* clear the desired bits */ + sim_error_serial ("ioctl", errno); /* report unexpected error */ + return SCPE_IOERR; /* return failure status */ + } + } +if (incoming_bits) { + if (ioctl (port, TIOCMGET, &bits)) { /* get the modem bits */ + sim_error_serial ("ioctl", errno); /* report unexpected error */ + return SCPE_IOERR; /* return failure status */ + } + *incoming_bits = ((bits&TIOCM_CTS) ? TMXR_MDM_CTS : 0) | + ((bits&TIOCM_DSR) ? TMXR_MDM_DSR : 0) | + ((bits&TIOCM_RNG) ? TMXR_MDM_RNG : 0) | + ((bits&TIOCM_CAR) ? TMXR_MDM_DCD : 0); + } + +return SCPE_OK; +} + + +/* Read from a serial port. + + The port is checked for available characters. If any are present, they are + copied to the passed buffer, and the count of characters is returned. If no + characters are available, 0 is returned. If an error occurs, -1 is returned. + If a BREAK is detected on the communications line, the corresponding flag in + the "brk" array is set. + + Implementation notes: + + 1. A character with a framing or parity error is indicated in the input + stream by the three-character sequence \377 \000 \ccc, where "ccc" is the + bad character. A communications line BREAK is indicated by the sequence + \377 \000 \000. A received \377 character is indicated by the + two-character sequence \377 \377. If we find any of these sequences, + they are replaced by the single intended character by sliding the + succeeding characters backward by one or two positions. If a BREAK + sequence was encountered, the corresponding location in the "brk" array + is determined, and the flag is set. Note that there may be multiple + sequences in the buffer. +*/ + +int32 sim_read_serial (SERHANDLE port, char *buffer, int32 count, char *brk) +{ +int read_count; +char *bptr, *cptr; +int32 remaining; + +read_count = read (port, (void *) buffer, (size_t) count); /* read from the serial port */ + +if (read_count == -1) /* read error? */ + if (errno == EAGAIN) /* no characters available? */ + return 0; /* return 0 to indicate */ + else /* some other problem */ + sim_error_serial ("read", errno); /* report unexpected error */ + +else { /* read succeeded */ + cptr = buffer; /* point at start of buffer */ + remaining = read_count - 1; /* stop search one char from end of string */ + + while (remaining > 0 && /* still characters to search? */ + (bptr = memchr (cptr, '\377', remaining))) { /* search for start of PARMRK sequence */ + remaining = remaining - (bptr - cptr) - 1; /* calc characters remaining */ + + if (*(bptr + 1) == '\377') { /* is it a \377 \377 sequence? */ + memmove (bptr + 1, bptr + 2, remaining); /* slide string backward to leave first \377 */ + remaining = remaining - 1; /* drop remaining count */ + read_count = read_count - 1; /* and read count by char eliminated */ + } + + else if (remaining > 0 && *(bptr + 1) == '\0') { /* is it a \377 \000 \ccc sequence? */ + memmove (bptr, bptr + 2, remaining); /* slide string backward to leave \ccc */ + remaining = remaining - 2; /* drop remaining count */ + read_count = read_count - 2; /* and read count by chars eliminated */ + + if (*bptr == '\0') /* is it a BREAK sequence? */ + *(brk + (bptr - buffer)) = 1; /* set corresponding BREAK flag */ + } + + cptr = bptr + 1; /* point at remainder of string */ + } + } + +return (int32) read_count; /* return the number of characters read */ +} + + +/* Write to a serial port. + + "Count" characters are written from "buffer" to the serial port. The actual + number of characters written to the port is returned. If an error occurred + on writing, -1 is returned. +*/ + +int32 sim_write_serial (SERHANDLE port, char *buffer, int32 count) +{ +int written; + +written = write (port, (void *) buffer, (size_t) count); /* write the buffer to the serial port */ + +if (written == -1) { + if (errno != EAGAIN) /* unexpected error? */ + sim_error_serial ("write", errno); /* report it */ + else + written = 0; /* not an error, but nothing written */ + } + +return (int32) written; /* return number of characters written */ +} + + +/* Close a serial port. + + The serial port is closed. Errors are ignored. +*/ + +void sim_close_os_serial (SERHANDLE port) +{ +close (port); /* close the port */ +return; +} + + +#elif defined (VMS) + +/* VMS implementation */ + +#if defined(__VAX) +#define sys$assign SYS$ASSIGN +#define sys$qiow SYS$QIOW +#define sys$dassgn SYS$DASSGN +#define sys$device_scan SYS$DEVICE_SCAN +#define sys$getdviw SYS$GETDVIW +#endif + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +typedef struct { + unsigned short sense_count; + unsigned char sense_first_char; + unsigned char sense_reserved; + unsigned int stat; + unsigned int stat2; } SENSE_BUF; + +typedef struct { + unsigned short status; + unsigned short count; + unsigned int dev_status; } IOSB; + +typedef struct { + unsigned short buffer_size; + unsigned short item_code; + void *buffer_address; + void *return_length_address; + } ITEM; + +/* Enumerate the available serial ports. + + The serial port names generated by attempting to open /dev/ttyS0 thru + /dev/ttyS53 and /dev/ttyUSB0 thru /dev/ttyUSB0. Ones we can open and + are ttys (as determined by isatty()) are added to the list. The list + is sorted alphabetically by device name. + +*/ + +static int sim_serial_os_devices (int max, SERIAL_LIST* list) +{ +$DESCRIPTOR (wild, "*"); +char devstr[sizeof(list[0].name)]; +$DESCRIPTOR (device, devstr); +int ports; +IOSB iosb; +uint32 status; +uint32 devsts; +#define UCB$M_TEMPLATE 0x2000 /* Device is a template device */ +#define UCB$M_ONLINE 0x0010 /* Device is online */ +uint32 devtype; +uint32 devdepend; +#define DEV$M_RTM 0x20000000 +uint32 devnamlen = 0; +t_bool done = FALSE; +uint32 context[2]; +uint32 devclass = DC$_TERM; /* Only interested in terminal devices */ +ITEM select_items[] = { {sizeof (devclass), DVS$_DEVCLASS, &devclass, NULL}, + { 0, 0, NULL, NULL}}; +ITEM valid_items[] = { { sizeof (devsts), DVI$_STS, &devsts, NULL}, + { sizeof(devstr), DVI$_DEVNAM, devstr, &devnamlen}, + { sizeof(devtype), DVI$_DEVTYPE, &devtype, NULL}, + { sizeof(devdepend), DVI$_DEVDEPEND, &devdepend, NULL}, + { 0, 0, NULL, NULL}}; + +memset(context, 0, sizeof(context)); +memset(devstr, 0, sizeof(devstr)); +memset(list, 0, max*sizeof(*list)); +for (ports=0; (ports < max); ++ports) { + device.dsc$w_length = sizeof (devstr) - 1; + status = sys$device_scan (&device, + &device.dsc$w_length, + &wild, + select_items, + &context); + switch (status) { + case SS$_NOSUCHDEV: + case SS$_NOMOREDEV: + done = TRUE; + break; + default: + if (0 == (status&1)) + done = TRUE; + else { + status = sys$getdviw (0, 0, &device, valid_items, &iosb, NULL, 0, NULL); + if (status == SS$_NORMAL) + status = iosb.status; + if (status != SS$_NORMAL) { + done = TRUE; + break; + } + device.dsc$w_length = devnamlen; + if ((0 == (devsts & UCB$M_TEMPLATE)) && + (0 != (devsts & UCB$M_ONLINE)) && + (0 == (devdepend & DEV$M_RTM))) { + devstr[device.dsc$w_length] = '\0'; + strcpy (list[ports].name, devstr); + while (list[ports].name[0] == '_') + strcpy (list[ports].name, list[ports].name+1); + } + else + --ports; + } + break; + } + if (done) + break; + } +return ports; +} + +/* Open a serial port. + + The serial port designated by "name" is opened, and the handle to the port is + returned. If an error occurs, INVALID_HANDLE is returned instead. After + opening, the port is configured to "raw" mode. + + Implementation notes: + + 1. We use a non-blocking open to allow for polling during reads. + + 2. There is no way to limit "open" just to serial ports, so we must check + after the port is opened. We do this with sys$getdvi. + +*/ + +SERHANDLE sim_open_os_serial (char *name) +{ +uint32 status; +uint32 chan = 0; +IOSB iosb; +$DESCRIPTOR (devnam, name); +uint32 devclass; +ITEM items[] = { {sizeof (devclass), DVI$_DEVCLASS, &devclass, NULL}, + { 0, 0, NULL, NULL}}; +SENSE_BUF start_mode = { 0 }; +SENSE_BUF run_mode = { 0 }; + +devnam.dsc$w_length = strlen (devnam.dsc$a_pointer); +status = sys$assign (&devnam, &chan, 0, 0); +if (status != SS$_NORMAL) + return INVALID_HANDLE; +status = sys$getdviw (0, chan, NULL, items, &iosb, NULL, 0, NULL); +if ((status != SS$_NORMAL) || + (iosb.status != SS$_NORMAL) || + (devclass != DC$_TERM)) { + sys$dassgn (chan); + return INVALID_HANDLE; + } +status = sys$qiow (0, chan, IO$_SENSEMODE, &iosb, 0, 0, + &start_mode, sizeof (start_mode), 0, 0, 0, 0); +if ((status != SS$_NORMAL) || (iosb.status != SS$_NORMAL)) { + sys$dassgn (chan); + return INVALID_HANDLE; + } +run_mode = start_mode; +run_mode.stat = start_mode.stat | TT$M_NOECHO & ~(TT$M_HOSTSYNC | TT$M_TTSYNC | TT$M_HALFDUP); +run_mode.stat2 = start_mode.stat2 | TT2$M_PASTHRU; +status = sys$qiow (0, chan, IO$_SETMODE, &iosb, 0, 0, + &run_mode, sizeof (run_mode), 0, 0, 0, 0); +if ((status != SS$_NORMAL) || (iosb.status != SS$_NORMAL)) { + sys$dassgn (chan); + return INVALID_HANDLE; + } +return chan; /* return channel for success */ +} + + +/* Configure a serial port. + + Port parameters are configured as specified in the "config" structure. If + "config" contains an invalid configuration value, or if the host system + rejects the configuration (e.g., by requesting an unsupported combination of + character size and stop bits), SCPE_ARG is returned to the caller. If an + unexpected error occurs, SCPE_IOERR is returned. If the configuration + succeeds, SCPE_OK is returned. + + Implementation notes: + + 1. 1.5 stop bits is not a supported configuration. + +*/ + +t_stat sim_config_os_serial (SERHANDLE port, SERCONFIG config) +{ +int32 i; +SENSE_BUF sense; +uint32 status, speed, parity, charsize, stopbits; +IOSB iosb; +static const struct { + uint32 rate; + uint32 rate_code; + } baud_map [] = + { { 50, TT$C_BAUD_50 }, { 75, TT$C_BAUD_75 }, { 110, TT$C_BAUD_110 }, { 134, TT$C_BAUD_134 }, + { 150, TT$C_BAUD_150 }, { 300, TT$C_BAUD_300 }, { 600, TT$C_BAUD_600 }, { 1200, TT$C_BAUD_1200 }, + { 1800, TT$C_BAUD_1800 }, { 2000, TT$C_BAUD_2000 }, { 2400, TT$C_BAUD_2400 }, { 3600, TT$C_BAUD_3600 }, + { 4800, TT$C_BAUD_4800 }, { 7200, TT$C_BAUD_7200 }, { 9600, TT$C_BAUD_9600 }, { 19200, TT$C_BAUD_19200 }, + { 38400, TT$C_BAUD_38400 }, { 57600, TT$C_BAUD_57600 }, { 76800, TT$C_BAUD_76800 }, { 115200, TT$C_BAUD_115200} }; + +static const int32 baud_count = sizeof (baud_map) / sizeof (baud_map [0]); + +status = sys$qiow (0, port, IO$_SENSEMODE, &iosb, 0, 0, &sense, sizeof(sense), 0, NULL, 0, 0); +if (status == SS$_NORMAL) + status = iosb.status; +if (status != SS$_NORMAL) { + sim_error_serial ("config-SENSEMODE", status); /* report unexpected error */ + return SCPE_IOERR; + } + +for (i = 0; i < baud_count; i++) /* assign baud rate */ + if (config.baudrate == baud_map [i].rate) { /* match mapping value? */ + speed = baud_map [i].rate_code << 8 | /* set input rate */ + baud_map [i].rate_code; /* set output rate */ + break; + } + +if (i == baud_count) /* baud rate assigned? */ + return SCPE_ARG; /* invalid rate specified */ + +if (config.charsize >= 5 && config.charsize <= 8) /* character size OK? */ + charsize = TT$M_ALTFRAME | config.charsize; /* set character size */ +else + return SCPE_ARG; /* not a valid size */ + +switch (config.parity) { /* assign parity */ + case 'E': + parity = TT$M_ALTRPAR | TT$M_PARITY; /* set for even parity */ + break; + + case 'N': + parity = TT$M_ALTRPAR; /* set for no parity */ + break; + + case 'O': + parity = TT$M_ALTRPAR | TT$M_PARITY | TT$M_ODD; /* set for odd parity */ + break; + + default: + return SCPE_ARG; /* not a valid parity specifier */ + } + + +switch (config.stopbits) { + case 1: /* one stop bit? */ + stopbits = 0; + break; + case 2: /* two stop bits? */ + if ((speed & 0xff) <= TT$C_BAUD_150) { /* Only valid for */ + stopbits = TT$M_TWOSTOP; /* speeds 150baud or less */ + break; + } + default: + return SCPE_ARG; /* not a valid number of stop bits */ + } + +status = sys$qiow (0, port, IO$_SETMODE, &iosb, 0, 0, + &sense, sizeof (sense), speed, 0, parity | charsize | stopbits, 0); +if (status == SS$_NORMAL) + status = iosb.status; +if (status != SS$_NORMAL) { + sim_error_serial ("config-SETMODE", status); /* report unexpected error */ + return SCPE_IOERR; + } +return SCPE_OK; /* configuration set successfully */ +} + + +/* Control a serial port. + + The DTR and RTS line of the serial port is set or cleared as indicated in + the respective bits_to_set or bits_to_clear parameters. If the + incoming_bits parameter is not NULL, then the modem status bits DCD, RNG, + DSR and CTS are returned. + + If unreasonable or nonsense bits_to_set or bits_to_clear bits are + specified, then the return status is SCPE_ARG; + If an error occurs, SCPE_IOERR is returned. +*/ + +t_stat sim_control_serial (SERHANDLE port, int32 bits_to_set, int32 bits_to_clear, int32 *incoming_bits) +{ +uint32 status; +IOSB iosb; +uint32 bits[2] = {0, 0}; + +if ((bits_to_set & ~(TMXR_MDM_OUTGOING)) || /* Assure only settable bits */ + (bits_to_clear & ~(TMXR_MDM_OUTGOING)) || + (bits_to_set & bits_to_clear)) /* and can't set and clear the same bits */ + return SCPE_ARG; +if (bits_to_set) + bits[0] |= (((bits_to_set&TMXR_MDM_DTR) ? TT$M_DS_DTR : 0) | + ((bits_to_set&TMXR_MDM_RTS) ? TT$M_DS_RTS : 0)) << 16; +if (bits_to_clear) + bits[0] |= (((bits_to_clear&TMXR_MDM_DTR) ? TT$M_DS_DTR : 0) | + ((bits_to_clear&TMXR_MDM_RTS) ? TT$M_DS_RTS : 0)) << 24; +if (bits_to_set || bits_to_clear) { + status = sys$qiow (0, port, IO$_SETMODE|IO$M_SET_MODEM|IO$M_MAINT, &iosb, 0, 0, + bits, 0, 0, 0, 0, 0); + if (status == SS$_NORMAL) + status = iosb.status; + if (status != SS$_NORMAL) { + sim_error_serial ("control-SETMODE", status); /* report unexpected error */ + return SCPE_IOERR; + } + } +if (incoming_bits) { + uint32 modem; + + status = sys$qiow (0, port, IO$_SENSEMODE|IO$M_RD_MODEM, &iosb, 0, 0, + bits, 0, 0, 0, 0, 0); + if (status == SS$_NORMAL) + status = iosb.status; + if (status != SS$_NORMAL) { + sim_error_serial ("control-SENSEMODE", status); /* report unexpected error */ + return SCPE_IOERR; + } + modem = bits[0] >> 16; + *incoming_bits = ((modem&TT$M_DS_CTS) ? TMXR_MDM_CTS : 0) | + ((modem&TT$M_DS_DSR) ? TMXR_MDM_DSR : 0) | + ((modem&TT$M_DS_RING) ? TMXR_MDM_RNG : 0) | + ((modem&TT$M_DS_CARRIER) ? TMXR_MDM_DCD : 0); + } + +return SCPE_OK; +} + + +/* Read from a serial port. + + The port is checked for available characters. If any are present, they are + copied to the passed buffer, and the count of characters is returned. If no + characters are available, 0 is returned. If an error occurs, -1 is returned. + If a BREAK is detected on the communications line, the corresponding flag in + the "brk" array is set. + + Implementation notes: + + 1. A character with a framing or parity error is indicated in the input + stream by the three-character sequence \377 \000 \ccc, where "ccc" is the + bad character. A communications line BREAK is indicated by the sequence + \377 \000 \000. A received \377 character is indicated by the + two-character sequence \377 \377. If we find any of these sequences, + they are replaced by the single intended character by sliding the + succeeding characters backward by one or two positions. If a BREAK + sequence was encountered, the corresponding location in the "brk" array + is determined, and the flag is set. Note that there may be multiple + sequences in the buffer. +*/ + +int32 sim_read_serial (SERHANDLE port, char *buffer, int32 count, char *brk) +{ +int read_count = 0; +uint32 status; +static uint32 term[2] = {0, 0}; +unsigned char buf[4]; +IOSB iosb; +SENSE_BUF sense; + +status = sys$qiow (0, port, IO$_SENSEMODE | IO$M_TYPEAHDCNT, &iosb, + 0, 0, &sense, 8, 0, term, 0, 0); +if (status == SS$_NORMAL) + status = iosb.status; +if (status != SS$_NORMAL) { + sim_error_serial ("read", status); /* report unexpected error */ + return -1; + } +if (sense.sense_count == 0) /* no characters available? */ + return 0; /* return 0 to indicate */ +status = sys$qiow (0, port, IO$_READLBLK | IO$M_NOECHO | IO$M_NOFILTR | IO$M_TIMED | IO$M_TRMNOECHO, + &iosb, 0, 0, buffer, (count < sense.sense_count) ? count : sense.sense_count, 0, term, 0, 0); +if (status == SS$_NORMAL) + status = iosb.status; +if (status != SS$_NORMAL) { + sim_error_serial ("read", status); /* report unexpected error */ + return -1; + } +return (int32)iosb.count; /* return the number of characters read */ +} + + +/* Write to a serial port. + + "Count" characters are written from "buffer" to the serial port. The actual + number of characters written to the port is returned. If an error occurred + on writing, -1 is returned. +*/ + +int32 sim_write_serial (SERHANDLE port, char *buffer, int32 count) +{ +uint32 status; +static uint32 term[2] = {0, 0}; +unsigned char buf[4]; +IOSB iosb; +uint32 devsts = 0; +#define UCB$M_BSY 0x100 /* Device I/O busy flag */ +ITEM items[] = { {sizeof (devsts), DVI$_STS, &devsts, NULL}, + { 0, 0, NULL, NULL}}; + +status = sys$getdviw (0, port, NULL, items, &iosb, NULL, 0, 0); +if (status == SS$_NORMAL) + status = iosb.status; +if (status != SS$_NORMAL) { + sim_error_serial ("write-GETDVI", status); /* report unexpected error */ + return -1; + } +if (devsts & UCB$M_BSY) + return 0; /* Would block */ +status = sys$qio (0, port, IO$_WRITELBLK | IO$M_NOFORMAT, + NULL, 0, 0, buffer, count, 0, 0, 0, 0); +if (status != SS$_NORMAL) { + sim_error_serial ("write", status); /* report unexpected error */ + return -1; + } +return (int32)iosb.count; /* return number of characters written */ +} + + +/* Close a serial port. + + The serial port is closed. Errors are ignored. +*/ + +void sim_close_os_serial (SERHANDLE port) +{ +sys$dassgn (port); /* close the port */ +return; +} + + +#else + +/* Non-implemented stubs */ + +/* Enumerate the available serial ports. */ + +static int sim_serial_os_devices (int max, SERIAL_LIST* list) +{ +return 0; +} + +/* Open a serial port */ + +SERHANDLE sim_open_os_serial (char *name) +{ +return INVALID_HANDLE; +} + + +/* Configure a serial port */ + +t_stat sim_config_os_serial (SERHANDLE port, SERCONFIG config) +{ +return SCPE_IERR; +} + + +/* Control a serial port */ + +t_stat sim_control_serial (SERHANDLE port, int32 bits_to_set, int32 bits_to_clear, int32 *incoming_bits) +{ +return SCPE_NOFNC; +} + + +/* Read from a serial port */ + +int32 sim_read_serial (SERHANDLE port, char *buffer, int32 count, char *brk) +{ +return -1; +} + + +/* Write to a serial port */ + +int32 sim_write_serial (SERHANDLE port, char *buffer, int32 count) +{ +return -1; +} + + +/* Close a serial port */ + +void sim_close_os_serial (SERHANDLE port) +{ +return; +} + + + +#endif /* end else !implemented */ diff --git a/sim_serial.h b/sim_serial.h new file mode 100644 index 00000000..9b1d2a7c --- /dev/null +++ b/sim_serial.h @@ -0,0 +1,96 @@ +/* sim_serial.h: OS-dependent serial port routines header file + + Copyright (c) 2008, J. David Bryan + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHOR BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name of the author shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from the author. + + 07-Oct-08 JDB [serial] Created file +*/ + + +#ifndef _SIM_SERIAL_H_ +#define _SIM_SERIAL_H_ 0 + +#if defined (_WIN32) /* Windows definitions */ + +/* We need the basic Win32 definitions, but including "windows.h" also includes + "winsock.h" as well. However, "sim_sock.h" explicitly includes "winsock2.h," + and this file cannot coexist with "winsock.h". So we set a guard definition + that prevents "winsock.h" from being included. +*/ + +#ifndef WIN32_LEAN_AND_MEAN +#define WIN32_LEAN_AND_MEAN +#endif +#include +#if !defined(INVALID_HANDLE) +#define INVALID_HANDLE INVALID_HANDLE_VALUE +#endif /* !defined(INVALID_HANDLE) */ + +#elif defined (__unix__) || defined(__APPLE__) /* UNIX definitions */ + +#include +#include +#include +#include + +#if !defined(INVALID_HANDLE) +#define INVALID_HANDLE -1 +#endif /* !defined(INVALID_HANDLE) */ + +#elif defined (VMS) /* VMS definitions */ +#if !defined(INVALID_HANDLE) +#define INVALID_HANDLE (uint32)(-1) +#endif /* !defined(INVALID_HANDLE) */ + +#else /* Non-implemented definitions */ + +#if !defined(INVALID_HANDLE) +#define INVALID_HANDLE -1 +#endif /* !defined(INVALID_HANDLE) */ + +#endif /* OS variants */ + +#ifndef _SERHANDLE_DEFINED +#define _SERHANDLE_DEFINED 0 +#if defined (_WIN32) /* Windows definitions */ +typedef void *SERHANDLE; +#else /* all other platforms */ +typedef int SERHANDLE; +#endif +#endif /* _SERHANDLE_DEFINED */ + + +/* Common definitions */ + +/* Global routines */ +#include "sim_tmxr.h" /* need TMLN definition and modem definitions */ + +extern SERHANDLE sim_open_serial (char *name, TMLN *lp, t_stat *status); +extern t_stat sim_config_serial (SERHANDLE port, const char *config); +extern t_stat sim_control_serial (SERHANDLE port, int32 bits_to_set, int32 bits_to_clear, int32 *incoming_bits); +extern int32 sim_read_serial (SERHANDLE port, char *buffer, int32 count, char *brk); +extern int32 sim_write_serial (SERHANDLE port, char *buffer, int32 count); +extern void sim_close_serial (SERHANDLE port); +extern t_stat sim_show_serial (FILE* st, DEVICE *dptr, UNIT* uptr, int32 val, char* desc); + +#endif diff --git a/sim_sock.c b/sim_sock.c index 027f7f1d..52617476 100644 --- a/sim_sock.c +++ b/sim_sock.c @@ -23,6 +23,9 @@ used in advertising or otherwise to promote the sale, use or other dealings in this Software without prior written authorization from Robert M Supnik. + 15-Oct-12 MP Added definitions needed to detect possible tcp + connect failures + 25-Sep-12 MP Reworked for RFC3493 interfaces supporting IPv6 and IPv4 22-Jun-10 RMS Fixed types in sim_accept_conn (from Mark Pizzolato) 19-Nov-05 RMS Added conditional for OpenBSD (from Federico G. Schwindt) 16-Aug-05 RMS Fixed spurious SIGPIPE signal error in Unix @@ -43,6 +46,26 @@ #include "sim_sock.h" #include +#if defined(AF_INET6) && defined(_WIN32) +#include +#endif + +#ifdef HAVE_DLOPEN +#include +#endif + +#ifndef WSAAPI +#define WSAAPI +#endif + +#if defined(SHUT_RDWR) && !defined(SD_BOTH) +#define SD_BOTH SHUT_RDWR +#endif + +#ifndef NI_MAXHOST +#define NI_MAXHOST 1025 +#endif + /* OS dependent routines sim_master_sock create master socket @@ -54,23 +77,29 @@ sim_msg_sock send message to socket */ -int32 sim_sock_cnt = 0; - /* First, all the non-implemented versions */ #if defined (__OS2__) && !defined (__EMX__) -SOCKET sim_master_sock (int32 port) +void sim_init_sock (void) +{ +} + +void sim_cleanup_sock (void) +{ +} + +SOCKET sim_master_sock (const char *hostport, t_stat *parse_status) { return INVALID_SOCKET; } -SOCKET sim_connect_sock (int32 ip, int32 port) +SOCKET sim_connect_sock (const char *hostport, const char *default_host, const char *default_port) { return INVALID_SOCKET; } -SOCKET sim_accept_conn (SOCKET master, uint32 *ipaddr) +SOCKET sim_accept_conn (SOCKET master, char **connectaddr); { return INVALID_SOCKET; } @@ -90,11 +119,6 @@ void sim_close_sock (SOCKET sock, t_bool master) return; } -int32 sim_setnonblock (SOCKET sock) -{ -return SOCKET_ERROR; -} - #else /* endif unimpl */ /* UNIX, Win32, Macintosh, VMS, OS2 (Berkeley socket) routines */ @@ -108,30 +132,531 @@ sim_close_sock (s, flg); return INVALID_SOCKET; } -SOCKET sim_create_sock (void) +typedef void (WSAAPI *freeaddrinfo_func) (struct addrinfo *ai); +static freeaddrinfo_func p_freeaddrinfo; + +typedef int (WSAAPI *getaddrinfo_func) (const char *hostname, + const char *service, + const struct addrinfo *hints, + struct addrinfo **res); +static getaddrinfo_func p_getaddrinfo; + +#if defined(VMS) +typedef size_t socklen_t; +#if !defined(EAI_OVERFLOW) +#define EAI_OVERFLOW EAI_FAIL +#endif +#endif + +typedef int (WSAAPI *getnameinfo_func) (const struct sockaddr *sa, socklen_t salen, char *host, size_t hostlen, char *serv, size_t servlen, int flags); +static getnameinfo_func p_getnameinfo; + +static void WSAAPI s_freeaddrinfo (struct addrinfo *ai) +{ +struct addrinfo *a, *an; + +for (a=ai; a != NULL; a=an) { + an = a->ai_next; + free (a->ai_canonname); + free (a->ai_addr); + free (a); + } +} + +static int WSAAPI s_getaddrinfo (const char *hostname, + const char *service, + const struct addrinfo *hints, + struct addrinfo **res) +{ +struct hostent *he; +struct servent *se = NULL; +struct sockaddr_in *sin; +struct addrinfo *result = NULL; +struct addrinfo *ai, *lai; +struct addrinfo dhints; +struct in_addr ipaddr; +struct in_addr *fixed[2]; +struct in_addr **ips = NULL; +struct in_addr **ip; +const char *cname = NULL; +int port = 0; + +// Validate parameters +if ((hostname == NULL) && (service == NULL)) + return EAI_NONAME; + +if (hints) { + if ((hints->ai_family != PF_INET) && (hints->ai_family != PF_UNSPEC)) + return EAI_FAMILY; + switch (hints->ai_socktype) + { + default: + return EAI_SOCKTYPE; + case SOCK_DGRAM: + case SOCK_STREAM: + case 0: + break; + } + } +else { + hints = &dhints; + memset(&dhints, 0, sizeof(dhints)); + dhints.ai_family = PF_UNSPEC; + } +if (service) { + char *c; + + port = strtoul(service, &c, 10); + if ((port == 0) || (*c != '\0')) { + switch (hints->ai_socktype) + { + case SOCK_DGRAM: + se = getservbyname(service, "udp"); + break; + case SOCK_STREAM: + case 0: + se = getservbyname(service, "tcp"); + break; + } + if (NULL == se) + return EAI_SERVICE; + port = se->s_port; + } + } + +if (hostname) { + if ((0xffffffff != (ipaddr.s_addr = inet_addr(hostname))) || + (0 == strcmp("255.255.255.255", hostname))) { + fixed[0] = &ipaddr; + fixed[1] = NULL; + } + else { + if ((0xffffffff != (ipaddr.s_addr = inet_addr(hostname))) || + (0 == strcmp("255.255.255.255", hostname))) { + fixed[0] = &ipaddr; + fixed[1] = NULL; + if ((hints->ai_flags & AI_CANONNAME) && !(hints->ai_flags & AI_NUMERICHOST)) { + he = gethostbyaddr((char *)&ipaddr, 4, AF_INET); + if (NULL != he) + cname = he->h_name; + else + cname = hostname; + } + ips = fixed; + } + else { + if (hints->ai_flags & AI_NUMERICHOST) + return EAI_NONAME; + he = gethostbyname(hostname); + if (he) { + ips = (struct in_addr **)he->h_addr_list; + if (hints->ai_flags & AI_CANONNAME) + cname = he->h_name; + } + else { + switch (h_errno) + { + case HOST_NOT_FOUND: + case NO_DATA: + return EAI_NONAME; + case TRY_AGAIN: + return EAI_AGAIN; + default: + return EAI_FAIL; + } + } + } + } + } +else { + if (hints->ai_flags & AI_PASSIVE) + ipaddr.s_addr = htonl(INADDR_ANY); + else + ipaddr.s_addr = htonl(INADDR_LOOPBACK); + fixed[0] = &ipaddr; + fixed[1] = NULL; + ips = fixed; + } +for (ip=ips; *ip != NULL; ++ip) { + ai = calloc(1, sizeof(*ai)); + if (NULL == ai) { + s_freeaddrinfo(result); + return EAI_MEMORY; + } + ai->ai_family = PF_INET; + ai->ai_socktype = hints->ai_socktype; + ai->ai_protocol = hints->ai_protocol; + ai->ai_addr = NULL; + ai->ai_addrlen = sizeof(struct sockaddr_in); + ai->ai_canonname = NULL; + ai->ai_next = NULL; + ai->ai_addr = calloc(1, sizeof(struct sockaddr_in)); + if (NULL == ai->ai_addr) { + free(ai); + s_freeaddrinfo(result); + return EAI_MEMORY; + } + sin = (struct sockaddr_in *)ai->ai_addr; + sin->sin_family = PF_INET; + sin->sin_port = port; + memcpy(&sin->sin_addr, *ip, sizeof(sin->sin_addr)); + if (NULL == result) + result = ai; + else + lai->ai_next = ai; + lai = ai; + } +if (cname) { + result->ai_canonname = calloc(1, strlen(cname)+1); + if (NULL == result->ai_canonname) { + s_freeaddrinfo(result); + return EAI_MEMORY; + } + strcpy(result->ai_canonname, cname); + } +*res = result; +return 0; +} + +#ifndef EAI_OVERFLOW +#define EAI_OVERFLOW WSAENAMETOOLONG +#endif + +static int WSAAPI s_getnameinfo (const struct sockaddr *sa, socklen_t salen, + char *host, size_t hostlen, + char *serv, size_t servlen, + int flags) +{ +struct hostent *he; +struct servent *se = NULL; +struct sockaddr_in *sin = (struct sockaddr_in *)sa; + +if (sin->sin_family != PF_INET) + return EAI_FAMILY; +if ((NULL == host) && (NULL == serv)) + return EAI_NONAME; +if ((serv) && (servlen > 0)) { + if (flags & NI_NUMERICSERV) + se = NULL; + else + if (flags & NI_DGRAM) + se = getservbyport(sin->sin_port, "udp"); + else + se = getservbyport(sin->sin_port, "tcp"); + if (se) { + if (servlen <= strlen(se->s_name)) + return EAI_OVERFLOW; + strcpy(serv, se->s_name); + } + else { + char buf[16]; + + sprintf(buf, "%d", ntohs(sin->sin_port)); + if (servlen <= strlen(buf)) + return EAI_OVERFLOW; + strcpy(serv, buf); + } + } +if ((host) && (hostlen > 0)) { + if (flags & NI_NUMERICHOST) + he = NULL; + else + he = gethostbyaddr((char *)&sin->sin_addr, 4, AF_INET); + if (he) { + if (hostlen < strlen(he->h_name)+1) + return EAI_OVERFLOW; + strcpy(host, he->h_name); + } + else { + if (flags & NI_NAMEREQD) + return EAI_NONAME; + if (hostlen < strlen(inet_ntoa(sin->sin_addr))+1) + return EAI_OVERFLOW; + strcpy(host, inet_ntoa(sin->sin_addr)); + } + } +return 0; +} + +#if defined(_WIN32) || defined(__CYGWIN__) + +#if !defined(IPV6_V6ONLY) /* Older XP environments may not define IPV6_V6ONLY */ +#define IPV6_V6ONLY 27 /* Treat wildcard bind as AF_INET6-only. */ +#endif +/* Dynamic DLL load variables */ +#ifdef _WIN32 +static HINSTANCE hLib = 0; /* handle to DLL */ +#else +static void *hLib = NULL; /* handle to Library */ +#endif +static int lib_loaded = 0; /* 0=not loaded, 1=loaded, 2=library load failed, 3=Func load failed */ +static char* lib_name = "Ws2_32.dll"; + +/* load function pointer from DLL */ +typedef int (*_func)(); + +static void load_function(char* function, _func* func_ptr) { +#ifdef _WIN32 + *func_ptr = (_func)GetProcAddress(hLib, function); +#else + *func_ptr = (_func)dlsym(hLib, function); +#endif + if (*func_ptr == 0) { + char* msg = "Sockets: Failed to find function '%s' in %s\r\n"; + + printf (msg, function, lib_name); + if (sim_log) fprintf (sim_log, msg, function, lib_name); + lib_loaded = 3; + } +} + +/* load Ws2_32.dll as required */ +int load_ws2(void) { + switch(lib_loaded) { + case 0: /* not loaded */ + /* attempt to load DLL */ +#ifdef _WIN32 + hLib = LoadLibraryA(lib_name); +#else + hLib = dlopen(lib_name, RTLD_NOW); +#endif + if (hLib == 0) { + /* failed to load DLL */ + char* msg = "Sockets: Failed to load %s\r\n"; + + printf (msg, lib_name); + if (sim_log) + fprintf (sim_log, msg, lib_name); + lib_loaded = 2; + break; + } else { + /* library loaded OK */ + lib_loaded = 1; + } + + /* load required functions; sets dll_load=3 on error */ + load_function("getaddrinfo", (_func *) &p_getaddrinfo); + load_function("getnameinfo", (_func *) &p_getnameinfo); + load_function("freeaddrinfo", (_func *) &p_freeaddrinfo); + + if (lib_loaded != 1) { + /* unsuccessful load, connect stubs */ + p_getaddrinfo = (getaddrinfo_func)s_getaddrinfo; + p_getnameinfo = (getnameinfo_func)s_getnameinfo; + p_freeaddrinfo = (freeaddrinfo_func)s_freeaddrinfo; + } + break; + default: /* loaded or failed */ + break; + } + return (lib_loaded == 1) ? 1 : 0; +} +#endif + +/* OS independent routines + + sim_parse_addr parse a hostname/ipaddress from port and apply defaults and + optionally validate an address match +*/ + +/* sim_parse_addr host:port + + Presumption is that the input, if it doesn't contain a ':' character is a port specifier. + If the host field contains one or more colon characters (i.e. it is an IPv6 address), + the IPv6 address MUST be enclosed in square bracket characters (i.e. Domain Literal format) + + Inputs: + cptr = pointer to input string + default_host + = optional pointer to default host if none specified + host_len = length of host buffer + default_port + = optional pointer to default port if none specified + port_len = length of port buffer + validate_addr = optional name/addr which is checked to be equivalent + to the host result of parsing the other input. This + address would usually be returned by sim_accept_conn. + Outputs: + host = pointer to buffer for IP address (may be NULL), 0 = none + port = pointer to buffer for IP port (may be NULL), 0 = none + result = status (SCPE_OK on complete success or SCPE_ARG if + parsing can't happen due to bad syntax, a value is + out of range, a result can't fit into a result buffer, + a service name doesn't exist, or a validation name + doesn't match the parsed host) +*/ + +t_stat sim_parse_addr (const char *cptr, char *host, size_t host_len, const char *default_host, char *port, size_t port_len, const char *default_port, const char *validate_addr) +{ +char gbuf[CBUFSIZE]; +char *hostp, *portp; +char *endc; +unsigned long portval; + +if ((cptr == NULL) || (*cptr == 0)) + return SCPE_ARG; +if ((host != NULL) && (host_len != 0)) + memset (host, 0, host_len); +if ((port != NULL) && (port_len != 0)) + memset (port, 0, port_len); +gbuf[sizeof(gbuf)-1] = '\0'; +strncpy (gbuf, cptr, sizeof(gbuf)-1); +hostp = gbuf; /* default addr */ +portp = NULL; +if ((portp = strrchr (gbuf, ':')) && /* x:y? split */ + (NULL == strchr (portp, ']'))) { + *portp++ = 0; + if (*portp == '\0') + portp = (char *)default_port; + } +else { /* No colon in input */ + portp = gbuf; /* Input is the port specifier */ + hostp = (char *)default_host; /* host is defaulted if provided */ + } +if (portp != NULL) { + portval = strtoul(portp, &endc, 10); + if ((*endc == '\0') && ((portval == 0) || (portval > 65535))) + return SCPE_ARG; /* numeric value too big */ + if (*endc != '\0') { + struct servent *se = getservbyname(portp, "tcp"); + + if (se == NULL) + return SCPE_ARG; /* invalid service name */ + } + } +if (port) /* port wanted? */ + if (portp != NULL) { + if (strlen(portp) >= port_len) + return SCPE_ARG; /* no room */ + else + strcpy (port, portp); + } +if (hostp != NULL) { + if (']' == hostp[strlen(hostp)-1]) { + if ('[' != hostp[0]) + return SCPE_ARG; /* invalid domain literal */ + /* host may be the const default_host so move to temp buffer before modifying */ + strncpy(gbuf, hostp+1, sizeof(gbuf)-1); /* remove brackets from domain literal host */ + hostp = gbuf; + hostp[strlen(hostp)-1] = '\0'; + } + } +if (host) /* host wanted? */ + if (hostp != NULL) { + if (strlen(hostp) >= host_len) + return SCPE_ARG; /* no room */ + else + strcpy (host, hostp); + } +if (validate_addr) { + struct addrinfo *ai_host, *ai_validate, *ai; + t_stat status; + + if (hostp == NULL) + return SCPE_ARG; + if (p_getaddrinfo(hostp, NULL, NULL, &ai_host)) + return SCPE_ARG; + if (p_getaddrinfo(validate_addr, NULL, NULL, &ai_validate)) { + p_freeaddrinfo (ai_host); + return SCPE_ARG; + } + status = SCPE_ARG; + for (ai = ai_host; ai != NULL; ai = ai->ai_next) { + if ((ai->ai_addrlen == ai_validate->ai_addrlen) && + (ai->ai_family == ai_validate->ai_family) && + (0 == memcmp (ai->ai_addr, ai_validate->ai_addr, ai->ai_addrlen))) { + status = SCPE_OK; + break; + } + } + p_freeaddrinfo (ai_host); + p_freeaddrinfo (ai_validate); + return status; + } +return SCPE_OK; +} + +void sim_init_sock (void) +{ +#if defined (_WIN32) +int err; +WORD wVersionRequested; +WSADATA wsaData; +wVersionRequested = MAKEWORD (2, 2); + +err = WSAStartup (wVersionRequested, &wsaData); /* start Winsock */ +if (err != 0) + printf ("Winsock: startup error %d\n", err); +#if defined(AF_INET6) +load_ws2 (); +#endif /* endif AF_INET6 */ +#else /* Use native addrinfo APIs */ +#if defined(AF_INET6) + p_getaddrinfo = (getaddrinfo_func)getaddrinfo; + p_getnameinfo = (getnameinfo_func)getnameinfo; + p_freeaddrinfo = (freeaddrinfo_func)freeaddrinfo; +#else + /* Native APIs not available, connect stubs */ + p_getaddrinfo = (getaddrinfo_func)s_getaddrinfo; + p_getnameinfo = (getnameinfo_func)s_getnameinfo; + p_freeaddrinfo = (freeaddrinfo_func)s_freeaddrinfo; +#endif /* endif AF_INET6 */ +#endif /* endif _WIN32 */ +#if defined (SIGPIPE) +signal (SIGPIPE, SIG_IGN); /* no pipe signals */ +#endif +} + +void sim_cleanup_sock (void) +{ +#if defined (_WIN32) +WSACleanup (); +#endif +} + +#if defined (_WIN32) /* Windows */ +static int32 sim_setnonblock (SOCKET sock) +{ +unsigned long non_block = 1; + +return ioctlsocket (sock, FIONBIO, &non_block); /* set nonblocking */ +} + +#elif defined (VMS) /* VMS */ +static int32 sim_setnonblock (SOCKET sock) +{ +int non_block = 1; + +return ioctl (sock, FIONBIO, &non_block); /* set nonblocking */ +} + +#else /* Mac, Unix, OS/2 */ +static int32 sim_setnonblock (SOCKET sock) +{ +int32 fl, sta; + +fl = fcntl (sock, F_GETFL,0); /* get flags */ +if (fl == -1) + return SOCKET_ERROR; +sta = fcntl (sock, F_SETFL, fl | O_NONBLOCK); /* set nonblock */ +if (sta == -1) + return SOCKET_ERROR; +#if !defined (macintosh) && !defined (__EMX__) /* Unix only */ +sta = fcntl (sock, F_SETOWN, getpid()); /* set ownership */ +if (sta == -1) + return SOCKET_ERROR; +#endif +return 0; +} + +#endif /* endif !Win32 && !VMS */ + +static SOCKET sim_create_sock (int af) { SOCKET newsock; int32 err; -#if defined (_WIN32) -WORD wVersionRequested; -WSADATA wsaData; -wVersionRequested = MAKEWORD (1, 1); - -if (sim_sock_cnt == 0) { - err = WSAStartup (wVersionRequested, &wsaData); /* start Winsock */ - if (err != 0) { - printf ("Winsock: startup error %d\n", err); - return INVALID_SOCKET; - } - } -sim_sock_cnt = sim_sock_cnt + 1; -#endif /* endif Win32 */ -#if defined (SIGPIPE) -signal (SIGPIPE, SIG_IGN); /* no pipe signals */ -#endif - -newsock = socket (AF_INET, SOCK_STREAM, 0); /* create socket */ +newsock = socket (af, SOCK_STREAM, 0); /* create socket */ if (newsock == INVALID_SOCKET) { /* socket error? */ err = WSAGetLastError (); printf ("Sockets: socket error %d\n", err); @@ -140,21 +665,51 @@ if (newsock == INVALID_SOCKET) { /* socket error? */ return newsock; } -SOCKET sim_master_sock (int32 port) -{ -SOCKET newsock; -struct sockaddr_in name; -int32 sta; +/* + Some platforms and/or network stacks have varying support for listening on + an IPv6 socket and receiving connections from both IPv4 and IPv6 client + connections. This is known as IPv4-Mapped. Some platforms claim such + support (i.e. some Windows versions), but it doesn't work in all cases. +*/ -newsock = sim_create_sock (); /* create socket */ -if (newsock == INVALID_SOCKET) /* socket error? */ +SOCKET sim_master_sock (const char *hostport, t_stat *parse_status) +{ +SOCKET newsock = INVALID_SOCKET; +int32 sta; +char host[CBUFSIZE], port[CBUFSIZE]; +t_stat r; +struct addrinfo hints; +struct addrinfo *result = NULL; + +r = sim_parse_addr (hostport, host, sizeof(host), NULL, port, sizeof(port), NULL, NULL); +if (parse_status) + *parse_status = r; +if (r != SCPE_OK) return newsock; -name.sin_family = AF_INET; /* name socket */ -name.sin_port = htons ((unsigned short) port); /* insert port */ -name.sin_addr.s_addr = htonl (INADDR_ANY); /* insert addr */ - -sta = bind (newsock, (struct sockaddr *) &name, sizeof (name)); +memset(&hints, 0, sizeof(hints)); +hints.ai_flags = AI_PASSIVE; +hints.ai_family = AF_UNSPEC; +hints.ai_protocol = IPPROTO_TCP; +hints.ai_socktype = SOCK_STREAM; +if (p_getaddrinfo(host[0] ? host : NULL, port[0] ? port : NULL, &hints, &result)) { + if (parse_status) + *parse_status = SCPE_ARG; + return newsock; + } +newsock = sim_create_sock (result->ai_family); /* create socket */ +if (newsock == INVALID_SOCKET) { /* socket error? */ + p_freeaddrinfo(result); + return newsock; + } +#ifdef IPV6_V6ONLY +if (result->ai_family == AF_INET6) { + int off = FALSE; + sta = setsockopt (newsock, IPPROTO_IPV6, IPV6_V6ONLY, (char *)&off, sizeof(off)); + } +#endif +sta = bind (newsock, result->ai_addr, result->ai_addrlen); +p_freeaddrinfo(result); if (sta == SOCKET_ERROR) /* bind error? */ return sim_err_sock (newsock, "bind", 1); sta = sim_setnonblock (newsock); /* set nonblocking */ @@ -166,24 +721,38 @@ if (sta == SOCKET_ERROR) /* listen error? */ return newsock; /* got it! */ } -SOCKET sim_connect_sock (int32 ip, int32 port) +SOCKET sim_connect_sock (const char *hostport, const char *default_host, const char *default_port) { -SOCKET newsock; -struct sockaddr_in name; +SOCKET newsock = INVALID_SOCKET; int32 sta; +char host[CBUFSIZE], port[CBUFSIZE]; +t_stat r; +struct addrinfo hints; +struct addrinfo *result = NULL; -newsock = sim_create_sock (); /* create socket */ -if (newsock == INVALID_SOCKET) /* socket error? */ +r = sim_parse_addr (hostport, host, sizeof(host), default_host, port, sizeof(port), default_port, NULL); +if (r != SCPE_OK) return newsock; -name.sin_family = AF_INET; /* name socket */ -name.sin_port = htons ((unsigned short) port); /* insert port */ -name.sin_addr.s_addr = htonl (ip); /* insert addr */ +memset(&hints, 0, sizeof(hints)); +hints.ai_family = AF_UNSPEC; +hints.ai_protocol = IPPROTO_TCP; +hints.ai_socktype = SOCK_STREAM; +if (p_getaddrinfo(host[0] ? host : NULL, port[0] ? port : NULL, &hints, &result)) + return newsock; +newsock = sim_create_sock (result->ai_family); /* create socket */ +if (newsock == INVALID_SOCKET) { /* socket error? */ + p_freeaddrinfo (result); + return newsock; + } sta = sim_setnonblock (newsock); /* set nonblocking */ -if (sta == SOCKET_ERROR) /* fcntl error? */ +if (sta == SOCKET_ERROR) { /* fcntl error? */ + p_freeaddrinfo (result); return sim_err_sock (newsock, "fcntl", 1); -sta = connect (newsock, (struct sockaddr *) &name, sizeof (name)); + } +sta = connect (newsock, result->ai_addr, result->ai_addrlen); +p_freeaddrinfo (result); if ((sta == SOCKET_ERROR) && (WSAGetLastError () != WSAEWOULDBLOCK) && (WSAGetLastError () != WSAEINPROGRESS)) @@ -192,7 +761,7 @@ if ((sta == SOCKET_ERROR) && return newsock; /* got it! */ } -SOCKET sim_accept_conn (SOCKET master, uint32 *ipaddr) +SOCKET sim_accept_conn (SOCKET master, char **connectaddr) { int32 sta, err; #if defined (macintosh) || defined (__linux) || \ @@ -206,11 +775,12 @@ int size; size_t size; #endif SOCKET newsock; -struct sockaddr_in clientname; +struct sockaddr_storage clientname; if (master == 0) /* not attached? */ return INVALID_SOCKET; size = sizeof (clientname); +memset (&clientname, 0, sizeof(clientname)); newsock = accept (master, (struct sockaddr *) &clientname, &size); if (newsock == INVALID_SOCKET) { /* error? */ err = WSAGetLastError (); @@ -218,8 +788,16 @@ if (newsock == INVALID_SOCKET) { /* error? */ printf ("Sockets: accept error %d\n", err); return INVALID_SOCKET; } -if (ipaddr != NULL) - *ipaddr = ntohl (clientname.sin_addr.s_addr); +if (connectaddr != NULL) { + *connectaddr = calloc(1, NI_MAXHOST+1); +#ifdef AF_INET6 + p_getnameinfo((struct sockaddr *)&clientname, size, *connectaddr, NI_MAXHOST, NULL, 0, NI_NUMERICHOST); + if (0 == memcmp("::ffff:", *connectaddr, 7)) /* is this a IPv4-mapped IPv6 address? */ + strcpy(*connectaddr, 7+*connectaddr); /* prefer bare IPv4 address if possible */ +#else + strcpy(*connectaddr, inet_ntoa(((struct sockaddr_in *)&connectaddr)->s_addr)); +#endif + } sta = sim_setnonblock (newsock); /* set nonblocking */ if (sta == SOCKET_ERROR) /* fcntl error? */ @@ -260,7 +838,10 @@ if (rbytes == SOCKET_ERROR) { err = WSAGetLastError (); if (err == WSAEWOULDBLOCK) /* no data */ return 0; - printf ("Sockets: read error %d\n", err); + if ((err != WSAETIMEDOUT) && /* expected errors after a connect failure */ + (err != WSAEHOSTUNREACH) && + (err != WSAECONNREFUSED)) + printf ("Sockets: read error %d\n", err); return -1; } return rbytes; @@ -273,56 +854,8 @@ return send (sock, msg, nbytes, 0); void sim_close_sock (SOCKET sock, t_bool master) { -#if defined (_WIN32) +shutdown(sock, SD_BOTH); closesocket (sock); -if (master) { - sim_sock_cnt = sim_sock_cnt - 1; - if (sim_sock_cnt <= 0) { - WSACleanup (); - sim_sock_cnt = 0; - } - } -#else -close (sock); -#endif -return; } -#if defined (_WIN32) /* Windows */ -int32 sim_setnonblock (SOCKET sock) -{ -unsigned long non_block = 1; - -return ioctlsocket (sock, FIONBIO, &non_block); /* set nonblocking */ -} - -#elif defined (VMS) /* VMS */ -int32 sim_setnonblock (SOCKET sock) -{ -int non_block = 1; - -return ioctl (sock, FIONBIO, &non_block); /* set nonblocking */ -} - -#else /* Mac, Unix, OS/2 */ -int32 sim_setnonblock (SOCKET sock) -{ -int32 fl, sta; - -fl = fcntl (sock, F_GETFL,0); /* get flags */ -if (fl == -1) - return SOCKET_ERROR; -sta = fcntl (sock, F_SETFL, fl | O_NONBLOCK); /* set nonblock */ -if (sta == -1) - return SOCKET_ERROR; -#if !defined (macintosh) && !defined (__EMX__) /* Unix only */ -sta = fcntl (sock, F_SETOWN, getpid()); /* set ownership */ -if (sta == -1) - return SOCKET_ERROR; -#endif -return 0; -} - -#endif /* endif !Win32 && !VMS */ - #endif /* end else !implemented */ diff --git a/sim_sock.h b/sim_sock.h index d8531cbe..36d4122c 100644 --- a/sim_sock.h +++ b/sim_sock.h @@ -23,6 +23,9 @@ used in advertising or otherwise to promote the sale, use or other dealings in this Software without prior written authorization from Robert M Supnik. + 15-Oct-12 MP Added definitions needed to detect possible tcp + connect failures + 25-Sep-12 MP Reworked for RFC3493 interfaces supporting IPv6 and IPv4 04-Jun-08 RMS Addes sim_create_sock, for IBM 1130 14-Apr-05 RMS Added WSAEINPROGRESS (from Tim Riker) 20-Aug-04 HV Added missing definition for OS/2 (from Holger Veit) @@ -44,21 +47,25 @@ #define _SIM_SOCK_H_ 0 #if defined (_WIN32) /* Windows */ -#undef INT_PTR /* hack, hack */ #include #elif !defined (__OS2__) || defined (__EMX__) /* VMS, Mac, Unix, OS/2 EMX */ #define WSAGetLastError() errno /* Windows macros */ +#define closesocket close #define SOCKET int32 #define WSAEWOULDBLOCK EWOULDBLOCK #define WSAEINPROGRESS EINPROGRESS -#define INVALID_SOCKET -1 +#define WSAETIMEDOUT ETIMEDOUT +#define WSAECONNREFUSED ECONNREFUSED +#define WSAEHOSTUNREACH EHOSTUNREACH +#define INVALID_SOCKET ((SOCKET)-1) #define SOCKET_ERROR -1 #include /* for fcntl, getpid */ #include /* for sockets */ #include #include #include /* for sockaddr_in */ +#include /* for inet_addr and inet_ntoa */ #include #include /* for EMX */ #endif @@ -75,14 +82,15 @@ #endif #endif -SOCKET sim_master_sock (int32 port); -SOCKET sim_connect_sock (int32 ip, int32 port); -SOCKET sim_create_sock (void); -SOCKET sim_accept_conn (SOCKET master, uint32 *ipaddr); +t_stat sim_parse_addr (const char *cptr, char *host, size_t hostlen, const char *default_host, char *port, size_t port_len, const char *default_port, const char *validate_addr); +SOCKET sim_master_sock (const char *hostport, t_stat *parse_status); +SOCKET sim_connect_sock (const char *hostport, const char *default_host, const char *default_port); +SOCKET sim_accept_conn (SOCKET master, char **connectaddr); int32 sim_check_conn (SOCKET sock, t_bool rd); int32 sim_read_sock (SOCKET sock, char *buf, int32 nbytes); int32 sim_write_sock (SOCKET sock, char *msg, int32 nbytes); void sim_close_sock (SOCKET sock, t_bool master); -int32 sim_setnonblock (SOCKET sock); +void sim_init_sock (void); +void sim_cleanup_sock (void); #endif diff --git a/sim_tape.c b/sim_tape.c index 8341089c..8d44d535 100644 --- a/sim_tape.c +++ b/sim_tape.c @@ -58,6 +58,7 @@ sim_tape_attach attach tape unit sim_tape_detach detach tape unit + sim_tape_attach_help help routine for attaching tapes sim_tape_rdrecf read tape record forward sim_tape_rdrecr read tape record reverse sim_tape_wrrecf write tape record forward @@ -108,8 +109,6 @@ static struct sim_tape_fmt fmts[MTUF_N_FMT] = { { NULL, 0, 0 } }; -extern int32 sim_switches; - t_stat sim_tape_ioerr (UNIT *uptr); t_stat sim_tape_wrdata (UNIT *uptr, uint32 dat); uint32 sim_tape_tpc_map (UNIT *uptr, t_addr *map); @@ -125,6 +124,7 @@ struct tape_context { pthread_t io_thread; /* I/O Thread Id */ pthread_mutex_t io_lock; pthread_cond_t io_cond; + pthread_cond_t io_done; pthread_cond_t startup_cond; int io_top; uint8 *buf; @@ -273,6 +273,7 @@ struct tape_context *ctx = (struct tape_context *)uptr->tape_ctx; } pthread_mutex_lock (&ctx->io_lock); ctx->io_top = TOP_DONE; + pthread_cond_signal (&ctx->io_done); sim_activate (uptr, ctx->asynch_io_latency); } pthread_mutex_unlock (&ctx->io_lock); @@ -286,7 +287,7 @@ struct tape_context *ctx = (struct tape_context *)uptr->tape_ctx; processing events for any unit. It is only called when an asynchronous thread has called sim_activate() to activate a unit. The job of this routine is to put the unit in proper condition to digest what may have - occurred in the asynchrcondition thread. + occurred in the asynchronous thread. Since tape processing only handles a single I/O at a time to a particular tape device, we have the opportunity to possibly detect @@ -306,6 +307,32 @@ if (ctx->callback && ctx->io_top == TOP_DONE) { callback (uptr, ctx->io_status); } } + +static t_bool _tape_is_active (UNIT *uptr) +{ +struct tape_context *ctx = (struct tape_context *)uptr->tape_ctx; + +if (ctx) { + sim_debug (ctx->dbit, ctx->dptr, "_tape_is_active(unit=%d, top=%d)\n", uptr-ctx->dptr->units, ctx->io_top); + return (ctx->io_top != TOP_DONE); + } +return FALSE; +} + +static void _tape_cancel (UNIT *uptr) +{ +struct tape_context *ctx = (struct tape_context *)uptr->tape_ctx; + +if (ctx) { + sim_debug (ctx->dbit, ctx->dptr, "_tape_cancel(unit=%d, top=%d)\n", uptr-ctx->dptr->units, ctx->io_top); + if (ctx->asynch_io) { + pthread_mutex_lock (&ctx->io_lock); + while (ctx->io_top != TOP_DONE) + pthread_cond_wait (&ctx->io_done, &ctx->io_lock); + pthread_mutex_unlock (&ctx->io_lock); + } + } +} #else #define AIO_CALLSETUP #define AIO_CALL(op, _buf, _fc, _bc, _max, _vbc, _gaplen, _bpi, _obj, _callback) \ @@ -319,7 +346,6 @@ if (ctx->callback && ctx->io_top == TOP_DONE) { t_stat sim_tape_set_async (UNIT *uptr, int latency) { #if !defined(SIM_ASYNCH_IO) -extern FILE *sim_log; /* log file */ char *msg = "Tape: can't operate asynchronously\r\n"; printf ("%s", msg); if (sim_log) fprintf (sim_log, "%s", msg); @@ -333,6 +359,7 @@ ctx->asynch_io_latency = latency; if (ctx->asynch_io) { pthread_mutex_init (&ctx->io_lock, NULL); pthread_cond_init (&ctx->io_cond, NULL); + pthread_cond_init (&ctx->io_done, NULL); pthread_cond_init (&ctx->startup_cond, NULL); pthread_attr_init(&attr); pthread_attr_setscope(&attr, PTHREAD_SCOPE_SYSTEM); @@ -344,6 +371,8 @@ if (ctx->asynch_io) { pthread_cond_destroy (&ctx->startup_cond); } uptr->a_check_completion = _tape_completion_dispatch; +uptr->a_is_active = _tape_is_active; +uptr->a_cancel = _tape_cancel; #endif return SCPE_OK; } @@ -368,12 +397,16 @@ if (ctx->asynch_io) { pthread_join (ctx->io_thread, NULL); pthread_mutex_destroy (&ctx->io_lock); pthread_cond_destroy (&ctx->io_cond); - pthread_cond_destroy (&ctx->startup_cond); + pthread_cond_destroy (&ctx->io_done); } return SCPE_OK; #endif } +/* + This routine is called when the simulator stops and any time + the asynch mode is changed (enabled or disabled) +*/ static void _sim_tape_io_flush (UNIT *uptr) { #if defined (SIM_ASYNCH_IO) @@ -455,9 +488,10 @@ t_stat sim_tape_detach (UNIT *uptr) uint32 f = MT_GET_FMT (uptr); t_stat r; -#if defined (SIM_ASYNCH_IO) sim_tape_clr_async (uptr); -#endif + +if (uptr->io_flush) + uptr->io_flush (uptr); /* flush buffered data */ r = detach_unit (uptr); /* detach unit */ if (r != SCPE_OK) @@ -482,6 +516,33 @@ uptr->io_flush = NULL; return SCPE_OK; } +t_stat sim_tape_attach_help(FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr) +{ +fprintf (st, "%s Tape Attach Help\n\n", dptr->name); +if (0 == (uptr-dptr->units)) { + if (dptr->numunits > 1) { + uint32 i; + + for (i=0; i < dptr->numunits; ++i) + if (dptr->units[i].flags & UNIT_ATTABLE) + fprintf (st, " sim> ATTACH {switches} %s%d tapefile\n\n", dptr->name, i); + } + else + fprintf (st, " sim> ATTACH {switches} %s tapefile\n\n", dptr->name); + } +else + fprintf (st, " sim> ATTACH {switches} %s tapefile\n\n", dptr->name); +fprintf (st, "Attach command switches\n"); +fprintf (st, " -R Attach Read Only.\n"); +fprintf (st, " -E Must Exist (if not specified an attempt to create the indicated\n"); +fprintf (st, " virtual tape will be attempted).\n"); +fprintf (st, " -F Open the indicated tape container in a specific format (default\n"); +fprintf (st, " is SIMH, alternatives are E11, TPC and P7B)\n"); +return SCPE_OK; + +return SCPE_OK; +} + void sim_tape_data_trace(UNIT *uptr, const uint8 *data, size_t len, const char* txt, int detail, uint32 reason) { struct tape_context *ctx = (struct tape_context *)uptr->tape_ctx; @@ -497,11 +558,11 @@ if (ctx->dptr->dctrl & reason) { if ((i > 0) && (0 == memcmp (&data[i], &data[i-16], 16))) { ++same; continue; - } + } if (same > 0) { sim_debug (reason, ctx->dptr, "%04X thru %04X same as above\n", i-(16*same), i-1); same = 0; - } + } group = (((len - i) > 16) ? 16 : (len - i)); for (sidx=oidx=0; sidxdptr->dctrl & reason) { strbuf[sidx] = data[i+sidx]; else strbuf[sidx] = '.'; - } + } outbuf[oidx] = '\0'; strbuf[sidx] = '\0'; sim_debug (reason, ctx->dptr, "%04X%-48s %s\n", i, outbuf, strbuf); - } - if (same > 0) - sim_debug (reason, ctx->dptr, "%04X thru %04X same as above\n", i-(16*same), len-1); + } + if (same > 0) { + sim_debug (reason, ctx->dptr, "%04X thru %04X same as above\n", i-(16*same), len-1); + } } } } @@ -1641,8 +1703,9 @@ t_stat sim_tape_rewind (UNIT *uptr) { struct tape_context *ctx = (struct tape_context *)uptr->tape_ctx; -if (uptr->flags & UNIT_ATT) +if (uptr->flags & UNIT_ATT) { sim_debug (ctx->dbit, ctx->dptr, "sim_tape_rewind(unit=%d)\n", uptr-ctx->dptr->units); + } uptr->pos = 0; MT_CLR_PNU (uptr); return MTSE_OK; @@ -1722,9 +1785,14 @@ return r; t_stat sim_tape_reset (UNIT *uptr) { +struct tape_context *ctx = (struct tape_context *)uptr->tape_ctx; + MT_CLR_PNU (uptr); if (!(uptr->flags & UNIT_ATT)) /* attached? */ return SCPE_OK; + +sim_debug (ctx->dbit, ctx->dptr, "sim_tape_reset(unit=%d)\n", (int)(uptr-ctx->dptr->units)); + _sim_tape_io_flush(uptr); AIO_VALIDATE; AIO_UPDATE_QUEUE; @@ -1847,7 +1915,6 @@ return ((p == 0)? map[p]: map[p - 1]); t_stat sim_tape_set_capac (UNIT *uptr, int32 val, char *cptr, void *desc) { -extern uint32 sim_taddr_64; t_addr cap; t_stat r; @@ -1869,10 +1936,14 @@ t_stat sim_tape_show_capac (FILE *st, UNIT *uptr, int32 val, void *desc) if (uptr->capac) { if (uptr->capac >= (t_addr) 1000000) fprintf (st, "capacity=%dMB", (uint32) (uptr->capac / ((t_addr) 1000000))); - else if (uptr->capac >= (t_addr) 1000) - fprintf (st, "capacity=%dKB", (uint32) (uptr->capac / ((t_addr) 1000))); - else fprintf (st, "capacity=%dB", (uint32) uptr->capac); + else { + if (uptr->capac >= (t_addr) 1000) + fprintf (st, "capacity=%dKB", (uint32) (uptr->capac / ((t_addr) 1000))); + else + fprintf (st, "capacity=%dB", (uint32) uptr->capac); + } } -else fprintf (st, "unlimited capacity"); +else + fprintf (st, "unlimited capacity"); return SCPE_OK; } diff --git a/sim_tape.h b/sim_tape.h index 3ce45ebd..0e8bff43 100644 --- a/sim_tape.h +++ b/sim_tape.h @@ -124,6 +124,7 @@ typedef void (*TAPE_PCALLBACK)(UNIT *unit, t_stat status); t_stat sim_tape_attach_ex (UNIT *uptr, char *cptr, uint32 dbit, int completion_delay); t_stat sim_tape_attach (UNIT *uptr, char *cptr); t_stat sim_tape_detach (UNIT *uptr); +t_stat sim_tape_attach_help(FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr); t_stat sim_tape_rdrecf (UNIT *uptr, uint8 *buf, t_mtrlnt *bc, t_mtrlnt max); t_stat sim_tape_rdrecf_a (UNIT *uptr, uint8 *buf, t_mtrlnt *bc, t_mtrlnt max, TAPE_PCALLBACK callback); t_stat sim_tape_rdrecr (UNIT *uptr, uint8 *buf, t_mtrlnt *bc, t_mtrlnt max); diff --git a/sim_timer.c b/sim_timer.c index 5f3ca2b4..b5c56617 100644 --- a/sim_timer.c +++ b/sim_timer.c @@ -60,7 +60,7 @@ This library includes the following routines: - sim_timer_init - initialize timing system + sim_timer_init - initialize timing system sim_rtc_init - initialize calibration sim_rtc_calb - calibrate clock sim_timer_init - initialize timing system @@ -103,14 +103,11 @@ static uint32 sim_throt_sleep_time = 0; static int32 sim_throt_wait = 0; static UNIT *sim_clock_unit = NULL; static t_bool sim_asynch_timer = -#if defined (SIM_ASYNCH_IO) +#if defined (SIM_ASYNCH_CLOCKS) TRUE; #else FALSE; #endif -extern int32 sim_interval, sim_switches; -extern FILE *sim_log; -extern UNIT *sim_clock_queue; t_stat sim_throt_svc (UNIT *uptr); @@ -430,7 +427,7 @@ if (tim > SIM_IDLE_MAX) tim = 0; return tim; } -#if !defined(_POSIX_SOURCE) && defined(SIM_ASYNCH_IO) +#if !defined(_POSIX_SOURCE) #ifdef NEED_CLOCK_GETTIME typedef int clockid_t; int clock_gettime(clockid_t clk_id, struct timespec *tp) @@ -474,6 +471,7 @@ while (sub->tv_nsec > diff->tv_nsec) { } diff->tv_nsec -= sub->tv_nsec; diff->tv_sec -= sub->tv_sec; +/* Normalize the result */ while (diff->tv_nsec > 1000000000) { ++diff->tv_sec; diff->tv_nsec -= 1000000000; @@ -518,7 +516,7 @@ if (done_time.tv_nsec > 1000000000) { } pthread_mutex_lock (&sim_asynch_lock); sim_idle_wait = TRUE; -if (!pthread_cond_timedwait (&sim_idle_wake, &sim_asynch_lock, &done_time)) +if (!pthread_cond_timedwait (&sim_asynch_wake, &sim_asynch_lock, &done_time)) sim_asynch_check = 0; /* force check of asynch queue now */ else timedout = TRUE; @@ -730,21 +728,21 @@ return SCPE_OK; } REG sim_timer_reg[] = { - { DRDATA (TICKS_PER_SEC, rtc_hz[0], 32), PV_RSPC|REG_RO}, - { DRDATA (INSTS_PER_TICK, rtc_currd[0], 32), PV_RSPC|REG_RO}, - { FLDATA (IDLE_ENAB, sim_idle_enab, 0), REG_RO}, - { DRDATA (IDLE_RATE_MS, sim_idle_rate_ms, 32), PV_RSPC|REG_RO}, - { DRDATA (OS_SLEEP_MIN_MS, sim_os_sleep_min_ms, 32), PV_RSPC|REG_RO}, - { DRDATA (IDLE_STABLE, sim_idle_stable, 32), PV_RSPC}, - { FLDATA (IDLE_IDLED, sim_idle_idled, 0), REG_RO}, - { DRDATA (TMR, sim_calb_tmr, 32), PV_RSPC|REG_RO}, - { DRDATA (THROT_MS_START, sim_throt_ms_start, 32), PV_RSPC|REG_RO}, - { DRDATA (THROT_MS_STOP, sim_throt_ms_stop, 32), PV_RSPC|REG_RO}, - { DRDATA (THROT_TYPE, sim_throt_type, 32), PV_RSPC|REG_RO}, - { DRDATA (THROT_VAL, sim_throt_val, 32), PV_RSPC|REG_RO}, - { DRDATA (THROT_STATE, sim_throt_state, 32), PV_RSPC|REG_RO}, - { DRDATA (THROT_SLEEP_TIME, sim_throt_sleep_time, 32), PV_RSPC|REG_RO}, - { DRDATA (THROT_WAIT, sim_throt_wait, 32), PV_RSPC|REG_RO}, + { DRDATAD (TICKS_PER_SEC, rtc_hz[0], 32, "Ticks Per Second"), PV_RSPC|REG_RO}, + { DRDATAD (INSTS_PER_TICK, rtc_currd[0], 32, "Instructions Per Tick"), PV_RSPC|REG_RO}, + { FLDATAD (IDLE_ENAB, sim_idle_enab, 0, "Idle Enabled"), REG_RO}, + { DRDATAD (IDLE_RATE_MS, sim_idle_rate_ms, 32, "Idle Rate Milliseconds"), PV_RSPC|REG_RO}, + { DRDATAD (OS_SLEEP_MIN_MS, sim_os_sleep_min_ms, 32, "Minimum Sleep Resolution"), PV_RSPC|REG_RO}, + { DRDATAD (IDLE_STABLE, sim_idle_stable, 32, "Idle Stable"), PV_RSPC}, + { FLDATAD (IDLE_IDLED, sim_idle_idled, 0, ""), REG_RO}, + { DRDATAD (TMR, sim_calb_tmr, 32, ""), PV_RSPC|REG_RO}, + { DRDATAD (THROT_MS_START, sim_throt_ms_start, 32, ""), PV_RSPC|REG_RO}, + { DRDATAD (THROT_MS_STOP, sim_throt_ms_stop, 32, ""), PV_RSPC|REG_RO}, + { DRDATAD (THROT_TYPE, sim_throt_type, 32, ""), PV_RSPC|REG_RO}, + { DRDATAD (THROT_VAL, sim_throt_val, 32, ""), PV_RSPC|REG_RO}, + { DRDATAD (THROT_STATE, sim_throt_state, 32, ""), PV_RSPC|REG_RO}, + { DRDATAD (THROT_SLEEP_TIME, sim_throt_sleep_time, 32, ""), PV_RSPC|REG_RO}, + { DRDATAD (THROT_WAIT, sim_throt_wait, 32, ""), PV_RSPC|REG_RO}, { NULL } }; @@ -804,7 +802,7 @@ DEVICE sim_timer_dev = { w = ms_to_wait / ms_per_wait */ -t_bool sim_idle (int32 tmr, t_bool sin_cyc) +t_bool sim_idle (uint32 tmr, t_bool sin_cyc) { static uint32 cyc_ms = 0; uint32 w_ms, w_idle, act_ms; @@ -813,7 +811,7 @@ int32 act_cyc; //sim_idle_idled = TRUE; /* record idle attempt */ if ((!sim_idle_enab) || /* idling disabled */ ((sim_clock_queue == QUEUE_LIST_END) && /* or clock queue empty? */ -#if defined(SIM_ASYNCH_IO) +#if defined(SIM_ASYNCH_IO) && defined(SIM_ASYNCH_CLOCKS) (!(sim_asynch_enabled && sim_asynch_timer)))|| /* and not asynch? */ #else (TRUE)) || @@ -1103,7 +1101,7 @@ sim_activate (uptr, sim_throt_wait); /* reschedule */ return SCPE_OK; } -#if defined(SIM_ASYNCH_IO) +#if defined(SIM_ASYNCH_IO) && defined(SIM_ASYNCH_CLOCKS) static double _timespec_to_double (struct timespec *time) { @@ -1244,11 +1242,11 @@ sim_debug (DBG_TIM, &sim_timer_dev, "_timer_thread() - exiting\n"); return NULL; } -#endif +#endif /* defined(SIM_ASYNCH_IO) && defined(SIM_ASYNCH_CLOCKS) */ void sim_start_timer_services (void) { -#if defined(SIM_ASYNCH_IO) +#if defined(SIM_ASYNCH_IO) && defined(SIM_ASYNCH_CLOCKS) pthread_mutex_lock (&sim_timer_lock); if (sim_asynch_enabled && sim_asynch_timer) { pthread_attr_t attr; @@ -1285,7 +1283,7 @@ pthread_mutex_unlock (&sim_timer_lock); void sim_stop_timer_services (void) { -#if defined(SIM_ASYNCH_IO) +#if defined(SIM_ASYNCH_IO) && defined(SIM_ASYNCH_CLOCKS) pthread_mutex_lock (&sim_timer_lock); if (sim_timer_thread_running) { sim_debug (DBG_TRC, &sim_timer_dev, "sim_stop_timer_services() - stopping\n"); @@ -1301,7 +1299,7 @@ else t_stat sim_timer_change_asynch (void) { -#if defined(SIM_ASYNCH_IO) +#if defined(SIM_ASYNCH_IO) && defined(SIM_ASYNCH_CLOCKS) if (sim_asynch_enabled && sim_asynch_timer) sim_start_timer_services (); else { @@ -1347,11 +1345,11 @@ int32 inst_delay; double inst_per_sec; AIO_VALIDATE; -if (sim_is_active_bool (uptr)) /* already active? */ +if (sim_is_active (uptr)) /* already active? */ return SCPE_OK; inst_per_sec = sim_timer_inst_per_sec (); inst_delay = (int32)((inst_per_sec*usec_delay)/1000000.0); -#if defined(SIM_ASYNCH_IO) +#if defined(SIM_ASYNCH_IO) && defined(SIM_ASYNCH_CLOCKS) if ((sim_calb_tmr == -1) || /* if No timer initialized */ (inst_delay < rtc_currd[sim_calb_tmr]) || /* or sooner than next clock tick? */ (rtc_elapsed[sim_calb_tmr] < sim_idle_stable) || /* or not idle stable yet */ @@ -1432,8 +1430,8 @@ if (NULL == sim_clock_unit) return sim_activate (uptr, interval); else if (sim_asynch_enabled && sim_asynch_timer) { - if (!sim_is_active_bool (uptr)) { /* already active? */ -#if defined(SIM_ASYNCH_IO) + if (!sim_is_active (uptr)) { /* already active? */ +#if defined(SIM_ASYNCH_IO) && defined(SIM_ASYNCH_CLOCKS) sim_debug (DBG_TIM, &sim_timer_dev, "sim_clock_coschedule() - queueing %s for clock co-schedule\n", sim_uname (uptr)); pthread_mutex_lock (&sim_timer_lock); uptr->next = sim_clock_cosched_queue; @@ -1446,7 +1444,7 @@ else else { int32 t; - t = sim_is_active (sim_clock_unit); + t = sim_activate_time (sim_clock_unit); return sim_activate (uptr, t? t - 1: interval); } } diff --git a/sim_timer.h b/sim_timer.h index 5b9f999a..6553e462 100644 --- a/sim_timer.h +++ b/sim_timer.h @@ -86,7 +86,7 @@ int clock_gettime(int clock_id, struct timespec *tp); t_bool sim_timer_init (void); void sim_timespec_diff (struct timespec *diff, struct timespec *min, struct timespec *sub); -#if defined(SIM_ASYNCH_IO) +#if defined(SIM_ASYNCH_CLOCKS) double sim_timenow_double (void); #endif int32 sim_rtcn_init (int32 time, int32 tmr); @@ -95,7 +95,7 @@ int32 sim_rtcn_calb (int32 ticksper, int32 tmr); int32 sim_rtc_init (int32 time); int32 sim_rtc_calb (int32 ticksper); t_stat sim_show_timers (FILE* st, DEVICE *dptr, UNIT* uptr, int32 val, char* desc); -t_bool sim_idle (int32 tmr, t_bool sin_cyc); +t_bool sim_idle (uint32 tmr, t_bool sin_cyc); t_stat sim_set_throt (int32 arg, char *cptr); t_stat sim_show_throt (FILE *st, DEVICE *dnotused, UNIT *unotused, int32 flag, char *cptr); t_stat sim_set_idle (UNIT *uptr, int32 val, char *cptr, void *desc); diff --git a/sim_tmxr.c b/sim_tmxr.c index 3f326cf1..ff2c46d9 100644 --- a/sim_tmxr.c +++ b/sim_tmxr.c @@ -26,11 +26,17 @@ Based on the original DZ11 simulator by Thord Nilson, as updated by Arthur Krewat. + 12-Oct-12 MP Revised serial port support to not require changes to + any code in TMXR library using code. Added support + for per line listener ports and outgoing tcp connections. 02-Jun-11 MP Fixed telnet option negotiation loop with some clients Added Option Negotiation and Debugging Support 17-Jan-11 MP Added Buffered line capabilities 16-Jan-11 MP Made option negotiation more reliable 20-Nov-08 RMS Added three new standardized SHOW routines + 05-Nov-08 JDB Moved logging call after connection check in tmxr_putc_ln + 03-Nov-08 JDB Added TMXR null check to tmxr_find_ldsc + 07-Oct-08 JDB Added initial serial port support 30-Sep-08 JDB Reverted tmxr_find_ldsc to original implementation 27-May-08 JDB Added line connection order to tmxr_poll_conn, added tmxr_set_lnorder and tmxr_show_lnorder @@ -57,39 +63,270 @@ This library includes: - tmxr_poll_conn - poll for connection - tmxr_reset_ln - reset line - tmxr_getc_ln - get character for line - tmxr_poll_rx - poll receive - tmxr_putc_ln - put character for line - tmxr_poll_tx - poll transmit - tmxr_open_master - open master connection - tmxr_close_master - close master connection - tmxr_attach - attach terminal multiplexer - tmxr_detach - detach terminal multiplexer - tmxr_ex - (null) examine - tmxr_dep - (null) deposit - tmxr_msg - send message to socket - tmxr_linemsg - send message to line - tmxr_fconns - output connection status - tmxr_fstats - output connection statistics - tmxr_dscln - disconnect line (SET routine) - tmxr_rqln - number of available characters for line - tmxr_tqln - number of buffered characters for line - tmxr_set_lnorder - set line connection order - tmxr_show_lnorder - show line connection order - tmxr_show_open_devices - show info about all open tmxr devices - tmxr_startup - initialize the tmxr library - tmxr_shutdown - shutdown the tmxr library + tmxr_poll_conn - poll for connection + tmxr_reset_ln - reset line (drops Telnet/tcp and serial connections) + tmxr_getc_ln - get character for line + tmxr_poll_rx - poll receive + tmxr_putc_ln - put character for line + tmxr_poll_tx - poll transmit + tmxr_send_buffered_data - transmit buffered data + tmxr_set_modem_control_passthru - enable modem control on a multiplexer + tmxr_clear_modem_control_passthru - disable modem control on a multiplexer + tmxr_set_get_modem_bits - set and/or get a line modem bits + tmxr_set_config_line - set port speed, character size, parity and stop bits + tmxr_open_master - open master connection + tmxr_close_master - close master connection + tmxr_attach - attach terminal multiplexor to listening port + tmxr_detach - detach terminal multiplexor to listening port + tmxr_attach_help - help routine for attaching multiplexer devices + tmxr_set_line_unit - set the unit which polls for input for a given line + tmxr_ex - (null) examine + tmxr_dep - (null) deposit + tmxr_msg - send message to socket + tmxr_linemsg - send message to line + tmxr_fconns - output connection status + tmxr_fstats - output connection statistics + tmxr_set_log - enable logging for line + tmxr_set_nolog - disable logging for line + tmxr_show_log - show logging status for line + tmxr_dscln - disconnect line (SET routine) + tmxr_rqln - number of available characters for line + tmxr_tqln - number of buffered characters for line + tmxr_set_lnorder - set line connection order + tmxr_show_lnorder - show line connection order + tmxr_show_summ - show connection summary + tmxr_show_cstat - show line connections or status + tmxr_show_lines - show number of lines + tmxr_show_open_devices - show info about all open tmxr devices All routines are OS-independent. + + + This library supports the simulation of multiple-line terminal multiplexers. + It may also be used to create single-line "multiplexers" to provide + additional terminals beyond the simulation console. It may also be used to + create single-line or multi-line simulated synchronous (BiSync) devices. + Multiplexer lines may be connected to terminal emulators supporting the + Telnet protocol via sockets, or to hardware terminals via host serial + ports. Concurrent Telnet and serial connections may be mixed on a given + multiplexer. + + When connecting via sockets, the simulated multiplexer is attached to a + listening port on the host system: + + sim> attach MUX 23 + Listening on port 23 + + Once attached, the listening port must be polled for incoming connections. + When a connection attempt is received, it will be associated with the next + multiplexer line in the user-specified line order, or with the next line in + sequence if no order has been specified. Individual lines may be connected + to serial ports or remote systems via TCP (telnet or not as desired), OR + they may have separate listening TCP ports. + + Logging of Multiplexer Line output: + + The traffic going out multiplexer lines can be logged to files. A single + line multiplexer can log it's traffic with the following command: + + sim> atta MUX 23,Log=LogFileName + sim> atta MUX Connect=ser0,Log=LogFileName + + Specifying a Log value for a multi-line multiplexer is specifying a + template filename. The actual file name used for each line will be + the indicated filename with _n appended (n being the line number). + + Buffered Multiplexer Line: + + A Multiplexer Line Buffering has been implemented. A Buffered Line will + have a copy of the last 'buffer size' bytes of output retained in a line + specific buffer. The contents of this buffer will be transmitted out any + new connection on that line when a new telnet session is established. + + This capability is most useful for the Console Telnet session. When a + Console Telnet session is Buffered, a simulator will start (via BOOT CPU + or whatever is appropriate for a particular simulator) without needing to + have an active telnet connection. When a Telnet connection comes along + for the telnet port, the contents of the saved buffer (which wraps on + overflow) are presented on the telnet session as output before session + traffic. This allows the connecting telnet client to see what happened + before he connected since the likely reason he might be connecting to the + console of a background simulator is to troubleshoot unusual behavior, + the details of which may have already been sent to the console. + + Serial Port support: + + Serial ports may be specified as an operating system specific device names + or using simh generic serial names. simh generic names are of the form + serN, where N is from 0 thru one less than the maximum number of serial + ports on the local system. The mapping of simh generic port names to OS + specific names can be displayed using the following command: + + sim> show serial + Serial devices: + ser0 COM1 (\Device\Serial0) + ser1 COM3 (Winachcf0) + + sim> attach MUX Line=2,Connect=ser0 + + or equivalently + + sim> attach MUX Line=2,Connect=COM1 + + An optional configuration string may be present after the port name. If + present, it must be separated from the port name with a semicolon and has + this form: + + - + + where: + + rate = communication rate in bits per second + charsize = character size in bits (5-8, including optional parity) + parity = parity designator (N/E/O/M/S for no/even/odd/mark/space parity) + stopbits = number of stop bits (1, 1.5, or 2) + + As an example: + + 9600-8n1 + + The supported rates, sizes, and parity options are host-specific. If + a configuration string is not supplied, then the default of 9600-8N1 + is used. + + An attachment to a serial port with the '-V' switch will cause a + connection message to be output to the connected serial port. + This will help to confirm the correct port has been connected and + that the port settings are reasonable for the connected device. + This would be done as: + + sim> attach -V MUX Connect=SerN + + + Line specific tcp listening ports are supported. These are configured + using commands of the form: + + sim> attach MUX Line=2,port{;notelnet} + + Direct computer to computer connections (Virutal Null Modem cables) may + be established using the telnet protocol or via raw tcp sockets. + + sim> attach MUX Line=2,Connect=host:port{;notelnet} + + Computer to computer virtual connections can be one way (as illustrated + above) or symmetric. A symmetric connection is configured by combining + a one way connection with a tcp listening port on the same line: + + sim> attach MUX Line=2,Connect=host:port,listenport + + When symmetric virtual connections are configured, incoming connections + on the specified listening port are checked to assure that they actually + come from the specified connection destination host system. + + + + The command syntax for a single line device (MX) is: + + sim> attach MX port{;notelnet} + sim> attach MX Connect=serN{;config} + sim> attach MX Connect=COM9{;config} + sim> attach MX Connect=host:port{;notelnet} + + The command syntax for ANY multi-line device is: + + sim> attach MX port{;notelnet} ; Defines the master listening port for the mux and optionally allows non-telnet (i.e. raw socket) operation for all lines. + sim> attach MX Line=n,port{;notelnet} ; Defines a line specific listen port for a particular line. Each line can have a separate listen port and the mux can have its own as well. Optionally disable telnet wire protocol (i.e. raw socket) + sim> attach MX Line=n,Connect=serN{;config} ; Connects line n to simh generic serial port N (port list visible with the sim> SHOW SERIAL command), the optional ";config" data specifies the speed, parity and stop bits for the connection + ; DTR (and RTS) will be raised at attach time and will drop at detach/disconnect time + sim> attach MX Line=n,Connect=host:port{;notelnet} ; Causes a connection to be established to the designated host:port. The actual connection will happen in a non-blocking fashion and will be completed and/or re-established by the normal tmxr_poll_conn activities + + All connections configured for any multiplexer device are unconfigured by: + + sim> detach MX ; detaches ALL connections/ports/sessions on the MUX. + + Console serial connections are achieved by: + + sim> set console serial=serN{;config} + or + sim> set console serial=COM2{;config} + + A line specific listening port (12366) can be specified by the following: + + sim> attach MUX Line=2,12366 + + A line specific remote telnet (or raw tcp) destination can be specified + by the following: + + sim> attach MUX Line=2,Connect=remotehost:port + + If a connection to a remotehost:port wants a raw binary data channel + (instead of a telnet session) the following would be used: + + sim> attach MUX Line=2,Connect=remotehost:port;notelnet + + A single line multiplexor can indicate any of the above line options + without specifying a line number: + + sim> attach MUX Connect=ser0;9600-8N1 + sim> attach MUX 12366 + sim> attach MUX Connect=remotehost:port + sim> attach MUX Connect=remotehost:port;notelnet + + A multiplexor can disconnect all (telnet, serial and outgoing) previous + attachments with: + + sim> detach MUX + + A device emulation may choose to implement a command interface to + disconnect specific individual lines. This would usually be done via + a Unit Modifier table entry (MTAB) which dispatches the command + "SET dev DISCONNECT[=line]" to tmxr_dscln. This will cause a telnet + connection to be closed, but a serial port will normally have DTR + dropped for 500ms and raised again (thus hanging up a modem on that + serial port). + + sim> set MUX disconnect=2 + + A line which is connected to a serial port can be manually closed by + adding the -C switch to a disconnect command. + + sim> set -C MUX disconnect=2 + + Full Modem Control serial port support. + + This library supports devices which wish to emulate full modem + control/signalling for serial ports. Any device emulation which wishes + to support this functionality for attached serial ports must call + "tmxr_set_modem_control_passthru" before any call to tmxr_attach. + This disables automatic DTR (&RTS) manipulation by this library. + Responsibility for manipulating DTR falls on the simulated operating + system. Calling tmxr_set_modem_control_passthru would usually be in + a device reset routine. It may also be called by a device attach + routine based on user specified options. + Once support for full modem control has been declared by a device + emulation for a particular TMXR device, this library will make no + direct effort to manipulate modem bits while connected to serial ports. + The "tmxr_set_get_modem_bits" API exists to allow the device emulation + layer to query and control modem signals. The "tmxr_set_config_line" + API exists to allow the device emulation layer to change port settings + (baud rate, parity and stop bits). A modem_control enabled line + merely passes the VM's port status bits, data and settings through to + and from the serial port. + + The "tmxr_set_get_modem_bits" and "tmxr_set_config_line" APIs will + ONLY work on a modem control enabled TMXR device. + */ #define NOT_MUX_USING_CODE /* sim_tmxr library define */ #include "sim_defs.h" +#include "sim_serial.h" +#include "sim_sock.h" +#include "sim_timer.h" #include "sim_tmxr.h" #include "scp.h" + #include /* Telnet protocol constants - negatives are for init'ing signed char data */ @@ -133,15 +370,341 @@ #define TNS_DO 006 /* DO request pending rejection */ -void tmxr_rmvrc (TMLN *lp, int32 p); -int32 tmxr_send_buffered_data (TMLN *lp); -TMLN *tmxr_find_ldsc (UNIT *uptr, int32 val, TMXR *mp); -extern int32 sim_switches; -extern int32 sim_is_running; -extern char sim_name[]; -extern FILE *sim_log; -extern uint32 sim_os_msec (void); +/* Local routines */ + + +/* Initialize the line state. + + Reset the line state to represent an idle line. Note that we do not clear + all of the line structure members, so a connected line remains connected + after this call. + + Because a line break is represented by a flag in the "receive break status" + array, we must zero that array in order to clear any pending break + indications. +*/ + +static void tmxr_init_line (TMLN *lp) +{ +lp->tsta = 0; /* init telnet state */ +lp->xmte = 1; /* enable transmit */ +lp->dstb = 0; /* default bin mode */ +lp->rxbpr = lp->rxbpi = lp->rxcnt = 0; /* init receive indexes */ +if (!lp->txbfd) /* if not buffered */ + lp->txbpr = lp->txbpi = lp->txcnt = 0; /* init transmit indexes */ +memset (lp->rbr, 0, TMXR_MAXBUF); /* clear break status array */ +lp->txdrp = 0; +if (!lp->mp->buffered) { + lp->txbfd = 0; + lp->txbsz = TMXR_MAXBUF; + lp->txb = (char *)realloc (lp->txb, lp->txbsz); + } +return; +} + + +/* Report a connection to a line. + + If the indicated line (lp) is speaking the telnet wire protocol, a + notification of the form: + + Connected to the simulator device, line + + is sent to the newly connected line. If the device has only one line, the + "line " part is omitted. If the device has not been defined, the " + device" part is omitted. + +*/ + +static void tmxr_report_connection (TMXR *mp, TMLN *lp) +{ +int32 unwritten, psave; +char cmsg[80]; +char dmsg[80] = ""; +char lmsg[80] = ""; +char msgbuf[256] = ""; + +if ((!lp->notelnet) || (sim_switches & SWMASK ('V'))) { + sprintf (cmsg, "\n\r\nConnected to the %s simulator ", sim_name); + + if (mp->dptr) { /* device defined? */ + sprintf (dmsg, "%s device", /* report device name */ + sim_dname (mp->dptr)); + + if (mp->lines > 1) /* more than one line? */ + sprintf (lmsg, ", line %d", (int)(lp-mp->ldsc));/* report the line number */ + } + + sprintf (msgbuf, "%s%s%s\r\n\n", cmsg, dmsg, lmsg); + } + +if (!mp->buffered) { + lp->txbpi = 0; /* init buf pointers */ + lp->txbpr = (int32)(lp->txbsz - strlen (msgbuf)); + lp->rxcnt = lp->txcnt = lp->txdrp = 0; /* init counters */ + } +else + if (lp->txcnt > lp->txbsz) + lp->txbpr = (lp->txbpi + 1) % lp->txbsz; + else + lp->txbpr = (int32)(lp->txbsz - strlen (msgbuf)); + +psave = lp->txbpi; /* save insertion pointer */ +lp->txbpi = lp->txbpr; /* insert connection message */ +tmxr_linemsg (lp, msgbuf); /* beginning of buffer */ +lp->txbpi = psave; /* restore insertion pointer */ + +unwritten = tmxr_send_buffered_data (lp); /* send the message */ + +if (unwritten == 0) /* buffer now empty? */ + lp->xmte = 1; /* reenable transmission if paused */ + +lp->txcnt -= (int32)strlen (msgbuf); /* adjust statistics */ +return; +} + + +/* Report a disconnection to a line. + + A notification of the form: + + Disconnected from the simulator + + is sent to the line about to be disconnected. We do not flush the buffer + here, because the disconnect routines will do that just after calling us. +*/ + +static void tmxr_report_disconnection (TMLN *lp) +{ +if (lp->notelnet) + return; +tmxr_linemsg (lp, "\r\nDisconnected from the "); /* report disconnection */ +tmxr_linemsg (lp, sim_name); +tmxr_linemsg (lp, " simulator\r\n\n"); +return; +} + + +/* Read from a line. + + Up to "length" characters are read into the character buffer associated with + line "lp". The actual number of characters read is returned. If no + characters are available, 0 is returned. If an error occurred while reading, + -1 is returned. + + If a line break was detected on serial input, the associated receive break + status flag will be set. Line break indication for Telnet connections is + embedded in the Telnet protocol and must be determined externally. +*/ + +static int32 tmxr_read (TMLN *lp, int32 length) +{ +int32 i = lp->rxbpi; + +if (lp->serport) /* serial port connection? */ + return sim_read_serial (lp->serport, &(lp->rxb[i]), length, &(lp->rbr[i])); +else /* Telnet connection */ + return sim_read_sock (lp->sock, &(lp->rxb[i]), length); +} + + +/* Write to a line. + + Up to "length" characters are written from the character buffer associated + with "lp". The actual number of characters written is returned. If an error + occurred while writing, -1 is returned. +*/ + +static int32 tmxr_write (TMLN *lp, int32 length) +{ +int32 written; +int32 i = lp->txbpr; + +if (lp->serport) /* serial port connection? */ + return sim_write_serial (lp->serport, &(lp->txb[i]), length); + +else { /* Telnet connection */ + written = sim_write_sock (lp->sock, &(lp->txb[i]), length); + + if (written == SOCKET_ERROR) /* did an error occur? */ + return -1; /* return error indication */ + else + return written; + } +} + + +/* Remove a character from the read buffer. + + The character at position "p" in the read buffer associated with line "lp" is + removed by moving all of the following received characters down one position. + The receive break status array is adjusted accordingly. +*/ + +static void tmxr_rmvrc (TMLN *lp, int32 p) +{ +for ( ; p < lp->rxbpi; p++) { /* work from "p" through end of buffer */ + lp->rxb[p] = lp->rxb[p + 1]; /* slide following character down */ + lp->rbr[p] = lp->rbr[p + 1]; /* adjust break status too */ + } + +lp->rbr[p] = 0; /* clear potential break from vacated slot */ +lp->rxbpi = lp->rxbpi - 1; /* drop buffer insert index */ +return; +} + + +/* Find a line descriptor indicated by unit or number. + + If "uptr" is NULL, then the line descriptor is determined by the line number + passed in "val". If "uptr" is not NULL, then it must point to a unit + associated with a line, and the line descriptor is determined by the unit + number, which is derived by the position of the unit in the device's unit + array. + + Note: This routine may be called with a UNIT that does not belong to the + device indicated in the TMXR structure. That is, the multiplexer lines may + belong to a device other than the one attached to the socket (the HP 2100 MUX + device is one example). Therefore, we must look up the device from the unit + at each call, rather than depending on the DEVICE pointer stored in the TMXR. +*/ + +static TMLN *tmxr_find_ldsc (UNIT *uptr, int32 val, TMXR *mp) +{ +if (mp == NULL) /* invalid multiplexer descriptor? */ + return NULL; /* programming error! */ +if (uptr) { /* called from SET? */ + DEVICE *dptr = find_dev_from_unit (uptr); /* find device */ + if (dptr == NULL) /* what?? */ + return NULL; + val = (int32) (uptr - dptr->units); /* implicit line # */ + } +if ((val < 0) || (val >= mp->lines)) /* invalid line? */ + return NULL; +return mp->ldsc + val; /* line descriptor */ +} + + +/* Get a line descriptor indicated by a string or unit. + + A pointer to the line descriptor associated with multiplexer "mp" and unit + "uptr" or specified by string "cptr" is returned. If "uptr" is non-null, + then the unit number within its associated device implies the line number. + If "uptr" is null, then the string "cptr" is parsed for a decimal line + number. If the line number is missing, malformed, or outside of the range of + line numbers associated with "mp", then NULL is returned with status set to + SCPE_ARG. + + Implementation note: + + 1. A return status of SCPE_IERR implies a programming error (passing an + invalid pointer or an invalid unit). +*/ + +static TMLN *tmxr_get_ldsc (UNIT *uptr, char *cptr, TMXR *mp, t_stat *status) +{ +t_value ln; +TMLN *lp = NULL; +t_stat code = SCPE_OK; + +if (mp == NULL) /* missing mux descriptor? */ + code = SCPE_IERR; /* programming error! */ + +else if (uptr) { /* implied line form? */ + lp = tmxr_find_ldsc (uptr, mp->lines, mp); /* determine line from unit */ + + if (lp == NULL) /* invalid line number? */ + code = SCPE_IERR; /* programming error! */ + } + +else if (cptr == NULL) /* named line form, parameter supplied? */ + code = SCPE_ARG; /* no, so report missing */ + +else { + ln = get_uint (cptr, 10, mp->lines - 1, &code); /* get line number */ + + if (code == SCPE_OK) /* line number OK? */ + lp = mp->ldsc + (int32) ln; /* use as index to determine line */ + } + +if (status) /* return value pointer supplied? */ + *status = code; /* store return status value */ + +return lp; /* return pointer to line descriptor */ +} + +/* Generate the Attach string which will fully configure the multiplexer + + Inputs: + old = pointer to the original configuration string which will be replaced + *mp = pointer to multiplexer + + Output: + a complete attach string for the current state of the multiplexer + +*/ +static char *growstring(char **string, size_t growth) +{ +*string = (char *)realloc (*string, 1 + (*string ? strlen (*string) : 0) + growth); +return *string + strlen(*string); +} + +static char *_mux_attach_string(char *old, TMXR *mp) +{ +char* tptr = NULL; +int32 i; +TMLN *lp; + +free (old); +tptr = (char *) calloc (1, 1); + +if (tptr == NULL) /* no more mem? */ + return tptr; + +if (mp->port) /* copy port */ + sprintf (growstring(&tptr, 13 + strlen (mp->port)), "%s%s", mp->port, mp->notelnet ? ";notelnet" : ""); +if (mp->buffered) + sprintf (growstring(&tptr, 32), ",Buffered=%d", mp->buffered); +if (mp->logfiletmpl[0]) /* logfile info */ + sprintf (growstring(&tptr, 7 + strlen (mp->logfiletmpl)), ",Log=%s", mp->logfiletmpl); +while ((*tptr == ',') || (*tptr == ' ')) + strcpy(tptr, tptr+1); +for (i=0; ilines; ++i) { + lp = mp->ldsc + i; + if (lp->destination || lp->port) { + if (mp->lines > 1) + sprintf (growstring(&tptr, 32), "%sLine=%d", *tptr ? "," : "", i); + else + sprintf (growstring(&tptr, 32), "%s", *tptr ? "," : ""); + if (lp->destination) { + if (lp->serport) { + char portname[CBUFSIZE]; + + get_glyph_nc (lp->destination, portname, ';'); + sprintf (growstring(&tptr, 25 + strlen (lp->destination)), ",Connect=%s%s%s", portname, strcmp("9600-8N1", lp->serconfig) ? ";" : "", strcmp("9600-8N1", lp->serconfig) ? lp->serconfig : ""); + } + else + sprintf (growstring(&tptr, 18 + strlen (lp->destination)), ",Connect=%s%s", lp->destination, lp->notelnet ? ";notelnet" : ""); + } + if (lp->port) + sprintf (growstring(&tptr, 12 + strlen (lp->port)), ",%s%s", lp->port, lp->notelnet ? ";notelnet" : ""); + } + } +if (mp->lines == 1) + while ((*tptr == ',') || (*tptr == ' ')) + strcpy(tptr, tptr+1); +if (*tptr == '\0') { + free (tptr); + tptr = NULL; + } +return tptr; +} + + + +/* Global routines */ + /* Poll for new connection @@ -155,6 +718,7 @@ extern uint32 sim_os_msec (void); If a connection order is defined for the descriptor, and the first value is not -1 (indicating default order), then the order array is used to find an open line. Otherwise, a search is made of all lines in numerical sequence. + */ int32 tmxr_poll_conn (TMXR *mp) @@ -162,12 +726,10 @@ int32 tmxr_poll_conn (TMXR *mp) SOCKET newsock; TMLN *lp; int32 *op; -int32 i, j, psave; -uint32 ipaddr; -char cmsg[80]; -char dmsg[80] = ""; -char lmsg[80] = ""; -char msgbuf[256]; +int32 i, j; +char *address; +char msg[512]; +uint32 poll_time = sim_os_msec (); static char mantra[] = { TN_IAC, TN_WILL, TN_LINE, TN_IAC, TN_WILL, TN_SGA, @@ -176,96 +738,378 @@ static char mantra[] = { TN_IAC, TN_DO, TN_BIN }; +if (mp->last_poll_time == 0) { /* first poll initializations */ + UNIT *uptr = mp->uptr; + + if (!uptr) /* Attached ? */ + return -1; /* No connections are possinle! */ + + if (!(uptr->dynflags & TMUF_NOASYNCH)) { /* if asynch not disabled */ + uptr->dynflags |= UNIT_TM_POLL; /* tag as polling unit */ + sim_cancel (uptr); + } + for (i=0; i < mp->lines; i++) { + uptr = mp->ldsc[i].uptr ? mp->ldsc[i].uptr : mp->uptr; + + if (!(mp->uptr->dynflags & TMUF_NOASYNCH)) { /* if asynch not disabled */ + uptr->dynflags |= UNIT_TM_POLL; /* tag as polling unit */ + sim_cancel (uptr); + } + } + } + +if ((poll_time - mp->last_poll_time) < TMXR_CONNECT_POLL_INTERVAL) + return -1; /* too soon to try */ + tmxr_debug_trace (mp, "tmxr_poll_conn()"); -newsock = sim_accept_conn (mp->master, &ipaddr); /* poll connect */ -if (newsock != INVALID_SOCKET) { /* got a live one? */ - op = mp->lnorder; /* get line connection order list pointer */ - i = mp->lines; /* play it safe in case lines == 0 */ - ++mp->sessions; /* count the new session */ - for (j = 0; j < mp->lines; j++, i++) { /* find next avail line */ - if (op && (*op >= 0) && (*op < mp->lines)) /* order list present and valid? */ - i = *op++; /* get next line in list to try */ - else /* no list or not used or range error */ - i = j; /* get next sequential line */ +mp->last_poll_time = poll_time; - lp = mp->ldsc + i; /* get pointer to line descriptor */ - if (lp->conn == 0) /* is the line available? */ - break; /* yes, so stop search */ - } +/* Check for a pending Telnet connection */ - if (i >= mp->lines) { /* all busy? */ - tmxr_msg (newsock, "All connections busy\r\n"); - sim_close_sock (newsock, 0); - } - else { - lp = mp->ldsc + i; /* get line desc */ - lp->conn = newsock; /* record connection */ - lp->ipad = ipaddr; /* ip address */ - lp->mp = mp; /* save mux */ - sim_write_sock (newsock, mantra, sizeof(mantra)); - tmxr_debug (TMXR_DBG_XMT, lp, "Sending", mantra, sizeof(mantra)); - sprintf (cmsg, "\n\r\nConnected to the %s simulator ", sim_name); +if (mp->master) { + newsock = sim_accept_conn (mp->master, &address); /* poll connect */ - if (mp->dptr) { /* device defined? */ - sprintf (dmsg, "%s device", /* report device name */ - sim_dname (mp->dptr)); + if (newsock != INVALID_SOCKET) { /* got a live one? */ + sprintf (msg, "tmxr_poll_conn() - Connection from %s", address); + tmxr_debug_trace (mp, msg); + op = mp->lnorder; /* get line connection order list pointer */ + i = mp->lines; /* play it safe in case lines == 0 */ + ++mp->sessions; /* count the new session */ - if (mp->lines > 1) /* more than one line? */ - sprintf (lmsg, ", line %d", i); /* report the line number */ + for (j = 0; j < mp->lines; j++, i++) { /* find next avail line */ + if (op && (*op >= 0) && (*op < mp->lines)) /* order list present and valid? */ + i = *op++; /* get next line in list to try */ + else /* no list or not used or range error */ + i = j; /* get next sequential line */ + + lp = mp->ldsc + i; /* get pointer to line descriptor */ + if ((lp->conn == 0) && /* is the line available? */ + (lp->destination == NULL) && + (lp->master == 0)) + break; /* yes, so stop search */ } - sprintf (msgbuf, "%s%s%s\r\n\n", cmsg, dmsg, lmsg); - lp->cnms = sim_os_msec (); /* time of conn */ - if (!mp->buffered) { - lp->txbpi = 0; /* init buf pointers */ - lp->txbpr = (int32)(lp->txbsz - strlen (msgbuf)); - lp->rxcnt = lp->txcnt = lp->txdrp = 0; /* init counters */ + if (i >= mp->lines) { /* all busy? */ + tmxr_msg (newsock, "All connections busy\r\n"); + tmxr_debug_trace (mp, "tmxr_poll_conn() - All connections busy"); + sim_close_sock (newsock, 0); + free (address); } - else - if (lp->txcnt > lp->txbsz) - lp->txbpr = (lp->txbpi + 1) % lp->txbsz; - else - lp->txbpr = (int32)(lp->txbsz - strlen (msgbuf)); - lp->tsta = 0; /* init telnet state */ - lp->xmte = 1; /* enable transmit */ - lp->dstb = 0; /* default bin mode */ - psave = lp->txbpi; /* save insertion pointer */ - lp->txbpi = lp->txbpr; /* insert connection message */ - tmxr_linemsg (lp, msgbuf); /* beginning of buffer */ - lp->txbpi = psave; /* restore insertion pointer */ - tmxr_poll_tx (mp); /* flush output */ - lp->txcnt -= (int32)strlen (msgbuf); /* adjust statistics */ + else { + lp = mp->ldsc + i; /* get line desc */ + tmxr_init_line (lp); /* init line */ + lp->conn = TRUE; /* record connection */ + lp->sock = newsock; /* save socket */ + lp->ipad = address; /* ip address */ + lp->notelnet = mp->notelnet; /* apply mux default telnet setting */ + if (!lp->notelnet) { + sim_write_sock (newsock, mantra, sizeof(mantra)); + tmxr_debug (TMXR_DBG_XMT, lp, "Sending", mantra, sizeof(mantra)); + } + tmxr_report_connection (mp, lp); + lp->cnms = sim_os_msec (); /* time of connection */ + return i; + } + } /* end if newsock */ + } + +/* Look for per line listeners or outbound connecting sockets */ +for (i = 0; i < mp->lines; i++) { /* check each line in sequence */ + lp = mp->ldsc + i; /* get pointer to line descriptor */ + + if (lp->connecting) { /* connecting? */ + switch (sim_check_conn(lp->connecting, FALSE)) + { + case 1: /* successful connection */ + lp->conn = TRUE; /* record connection */ + lp->sock = lp->connecting; /* it now looks normal */ + lp->connecting = 0; + lp->ipad = realloc (lp->ipad, 1+strlen (lp->destination)); + strcpy (lp->ipad, lp->destination); + lp->cnms = sim_os_msec (); + break; + case -1: /* failed connection */ + tmxr_reset_ln (lp); /* retry */ + break; + } + } + + /* Check for a pending Telnet connection */ + + if (lp->master) { + + newsock = sim_accept_conn (lp->master, &address);/* poll connect */ + + if (newsock != INVALID_SOCKET) { /* got a live one? */ + sprintf (msg, "tmxr_poll_conn() - Line Connection from %s", address); + tmxr_debug_trace_line (lp, msg); + ++mp->sessions; /* count the new session */ + + if (lp->destination) { /* Virtual Null Modem Cable? */ + char host[CBUFSIZE]; + + if (sim_parse_addr (lp->destination, host, sizeof(host), NULL, NULL, 0, NULL, address)) { + tmxr_msg (newsock, "Rejecting connection from unexpected source\r\n"); + sprintf (msg, "tmxr_poll_conn() - Rejecting line connection from: %s, Expected: %s", address, host); + tmxr_debug_trace_line (lp, msg); + sim_close_sock (newsock, 0); + free (address); + continue; /* Move on to next line */ + } + if (lp->connecting) { + sim_close_sock (lp->connecting, 0); /* abort our as yet unconnnected socket */ + lp->connecting = 0; + } + } + if (lp->conn == 0) { /* is the line available? */ + tmxr_init_line (lp); /* init line */ + lp->conn = TRUE; /* record connection */ + lp->sock = newsock; /* save socket */ + lp->ipad = address; /* ip address */ + if (!lp->notelnet) { + sim_write_sock (newsock, mantra, sizeof(mantra)); + tmxr_debug (TMXR_DBG_XMT, lp, "Sending", mantra, sizeof(mantra)); + } + tmxr_report_connection (mp, lp); + lp->cnms = sim_os_msec (); /* time of connection */ + return i; + } + else { + tmxr_msg (newsock, "Line connection busy\r\n"); + tmxr_debug_trace_line (lp, "tmxr_poll_conn() - Line connection busy"); + sim_close_sock (newsock, 0); + free (address); + } + } + } + + /* Check for pending serial port connection notification */ + + if (lp->ser_connect_pending) { + lp->ser_connect_pending = FALSE; + lp->conn = TRUE; return i; } - } /* end if newsock */ -return -1; + } + +return -1; /* no new connections made */ } -/* Reset line */ +/* Reset a line. -void tmxr_reset_ln (TMLN *lp) + The telnet/tcp or serial session associated with multiplexer descriptor "mp" and + line descriptor "lp" is disconnected. An associated tcp socket is + closed; a serial port is closed if the closeserial parameter is true, otherwise + for non modem control serial lines DTR is dropped and raised again after 500ms + to signal the attached serial device. +*/ + +static t_stat tmxr_reset_ln_ex (TMLN *lp, t_bool closeserial) +{ +tmxr_debug_trace_line (lp, "tmxr_reset_ln_ex)"); + fflush (lp->txlog); /* flush log */ + +tmxr_send_buffered_data (lp); /* send any buffered data */ + +if (lp->serport) { + if (closeserial) { + sim_close_serial (lp->serport); + lp->serport = 0; + lp->ser_connect_pending = FALSE; + free (lp->destination); + lp->destination = NULL; + free (lp->serconfig); + lp->serconfig = NULL; + lp->cnms = 0; + lp->conn = FALSE; + lp->rcve = lp->xmte = 0; + } + else + if (!lp->mp->modem_control) { /* serial connection? */ + sim_control_serial (lp->serport, 0, TMXR_MDM_DTR|TMXR_MDM_RTS, NULL);/* drop DTR and RTS */ + sim_os_ms_sleep (TMXR_DTR_DROP_TIME); + sim_control_serial (lp->serport, TMXR_MDM_DTR|TMXR_MDM_RTS, 0, NULL);/* raise DTR and RTS */ + } + } +else /* Telnet connection */ + if (lp->sock) { + sim_close_sock (lp->sock, 0); /* close socket */ + lp->sock = 0; + lp->conn = FALSE; + lp->rcve = lp->xmte = 0; + } +free(lp->ipad); +lp->ipad = NULL; +if ((lp->destination) && (!lp->serport)) { + if (lp->connecting) + sim_close_sock (lp->connecting, 0); + lp->connecting = sim_connect_sock (lp->destination, "localhost", NULL); + } +tmxr_init_line (lp); /* initialize line state */ +/* Revise the unit's connect string to reflect the current attachments */ +lp->mp->uptr->filename = _mux_attach_string (lp->mp->uptr->filename, lp->mp); +/* No connections or listeners exist, then we're equivalent to being fully detached. We should reflect that */ +if (lp->mp->uptr->filename == NULL) + tmxr_detach (lp->mp, lp->mp->uptr); +return SCPE_OK; +} + +t_stat tmxr_close_ln (TMLN *lp) +{ +tmxr_debug_trace_line (lp, "tmxr_close_ln()"); +return tmxr_reset_ln_ex (lp, TRUE); +} + +t_stat tmxr_reset_ln (TMLN *lp) { tmxr_debug_trace_line (lp, "tmxr_reset_ln()"); -if (lp->txlog) /* dump log */ - fflush (lp->txlog); -tmxr_send_buffered_data (lp); /* send buffered data */ -sim_close_sock (lp->conn, 0); /* reset conn */ -lp->conn = lp->tsta = 0; /* reset state */ -lp->rxbpr = lp->rxbpi = 0; -if (!lp->txbfd) - lp->txbpr = lp->txbpi = 0; -lp->xmte = 1; -lp->dstb = 0; -return; +return tmxr_reset_ln_ex (lp, FALSE); } +/* Enable modem control pass thru + + Inputs: + none + + Output: + none + + Implementation note: + + 1 Calling this API disables any actions on the part of this + library to directly manipulate DTR (&RTS) on serial ports. + + 2 Calling this API enables the tmxr_set_get_modem_bits and + tmxr_set_config_line APIs. + +*/ +t_stat tmxr_set_modem_control_passthru (TMXR *mp) +{ +mp->modem_control = TRUE; +return SCPE_OK; +} + +/* Disable modem control pass thru + + Inputs: + none + + Output: + none + + Implementation note: + + 1 Calling this API enables this library's direct manipulation + of DTR (&RTS) on serial ports. + + 2 Calling this API disables the tmxr_set_get_modem_bits and + tmxr_set_config_line APIs. + + 3 This API will only change the state of the modem control processing + of this library if there are no listening ports, serial ports or + outgoing connecctions associated with the specified multiplexer + +*/ +t_stat tmxr_clear_modem_control_passthru (TMXR *mp) +{ +int i; + +if (!mp->modem_control) + return SCPE_OK; +if (mp->master) + return SCPE_ALATT; +for (i=0; ilines; ++i) { + TMLN *lp; + + lp = mp->ldsc + i; + if ((lp->master) || + (lp->sock) || + (lp->connecting) || + (lp->serport)) + return SCPE_ALATT; + } +mp->modem_control = FALSE; +return SCPE_OK; +} + +/* Manipulate the modem control bits of a specific line + + Inputs: + *lp = pointer to terminal line descriptor + bits_to_set TMXR_MDM_DTR and/or TMXR_MDM_RTS as desired + bits_to_clear TMXR_MDM_DTR and/or TMXR_MDM_RTS as desired + + Output: + incoming_bits if non NULL, returns the current stat of DCD, + RNG, CTS and DSR + + Implementation note: + + If a line is connected to a serial port, then these valus affect + and reflect the state of the serial port. If the line is connected + to a network socket (or could be) then the network session state is + set, cleared and/or returned. +*/ +t_stat tmxr_set_get_modem_bits (TMLN *lp, int32 bits_to_set, int32 bits_to_clear, int32 *incoming_bits) +{ +t_stat r = SCPE_OK; + +tmxr_debug_trace_line (lp, "tmxr_set_get_modem_bits()"); + +if (!lp->mp->modem_control) /* This API ONLY works on modem_control enabled multiplexers */ + return SCPE_IERR; +if ((bits_to_set & ~(TMXR_MDM_OUTGOING)) || /* Assure only settable bits */ + (bits_to_clear & ~(TMXR_MDM_OUTGOING)) || + (bits_to_set & bits_to_clear)) /* and can't set and clear the same bits */ + return SCPE_ARG; +if (lp->serport) + return sim_control_serial (lp->serport, bits_to_set, bits_to_clear, incoming_bits); +if (lp->sock) { + if (bits_to_clear&TMXR_MDM_DTR) /* drop DTR? */ + tmxr_reset_ln (lp); + } +if (incoming_bits) { + if (lp->sock) + *incoming_bits = TMXR_MDM_DCD | TMXR_MDM_CTS | TMXR_MDM_DSR; + else + *incoming_bits = lp->mp->master ? (TMXR_MDM_CTS | TMXR_MDM_DSR) : 0; + } +return r; +} + +t_stat tmxr_set_config_line (TMLN *lp, char *config) +{ +t_stat r; + +tmxr_debug_trace_line (lp, "tmxr_set_config_line()"); +if (!lp->mp->modem_control) /* This API ONLY works on modem_control enabled multiplexers */ + return SCPE_IERR; +if (lp->serport) + r = sim_config_serial (lp->serport, config); +else { + lp->serconfig = (char *)realloc (lp->serconfig, 1 + strlen (config)); + strcpy (lp->serconfig, config); + r = SCPE_OK; + } +if (r == SCPE_OK) /* Record port state for proper restore */ + lp->mp->uptr->filename = _mux_attach_string (lp->mp->uptr->filename, lp->mp); +return r; +} + + /* Get character from specific line Inputs: *lp = pointer to terminal line descriptor Output: valid + char, 0 if line + + Implementation note: + + 1. If a line break was detected coincident with the current character, the + receive break status associated with the character is cleared, and + SCPE_BREAK is ORed into the return value. */ int32 tmxr_getc_ln (TMLN *lp) @@ -279,8 +1123,10 @@ if (lp->conn && lp->rcve) { /* conn & enb? */ if (j) { /* any? */ tmp = lp->rxb[lp->rxbpr]; /* get char */ val = TMXR_VALID | (tmp & 0377); /* valid + chr */ - if (lp->rbr[lp->rxbpr]) /* break? */ - val = val | SCPE_BREAK; + if (lp->rbr[lp->rxbpr]) { /* break? */ + lp->rbr[lp->rxbpr] = 0; /* clear status */ + val = val | SCPE_BREAK; /* indicate to caller */ + } lp->rxbpr = lp->rxbpr + 1; /* adv pointer */ } } /* end if conn */ @@ -289,6 +1135,7 @@ if (lp->rxbpi == lp->rxbpr) /* empty? zero ptrs */ return val; } + /* Poll for input Inputs: @@ -304,132 +1151,132 @@ TMLN *lp; tmxr_debug_trace (mp, "tmxr_poll_rx()"); for (i = 0; i < mp->lines; i++) { /* loop thru lines */ lp = mp->ldsc + i; /* get line desc */ - if (!lp->conn) /* skip if !conn */ + if (!(lp->sock || lp->serport) || !lp->rcve) /* skip if not connected */ continue; nbytes = 0; if (lp->rxbpi == 0) /* need input? */ - nbytes = sim_read_sock (lp->conn, /* yes, read */ - &(lp->rxb[lp->rxbpi]), /* leave spc for */ - TMXR_MAXBUF - TMXR_GUARD); /* Telnet cruft */ + nbytes = tmxr_read (lp, /* yes, read */ + TMXR_MAXBUF - TMXR_GUARD); /* leave spc for Telnet cruft */ else if (lp->tsta) /* in Telnet seq? */ - nbytes = sim_read_sock (lp->conn, /* yes, read to end */ - &(lp->rxb[lp->rxbpi]), + nbytes = tmxr_read (lp, /* yes, read to end */ TMXR_MAXBUF - lp->rxbpi); - if (nbytes < 0) /* closed? reset ln */ - tmxr_reset_ln (lp); + + if (nbytes < 0) { /* line error? */ + if (!lp->txbfd) + lp->txbpi = lp->txbpr = 0; /* Drop the data we already know we can't send */ + tmxr_close_ln (lp); /* disconnect line */ + } + else if (nbytes > 0) { /* if data rcvd */ tmxr_debug (TMXR_DBG_RCV, lp, "Received", &(lp->rxb[lp->rxbpi]), nbytes); j = lp->rxbpi; /* start of data */ - memset (&lp->rbr[j], 0, nbytes); /* clear status */ lp->rxbpi = lp->rxbpi + nbytes; /* adv pointers */ lp->rxcnt = lp->rxcnt + nbytes; /* Examine new data, remove TELNET cruft before making input available */ - for (; j < lp->rxbpi; ) { /* loop thru char */ - signed char tmp = lp->rxb[j]; /* get char */ - switch (lp->tsta) { /* case tlnt state */ + if (!lp->notelnet) { /* Are we looking for telnet interpretation? */ + for (; j < lp->rxbpi; ) { /* loop thru char */ + signed char tmp = lp->rxb[j]; /* get char */ + switch (lp->tsta) { /* case tlnt state */ - case TNS_NORM: /* normal */ - if (tmp == TN_IAC) { /* IAC? */ - lp->tsta = TNS_IAC; /* change state */ + case TNS_NORM: /* normal */ + if (tmp == TN_IAC) { /* IAC? */ + lp->tsta = TNS_IAC; /* change state */ + tmxr_rmvrc (lp, j); /* remove char */ + break; + } + if ((tmp == TN_CR) && lp->dstb) /* CR, no bin */ + lp->tsta = TNS_CRPAD; /* skip pad char */ + j = j + 1; /* advance j */ + break; + + case TNS_IAC: /* IAC prev */ + if (tmp == TN_IAC) { /* IAC + IAC */ + lp->tsta = TNS_NORM; /* treat as normal */ + j = j + 1; /* advance j */ + break; /* keep IAC */ + } + if (tmp == TN_BRK) { /* IAC + BRK? */ + lp->tsta = TNS_NORM; /* treat as normal */ + lp->rxb[j] = 0; /* char is null */ + lp->rbr[j] = 1; /* flag break */ + j = j + 1; /* advance j */ + break; + } + switch (tmp) { + case TN_WILL: /* IAC + WILL? */ + lp->tsta = TNS_WILL; + break; + case TN_WONT: /* IAC + WONT? */ + lp->tsta = TNS_WONT; + break; + case TN_DO: /* IAC + DO? */ + lp->tsta = TNS_DO; + break; + case TN_DONT: /* IAC + DONT? */ + lp->tsta = TNS_SKIP; /* IAC + other */ + break; + case TN_GA: case TN_EL: /* IAC + other 2 byte types */ + case TN_EC: case TN_AYT: + case TN_AO: case TN_IP: + case TN_NOP: + lp->tsta = TNS_NORM; /* ignore */ + break; + case TN_SB: /* IAC + SB sub-opt negotiation */ + case TN_DATAMK: /* IAC + data mark */ + case TN_SE: /* IAC + SE sub-opt end */ + lp->tsta = TNS_NORM; /* ignore */ + break; + } tmxr_rmvrc (lp, j); /* remove char */ break; - } - if ((tmp == TN_CR) && lp->dstb) /* CR, no bin */ - lp->tsta = TNS_CRPAD; /* skip pad char */ - j = j + 1; /* advance j */ - break; - case TNS_IAC: /* IAC prev */ - if (tmp == TN_IAC) { /* IAC + IAC */ - lp->tsta = TNS_NORM; /* treat as normal */ - j = j + 1; /* advance j */ - break; /* keep IAC */ - } - if (tmp == TN_BRK) { /* IAC + BRK? */ - lp->tsta = TNS_NORM; /* treat as normal */ - lp->rxb[j] = 0; /* char is null */ - lp->rbr[j] = 1; /* flag break */ - j = j + 1; /* advance j */ - break; - } - switch (tmp) { - case TN_WILL: /* IAC + WILL? */ - lp->tsta = TNS_WILL; - break; - case TN_WONT: /* IAC + WONT? */ - lp->tsta = TNS_WONT; - break; - case TN_DO: /* IAC + DO? */ - lp->tsta = TNS_DO; - break; - case TN_DONT: /* IAC + DONT? */ - lp->tsta = TNS_SKIP; /* IAC + other */ - break; - case TN_GA: case TN_EL: /* IAC + other 2 byte types */ - case TN_EC: case TN_AYT: - case TN_AO: case TN_IP: - case TN_NOP: - lp->tsta = TNS_NORM; /* ignore */ - break; - case TN_SB: /* IAC + SB sub-opt negotiation */ - case TN_DATAMK: /* IAC + data mark */ - case TN_SE: /* IAC + SE sub-opt end */ - lp->tsta = TNS_NORM; /* ignore */ - break; - } - tmxr_rmvrc (lp, j); /* remove char */ - break; - - case TNS_WILL: case TNS_WONT: /* IAC+WILL/WONT prev */ - if (tmp == TN_BIN) { /* BIN? */ - if (lp->tsta == TNS_WILL) - lp->dstb = 0; - else lp->dstb = 1; - } - tmxr_rmvrc (lp, j); /* remove it */ - lp->tsta = TNS_NORM; /* next normal */ - break; - - /* Negotiation with the HP terminal emulator "QCTerm" is not working. - QCTerm says "WONT BIN" but sends bare CRs. RFC 854 says: - - Note that "CR LF" or "CR NUL" is required in both directions - (in the default ASCII mode), to preserve the symmetry of the - NVT model. ...The protocol requires that a NUL be inserted - following a CR not followed by a LF in the data stream. - - Until full negotiation is implemented, we work around the problem - by checking the character following the CR in non-BIN mode and - strip it only if it is LF or NUL. This should not affect - conforming clients. - */ - - case TNS_CRPAD: /* only LF or NUL should follow CR */ - lp->tsta = TNS_NORM; /* next normal */ - if ((tmp == TN_LF) || /* CR + LF ? */ - (tmp == TN_NUL)) /* CR + NUL? */ + case TNS_WILL: case TNS_WONT: /* IAC+WILL/WONT prev */ + if (tmp == TN_BIN) { /* BIN? */ + if (lp->tsta == TNS_WILL) + lp->dstb = 0; + else lp->dstb = 1; + } tmxr_rmvrc (lp, j); /* remove it */ - break; + lp->tsta = TNS_NORM; /* next normal */ + break; - case TNS_DO: /* pending DO request */ - case TNS_SKIP: default: /* skip char */ - tmxr_rmvrc (lp, j); /* remove char */ - lp->tsta = TNS_NORM; /* next normal */ - break; - } /* end case state */ - } /* end for char */ - if (nbytes != (lp->rxbpi-lp->rxbpr)) + /* Negotiation with the HP terminal emulator "QCTerm" is not working. + QCTerm says "WONT BIN" but sends bare CRs. RFC 854 says: + + Note that "CR LF" or "CR NUL" is required in both directions + (in the default ASCII mode), to preserve the symmetry of the + NVT model. ...The protocol requires that a NUL be inserted + following a CR not followed by a LF in the data stream. + + Until full negotiation is implemented, we work around the problem + by checking the character following the CR in non-BIN mode and + strip it only if it is LF or NUL. This should not affect + conforming clients. + */ + + case TNS_CRPAD: /* only LF or NUL should follow CR */ + lp->tsta = TNS_NORM; /* next normal */ + if ((tmp == TN_LF) || /* CR + LF ? */ + (tmp == TN_NUL)) /* CR + NUL? */ + tmxr_rmvrc (lp, j); /* remove it */ + break; + + case TNS_DO: /* pending DO request */ + case TNS_SKIP: default: /* skip char */ + tmxr_rmvrc (lp, j); /* remove char */ + lp->tsta = TNS_NORM; /* next normal */ + break; + } /* end case state */ + } /* end for char */ + if (nbytes != (lp->rxbpi-lp->rxbpr)) { tmxr_debug (TMXR_DBG_RCV, lp, "Remaining", &(lp->rxb[lp->rxbpi]), lp->rxbpi-lp->rxbpr); - if (!lp->rcve) { - nbytes = lp->rxbpi-lp->rxbpr; - lp->rxbpi = lp->rxbpi - nbytes; /* reverse pointers */ - tmxr_debug (TMXR_DBG_RCV, lp, "Receive Disabled...Discarding", &(lp->rxb[lp->rxbpi]), nbytes); } + } } /* end else nbytes */ } /* end for lines */ for (i = 0; i < mp->lines; i++) { /* loop thru lines */ @@ -440,6 +1287,7 @@ for (i = 0; i < mp->lines; i++) { /* loop thru lines */ return; } + /* Return count of available characters for line */ int32 tmxr_rqln (TMLN *lp) @@ -447,17 +1295,6 @@ int32 tmxr_rqln (TMLN *lp) return (lp->rxbpi - lp->rxbpr + ((lp->rxbpi < lp->rxbpr)? TMXR_MAXBUF: 0)); } -/* Remove character p (and matching status) from line l input buffer */ - -void tmxr_rmvrc (TMLN *lp, int32 p) -{ -for ( ; p < lp->rxbpi; p++) { - lp->rxb[p] = lp->rxb[p + 1]; - lp->rbr[p] = lp->rbr[p + 1]; - } -lp->rxbpi = lp->rxbpi - 1; -return; -} /* Store character in line buffer @@ -466,37 +1303,35 @@ return; chr = character Outputs: status = ok, connection lost, or stall + + Implementation note: + + 1. If the line is not connected, SCPE_LOST is returned. */ t_stat tmxr_putc_ln (TMLN *lp, int32 chr) { -if ((lp->conn == 0) && /* no conn & */ - (!(lp->mp && lp->mp->buffered))) { /* not buffered? */ +if ((lp->conn == FALSE) && /* no conn & not buffered? */ + (!lp->txbfd)) { ++lp->txdrp; /* lost */ return SCPE_LOST; } tmxr_debug_trace_line (lp, "tmxr_putc_ln()"); -if (lp->txlog) /* log if available */ - fputc (chr, lp->txlog); #define TXBUF_AVAIL(lp) (lp->txbsz - tmxr_tqln (lp)) #define TXBUF_CHAR(lp, c) { \ lp->txb[lp->txbpi++] = (char)(c); \ - ++lp->mp->txcount; \ lp->txbpi %= lp->txbsz; \ - if (lp->txbpi == lp->txbpr) { \ - lp->txbpr = (1+lp->txbpr)%lp->txbsz; \ - ++lp->txdrp; \ - } \ + if (lp->txbpi == lp->txbpr) \ + lp->txbpr = (1+lp->txbpr)%lp->txbsz, ++lp->txdrp; \ } if ((lp->txbfd) || (TXBUF_AVAIL(lp) > 1)) { /* room for char (+ IAC)? */ - if (TN_IAC == (char) chr) /* char == IAC ? */ + if ((TN_IAC == (char) chr) && (!lp->notelnet)) /* char == IAC in telnet session? */ TXBUF_CHAR (lp, TN_IAC); /* stuff extra IAC char */ TXBUF_CHAR (lp, chr); /* buffer char & adv pointer */ - if ((!lp->txbfd) && (TXBUF_AVAIL (lp) <= TMXR_GUARD)) {/* near full? */ + if ((!lp->txbfd) && (TXBUF_AVAIL (lp) <= TMXR_GUARD))/* near full? */ lp->xmte = 0; /* disable line */ - if (0 == tmxr_send_buffered_data (lp)) /* try to flush now */ - lp->xmte = 1; /* re-enable since empty now */ - } + if (lp->txlog) /* log if available */ + fputc (chr, lp->txlog); return SCPE_OK; /* char sent */ } ++lp->txdrp; lp->xmte = 0; /* no room, dsbl line */ @@ -519,22 +1354,24 @@ TMLN *lp; tmxr_debug_trace (mp, "tmxr_poll_tx()"); for (i = 0; i < mp->lines; i++) { /* loop thru lines */ lp = mp->ldsc + i; /* get line desc */ - if (lp->conn == 0) /* skip if !conn */ + if (!lp->conn) /* skip if !conn */ continue; - nbytes = tmxr_send_buffered_data (lp); /* buffered bytes */ - if (nbytes == 0) /* buf empty? enab line */ - lp->xmte = 1; -#if defined(SIM_ASYNCH_IO) - if (lp->uptr && - (lp->uptr->flags & UNIT_TM_POLL) && + nbytes = tmxr_send_buffered_data (lp); /* buffered bytes */ + if (nbytes == 0) { /* buf empty? enab line */ +#if defined(SIM_ASYNCH_IO) && defined(SIM_ASYNCH_MUX) + UNIT *ruptr = lp->uptr ? lp->uptr : lp->mp->uptr; + if ((ruptr->dynflags & UNIT_TM_POLL) && sim_asynch_enabled && tmxr_rqln (lp)) - _sim_activate (lp->uptr, 0); + _sim_activate (ruptr, 0); #endif - } /* end for */ + lp->xmte = 1; /* enable line transmit */ + } + } /* end for */ return; } + /* Send buffered data across network Inputs: @@ -551,11 +1388,11 @@ tmxr_debug_trace_line (lp, "tmxr_send_buffered_data()"); nbytes = tmxr_tqln(lp); /* avail bytes */ if (nbytes) { /* >0? write */ if (lp->txbpr < lp->txbpi) /* no wrap? */ - sbytes = sim_write_sock (lp->conn, /* write all data */ - &(lp->txb[lp->txbpr]), nbytes); - else sbytes = sim_write_sock (lp->conn, /* write to end buf */ - &(lp->txb[lp->txbpr]), lp->txbsz - lp->txbpr); - if (sbytes != SOCKET_ERROR) { /* ok? */ + sbytes = tmxr_write (lp, nbytes); /* write all data */ + else + sbytes = tmxr_write (lp, lp->txbsz - lp->txbpr);/* write to end buf */ + + if (sbytes >= 0) { /* ok? */ tmxr_debug (TMXR_DBG_XMT, lp, "Sent", &(lp->txb[lp->txbpr]), sbytes); lp->txbpr = (lp->txbpr + sbytes); /* update remove ptr */ if (lp->txbpr >= lp->txbsz) /* wrap? */ @@ -563,9 +1400,14 @@ if (nbytes) { /* >0? write */ lp->txcnt = lp->txcnt + sbytes; /* update counts */ nbytes = nbytes - sbytes; } + if (sbytes < 0) { /* I/O Error? */ + lp->txbpi = lp->txbpr = 0; /* Drop the data we already know we can't send */ + tmxr_close_ln (lp); /* close line/port on error */ + return nbytes; /* done now. */ + } if (nbytes && (lp->txbpr == 0)) { /* more data and wrap? */ - sbytes = sim_write_sock (lp->conn, lp->txb, nbytes); - if (sbytes != SOCKET_ERROR) { /* ok */ + sbytes = tmxr_write (lp, nbytes); + if (sbytes > 0) { /* ok */ tmxr_debug (TMXR_DBG_XMT, lp, "Sent", lp->txb, sbytes); lp->txbpr = (lp->txbpr + sbytes); /* update remove ptr */ if (lp->txbpr >= lp->txbsz) /* wrap? */ @@ -578,6 +1420,7 @@ if (nbytes) { /* >0? write */ return nbytes; } + /* Return count of buffered characters for line */ int32 tmxr_tqln (TMLN *lp) @@ -585,80 +1428,337 @@ int32 tmxr_tqln (TMLN *lp) return (lp->txbpi - lp->txbpr + ((lp->txbpi < lp->txbpr)? lp->txbsz: 0)); } -/* Open master socket */ +static void _mux_detach_line (TMLN *lp, t_bool close_listener, t_bool close_connecting) +{ +if (close_listener && lp->master) { + sim_close_sock (lp->master, 1); + lp->master = 0; + free (lp->port); + lp->port = NULL; + } +if (lp->sock) { /* if existing tcp, drop it */ + tmxr_report_disconnection (lp); /* report disconnection */ + tmxr_reset_ln (lp); + } +if (close_connecting) { + free (lp->destination); + lp->destination = NULL; + if (lp->connecting) { /* if existing outgoing tcp, drop it */ + lp->sock = lp->connecting; + lp->connecting = 0; + tmxr_reset_ln (lp); + } + } +if (lp->serport) { /* close current serial connection */ + tmxr_reset_ln (lp); + sim_control_serial (lp->serport, 0, TMXR_MDM_DTR|TMXR_MDM_RTS, NULL);/* drop DTR and RTS */ + sim_close_serial (lp->serport); + lp->serport = 0; + free (lp->serconfig); + lp->serconfig = NULL; + free (lp->destination); + lp->destination = NULL; + } +} + +/* Open a master listening socket (and all of the other variances of connections). + + A listening socket for the port number described by "cptr" is opened for the + multiplexer associated with descriptor "mp". If the open is successful, all + lines not currently otherwise connected (via serial, outgoing or direct + listener) are initialized for Telnet connections. + + Initialization for all connection styles (MUX wide listener, per line serial, + listener, outgoing, logging, buffering) are handled by this routine. + +*/ t_stat tmxr_open_master (TMXR *mp, char *cptr) { -int32 i, port; +int32 i, line, nextline = -1; +char tbuf[CBUFSIZE], listen[CBUFSIZE], destination[CBUFSIZE], + logfiletmpl[CBUFSIZE], buffered[CBUFSIZE], hostport[CBUFSIZE], + port[CBUFSIZE], option[CBUFSIZE]; SOCKET sock; +SERHANDLE serport; +char *tptr = cptr; +t_bool nolog, notelnet, listennotelnet, unbuffered; TMLN *lp; -t_stat r; +t_stat r = SCPE_ARG; tmxr_debug_trace (mp, "tmxr_open_master()"); -if (!isdigit(*cptr)) { - char gbuf[CBUFSIZE]; - cptr = get_glyph (cptr, gbuf, '='); - if (0 == MATCH_CMD (gbuf, "LOG")) { - if ((NULL == cptr) || ('\0' == *cptr)) - return SCPE_2FARG; - strncpy(mp->logfiletmpl, cptr, sizeof(mp->logfiletmpl)-1); - for (i = 0; i < mp->lines; i++) { - lp = mp->ldsc + i; +while (*tptr) { + line = nextline; + memset(logfiletmpl, '\0', sizeof(logfiletmpl)); + memset(listen, '\0', sizeof(listen)); + memset(destination, '\0', sizeof(destination)); + memset(buffered, '\0', sizeof(buffered)); + memset(port, '\0', sizeof(port)); + memset(option, '\0', sizeof(option)); + nolog = notelnet = listennotelnet = unbuffered = FALSE; + while (*tptr) { + tptr = get_glyph_nc (tptr, tbuf, ','); + if (!tbuf[0]) + break; + cptr = tbuf; + if (!isdigit(*cptr)) { + char gbuf[CBUFSIZE]; + char *init_cptr = cptr; + + cptr = get_glyph (cptr, gbuf, '='); + if (0 == MATCH_CMD (gbuf, "LINE")) { + if ((NULL == cptr) || ('\0' == *cptr)) + return SCPE_ARG; + nextline = (int32) get_uint (cptr, 10, mp->lines, &r); + if ((r != SCPE_OK) || (mp->lines == 1)) + return SCPE_ARG; + break; + } + if (0 == MATCH_CMD (gbuf, "LOG")) { + if ((NULL == cptr) || ('\0' == *cptr)) + return SCPE_2FARG; + strncpy(logfiletmpl, cptr, sizeof(logfiletmpl)-1); + continue; + } + if ((0 == MATCH_CMD (gbuf, "NOBUFFERED")) || + (0 == MATCH_CMD (gbuf, "UNBUFFERED"))) { + if ((NULL != cptr) && ('\0' != *cptr)) + return SCPE_2MARG; + unbuffered = TRUE; + continue; + } + if (0 == MATCH_CMD (gbuf, "BUFFERED")) { + if ((NULL == cptr) || ('\0' == *cptr)) + strcpy(buffered, "32768"); + else { + i = (int32) get_uint (cptr, 10, 1024*1024, &r); + if ((r != SCPE_OK) || (i == 0)) + return SCPE_ARG; + sprintf(buffered, "%d", i); + } + continue; + } + if (0 == MATCH_CMD (gbuf, "NOLOG")) { + if ((NULL != cptr) && ('\0' != *cptr)) + return SCPE_2MARG; + nolog = TRUE; + continue; + } + if (0 == MATCH_CMD (gbuf, "CONNECT")) { + if ((NULL == cptr) || ('\0' == *cptr)) + return SCPE_ARG; + serport = sim_open_serial (cptr, NULL, &r); + if (serport != INVALID_HANDLE) { + sim_close_serial (serport); + if (strchr (cptr, ';') && mp->modem_control) + return SCPE_ARG; + } + else { + memset (hostport, '\0', sizeof(hostport)); + strncpy (hostport, cptr, sizeof(hostport)-1); + if ((cptr = strchr (hostport, ';'))) + *(cptr++) = '\0'; + sock = sim_connect_sock (hostport, "localhost", NULL); + if (sock != INVALID_SOCKET) + sim_close_sock (sock, 0); + else + return SCPE_ARG; + if (cptr) + get_glyph (cptr, cptr, 0); /* upcase this string */ + if (0 == MATCH_CMD (cptr, "NOTELNET")) + notelnet = TRUE; + cptr = hostport; + } + strcpy(destination, cptr); + continue; + } + cptr = get_glyph (gbuf, port, ';'); + if (SCPE_OK != sim_parse_addr (port, NULL, 0, NULL, NULL, 0, NULL, NULL)) + return SCPE_ARG; + if (cptr) + get_glyph (cptr, cptr, 0); /* upcase this string */ + if (0 == MATCH_CMD (cptr, "NOTELNET")) + listennotelnet = TRUE; + cptr = init_cptr; + } + cptr = get_glyph_nc (cptr, port, ';'); + sock = sim_master_sock (port, &r); /* make master socket */ + if (r != SCPE_OK) + return r; + if (sock == INVALID_SOCKET) /* open error */ + return SCPE_OPENERR; + sim_close_sock (sock, 1); + strcpy(listen, port); + cptr = get_glyph (cptr, option, ';'); + if (0 == MATCH_CMD (option, "NOTELNET")) + listennotelnet = TRUE; + } + if (line == -1) { + if (logfiletmpl[0]) { + strncpy(mp->logfiletmpl, logfiletmpl, sizeof(mp->logfiletmpl)-1); + for (i = 0; i < mp->lines; i++) { + lp = mp->ldsc + i; + sim_close_logfile (&lp->txlogref); + lp->txlog = NULL; + lp->txlogname = (char *)realloc(lp->txlogname, CBUFSIZE); + if (mp->lines > 1) + sprintf(lp->txlogname, "%s_%d", mp->logfiletmpl, i); + else + strcpy(lp->txlogname, mp->logfiletmpl); + r = sim_open_logfile (lp->txlogname, TRUE, &lp->txlog, &lp->txlogref); + if (r == SCPE_OK) + setvbuf(lp->txlog, NULL, _IOFBF, 65536); + else { + free (lp->txlogname); + lp->txlogname = NULL; + break; + } + } + } + if (unbuffered) { + if (mp->buffered) { + mp->buffered = 0; + for (i = 0; i < mp->lines; i++) { /* default line buffers */ + lp = mp->ldsc + i; + lp->txbsz = TMXR_MAXBUF; + lp->txb = (char *)realloc(lp->txb, lp->txbsz); + lp->txbfd = lp->txbpi = lp->txbpr = 0; + } + } + } + if (buffered[0]) { + mp->buffered = atoi(buffered); + for (i = 0; i < mp->lines; i++) { /* initialize line buffers */ + lp = mp->ldsc + i; + lp->txbsz = mp->buffered; + lp->txbfd = 1; + lp->txb = (char *)realloc(lp->txb, lp->txbsz); + lp->txbpi = lp->txbpr = 0; + } + } + if (nolog) { + mp->logfiletmpl[0] = '\0'; + for (i = 0; i < mp->lines; i++) { /* close line logs */ + lp = mp->ldsc + i; + free(lp->txlogname); + lp->txlogname = NULL; + if (lp->txlog) { + sim_close_logfile (&lp->txlogref); + lp->txlog = NULL; + } + } + } + if (listen[0]) { + sock = sim_master_sock (listen, &r); /* make master socket */ + if (r != SCPE_OK) + return r; + if (sock == INVALID_SOCKET) /* open error */ + return SCPE_OPENERR; + if (mp->port) { /* close prior listener */ + sim_close_sock (mp->master, 1); + mp->master = 0; + free (mp->port); + mp->port = NULL; + } + printf ("Listening on port %s\n", listen); + if (sim_log) + fprintf (sim_log, "Listening on port %s\n", listen); + mp->port = (char *)realloc (mp->port, 1 + strlen (listen)); + strcpy (mp->port, listen); /* save port */ + mp->master = sock; /* save master socket */ + mp->notelnet = listennotelnet; /* save desired telnet behavior flag */ + for (i = 0; i < mp->lines; i++) { /* initialize lines */ + lp = mp->ldsc + i; + lp->mp = mp; /* set the back pointer */ + + if (lp->serport) { /* serial port attached? */ + tmxr_reset_ln (lp); /* close current serial connection */ + sim_control_serial (lp->serport, 0, TMXR_MDM_DTR|TMXR_MDM_RTS, NULL);/* drop DTR and RTS */ + sim_close_serial (lp->serport); + lp->serport = 0; + free (lp->serconfig); + lp->serconfig = NULL; + } + tmxr_init_line (lp); /* initialize line state */ + lp->sock = 0; /* clear the socket */ + } + } + if (destination[0]) { + if (mp->lines > 1) + return SCPE_ARG; /* ambiguous */ + lp = &mp->ldsc[0]; + serport = sim_open_serial (destination, lp, &r); + if (serport != INVALID_HANDLE) { + _mux_detach_line (lp, TRUE, TRUE); + if (lp->mp && lp->mp->master) { /* if existing listener, close it */ + sim_close_sock (lp->mp->master, 1); + lp->mp->master = 0; + free (lp->mp->port); + lp->mp->port = NULL; + } + lp->destination = malloc(1+strlen(destination)); + strcpy (lp->destination, destination); + lp->mp = mp; + lp->serport = serport; + lp->ser_connect_pending = TRUE; + lp->notelnet = TRUE; + tmxr_init_line (lp); /* init the line state */ + if (!lp->mp->modem_control) /* raise DTR and RTS for non modem control lines */ + sim_control_serial (lp->serport, TMXR_MDM_DTR|TMXR_MDM_RTS, 0, NULL); + lp->cnms = sim_os_msec (); /* record time of connection */ + if (sim_switches & SWMASK ('V')) { /* -V flag reports connection on port */ + sim_os_ms_sleep (TMXR_DTR_DROP_TIME); + tmxr_report_connection (mp, lp); /* report the connection to the line */ + } + } + else { + sock = sim_connect_sock (destination, "localhost", NULL); + if (sock != INVALID_SOCKET) { + _mux_detach_line (lp, FALSE, TRUE); + lp->destination = malloc(1+strlen(destination)); + strcpy (lp->destination, destination); + lp->mp = mp; + lp->connecting = sock; + lp->ipad = malloc (1 + strlen (lp->destination)); + strcpy (lp->ipad, lp->destination); + lp->notelnet = notelnet; + lp->cnms = sim_os_msec (); /* record time of connection */ + tmxr_init_line (lp); /* init the line state */ + } + else + return SCPE_ARG; + } + } + } + else { /* line specific attach */ + lp = &mp->ldsc[line]; + lp->mp = mp; + if (logfiletmpl[0]) { sim_close_logfile (&lp->txlogref); lp->txlog = NULL; - lp->txlogname = realloc(lp->txlogname, CBUFSIZE); - if (mp->lines > 1) - sprintf(lp->txlogname, "%s_%d", mp->logfiletmpl, i); - else - strcpy(lp->txlogname, mp->logfiletmpl); + lp->txlogname = (char *)realloc (lp->txlogname, 1 + strlen (logfiletmpl)); + strcpy(lp->txlogname, mp->logfiletmpl); r = sim_open_logfile (lp->txlogname, TRUE, &lp->txlog, &lp->txlogref); if (r == SCPE_OK) setvbuf(lp->txlog, NULL, _IOFBF, 65536); else { free (lp->txlogname); lp->txlogname = NULL; - break; + return r; } } - return r; - } - if ((0 == MATCH_CMD (gbuf, "NOBUFFERED")) || - (0 == MATCH_CMD (gbuf, "UNBUFFERED"))) { - if (mp->buffered) { - mp->buffered = 0; - for (i = 0; i < mp->lines; i++) { /* default line buffers */ - lp = mp->ldsc + i; - lp->txbsz = TMXR_MAXBUF; - lp->txb = (char *)realloc(lp->txb, lp->txbsz); - lp->txbfd = lp->txbpi = lp->txbpr = 0; - } + if (unbuffered) { + lp->txbsz = TMXR_MAXBUF; + lp->txb = (char *)realloc (lp->txb, lp->txbsz); + lp->txbfd = lp->txbpi = lp->txbpr = 0; } - return SCPE_OK; - } - if (0 == MATCH_CMD (gbuf, "BUFFERED")) { - if ((NULL == cptr) || ('\0' == *cptr)) - mp->buffered = 32768; - else { - i = (int32) get_uint (cptr, 10, 1024*1024, &r); - if ((r != SCPE_OK) || (i == 0)) - return SCPE_ARG; - mp->buffered = i; - } - for (i = 0; i < mp->lines; i++) { /* initialize line buffers */ - lp = mp->ldsc + i; - lp->txbsz = mp->buffered; + if (buffered[0]) { + lp->txbsz = atoi(buffered); lp->txbfd = 1; - lp->txb = (char *)realloc(lp->txb, lp->txbsz); + lp->txb = (char *)realloc (lp->txb, lp->txbsz); lp->txbpi = lp->txbpr = 0; } - return SCPE_OK; - } - if (0 == MATCH_CMD (gbuf, "NOLOG")) { - if ((NULL != cptr) && ('\0' != *cptr)) - return SCPE_2MARG; - mp->logfiletmpl[0] = '\0'; - for (i = 0; i < mp->lines; i++) { /* close line logs */ - lp = mp->ldsc + i; + if (nolog) { free(lp->txlogname); lp->txlogname = NULL; if (lp->txlog) { @@ -666,39 +1766,66 @@ if (!isdigit(*cptr)) { lp->txlog = NULL; } } - return SCPE_OK; + if (listen[0]) { + sock = sim_master_sock (listen, &r); /* make master socket */ + if (r != SCPE_OK) + return r; + if (sock == INVALID_SOCKET) /* open error */ + return SCPE_OPENERR; + _mux_detach_line (lp, TRUE, FALSE); + printf ("Line %d Listening on port %s\n", line, listen); + if (sim_log) + fprintf (sim_log, "Line %d Listening on port %s\n", line, listen); + lp->port = (char *)realloc (lp->port, 1 + strlen (listen)); + strcpy(lp->port, listen); /* save port */ + lp->master = sock; /* save master socket */ + if (listennotelnet) + lp->notelnet = listennotelnet; + else + lp->notelnet = mp->notelnet; + } + if (destination[0]) { + serport = sim_open_serial (destination, lp, &r); + if (serport != INVALID_HANDLE) { + _mux_detach_line (lp, TRUE, TRUE); + lp->destination = malloc(1+strlen(destination)); + strcpy (lp->destination, destination); + lp->serport = serport; + lp->ser_connect_pending = TRUE; + lp->notelnet = TRUE; + tmxr_init_line (lp); /* init the line state */ + if (!lp->mp->modem_control) /* raise DTR and RTS for non modem control lines */ + sim_control_serial (lp->serport, TMXR_MDM_DTR|TMXR_MDM_RTS, 0, NULL); + lp->cnms = sim_os_msec (); /* record time of connection */ + if (sim_switches & SWMASK ('V')) { /* -V flag reports connection on port */ + sim_os_ms_sleep (TMXR_DTR_DROP_TIME); + tmxr_report_connection (mp, lp); /* report the connection to the line */ + } + } + else { + sock = sim_connect_sock (destination, "localhost", NULL); + if (sock != INVALID_SOCKET) { + _mux_detach_line (lp, FALSE, TRUE); + lp->destination = malloc(1+strlen(destination)); + strcpy (lp->destination, destination); + lp->connecting = sock; + lp->ipad = malloc (1 + strlen (lp->destination)); + strcpy (lp->ipad, lp->destination); + lp->notelnet = notelnet; + lp->cnms = sim_os_msec (); /* record time of connection */ + tmxr_init_line (lp); /* init the line state */ + } + else + return SCPE_ARG; + } + } + r = SCPE_OK; } - return SCPE_ARG; } -port = (int32) get_uint (cptr, 10, 65535, &r); /* get port */ -if ((r != SCPE_OK) || (port == 0)) - return SCPE_ARG; -sock = sim_master_sock (port); /* make master socket */ -if (sock == INVALID_SOCKET) /* open error */ - return SCPE_OPENERR; -printf ("Listening on port %d (socket %d)\n", port, sock); -if (sim_log) - fprintf (sim_log, "Listening on port %d (socket %d)\n", port, sock); -mp->port = port; /* save port */ -mp->master = sock; /* save master socket */ -for (i = 0; i < mp->lines; i++) { /* initialize lines */ - lp = mp->ldsc + i; - lp->mp = mp; - lp->conn = lp->tsta = 0; - lp->rxbpi = lp->rxbpr = 0; - lp->txbpi = lp->txbpr = 0; - if (!mp->buffered) { - lp->txbfd = lp->txbpi = lp->txbpr = 0; - lp->txbsz = TMXR_MAXBUF; - lp->txb = (char *)realloc(lp->txb, lp->txbsz); - } - lp->rxcnt = lp->txcnt = lp->txdrp = 0; - lp->xmte = 1; - lp->dstb = 0; - } -return SCPE_OK; +return r; } + /* Declare which unit polls for input Inputs: @@ -726,19 +1853,6 @@ mp->ldsc[line].uptr = uptr_poll; return SCPE_OK; } -t_stat tmxr_set_console_input_unit (UNIT *uptr) -{ -extern TMLN sim_con_ldsc; - -sim_con_ldsc.uptr = uptr; -if (!(uptr->flags & UNIT_TM_POLL)) { - uptr->flags |= UNIT_TM_POLL; /* tag as polling unit */ - } -else - sim_cancel (uptr); -return SCPE_OK; -} - /* Declare which unit polls for output Inputs: @@ -752,7 +1866,7 @@ return SCPE_OK; Implementation note: Only devices which poll on a unit different from the unit provided - at MUX attach time need call this function AND different from the + at MUX attach time need call this function ABD different from the unit which polls for input. Calling this API is necessary for asynchronous multiplexer support and unnecessary otherwise. @@ -766,12 +1880,43 @@ mp->ldsc[line].o_uptr = uptr_poll; return SCPE_OK; } +/* Declare which units are the console input and out devices + + Inputs: + *rxuptr = the console input unit + *txuptr = the console output unit + + Outputs: + none + + Implementation note: + + This routine is exported by the tmxr library so that it gets + defined to code which uses it by including sim_tmxr.h. Including + sim_tmxr.h is necessary so that sim_activate is properly defined + in the caller's code to actually call tmxr_activate. + +*/ + +t_stat tmxr_set_console_units (UNIT *rxuptr, UNIT *txuptr) +{ +extern TMXR sim_con_tmxr; + +tmxr_set_line_unit (&sim_con_tmxr, 0, rxuptr); +tmxr_set_line_output_unit (&sim_con_tmxr, 0, txuptr); +return SCPE_OK; +} + static TMXR **tmxr_open_devices = NULL; static int tmxr_open_device_count = 0; -#if defined(SIM_ASYNCH_IO) +#if defined(SIM_ASYNCH_IO) && defined(SIM_ASYNCH_MUX) pthread_t sim_tmxr_poll_thread; /* Polling Thread Id */ +#if defined(_WIN32) || defined(VMS) +pthread_t sim_tmxr_serial_poll_thread; /* Serial Polling Thread Id */ +pthread_cond_t sim_tmxr_serial_startup_cond; +#endif pthread_mutex_t sim_tmxr_poll_lock; pthread_cond_t sim_tmxr_poll_cond; pthread_cond_t sim_tmxr_startup_cond; @@ -816,6 +1961,7 @@ while (sim_asynch_enabled) { if ((tmxr_open_device_count == 0) || (!sim_is_running)) { for (j=0; ja_poll_waiter_count); --activated[j]->a_poll_waiter_count; --sim_tmxr_poll_count; @@ -824,6 +1970,7 @@ while (sim_asynch_enabled) { } /* If we started something we should wait for, let it finish before polling again */ if (wait_count) { + sim_debug (TMXR_DBG_ASY, dptr, "_tmxr_poll() - waiting for %d units\n", wait_count); pthread_cond_wait (&sim_tmxr_poll_cond, &sim_tmxr_poll_lock); sim_debug (TMXR_DBG_ASY, dptr, "_tmxr_poll() - continuing with timeout of %dms\n", timeout_usec/1000); } @@ -831,7 +1978,7 @@ while (sim_asynch_enabled) { FD_ZERO (&errorfds); for (i=max_socket_fd=socket_count=0; imaster) && (mp->uptr->flags&UNIT_TM_POLL)) { + if ((mp->master) && (mp->uptr->dynflags&UNIT_TM_POLL)) { units[socket_count] = mp->uptr; sockets[socket_count] = mp->master; FD_SET (mp->master, &readfds); @@ -841,15 +1988,46 @@ while (sim_asynch_enabled) { ++socket_count; } for (j=0; jlines; ++j) { - if (mp->ldsc[j].conn) { + if (mp->ldsc[j].sock) { units[socket_count] = mp->ldsc[j].uptr; if (units[socket_count] == NULL) units[socket_count] = mp->uptr; - sockets[socket_count] = mp->ldsc[j].conn; - FD_SET (mp->ldsc[j].conn, &readfds); - FD_SET (mp->ldsc[j].conn, &errorfds); - if (mp->ldsc[j].conn > max_socket_fd) - max_socket_fd = mp->ldsc[j].conn; + sockets[socket_count] = mp->ldsc[j].sock; + FD_SET (mp->ldsc[j].sock, &readfds); + FD_SET (mp->ldsc[j].sock, &errorfds); + if (mp->ldsc[j].sock > max_socket_fd) + max_socket_fd = mp->ldsc[j].sock; + ++socket_count; + } +#if !defined(_WIN32) && !defined(VMS) + if (mp->ldsc[j].serport) { + units[socket_count] = mp->ldsc[j].uptr; + if (units[socket_count] == NULL) + units[socket_count] = mp->uptr; + sockets[socket_count] = mp->ldsc[j].serport; + FD_SET (mp->ldsc[j].serport, &readfds); + FD_SET (mp->ldsc[j].serport, &errorfds); + if (mp->ldsc[j].serport > max_socket_fd) + max_socket_fd = mp->ldsc[j].serport; + ++socket_count; + } +#endif + if (mp->ldsc[j].connecting) { + units[socket_count] = mp->uptr; + sockets[socket_count] = mp->ldsc[j].connecting; + FD_SET (mp->ldsc[j].connecting, &readfds); + FD_SET (mp->ldsc[j].connecting, &errorfds); + if (mp->ldsc[j].connecting > max_socket_fd) + max_socket_fd = mp->ldsc[j].connecting; + ++socket_count; + } + if (mp->ldsc[j].master) { + units[socket_count] = mp->uptr; + sockets[socket_count] = mp->ldsc[j].master; + FD_SET (mp->ldsc[j].master, &readfds); + FD_SET (mp->ldsc[j].master, &errorfds); + if (mp->ldsc[j].master > max_socket_fd) + max_socket_fd = mp->ldsc[j].master; ++socket_count; } } @@ -860,7 +2038,12 @@ while (sim_asynch_enabled) { timeout.tv_sec = timeout_usec/1000000; timeout.tv_usec = timeout_usec%1000000; select_errno = 0; - status = select(1+(int)max_socket_fd, &readfds, NULL, &errorfds, &timeout); + if (socket_count == 0) { + sim_os_ms_sleep (timeout_usec/1000); + status = 0; + } + else + status = select (1+(int)max_socket_fd, &readfds, NULL, &errorfds, &timeout); select_errno = errno; wait_count=0; pthread_mutex_lock (&sim_tmxr_poll_lock); @@ -958,10 +2141,296 @@ sim_debug (TMXR_DBG_ASY, dptr, "_tmxr_poll() - exiting\n"); return NULL; } -#endif + +#if defined(_WIN32) +static void * +_tmxr_serial_poll(void *arg) +{ +int sched_policy; +struct sched_param sched_priority; +int timeout_usec; +DEVICE *dptr = tmxr_open_devices[0]->dptr; +UNIT **units = NULL; +UNIT **activated = NULL; +SERHANDLE *serports = NULL; +int wait_count = 0; + +/* Boost Priority for this I/O thread vs the CPU instruction execution + thread which, in general, won't be readily yielding the processor when + this thread needs to run */ +pthread_getschedparam (pthread_self(), &sched_policy, &sched_priority); +++sched_priority.sched_priority; +pthread_setschedparam (pthread_self(), sched_policy, &sched_priority); + +sim_debug (TMXR_DBG_ASY, dptr, "_tmxr_serial_poll() - starting\n"); + +units = calloc(MAXIMUM_WAIT_OBJECTS, sizeof(*units)); +activated = calloc(MAXIMUM_WAIT_OBJECTS, sizeof(*activated)); +serports = calloc(MAXIMUM_WAIT_OBJECTS, sizeof(*serports)); +timeout_usec = 1000000; +pthread_mutex_lock (&sim_tmxr_poll_lock); +pthread_cond_signal (&sim_tmxr_serial_startup_cond); /* Signal we're ready to go */ +while (sim_asynch_enabled) { + int i, j; + DWORD status; + int serport_count; + TMXR *mp; + DEVICE *d; + + if ((tmxr_open_device_count == 0) || (!sim_is_running)) { + for (j=0; ja_poll_waiter_count); + --activated[j]->a_poll_waiter_count; + --sim_tmxr_poll_count; + } + break; + } + /* If we started something we should wait for, let it finish before polling again */ + if (wait_count) { + sim_debug (TMXR_DBG_ASY, dptr, "_tmxr_serial_poll() - waiting for %d units\n", wait_count); + pthread_cond_wait (&sim_tmxr_poll_cond, &sim_tmxr_poll_lock); + sim_debug (TMXR_DBG_ASY, dptr, "_tmxr_serial_poll() - continuing with timeout of %dms\n", timeout_usec/1000); + } + for (i=serport_count=0; ilines; ++j) { + if (mp->ldsc[j].serport) { + units[serport_count] = mp->ldsc[j].uptr; + if (units[serport_count] == NULL) + units[serport_count] = mp->uptr; + serports[serport_count] = mp->ldsc[j].serport; + ++serport_count; + } + } + } + if (serport_count == 0) /* No open serial ports? */ + break; /* We're done */ + pthread_mutex_unlock (&sim_tmxr_poll_lock); + if (timeout_usec > 1000000) + timeout_usec = 1000000; + status = WaitForMultipleObjects (serport_count, serports, FALSE, timeout_usec/1000); + wait_count=0; + pthread_mutex_lock (&sim_tmxr_poll_lock); + switch (status) { + case WAIT_FAILED: + fprintf (stderr, "WaitForMultipleObjects() Failed, LastError=%d\r\n", GetLastError()); + abort(); + break; + case WAIT_TIMEOUT: + sim_debug (TMXR_DBG_ASY, dptr, "_tmxr_serial_poll() - Poll Timeout - %dms\n", timeout_usec/1000); + timeout_usec *= 2; /* Double timeout time */ + break; + default: + i = status - WAIT_OBJECT_0; + wait_count = 0; + j = wait_count; + activated[j] = units[i]; + ++wait_count; + if (!activated[j]->a_polling_now) { + activated[j]->a_polling_now = TRUE; + activated[j]->a_poll_waiter_count = 1; + d = find_dev_from_unit(activated[j]); + sim_debug (TMXR_DBG_ASY, d, "_tmxr_serial_poll() - Activating for data %s\n", sim_uname(activated[j])); + pthread_mutex_unlock (&sim_tmxr_poll_lock); + _sim_activate (activated[j], 0); + pthread_mutex_lock (&sim_tmxr_poll_lock); + } + else { + d = find_dev_from_unit(activated[j]); + sim_debug (TMXR_DBG_ASY, d, "_tmxr_serial_poll() - Already Activated %s%d %d times\n", sim_uname(activated[j]), activated[j]->a_poll_waiter_count); + ++activated[j]->a_poll_waiter_count; + } + if (wait_count) + timeout_usec = 10000; /* Wait 10ms next time */ + break; + } + sim_tmxr_poll_count += wait_count; + } +pthread_mutex_unlock (&sim_tmxr_poll_lock); +free(units); +free(activated); +free(serports); + +sim_debug (TMXR_DBG_ASY, dptr, "_tmxr_serial_poll() - exiting\n"); + +return NULL; +} +#endif /* _WIN32 */ + +#if defined(VMS) + +#include +#include +#include +#include +#include +#include +#include + +typedef struct { + unsigned short status; + unsigned short count; + unsigned int dev_status; } IOSB; + +#define MAXIMUM_WAIT_OBJECTS 64 /* Number of possible concurrently opened serial ports */ + +pthread_cond_t sim_serial_line_startup_cond; + + +static void * +_tmxr_serial_line_poll(void *arg) +{ +TMLN *lp = (TMLN *)arg; +int sched_policy; +struct sched_param sched_priority; +DEVICE *dptr = tmxr_open_devices[0]->dptr; +UNIT *uptr = (lp->uptr ? lp->uptr : lp->mp->uptr); +DEVICE *d = find_dev_from_unit(uptr); +int wait_count = 0; + +/* Boost Priority for this I/O thread vs the CPU instruction execution + thread which, in general, won't be readily yielding the processor when + this thread needs to run */ +pthread_getschedparam (pthread_self(), &sched_policy, &sched_priority); +++sched_priority.sched_priority; +pthread_setschedparam (pthread_self(), sched_policy, &sched_priority); + +sim_debug (TMXR_DBG_ASY, dptr, "_tmxr_serial_line_poll() - starting\n"); + +pthread_mutex_lock (&sim_tmxr_poll_lock); +pthread_cond_signal (&sim_serial_line_startup_cond); /* Signal we're ready to go */ +while (sim_asynch_enabled) { + int i, j; + int serport_count; + TMXR *mp = lp->mp; + unsigned int status, term[2]; + unsigned char buf[4]; + IOSB iosb; + + if ((tmxr_open_device_count == 0) || (!sim_is_running)) { + if (wait_count) { + sim_debug (TMXR_DBG_ASY, d, "_tmxr_serial_line_poll() - Removing interest in %s. Other interest: %d\n", sim_uname(uptr), uptr->a_poll_waiter_count); + --uptr->a_poll_waiter_count; + --sim_tmxr_poll_count; + } + break; + } + /* If we started something we should wait for, let it finish before polling again */ + if (wait_count) { + sim_debug (TMXR_DBG_ASY, dptr, "_tmxr_serial_line_poll() - waiting for %d units\n", wait_count); + pthread_cond_wait (&sim_tmxr_poll_cond, &sim_tmxr_poll_lock); + sim_debug (TMXR_DBG_ASY, dptr, "_tmxr_serial_line_poll() - continuing with timeout of 1 sec\n"); + } + lp->a_active = TRUE; + pthread_mutex_unlock (&sim_tmxr_poll_lock); + term[0] = term[1] = 0; + status = sys$qio (0, lp->serport, + IO$_READLBLK | IO$M_NOECHO | IO$M_NOFILTR | IO$M_TIMED | IO$M_TRMNOECHO, + &iosb, 0, 0, buf, 1, 1, term, 0, 0); + if (status != SS$_NORMAL) { + fprintf (stderr, "_tmxr_serial_line_poll() - QIO Failed, Status=%d\r\n", status); + abort(); + } + wait_count = 0; + sys$synch (0, &iosb); + pthread_mutex_lock (&sim_tmxr_poll_lock); + lp->a_active = FALSE; + if (iosb.count == 1) { + lp->a_buffered_character = buf[0] | SCPE_KFLAG; + wait_count = 1; + if (!uptr->a_polling_now) { + uptr->a_polling_now = TRUE; + uptr->a_poll_waiter_count = 1; + sim_debug (TMXR_DBG_ASY, d, "_tmxr_serial_line_poll() - Activating for data %s\n", sim_uname(uptr)); + pthread_mutex_unlock (&sim_tmxr_poll_lock); + _sim_activate (uptr, 0); + pthread_mutex_lock (&sim_tmxr_poll_lock); + } + else { + sim_debug (TMXR_DBG_ASY, d, "_tmxr_serial_line_poll() - Already Activated %s%d %d times\n", sim_uname(uptr), uptr->a_poll_waiter_count); + ++uptr->a_poll_waiter_count; + } + } + sim_tmxr_poll_count += wait_count; + } +pthread_mutex_unlock (&sim_tmxr_poll_lock); + +sim_debug (TMXR_DBG_ASY, dptr, "_tmxr_serial_line_poll() - exiting\n"); + +return NULL; +} + +static void * +_tmxr_serial_poll(void *arg) +{ +int sched_policy; +struct sched_param sched_priority; +int timeout_usec; +DEVICE *dptr = tmxr_open_devices[0]->dptr; +TMLN **lines = NULL; +pthread_t *threads = NULL; + +/* Boost Priority for this I/O thread vs the CPU instruction execution + thread which, in general, won't be readily yielding the processor when + this thread needs to run */ +pthread_getschedparam (pthread_self(), &sched_policy, &sched_priority); +++sched_priority.sched_priority; +pthread_setschedparam (pthread_self(), sched_policy, &sched_priority); + +sim_debug (TMXR_DBG_ASY, dptr, "_tmxr_serial_poll() - starting\n"); + +lines = calloc(MAXIMUM_WAIT_OBJECTS, sizeof(*lines)); +threads = calloc(MAXIMUM_WAIT_OBJECTS, sizeof(*threads)); +pthread_mutex_lock (&sim_tmxr_poll_lock); +pthread_cond_signal (&sim_tmxr_serial_startup_cond); /* Signal we're ready to go */ +pthread_cond_init (&sim_serial_line_startup_cond, NULL); +while (sim_asynch_enabled) { + pthread_attr_t attr; + int i, j; + int serport_count; + TMXR *mp; + DEVICE *d; + + if ((tmxr_open_device_count == 0) || (!sim_is_running)) + break; + pthread_attr_init (&attr); + pthread_attr_setscope (&attr, PTHREAD_SCOPE_SYSTEM); + for (i=serport_count=0; ilines; ++j) { + if (mp->ldsc[j].serport) { + lines[serport_count] = &mp->ldsc[j]; + pthread_create (&threads[serport_count], &attr, _tmxr_serial_line_poll, (void *)&mp->ldsc[j]); + pthread_cond_wait (&sim_serial_line_startup_cond, &sim_tmxr_poll_lock); /* Wait for thread to stabilize */ + ++serport_count; + } + } + } + pthread_attr_destroy( &attr); + if (serport_count == 0) /* No open serial ports? */ + break; /* We're done */ + pthread_mutex_unlock (&sim_tmxr_poll_lock); + for (i=0; i 0) && sim_asynch_enabled && @@ -985,7 +2454,7 @@ return SCPE_OK; t_stat tmxr_stop_poll (void) { -#if defined(SIM_ASYNCH_IO) +#if defined(SIM_ASYNCH_IO) && defined(SIM_ASYNCH_MUX) pthread_mutex_lock (&sim_tmxr_poll_lock); if (sim_tmxr_poll_running) { pthread_cond_signal (&sim_tmxr_poll_cond); @@ -1015,9 +2484,23 @@ return SCPE_OK; static void _tmxr_add_to_open_list (TMXR* mux) { -tmxr_open_devices = realloc(tmxr_open_devices, (tmxr_open_device_count+1)*sizeof(*tmxr_open_devices)); -tmxr_open_devices[tmxr_open_device_count++] = mux; -#if defined(SIM_ASYNCH_IO) +int i; +t_bool found = FALSE; + +#if defined(SIM_ASYNCH_IO) && defined(SIM_ASYNCH_MUX) +pthread_mutex_lock (&sim_tmxr_poll_lock); +#endif +for (i=0; iuptr = uptr; /* save unit for polling */ +uptr->filename = _mux_attach_string (uptr->filename, mp);/* save */ +uptr->flags = uptr->flags | UNIT_ATT; /* no more errors */ +if ((mp->lines > 1) || + ((mp->master == 0) && + (mp->ldsc[0].connecting == 0) && + (mp->ldsc[0].serport == 0))) + uptr->flags = uptr->dynflags | UNIT_ATTMULT; /* allow multiple attach commands */ + +#if defined(SIM_ASYNCH_IO) && defined(SIM_ASYNCH_MUX) +if (!async || (uptr->flags & TMUF_NOASYNCH)) /* if asynch disabled */ + uptr->dynflags |= TMUF_NOASYNCH; /* tag as no asynch */ +#else +uptr->dynflags |= TMUF_NOASYNCH; /* tag as no asynch */ +#endif + +if (mp->dptr == NULL) /* has device been set? */ + mp->dptr = find_dev_from_unit (uptr); /* no, so set device now */ + +_tmxr_add_to_open_list (mp); +return SCPE_OK; +} + + t_stat tmxr_startup (void) { return SCPE_OK; @@ -1079,20 +2603,24 @@ else { fprintf(st, "Multiplexer device: %s", mp->dptr->name); fprintf(st, ", attached to %s, ", mp->uptr->filename); - tmxr_show_lines(st, NULL, 0, mp); - fprintf(st, ", "); + if (mp->lines > 1) { + tmxr_show_lines(st, NULL, 0, mp); + fprintf(st, ", "); + } tmxr_show_summ(st, NULL, 0, mp); fprintf(st, ", sessions=%d\n", mp->sessions); for (j = 0; j < mp->lines; j++) { lp = mp->ldsc + j; - fprintf (st, "Line: %d", j); - if (lp->uptr && (lp->uptr != lp->mp->uptr)) - fprintf (st, " - Unit: %s\n", sim_uname (lp->uptr)); - else - fprintf (st, "\n"); - if (!lp->conn) + if (mp->lines > 1) { + fprintf (st, "Line: %d", j); + if (lp->uptr && (lp->uptr != lp->mp->uptr)) + fprintf (st, " - Unit: %s\n", sim_uname (lp->uptr)); + else + fprintf (st, "\n"); + } + if ((!lp->sock) && (!lp->connecting) && (!lp->serport) && (!lp->master)) continue; - tmxr_fconns (st, lp, j); + tmxr_fconns (st, lp, -1); tmxr_fstats (st, lp, -1); } } @@ -1101,84 +2629,95 @@ return SCPE_OK; } +/* Close a master listening socket. - -/* Attach unit to master socket */ - -t_stat tmxr_attach_ex (TMXR *mp, UNIT *uptr, char *cptr, t_bool async) -{ -char* tptr; -t_stat r; -char pmsg[20], bmsg[32] = "", lmsg[64+PATH_MAX] = ""; - -tptr = (char *) malloc (strlen (cptr) + /* get string buf */ - sizeof(pmsg) + - sizeof(bmsg) + sizeof(lmsg)); -if (tptr == NULL) /* no more mem? */ - return SCPE_MEM; -mp->uptr = uptr; /* save unit for polling */ -r = tmxr_open_master (mp, cptr); /* open master socket */ -if (r != SCPE_OK) { /* error? */ - free (tptr); /* release buf */ - return SCPE_OPENERR; - } -sprintf (pmsg, "%d", mp->port); /* copy port */ -if (mp->buffered) - sprintf (bmsg, ", buffered=%d", mp->buffered); /* buffer info */ -if (mp->logfiletmpl[0]) - sprintf (lmsg, ", log=%s", mp->logfiletmpl); /* logfile info */ -sprintf (tptr, "%s%s%s", pmsg, bmsg, lmsg); /* assemble all */ -uptr->filename = tptr; /* save */ -uptr->flags = uptr->flags | UNIT_ATT; /* no more errors */ -if (!(uptr->flags & TMUF_NOASYNCH) && async) /* if asynch not disabled */ - uptr->flags |= UNIT_TM_POLL; /* tag as polling unit */ - -if (mp->dptr == NULL) /* has device been set? */ - mp->dptr = find_dev_from_unit (uptr); /* no, so set device now */ - -_tmxr_add_to_open_list (mp); -return SCPE_OK; -} - -/* Close master socket */ + The listening socket associated with multiplexer descriptor "mp" is closed + and deallocated. In addition, all current Telnet sessions are disconnected. + Serial and outgoing sessions are also disconnected. +*/ t_stat tmxr_close_master (TMXR *mp) { int32 i; TMLN *lp; -for (i = 0; i < mp->lines; i++) { /* loop thru conn */ +for (i = 0; i < mp->lines; i++) { /* loop thru conn */ lp = mp->ldsc + i; - if (lp->conn) { - tmxr_linemsg (lp, "\r\nDisconnected from the "); - tmxr_linemsg (lp, sim_name); - tmxr_linemsg (lp, " simulator\r\n\n"); - tmxr_reset_ln (lp); - } /* end if conn */ - } /* end for */ -sim_close_sock (mp->master, 1); /* close master socket */ + + if (!lp->destination && lp->sock) { /* not serial and is connected? */ + tmxr_report_disconnection (lp); /* report disconnection */ + tmxr_reset_ln (lp); /* disconnect line */ + } + else { + if (lp->sock) { + tmxr_report_disconnection (lp); /* report disconnection */ + tmxr_reset_ln (lp); + } + if (lp->connecting) { + lp->sock = lp->connecting; + lp->connecting = 0; + tmxr_reset_ln (lp); + } + if (lp->serport) { + sim_control_serial (lp->serport, 0, TMXR_MDM_DTR|TMXR_MDM_RTS, NULL);/* drop DTR and RTS */ + tmxr_close_ln (lp); + } + free (lp->destination); + lp->destination = NULL; + lp->conn = FALSE; + } + if (lp->master) { + sim_close_sock (lp->master, 1); /* close master socket */ + lp->master = 0; + free (lp->port); + lp->port = NULL; + } + } + +if (mp->master) + sim_close_sock (mp->master, 1); /* close master socket */ mp->master = 0; +free (mp->port); +mp->port = NULL; _tmxr_remove_from_open_list (mp); return SCPE_OK; } -/* Detach unit from master socket */ + +/* Detach unit from master socket and close all active network connections + and/or serial ports. + + Note that we return SCPE_OK, regardless of whether a listening socket was + attached. +*/ t_stat tmxr_detach (TMXR *mp, UNIT *uptr) { +int32 i; + if (!(uptr->flags & UNIT_ATT)) /* attached? */ return SCPE_OK; tmxr_close_master (mp); /* close master socket */ -free (uptr->filename); /* free port string */ +free (uptr->filename); /* free setup string */ uptr->filename = NULL; -uptr->flags = uptr->flags & ~(UNIT_ATT|UNIT_TM_POLL); /* not attached, no polling */ +mp->last_poll_time = 0; +for (i=0; i < mp->lines; i++) { + UNIT *uptr = mp->ldsc[i].uptr ? mp->ldsc[i].uptr : mp->uptr; + UNIT *o_uptr = mp->ldsc[i].o_uptr ? mp->ldsc[i].o_uptr : mp->uptr; + + uptr->dynflags &= ~UNIT_TM_POLL; /* no polling */ + o_uptr->dynflags &= ~UNIT_TM_POLL; /* no polling */ + } +uptr->flags &= ~(UNIT_ATT); /* not attached */ +uptr->dynflags &= ~(UNIT_TM_POLL|TMUF_NOASYNCH); /* no polling, not asynch disabled */ return SCPE_OK; } + t_stat tmxr_activate (UNIT *uptr, int32 interval) { -#if defined(SIM_ASYNCH_IO) -if ((!(uptr->flags & UNIT_TM_POLL)) || +#if defined(SIM_ASYNCH_IO) && defined(SIM_ASYNCH_MUX) +if ((!(uptr->dynflags & UNIT_TM_POLL)) || (!sim_asynch_enabled)) { return _sim_activate (uptr, interval); } @@ -1190,8 +2729,8 @@ return _sim_activate (uptr, interval); t_stat tmxr_activate_after (UNIT *uptr, int32 usecs_walltime) { -#if defined(SIM_ASYNCH_IO) -if ((!(uptr->flags & UNIT_TM_POLL)) || +#if defined(SIM_ASYNCH_IO) && defined(SIM_ASYNCH_MUX) +if ((!(uptr->dynflags & UNIT_TM_POLL)) || (!sim_asynch_enabled)) { return _sim_activate_after (uptr, usecs_walltime); } @@ -1203,8 +2742,8 @@ return _sim_activate_after (uptr, usecs_walltime); t_stat tmxr_clock_coschedule (UNIT *uptr, int32 interval) { -#if defined(SIM_ASYNCH_IO) -if ((!(uptr->flags & UNIT_TM_POLL)) || +#if defined(SIM_ASYNCH_IO) && defined(SIM_ASYNCH_MUX) +if ((!(uptr->dynflags & UNIT_TM_POLL)) || (!sim_asynch_enabled)) { return sim_clock_coschedule (uptr, interval); } @@ -1214,6 +2753,147 @@ return sim_clock_coschedule (uptr, interval); #endif } +/* Generic Multiplexer attach help */ + +t_stat tmxr_attach_help(FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr) +{ +TMXR *mux = (TMXR *)dptr->help_ctx; +t_bool single_line = FALSE; /* default to Multi-Line help */ + +if (mux) + single_line = (mux->lines == 1); + +fprintf (st, "%s Multiplexer Attach Help\n\n", dptr->name); +if (single_line) { /* Single Line Multiplexer */ + fprintf (st, "The %s multiplexer may be connected to terminal emulators supporting the\n", dptr->name); + fprintf (st, "Telnet protocol via sockets, or to hardware terminals via host serial\n"); + fprintf (st, "ports.\n\n"); + fprintf (st, "A Telnet listening port can be configured with:\n\n"); + fprintf (st, " sim> ATTACH %s {interface:}port\n\n", dptr->name); + fprintf (st, "Line buffering can be enabled for the %s device with:\n\n", dptr->name); + fprintf (st, " sim> ATTACH %s Buffer{=bufsize}\n\n", dptr->name); + fprintf (st, "Line buffering can be disabled for the %s device with:\n\n", dptr->name); + fprintf (st, " sim> ATTACH %s NoBuffer\n\n", dptr->name); + fprintf (st, "The default buffer size is 32k bytes, the max buffer size is 1024k bytes\n\n"); + fprintf (st, "The outbound traffic the %s device can be logged to a file with:\n", dptr->name); + fprintf (st, " sim> ATTACH %s Log=LogFileName\n\n", dptr->name); + fprintf (st, "File logging can be disabled for the %s device with:\n\n", dptr->name); + fprintf (st, " sim> ATTACH %s NoLog\n\n", dptr->name); + fprintf (st, "The %s device may be connected to a serial port on the host system.\n", dptr->name); + } +else { + fprintf (st, "%s multiplexer lines may be connected to terminal emulators supporting the\n", dptr->name); + fprintf (st, "Telnet protocol via sockets, or to hardware terminals via host serial\n"); + fprintf (st, "ports. Concurrent Telnet and serial connections may be mixed on a given\n"); + fprintf (st, "multiplexer.\n\n"); + fprintf (st, "A Telnet listening port can be configured with:\n\n"); + fprintf (st, " sim> ATTACH %s {interface:}port\n\n", dptr->name); + if (mux) + fprintf (st, "Line buffering for all %d lines on the %s device can be configured with:\n\n", mux->lines, dptr->name); + else + fprintf (st, "Line buffering for all lines on the %s device can be configured with:\n\n", dptr->name); + fprintf (st, " sim> ATTACH %s Buffer{=bufsize}\n\n", dptr->name); + if (mux) + fprintf (st, "Line buffering for all %d lines on the %s device can be disabled with:\n\n", mux->lines, dptr->name); + else + fprintf (st, "Line buffering for all lines on the %s device can be disabled with:\n\n", dptr->name); + fprintf (st, " sim> ATTACH %s NoBuffer\n\n", dptr->name); + fprintf (st, "The default buffer size is 32k bytes, the max buffer size is 1024k bytes\n\n"); + fprintf (st, "The outbound traffic for the lines of the %s device can be logged to files\n", dptr->name); + fprintf (st, "with:\n\n"); + fprintf (st, " sim> ATTACH %s Log=LogFileName\n\n", dptr->name); + fprintf (st, "The log file name for each line uses the above LogFileName as a template\n"); + fprintf (st, "for the actual file name which will be LogFileName_n where n is the line\n"); + fprintf (st, "number.\n\n"); + fprintf (st, "Multiplexer lines may be connected to serial ports on the host system.\n"); + } +fprintf (st, "Serial ports may be specified as an operating system specific device names\n"); +fprintf (st, "or using simh generic serial names. simh generic names are of the form\n"); +fprintf (st, "serN, where N is from 0 thru one less than the maximum number of serial\n"); +fprintf (st, "ports on the local system. The mapping of simh generic port names to OS \n"); +fprintf (st, "specific names can be displayed using the following command:\n\n"); +fprintf (st, " sim> SHOW SERIAL\n"); +fprintf (st, " Serial devices:\n"); +fprintf (st, " ser0 COM1 (\\Device\\Serial0)\n"); +fprintf (st, " ser1 COM3 (Winachcf0)\n\n"); +if (single_line) { /* Single Line Multiplexer */ + fprintf (st, " sim> ATTACH %s Connect=ser0\n\n", dptr->name); + fprintf (st, "or equivalently:\n\n"); + fprintf (st, " sim> ATTACH %s Connect=COM1\n\n", dptr->name); + } +else { + fprintf (st, " sim> ATTACH %s Line=n,Connect=ser0\n\n", dptr->name); + fprintf (st, "or equivalently:\n\n"); + fprintf (st, " sim> ATTACH %s Line=n,Connect=COM1\n\n", dptr->name); + if (mux) + fprintf (st, "Valid line numbers are from 0 thru %d\n\n", mux->lines-1); + } +fprintf (st, "An optional serial port configuration string may be present after the port\n"); +fprintf (st, "name. If present, it must be separated from the port name with a semicolon\n"); +fprintf (st, "and has this form:\n\n"); +fprintf (st, " -\n\n"); +fprintf (st, "where:\n"); +fprintf (st, " rate = communication rate in bits per second\n"); +fprintf (st, " charsize = character size in bits (5-8, including optional parity)\n"); +fprintf (st, " parity = parity designator (N/E/O/M/S for no/even/odd/mark/space parity)\n"); +fprintf (st, " stopbits = number of stop bits (1, 1.5, or 2)\n\n"); +fprintf (st, "As an example:\n\n"); +fprintf (st, " 9600-8n1\n\n"); +fprintf (st, "The supported rates, sizes, and parity options are host-specific. If\n"); +fprintf (st, "a configuration string is not supplied, then the default of 9600-8N1\n"); +fprintf (st, "is used.\n\n"); +fprintf (st, "An attachment to a serial port with the '-V' switch will cause a\n"); +fprintf (st, "connection message to be output to the connected serial port.\n"); +fprintf (st, "This will help to confirm the correct port has been connected and\n"); +fprintf (st, "that the port settings are reasonable for the connected device.\n"); +fprintf (st, "This would be done as:\n\n"); +if (single_line) /* Single Line Multiplexer */ + fprintf (st, " sim> ATTACH -V %s Connect=SerN\n", dptr->name); +else { + fprintf (st, " sim> ATTACH -V %s Line=n,Connect=SerN\n\n", dptr->name); + fprintf (st, "Line specific tcp listening ports are supported. These are configured\n"); + fprintf (st, "using commands of the form:\n\n"); + fprintf (st, " sim> ATTACH %s Line=n,{interface:}port{;notelnet}\n\n", dptr->name); + } +fprintf (st, "Direct computer to computer connections (Virutal Null Modem cables) may\n"); +fprintf (st, "be established using the telnet protocol or via raw tcp sockets.\n\n"); +fprintf (st, " sim> ATTACH %s Line=n,Connect=host:port{;notelnet}\n\n", dptr->name); +fprintf (st, "Computer to computer virtual connections can be one way (as illustrated\n"); +fprintf (st, "above) or symmetric. A symmetric connection is configured by combining\n"); +if (single_line) { /* Single Line Multiplexer */ + fprintf (st, "a one way connection with a tcp listening port on the same line:\n\n"); + fprintf (st, " sim> ATTACH %s listenport,Connect=host:port\n\n", dptr->name); + } +else { + fprintf (st, "a one way connection with a tcp listening port on the same line:\n\n"); + fprintf (st, " sim> ATTACH %s Line=n,listenport,Connect=host:port\n\n", dptr->name); + } +fprintf (st, "When symmetric virtual connections are configured, incoming connections\n"); +fprintf (st, "on the specified listening port are checked to assure that they actually\n"); +fprintf (st, "come from the specified connection destination host system.\n\n"); +if (single_line) /* Single Line Multiplexer */ + fprintf (st, "The connection configured for the %s device is unconfigured by:\n\n", dptr->name); +else + fprintf (st, "All connections configured for the %s device are unconfigured by:\n\n", dptr->name); +fprintf (st, " sim> DETACH %s\n\n", dptr->name); +if (dptr->modifiers) { + MTAB *mptr; + + for (mptr = dptr->modifiers; mptr->mask != 0; mptr++) + if (mptr->valid == &tmxr_dscln) { + fprintf (st, "A specific line on the %s device can be disconnected with:\n\n", dptr->name); + fprintf (st, " sim> SET %s %s=n\n\n", dptr->name, mptr->mstring); + fprintf (st, "This will cause a telnet connection to be closed, but a serial port will\n"); + fprintf (st, "normally have DTR dropped for 500ms and raised again (thus hanging up a\n"); + fprintf (st, "modem on that serial port).\n\n"); + fprintf (st, "A line which is connected to a serial port can be manually closed by\n"); + fprintf (st, "adding the -C switch to a %s command.\n\n", mptr->mstring); + fprintf (st, " sim> SET -C %s %s=n\n\n", dptr->name, mptr->mstring); + } + } +return SCPE_OK; +} + /* Stub examine and deposit */ t_stat tmxr_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw) @@ -1226,15 +2906,19 @@ t_stat tmxr_dep (t_value val, t_addr addr, UNIT *uptr, int32 sw) return SCPE_NOFNC; } -/* Output message to socket or line descriptor */ + +/* Write a message directly to a socket */ void tmxr_msg (SOCKET sock, char *msg) { -if (sock) +if ((sock) && (sock != INVALID_SOCKET)) sim_write_sock (sock, msg, (int32)strlen (msg)); return; } + +/* Write a message to a line */ + void tmxr_linemsg (TMLN *lp, char *msg) { int32 len; @@ -1244,34 +2928,49 @@ for (len = (int32)strlen (msg); len > 0; --len) return; } + /* Print connections - used only in named SHOW command */ void tmxr_fconns (FILE *st, TMLN *lp, int32 ln) { +int32 hr, mn, sc; +uint32 ctime; + if (ln >= 0) fprintf (st, "line %d: ", ln); -if (lp->conn) { - int32 o1, o2, o3, o4, hr, mn, sc; - uint32 ctime; - o1 = (lp->ipad >> 24) & 0xFF; - o2 = (lp->ipad >> 16) & 0xFF; - o3 = (lp->ipad >> 8) & 0xFF; - o4 = (lp->ipad) & 0xFF; +if ((lp->sock) || (lp->connecting)) { /* tcp connection? */ + if (lp->destination) /* remote connection? */ + fprintf (st, "Connection to remote port %s\n", lp->destination);/* print port name */ + else /* incoming connection */ + fprintf (st, "Connection from IP address %s\n", lp->ipad); + } + +if (lp->port) + fprintf (st, "Listening on port %s\n", lp->port); /* print port name */ + +if (lp->serport) /* serial connection? */ + fprintf (st, "Connected to serial port %s\n", lp->destination); /* print port name */ + +if (lp->cnms) { ctime = (sim_os_msec () - lp->cnms) / 1000; hr = ctime / 3600; mn = (ctime / 60) % 60; sc = ctime % 60; - fprintf (st, "IP address %d.%d.%d.%d", o1, o2, o3, o4); if (ctime) - fprintf (st, ", connected %02d:%02d:%02d\n", hr, mn, sc); + fprintf (st, " %s %02d:%02d:%02d\n", lp->connecting ? "Connecting for" : "Connected", hr, mn, sc); } -else fprintf (st, "line disconnected\n"); +else + fprintf (st, " Line disconnected\n"); + +if ((lp->serport == 0) && (lp->sock)) + fprintf (st, " %s\n", (lp->notelnet) ? "Telnet disabled (RAW data)" : "Telnet protocol"); if (lp->txlog) - fprintf (st, "Logging to %s\n", lp->txlogname); + fprintf (st, " Logging to %s\n", lp->txlogname); return; } + /* Print statistics - used only in named SHOW command */ void tmxr_fstats (FILE *st, TMLN *lp, int32 ln) @@ -1280,17 +2979,22 @@ static const char *enab = "on"; static const char *dsab = "off"; if (ln >= 0) - fprintf (st, "line %d:\b", ln); -if (!lp->conn) - fprintf (st, "line disconnected\n"); -if (lp->rxcnt) - fprintf (st, " input (%s) queued/total = %d/%d\n", - (lp->rcve? enab: dsab), - tmxr_rqln (lp), lp->rxcnt); -if (lp->txcnt || lp->txbpi) - fprintf (st, " output (%s) queued/total = %d/%d\n", - (lp->xmte? enab: dsab), - tmxr_tqln (lp), lp->txcnt); + fprintf (st, "Line %d:", ln); +if ((!lp->sock) && (!lp->connecting) && (!lp->serport)) + fprintf (st, " not connected\n"); +else { + if (ln >= 0) + fprintf (st, "\n"); + fprintf (st, " input (%s)", (lp->rcve? enab: dsab)); + if (lp->rxcnt) + fprintf (st, " queued/total = %d/%d", + tmxr_rqln (lp), lp->rxcnt); + fprintf (st, "\n output (%s)", (lp->xmte? enab: dsab)); + if (lp->txcnt || lp->txbpi) + fprintf (st, " queued/total = %d/%d", + tmxr_tqln (lp), lp->txcnt); + fprintf (st, "\n"); + } if (lp->txbfd) fprintf (st, " output buffer size = %d\n", lp->txbsz); if (lp->txcnt || lp->txbpi) @@ -1301,38 +3005,59 @@ if (lp->txdrp) return; } -/* Disconnect line */ + +/* Disconnect a line. + + Disconnect a line of the multiplexer associated with descriptor "desc" from a + tcp session or a serial port. Two calling sequences are supported: + + 1. If "val" is zero, then "uptr" is implicitly associated with the line + number corresponding to the position of the unit in the zero-based array + of units belonging to the associated device, and "cptr" is ignored. For + example, if "uptr" points to unit 3 in a given device, then line 3 will + be disconnected. + + 2. If "val" is non-zero, then "cptr" points to a string that is parsed for + an explicit line number, and "uptr" is ignored. For example, if "cptr" + points to the string "3", then line 3 will be disconnected. + + If the line was connected to a tcp session, the socket associated with the + line will be closed. If the line was connected to a serial port, the port + will NOT be closed, but DTR will be dropped. After a 500ms delay DTR will + be raised again. If the sim_switches -C flag is set, then a serial port + connection will be closed. + + Implementation notes: + + 1. This function is usually called as an MTAB processing routine. +*/ t_stat tmxr_dscln (UNIT *uptr, int32 val, char *cptr, void *desc) { TMXR *mp = (TMXR *) desc; TMLN *lp; -int32 ln; -t_stat r; +t_stat status; + +if (val) /* explicit line? */ + uptr = NULL; /* indicate to get routine */ -if (mp == NULL) - return SCPE_IERR; tmxr_debug_trace (mp, "tmxr_dscln()"); -if (val) { /* = n form */ - if (cptr == NULL) - return SCPE_ARG; - ln = (int32) get_uint (cptr, 10, mp->lines - 1, &r); - if (r != SCPE_OK) - return SCPE_ARG; - lp = mp->ldsc + ln; - } -else { - lp = tmxr_find_ldsc (uptr, 0, mp); - if (lp == NULL) - return SCPE_IERR; - } -if (lp->conn) { - tmxr_linemsg (lp, "\r\nOperator disconnected line\r\n\n"); - tmxr_reset_ln (lp); + +lp = tmxr_get_ldsc (uptr, cptr, mp, &status); /* get referenced line */ + +if (lp == NULL) /* bad line number? */ + return status; /* report it */ + +if ((lp->sock) || (lp->serport)) { /* connection active? */ + if (!lp->notelnet) + tmxr_linemsg (lp, "\r\nOperator disconnected line\r\n\n");/* report closure */ + tmxr_reset_ln_ex (lp, (sim_switches & SWMASK ('C'))); /* drop the line */ } + return SCPE_OK; } + /* Enable logging for line */ t_stat tmxr_set_log (UNIT *uptr, int32 val, char *cptr, void *desc) @@ -1356,9 +3081,11 @@ if (lp->txlog == NULL) { /* error? */ free (lp->txlogname); /* free buffer */ return SCPE_OPENERR; } +lp->mp->uptr->filename = _mux_attach_string (lp->mp->uptr->filename, lp->mp); return SCPE_OK; } + /* Disable logging for line */ t_stat tmxr_set_nolog (UNIT *uptr, int32 val, char *cptr, void *desc) @@ -1377,9 +3104,11 @@ if (lp->txlog) { /* logging? */ lp->txlog = NULL; lp->txlogname = NULL; } +lp->mp->uptr->filename = _mux_attach_string (lp->mp->uptr->filename, lp->mp); return SCPE_OK; } + /* Show logging status for line */ t_stat tmxr_show_log (FILE *st, UNIT *uptr, int32 val, void *desc) @@ -1396,27 +3125,6 @@ else fprintf (st, "no logging"); return SCPE_OK; } -/* Find line descriptor. - - Note: This routine may be called with a UNIT that does not belong to the - device indicated in the TMXR structure. That is, the multiplexer lines may - belong to a device other than the one attached to the socket (the HP 2100 MUX - device is one example). Therefore, we must look up the device from the unit - at each call, rather than depending on the DPTR stored in the TMXR. -*/ - -TMLN *tmxr_find_ldsc (UNIT *uptr, int32 val, TMXR *mp) -{ -if (uptr) { /* called from SET? */ - DEVICE *dptr = find_dev_from_unit (uptr); /* find device */ - if (dptr == NULL) /* what?? */ - return NULL; - val = (int32) (uptr - dptr->units); /* implicit line # */ - } -if ((val < 0) || (val >= mp->lines)) /* invalid line? */ - return NULL; -return mp->ldsc + val; /* line descriptor */ -} /* Set the line connection order. @@ -1523,6 +3231,7 @@ free (set); /* free set allocation * return result; } + /* Show line connection order. Parameters: @@ -1598,8 +3307,12 @@ int32 i, t; if (mp == NULL) return SCPE_IERR; for (i = t = 0; i < mp->lines; i++) - t = t + (mp->ldsc[i].conn != 0); -fprintf (st, "%d connection%s", t, (t != 1) ? "s" : ""); + if ((mp->ldsc[i].sock != 0) || (mp->ldsc[i].serport != 0)) + t = t + 1; +if (mp->lines > 1) + fprintf (st, "%d connection%s", t, (t != 1) ? "s" : ""); +else + fprintf (st, "%s", (t == 1) ? "connected" : "disconnected"); return SCPE_OK; } @@ -1613,7 +3326,7 @@ int32 i, any; if (mp == NULL) return SCPE_IERR; for (i = any = 0; i < mp->lines; i++) { - if (mp->ldsc[i].conn) { + if ((mp->ldsc[i].sock != 0) || (mp->ldsc[i].serport != 0)) { any++; if (val) tmxr_fconns (st, &mp->ldsc[i], i); @@ -1676,7 +3389,7 @@ static void tmxr_buf_debug_char (char value) { if (tmxr_debug_buf_used+2 > tmxr_debug_buf_size) { tmxr_debug_buf_size += 1024; - tmxr_debug_buf = realloc(tmxr_debug_buf, tmxr_debug_buf_size); + tmxr_debug_buf = (char *)realloc (tmxr_debug_buf, tmxr_debug_buf_size); } tmxr_debug_buf[tmxr_debug_buf_used++] = value; tmxr_debug_buf[tmxr_debug_buf_used] = '\0'; diff --git a/sim_tmxr.h b/sim_tmxr.h index b2996569..db5c0a3f 100644 --- a/sim_tmxr.h +++ b/sim_tmxr.h @@ -26,8 +26,11 @@ Based on the original DZ11 simulator by Thord Nilson, as updated by Arthur Krewat. + 10-Oct-12 MP Added extended attach support for serial, per line + listener and outgoing connections 17-Jan-11 MP Added buffered line capabilities 20-Nov-08 RMS Added three new standardized SHOW routines + 07-Oct-08 JDB Added serial port support to TMXR, TMLN 27-May-08 JDB Added lnorder to TMXR structure, added tmxr_set_lnorder and tmxr_set_lnorder 14-May-08 JDB Added dptr to TMXR structure @@ -44,6 +47,15 @@ #ifndef _SIM_TMXR_H_ #define _SIM_TMXR_H_ 0 +#ifndef _SERHANDLE_DEFINED +#define _SERHANDLE_DEFINED 0 +#if defined (_WIN32) /* Windows definitions */ +typedef void *SERHANDLE; +#else /* all other platforms */ +typedef int SERHANDLE; +#endif +#endif + #include "sim_sock.h" #define TMXR_V_VALID 15 @@ -51,11 +63,25 @@ #define TMXR_MAXBUF 256 /* buffer size */ #define TMXR_GUARD 12 /* buffer guard */ +#define TMXR_DTR_DROP_TIME 500 /* milliseconds to drop DTR for 'pseudo' modem control */ +#define TMXR_CONNECT_POLL_INTERVAL 1000 /* milliseconds between connection polls */ + #define TMXR_DBG_XMT 0x10000 /* Debug Transmit Data */ #define TMXR_DBG_RCV 0x20000 /* Debug Received Data */ -#define TMXR_DBG_ASY 0x40000 /* Debug Received Data */ +#define TMXR_DBG_ASY 0x40000 /* Debug Asynchronous Activities */ #define TMXR_DBG_TRC 0x80000 /* Debug trace routine calls */ +/* Modem Control Bits */ + +#define TMXR_MDM_DTR 0x01 /* Data Terminal Ready */ +#define TMXR_MDM_RTS 0x02 /* Request To Send */ +#define TMXR_MDM_DCD 0x04 /* Data Carrier Detect */ +#define TMXR_MDM_RNG 0x08 /* Ring Indicator */ +#define TMXR_MDM_CTS 0x10 /* Clear To Send */ +#define TMXR_MDM_DSR 0x20 /* Data Set Ready */ +#define TMXR_MDM_INCOMING (TMXR_MDM_DCD|TMXR_MDM_RNG|TMXR_MDM_CTS|TMXR_MDM_DSR) /* Settable Modem Bits */ +#define TMXR_MDM_OUTGOING (TMXR_MDM_DTR|TMXR_MDM_RTS) /* Settable Modem Bits */ + /* Unit flags */ #define TMUF_V_NOASYNCH (UNIT_V_UF + 12) /* Asynch Disabled unit */ @@ -68,13 +94,18 @@ typedef struct tmln TMLN; typedef struct tmxr TMXR; struct tmln { - SOCKET conn; /* line conn */ - uint32 ipad; /* IP address */ + int conn; /* line connected flag */ + SOCKET sock; /* connection socket */ + char *ipad; /* IP address */ + SOCKET master; /* line specific master socket */ + char *port; /* line specific listening port */ + int32 sessions; /* count of tcp connections received */ uint32 cnms; /* conn time */ int32 tsta; /* Telnet state */ int32 rcve; /* rcv enable */ int32 xmte; /* xmt enable */ int32 dstb; /* disable Tlnt bin */ + t_bool notelnet; /* raw binary data (no telnet interpretation) */ int32 rxbpr; /* rcv buf remove */ int32 rxbpi; /* rcv buf insert */ int32 rxcnt; /* rcv count */ @@ -91,13 +122,18 @@ struct tmln { char rbr[TMXR_MAXBUF]; /* rcv break */ char *txb; /* xmt buffer */ TMXR *mp; /* back pointer to mux */ + char *serconfig; /* line config */ + SERHANDLE serport; /* serial port handle */ + t_bool ser_connect_pending; /* serial connection notice pending */ + SOCKET connecting; /* Outgoing socket while connecting */ + char *destination; /* Outgoing destination address:port */ UNIT *uptr; /* input polling unit (default to mp->uptr) */ UNIT *o_uptr; /* output polling unit (default to lp->uptr)*/ }; struct tmxr { int32 lines; /* # lines */ - int32 port; /* listening port */ + char *port; /* listening port */ SOCKET master; /* master socket */ TMLN *ldsc; /* line descriptors */ int32 *lnorder; /* line connection order */ @@ -107,21 +143,30 @@ struct tmxr { int32 txcount; /* count of transmit bytes */ int32 buffered; /* Buffered Line Behavior and Buffer Size Flag */ int32 sessions; /* count of tcp connections received */ + uint32 last_poll_time; /* time of last connection poll */ + t_bool notelnet; /* default telnet capability for incoming connections */ + t_bool modem_control; /* multiplexer supports modem control behaviors */ }; int32 tmxr_poll_conn (TMXR *mp); -void tmxr_reset_ln (TMLN *lp); +t_stat tmxr_reset_ln (TMLN *lp); int32 tmxr_getc_ln (TMLN *lp); void tmxr_poll_rx (TMXR *mp); t_stat tmxr_putc_ln (TMLN *lp, int32 chr); void tmxr_poll_tx (TMXR *mp); +int32 tmxr_send_buffered_data (TMLN *lp); t_stat tmxr_open_master (TMXR *mp, char *cptr); t_stat tmxr_close_master (TMXR *mp); t_stat tmxr_attach_ex (TMXR *mp, UNIT *uptr, char *cptr, t_bool async); t_stat tmxr_detach (TMXR *mp, UNIT *uptr); +t_stat tmxr_attach_help(FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr); +t_stat tmxr_set_modem_control_passthru (TMXR *mp); +t_stat tmxr_clear_modem_control_passthru (TMXR *mp); +t_stat tmxr_set_get_modem_bits (TMLN *lp, int32 bits_to_set, int32 bits_to_clear, int32 *incoming_bits); +t_stat tmxr_set_config_line (TMLN *lp, char *config); t_stat tmxr_set_line_unit (TMXR *mp, int line, UNIT *uptr_poll); t_stat tmxr_set_line_output_unit (TMXR *mp, int line, UNIT *uptr_poll); -t_stat tmxr_set_console_input_unit (UNIT *uptr); +t_stat tmxr_set_console_units (UNIT *rxuptr, UNIT *txuptr); t_stat tmxr_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw); t_stat tmxr_dep (t_value val, t_addr addr, UNIT *uptr, int32 sw); void tmxr_msg (SOCKET sock, char *msg); @@ -154,7 +199,7 @@ extern FILE *sim_deb; /* debug file */ #define tmxr_debug_trace(mp, msg) if (sim_deb && (mp)->dptr && (TMXR_DBG_TRC & (mp)->dptr->dctrl)) sim_debug (TMXR_DBG_TRC, mp->dptr, "%s\n", (msg)); else (void)0 #define tmxr_debug_trace_line(lp, msg) if (sim_deb && (lp)->mp && (lp)->mp->dptr && (TMXR_DBG_TRC & (lp)->mp->dptr->dctrl)) sim_debug (TMXR_DBG_TRC, (lp)->mp->dptr, "%s\n", (msg)); else (void)0 -#if defined(SIM_ASYNCH_IO) && !defined(NO_ASYNCH_MUX) +#if defined(SIM_ASYNCH_IO) && defined(SIM_ASYNCH_MUX) #define tmxr_attach(mp, uptr, cptr) tmxr_attach_ex(mp, uptr, cptr, TRUE) #if (!defined(NOT_MUX_USING_CODE)) #define sim_activate tmxr_activate diff --git a/swtp6800/common/dc-4.c b/swtp6800/common/dc-4.c index 80cfd54d..b4aff57d 100644 --- a/swtp6800/common/dc-4.c +++ b/swtp6800/common/dc-4.c @@ -551,18 +551,18 @@ int32 fdcdata(int32 io, int32 data) } return 0; } else { /* read byte from fdc */ - if (dsk_unit[cur_dsk].pos < SECSIZ) { /* copy bytes from buffer */ - if (dsk_dev.dctrl & DEBUG_read) - printf("\nfdcdata: Reading byte %d u3=%02X", dsk_unit[cur_dsk].pos, dsk_unit[cur_dsk].u3); - val = *((uint8 *)(dsk_unit[cur_dsk].filebuf) + dsk_unit[cur_dsk].pos) & 0xFF; - dsk_unit[cur_dsk].pos++; /* step counter */ - if (dsk_unit[cur_dsk].pos == SECSIZ) { /* done? */ - dsk_unit[cur_dsk].u3 &= ~(BUSY | DRQ); /* clear flags */ - if (dsk_dev.dctrl & DEBUG_write) - printf("\nfdcdata: Sector read complete"); - } - return val; - } else + if (dsk_unit[cur_dsk].pos < SECSIZ) { /* copy bytes from buffer */ + if (dsk_dev.dctrl & DEBUG_read) + printf("\nfdcdata: Reading byte %d u3=%02X", dsk_unit[cur_dsk].pos, dsk_unit[cur_dsk].u3); + val = *((uint8 *)(dsk_unit[cur_dsk].filebuf) + dsk_unit[cur_dsk].pos) & 0xFF; + dsk_unit[cur_dsk].pos++; /* step counter */ + if (dsk_unit[cur_dsk].pos == SECSIZ) { /* done? */ + dsk_unit[cur_dsk].u3 &= ~(BUSY | DRQ); /* clear flags */ + if (dsk_dev.dctrl & DEBUG_write) + printf("\nfdcdata: Sector read complete"); + } + return val; + } else return 0; } } diff --git a/swtp6800/common/m6800.c b/swtp6800/common/m6800.c index c78a5bbb..794184c7 100644 --- a/swtp6800/common/m6800.c +++ b/swtp6800/common/m6800.c @@ -119,9 +119,6 @@ int32 int_req = 0; /* Interrupt request */ int32 mem_fault = 0; /* memory fault flag */ -extern int32 sim_int_char; -extern uint32 sim_brk_types, sim_brk_dflt, sim_brk_summ; /* breakpoint info */ - /* function prototypes */ t_stat m6800_reset (DEVICE *dptr); @@ -151,7 +148,6 @@ extern void CPU_BD_put_mbyte(int32 addr, int32 val); extern void CPU_BD_put_mword(int32 addr, int32 val); extern int32 CPU_BD_get_mbyte(int32 addr); extern int32 CPU_BD_get_mword(int32 addr); -extern int32 sim_switches; /* CPU data structures @@ -303,9 +299,8 @@ int32 oplen[256] = { 3,3,3,0,3,3,3,3,3,3,3,3,0,0,3,3 }; -int32 sim_instr (void) +t_stat sim_instr (void) { - extern int32 sim_interval; int32 IR, OP, DAR, reason, hi, lo, op1; PC = saved_PC & ADDRMASK; /* load local PC */ @@ -1927,7 +1922,7 @@ t_stat m6800_reset (DEVICE *dptr) takes the address from the hex record or the current PC for binary. */ -int32 sim_load (FILE *fileref, char *cptr, char *fnam, int flag) +t_stat sim_load (FILE *fileref, char *cptr, char *fnam, int flag) { int32 i, addr = 0, cnt = 0; @@ -1955,7 +1950,7 @@ int32 sim_load (FILE *fileref, char *cptr, char *fnam, int flag) for M6800 */ -int32 fprint_sym (FILE *of, int32 addr, uint32 *val, UNIT *uptr, int32 sw) +t_stat fprint_sym (FILE *of, t_addr addr, t_value *val, UNIT *uptr, int32 sw) { int32 i, inst, inst1; @@ -2010,7 +2005,7 @@ int32 fprint_sym (FILE *of, int32 addr, uint32 *val, UNIT *uptr, int32 sw) status = error status */ -int32 parse_sym (char *cptr, int32 addr, UNIT *uptr, uint32 *val, int32 sw) +t_stat parse_sym (char *cptr, t_addr addr, UNIT *uptr, t_value *val, int32 sw) { return (-2); } diff --git a/swtp6800/common/mp-b2.c b/swtp6800/common/mp-b2.c index 7b93d7d5..c5253ec9 100644 --- a/swtp6800/common/mp-b2.c +++ b/swtp6800/common/mp-b2.c @@ -76,7 +76,7 @@ address is here, 'nulldev' means no device is available */ struct idev { - int32 (*routine)(); + int32 (*routine)(int32, int32); }; struct idev dev_table[32] = { diff --git a/swtp6800/common/mp-s.c b/swtp6800/common/mp-s.c index 6c9c12a3..47394233 100644 --- a/swtp6800/common/mp-s.c +++ b/swtp6800/common/mp-s.c @@ -1,4 +1,4 @@ -/* mp-s.c: SWTP MP-S serial I/O card emulator +/* mp-s.c: SWTP MP-S serial I/O card simulator Copyright (c) 2005-2011, William Beech @@ -145,7 +145,7 @@ DEVICE ptp_dev = { /* console input service routine */ -int32 sio_svc (UNIT *uptr) +t_stat sio_svc (UNIT *uptr) { int32 temp; @@ -161,7 +161,7 @@ int32 sio_svc (UNIT *uptr) /* paper tape reader input service routine */ -int32 ptr_svc (UNIT *uptr) +t_stat ptr_svc (UNIT *uptr) { int32 temp; @@ -177,40 +177,41 @@ int32 ptr_svc (UNIT *uptr) /* paper tape punch output service routine */ -int32 ptp_svc (UNIT *uptr) +t_stat ptp_svc (UNIT *uptr) { return SCPE_OK; } /* Reset console */ -int32 sio_reset (DEVICE *dptr) +t_stat sio_reset (DEVICE *dptr) { sio_unit.buf = 0; // Data buffer sio_unit.u3 = 0x02; // Status buffer + sio_unit.wait = 10000; sim_activate (&sio_unit, sio_unit.wait); // activate unit return SCPE_OK; } /* Reset paper tape reader */ -int32 ptr_reset (DEVICE *dptr) +t_stat ptr_reset (DEVICE *dptr) { ptr_unit.buf = 0; ptr_unit.u3 = 0x02; - sim_activate (&ptr_unit, ptr_unit.wait); // activate unit -// sim_cancel (&ptr_unit); // deactivate unit +// sim_activate (&ptr_unit, ptr_unit.wait); // activate unit + sim_cancel (&ptr_unit); // deactivate unit return SCPE_OK; } /* Reset paper tape punch */ -int32 ptp_reset (DEVICE *dptr) +t_stat ptp_reset (DEVICE *dptr) { ptp_unit.buf = 0; ptp_unit.u3 = 0x02; - sim_activate (&ptp_unit, ptp_unit.wait); // activate unit -// sim_cancel (&ptp_unit); // deactivate unit +// sim_activate (&ptp_unit, ptp_unit.wait); // activate unit + sim_cancel (&ptp_unit); // deactivate unit return SCPE_OK; } diff --git a/swtp6800/swtp6800/swtp_defs.h b/swtp6800/swtp6800/swtp_defs.h index 6b286405..2466a5c0 100644 --- a/swtp6800/swtp6800/swtp_defs.h +++ b/swtp6800/swtp6800/swtp_defs.h @@ -25,7 +25,7 @@ Copyright (c) 2005-2012, William Beech */ #include -#include "sim_defs.h" // simulator defs +#include "sim_defs.h" // simulator defs /* Memory */