Merge remote-tracking branch 'origin/pr/5'

This commit is contained in:
Paul Koning 2022-06-11 15:30:52 -04:00
commit 88ce8f7072
5 changed files with 261 additions and 0 deletions

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@ -1587,6 +1587,11 @@ IMLAC = ${IMLACD}/imlac_sys.c ${IMLACD}/imlac_cpu.c \
IMLAC_OPT = -I ${IMLACD} ${DISPLAY_OPT}
STUBD = ${SIMHD}/stub
STUB = ${STUBD}/stub_sys.c ${STUBD}/stub_cpu.c
STUB_OPT = -I ${STUBD}
TT2500D = ${SIMHD}/tt2500
TT2500 = ${TT2500D}/tt2500_sys.c ${TT2500D}/tt2500_cpu.c \
${TT2500D}/tt2500_dpy.c ${TT2500D}/tt2500_crt.c ${TT2500D}/tt2500_tv.c \
@ -2250,6 +2255,12 @@ ifneq (,$(call find_test,${IMLAC},imlac))
$@ $(call find_test,${IMLACD},imlac) ${TEST_ARG}
endif
stub : ${BIN}stub${EXE}
${BIN}stub${EXE} : ${STUB} ${SIM}
${MKDIRBIN}
${CC} ${STUB} ${SIM} ${STUB_OPT} ${CC_OUTSPEC} ${LDFLAGS}
tt2500 : ${BIN}tt2500${EXE}
${BIN}tt2500${EXE} : ${TT2500} ${SIM}

16
stub/readme.txt Normal file
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@ -0,0 +1,16 @@
You fill in sim_instr do the instruction decoding and execution.
sim_load will typically take some input file and put it in memory.
cpu_reg should contain all machine state.
parse_sym/fprint_sym is to assemble (with DEPOSIT) and disassemble (EXAMINE-M) instructions.
sim_devices is an array of DEVICE * for peripherals. Something like
build_dev_tab will go through the array and initialize data structures
at run time.
Refer to this: https://github.com/open-simh/simh/blob/master/doc/simh.doc
Make use of asynchronous events. sim_activate posts a future event.
The "svc" routine will be called.

121
stub/stub_cpu.c Normal file
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@ -0,0 +1,121 @@
/* stub_cpu.c: Stub CPU simulator
Copyright (c) 2020, Lars Brinkhoff
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
LARS BRINKHOFF BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
Except as contained in this notice, the name of Lars Brinkhoff shall not be
used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Lars Brinkhoff.
*/
#include "stub_defs.h"
/* Debug */
#define DBG_CPU 0001
/* CPU state. */
static uint16 PC;
/* Function declaration. */
static t_stat cpu_ex (t_value *vptr, t_addr ea, UNIT *uptr, int32 sw);
static t_stat cpu_dep (t_value val, t_addr ea, UNIT *uptr, int32 sw);
static t_stat cpu_reset (DEVICE *dptr);
static UNIT cpu_unit = { UDATA (NULL, UNIT_FIX + UNIT_BINK, 020000) };
REG cpu_reg[] = {
{ ORDATAD (PC, PC, 13, "Program Counter") },
{ NULL }
};
static MTAB cpu_mod[] = {
{ 0 }
};
static DEBTAB cpu_deb[] = {
{ "CPU", DBG_CPU },
{ NULL, 0 }
};
DEVICE cpu_dev = {
"CPU", &cpu_unit, cpu_reg, cpu_mod,
0, 8, 16, 1, 8, 16,
&cpu_ex, &cpu_dep, &cpu_reset,
NULL, NULL, NULL, NULL, DEV_DEBUG, 0, cpu_deb,
NULL, NULL, NULL, NULL, NULL, NULL
};
t_stat sim_instr (void)
{
t_stat reason;
if ((reason = build_dev_tab ()) != SCPE_OK)
return reason;
for (;;) {
AIO_CHECK_EVENT;
if (sim_interval <= 0) {
if ((reason = sim_process_event()) != SCPE_OK)
return reason;
}
if (sim_brk_summ && sim_brk_test(PC, SWMASK('E')))
return STOP_IBKPT;
if (sim_step != 0) {
if (--sim_step == 0)
return SCPE_STEP;
}
}
return SCPE_OK;
}
static t_stat cpu_ex (t_value *vptr, t_addr ea, UNIT *uptr, int32 sw)
{
if (vptr == NULL)
return SCPE_ARG;
if (ea >= 040000)
return SCPE_NXM;
*vptr = M[ea];
return SCPE_OK;
}
static t_stat cpu_dep (t_value val, t_addr ea, UNIT *uptr, int32 sw)
{
if (ea >= 040000)
return SCPE_NXM;
M[ea] = val & 0177777;
return SCPE_OK;
}
static t_bool pc_is_a_subroutine_call (t_addr **ret_addrs)
{
return FALSE;
}
static t_stat
cpu_reset (DEVICE *dptr)
{
sim_brk_types = SWMASK('D') | SWMASK('E');
sim_brk_dflt = SWMASK ('E');
sim_vm_is_subroutine_call = &pc_is_a_subroutine_call;
return SCPE_OK;
}

44
stub/stub_defs.h Normal file
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@ -0,0 +1,44 @@
/* stub_defs.h: Stub simulator definitions
Copyright (c) 2020, Lars Brinkhoff
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
LARS BRINKHOFF BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
Except as contained in this notice, the name of Lars Brinkhoff shall not be
used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Lars Brinkhoff.
21-Apr-20 LB New simulator.
*/
#ifndef STUB_DEFS_H_
#define STUB_DEFS_H_ 0
#include "sim_defs.h"
#define STOP_HALT 1
#define STOP_IBKPT 2
#define STOP_ACCESS 3
extern t_bool build_dev_tab (void);
extern REG cpu_reg[];
extern uint16 M[];
extern DEVICE cpu_dev;
#endif /* STUB_DEFS_H_ */

69
stub/stub_sys.c Normal file
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@ -0,0 +1,69 @@
/* stub_sys.c: Stub simulator interface
Copyright (c) 2020, Lars Brinkhoff
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
LARS BRINKHOFF BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
Except as contained in this notice, the name of Lars Brinkhoff shall not be
used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Lars Brinkhoff.
21-Apr-20 LB New simulator.
*/
#include "stub_defs.h"
int32 sim_emax = 1;
char sim_name[] = "Stub";
uint16 M[040000];
REG *sim_PC = &cpu_reg[0];
DEVICE *sim_devices[] = {
&cpu_dev,
NULL
};
const char *sim_stop_messages[SCPE_BASE] = {
"Unknown error",
"HALT instruction",
"Breakpoint",
"Invalid access",
};
t_stat
sim_load (FILE *fileref, CONST char *cptr, CONST char *fnam, int flag)
{
return SCPE_OK;
}
t_bool build_dev_tab (void)
{
return SCPE_OK;
}
t_stat fprint_sym (FILE *of, t_addr addr, t_value *val,
UNIT *uptr, int32 sw)
{
}
t_stat parse_sym (CONST char *cptr, t_addr addr, UNIT *uptr,
t_value *val, int32 sw)
{
return SCPE_OK;
}