AltairZ80: Add Z80 Interrupt Mode register (IM.)
This commit is contained in:
Howard M. Harte
parent
d0c009504b
commit
898d7cbdbb
1 changed files with 91 additions and 84 deletions
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@ -224,6 +224,7 @@ UNIT cpu_unit = {
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int32 DE1_S; /* alternate DE register */
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int32 HL1_S; /* alternate HL register */
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int32 IFF_S; /* Interrupt Flip Flop */
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int32 IM_S; /* Interrupt Mode register */
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int32 IR_S; /* Interrupt (upper) / Refresh (lower) register */
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int32 AX_S; /* AX register (8086) */
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int32 BX_S; /* BX register (8086) */
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@ -289,8 +290,8 @@ static int32 switcherPort = SWITCHCPU_DEFAULT;
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static struct idev oldSwitcherDevice = { NULL, NULL };
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// CPU_INDEX_8080 is defined in altairz80_defs.h
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#define CPU_INDEX_8086 26
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#define CPU_INDEX_M68K 53
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#define CPU_INDEX_8086 27
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#define CPU_INDEX_M68K 54
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REG cpu_reg[] = {
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// 8080 and Z80 registers
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@ -309,165 +310,168 @@ REG cpu_reg[] = {
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// Z80 registers
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{ HRDATAD (IX, IX_S, 16, "Z80 IX register")
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}, /* 8 */
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{ HRDATAD (IY, IY_S, 16, "Z80 IY register")
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}, /* 9 */
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{ HRDATAD (AF1, AF1_S, 16, "Z80 Alternate Accumulator Flag register")
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}, /* 10 */
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{ HRDATAD (BC1, BC1_S, 16, "Z80 Alternate BC register")
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}, /* 11 */
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{ HRDATAD (DE1, DE1_S, 16, "Z80 Alternate DE register")
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}, /* 12 */
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{ HRDATAD (HL1, HL1_S, 16, "Z80 Alternate HL register")
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}, /* 13 */
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{ GRDATAD (IFF, IFF_S, 2, 2, 0, "Z80 Interrupt Flip Flop register")
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}, /* 6 */
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{ HRDATAD (IR, IR_S, 16, "Z80 Interrupt (upper) / Refresh (lower) register")
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{ HRDATAD (IY, IY_S, 16, "Z80 IY register")
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}, /* 7 */
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{ HRDATAD (AF1, AF1_S, 16, "Z80 Alternate Accumulator Flag register")
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}, /* 8 */
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{ HRDATAD (BC1, BC1_S, 16, "Z80 Alternate BC register")
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}, /* 9 */
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{ HRDATAD (DE1, DE1_S, 16, "Z80 Alternate DE register")
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}, /* 10 */
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{ HRDATAD (HL1, HL1_S, 16, "Z80 Alternate HL register")
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}, /* 11 */
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{ GRDATAD (IFF, IFF_S, 2, 2, 0, "Z80 Interrupt Flip Flop register")
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}, /* 12 */
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{ HRDATAD (IM, IM_S, 2, "Z80 Interrupt Mode register")
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}, /* 13 */
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{ HRDATAD (IR, IR_S, 16, "Z80 Interrupt (upper) / Refresh (lower) register")
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}, /* 14 */
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// 8086 registers
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{ HRDATAD (AX, AX_S, 16, "8086 AX register")
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}, /* 14 8086 */
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}, /* 15 8086 */
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{ GRDATAD (AL, AX_S, 16, 8, 0, "8086 low bits of AX register")
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}, /* 15 8086, low 8 bits of AX */
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}, /* 16 8086, low 8 bits of AX */
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{ GRDATAD (AH, AX_S, 16, 8, 8, "8086 high bits of AX register")
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}, /* 16 8086, high 8 bits of AX */
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}, /* 17 8086, high 8 bits of AX */
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{ HRDATAD (BX, BX_S, 16, "8086 BX register")
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}, /* 17 8086 */
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}, /* 18 8086 */
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{ GRDATAD (BL, BX_S, 16, 8, 0, "8086 low bits of BX register")
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}, /* 18 8086, low 8 bits of BX */
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}, /* 19 8086, low 8 bits of BX */
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{ GRDATAD (BH, BX_S, 16, 8, 8, "8086 high bits of BX register")
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}, /* 19 8086, high 8 bits of BX */
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}, /* 20 8086, high 8 bits of BX */
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{ HRDATAD (CX, CX_S, 16, "8086 CX register")
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}, /* 20 8086 */
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}, /* 21 8086 */
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{ GRDATAD (CL, CX_S, 16, 8, 0, "8086 low bits of CX register")
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}, /* 21 8086, low 8 bits of CX */
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}, /* 22 8086, low 8 bits of CX */
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{ GRDATAD (CH, CX_S, 16, 8, 8, "8086 high bits of CX register")
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}, /* 22 8086, high 8 bits of CX */
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}, /* 23 8086, high 8 bits of CX */
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{ HRDATAD (DX, DX_S, 16, "8086 DX register")
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}, /* 23 8086 */
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}, /* 24 8086 */
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{ GRDATAD (DL, DX_S, 16, 8, 0, "8086 low bits of DX register")
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}, /* 24 8086, low 8 bits of DX */
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}, /* 25 8086, low 8 bits of DX */
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{ GRDATAD (DH, DX_S, 16, 8, 8, "8086 high bits of DX register")
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}, /* 25 8086, high 8 bits of DX */
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}, /* 26 8086, high 8 bits of DX */
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{ HRDATAD (PCX, PCX_S, 16 + MAXBANKSLOG2, "8086 Program Counter register")
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}, /* 26 8086, Program Counter */
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}, /* 27 8086, Program Counter */
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{ HRDATAD (SPX, SPX_S, 16, "8086 Stack Pointer register")
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}, /* 27 8086, Stack Pointer */
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}, /* 28 8086, Stack Pointer */
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{ HRDATAD (BP, BP_S, 16, "8086 Base Pointer register")
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}, /* 28 8086, Base Pointer */
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}, /* 29 8086, Base Pointer */
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{ HRDATAD (SI, SI_S, 16, "8086 Source Index register")
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}, /* 29 8086, Source Index */
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}, /* 30 8086, Source Index */
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{ HRDATAD (DI, DI_S, 16, "8086 Destination Index register")
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}, /* 30 8086, Destination Index */
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}, /* 31 8086, Destination Index */
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{ HRDATAD (CS, CS_S, 16, "8086 Code Segment register")
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}, /* 31 8086, Code Segment */
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}, /* 32 8086, Code Segment */
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{ HRDATAD (DS, DS_S, 16, "8086 Data Segment register")
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}, /* 32 8086, Data Segment */
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}, /* 33 8086, Data Segment */
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{ HRDATAD (ES, ES_S, 16, "8086 Extra Segment register")
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}, /* 33 8086, Extra Segment */
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}, /* 34 8086, Extra Segment */
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{ HRDATAD (SS, SS_S, 16, "8086 Stack Segment register")
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}, /* 34 8086, Stack Segment */
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}, /* 35 8086, Stack Segment */
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{ HRDATAD (FLAGS, FLAGS_S, 16, "8086 Flag register")
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}, /* 35 8086, FLAGS */
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}, /* 36 8086, FLAGS */
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{ HRDATAD (IP, IP_S, 16, "8086 Instruction Pointer register"),
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REG_RO }, /* 36 8086, set via PC */
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REG_RO }, /* 37 8086, set via PC */
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// M68K registers
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{ HRDATAD (M68K_D0, m68k_registers[M68K_REG_D0], 32, "M68K D0 register"),
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}, /* 37 M68K, D0 */
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}, /* 38 M68K, D0 */
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{ HRDATAD (M68K_D1, m68k_registers[M68K_REG_D1], 32, "M68K D1 register"),
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}, /* 38 M68K, D1 */
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}, /* 39 M68K, D1 */
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{ HRDATAD (M68K_D2, m68k_registers[M68K_REG_D2], 32, "M68K D2 register"),
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}, /* 39 M68K, D2 */
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}, /* 40 M68K, D2 */
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{ HRDATAD (M68K_D3, m68k_registers[M68K_REG_D3], 32, "M68K D3 register"),
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}, /* 40 M68K, D3 */
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}, /* 41 M68K, D3 */
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{ HRDATAD (M68K_D4, m68k_registers[M68K_REG_D4], 32, "M68K D4 register"),
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}, /* 41 M68K, D4 */
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}, /* 42 M68K, D4 */
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{ HRDATAD (M68K_D5, m68k_registers[M68K_REG_D5], 32, "M68K D5 register"),
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}, /* 42 M68K, D5 */
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}, /* 43 M68K, D5 */
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{ HRDATAD (M68K_D6, m68k_registers[M68K_REG_D6], 32, "M68K D6 register"),
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}, /* 43 M68K, D6 */
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}, /* 44 M68K, D6 */
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{ HRDATAD (M68K_D7, m68k_registers[M68K_REG_D7], 32, "M68K D7 register"),
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}, /* 44 M68K, D7 */
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}, /* 45 M68K, D7 */
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{ HRDATAD (M68K_A0, m68k_registers[M68K_REG_A0], 32, "M68K A0 register"),
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}, /* 45 M68K, A0 */
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}, /* 46 M68K, A0 */
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{ HRDATAD (M68K_A1, m68k_registers[M68K_REG_A1], 32, "M68K A1 register"),
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}, /* 46 M68K, A1 */
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}, /* 47 M68K, A1 */
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{ HRDATAD (M68K_A2, m68k_registers[M68K_REG_A2], 32, "M68K A2 register"),
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}, /* 47 M68K, A2 */
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}, /* 48 M68K, A2 */
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{ HRDATAD (M68K_A3, m68k_registers[M68K_REG_A3], 32, "M68K A3 register"),
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}, /* 48 M68K, A3 */
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}, /* 49 M68K, A3 */
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{ HRDATAD (M68K_A4, m68k_registers[M68K_REG_A4], 32, "M68K A4 register"),
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}, /* 49 M68K, A4 */
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}, /* 50 M68K, A4 */
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{ HRDATAD (M68K_A5, m68k_registers[M68K_REG_A5], 32, "M68K A5 register"),
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}, /* 50 M68K, A5 */
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}, /* 51 M68K, A5 */
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{ HRDATAD (M68K_A6, m68k_registers[M68K_REG_A6], 32, "M68K A6 register"),
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}, /* 51 M68K, A6 */
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}, /* 52 M68K, A6 */
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{ HRDATAD (M68K_A7, m68k_registers[M68K_REG_A7], 32, "M68K A7 register"),
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}, /* 52 M68K, A7 */
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}, /* 53 M68K, A7 */
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{ HRDATAD (M68K_PC, m68k_registers[M68K_REG_PC], 32, "M68K Program Counter register"),
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}, /* 53 M68K, PC */
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}, /* 54 M68K, PC */
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{ HRDATAD (M68K_SR, m68k_registers[M68K_REG_SR], 32, "M68K Status Register"),
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}, /* 54 M68K, SR */
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}, /* 55 M68K, SR */
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{ HRDATAD (M68K_SP, m68k_registers[M68K_REG_SP], 32, "M68K Stack Pointer register"),
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}, /* 55 M68K, SP */
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}, /* 56 M68K, SP */
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{ HRDATAD (M68K_USP, m68k_registers[M68K_REG_USP], 32, "M68K User Stack Pointer register"),
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}, /* 56 M68K, USP */
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}, /* 57 M68K, USP */
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{ HRDATAD (M68K_ISP, m68k_registers[M68K_REG_ISP], 32, "M68K Interrupt Stack Pointer register"),
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}, /* 57 M68K, ISP */
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}, /* 58 M68K, ISP */
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{ HRDATAD (M68K_MSP, m68k_registers[M68K_REG_MSP], 32, "M68K Master Stack Pointer register"),
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}, /* 58 M68K, MSP */
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}, /* 59 M68K, MSP */
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{ HRDATAD (M68K_SFC, m68k_registers[M68K_REG_SFC], 32, "M68K Source Function Code register"),
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}, /* 59 M68K, SFC */
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}, /* 60 M68K, SFC */
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{ HRDATAD (M68K_DFC, m68k_registers[M68K_REG_DFC], 32, "M68K Destination Function Code register"),
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}, /* 60 M68K, DFC */
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}, /* 61 M68K, DFC */
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{ HRDATAD (M68K_VBR, m68k_registers[M68K_REG_VBR], 32, "M68K Vector Base Register"),
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}, /* 61 M68K, VBR */
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}, /* 62 M68K, VBR */
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{ HRDATAD (M68K_CACR, m68k_registers[M68K_REG_CACR], 32, "M68K Cache Control Register"),
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}, /* 62 M68K, CACR */
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}, /* 63 M68K, CACR */
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{ HRDATAD (M68K_CAAR, m68k_registers[M68K_REG_CAAR], 32, "M68K Cache Address Register"),
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}, /* 63 M68K, CAAR */
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}, /* 64 M68K, CAAR */
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{ HRDATAD (M68K_PREF_ADDR, m68k_registers[M68K_REG_PREF_ADDR], 32, "M68K Last Prefetch Address register"),
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}, /* 64 M68K, PREF_ADDR */
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}, /* 65 M68K, PREF_ADDR */
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{ HRDATAD (M68K_PREF_DATA, m68k_registers[M68K_REG_PREF_DATA], 32, "M68K Last Prefetch Data register"),
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}, /* 65 M68K, PREF_DATA */
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}, /* 66 M68K, PREF_DATA */
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{ HRDATAD (M68K_PPC, m68k_registers[M68K_REG_PPC], 32, "M68K Previous Proram Counter register"),
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}, /* 66 M68K, PPC */
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}, /* 67 M68K, PPC */
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{ HRDATAD (M68K_IR, m68k_registers[M68K_REG_IR], 32, "M68K Instruction Register"),
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}, /* 67 M68K, IR */
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}, /* 68 M68K, IR */
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{ HRDATAD (M68K_CPU_TYPE, m68k_registers[M68K_REG_CPU_TYPE], 32, "M68K CPU Type register"),
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REG_RO }, /* 68 M68K, CPU_TYPE */
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REG_RO }, /* 69 M68K, CPU_TYPE */
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// Pseudo registers
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{ FLDATAD (OPSTOP, cpu_unit.flags, UNIT_CPU_V_OPSTOP, "Stop on invalid operation pseudo register"),
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REG_HRO }, /* 69 */
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REG_HRO }, /* 70 */
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{ HRDATAD (SR, SR, 8, "Front panel switches pseudo register"),
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}, /* 70 */
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{ HRDATAD (BANK, bankSelect, MAXBANKSLOG2, "Active bank pseudo register"),
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}, /* 71 */
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{ HRDATAD (COMMON, common, 32, "Starting address of common memory pseudo register"),
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{ HRDATAD (BANK, bankSelect, MAXBANKSLOG2, "Active bank pseudo register"),
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}, /* 72 */
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{ HRDATAD (SWITCHERPORT, switcherPort, 8, "I/O port for CPU switcher pseudo register"),
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{ HRDATAD (COMMON, common, 32, "Starting address of common memory pseudo register"),
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}, /* 73 */
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{ DRDATAD (CLOCK, clockFrequency, 32, "Clock frequency in kHz for 8080 / Z80 pseudo register"),
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{ HRDATAD (SWITCHERPORT, switcherPort, 8, "I/O port for CPU switcher pseudo register"),
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}, /* 74 */
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{ DRDATAD (SLICE, sliceLength, 16, "Length of time slice for 8080 / Z80 pseudo register"),
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{ DRDATAD (CLOCK, clockFrequency, 32, "Clock frequency in kHz for 8080 / Z80 pseudo register"),
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}, /* 75 */
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{ DRDATAD (SLICE, sliceLength, 16, "Length of time slice for 8080 / Z80 pseudo register"),
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}, /* 76 */
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{ DRDATAD (TSTATES, executedTStates, 32, "Executed t-states for 8080 / Z80 pseudo register"),
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REG_RO }, /* 76 */
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{ HRDATAD (CAPACITY,cpu_unit.capac, 32, "Size of RAM pseudo register"),
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REG_RO }, /* 77 */
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{ HRDATAD (PREVCAP, previousCapacity, 32, "Previous size of RAM pseudo register"),
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{ HRDATAD (CAPACITY,cpu_unit.capac, 32, "Size of RAM pseudo register"),
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REG_RO }, /* 78 */
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{ HRDATAD (PREVCAP, previousCapacity, 32, "Previous size of RAM pseudo register"),
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REG_RO }, /* 79 */
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{ BRDATAD (PCQ, pcq, 16, 16, PCQ_SIZE, "Program counter circular buffer for 8080 /Z80 pseudo register"),
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REG_RO + REG_CIRC }, /* 79 */
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REG_RO + REG_CIRC }, /* 80 */
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{ DRDATAD (PCQP, pcq_p, PCQ_SIZE_LOG2, "Circular buffer head for 8080 / Z80 pseudo register"),
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REG_HRO }, /* 80 */
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REG_HRO }, /* 81 */
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{ HRDATAD (WRU, sim_int_char, 8, "Interrupt character pseudo register"),
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}, /* 81 */
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{ HRDATAD(COMMONLOW,common_low, 1, "If set, use low memory for common area"),
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}, /* 82 */
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{ HRDATAD(COMMONLOW,common_low, 1, "If set, use low memory for common area"),
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}, /* 83 */
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{ NULL }
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};
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@ -4787,6 +4791,7 @@ static t_stat sim_instr_mmu (void) {
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break;
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case 0x46: /* IM 0 */
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IM_S = 0;
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tStates += 8; /* interrupt mode 0 */
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break;
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@ -4869,6 +4874,7 @@ static t_stat sim_instr_mmu (void) {
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break;
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case 0x56: /* IM 1 */
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IM_S = 1;
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tStates += 8; /* interrupt mode 1 */
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break;
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@ -4908,6 +4914,7 @@ static t_stat sim_instr_mmu (void) {
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break;
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case 0x5e: /* IM 2 */
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IM_S = 2;
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tStates += 8; /* interrupt mode 2 */
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break;
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