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pdp11_vh.c: - Added debugging support to trace register, interrupt

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and data traffic (SET VH DEBUG[=REG;INT;XMT;RCV])
                 -  Added SET LOG and SET NOLOG support for logging mux
                    traffic
                 -  Fixed SET VH LINES=n to correctly adjust the number
                    of lines available to be 8, 16, 24, or 32.
                 -  Fixed performance issue avoiding redundant polling in unit
                    service routine (removed 75% of polling overhead)

pdp11_dz.c:      -  Added debugging support to trace register, interrupt
                    and data traffic (SET VH DEBUG[=REG;INT;XMT;RCV])
This commit is contained in:
Mark Pizzolato 2011-06-03 09:27:27 -07:00
parent 338ad5147b
commit 89a27e0816
2 changed files with 1173 additions and 1017 deletions
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29
PDP11/pdp11_dz.c
View file

@ -160,6 +160,20 @@ int32 dz_auto = 0; /* autodiscon enabled */
TMLN dz_ldsc[DZ_MUXES * DZ_LINES] = { 0 }; /* line descriptors */ TMLN dz_ldsc[DZ_MUXES * DZ_LINES] = { 0 }; /* line descriptors */
TMXR dz_desc = { DZ_MUXES * DZ_LINES, 0, 0, dz_ldsc }; /* mux descriptor */ TMXR dz_desc = { DZ_MUXES * DZ_LINES, 0, 0, dz_ldsc }; /* mux descriptor */
/* debugging bitmaps */
#define DBG_REG 0x0001 /* trace read/write registers */
#define DBG_INT 0x0002 /* display transfer requests */
#define DBG_XMT TMXR_DBG_XMT /* display Transmitted Data */
#define DBG_RCV TMXR_DBG_RCV /* display Received Data */
DEBTAB dz_debug[] = {
{"REG", DBG_REG},
{"INT", DBG_INT},
{"XMT", DBG_XMT},
{"RCV", DBG_RCV},
{0}
};
DEVICE dz_dev; DEVICE dz_dev;
t_stat dz_rd (int32 *data, int32 PA, int32 access); t_stat dz_rd (int32 *data, int32 PA, int32 access);
t_stat dz_wr (int32 data, int32 PA, int32 access); t_stat dz_wr (int32 data, int32 PA, int32 access);
@ -249,9 +263,16 @@ DEVICE dz_dev = {
1, DEV_RDX, 8, 1, DEV_RDX, 8, 1, DEV_RDX, 8, 1, DEV_RDX, 8,
&tmxr_ex, &tmxr_dep, &dz_reset, &tmxr_ex, &tmxr_dep, &dz_reset,
NULL, &dz_attach, &dz_detach, NULL, &dz_attach, &dz_detach,
&dz_dib, DEV_FLTA | DEV_DISABLE | DEV_NET | DEV_UBUS | DEV_QBUS &dz_dib, DEV_FLTA | DEV_DISABLE | DEV_NET | DEV_UBUS | DEV_QBUS | DEV_DEBUG,
0, dz_debug
}; };
/* Register names for Debug tracing */
static char *dz_rd_regs[] =
{"CSR ", "RBUF", "TCR ", "MSR " };
static char *dz_wr_regs[] =
{"CSR ", "LPR ", "TCR ", "TDR "};
/* IO dispatch routines, I/O addresses 177601x0 - 177601x7 */ /* IO dispatch routines, I/O addresses 177601x0 - 177601x7 */
t_stat dz_rd (int32 *data, int32 PA, int32 access) t_stat dz_rd (int32 *data, int32 PA, int32 access)
@ -289,6 +310,8 @@ switch ((PA >> 1) & 03) { /* case on PA<2:1> */
break; break;
} }
sim_debug(DBG_REG, &dz_dev, "dz_rd(PA=0x%08X [%s], access=%d, data=0x%X)\n", PA, dz_rd_regs[(PA >> 1) & 03], access, *data);
return SCPE_OK; return SCPE_OK;
} }
@ -298,6 +321,8 @@ int32 dz = ((PA - dz_dib.ba) >> 3) & DZ_MNOMASK; /* get mux num */
int32 i, c, line; int32 i, c, line;
TMLN *lp; TMLN *lp;
sim_debug(DBG_REG, &dz_dev, "dz_wr(PA=0x%08X [%s], access=%d, data=0x%X)\n", PA, dz_wr_regs[(PA >> 1) & 03], access, data);
switch ((PA >> 1) & 03) { /* case on PA<2:1> */ switch ((PA >> 1) & 03) { /* case on PA<2:1> */
case 00: /* CSR */ case 00: /* CSR */
@ -517,6 +542,7 @@ int32 dz;
for (dz = 0; dz < DZ_MUXES; dz++) { /* find 1st mux */ for (dz = 0; dz < DZ_MUXES; dz++) { /* find 1st mux */
if (dz_rxi & (1 << dz)) { if (dz_rxi & (1 << dz)) {
sim_debug(DBG_INT, &dz_dev, "dz_rzinta(dz=%d)\n", dz);
dz_clr_rxint (dz); /* clear intr */ dz_clr_rxint (dz); /* clear intr */
return (dz_dib.vec + (dz * 010)); /* return vector */ return (dz_dib.vec + (dz * 010)); /* return vector */
} }
@ -546,6 +572,7 @@ int32 dz;
for (dz = 0; dz < DZ_MUXES; dz++) { /* find 1st mux */ for (dz = 0; dz < DZ_MUXES; dz++) { /* find 1st mux */
if (dz_txi & (1 << dz)) { if (dz_txi & (1 << dz)) {
sim_debug(DBG_INT, &dz_dev, "dz_txinta(dz=%d)\n", dz);
dz_clr_txint (dz); /* clear intr */ dz_clr_txint (dz); /* clear intr */
return (dz_dib.vec + 4 + (dz * 010)); /* return vector */ return (dz_dib.vec + 4 + (dz * 010)); /* return vector */
} }

2161
PDP11/pdp11_vh.c
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