VAX: Add computed results to instruction history trace
This commit is contained in:
Mark Pizzolato
parent
c8cd853102
commit
8d51b3517d
3 changed files with 627 additions and 529 deletions
113
VAX/vax_cpu.c
113
VAX/vax_cpu.c
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@ -215,18 +215,20 @@
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#define WRITE_L(r) if (spec > (GRN | nPC)) \
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Write (va, r, L_LONG, WA); \
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else R[rn] = (r)
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#define WRITE_Q(rl,rh) if (spec > (GRN | nPC)) { \
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#define WRITE_Q(arl,arh) if (spec > (GRN | nPC)) { \
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if ((Test (va + 7, WA, &mstat) >= 0) || \
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(Test (va, WA, &mstat) < 0)) \
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Write (va, rl, L_LONG, WA); \
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Write (va + 4, rh, L_LONG, WA); \
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Write (va, arl, L_LONG, WA); \
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Write (va + 4, arh, L_LONG, WA); \
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} \
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else { \
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if (rn >= nSP) \
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RSVD_ADDR_FAULT; \
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R[rn] = rl; \
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R[rn + 1] = rh; \
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}
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R[rn] = arl; \
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R[rn + 1] = arh; \
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} \
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r = arl; \
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rh = arh
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#define HIST_MIN 64
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@ -238,7 +240,8 @@ typedef struct {
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int32 PSL;
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int32 opc;
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uint8 inst[INST_SIZE];
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int32 opnd[OPND_SIZE];
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uint32 opnd[OPND_SIZE];
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uint32 res[6];
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} InstHistory;
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uint32 *M = NULL; /* memory */
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@ -668,6 +671,43 @@ for ( ;; ) {
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uint32 va, iad;
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int32 opnd[OPND_SIZE]; /* operand queue */
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/* Optionally record instruction history results from prior instruction */
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if (hst_lnt) {
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InstHistory *hlast = &hst[hst_p ? hst_p-1 : hst_lnt -1];
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int res = (drom[hlast->opc][0] & DR_M_RESMASK) >> DR_V_RESMASK;
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switch ((drom[hlast->opc][0] & DR_M_RESMASK) >> DR_V_RESMASK) {
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case RB_O>>DR_V_RESMASK:
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break;
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case RB_Q>>DR_V_RESMASK:
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hlast->res[1] = rh;
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hlast->res[0] = r;
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break;
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case RB_B>>DR_V_RESMASK:
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case RB_W>>DR_V_RESMASK:
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case RB_L>>DR_V_RESMASK:
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hlast->res[0] = r;
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break;
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case RB_R5>>DR_V_RESMASK:
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hlast->res[5] = R[5];
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hlast->res[4] = R[4];
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case RB_R3>>DR_V_RESMASK:
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hlast->res[3] = R[3];
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hlast->res[2] = R[2];
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case RB_R1>>DR_V_RESMASK:
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hlast->res[1] = R[1];
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case RB_R0>>DR_V_RESMASK:
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hlast->res[0] = R[0];
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break;
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case RB_SP>>DR_V_RESMASK:
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hlast->res[0] = Read (SP, L_LONG, RA);
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break;
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default:
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break;
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}
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}
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if (cpu_astop) {
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cpu_astop = 0;
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ABORT (SCPE_STOP);
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@ -1605,17 +1645,20 @@ for ( ;; ) {
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*/
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case CLRB:
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WRITE_B (0); /* store result */
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r = 0;
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WRITE_B (r); /* store result */
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CC_ZZ1P; /* set cc's */
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break;
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case CLRW:
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WRITE_W (0); /* store result */
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r = 0;
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WRITE_W (r); /* store result */
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CC_ZZ1P; /* set cc's */
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break;
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case CLRL:
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WRITE_L (0); /* store result */
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r = 0;
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WRITE_L (r); /* store result */
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CC_ZZ1P; /* set cc's */
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break;
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@ -1714,19 +1757,22 @@ for ( ;; ) {
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*/
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case MOVB:
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WRITE_B (op0); /* result */
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CC_IIZP_B (op0); /* set cc's */
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r = op0;
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WRITE_B (r); /* result */
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CC_IIZP_B (r); /* set cc's */
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break;
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case MOVW: case MOVZBW:
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WRITE_W (op0); /* result */
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CC_IIZP_W (op0); /* set cc's */
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r = op0;
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WRITE_W (r); /* result */
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CC_IIZP_W (r); /* set cc's */
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break;
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case MOVL: case MOVZBL: case MOVZWL:
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case MOVAB: case MOVAW: case MOVAL: case MOVAQ:
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WRITE_L (op0); /* result */
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CC_IIZP_L (op0); /* set cc's */
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r = op0;
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WRITE_L (r); /* result */
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CC_IIZP_L (r); /* set cc's */
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break;
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case MCOMB:
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@ -3521,7 +3567,7 @@ for (k = 0; k < count; k++) { /* print specified */
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if (hst_switches & SWMASK('T')) /* sim_time */
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fprintf(st, "%10.0f ", h->time);
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fprintf(st, "%08X %08X| ", h->iPC, h->PSL); /* PC, PSL */
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numspec = drom[h->opc][0] & DR_NSPMASK; /* #specifiers */
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numspec = DR_GETNSP (drom[h->opc][0]); /* #specifiers */
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if (opcode[h->opc] == NULL) /* undefined? */
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fprintf (st, "%03X (undefined)", h->opc);
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else if (h->PSL & PSL_FPD) /* FPD set? */
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@ -3594,6 +3640,39 @@ for (i = 1, j = 0, more = FALSE; i <= numspec; i++) { /* loop thru specs */
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break;
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} /* end case */
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} /* end for */
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if ((line == 0) && ((drom[h->opc][0] & DR_M_RESMASK) >> DR_V_RESMASK)) {
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fprintf (st, " ->");
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switch ((drom[h->opc][0] & DR_M_RESMASK) >> DR_V_RESMASK) {
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case RB_O>>DR_V_RESMASK:
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fprintf (st, " %08X %08X %08X %08X", h->res[0], h->res[1], h->res[2], h->res[3]);
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break;
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case RB_Q>>DR_V_RESMASK:
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fprintf (st, " %08X %08X", h->res[0], h->res[1]);
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break;
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case RB_B>>DR_V_RESMASK:
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case RB_W>>DR_V_RESMASK:
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case RB_L>>DR_V_RESMASK:
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fprintf (st, " %08X", h->res[0]);
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break;
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case RB_R5>>DR_V_RESMASK:
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case RB_R3>>DR_V_RESMASK:
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case RB_R1>>DR_V_RESMASK:
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case RB_R0>>DR_V_RESMASK:
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if (1) {
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static const int rcnts[] = {1, 2, 4, 6};
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int i;
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for (i = 0; i < rcnts[((drom[h->opc][0] & DR_M_RESMASK) - RB_R0) >> DR_V_RESMASK]; i++)
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fprintf (st, " R%d:%08X", i, h->res[i]);
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}
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break;
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case RB_SP>>DR_V_RESMASK:
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fprintf (st, " SP: %08X", h->res[0]);
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break;
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default:
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break;
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}
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}
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return more;
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}
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@ -381,6 +381,22 @@
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#define DR_GETNSP(x) ((x) & DR_NSPMASK)
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#define DR_GETUSP(x) (((x) >> DR_V_USPMASK) & DR_M_USPMASK)
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/* Extra bits in the opcode flag word of the Decode ROM array only for history results */
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#define DR_V_RESMASK 8
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#define DR_M_RESMASK 0x0F00
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#define RB_0 (0 << DR_V_RESMASK) /* No Results */
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#define RB_B (1 << DR_V_RESMASK) /* Byte Result */
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#define RB_W (2 << DR_V_RESMASK) /* Word Result */
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#define RB_L (3 << DR_V_RESMASK) /* Long Result */
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#define RB_Q (4 << DR_V_RESMASK) /* Quad Result */
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#define RB_O (5 << DR_V_RESMASK) /* Octa Result */
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#define RB_R0 (6 << DR_V_RESMASK) /* Reg R0 */
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#define RB_R1 (7 << DR_V_RESMASK) /* Regs R0-R1 */
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#define RB_R3 (8 << DR_V_RESMASK) /* Regs R0-R3 */
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#define RB_R5 (9 << DR_V_RESMASK) /* Regs R0-R5 */
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#define RB_SP (10 << DR_V_RESMASK) /* @SP */
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/* Decode ROM: specifier entry */
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#define DR_ACMASK 0x300 /* type */
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417
VAX/vax_sys.c
417
VAX/vax_sys.c
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@ -111,8 +111,11 @@ const char *sim_stop_messages[] = {
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- FPD legal flag (DR_F)
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- number of specifiers for decode bits 2:0>
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- number of specifiers for unimplemented instructions bits<6:4>
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- ONLY for simulator instruction history bits 11:8 reflect where
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results are recorded from
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*/
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const uint16 drom[NUM_INST][MAX_SPEC + 1] = {
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{0, 0, 0, 0, 0, 0, 0}, /* HALT */
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{0, 0, 0, 0, 0, 0, 0}, /* NOP */
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@ -124,8 +127,8 @@ const uint16 drom[NUM_INST][MAX_SPEC + 1] = {
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{0, 0, 0, 0, 0, 0, 0}, /* SVPCTX */
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{4+DR_F, RW, AB, RW, AB, 0, 0}, /* CVTPS */
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{4+DR_F, RW, AB, RW, AB, 0, 0}, /* CVTSP */
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{6, RL, RL, RL, RL, RL, WL}, /* INDEX */
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{4+DR_F, AB, RL, RW, AB, 0, 0}, /* CRC */
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{6 +RB_L, RL, RL, RL, RL, RL, WL}, /* INDEX */
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{4+DR_F +RB_L, AB, RL, RW, AB, 0, 0}, /* CRC */
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{3, RB, RW, AB, 0, 0, 0}, /* PROBER */
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{3, RB, RW, AB, 0, 0, 0}, /* PROBEW */
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{2, AB, AB, 0, 0, 0, 0}, /* INSQUE */
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@ -146,63 +149,63 @@ const uint16 drom[NUM_INST][MAX_SPEC + 1] = {
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{1, BB, 0, 0, 0, 0, 0}, /* BVS */
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{1, BB, 0, 0, 0, 0, 0}, /* BCC */
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{1, BB, 0, 0, 0, 0, 0}, /* BCS */
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{4+DR_F, RW, AB, RW, AB, 0, 0}, /* ADDP4 */
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{6+DR_F, RW, AB, RW, AB, RW, AB}, /* ADDP6 */
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{4+DR_F, RW, AB, RW, AB, 0, 0}, /* SUBP4 */
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{6+DR_F, RW, AB, RW, AB, RW, AB}, /* SUBP6 */
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{5+DR_F, RW, AB, AB, RW, AB, 0}, /* CVTPT */
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{6+DR_F, RW, AB, RW, AB, RW, AB}, /* MULP6 */
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{5+DR_F, RW, AB, AB, RW, AB, 0}, /* CVTTP */
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{6+DR_F, RW, AB, RW, AB, RW, AB}, /* DIVP6 */
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{3+DR_F, RW, AB, AB, 0, 0, 0}, /* MOVC3 */
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{3+DR_F, RW, AB, AB, 0, 0, 0}, /* CMPC3 */
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{4+DR_F, RW, AB, AB, RB, 0, 0}, /* SCANC */
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{4+DR_F, RW, AB, AB, RB, 0, 0}, /* SPANC */
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{5+DR_F, RW, AB, RB, RW, AB, 0}, /* MOVC5 */
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{5+DR_F, RW, AB, RB, RW, AB, 0}, /* CMPC5 */
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{6+DR_F, RW, AB, RB, AB, RW, AB}, /* MOVTC */
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{6+DR_F, RW, AB, RB, AB, RW, AB}, /* MOVTUC */
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{4+DR_F +RB_R3, RW, AB, RW, AB, 0, 0}, /* ADDP4 */
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{6+DR_F +RB_R5, RW, AB, RW, AB, RW, AB}, /* ADDP6 */
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{4+DR_F +RB_R3, RW, AB, RW, AB, 0, 0}, /* SUBP4 */
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{6+DR_F +RB_R5, RW, AB, RW, AB, RW, AB}, /* SUBP6 */
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{5+DR_F +RB_R3, RW, AB, AB, RW, AB, 0}, /* CVTPT */
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{6+DR_F +RB_R5, RW, AB, RW, AB, RW, AB}, /* MULP6 */
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{5+DR_F +RB_R3, RW, AB, AB, RW, AB, 0}, /* CVTTP */
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{6+DR_F +RB_R5, RW, AB, RW, AB, RW, AB}, /* DIVP6 */
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{3+DR_F +RB_R5, RW, AB, AB, 0, 0, 0}, /* MOVC3 */
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{3+DR_F +RB_R3, RW, AB, AB, 0, 0, 0}, /* CMPC3 */
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{4+DR_F +RB_R3, RW, AB, AB, RB, 0, 0}, /* SCANC */
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{4+DR_F +RB_R3, RW, AB, AB, RB, 0, 0}, /* SPANC */
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{5+DR_F +RB_R5, RW, AB, RB, RW, AB, 0}, /* MOVC5 */
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{5+DR_F +RB_R3, RW, AB, RB, RW, AB, 0}, /* CMPC5 */
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{6+DR_F +RB_R5, RW, AB, RB, AB, RW, AB}, /* MOVTC */
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{6+DR_F +RB_R3, RW, AB, RB, AB, RW, AB}, /* MOVTUC */
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{1, BW, 0, 0, 0, 0, 0}, /* BSBW */
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{1, BW, 0, 0, 0, 0, 0}, /* BRW */
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{2, RW, WL, 0, 0, 0, 0}, /* CVTWL */
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{2, RW, WB, 0, 0, 0, 0}, /* CVTWB */
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{3+DR_F, RW, AB, AB, 0, 0, 0}, /* MOVP */
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{3+DR_F, RW, AB, AB, 0, 0, 0}, /* CMPP3 */
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{3+DR_F, RW, AB, WL, 0, 0, 0}, /* CVTPL */
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{4+DR_F, RW, AB, RW, AB, 0, 0}, /* CMPP4 */
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{4+DR_F, RW, AB, AB, AB, 0, 0}, /* EDITPC */
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{4+DR_F, RW, AB, RW, AB, 0, 0}, /* MATCHC */
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{3+DR_F, RB, RW, AB, 0, 0, 0}, /* LOCC */
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{3+DR_F, RB, RW, AB, 0, 0, 0}, /* SKPC */
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{2, RW, WL, 0, 0, 0, 0}, /* MOVZWL */
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{2 +RB_L, RW, WL, 0, 0, 0, 0}, /* CVTWL */
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{2 +RB_B, RW, WB, 0, 0, 0, 0}, /* CVTWB */
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{3+DR_F +RB_R3, RW, AB, AB, 0, 0, 0}, /* MOVP */
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{3+DR_F +RB_R3, RW, AB, AB, 0, 0, 0}, /* CMPP3 */
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{3+DR_F +RB_L, RW, AB, WL, 0, 0, 0}, /* CVTPL */
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{4+DR_F +RB_R3, RW, AB, RW, AB, 0, 0}, /* CMPP4 */
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{4+DR_F +RB_R5, RW, AB, AB, AB, 0, 0}, /* EDITPC */
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{4+DR_F +RB_R3, RW, AB, RW, AB, 0, 0}, /* MATCHC */
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{3+DR_F +RB_R1, RB, RW, AB, 0, 0, 0}, /* LOCC */
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{3+DR_F +RB_R1, RB, RW, AB, 0, 0, 0}, /* SKPC */
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{2 +RB_L, RW, WL, 0, 0, 0, 0}, /* MOVZWL */
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{4, RW, RW, MW, BW, 0, 0}, /* ACBW */
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{2, AW, WL, 0, 0, 0, 0}, /* MOVAW */
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{1, AW, 0, 0, 0, 0, 0}, /* PUSHAW */
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{2, RF, ML, 0, 0, 0, 0}, /* ADDF2 */
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{3, RF, RF, WL, 0, 0, 0}, /* ADDF3 */
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{2, RF, ML, 0, 0, 0, 0}, /* SUBF2 */
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{3, RF, RF, WL, 0, 0, 0}, /* SUBF3 */
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{2, RF, ML, 0, 0, 0, 0}, /* MULF2 */
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{3, RF, RF, WL, 0, 0, 0}, /* MULF3 */
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{2, RF, ML, 0, 0, 0, 0}, /* DIVF2 */
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{3, RF, RF, WL, 0, 0, 0}, /* DIVF3 */
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{2, RF, WB, 0, 0, 0, 0}, /* CVTFB */
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{2, RF, WW, 0, 0, 0, 0}, /* CVTFW */
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{2, RF, WL, 0, 0, 0, 0}, /* CVTFL */
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{2, RF, WL, 0, 0, 0, 0}, /* CVTRFL */
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{2, RB, WL, 0, 0, 0, 0}, /* CVTBF */
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{2, RW, WL, 0, 0, 0, 0}, /* CVTWF */
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{2, RL, WL, 0, 0, 0, 0}, /* CVTLF */
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{1 +RB_SP, AW, 0, 0, 0, 0, 0}, /* PUSHAW */
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{2 +RB_L, RF, ML, 0, 0, 0, 0}, /* ADDF2 */
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{3 +RB_L, RF, RF, WL, 0, 0, 0}, /* ADDF3 */
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{2 +RB_L, RF, ML, 0, 0, 0, 0}, /* SUBF2 */
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{3 +RB_L, RF, RF, WL, 0, 0, 0}, /* SUBF3 */
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{2 +RB_L, RF, ML, 0, 0, 0, 0}, /* MULF2 */
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{3 +RB_L, RF, RF, WL, 0, 0, 0}, /* MULF3 */
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{2 +RB_L, RF, ML, 0, 0, 0, 0}, /* DIVF2 */
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{3 +RB_L, RF, RF, WL, 0, 0, 0}, /* DIVF3 */
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{2 +RB_B, RF, WB, 0, 0, 0, 0}, /* CVTFB */
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{2 +RB_W, RF, WW, 0, 0, 0, 0}, /* CVTFW */
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{2 +RB_L, RF, WL, 0, 0, 0, 0}, /* CVTFL */
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{2 +RB_L, RF, WL, 0, 0, 0, 0}, /* CVTRFL */
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{2 +RB_L, RB, WL, 0, 0, 0, 0}, /* CVTBF */
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{2 +RB_L, RW, WL, 0, 0, 0, 0}, /* CVTWF */
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{2 +RB_L, RL, WL, 0, 0, 0, 0}, /* CVTLF */
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{4, RF, RF, ML, BW, 0, 0}, /* ACBF */
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{2, RF, WL, 0, 0, 0, 0}, /* MOVF */
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{2 +RB_L, RF, WL, 0, 0, 0, 0}, /* MOVF */
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{2, RF, RF, 0, 0, 0, 0}, /* CMPF */
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||||
{2, RF, WL, 0, 0, 0, 0}, /* MNEGF */
|
||||
{2 +RB_L, RF, WL, 0, 0, 0, 0}, /* MNEGF */
|
||||
{1, RF, 0, 0, 0, 0, 0}, /* TSTF */
|
||||
{5, RF, RB, RF, WL, WL, 0}, /* EMODF */
|
||||
{3, RF, RW, AB, 0, 0, 0}, /* POLYF */
|
||||
{2, RF, WQ, 0, 0, 0, 0}, /* CVTFD */
|
||||
{3 +RB_R0, RF, RW, AB, 0, 0, 0}, /* POLYF */
|
||||
{2 +RB_Q, RF, WQ, 0, 0, 0, 0}, /* CVTFD */
|
||||
{0, 0, 0, 0, 0, 0, 0}, /* reserved */
|
||||
{2, RW, WW, 0, 0, 0, 0}, /* ADAWI */
|
||||
{2 +RB_W, RW, WW, 0, 0, 0, 0}, /* ADAWI */
|
||||
{0, 0, 0, 0, 0, 0, 0}, /* reserved */
|
||||
{0, 0, 0, 0, 0, 0, 0}, /* reserved */
|
||||
{0, 0, 0, 0, 0, 0, 0}, /* reserved */
|
||||
|
|
@ -210,94 +213,94 @@ const uint16 drom[NUM_INST][MAX_SPEC + 1] = {
|
|||
{2, AB, AQ, 0, 0, 0, 0}, /* INSQTI */
|
||||
{2, AQ, WL, 0, 0, 0, 0}, /* REMQHI */
|
||||
{2, AQ, WL, 0, 0, 0, 0}, /* REMQTI */
|
||||
{2, RD, MQ, 0, 0, 0, 0}, /* ADDD2 */
|
||||
{3, RD, RD, WQ, 0, 0, 0}, /* ADDD3 */
|
||||
{2, RD, MQ, 0, 0, 0, 0}, /* SUBD2 */
|
||||
{3, RD, RD, WQ, 0, 0, 0}, /* SUBD3 */
|
||||
{2, RD, MQ, 0, 0, 0, 0}, /* MULD2 */
|
||||
{3, RD, RD, WQ, 0, 0, 0}, /* MULD3 */
|
||||
{2, RD, MQ, 0, 0, 0, 0}, /* DIVD2 */
|
||||
{3, RD, RD, WQ, 0, 0, 0}, /* DIVD3 */
|
||||
{2, RD, WB, 0, 0, 0, 0}, /* CVTDB */
|
||||
{2, RD, WW, 0, 0, 0, 0}, /* CVTDW */
|
||||
{2, RD, WL, 0, 0, 0, 0}, /* CVTDL */
|
||||
{2, RD, WL, 0, 0, 0, 0}, /* CVTRDL */
|
||||
{2, RB, WQ, 0, 0, 0, 0}, /* CVTBD */
|
||||
{2, RW, WQ, 0, 0, 0, 0}, /* CVTWD */
|
||||
{2, RL, WQ, 0, 0, 0, 0}, /* CVTLD */
|
||||
{2 +RB_Q, RD, MQ, 0, 0, 0, 0}, /* ADDD2 */
|
||||
{3 +RB_Q, RD, RD, WQ, 0, 0, 0}, /* ADDD3 */
|
||||
{2 +RB_Q, RD, MQ, 0, 0, 0, 0}, /* SUBD2 */
|
||||
{3 +RB_Q, RD, RD, WQ, 0, 0, 0}, /* SUBD3 */
|
||||
{2 +RB_Q, RD, MQ, 0, 0, 0, 0}, /* MULD2 */
|
||||
{3 +RB_Q, RD, RD, WQ, 0, 0, 0}, /* MULD3 */
|
||||
{2 +RB_Q, RD, MQ, 0, 0, 0, 0}, /* DIVD2 */
|
||||
{3 +RB_Q, RD, RD, WQ, 0, 0, 0}, /* DIVD3 */
|
||||
{2 +RB_B, RD, WB, 0, 0, 0, 0}, /* CVTDB */
|
||||
{2 +RB_W, RD, WW, 0, 0, 0, 0}, /* CVTDW */
|
||||
{2 +RB_L, RD, WL, 0, 0, 0, 0}, /* CVTDL */
|
||||
{2 +RB_L, RD, WL, 0, 0, 0, 0}, /* CVTRDL */
|
||||
{2 +RB_Q, RB, WQ, 0, 0, 0, 0}, /* CVTBD */
|
||||
{2 +RB_Q, RW, WQ, 0, 0, 0, 0}, /* CVTWD */
|
||||
{2 +RB_Q, RL, WQ, 0, 0, 0, 0}, /* CVTLD */
|
||||
{4, RD, RD, MQ, BW, 0, 0}, /* ACBD */
|
||||
{2, RD, WQ, 0, 0, 0, 0}, /* MOVD */
|
||||
{2, RD, RD, 0, 0, 0, 0}, /* CMPD */
|
||||
{2, RD, WQ, 0, 0, 0, 0}, /* MNEGD */
|
||||
{2 +RB_Q, RD, WQ, 0, 0, 0, 0}, /* MOVD */
|
||||
{2 +RB_Q, RD, RD, 0, 0, 0, 0}, /* CMPD */
|
||||
{2 +RB_Q, RD, WQ, 0, 0, 0, 0}, /* MNEGD */
|
||||
{1, RD, 0, 0, 0, 0, 0}, /* TSTD */
|
||||
{5, RD, RB, RD, WL, WQ, 0}, /* EMODD */
|
||||
{3, RD, RW, AB, 0, 0, 0}, /* POLYD */
|
||||
{2, RD, WL, 0, 0, 0, 0}, /* CVTDF */
|
||||
{3 +RB_R1, RD, RW, AB, 0, 0, 0}, /* POLYD */
|
||||
{2 +RB_L, RD, WL, 0, 0, 0, 0}, /* CVTDF */
|
||||
{0, 0, 0, 0, 0, 0, 0}, /* reserved */
|
||||
{3, RB, RL, WL, 0, 0, 0}, /* ASHL */
|
||||
{3, RB, RQ, WQ, 0, 0, 0}, /* ASHQ */
|
||||
{3 +RB_L, RB, RL, WL, 0, 0, 0}, /* ASHL */
|
||||
{3 +RB_Q, RB, RQ, WQ, 0, 0, 0}, /* ASHQ */
|
||||
{4, RL, RL, RL, WQ, 0, 0}, /* EMUL */
|
||||
{4, RL, RQ, WL, WL, 0, 0}, /* EDIV */
|
||||
{1, WQ, 0, 0, 0, 0, 0}, /* CLRQ */
|
||||
{2, RQ, WQ, 0, 0, 0, 0}, /* MOVQ */
|
||||
{2, AQ, WL, 0, 0, 0, 0}, /* MOVAQ */
|
||||
{1, AQ, 0, 0, 0, 0, 0}, /* PUSHAQ */
|
||||
{2, RB, MB, 0, 0, 0, 0}, /* ADDB2 */
|
||||
{3, RB, RB, WB, 0, 0, 0}, /* ADDB3 */
|
||||
{2, RB, MB, 0, 0, 0, 0}, /* SUBB2 */
|
||||
{3, RB, RB, WB, 0, 0, 0}, /* SUBB3 */
|
||||
{2, RB, MB, 0, 0, 0, 0}, /* MULB2 */
|
||||
{3, RB, RB, WB, 0, 0, 0}, /* MULB3 */
|
||||
{2, RB, MB, 0, 0, 0, 0}, /* DIVB2 */
|
||||
{3, RB, RB, WB, 0, 0, 0}, /* DIVB3 */
|
||||
{2, RB, MB, 0, 0, 0, 0}, /* BISB2 */
|
||||
{3, RB, RB, WB, 0, 0, 0}, /* BISB3 */
|
||||
{2, RB, MB, 0, 0, 0, 0}, /* BICB2 */
|
||||
{3, RB, RB, WB, 0, 0, 0}, /* BICB3 */
|
||||
{2, RB, MB, 0, 0, 0, 0}, /* XORB2 */
|
||||
{3, RB, RB, WB, 0, 0, 0}, /* XORB3 */
|
||||
{2, RB, WB, 0, 0, 0, 0}, /* MNEGB */
|
||||
{1 +RB_Q, WQ, 0, 0, 0, 0, 0}, /* CLRQ */
|
||||
{2 +RB_Q, RQ, WQ, 0, 0, 0, 0}, /* MOVQ */
|
||||
{2 +RB_L, AQ, WL, 0, 0, 0, 0}, /* MOVAQ */
|
||||
{1 +RB_SP, AQ, 0, 0, 0, 0, 0}, /* PUSHAQ */
|
||||
{2 +RB_B, RB, MB, 0, 0, 0, 0}, /* ADDB2 */
|
||||
{3 +RB_B, RB, RB, WB, 0, 0, 0}, /* ADDB3 */
|
||||
{2 +RB_B, RB, MB, 0, 0, 0, 0}, /* SUBB2 */
|
||||
{3 +RB_B, RB, RB, WB, 0, 0, 0}, /* SUBB3 */
|
||||
{2 +RB_B, RB, MB, 0, 0, 0, 0}, /* MULB2 */
|
||||
{3 +RB_B, RB, RB, WB, 0, 0, 0}, /* MULB3 */
|
||||
{2 +RB_B, RB, MB, 0, 0, 0, 0}, /* DIVB2 */
|
||||
{3 +RB_B, RB, RB, WB, 0, 0, 0}, /* DIVB3 */
|
||||
{2 +RB_B, RB, MB, 0, 0, 0, 0}, /* BISB2 */
|
||||
{3 +RB_B, RB, RB, WB, 0, 0, 0}, /* BISB3 */
|
||||
{2 +RB_B, RB, MB, 0, 0, 0, 0}, /* BICB2 */
|
||||
{3 +RB_B, RB, RB, WB, 0, 0, 0}, /* BICB3 */
|
||||
{2 +RB_B, RB, MB, 0, 0, 0, 0}, /* XORB2 */
|
||||
{3 +RB_B, RB, RB, WB, 0, 0, 0}, /* XORB3 */
|
||||
{2 +RB_B, RB, WB, 0, 0, 0, 0}, /* MNEGB */
|
||||
{3, RB, RB, RB, 0, 0, 0}, /* CASEB */
|
||||
{2, RB, WB, 0, 0, 0, 0}, /* MOVB */
|
||||
{2 +RB_B, RB, WB, 0, 0, 0, 0}, /* MOVB */
|
||||
{2, RB, RB, 0, 0, 0, 0}, /* CMPB */
|
||||
{2, RB, WB, 0, 0, 0, 0}, /* MCOMB */
|
||||
{2, RB, RB, 0, 0, 0, 0}, /* BITB */
|
||||
{1, WB, 0, 0, 0, 0, 0}, /* CLRB */
|
||||
{2 +RB_B, RB, WB, 0, 0, 0, 0}, /* MCOMB */
|
||||
{2 +RB_B, RB, RB, 0, 0, 0, 0}, /* BITB */
|
||||
{1 +RB_B, WB, 0, 0, 0, 0, 0}, /* CLRB */
|
||||
{1, RB, 0, 0, 0, 0, 0}, /* TSTB */
|
||||
{1, MB, 0, 0, 0, 0, 0}, /* INCB */
|
||||
{1, MB, 0, 0, 0, 0, 0}, /* DECB */
|
||||
{2, RB, WL, 0, 0, 0, 0}, /* CVTBL */
|
||||
{2, RB, WW, 0, 0, 0, 0}, /* CVTBW */
|
||||
{2, RB, WL, 0, 0, 0, 0}, /* MOVZBL */
|
||||
{2, RB, WW, 0, 0, 0, 0}, /* MOVZBW */
|
||||
{3, RB, RL, WL, 0, 0, 0}, /* ROTL */
|
||||
{1 +RB_B, MB, 0, 0, 0, 0, 0}, /* INCB */
|
||||
{1 +RB_B, MB, 0, 0, 0, 0, 0}, /* DECB */
|
||||
{2 +RB_L, RB, WL, 0, 0, 0, 0}, /* CVTBL */
|
||||
{2 +RB_W, RB, WW, 0, 0, 0, 0}, /* CVTBW */
|
||||
{2 +RB_L, RB, WL, 0, 0, 0, 0}, /* MOVZBL */
|
||||
{2 +RB_W, RB, WW, 0, 0, 0, 0}, /* MOVZBW */
|
||||
{3 +RB_L, RB, RL, WL, 0, 0, 0}, /* ROTL */
|
||||
{4, RB, RB, MB, BW, 0, 0}, /* ACBB */
|
||||
{2, AB, WL, 0, 0, 0, 0}, /* MOVAB */
|
||||
{1, AB, 0, 0, 0, 0, 0}, /* PUSHAB */
|
||||
{2, RW, MW, 0, 0, 0, 0}, /* ADDW2 */
|
||||
{3, RW, RW, WW, 0, 0, 0}, /* ADDW3 */
|
||||
{2, RW, MW, 0, 0, 0, 0}, /* SUBW2 */
|
||||
{3, RW, RW, WW, 0, 0, 0}, /* SUBW3 */
|
||||
{2, RW, MW, 0, 0, 0, 0}, /* MULW2 */
|
||||
{3, RW, RW, WW, 0, 0, 0}, /* MULW3 */
|
||||
{2, RW, MW, 0, 0, 0, 0}, /* DIVW2 */
|
||||
{3, RW, RW, WW, 0, 0, 0}, /* DIVW3 */
|
||||
{2, RW, MW, 0, 0, 0, 0}, /* BISW2 */
|
||||
{3, RW, RW, WW, 0, 0, 0}, /* BISW3 */
|
||||
{2, RW, MW, 0, 0, 0, 0}, /* BICW2 */
|
||||
{3, RW, RW, WW, 0, 0, 0}, /* BICW3 */
|
||||
{2, RW, MW, 0, 0, 0, 0}, /* XORW2 */
|
||||
{3, RW, RW, WW, 0, 0, 0}, /* XORW3 */
|
||||
{2, RW, WW, 0, 0, 0, 0}, /* MNEGW */
|
||||
{2 +RB_L, AB, WL, 0, 0, 0, 0}, /* MOVAB */
|
||||
{1 +RB_SP, AB, 0, 0, 0, 0, 0}, /* PUSHAB */
|
||||
{2 +RB_W, RW, MW, 0, 0, 0, 0}, /* ADDW2 */
|
||||
{3 +RB_W, RW, RW, WW, 0, 0, 0}, /* ADDW3 */
|
||||
{2 +RB_W, RW, MW, 0, 0, 0, 0}, /* SUBW2 */
|
||||
{3 +RB_W, RW, RW, WW, 0, 0, 0}, /* SUBW3 */
|
||||
{2 +RB_W, RW, MW, 0, 0, 0, 0}, /* MULW2 */
|
||||
{3 +RB_W, RW, RW, WW, 0, 0, 0}, /* MULW3 */
|
||||
{2 +RB_W, RW, MW, 0, 0, 0, 0}, /* DIVW2 */
|
||||
{3 +RB_W, RW, RW, WW, 0, 0, 0}, /* DIVW3 */
|
||||
{2 +RB_W, RW, MW, 0, 0, 0, 0}, /* BISW2 */
|
||||
{3 +RB_W, RW, RW, WW, 0, 0, 0}, /* BISW3 */
|
||||
{2 +RB_W, RW, MW, 0, 0, 0, 0}, /* BICW2 */
|
||||
{3 +RB_W, RW, RW, WW, 0, 0, 0}, /* BICW3 */
|
||||
{2 +RB_W, RW, MW, 0, 0, 0, 0}, /* XORW2 */
|
||||
{3 +RB_W, RW, RW, WW, 0, 0, 0}, /* XORW3 */
|
||||
{2 +RB_W, RW, WW, 0, 0, 0, 0}, /* MNEGW */
|
||||
{3, RW, RW, RW, 0, 0, 0}, /* CASEW */
|
||||
{2, RW, WW, 0, 0, 0, 0}, /* MOVW */
|
||||
{2 +RB_W, RW, WW, 0, 0, 0, 0}, /* MOVW */
|
||||
{2, RW, RW, 0, 0, 0, 0}, /* CMPW */
|
||||
{2, RW, WW, 0, 0, 0, 0}, /* MCOMW */
|
||||
{2 +RB_W, RW, WW, 0, 0, 0, 0}, /* MCOMW */
|
||||
{2, RW, RW, 0, 0, 0, 0}, /* BITW */
|
||||
{1, WW, 0, 0, 0, 0, 0}, /* CLRW */
|
||||
{1 +RB_W, WW, 0, 0, 0, 0, 0}, /* CLRW */
|
||||
{1, RW, 0, 0, 0, 0, 0}, /* TSTW */
|
||||
{1, MW, 0, 0, 0, 0, 0}, /* INCW */
|
||||
{1, MW, 0, 0, 0, 0, 0}, /* DECW */
|
||||
{1 +RB_W, MW, 0, 0, 0, 0, 0}, /* INCW */
|
||||
{1 +RB_W, MW, 0, 0, 0, 0, 0}, /* DECW */
|
||||
{1, RW, 0, 0, 0, 0, 0}, /* BISPSW */
|
||||
{1, RW, 0, 0, 0, 0, 0}, /* BICPSW */
|
||||
{1, RW, 0, 0, 0, 0, 0}, /* POPR */
|
||||
|
|
@ -306,38 +309,38 @@ const uint16 drom[NUM_INST][MAX_SPEC + 1] = {
|
|||
{1, RW, 0, 0, 0, 0, 0}, /* CHME */
|
||||
{1, RW, 0, 0, 0, 0, 0}, /* CHMS */
|
||||
{1, RW, 0, 0, 0, 0, 0}, /* CHMU */
|
||||
{2, RL, ML, 0, 0, 0, 0}, /* ADDL2 */
|
||||
{3, RL, RL, WL, 0, 0, 0}, /* ADDL3 */
|
||||
{2, RL, ML, 0, 0, 0, 0}, /* SUBL2 */
|
||||
{3, RL, RL, WL, 0, 0, 0}, /* SUBL3 */
|
||||
{2, RL, ML, 0, 0, 0, 0}, /* MULL2 */
|
||||
{3, RL, RL, WL, 0, 0, 0}, /* MULL3 */
|
||||
{2, RL, ML, 0, 0, 0, 0}, /* DIVL2 */
|
||||
{3, RL, RL, WL, 0, 0, 0}, /* DIVL3 */
|
||||
{2, RL, ML, 0, 0, 0, 0}, /* BISL2 */
|
||||
{3, RL, RL, WL, 0, 0, 0}, /* BISL3 */
|
||||
{2, RL, ML, 0, 0, 0, 0}, /* BICL2 */
|
||||
{3, RL, RL, WL, 0, 0, 0}, /* BICL3 */
|
||||
{2, RL, ML, 0, 0, 0, 0}, /* XORL2 */
|
||||
{3, RL, RL, WL, 0, 0, 0}, /* XORL3 */
|
||||
{2, RL, WL, 0, 0, 0, 0}, /* MNEGL */
|
||||
{2 +RB_L, RL, ML, 0, 0, 0, 0}, /* ADDL2 */
|
||||
{3 +RB_L, RL, RL, WL, 0, 0, 0}, /* ADDL3 */
|
||||
{2 +RB_L, RL, ML, 0, 0, 0, 0}, /* SUBL2 */
|
||||
{3 +RB_L, RL, RL, WL, 0, 0, 0}, /* SUBL3 */
|
||||
{2 +RB_L, RL, ML, 0, 0, 0, 0}, /* MULL2 */
|
||||
{3 +RB_L, RL, RL, WL, 0, 0, 0}, /* MULL3 */
|
||||
{2 +RB_L, RL, ML, 0, 0, 0, 0}, /* DIVL2 */
|
||||
{3 +RB_L, RL, RL, WL, 0, 0, 0}, /* DIVL3 */
|
||||
{2 +RB_L, RL, ML, 0, 0, 0, 0}, /* BISL2 */
|
||||
{3 +RB_L, RL, RL, WL, 0, 0, 0}, /* BISL3 */
|
||||
{2 +RB_L, RL, ML, 0, 0, 0, 0}, /* BICL2 */
|
||||
{3 +RB_L, RL, RL, WL, 0, 0, 0}, /* BICL3 */
|
||||
{2 +RB_L, RL, ML, 0, 0, 0, 0}, /* XORL2 */
|
||||
{3 +RB_L, RL, RL, WL, 0, 0, 0}, /* XORL3 */
|
||||
{2 +RB_L, RL, WL, 0, 0, 0, 0}, /* MNEGL */
|
||||
{3, RL, RL, RL, 0, 0, 0}, /* CASEL */
|
||||
{2, RL, WL, 0, 0, 0, 0}, /* MOVL */
|
||||
{2 +RB_L, RL, WL, 0, 0, 0, 0}, /* MOVL */
|
||||
{2, RL, RL, 0, 0, 0, 0}, /* CMPL */
|
||||
{2, RL, WL, 0, 0, 0, 0}, /* MCOML */
|
||||
{2 +RB_L, RL, WL, 0, 0, 0, 0}, /* MCOML */
|
||||
{2, RL, RL, 0, 0, 0, 0}, /* BITL */
|
||||
{1, WL, 0, 0, 0, 0, 0}, /* CLRL */
|
||||
{1 +RB_L, WL, 0, 0, 0, 0, 0}, /* CLRL */
|
||||
{1, RL, 0, 0, 0, 0, 0}, /* TSTL */
|
||||
{1, ML, 0, 0, 0, 0, 0}, /* INCL */
|
||||
{1, ML, 0, 0, 0, 0, 0}, /* DECL */
|
||||
{2, RL, ML, 0, 0, 0, 0}, /* ADWC */
|
||||
{2, RL, ML, 0, 0, 0, 0}, /* SBWC */
|
||||
{1 +RB_L, ML, 0, 0, 0, 0, 0}, /* INCL */
|
||||
{1 +RB_L, ML, 0, 0, 0, 0, 0}, /* DECL */
|
||||
{2 +RB_L, RL, ML, 0, 0, 0, 0}, /* ADWC */
|
||||
{2 +RB_L, RL, ML, 0, 0, 0, 0}, /* SBWC */
|
||||
{2, RL, RL, 0, 0, 0, 0}, /* MTPR */
|
||||
{2, RL, WL, 0, 0, 0, 0}, /* MFPR */
|
||||
{1, WL, 0, 0, 0, 0, 0}, /* MOVPSL */
|
||||
{1, RL, 0, 0, 0, 0, 0}, /* PUSHL */
|
||||
{2, AL, WL, 0, 0, 0, 0}, /* MOVAL */
|
||||
{1, AL, 0, 0, 0, 0, 0}, /* PUSHAL */
|
||||
{2 +RB_L, RL, WL, 0, 0, 0, 0}, /* MFPR */
|
||||
{1 +RB_L, WL, 0, 0, 0, 0, 0}, /* MOVPSL */
|
||||
{1 +RB_SP, RL, 0, 0, 0, 0, 0}, /* PUSHL */
|
||||
{2 +RB_L, AL, WL, 0, 0, 0, 0}, /* MOVAL */
|
||||
{1 +RB_SP, AL, 0, 0, 0, 0, 0}, /* PUSHAL */
|
||||
{3, RL, VB, BB, 0, 0, 0}, /* BBS */
|
||||
{3, RL, VB, BB, 0, 0, 0}, /* BBC */
|
||||
{3, RL, VB, BB, 0, 0, 0}, /* BBSS */
|
||||
|
|
@ -348,22 +351,22 @@ const uint16 drom[NUM_INST][MAX_SPEC + 1] = {
|
|||
{3, RL, VB, BB, 0, 0, 0}, /* BBCCI */
|
||||
{2, RL, BB, 0, 0, 0, 0}, /* BLBS */
|
||||
{2, RL, BB, 0, 0, 0, 0}, /* BLBC */
|
||||
{4, RL, RB, VB, WL, 0, 0}, /* FFS */
|
||||
{4, RL, RB, VB, WL, 0, 0}, /* FFC */
|
||||
{4 +RB_L, RL, RB, VB, WL, 0, 0}, /* FFS */
|
||||
{4 +RB_L, RL, RB, VB, WL, 0, 0}, /* FFC */
|
||||
{4, RL, RB, VB, RL, 0, 0}, /* CMPV */
|
||||
{4, RL, RB, VB, RL, 0, 0}, /* CMPZV */
|
||||
{4, RL, RB, VB, WL, 0, 0}, /* EXTV */
|
||||
{4, RL, RB, VB, WL, 0, 0}, /* EXTZV */
|
||||
{4 +RB_L, RL, RB, VB, WL, 0, 0}, /* EXTV */
|
||||
{4 +RB_L, RL, RB, VB, WL, 0, 0}, /* EXTZV */
|
||||
{4, RL, RL, RB, VB, 0, 0}, /* INSV */
|
||||
{4, RL, RL, ML, BW, 0, 0}, /* ACBL */
|
||||
{3, RL, ML, BB, 0, 0, 0}, /* AOBLSS */
|
||||
{3, RL, ML, BB, 0, 0, 0}, /* AOBLEQ */
|
||||
{2, ML, BB, 0, 0, 0, 0}, /* SOBGEQ */
|
||||
{2, ML, BB, 0, 0, 0, 0}, /* SOBGTR */
|
||||
{2, RL, WB, 0, 0, 0, 0}, /* CVTLB */
|
||||
{2, RL, WW, 0, 0, 0, 0}, /* CVTLW */
|
||||
{6+DR_F, RB, RW, AB, RB, RW, AB}, /* ASHP */
|
||||
{3+DR_F, RL, RW, AB, 0, 0, 0}, /* CVTLP */
|
||||
{2 +RB_B, RL, WB, 0, 0, 0, 0}, /* CVTLB */
|
||||
{2 +RB_W, RL, WW, 0, 0, 0, 0}, /* CVTLW */
|
||||
{6+DR_F+RB_R3, RB, RW, AB, RB, RW, AB}, /* ASHP */
|
||||
{3+DR_F+RB_R3, RL, RW, AB, 0, 0, 0}, /* CVTLP */
|
||||
{2, AB, AB, 0, 0, 0, 0}, /* CALLG */
|
||||
{2, RL, AB, 0, 0, 0, 0}, /* CALLS */
|
||||
{0, 0, 0, 0, 0, 0, 0}, /* XFC */
|
||||
|
|
@ -420,8 +423,8 @@ const uint16 drom[NUM_INST][MAX_SPEC + 1] = {
|
|||
{0, 0, 0, 0, 0, 0, 0},
|
||||
{0, 0, 0, 0, 0, 0, 0}, /* 130-13F */
|
||||
{0, 0, 0, 0, 0, 0, 0},
|
||||
{ODC(2), RD, WO, 0, 0, 0, 0}, /* CVTDH */
|
||||
{2, RG, WL, 0, 0, 0, 0}, /* CVTGF */
|
||||
{ODC(2) +RB_O, RD, WO, 0, 0, 0, 0}, /* CVTDH */
|
||||
{2 +RB_L, RG, WL, 0, 0, 0, 0}, /* CVTGF */
|
||||
{0, 0, 0, 0, 0, 0, 0},
|
||||
{0, 0, 0, 0, 0, 0, 0},
|
||||
{0, 0, 0, 0, 0, 0, 0},
|
||||
|
|
@ -434,29 +437,29 @@ const uint16 drom[NUM_INST][MAX_SPEC + 1] = {
|
|||
{0, 0, 0, 0, 0, 0, 0},
|
||||
{0, 0, 0, 0, 0, 0, 0},
|
||||
{0, 0, 0, 0, 0, 0, 0},
|
||||
{2, RG, MQ, 0, 0, 0, 0}, /* ADDG2 */
|
||||
{3, RG, RG, WQ, 0, 0, 0}, /* ADDG3 */
|
||||
{2, RG, MQ, 0, 0, 0, 0}, /* SUBG2 */
|
||||
{3, RG, RG, WQ, 0, 0, 0}, /* SUBG3 */
|
||||
{2, RG, MQ, 0, 0, 0, 0}, /* MULG2 */
|
||||
{3, RG, RG, WQ, 0, 0, 0}, /* MULG3 */
|
||||
{2, RG, MQ, 0, 0, 0, 0}, /* DIVG2 */
|
||||
{3, RG, RG, WQ, 0, 0, 0}, /* DIVG3 */
|
||||
{2, RG, WB, 0, 0, 0, 0}, /* CVTGB */
|
||||
{2, RG, WW, 0, 0, 0, 0}, /* CVTGW */
|
||||
{2, RG, WL, 0, 0, 0, 0}, /* CVTGL */
|
||||
{2, RG, WL, 0, 0, 0, 0}, /* CVTRGL */
|
||||
{2, RB, WQ, 0, 0, 0, 0}, /* CVTBG */
|
||||
{2, RW, WQ, 0, 0, 0, 0}, /* CVTWG */
|
||||
{2, RL, WQ, 0, 0, 0, 0}, /* CVTLG */
|
||||
{2 +RB_Q, RG, MQ, 0, 0, 0, 0}, /* ADDG2 */
|
||||
{3 +RB_Q, RG, RG, WQ, 0, 0, 0}, /* ADDG3 */
|
||||
{2 +RB_Q, RG, MQ, 0, 0, 0, 0}, /* SUBG2 */
|
||||
{3 +RB_Q, RG, RG, WQ, 0, 0, 0}, /* SUBG3 */
|
||||
{2 +RB_Q, RG, MQ, 0, 0, 0, 0}, /* MULG2 */
|
||||
{3 +RB_Q, RG, RG, WQ, 0, 0, 0}, /* MULG3 */
|
||||
{2 +RB_Q, RG, MQ, 0, 0, 0, 0}, /* DIVG2 */
|
||||
{3 +RB_Q, RG, RG, WQ, 0, 0, 0}, /* DIVG3 */
|
||||
{2 +RB_B, RG, WB, 0, 0, 0, 0}, /* CVTGB */
|
||||
{2 +RB_W, RG, WW, 0, 0, 0, 0}, /* CVTGW */
|
||||
{2 +RB_L, RG, WL, 0, 0, 0, 0}, /* CVTGL */
|
||||
{2 +RB_L, RG, WL, 0, 0, 0, 0}, /* CVTRGL */
|
||||
{2 +RB_Q, RB, WQ, 0, 0, 0, 0}, /* CVTBG */
|
||||
{2 +RB_Q, RW, WQ, 0, 0, 0, 0}, /* CVTWG */
|
||||
{2 +RB_Q, RL, WQ, 0, 0, 0, 0}, /* CVTLG */
|
||||
{4, RG, RG, MQ, BW, 0, 0}, /* ACBG */
|
||||
{2, RG, WQ, 0, 0, 0, 0}, /* MOVG */
|
||||
{2 +RB_Q, RG, WQ, 0, 0, 0, 0}, /* MOVG */
|
||||
{2, RG, RG, 0, 0, 0, 0}, /* CMPG */
|
||||
{2, RG, WQ, 0, 0, 0, 0}, /* MNEGG */
|
||||
{2 +RB_Q, RG, WQ, 0, 0, 0, 0}, /* MNEGG */
|
||||
{1, RG, 0, 0, 0, 0, 0}, /* TSTG */
|
||||
{5, RG, RW, RG, WL, WQ, 0}, /* EMODG */
|
||||
{3, RG, RW, AB, 0, 0, 0}, /* POLYG */
|
||||
{ODC(2), RG, WO, 0, 0, 0, 0}, /* CVTGH */
|
||||
{3 +RB_R1, RG, RW, AB, 0, 0, 0}, /* POLYG */
|
||||
{ODC(2) +RB_O, RG, WO, 0, 0, 0, 0}, /* CVTGH */
|
||||
{0, 0, 0, 0, 0, 0, 0}, /* reserved */
|
||||
{0, 0, 0, 0, 0, 0, 0}, /* reserved */
|
||||
{0, 0, 0, 0, 0, 0, 0}, /* reserved */
|
||||
|
|
@ -466,38 +469,38 @@ const uint16 drom[NUM_INST][MAX_SPEC + 1] = {
|
|||
{0, 0, 0, 0, 0, 0, 0}, /* reserved */
|
||||
{0, 0, 0, 0, 0, 0, 0}, /* reserved */
|
||||
{0, 0, 0, 0, 0, 0, 0}, /* reserved */
|
||||
{ODC(2), RH, MO, 0, 0, 0, 0}, /* ADDH2 */
|
||||
{ODC(3), RH, RH, WO, 0, 0, 0}, /* ADDH3 */
|
||||
{ODC(2), RH, MO, 0, 0, 0, 0}, /* SUBH2 */
|
||||
{ODC(3), RH, RH, WO, 0, 0, 0}, /* SUBH3 */
|
||||
{ODC(2), RH, MO, 0, 0, 0, 0}, /* MULH2 */
|
||||
{ODC(3), RH, RH, WO, 0, 0, 0}, /* MULH3 */
|
||||
{ODC(2), RH, MO, 0, 0, 0, 0}, /* DIVH2 */
|
||||
{ODC(3), RH, RH, WO, 0, 0, 0}, /* DIVH3 */
|
||||
{ODC(2), RH, WB, 0, 0, 0, 0}, /* CVTHB */
|
||||
{ODC(2), RH, WW, 0, 0, 0, 0}, /* CVTHW */
|
||||
{ODC(2), RH, WL, 0, 0, 0, 0}, /* CVTHL */
|
||||
{ODC(2), RH, WL, 0, 0, 0, 0}, /* CVTRHL */
|
||||
{ODC(2), RB, WO, 0, 0, 0, 0}, /* CVTBH */
|
||||
{ODC(2), RW, WO, 0, 0, 0, 0}, /* CVTWH */
|
||||
{ODC(2), RL, WO, 0, 0, 0, 0}, /* CVTLH */
|
||||
{ODC(2) +RB_O, RH, MO, 0, 0, 0, 0}, /* ADDH2 */
|
||||
{ODC(3) +RB_O, RH, RH, WO, 0, 0, 0}, /* ADDH3 */
|
||||
{ODC(2) +RB_O, RH, MO, 0, 0, 0, 0}, /* SUBH2 */
|
||||
{ODC(3) +RB_O, RH, RH, WO, 0, 0, 0}, /* SUBH3 */
|
||||
{ODC(2) +RB_O, RH, MO, 0, 0, 0, 0}, /* MULH2 */
|
||||
{ODC(3) +RB_O, RH, RH, WO, 0, 0, 0}, /* MULH3 */
|
||||
{ODC(2) +RB_O, RH, MO, 0, 0, 0, 0}, /* DIVH2 */
|
||||
{ODC(3) +RB_O, RH, RH, WO, 0, 0, 0}, /* DIVH3 */
|
||||
{ODC(2) +RB_B, RH, WB, 0, 0, 0, 0}, /* CVTHB */
|
||||
{ODC(2) +RB_W, RH, WW, 0, 0, 0, 0}, /* CVTHW */
|
||||
{ODC(2) +RB_L, RH, WL, 0, 0, 0, 0}, /* CVTHL */
|
||||
{ODC(2) +RB_O, RH, WL, 0, 0, 0, 0}, /* CVTRHL */
|
||||
{ODC(2) +RB_O, RB, WO, 0, 0, 0, 0}, /* CVTBH */
|
||||
{ODC(2) +RB_O, RW, WO, 0, 0, 0, 0}, /* CVTWH */
|
||||
{ODC(2) +RB_O, RL, WO, 0, 0, 0, 0}, /* CVTLH */
|
||||
{ODC(4), RH, RH, MO, BW, 0, 0}, /* ACBH */
|
||||
{ODC(2), RH, RO, 0, 0, 0, 0}, /* MOVH */
|
||||
{ODC(2) +RB_O, RH, RO, 0, 0, 0, 0}, /* MOVH */
|
||||
{ODC(2), RH, RH, 0, 0, 0, 0}, /* CMPH */
|
||||
{ODC(2), RH, WO, 0, 0, 0, 0}, /* MNEGH */
|
||||
{ODC(2) +RB_O, RH, WO, 0, 0, 0, 0}, /* MNEGH */
|
||||
{ODC(1), RH, 0, 0, 0, 0, 0}, /* TSTH */
|
||||
{ODC(5), RH, RW, RH, WL, WO, 0}, /* EMODH */
|
||||
{ODC(3), RH, RW, AB, 0, 0, 0}, /* POLYH */
|
||||
{ODC(2), RH, WQ, 0, 0, 0, 0}, /* CVTHG */
|
||||
{ODC(3) +RB_R3, RH, RW, AB, 0, 0, 0}, /* POLYH */
|
||||
{ODC(2) +RB_Q, RH, WQ, 0, 0, 0, 0}, /* CVTHG */
|
||||
{0, 0, 0, 0, 0, 0, 0}, /* reserved */
|
||||
{0, 0, 0, 0, 0, 0, 0}, /* reserved */
|
||||
{0, 0, 0, 0, 0, 0, 0}, /* reserved */
|
||||
{0, 0, 0, 0, 0, 0, 0}, /* reserved */
|
||||
{0, 0, 0, 0, 0, 0, 0}, /* reserved */
|
||||
{ODC(1), WO, 0, 0, 0, 0, 0}, /* CLRO */
|
||||
{ODC(2), RO, RO, 0, 0, 0, 0}, /* MOVO */
|
||||
{ODC(2), AO, WL, 0, 0, 0, 0}, /* MOVAO*/
|
||||
{ODC(1), AO, 0, 0, 0, 0, 0}, /* PUSHAO*/
|
||||
{ODC(1) +RB_O, WO, 0, 0, 0, 0, 0}, /* CLRO */
|
||||
{ODC(2) +RB_O, RO, RO, 0, 0, 0, 0}, /* MOVO */
|
||||
{ODC(2) +RB_L, AO, WL, 0, 0, 0, 0}, /* MOVAO*/
|
||||
{ODC(1) +RB_SP, AO, 0, 0, 0, 0, 0}, /* PUSHAO*/
|
||||
{0, 0, 0, 0, 0, 0, 0}, /* 180-18F */
|
||||
{0, 0, 0, 0, 0, 0, 0},
|
||||
{0, 0, 0, 0, 0, 0, 0},
|
||||
|
|
@ -522,8 +525,8 @@ const uint16 drom[NUM_INST][MAX_SPEC + 1] = {
|
|||
{0, 0, 0, 0, 0, 0, 0},
|
||||
{0, 0, 0, 0, 0, 0, 0},
|
||||
{0, 0, 0, 0, 0, 0, 0},
|
||||
{ODC(2), RF, WO, 0, 0, 0, 0}, /* CVTFH */
|
||||
{2, RF, WQ, 0, 0, 0, 0}, /* CVTFG */
|
||||
{ODC(2) +RB_O, RF, WO, 0, 0, 0, 0}, /* CVTFH */
|
||||
{2 +RB_Q, RF, WQ, 0, 0, 0, 0}, /* CVTFG */
|
||||
{0, 0, 0, 0, 0, 0, 0},
|
||||
{0, 0, 0, 0, 0, 0, 0},
|
||||
{0, 0, 0, 0, 0, 0, 0},
|
||||
|
|
@ -616,8 +619,8 @@ const uint16 drom[NUM_INST][MAX_SPEC + 1] = {
|
|||
{0, 0, 0, 0, 0, 0, 0},
|
||||
{0, 0, 0, 0, 0, 0, 0},
|
||||
{0, 0, 0, 0, 0, 0, 0},
|
||||
{ODC(2), RH, WL, 0, 0, 0, 0}, /* CVTHF */
|
||||
{ODC(2), RH, WQ, 0, 0, 0, 0}, /* CVTHD */
|
||||
{ODC(2) +RB_B, RH, WL, 0, 0, 0, 0}, /* CVTHF */
|
||||
{ODC(2) +RB_Q, RH, WQ, 0, 0, 0, 0}, /* CVTHD */
|
||||
{0, 0, 0, 0, 0, 0, 0},
|
||||
{0, 0, 0, 0, 0, 0, 0},
|
||||
{0, 0, 0, 0, 0, 0, 0},
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue