diff --git a/MDS-800/MDS-800/Mds-800.cfg b/MDS-800/MDS-800/Mds-800.cfg deleted file mode 100644 index 3db17a13..00000000 --- a/MDS-800/MDS-800/Mds-800.cfg +++ /dev/null @@ -1,44 +0,0 @@ -/* mds-800.cfg: Intel mds-800 simulator definitions - - This file holds the configuration for the mds-800 - boards I/O and Memory. - - Copyright (c) 2015, William A. Beech - - Permission is hereby granted, free of charge, to any person obtaining a - copy of this software and associated documentation files (the "Software"), - to deal in the Software without restriction, including without limitation - the rights to use, copy, modify, merge, publish, distribute, sublicense, - and/or sell copies of the Software, and to permit persons to whom the - Software is furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be included in - all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - William A. Beech BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - - Except as contained in this notice, the name of William A. Beech shall not be - used in advertising or otherwise to promote the sale, use or other dealings - in this Software without prior written authorization from William A. Beech. - - 16 Dec 12 - Original file - 08 Apr 15 - Modified to be mds-800.cfg file to set base and size. - Changed tabs to spaces - -*/ - -/* set the base I/O address for the iSBC 208 */ -#define SBC208_BASE 0x40 - -/* configure interrupt request line */ -#define SBC208_INT INT_1 - -/* set the base and size for the iSBC 064 */ -#define SBC064_BASE 0x0000 -#define SBC064_SIZE 0x10000 - diff --git a/MDS-800/MDS-800/Mds-800.vsd b/MDS-800/MDS-800/Mds-800.vsd deleted file mode 100644 index a0acb997..00000000 Binary files a/MDS-800/MDS-800/Mds-800.vsd and /dev/null differ diff --git a/MDS-800/MDS-800/mds-800_sys.c b/MDS-800/MDS-800/mds-800_sys.c deleted file mode 100644 index fa346ccb..00000000 --- a/MDS-800/MDS-800/mds-800_sys.c +++ /dev/null @@ -1,81 +0,0 @@ -/* system_80_10_sys.c: multibus system interface - - Copyright (c) 2010, William A. Beech - - Permission is hereby granted, free of charge, to any person obtaining a - copy of this software and associated documentation files (the "Software"), - to deal in the Software without restriction, including without limitation - the rights to use, copy, modify, merge, publish, distribute, sublicense, - and/or sell copies of the Software, and to permit persons to whom the - Software is furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be included in - all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - William A. Beech BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - - Except as contained in this notice, the name of William A. Beech shall not be - used in advertising or otherwise to promote the sale, use or other dealings - in this Software without prior written authorization from William A. Beech. - - ?? ??? 10 - Original file. - 16 Dec 12 - Modified to use isbc_80_10.cfg file to set base and size. - 08 Apr 15 - Modified to use mds-800.cfg file to set base and size. - Changed tabs to spaces - -*/ - -#include "system_defs.h" - -extern DEVICE i8080_dev; -extern REG i8080_reg[]; -extern DEVICE i8251_dev; -extern DEVICE i8255_dev; -extern DEVICE EPROM_dev; -extern DEVICE RAM_dev; -extern DEVICE multibus_dev; -extern DEVICE isbc208_dev; -extern DEVICE isbc064_dev; - -/* SCP data structures - - sim_name simulator name string - sim_PC pointer to saved PC register descriptor - sim_emax number of words needed for examine - sim_devices array of pointers to simulated devices - sim_stop_messages array of pointers to stop messages -*/ - -char sim_name[] = "Intel MDS-800"; - -REG *sim_PC = &i8080_reg[0]; - -int32 sim_emax = 4; - -DEVICE *sim_devices[] = { - &i8080_dev, - &EPROM_dev, - &RAM_dev, - &i8251_dev, - &i8255_dev, - &multibus_dev, - &isbc064_dev, - &isbc208_dev, - NULL -}; - -const char *sim_stop_messages[] = { - "Unknown error", - "Unknown I/O Instruction", - "HALT instruction", - "Breakpoint", - "Invalid Opcode", - "Invalid Memory", - "XACK Error" -}; - diff --git a/MDS-800/MDS-800/system_defs.h b/MDS-800/MDS-800/system_defs.h deleted file mode 100644 index 4892355c..00000000 --- a/MDS-800/MDS-800/system_defs.h +++ /dev/null @@ -1,84 +0,0 @@ -/* system_defs.h: Intel iSBC simulator definitions - - Copyright (c) 2010, William A. Beech - - Permission is hereby granted, free of charge, to any person obtaining a - copy of this software and associated documentation files (the "Software"), - to deal in the Software without restriction, including without limitation - the rights to use, copy, modify, merge, publish, distribute, sublicense, - and/or sell copies of the Software, and to permit persons to whom the - Software is furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be included in - all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - William A. Beech BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - - Except as contained in this notice, the name of William A. Beech shall not be - used in advertising or otherwise to promote the sale, use or other dealings - in this Software without prior written authorization from William A. Beech. - - ?? ??? 10 - Original file. - 16 Dec 12 - Modified to use isbc_80_10.cfg file to set base and size. - 08 Apr 15 - Modified to use mds-800.cfg file to set base and size. - Changed tabs to spaces - -*/ - -#include -#include -#include "mds-800.cfg" /* Intel System 80/10 configuration */ -#include "sim_defs.h" /* simulator defns */ - -/* multibus interrupt definitions */ - -#define INT_0 0x01 -#define INT_1 0x02 -#define INT_2 0x04 -#define INT_3 0x08 -#define INT_4 0x10 -#define INT_5 0x20 -#define INT_6 0x40 -#define INT_7 0x80 - -/* CPU interrupts definitions */ - -#define INT_R 0x200 -#define I75 0x40 -#define I65 0x20 -#define I55 0x10 - -/* Memory */ - -#define MAXMEMSIZE 0x10000 /* 8080 max memory size */ -#define MEMSIZE (i8080_unit.capac) /* 8080 actual memory size */ -#define ADDRMASK (MAXMEMSIZE - 1) /* 8080 address mask */ -#define MEM_ADDR_OK(x) (((uint32) (x)) < MEMSIZE) - -/* debug definitions */ - -#define DEBUG_flow 0x0001 -#define DEBUG_read 0x0002 -#define DEBUG_write 0x0004 -#define DEBUG_level1 0x0008 -#define DEBUG_level2 0x0010 -#define DEBUG_reg 0x0020 -#define DEBUG_asm 0x0040 -#define DEBUG_xack 0x0080 -#define DEBUG_all 0xFFFF - -/* Simulator stop codes */ - -#define STOP_RSRV 1 /* must be 1 */ -#define STOP_HALT 2 /* HALT */ -#define STOP_IBKPT 3 /* breakpoint */ -#define STOP_OPCODE 4 /* Invalid Opcode */ -#define STOP_IO 5 /* I/O error */ -#define STOP_MEM 6 /* Memory error */ -#define STOP_XACK 7 /* XACK error */ - diff --git a/MDS-800/System_80-10/System_80-10.txt b/MDS-800/System_80-10/System_80-10.txt deleted file mode 100644 index e63bdd6e..00000000 --- a/MDS-800/System_80-10/System_80-10.txt +++ /dev/null @@ -1,211 +0,0 @@ -Altair 8800 Simulator -===================== - -1. Background. - - The MITS (Micro Instrumentation and Telemetry Systems) Altair 8800 -was announced on the January 1975 cover of Popular Electronics, which -boasted you could buy and build this powerful computer kit for only $397. -The kit consisted at that time of only the parts to build a case, power -supply, card cage (18 slots), CPU card, and memory card with 256 *bytes* of -memory. Still, thousands were ordered within the first few months after the -announcement, starting the personal computer revolution as we know it today. - - Many laugh at the small size of the that first kit, noting there -were no peripherals and the 256 byte memory size. But the computer was an -open system, and by 1977 MITS and many other small startups had added many -expansion cards to make the Altair quite a respectable little computer. The -"Altair Bus" that made this possible was soon called the S-100 Bus, later -adopted as an industry standard, and eventually became the IEE-696 Bus. - -2. Hardware - - We are simulating a fairly "loaded" Altair 8800 from about 1977, -with the following configuration: - - device simulates - name(s) - - CPU Altair 8800 with Intel 8080 CPU board, 62KB - of RAM, 2K of EPROM with start boot ROM. - 2SIO MITS 88-2SIO Dual Serial Interface Board. Port 1 - is assumed to be connected to a serial "glass - TTY" that is your terminal running the Simulator. - PTR Paper Tape Reader attached to port 2 of the - 2SIO board. - PTP Paper Tape Punch attached to port 2 of the - 2SIO board. This also doubles as a printer - port. - DSK MITS 88-DISK Floppy Disk controller with up - to eight drives. - -2.1 CPU - - We have 2 CPU options that were not present on the original -machine but are useful in the simulator. We also allow you to select -memory sizes, but be aware that some sample software requires the full -64K (i.e. CP/M) and the MITS Disk Basic and Altair DOS require about -a minimum of 24K. - - SET CPU 8080 Simulates the 8080 CPU (normal) - SET CPU Z80 Simulates the later Z80 CPU [At the present time - this is not fully implemented and is not to be - trusted with real Z80 software] - SET CPU ITRAP Causes the simulator to halt if an invalid 8080 - Opcode is detected. - SET CPU NOITRAP Does not stop on an invalid Opcode. This is - how the real 8080 works. - SET CPU 4K - SET CPU 8K - SET CPU 12K - SET CPU 16K - ...... - SET CPU 64K All these set various CPU memory configurations. - The 2K EPROM at the high end of memory is always - present and will always boot. - -The BOOT EPROM card starts at address 177400. Jumping to this address -will always boot drive 0 of the floppy controller. If no valid bootable -software is present there the machine crashes. This is historically -accurate behavior. - -The real 8080, on receiving a HLT (Halt) instruction, freezes the processor -and only an interrupt or CPU hardware reset will restore it. The simulator -is alot nicer, it will halt but send you back to the simulator command line. - -CPU Registers include the following: - - name size comments - - PC 16 The Program Counter - A 8 The accumulator - BC 16 The BC register pair. Register B is the high - 8 bits, C is the lower 8 bits - DE 16 The DE register pair. D is the top 8 bits, E is - the bottom. - HL 16 The HL register pair. H is top, L is bottom. - C 1 Carry flag. - Z 1 Zero Flag. - AC 1 Auxillary Carry flag. - P 1 Parity flag. - S 1 Sign flag. - SR 16 The front panel switches. - BREAK 16 Breakpoint address (377777 to disable). - WRU 8 The interrupt character. This starts as 005 - (ctrl-E) but some Altair software uses this - keystroke so best to change this to something - exotic such as 035 (which is Ctl-]). - - -2.2 The Serial I/O Card (2SIO) - - This simple programmed I/O device provides 2 serial ports to the -outside world, which could be hardware jumpered to support RS-232 plugs or a -TTY current loop interface. The standard I/O addresses assigned by MITS -was 20-21 (octal) for the first port, and 22-23 (octal) for the second. -We follow this standard in the Simulator. - - The simulator directs I/O to/from the first port to the screen. The -second port reads from an attachable "tape reader" file on input, and writes -to an attachable "punch file" on output. These files are considered a -simple stream of 8-bit bytes. - -2.3 The 88-DISK controller. - - The MITS 88-DISK is a simple programmed I/O interface to the MITS -8-inch floppy drive, which was basically a Pertec FD-400 with a power -supply and buffer board builtin. The controller supports neither interrupts -nor DMA, so floppy access required the sustained attention of the CPU. -The standard I/O addresses were 10, 11, and 12 (octal), and we follow the -standard. Details on controlling this hardware are in the altair_dsk.c -source file. - - -3. Sample Software - - Running an Altair in 1977 you would be running either MITS Disk -Extended BASIC, or the brand new and sexy CP/M Operating System from Digital -Research. Or possibly, you ordered Altair DOS back when it was promised in -1975, and are still waiting for it to be delivered in early 1977. - - We have samples of all three for you to check out. We can't go into -the details of how they work, but we'll give you a few hints. - - -3.1 CP/M Version 2.2 - - This version is my own port of the standard CP/M to the Altair. -There were some "official" versions but I don't have them. None were -endorsed or sold by MITS to my knowledge, however. - To boot CP/M: - - sim> attach dsk0 altcpm.dsk - sim> go 177400 - 62K CP/M VERSION 2.2 (ALTAIR 8800) - A>DIR - - CP/M feels like DOS, sort of. DIR will work. I have included all -the standard CP/M utilities, plus a few common public-domain ones. I also -include the sources to the customized BIOS and some other small programs. -TYPE will print an ASCII file. DUMP will dump a binary one. LS is a better -DIR than DIR. ASM will assemble .ASM files to Hex, LOAD will "load" them to -binary format (.COM). ED is a simple editor, #A command will bring the -source file to the buffer, T command will "type" lines, L will move lines, -E exits the editor. 20L20T will move down 20 lines, and type 20. Very -DECish. DDT is the debugger, SUBMIT is a batch-type command processor. -A sample batch file that will assemble and write out the bootable CP/M -image (on drive A) is "SYSGEN.SUB". To run it, type "SUBMIT SYSGEN". - - -3.2 MITS Disk Extended BASIC Version 4.1 - - This was the commonly used software for serious users of the Altair -computer. It is a powerful (but slow) BASIC with some extended commands to -allow it to access and manage the disk. There was no operating system it -ran under. To boot: - - sim> attach dsk0 mbasic.dsk - sim> go 177400 - - MEMORY SIZE? [return] - LINEPRINTER? C [return] - HIGHEST DISK NUMBER? 0 [return] (3 here = 4 drive system) - NUMBER OF FILES? 3 [return] - NUMBER OF RANDOM FILES? 2 [return] - - 44297 BYTES FREE - ALTAIR BASIC REV. 4.1 - [DISK EXTENDED VERSION] - COPYRIGHT 1977 BY MITS INC. - OK - mount 0 - OK - files - - -3.3 Altair DOS Version 1.0 - - This was long promised but not delivered until it was almost -irrelevant. A short attempted tour will reveal it to be a dog, far inferior -to CP/M. To boot: - - sim> attach dsk0 altdos.dsk - sim> go 177400 - - MEMORY SIZE? 64 [return] - INTERRUPTS? N [return] - HIGHEST DISK NUMBER? 0 [return] (3 here = 4 drive system) - HOW MANY DISK FILES? 3 [return] - HOW MANY RANDOM FILES? 2 [return] - - 056769 BYTES AVAILABLE - DOS MONITOR VER 1.0 - COPYRIGHT 1977 BY MITS INC - .mnt 0 - - .dir 0 - - - - - diff --git a/MDS-800/System_80-10/functional description.vsd b/MDS-800/System_80-10/functional description.vsd deleted file mode 100644 index a6fd1978..00000000 Binary files a/MDS-800/System_80-10/functional description.vsd and /dev/null differ diff --git a/MDS-800/common/i8251.c b/MDS-800/common/i8251.c deleted file mode 100644 index b1092b37..00000000 --- a/MDS-800/common/i8251.c +++ /dev/null @@ -1,252 +0,0 @@ -/* i8251.c: Intel i8251 UART adapter - - Copyright (c) 2010, William A. Beech - - Permission is hereby granted, free of charge, to any person obtaining a - copy of this software and associated documentation files (the "Software"), - to deal in the Software without restriction, including without limitation - the rights to use, copy, modify, merge, publish, distribute, sublicense, - and/or sell copies of the Software, and to permit persons to whom the - Software is furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be included in - all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - WILLIAM A. BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - - Except as contained in this notice, the name of William A. Beech shall not be - used in advertising or otherwise to promote the sale, use or other dealings - in this Software without prior written authorization from William A. Beech. - - These functions support a simulated i8251 interface device on an iSBC. - The device had one physical I/O port which could be connected - to any serial I/O device that would connect to a current loop, - RS232, or TTY interface. Available baud rates were jumper - selectable for each port from 110 to 9600. - - All I/O is via programmed I/O. The i8251 has a status port - and a data port. - - The simulated device does not support synchronous mode. The simulated device - supports a select from I/O space and one address line. The data port is at the - lower address and the status/command port is at the higher. - - A write to the status port can select some options for the device: - - Asynchronous Mode Instruction - 7 6 5 4 3 2 1 0 - +---+---+---+---+---+---+---+---+ - | S2 S1 EP PEN L2 L1 B2 B1| - +---+---+---+---+---+---+---+---+ - - Baud Rate Factor - B2 0 1 0 1 - B1 0 0 1 1 - sync 1X 16X 64X - mode - - Character Length - L2 0 1 0 1 - L1 0 0 1 1 - 5 6 7 8 - bits bits bits bits - - EP - A 1 in this bit position selects even parity. - PEN - A 1 in this bit position enables parity. - - Number of Stop Bits - S2 0 1 0 1 - S1 0 0 1 1 - invalid 1 1.5 2 - bit bits bits - - Command Instruction Format - 7 6 5 4 3 2 1 0 - +---+---+---+---+---+---+---+---+ - | EH IR RTS ER SBRK RxE DTR TxE| - +---+---+---+---+---+---+---+---+ - - TxE - A 1 in this bit position enables transmit. - DTR - A 1 in this bit position forces *DTR to zero. - RxE - A 1 in this bit position enables receive. - SBRK - A 1 in this bit position forces TxD to zero. - ER - A 1 in this bit position resets the error bits - RTS - A 1 in this bit position forces *RTS to zero. - IR - A 1 in this bit position returns the 8251 to Mode Instruction Format. - EH - A 1 in this bit position enables search for sync characters. - - A read of the status port gets the port status: - - Status Read Format - 7 6 5 4 3 2 1 0 - +---+---+---+---+---+---+---+---+ - |DSR SD FE OE PE TxE RxR TxR| - +---+---+---+---+---+---+---+---+ - - TxR - A 1 in this bit position signals transmit ready to receive a character. - RxR - A 1 in this bit position signals receiver has a character. - TxE - A 1 in this bit position signals transmitter has no more characters to transmit. - PE - A 1 in this bit signals a parity error. - OE - A 1 in this bit signals an transmit overrun error. - FE - A 1 in this bit signals a framing error. - SD - A 1 in this bit position returns the 8251 to Mode Instruction Format. - DSR - A 1 in this bit position signals *DSR is at zero. - - A read from the data port gets the typed character, a write - to the data port writes the character to the device. - - ?? ??? 10 - Original file. - 16 Dec 12 - Modified to use isbc_80_10.cfg file to set base and size. -*/ - -#include "system_defs.h" - -#define UNIT_V_ANSI (UNIT_V_UF + 0) /* ANSI mode */ -#define UNIT_ANSI (1 << UNIT_V_ANSI) - -#define TXR 0x01 -#define RXR 0x02 -#define TXE 0x04 -#define SD 0x40 - -extern int32 reg_dev(int32 (*routine)(), int32 port); - -/* function prototypes */ - -t_stat i8251_svc (UNIT *uptr); -t_stat i8251_reset (DEVICE *dptr, int32 base); -int32 i8251s(int32 io, int32 data); -int32 i8251d(int32 io, int32 data); -void i8251_reset1(void); -/* i8251 Standard I/O Data Structures */ - -UNIT i8251_unit = { - UDATA (&i8251_svc, 0, 0), KBD_POLL_WAIT -}; - -REG i8251_reg[] = { - { HRDATA (DATA, i8251_unit.buf, 8) }, - { HRDATA (STAT, i8251_unit.u3, 8) }, - { HRDATA (MODE, i8251_unit.u4, 8) }, - { HRDATA (CMD, i8251_unit.u5, 8) }, - { NULL } -}; - -MTAB i8251_mod[] = { - { UNIT_ANSI, 0, "TTY", "TTY", NULL }, - { UNIT_ANSI, UNIT_ANSI, "ANSI", "ANSI", NULL }, - { 0 } -}; - -DEVICE i8251_dev = { - "8251", //name - &i8251_unit, //units - i8251_reg, //registers - i8251_mod, //modifiers - 1, //numunits - 10, //aradix - 31, //awidth - 1, //aincr - 16, //dradix - 8, //dwidth - NULL, //examine - NULL, //deposit -// &i8251_reset, //reset - NULL, //reset - NULL, //boot - NULL, //attach - NULL, //detach - NULL, //ctxt - 0, //flags - 0, //dctrl - NULL, //debflags - NULL, //msize - NULL //lname -}; - -/* Service routines to handle simulator functions */ - -/* i8251_svc - actually gets char & places in buffer */ - -t_stat i8251_svc (UNIT *uptr) -{ - int32 temp; - - sim_activate (&i8251_unit, i8251_unit.wait); /* continue poll */ - if ((temp = sim_poll_kbd ()) < SCPE_KFLAG) - return temp; /* no char or error? */ - i8251_unit.buf = temp & 0xFF; /* Save char */ - i8251_unit.u3 |= RXR; /* Set status */ - - /* Do any special character handling here */ - - i8251_unit.pos++; - return SCPE_OK; -} - -/* Reset routine */ - -t_stat i8251_reset (DEVICE *dptr, int32 base) -{ - reg_dev(i8251d, base); - reg_dev(i8251s, base + 1); - reg_dev(i8251d, base + 2); - reg_dev(i8251s, base + 3); - i8251_reset1(); - printf(" 8251: Registered at %02X\n", base); - sim_activate (&i8251_unit, i8251_unit.wait); /* activate unit */ - return SCPE_OK; -} - -/* I/O instruction handlers, called from the CPU module when an - IN or OUT instruction is issued. -*/ - -int32 i8251s(int32 io, int32 data) -{ -// printf("\nio=%d data=%04X\n", io, data); - if (io == 0) { /* read status port */ - return i8251_unit.u3; - } else { /* write status port */ - if (i8251_unit.u6) { /* if mode, set cmd */ - i8251_unit.u5 = data; - printf("8251: Command Instruction=%02X\n", data); - if (data & SD) /* reset port! */ - i8251_reset1(); - } else { /* set mode */ - i8251_unit.u4 = data; - printf("8251: Mode Instruction=%02X\n", data); - i8251_unit.u6 = 1; /* set cmd received */ - } - return (0); - } -} - -int32 i8251d(int32 io, int32 data) -{ - if (io == 0) { /* read data port */ - i8251_unit.u3 &= ~RXR; - return (i8251_unit.buf); - } else { /* write data port */ - sim_putchar(data); - } - return 0; -} - -void i8251_reset1(void) -{ - i8251_unit.u3 = TXR + TXE; /* status */ - i8251_unit.u4 = 0; /* mode instruction */ - i8251_unit.u5 = 0; /* command instruction */ - i8251_unit.u6 = 0; - i8251_unit.buf = 0; - i8251_unit.pos = 0; - printf(" 8251: Reset\n"); -} - -/* end of i8251.c */ diff --git a/MDS-800/common/isbc208.c b/MDS-800/common/isbc208.c deleted file mode 100644 index 349820bc..00000000 --- a/MDS-800/common/isbc208.c +++ /dev/null @@ -1,1699 +0,0 @@ -/* isbc208.c: Intel iSBC208 Floppy Disk adapter - - Copyright (c) 2011, William A. Beech - - Permission is hereby granted, free of charge, to any person obtaining a - copy of this software and associated documentation files (the "Software"), - to deal in the Software without restriction, including without limitation - the rights to use, copy, modify, merge, publish, distribute, sublicense, - and/or sell copies of the Software, and to permit persons to whom the - Software is furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be included in - all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - WILLIAM A. BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - - Except as contained in this notice, the name of William A. Beech shall not be - used in advertising or otherwise to promote the sale, use or other dealings - in this Software without prior written authorization from William A. Beech. - - These functions support a simulated iSBC208 interface to 4 each 8-, 5 1/4-, or - 3 1/2-inch floppy disk drives. Commands are setup with programmed I/O to the - simulated ports of an i8237 DMA controller and an i8272 FDC. Data transfer - to/from the simulated disks is performed directly with the multibus memory. - - The iSBC-208 can be configured for 8- or 16-bit addresses. It defaults to 8-bit - addresses for the 8080/8085 processors. It can be configured for I/O port - addresses with 3-bits (8-bit address) or 11-bits (16-bit address). Default is - 3-bits set to 0. This defines the port offset to be used to determine the actual - port address. Bus priority can be configured for parallel or serial mode. Default is - serial. The multibus interface interrupt can be configured for interrupt 0-7. - Default is none. Since all channel registers in the i8237 are 16-bit, transfers - are done as two 8-bit operations, low- then high-byte. - - Port addressing is as follows (Port offset = 0): - - Port Mode Command Function - - 00 Write Load DMAC Channel 0 Base and Current Address Regsiters - Read Read DMAC Channel 0 Current Address Register - 01 Write Load DMAC Channel 0 Base and Current Word Count Registers - Read Read DMAC Channel 0 Current Word Count Register - 04 Write Load DMAC Channel 2 Base and Current Address Regsiters - Read Read DMAC Channel 2 Current Address Register - 05 Write Load DMAC Channel 2 Base and Current Word Count Registers - Read Read DMAC Channel 2 Current Word Count Register - 06 Write Load DMAC Channel 3 Base and Current Address Regsiters - Read Read DMAC Channel 3 Current Address Register - 07 Write Load DMAC Channel 3 Base and Current Word Count Registers - Read Read DMAC Channel 3 Current Word Count Register - 08 Write Load DMAC Command Register - Read Read DMAC Status Register - 09 Write Load DMAC Request Register - OA Write Set/Reset DMAC Mask Register - OB Write Load DMAC Mode Register - OC Write Clear DMAC First/Last Flip-Flop - 0D Write DMAC Master Clear - OF Write Load DMAC Mask Register - 10 Read Read FDC Status Register - 11 Write Load FDC Data Register - Read Read FDC Data Register - 12 Write Load Controller Auxiliary Port - Read Poll Interrupt Status - 13 Write Controller Reset - 14 Write Load Controller Low-Byte Segment Address Register - 15 Write Load Controller High-Byte Segment Address Register - 20-2F Read/Write Reserved for iSBX Multimodule Board - - Register usage is defined in the following paragraphs. - - Read/Write DMAC Address Registers - - Used to simultaneously load a channel's current-address register and base-address - register with the memory address of the first byte to be transferred. (The Channel - 0 current/base address register must be loaded prior to initiating a diskette read - or write operation.) Since each channel's address registers are 16 bits in length - (64K address range), two "write address register" commands must be executed in - order to load the complete current/base address registers for any channel. - - Read/Write DMAC Word Count Registers - - The Write DMAC Word Count Register command is used to simultaneously load a - channel's current and base word-count registers with the number of bytes - to be transferred during a subsequent DMA operation. Since the word-count - registers are 16-bits in length, two commands must be executed to load both - halves of the registers. - - Write DMAC Command Register - - The Write DMAC Command Register command loads an 8-bit byte into the - DMAC's command register to define the operating characteristics of the - DMAC. The functions of the individual bits in the command register are - defined in the following diagram. Note that only two bits within the - register are applicable to the controller; the remaining bits select - functions that are not supported and, accordingly, must always be set - to zero. - - 7 6 5 4 3 2 1 0 - +---+---+---+---+---+---+---+---+ - | 0 0 0 0 0 0 | - +---+---+---+---+---+---+---+---+ - | | - | +---------- 0 CONTROLLER ENABLE - | 1 CONTROLLER DISABLE - | - +------------------ 0 FIXED PRIORITY - 1 ROTATING PRIORITY - - Read DMAC Status Register Command - - The Read DMAC Status Register command accesses an 8-bit status byte that - identifies the DMA channels that have reached terminal count or that - have a pending DMA request. - - 7 6 5 4 3 2 1 0 - +---+---+---+---+---+---+---+---+ - | 0 0 | - +---+---+---+---+---+---+---+---+ - | | | | | | - | | | | | +-- CHANNEL 0 TC - | | | | +---------- CHANNEL 2 TC - | | | +-------------- CHANNEL 3 TC - | | +------------------ CHANNEL 0 DMA REQUEST - | +-------------------------- CHANNEL 2 DMA REQUEST - +------------------------------ CHANNEL 3 DMA REQUEST - - Write DMAC Request Register - - The data byte associated with the Write DMAC Request Register command - sets or resets a channel's associated request bit within the DMAC's - internal 4-bit request register. - - 7 6 5 4 3 2 1 0 - +---+---+---+---+---+---+---+---+ - | X X X X X | - +---+---+---+---+---+---+---+---+ - | | | - | +---+-- 00 SELECT CHANNEL 0 - | 01 SELECT CHANNEL 1 - | 10 SELECT CHANNEL 2 - | 11 SELECT CHANNEL 3 - | - +---------- 0 RESET REQUEST BIT - 1 SET REQUEST BIT - - Set/Reset DMAC Mask Register - - Prior to a DREQ-initiated DMA transfer, the channel's mask bit must - be reset to enable recognition of the DREQ input. When the transfer - is complete (terminal count reached or external EOP applied) and - the channel is not programmed to autoinitialize, the channel's - mask bit is automatically set (disabling DREQ) and must be reset - prior to a subsequent DMA transfer. All four bits of the mask - register are set (disabling the DREQ inputs) by a DMAC master - clear or controller reset. Additionally, all four bits can be - set/reset by a single Write DMAC Mask Register command. - - - 7 6 5 4 3 2 1 0 - +---+---+---+---+---+---+---+---+ - | X X X X X | - +---+---+---+---+---+---+---+---+ - | | | - | +---+-- 00 SELECT CHANNEL 0 - | 01 SELECT CHANNEL 1 - | 10 SELECT CHANNEL 2 - | 11 SELECT CHANNEL 3 - | - +---------- 0 RESET REQUEST BIT - 1 SET REQUEST BIT - - Write DMAC Mode Register - - The Write DMAC Mode Register command is used to define the - operating mode characteristics for each DMA channel. Each - channel has an internal 6-bit mode register; the high-order - six bits of the associated data byte are written into the - mode register addressed by the two low-order bits. - - - 7 6 5 4 3 2 1 0 - +---+---+---+---+---+---+---+---+ - | | - +---+---+---+---+---+---+---+---+ - | | | | | | | | - | | | | | | +---+-- 00 SELECT CHANNEL 0 - | | | | | | 01 SELECT CHANNEL 1 - | | | | | | 10 SELECT CHANNEL 2 - | | | | | | 11 SELECT CHANNEL 3 - | | | | | | - | | | | +---+---------- 00 VERIFY TRANSFER - | | | | 01 WRITE TRANSFER - | | | | 10 READ TRANSFER - | | | | - | | | +------------------ 0 AUTOINITIALIZE DISABLE - | | | 1 AUTOINITIALIZE ENABLE - | | | - | | +---------------------- 0 ADDRESS INCREMENT - | | 1 ADDRESS DECREMENT - | | - +---+-------------------------- 00 DEMAND MODE - 01 SINGLE MODE - 10 BLOCK MODE - - Clear DMAC First/Last Flip-Flop - - The Clear DMAC First/Last Flip-Flop command initializes - the DMAC's internal first/last flip-flop so that the - next byte written to or re~d from the 16-bit address - or word-count registers is the low-order byte. The - flip-flop is toggled with each register access so that - a second register read or write command accesses the - high-order byte. - - DMAC Master Clear - - The DMAC Master Clear command clears the DMAC's command, status, - request, and temporary registers to zero, initializes the - first/last flip-flop, and sets the four channel mask bits in - the mask register to disable all DMA requests (i.e., the DMAC - is placed in an idle state). - - Write DMAC Mask Register - - The Write DMAC Mask Register command allows all four bits of the - DMAC's mask register to be written with a single command. - - 7 6 5 4 3 2 1 0 - +---+---+---+---+---+---+---+---+ - | X X X X X | - +---+---+---+---+---+---+---+---+ - | | | - | | +-- 0 CLEAR CHANNEL 0 MASK BIT - | | 1 SET CHANNEL 0 MASK BIT - | | - | +---------- 0 CLEAR CHANNEL 2 MASK BIT - | 1 SET CHANNEL 2 MASK BIT - | - +-------------- 0 CLEAR CHANNEL 3 MASK BIT - 1 SET CHANNEL 3 MASK BIT - - Read FDC Status Register - - The Read FDC Status Register command accesses the FDC's main - status register. The individual status register bits are as - follows: - - 7 6 5 4 3 2 1 0 - +---+---+---+---+---+---+---+---+ - | | - +---+---+---+---+---+---+---+---+ - | | | | | | | | - | | | | | | | +-- FDD 0 BUSY - | | | | | | +------ FDD 1 BUSY - | | | | | +---------- FDD 2 BUSY - | | | | +-------------- FDD 3 BUSY - | | | +------------------ FDC BUSY - | | +---------------------- NON-DMA MODE - | +-------------------------- DATA INPUT/OUTPUT - +------------------------------ REQUEST FOR MASTER - - Read/Write FDC Data Register - - The Read and Write FDC Data Register commands are used to write - command and parameter bytes to the FDC in order to specify the - operation to be performed (referred to as the "command phase") - and to read status bytes from the FDC following the operation - (referred to as the "result phase"). During the command and - result phases, the 8-bit data register is actually a series of - 8-bit registers in a stack. Each register is accessed in - sequence; the number of registers accessed and the individual - register contents are defined by the specific disk command. - - Write Controller Auxiliary Port - - The Write Controller Auxiliary Port command is used to set or - clear individual bits within the controller's auxiliary port. - The four low-order port bits are dedicated to auxiliary drive - control functions (jumper links are required to connect the - desired port bit to an available pin on the drive interface - connectors). The most common application for these bits is - the "Motor-On" control function for mini-sized drives. - - 7 6 5 4 3 2 1 0 - +---+---+---+---+---+---+---+---+ - | | - +---+---+---+---+---+---+---+---+ - | | | | | | | | - | | | | +---+---+---+-- DRIVE CONTROL - | | | +------------------ ADDR 20 - | | +---------------------- ADDR 21 - | +-------------------------- ADDR 22 - +------------------------------ ADDR 23 - - Poll Interrupt Status - - The Poll Interrupt Status command presents the interrupt - status of the controller and the two interrupt status - lines dedicated to the iSBX Multimodule board. - 7 6 5 4 3 2 1 0 - +---+---+---+---+---+---+---+---+ - | X X X X X | - +---+---+---+---+---+---+---+---+ - | | | - | | +-- CONTROLLER INTERRUPT - | +------ MULTIMODULE BOARD INTERRUPT 0 - +---------- MULTIMODULE BOARD INTERRUPT 1 - - Controller Reset - - The Controller Reset command is the software reset for the - controller. This command clears the controller's auxiliary - port and segment address register, provides a reset signal - to the iSBX Multimodule board and initializes the bus - controller (releases the bus), the DMAC (clears the internal - registers and masks the DREQ inputs), and the FDC (places - the FDC in an idle state and disables the output control - lines to the diskette drive). - - Write Controller Low- And High-Byte Segment Address Registers - - The Write Controller Low- and High-Byte Address Registers - commands are required when the controller uses 20-bit - addressing (memory address range from 0 to OFFFFFH). These - commands are issued prior to initiating a diskette read or - write operation to specify the 16-bit segment address. - - FDC Commands - - The 8272/D765 is capable of performing 15 different - commands. Each command is initiated by a multibyte transfer - from the processor, and the result after execution of the - command may also be a multibyte transfer back to the processor. - Because of this multibyte interchange of information between - the FDC and the processor, it is convenient to consider each - command as consisting of three phases: - - Command Phase: The FDC receives all information required to - perform a particular operation from the processor. - - Execution Phase: The FDC performs the operation it was - instructed to do. - - Result Phase: After completion of the operation, status - and other housekeeping information are made available - to the processor. - - Not all the FDC commands are supported by this emulation. Only the subset - of commands required to build an operable CP/M BIOS are supported. They are: - - Read - Read specified data from the selected FDD. - - Write - Write specified data to the selected FDD. - - Seek - Move the R/W head to the specified cylinder on the specified FDD. - - Specify - Set the characteristics for all the FDDs. - - Sense Interrupt - Sense change in FDD Ready line or and of Seek/Recalibrate - command. - - Sense Drive - Returns status of all the FDDs. - - Recalibrate - Move the R/W head to cylinder 0 on the specified FDD. - - Format Track - Format the current track on the specified FDD. - - Read ID - Reads the first address mark it finds. - - Simulated Floppy Disk Drives - - The units in this device simulate an 8- or 5 1/4- or 3 1/2 inch drives. The - drives can emulate SSSD, SSDD, and DSDD. Drives can be attached to files up - to 1.44MB in size. Drive configuration is selected when a disk is logged onto - the system. An identity sector or identity byte contains information to - configure the OS drivers for the type of drive to emulate. - - uptr->u3 - - uptr->u4 - - uptr->u5 - - uptr->u6 - unit number (0-FDD_NUM) - - ?? ??? 11 - Original file. - 16 Dec 12 - Modified to use system_80_10.cfg file to set I/O base address. -*/ - -#include "system_defs.h" - -#define UNIT_V_WPMODE (UNIT_V_UF) /* Write protect */ -#define UNIT_WPMODE (1 << UNIT_V_WPMODE) - -/* master status register definitions */ -#define RQM 0x80 /* Request for master */ -#define DIO 0x40 /* Data I/O Direction 0=W, 1=R */ -#define NDM 0x20 /* Non-DMA mode */ -#define CB 0x10 /* FDC busy */ -#define D3B 0x08 /* FDD 3 busy */` -#define D2B 0x04 /* FDD 2 busy */` -#define D1B 0x02 /* FDD 1 busy */` -#define D0B 0x01 /* FDD 0 busy */` - -/* status register 0 definitions */ -#define IC 0xC0 /* Interrupt code */ -#define IC_NORM 0x00 /* normal completion */ -#define IC_ABNORM 0x40 /* abnormal completion */ -#define IC_INVC 0x80 /* invalid command */ -#define IC_RC 0xC0 /* drive not ready */ -#define SE 0x20 /* Seek end */ -#define EC 0x10 /* Equipment check */ -#define NR 0x08 /* Not ready */ -#define HD 0x04 /* Head selected */ -#define US 0x03 /* Unit selected */ -#define US_0 0x00 /* Unit 0 */ -#define US_1 0x01 /* Unit 1 */ -#define US_2 0x02 /* Unit 2 */ -#define US_3 0x03 /* Unit 3 */ - -/* status register 1 definitions */ -#define EN 0x80 /* End of cylinder */ -#define DE 0x20 /* Data error */ -#define OR 0x10 /* Overrun */ -#define ND 0x04 /* No data */ -#define NW 0x02 /* Not writable */ -#define MA 0x01 /* Missing address mark */ - -/* status register 2 definitions */ -#define CM 0x40 /* Control mark */ -#define DD 0x20 /* Data error in data field */ -#define WC 0x10 /* Wrong cylinder */ -#define BC 0x02 /* Bad cylinder */ -#define MD 0x01 /* Missing address mark in data field */ - -/* status register 3/fddst definitions */ -#define FT 0x80 /* Fault */ -#define WP 0x40 /* Write protect */ -#define RDY 0x20 /* Ready */ -#define T0 0x10 /* Track 0 */ -#define TS 0x08 /* Two sided */ -//#define HD 0x04 /* Head selected */ -//#define US 0x03 /* Unit selected */ - -/* FDC command definitions */ -#define READTRK 0x02 -#define SPEC 0x03 -#define SENDRV 0x04 -#define WRITE 0x05 -#define READ 0x06 -#define HOME 0x07 -#define SENINT 0x08 -#define WRITEDEL 0x09 -#define READID 0x0A -#define READDEL 0x0C -#define FMTTRK 0x0D -#define SEEK 0x0F -#define SCANEQ 0x11 -#define SCANLOEQ 0x19 -#define SCANHIEQ 0x1D - -#define FDD_NUM 4 - -/* internal function prototypes */ - -t_stat isbc208_svc (UNIT *uptr); -t_stat isbc208_reset (DEVICE *dptr); -void isbc208_reset1 (void); -t_stat isbc208_attach (UNIT *uptr, char *cptr); -t_stat isbc208_set_mode (UNIT *uptr, int32 val, char *cptr, void *desc); -int32 isbc208_r0(int32 io, int32 data); -int32 isbc208_r1(int32 io, int32 data); -int32 isbc208_r2(int32 io, int32 data); -int32 isbc208_r3(int32 io, int32 data); -int32 isbc208_r4(int32 io, int32 data); -int32 isbc208_r5(int32 io, int32 data); -int32 isbc208_r6(int32 io, int32 data); -int32 isbc208_r7(int32 io, int32 data); -int32 isbc208_r8(int32 io, int32 data); -int32 isbc208_r9(int32 io, int32 data); -int32 isbc208_rA(int32 io, int32 data); -int32 isbc208_rB(int32 io, int32 data); -int32 isbc208_rC(int32 io, int32 data); -int32 isbc208_rD(int32 io, int32 data); -int32 isbc208_rE(int32 io, int32 data); -int32 isbc208_rF(int32 io, int32 data); -int32 isbc208_r10(int32 io, int32 data); -int32 isbc208_r11(int32 io, int32 data); -int32 isbc208_r12(int32 io, int32 data); -int32 isbc208_r13(int32 io, int32 data); -int32 isbc208_r14(int32 io, int32 data); -int32 isbc208_r15(int32 io, int32 data); - -/* external function prototypes */ - -extern void set_irq(int32 int_num); -extern void clr_irq(int32 int_num); -extern int32 reg_dev(int32 (*routine)(), int32 port); -extern void multibus_put_mbyte(int32 addr, int32 val); -extern int32 multibus_get_mbyte(int32 addr); - -/* 8237 physical register definitions */ -uint16 i8237_r0; // 8237 ch 0 address register -uint16 i8237_r1; // 8237 ch 0 count register -uint16 i8237_r2; // 8237 ch 1 address register -uint16 i8237_r3; // 8237 ch 1 count register -uint16 i8237_r4; // 8237 ch 2 address register -uint16 i8237_r5; // 8237 ch 2 count register -uint16 i8237_r6; // 8237 ch 3 address register -uint16 i8237_r7; // 8237 ch 3 count register -uint8 i8237_r8; // 8237 status register -uint8 i8237_r9; // 8237 command register -uint8 i8237_rA; // 8237 mode register -uint8 i8237_rB; // 8237 mask register -uint8 i8237_rC; // 8237 request register -uint8 i8237_rD; // 8237 first/last ff - -/* 8272 physical register definitions */ -/* 8272 command register stack*/ -uint8 i8272_w0; // MT+MFM+SK+command -uint8 i8272_w1; // HDS [HDS=H << 2] + DS1 + DS0 -uint8 i8272_w2; // cylinder # (0-XX) -uint8 i8272_w3; // head # (0 or 1) -uint8 i8272_w4; // sector # (1-XX) -uint8 i8272_w5; // number of bytes (128 << N) -uint8 i8272_w6; // End of track (last sector # on cylinder) -uint8 i8272_w7; // Gap length -uint8 i8272_w8; // Data length (when N=0, size to read or write) - -/* 8272 status register stack */ -uint8 i8272_msr; // main status -uint8 i8272_r0; // ST 0 -uint8 i8272_r1; // ST 1 -uint8 i8272_r2; // ST 2 -uint8 i8272_r3; // ST 3 - -/* iSBC-208 physical register definitions */ -uint16 isbc208_sr; // isbc-208 segment register -uint8 isbc208_i; // iSBC-208 interrupt register -uint8 isbc208_a; // iSBC-208 auxillary port register - -/* data obtained from analyzing command registers/attached file length */ -int32 wsp = 0, rsp = 0; // indexes to write and read stacks (8272 data) -int32 cyl; // current cylinder -int32 hed; // current head [ h << 2] -int32 h; // current head -int32 sec; // current sector -int32 drv; // current drive -uint8 cmd, pcmd; // current command -int32 secn; // N 0-128, 1-256, etc -int32 spt; // sectors per track -int32 ssize; // sector size (128 << N) - -uint8 *isbc208_buf[FDD_NUM] = { /* FDD buffer pointers */ - NULL, - NULL, - NULL, - NULL -}; - -int32 fddst[FDD_NUM] = { // in ST3 format - 0, // status of FDD 0 - 0, // status of FDD 1 - 0, // status of FDD 2 - 0 // status of FDD 3 -}; - -int8 maxcyl[FDD_NUM] = { - 0, // last cylinder + 1 of FDD 0 - 0, // last cylinder + 1 of FDD 1 - 0, // last cylinder + 1 of FDD 2 - 0 // last cylinder + 1 of FDD 3 -}; - -/* isbc208 Standard SIMH Device Data Structures - 4 units */ -UNIT isbc208_unit[] = { - { UDATA (&isbc208_svc, UNIT_ATTABLE+UNIT_DISABLE, 0), 20 }, - { UDATA (&isbc208_svc, UNIT_ATTABLE+UNIT_DISABLE, 0), 20 }, - { UDATA (&isbc208_svc, UNIT_ATTABLE+UNIT_DISABLE, 0), 20 }, - { UDATA (&isbc208_svc, UNIT_ATTABLE+UNIT_DISABLE, 0), 20 } -}; - -REG isbc208_reg[] = { - { HRDATA (CH0ADR, i8237_r0, 16) }, - { HRDATA (CH0CNT, i8237_r1, 16) }, - { HRDATA (CH1ADR, i8237_r2, 16) }, - { HRDATA (CH1CNT, i8237_r3, 16) }, - { HRDATA (CH2ADR, i8237_r4, 16) }, - { HRDATA (CH2CNT, i8237_r5, 16) }, - { HRDATA (CH3ADR, i8237_r6, 16) }, - { HRDATA (CH3CNT, i8237_r7, 16) }, - { HRDATA (STAT37, i8237_r8, 8) }, - { HRDATA (CMD37, i8237_r9, 8) }, - { HRDATA (MODE, i8237_rA, 8) }, - { HRDATA (MASK, i8237_rB, 8) }, - { HRDATA (REQ, i8237_rC, 8) }, - { HRDATA (FF, i8237_rD, 8) }, - { HRDATA (STAT72, i8272_msr, 8) }, - { HRDATA (STAT720, i8272_r0, 8) }, - { HRDATA (STAT721, i8272_r1, 8) }, - { HRDATA (STAT722, i8272_r2, 8) }, - { HRDATA (STAT723, i8272_r3, 8) }, - { HRDATA (CMD720, i8272_w0, 8) }, - { HRDATA (CMD721, i8272_w1, 8) }, - { HRDATA (CMD722, i8272_w2, 8) }, - { HRDATA (CMD723, i8272_w3, 8) }, - { HRDATA (CMD724, i8272_w4, 8) }, - { HRDATA (CMD725, i8272_w5, 8) }, - { HRDATA (CMD726, i8272_w6, 8) }, - { HRDATA (CMD727, i8272_w7, 8) }, - { HRDATA (CMD728, i8272_w8, 8) }, - { HRDATA (FDD0, fddst[0], 8) }, - { HRDATA (FDD1, fddst[1], 8) }, - { HRDATA (FDD2, fddst[2], 8) }, - { HRDATA (FDD3, fddst[3], 8) }, - { HRDATA (SEGREG, isbc208_sr, 8) }, - { HRDATA (AUX, isbc208_a, 8) }, - { HRDATA (INT, isbc208_i, 8) }, - { NULL } -}; - -MTAB isbc208_mod[] = { - { UNIT_WPMODE, 0, "RW", "RW", &isbc208_set_mode }, - { UNIT_WPMODE, UNIT_WPMODE, "WP", "WP", &isbc208_set_mode }, - { 0 } -}; - -DEBTAB isbc208_debug[] = { - { "ALL", DEBUG_all }, - { "FLOW", DEBUG_flow }, - { "READ", DEBUG_read }, - { "WRITE", DEBUG_write }, - { "LEV1", DEBUG_level1 }, - { "LEV2", DEBUG_level2 }, - { "REG", DEBUG_reg }, - { NULL } -}; - -DEVICE isbc208_dev = { - "SBC208", //name - isbc208_unit, //units - isbc208_reg, //registers - isbc208_mod, //modifiers - FDD_NUM, //numunits - 16, //aradix - 32, //awidth - 1, //aincr - 16, //dradix - 8, //dwidth - NULL, //examine - NULL, //deposit - &isbc208_reset, //deposit - NULL, //boot - &isbc208_attach, //attach - NULL, //detach - NULL, //ctxt - DEV_DEBUG+DEV_DISABLE+DEV_DIS, //flags - 0, //dctrl -// DEBUG_flow + DEBUG_read + DEBUG_write, //dctrl - isbc208_debug, //debflags - NULL, //msize - NULL //lname -}; - -/* Service routines to handle simulator functions */ - -/* service routine - actually does the simulated disk I/O */ - -t_stat isbc208_svc (UNIT *uptr) -{ - int32 i, imgadr, data; - int c; - int32 bpt, bpc; - FILE *fp; - - if ((i8272_msr & CB) && cmd && (uptr->u6 == drv)) { /* execution phase */ - if (isbc208_dev.dctrl & DEBUG_flow) - printf("isbc208_svc: Entered execution phase\n"); - switch (cmd) { - case READ: /* 0x06 */ -// printf("READ-e: fddst=%02X", fddst[uptr->u6]); - h = i8272_w3; // h = 0 or 1 - hed = i8272_w3 << 2; // hed = 0 or 4 [h << 2] - sec = i8272_w4; // sector number (1-XX) - secn = i8272_w5; // N (0-5) - spt = i8272_w6; // sectors/track - ssize = 128 << secn; // size of sector (bytes) - bpt = ssize * spt; // bytes/track - bpc = bpt * 2; // bytes/cylinder -// printf(" d=%d h=%d c=%d s=%d\n", drv, h, cyl, sec); - if (isbc208_dev.dctrl & DEBUG_flow) { - printf("isbc208_svc: FDC read: h=%d, hed=%d, sec=%d, secn=%d, spt=%d, ssize=%04X, bpt=%04X, bpc=%04X\n", - h, hed, sec, secn, spt, ssize, bpt, bpc); - printf("isbc208_svc: FDC read: d=%d h=%d c=%d s=%d N=%d spt=%d fddst=%02X\n", - drv, h, cyl, sec, secn, spt, fddst[uptr->u6]); - printf("\nFDC read of d=%d h=%d c=%d s=%d", - drv, h, cyl, sec); - } - if ((fddst[uptr->u6] & RDY) == 0) { // drive not ready - i8272_r0 = IC_ABNORM + NR + hed + drv; /* command done - Not ready error*/ - i8272_r3 = fddst[uptr->u6]; - i8272_msr |= (RQM + DIO + CB); /* enter result phase */ - if (isbc208_dev.dctrl & DEBUG_flow) - printf("isbc208_svc: FDC read: Not Ready\n"); - } else { // get image addr for this d, h, c, s - imgadr = (cyl * bpc) + (h * bpt) + ((sec - 1) * ssize); - if (isbc208_dev.dctrl & DEBUG_flow) - printf("isbc208_svc: FDC read: DMA addr=%04X cnt=%04X imgadr=%04X\n", - i8237_r0, i8237_r1, imgadr); - for (i=0; i<=i8237_r1; i++) { /* copy selected sector to memory */ - data = *(isbc208_buf[uptr->u6] + (imgadr + i)); - multibus_put_mbyte(i8237_r0 + i, data); - } -//*** need to step return results IAW table 3-11 in 143078-001 - i8272_w4 = ++sec; /* next sector */ - i8272_r0 = hed + drv; /* command done - no error */ - i8272_r3 = fddst[uptr->u6]; - } - i8272_r1 = 0; - i8272_r2 = 0; - i8272_w2 = cyl; /* generate a current address mark */ - i8272_w3 = h; - if (i8272_w4 > i8272_w6) { // beyond last sector of track? - i8272_w4 = 1; // yes, set to sector 1; - if (h) { // on head one? - i8272_w2++; // yes, step cylinder - h = 0; // back to head 0 - } - } - i8272_w5 = secn; - i8272_msr |= (RQM + DIO + CB); /* enter result phase */ - rsp = wsp = 0; /* reset indexes */ - set_irq(SBC208_INT); /* set interrupt */ -// printf("READ-x: fddst=%02X\n", fddst[uptr->u6]); - break; - case WRITE: /* 0x05 */ -// printf("WRITE-e: fddst=%02X\n", fddst[uptr->u6]); - h = i8272_w3; // h = 0 or 1 - hed = i8272_w3 << 2; // hed = 0 or 4 [h << 2] - sec = i8272_w4; // sector number (1-XX) - secn = i8272_w5; // N (0-5) - spt = i8272_w6; // sectors/track - ssize = 128 << secn; // size of sector (bytes) - bpt = ssize * spt; // bytes/track - bpc = bpt * 2; // bytes/cylinder - if (isbc208_dev.dctrl & DEBUG_flow) - printf("isbc208_svc: FDC write: hed=%d, sec=%d, secn=%d, spt=%d, ssize=%04X, bpt=%04X, bpc=%04X\n", - hed, sec, secn, spt, ssize, bpt, bpc); - if (isbc208_dev.dctrl & DEBUG_flow) - printf("isbc208_svc: FDC write: d=%d h=%d c=%d s=%d N=%d spt=%d fddst=%02X\n", - drv, h, cyl, sec, secn, spt, fddst[uptr->u6]); - i8272_r1 = 0; // clear ST1 - i8272_r2 = 0; // clear ST2 - if ((fddst[uptr->u6] & RDY) == 0) { - i8272_r0 = IC_ABNORM + NR + hed + drv; /* Not ready error*/ - i8272_r3 = fddst[uptr->u6]; - i8272_msr |= (RQM + DIO + CB); /* enter result phase */ - if (isbc208_dev.dctrl & DEBUG_flow) - printf("isbc208_svc: FDC write: Not Ready\n"); -// } else if (fddst[uptr->u6] & WP) { -// i8272_r0 = IC_ABNORM + hed + drv; /* write protect error*/ -// i8272_r1 = NW; // set not writable in ST1 -// i8272_r3 = fddst[uptr->u6] + WP; -// i8272_msr |= (RQM + DIO + CB); /* enter result phase */ -// printf("\nWrite Protected fddst[%d]=%02X\n", uptr->u6, fddst[uptr->u6]); -// if (isbc208_dev.dctrl & DEBUG_flow) -// printf("isbc208_svc: FDC write: Write Protected\n"); - } else { // get image addr for this d, h, c, s - imgadr = (cyl * bpc) + (h * bpt) + ((sec - 1) * ssize); - if (isbc208_dev.dctrl & DEBUG_flow) - printf("isbc208_svc: FDC write: DMA adr=%04X cnt=%04X imgadr=%04X\n", - i8237_r0, i8237_r1, imgadr); - for (i=0; i<=i8237_r1; i++) { /* copy selected memory to image */ - data = multibus_get_mbyte(i8237_r0 + i); - *(isbc208_buf[uptr->u6] + (imgadr + i)) = data; - } - //*** quick fix. Needs more thought! - fp = fopen(uptr->filename, "wb"); // write out modified image - for (i=0; icapac; i++) { - c = *(isbc208_buf[uptr->u6] + i) & 0xFF; - fputc(c, fp); - } - fclose(fp); -//*** need to step return results IAW table 3-11 in 143078-001 - i8272_w2 = cyl; /* generate a current address mark */ - i8272_w3 = hed >> 2; - i8272_w4 = ++sec; /* next sector */ - i8272_w5 = secn; - i8272_r0 = hed + drv; /* command done - no error */ - i8272_r3 = fddst[uptr->u6]; - i8272_msr |= (RQM + DIO + CB); /* enter result phase */ - } - rsp = wsp = 0; /* reset indexes */ - set_irq(SBC208_INT); /* set interrupt */ -// printf("WRITE-x: fddst=%02X\n", fddst[uptr->u6]); - break; - case FMTTRK: /* 0x0D */ - if ((fddst[uptr->u6] & RDY) == 0) { - i8272_r0 = IC_ABNORM + NR + hed + drv; /* Not ready error*/ - i8272_msr |= (RQM + DIO + CB); /* enter result phase */ - if (isbc208_dev.dctrl & DEBUG_flow) - printf("isbc208_svc: Not Ready\n"); - } else if (fddst[uptr->u6] & WP) { - i8272_r0 = IC_ABNORM + hed + drv; /* write protect error*/ - i8272_r3 = fddst[uptr->u6] + WP; - i8272_msr |= (RQM + DIO + CB); /* enter result phase */ - if (isbc208_dev.dctrl & DEBUG_flow) - printf("isbc208_svc: Write Protected\n"); - } else { - ; /* do nothing for now */ - i8272_msr |= (RQM + DIO + CB); /* enter result phase */ - } - rsp = wsp = 0; /* reset indexes */ - set_irq(SBC208_INT); /* set interrupt */ - break; - case SENINT: /* 0x08 */ - i8272_msr |= (RQM + DIO + CB); /* enter result phase */ - i8272_r0 = hed + drv; /* command done - no error */ - i8272_r1 = 0; - i8272_r2 = 0; - rsp = wsp = 0; /* reset indexes */ - clr_irq(SBC208_INT); /* clear interrupt */ - break; - case SENDRV: /* 0x04 */ - if (isbc208_dev.dctrl & DEBUG_flow) - printf("isbc208_svc: FDC sense drive of disk=%d fddst=%02X\n", drv, fddst[uptr->u6]); - i8272_msr |= (RQM + DIO + CB); /* enter result phase */ - i8272_r0 = hed + drv; /* command done - no error */ - i8272_r1 = 0; - i8272_r2 = 0; - i8272_r3 = fddst[drv]; /* drv status */ - rsp = wsp = 0; /* reset indexes */ - break; - case HOME: /* 0x07 */ -// printf("HOME-e: fddst=%02X\n", fddst[uptr->u6]); - if (isbc208_dev.dctrl & DEBUG_flow) - printf("isbc208_svc: FDC home: disk=%d fddst=%02X\n", drv, fddst[uptr->u6]); - if ((fddst[uptr->u6] & RDY) == 0) { - i8272_r0 = IC_ABNORM + NR + hed + drv; /* Not ready error*/ - i8272_r3 = fddst[uptr->u6]; - if (isbc208_dev.dctrl & DEBUG_flow) - printf("isbc208_svc: Not Ready\n"); - } else { - cyl = 0; /* now on cylinder 0 */ - fddst[drv] |= T0; /* set status flag */ - i8272_r0 = SE + hed + drv; /* seek end - no error */ - } - i8272_r1 = 0; - i8272_r2 = 0; - i8272_msr &= ~(RQM + DIO + CB + hed + drv); /* execution phase done*/ - i8272_msr |= RQM; /* enter COMMAND phase */ - rsp = wsp = 0; /* reset indexes */ - set_irq(SBC208_INT); /* set interrupt */ -// printf("HOME-x: fddst=%02X\n", fddst[uptr->u6]); - break; - case SPEC: /* 0x03 */ - fddst[0] |= TS; //*** bad, bad, bad! - fddst[1] |= TS; - fddst[2] |= TS; - fddst[3] |= TS; -// printf("SPEC-e: fddst[%d]=%02X\n", uptr->u6, fddst[uptr->u6]); - if (isbc208_dev.dctrl & DEBUG_flow) - printf("isbc208_svc: FDC specify SRT=%d ms HUT=%d ms HLT=%d ms \n", - 16 - (drv >> 4), 16 * (drv & 0x0f), i8272_w2 & 0xfe); - i8272_r0 = hed + drv; /* command done - no error */ - i8272_r1 = 0; - i8272_r2 = 0; - i8272_msr &= ~(RQM + DIO + CB); /* execution phase done*/ - i8272_msr = 0; // force 0 for now, where does 0x07 come from? - i8272_msr |= RQM; /* enter command phase */ - rsp = wsp = 0; /* reset indexes */ -// printf("SPEC-x: fddst[%d]=%02X\n", uptr->u6, fddst[uptr->u6]); - break; - case READID: /* 0x0A */ - if ((fddst[uptr->u6] & RDY) == 0) { - i8272_r0 = IC_RC + NR + hed + drv; /* Not ready error*/ - i8272_r3 = fddst[uptr->u6]; - if (isbc208_dev.dctrl & DEBUG_flow) - printf("isbc208_svc: Not Ready\n"); - } else { - i8272_w2 = cyl; /* generate a valid address mark */ - i8272_w3 = hed >> 2; - i8272_w4 = 1; /* always sector 1 */ - i8272_w5 = secn; - i8272_r0 = hed + drv; /* command done - no error */ - i8272_msr &= ~(RQM + DIO + CB); /* execution phase done*/ - i8272_msr |= RQM; /* enter command phase */ - } - i8272_r1 = 0; - i8272_r2 = 0; - rsp = wsp = 0; /* reset indexes */ - break; - case SEEK: /* 0x0F */ -// printf("SEEK-e: fddst=%02X\n", fddst[uptr->u6]); - if (isbc208_dev.dctrl & DEBUG_flow) - printf("isbc208_svc: FDC seek: disk=%d cyl=%d fddst=%02X\n", drv, i8272_w2, fddst[uptr->u6]); - if ((fddst[uptr->u6] & RDY) == 0) { /* Not ready? */ - i8272_r0 = IC_ABNORM + NR + hed + drv; /* error*/ - i8272_r3 = fddst[uptr->u6]; - if (isbc208_dev.dctrl & DEBUG_flow) - printf("isbc208_svc: FDC seek: Not Ready\n"); - } else if (i8272_w2 >= maxcyl[uptr->u6]) { - i8272_r0 = IC_ABNORM + RDY + hed + drv; /* seek error*/ - if (isbc208_dev.dctrl & DEBUG_flow) - printf("isbc208_svc: FDC seek: Invalid Cylinder %d\n", i8272_w2); - } else { - i8272_r0 |= SE + hed + drv; /* command done - no error */ - cyl = i8272_w2; /* new cylinder number */ - if (cyl == 0) { /* if cyl 0, set flag */ - fddst[drv] |= T0; /* set T0 status flag */ - i8272_r3 |= T0; - } else { - fddst[drv] &= ~T0; /* clear T0 status flag */ - i8272_r3 &= ~T0; - } - } - i8272_r1 = 0; - i8272_r2 = 0; - i8272_msr &= ~(RQM + DIO + CB + hed + drv); /* execution phase done*/ - i8272_msr |= RQM; /* enter command phase */ - rsp = wsp = 0; /* reset indexes */ -// set_irq(SBC208_INT); /* set interrupt */ -// printf("SEEK-x: fddst=%02X\n", fddst[uptr->u6]); - break; - default: - i8272_msr &= ~(RQM + DIO + CB); /* execution phase done*/ - i8272_msr |= RQM; /* enter command phase */ - i8272_r0 = IC_INVC + hed + drv; /* set bad command error */ - i8272_r1 = 0; - i8272_r2 = 0; - rsp = wsp = 0; /* reset indexes */ - break; - } - pcmd = cmd; /* save for result phase */ - cmd = 0; /* reset command */ - if (isbc208_dev.dctrl & DEBUG_flow) - printf("isbc208_svc: Exit: RSLT0 msr=%02X ST0=%02X ST1=%02X ST2=%02X ST3=%02X\n", - i8272_msr, i8272_r0, i8272_r1, i8272_r2, i8272_r3); - } - sim_activate (&isbc208_unit[uptr->u6], isbc208_unit[uptr->u6].wait); - return SCPE_OK; -} - -// read/write FDC data register -int32 isbc208_r11(int32 io, int32 data) -{ - if (io == 0) { /* read FDC data register */ - wsp = 0; /* clear write stack index */ - switch (rsp) { /* read from next stack register */ - case 0: - if (isbc208_dev.dctrl & DEBUG_reg) { - printf("i8272_r1 read as %02X\n", i8272_r1); - printf("i8272_r3 read as %02X\n", i8272_r3); - } - rsp++; /* step read stack index */ - clr_irq(SBC208_INT); /* clear interrupt */ - if (pcmd == SENDRV) { - i8272_msr = RQM; /* result phase SENDRV done */ - return i8272_r1; // SENDRV return ST1 - } - return i8272_r0; /* ST0 */ - case 1: - if (isbc208_dev.dctrl & DEBUG_reg) - printf("i8272_r2 read as %02X\n", i8272_r2); - rsp++; /* step read stack index */ - if (pcmd == SENINT) { - i8272_msr = RQM; /* result phase SENINT done */ - return cyl; // SENINT return current cylinder - } - return i8272_r1; /* ST1 */ - case 2: - if (isbc208_dev.dctrl & DEBUG_reg) - printf("i8272_r3 read as %02X\n", i8272_r3); - rsp++; /* step read stack index */ - return i8272_r2; /* ST2 */ - case 3: - if (isbc208_dev.dctrl & DEBUG_reg) - printf("i8272_w2 read as %02X\n", i8272_w2); - rsp++; /* step read stack index */ - return i8272_w2; /* C - cylinder */ - case 4: - if (isbc208_dev.dctrl & DEBUG_reg) - printf("i8272_w3 read as %02X\n", i8272_w3); - rsp++; /* step read stack index */ - return i8272_w3; /* H - head */ - case 5: - if (isbc208_dev.dctrl & DEBUG_reg) - printf("i8272_w4 read as %02X\n", i8272_w4); - rsp++; /* step read stack index */ - return i8272_w4; /* R - sector */ - case 6: - if (isbc208_dev.dctrl & DEBUG_reg) - printf("i8272_w5 read as %02X\n", i8272_w5); - i8272_msr = RQM; /* result phase ALL OTHERS done */ - return i8272_w5; /* N - sector size*/ - } - } else { /* write FDC data register */ - rsp = 0; /* clear read stack index */ - switch (wsp) { /* write to next stack register */ - case 0: - i8272_w0 = data; /* rws = MT + MFM + SK + cmd */ - cmd = data & 0x1F; /* save the current command */ - if (isbc208_dev.dctrl & DEBUG_reg) - printf("i8272_w0 set to %02X\n", data); - if (cmd == SENINT) { - i8272_msr = CB; /* command phase SENINT done */ - return 0; - } - wsp++; /* step write stack index */ - break; - case 1: - i8272_w1 = data; /* rws = hed + drv */ - if (cmd != SPEC) - drv = data & 0x03; - if (isbc208_dev.dctrl & DEBUG_reg) - printf("i8272_w1 set to %02X\n", data); - if (cmd == HOME || cmd == SENDRV || cmd == READID) { - i8272_msr = CB + hed + drv; /* command phase HOME, READID and SENDRV done */ - return 0; - } - wsp++; /* step write stack index */ - break; - case 2: - i8272_w2 = data; /* rws = C */ - if (isbc208_dev.dctrl & DEBUG_reg) - printf("i8272_w2 set to %02X\n", data); - if (cmd == SPEC || cmd == SEEK) { - i8272_msr = CB + hed + drv; /* command phase SPECIFY and SEEK done */ - return 0; - } - wsp++; /* step write stack index */ - break; - case 3: - i8272_w3 = data; /* rw = H */ - hed = data; - wsp++; /* step write stack index */ - if (isbc208_dev.dctrl & DEBUG_reg) - printf("i8272_w3 set to %02X\n", data); - break; - case 4: - i8272_w4 = data; /* rw = R */ - sec = data; - wsp++; /* step write stack index */ - if (isbc208_dev.dctrl & DEBUG_reg) - printf("i8272_w4 set to %02X\n", data); - break; - case 5: - i8272_w5 = data; /* rw = N */ - if (isbc208_dev.dctrl & DEBUG_reg) - printf("i8272_w5 set to %02X\n", data); - if (cmd == FMTTRK) { - i8272_msr = CB + hed + drv; /* command phase FMTTRK done */ - return 0; - } - wsp++; /* step write stack index */ - break; - case 6: - i8272_w6 = data; /* rw = last sector number */ - wsp++; /* step write stack index */ - if (isbc208_dev.dctrl & DEBUG_reg) - printf("i8272_w6 set to %02X\n", data); - break; - case 7: - i8272_w7 = data; /* rw = gap length */ - wsp++; /* step write stack index */ - if (isbc208_dev.dctrl & DEBUG_reg) - printf("i8272_w7 set to %02X\n", data); - break; - case 8: - i8272_w8 = data; /* rw = bytes to transfer */ - if (isbc208_dev.dctrl & DEBUG_reg) - printf("i8272_w8 set to %02X\n", data); - if (cmd == READ || cmd == WRITE) - i8272_msr = CB + hed + drv; /* command phase all others done */ - break; - } - return 0; - } -} - -/* Reset routine */ - -t_stat isbc208_reset (DEVICE *dptr) -{ - reg_dev(isbc208_r0, SBC208_BASE + 0); - reg_dev(isbc208_r1, SBC208_BASE + 1); - reg_dev(isbc208_r2, SBC208_BASE + 2); - reg_dev(isbc208_r3, SBC208_BASE + 3); - reg_dev(isbc208_r4, SBC208_BASE + 4); - reg_dev(isbc208_r5, SBC208_BASE + 5); - reg_dev(isbc208_r6, SBC208_BASE + 6); - reg_dev(isbc208_r7, SBC208_BASE + 7); - reg_dev(isbc208_r8, SBC208_BASE + 8); - reg_dev(isbc208_r9, SBC208_BASE + 9); - reg_dev(isbc208_rA, SBC208_BASE + 10); - reg_dev(isbc208_rB, SBC208_BASE + 11); - reg_dev(isbc208_rC, SBC208_BASE + 12); - reg_dev(isbc208_rD, SBC208_BASE + 13); - reg_dev(isbc208_rE, SBC208_BASE + 14); - reg_dev(isbc208_rF, SBC208_BASE + 15); - reg_dev(isbc208_r10, SBC208_BASE + 16); - reg_dev(isbc208_r11, SBC208_BASE + 17); - reg_dev(isbc208_r12, SBC208_BASE + 18); - reg_dev(isbc208_r13, SBC208_BASE + 19); - reg_dev(isbc208_r14, SBC208_BASE + 20); - reg_dev(isbc208_r15, SBC208_BASE + 21); - if ((isbc208_dev.flags & DEV_DIS) == 0) - isbc208_reset1(); - return SCPE_OK; -} - -void isbc208_reset1 (void) -{ - int32 i; - UNIT *uptr; - static int flag = 1; - - if (flag) printf("iSBC 208: Initializing\n"); - for (i = 0; i < FDD_NUM; i++) { /* handle all units */ - uptr = isbc208_dev.units + i; - if (uptr->capac == 0) { /* if not configured */ -// printf(" SBC208%d: Not configured\n", i); -// if (flag) { -// printf(" ALL: \"set isbc208 en\"\n"); -// printf(" EPROM: \"att isbc2080 \"\n"); -// flag = 0; -// } - uptr->capac = 0; /* initialize unit */ - uptr->u3 = 0; - uptr->u4 = 0; - uptr->u5 = 0; - uptr->u6 = i; /* unit number - only set here! */ - fddst[i] = WP + T0 + i; /* initial drive status */ - uptr->flags |= UNIT_WPMODE; /* set WP in unit flags */ - sim_activate (&isbc208_unit[uptr->u6], isbc208_unit[uptr->u6].wait); - } else { - fddst[i] = RDY + WP + T0 + i; /* initial attach drive status */ -// printf(" SBC208%d: Configured, Attached to %s\n", i, uptr->filename); - } - } - i8237_r8 = 0; /* status */ - i8237_r9 = 0; /* command */ - i8237_rB = 0x0F; /* mask */ - i8237_rC = 0; /* request */ - i8237_rD = 0; /* first/last FF */ - i8272_msr = RQM; /* 8272 ready for start of command */ - rsp = wsp = 0; /* reset indexes */ - cmd = 0; /* clear command */ - if (flag) { - printf(" 8237 Reset\n"); - printf(" 8272 Reset\n"); - } - flag = 0; -} - -/* isbc208 attach - attach an .IMG file to a FDD */ - -t_stat isbc208_attach (UNIT *uptr, char *cptr) -{ - t_stat r; - FILE *fp; - int32 i, c = 0; - long flen; - - if (isbc208_dev.dctrl & DEBUG_flow) - printf(" isbc208_attach: Entered with cptr=%s\n", cptr); - if ((r = attach_unit (uptr, cptr)) != SCPE_OK) { - printf(" isbc208_attach: Attach error\n"); - return r; - } - fp = fopen(uptr->filename, "rb"); - if (fp == NULL) { - printf(" Unable to open disk img file %s\n", uptr->filename); - printf(" No disk image loaded!!!\n"); - } else { - printf("iSBC 208: Attach\n"); - fseek(fp, 0, SEEK_END); /* size disk image */ - flen = ftell(fp); - fseek(fp, 0, SEEK_SET); - if (isbc208_buf[uptr->u6] == NULL) { /* no buffer allocated */ - isbc208_buf[uptr->u6] = malloc(flen); - if (isbc208_buf[uptr->u6] == NULL) { - printf(" iSBC208_attach: Malloc error\n"); - return SCPE_MEM; - } - } - uptr->capac = flen; - i = 0; - c = fgetc(fp); // copy disk image into buffer - while (c != EOF) { - *(isbc208_buf[uptr->u6] + i++) = c & 0xFF; - c = fgetc(fp); - } - fclose(fp); - fddst[uptr->u6] |= RDY; /* set unit ready */ - if (flen == 368640) { /* 5" 360K DSDD */ - maxcyl[uptr->u6] = 40; - fddst[uptr->u6] |= TS; // two sided - } - else if (flen == 737280) { /* 5" 720K DSQD / 3.5" 720K DSDD */ - maxcyl[uptr->u6] = 80; - fddst[uptr->u6] |= TS; // two sided - } - else if (flen == 1228800) { /* 5" 1.2M DSHD */ - maxcyl[uptr->u6] = 80; - fddst[uptr->u6] |= TS; // two sided - } - else if (flen == 1474560) { /* 3.5" 1.44M DSHD */ - maxcyl[uptr->u6] = 80; - fddst[uptr->u6] |= TS; // two sided - } - printf(" Drive-%d: %d bytes of disk image %s loaded, fddst=%02X\n", - uptr->u6, i, uptr->filename, fddst[uptr->u6]); - } - if (isbc208_dev.dctrl & DEBUG_flow) - printf(" iSBC208_attach: Done\n"); - return SCPE_OK; -} - -/* isbc208 set mode = 8- or 16-bit data bus */ - -t_stat isbc208_set_mode (UNIT *uptr, int32 val, char *cptr, void *desc) -{ - UNIT *uptr1; - - if (isbc208_dev.dctrl & DEBUG_flow) - printf(" isbc208_set_mode: Entered with val=%08XH uptr->flags=%08X\n", - val, uptr->flags); - if (val & UNIT_WPMODE) { /* write protect */ - fddst[uptr->u6] |= WP; - uptr->flags |= val; - } else { /* read write */ - fddst[uptr->u6] &= ~WP; - uptr->flags &= ~val; - } -// printf("fddst[%d]=%02XH uptr->flags=%08X\n", uptr->u6, fddst[uptr->u6], uptr->flags); - if (isbc208_dev.dctrl & DEBUG_flow) - printf(" isbc208_set_mode: Done\n"); - return SCPE_OK; -} - -/* I/O instruction handlers, called from the CPU module when an - IN or OUT instruction is issued. - - Each function is passed an 'io' flag, where 0 means a read from - the port, and 1 means a write to the port. On input, the actual - input is passed as the return value, on output, 'data' is written - to the device. -*/ - -int32 isbc208_r0(int32 io, int32 data) -{ - if (io == 0) { /* read current address CH 0 */ - if (i8237_rD) { /* high byte */ - i8237_rD = 0; - if (isbc208_dev.dctrl & DEBUG_reg) - printf("i8237_r0(H) read as %04X\n", i8237_r0); - return (i8237_r0 >> 8); - } else { /* low byte */ - i8237_rD++; - if (isbc208_dev.dctrl & DEBUG_reg) - printf("i8237_r0(L) read as %04X\n", i8237_r0); - return (i8237_r0 & 0xFF); - } - } else { /* write base & current address CH 0 */ - if (i8237_rD) { /* high byte */ - i8237_rD = 0; - i8237_r0 |= (data << 8); - if (isbc208_dev.dctrl & DEBUG_reg) - printf("i8237_r0(H) set to %04X\n", i8237_r0); - } else { /* low byte */ - i8237_rD++; - i8237_r0 = data & 0xFF; - if (isbc208_dev.dctrl & DEBUG_reg) - printf("i8237_r0(L) set to %04X\n", i8237_r0); - } - return 0; - } -} - -int32 isbc208_r1(int32 io, int32 data) -{ - if (io == 0) { /* read current word count CH 0 */ - if (i8237_rD) { /* high byte */ - i8237_rD = 0; - if (isbc208_dev.dctrl & DEBUG_reg) - printf("i8237_r1(H) read as %04X\n", i8237_r1); - return (i8237_r1 >> 8); - } else { /* low byte */ - i8237_rD++; - if (isbc208_dev.dctrl & DEBUG_reg) - printf("i8237_r1(L) read as %04X\n", i8237_r1); - return (i8237_r1 & 0xFF); - } - } else { /* write base & current address CH 0 */ - if (i8237_rD) { /* high byte */ - i8237_rD = 0; - i8237_r1 |= (data << 8); - if (isbc208_dev.dctrl & DEBUG_reg) - printf("i8237_r1(H) set to %04X\n", i8237_r1); - } else { /* low byte */ - i8237_rD++; - i8237_r1 = data & 0xFF; - if (isbc208_dev.dctrl & DEBUG_reg) - printf("i8237_r1(L) set to %04X\n", i8237_r1); - } - return 0; - } -} - -int32 isbc208_r2(int32 io, int32 data) -{ - if (io == 0) { /* read current address CH 1 */ - if (i8237_rD) { /* high byte */ - i8237_rD = 0; - if (isbc208_dev.dctrl & DEBUG_reg) - printf("i8237_r2(H) read as %04X\n", i8237_r2); - return (i8237_r2 >> 8); - } else { /* low byte */ - i8237_rD++; - if (isbc208_dev.dctrl & DEBUG_reg) - printf("i8237_r2(L) read as %04X\n", i8237_r2); - return (i8237_r2 & 0xFF); - } - } else { /* write base & current address CH 1 */ - if (i8237_rD) { /* high byte */ - i8237_rD = 0; - i8237_r2 |= (data << 8); - if (isbc208_dev.dctrl & DEBUG_reg) - printf("i8237_r2(H) set to %04X\n", i8237_r2); - } else { /* low byte */ - i8237_rD++; - i8237_r2 = data & 0xFF; - if (isbc208_dev.dctrl & DEBUG_reg) - printf("i8237_r2(L) set to %04X\n", i8237_r2); - } - return 0; - } -} - -int32 isbc208_r3(int32 io, int32 data) -{ - if (io == 0) { /* read current word count CH 1 */ - if (i8237_rD) { /* high byte */ - i8237_rD = 0; - if (isbc208_dev.dctrl & DEBUG_reg) - printf("i8237_r3(H) read as %04X\n", i8237_r3); - return (i8237_r3 >> 8); - } else { /* low byte */ - i8237_rD++; - if (isbc208_dev.dctrl & DEBUG_reg) - printf("i8237_r3(L) read as %04X\n", i8237_r3); - return (i8237_r3 & 0xFF); - } - } else { /* write base & current address CH 1 */ - if (i8237_rD) { /* high byte */ - i8237_rD = 0; - i8237_r3 |= (data << 8); - if (isbc208_dev.dctrl & DEBUG_reg) - printf("i8237_r3(H) set to %04X\n", i8237_r3); - } else { /* low byte */ - i8237_rD++; - i8237_r3 = data & 0xFF; - if (isbc208_dev.dctrl & DEBUG_reg) - printf("i8237_r3(L) set to %04X\n", i8237_r3); - } - return 0; - } -} - -int32 isbc208_r4(int32 io, int32 data) -{ - if (io == 0) { /* read current address CH 2 */ - if (i8237_rD) { /* high byte */ - i8237_rD = 0; - if (isbc208_dev.dctrl & DEBUG_reg) - printf("i8237_r4(H) read as %04X\n", i8237_r4); - return (i8237_r4 >> 8); - } else { /* low byte */ - i8237_rD++; - if (isbc208_dev.dctrl & DEBUG_reg) - printf("i8237_r4(L) read as %04X\n", i8237_r4); - return (i8237_r4 & 0xFF); - } - } else { /* write base & current address CH 2 */ - if (i8237_rD) { /* high byte */ - i8237_rD = 0; - i8237_r4 |= (data << 8); - if (isbc208_dev.dctrl & DEBUG_reg) - printf("i8237_r4(H) set to %04X\n", i8237_r4); - } else { /* low byte */ - i8237_rD++; - i8237_r4 = data & 0xFF; - if (isbc208_dev.dctrl & DEBUG_reg) - printf("i8237_r4(L) set to %04X\n", i8237_r4); - } - return 0; - } -} - -int32 isbc208_r5(int32 io, int32 data) -{ - if (io == 0) { /* read current word count CH 2 */ - if (i8237_rD) { /* high byte */ - i8237_rD = 0; - if (isbc208_dev.dctrl & DEBUG_reg) - printf("i8237_r5(H) read as %04X\n", i8237_r5); - return (i8237_r5 >> 8); - } else { /* low byte */ - i8237_rD++; - if (isbc208_dev.dctrl & DEBUG_reg) - printf("i8237_r5(L) read as %04X\n", i8237_r5); - return (i8237_r5 & 0xFF); - } - } else { /* write base & current address CH 2 */ - if (i8237_rD) { /* high byte */ - i8237_rD = 0; - i8237_r5 |= (data << 8); - if (isbc208_dev.dctrl & DEBUG_reg) - printf("i8237_r5(H) set to %04X\n", i8237_r5); - } else { /* low byte */ - i8237_rD++; - i8237_r5 = data & 0xFF; - if (isbc208_dev.dctrl & DEBUG_reg) - printf("i8237_r5(L) set to %04X\n", i8237_r5); - } - return 0; - } -} - -int32 isbc208_r6(int32 io, int32 data) -{ - if (io == 0) { /* read current address CH 3 */ - if (i8237_rD) { /* high byte */ - i8237_rD = 0; - if (isbc208_dev.dctrl & DEBUG_reg) - printf("i8237_r6(H) read as %04X\n", i8237_r6); - return (i8237_r6 >> 8); - } else { /* low byte */ - i8237_rD++; - if (isbc208_dev.dctrl & DEBUG_reg) - printf("i8237_r6(L) read as %04X\n", i8237_r6); - return (i8237_r6 & 0xFF); - } - } else { /* write base & current address CH 3 */ - if (i8237_rD) { /* high byte */ - i8237_rD = 0; - i8237_r6 |= (data << 8); - if (isbc208_dev.dctrl & DEBUG_reg) - printf("i8237_r6(H) set to %04X\n", i8237_r6); - } else { /* low byte */ - i8237_rD++; - i8237_r6 = data & 0xFF; - if (isbc208_dev.dctrl & DEBUG_reg) - printf("i8237_r6(L) set to %04X\n", i8237_r6); - } - return 0; - } -} - -int32 isbc208_r7(int32 io, int32 data) -{ - if (io == 0) { /* read current word count CH 3 */ - if (i8237_rD) { /* high byte */ - i8237_rD = 0; - if (isbc208_dev.dctrl & DEBUG_reg) - printf("i8237_r7(H) read as %04X\n", i8237_r7); - return (i8237_r7 >> 8); - } else { /* low byte */ - i8237_rD++; - if (isbc208_dev.dctrl & DEBUG_reg) - printf("i8237_r7(L) read as %04X\n", i8237_r7); - return (i8237_r7 & 0xFF); - } - } else { /* write base & current address CH 3 */ - if (i8237_rD) { /* high byte */ - i8237_rD = 0; - i8237_r7 |= (data << 8); - if (isbc208_dev.dctrl & DEBUG_reg) - printf("i8237_r7(H) set to %04X\n", i8237_r7); - } else { /* low byte */ - i8237_rD++; - i8237_r7 = data & 0xFF; - if (isbc208_dev.dctrl & DEBUG_reg) - printf("i8237_r7(L) set to %04X\n", i8237_r7); - } - return 0; - } -} - -int32 isbc208_r8(int32 io, int32 data) -{ - if (io == 0) { /* read status register */ - if (isbc208_dev.dctrl & DEBUG_reg) - printf("i8237_r8 (status) read as %02X\n", i8237_r8); - return (i8237_r8); - } else { /* write command register */ - i8237_r9 = data & 0xFF; - if (isbc208_dev.dctrl & DEBUG_reg) - printf("i8237_r9 (command) set to %02X\n", i8237_r9); - return 0; - } -} - -int32 isbc208_r9(int32 io, int32 data) -{ - if (io == 0) { - if (isbc208_dev.dctrl & DEBUG_reg) - printf("Illegal read of isbc208_r9\n"); - return 0; - } else { /* write request register */ - i8237_rC = data & 0xFF; - if (isbc208_dev.dctrl & DEBUG_reg) - printf("i8237_rC (request) set to %02X\n", i8237_rC); - return 0; - } -} - -int32 isbc208_rA(int32 io, int32 data) -{ - if (io == 0) { - if (isbc208_dev.dctrl & DEBUG_reg) - printf("Illegal read of isbc208_rA\n"); - return 0; - } else { /* write single mask register */ - switch(data & 0x03) { - case 0: - if (data & 0x04) - i8237_rB |= 1; - else - i8237_rB &= ~1; - break; - case 1: - if (data & 0x04) - i8237_rB |= 2; - else - i8237_rB &= ~2; - break; - case 2: - if (data & 0x04) - i8237_rB |= 4; - else - i8237_rB &= ~4; - break; - case 3: - if (data & 0x04) - i8237_rB |= 8; - else - i8237_rB &= ~8; - break; - } - if (isbc208_dev.dctrl & DEBUG_reg) - printf("i8237_rB (mask) set to %02X\n", i8237_rB); - return 0; - } -} - -int32 isbc208_rB(int32 io, int32 data) -{ - if (io == 0) { - if (isbc208_dev.dctrl & DEBUG_reg) - printf("Illegal read of isbc208_rB\n"); - return 0; - } else { /* write mode register */ - i8237_rA = data & 0xFF; - if (isbc208_dev.dctrl & DEBUG_reg) - printf("i8237_rA (mode) set to %02X\n", i8237_rA); - return 0; - } -} - -int32 isbc208_rC(int32 io, int32 data) -{ - if (io == 0) { - if (isbc208_dev.dctrl & DEBUG_reg) - printf("Illegal read of isbc208_rC\n"); - return 0; - } else { /* clear byte pointer FF */ - i8237_rD = 0; - if (isbc208_dev.dctrl & DEBUG_reg) - printf("i8237_rD (FF) cleared\n"); - return 0; - } -} - -int32 isbc208_rD(int32 io, int32 data) -{ - if (io == 0) { /* read temporary register */ - if (isbc208_dev.dctrl & DEBUG_reg) - printf("Illegal read of isbc208_rD\n"); - return 0; - } else { /* master clear */ - isbc208_reset1(); - if (isbc208_dev.dctrl & DEBUG_reg) - printf("i8237 master clear\n"); - return 0; - } -} - -int32 isbc208_rE(int32 io, int32 data) -{ - if (io == 0) { - if (isbc208_dev.dctrl & DEBUG_reg) - printf("Illegal read of isbc208_rE\n"); - return 0; - } else { /* clear mask register */ - i8237_rB = 0; - if (isbc208_dev.dctrl & DEBUG_reg) - printf("i8237_rB (mask) cleared\n"); - return 0; - } -} - -int32 isbc208_rF(int32 io, int32 data) -{ - if (io == 0) { - if (isbc208_dev.dctrl & DEBUG_reg) - printf("Illegal read of isbc208_rF\n"); - return 0; - } else { /* write all mask register bits */ - i8237_rB = data & 0x0F; - if (isbc208_dev.dctrl & DEBUG_reg) - printf("i8237_rB (mask) set to %02X\n", i8237_rB); - return 0; - } -} - -int32 isbc208_r10(int32 io, int32 data) -{ - if (io == 0) { /* read FDC status register */ - if (isbc208_dev.dctrl & DEBUG_reg) - printf("i8272_msr read as %02X\n", i8272_msr); - return i8272_msr; - } else { - if (isbc208_dev.dctrl & DEBUG_reg) - printf("Illegal write to isbc208_r10\n"); - return 0; - } -} - -int32 isbc208_r12(int32 io, int32 data) -{ - if (io == 0) { /* read interrupt status */ - if (isbc208_dev.dctrl & DEBUG_reg) - printf("isbc208_r12 read as %02X\n", isbc208_i); - return (isbc208_i); - } else { /* write controller auxillary port */ - isbc208_a = data & 0xFF; - if (isbc208_dev.dctrl & DEBUG_reg) - printf("isbc208_r12 set to %02X\n", isbc208_a); - return 0; - } -} - -int32 isbc208_r13(int32 io, int32 data) -{ - if (io == 0) { - if (isbc208_dev.dctrl & DEBUG_reg) - printf("Illegal read of isbc208_r13\n"); - return 0; - } else { /* reset controller */ - isbc208_reset1(); - if (isbc208_dev.dctrl & DEBUG_reg) - printf("isbc208_r13 controller reset\n"); - return 0; - } -} - -int32 isbc208_r14(int32 io, int32 data) -{ - if (io == 0) { - if (isbc208_dev.dctrl & DEBUG_reg) - printf("Illegal read of isbc208_r14\n"); - return 0; - } else { /* Low-Byte Segment Address Register */ - isbc208_sr = data & 0xFF; - if (isbc208_dev.dctrl & DEBUG_reg) - printf("isbc208_sr(L) set to %02X\n", data & 0xFF); - return 0; - } -} - -int32 isbc208_r15(int32 io, int32 data) -{ - if (io == 0) { - if (isbc208_dev.dctrl & DEBUG_reg) - printf("Illegal read of isbc208_r15\n"); - return 0; - } else { /* High-Byte Segment Address Register */ - isbc208_sr |= data << 8; - if (isbc208_dev.dctrl & DEBUG_reg) - printf("isbc208_sr(H) set to %02X\n", data); - return 0; - } -} - -/* end of isbc208.c */ diff --git a/MDS-800/makefile b/MDS-800/makefile deleted file mode 100644 index 4e65edcd..00000000 --- a/MDS-800/makefile +++ /dev/null @@ -1,1382 +0,0 @@ -# -# This GNU make makefile has been tested on: -# Linux (x86 & Sparc & PPC) -# OS X -# Solaris (x86 & Sparc) (gcc and Sun C) -# OpenBSD -# NetBSD -# FreeBSD -# HP-UX -# AIX -# Windows (MinGW & cygwin) -# Linux x86 targeting Android (using agcc script) -# -# Android targeted builds should invoke GNU make with GCC=agcc on -# the command line. -# -# In general, the logic below will detect and build with the available -# features which the host build environment provides. -# -# Dynamic loading of libpcap is the preferred default behavior if pcap.h -# is available at build time. Support to statically linking against libpcap -# is deprecated and may be removed in the future. Static linking against -# libpcap can be enabled if GNU make is invoked with USE_NETWORK=1 on the -# command line. -# -# Some platforms may not have vendor supplied libpcap available. HP-UX is -# one such example. The packages which are available for this platform -# install include files and libraries in user specified directories. In -# order for this makefile to locate where these components may have been -# installed, gmake should be invoked with LPATH=/usr/lib:/usr/local/lib -# defined (adjusted as needed depending on where they may be installed). -# -# The default build will build compiler optimized binaries. -# If debugging is desired, then GNU make can be invoked with -# DEBUG=1 on the command line. -# -# OSX and other environments may have the LLVM (clang) compiler -# installed. If you want to build with the clang compiler, invoke -# make with GCC=clang. -# -# Internal ROM support can be disabled if GNU make is invoked with -# DONT_USE_ROMS=1 on the command line. -# -# Asynchronous I/O support can be disabled if GNU make is invoked with -# NOASYNCH=1 on the command line. -# -# For linting (or other code analyzers) make may be invoked similar to: -# -# make GCC=cppcheck CC_OUTSPEC= LDFLAGS= CFLAGS_G="--enable=all --template=gcc" CC_STD=--std=c99 -# -# CC Command (and platform available options). (Poor man's autoconf) -# -ifeq (old,$(shell gmake --version /dev/null 2>&1 | grep 'GNU Make' | awk '{ if ($$3 < "3.81") {print "old"} }')) - GMAKE_VERSION = $(shell gmake --version /dev/null 2>&1 | grep 'GNU Make' | awk '{ print $$3 }') - $(warning *** Warning *** GNU Make Version $(GMAKE_VERSION) is too old to) - $(warning *** Warning *** fully process this makefile) -endif -# building the pdp11, or any vax simulator could use networking support -BUILD_SINGLE := $(MAKECMDGOALS) $(BLANK_SUFFIX) -ifneq (,$(or $(findstring pdp11,$(MAKECMDGOALS)),$(findstring vax,$(MAKECMDGOALS)),$(findstring all,$(MAKECMDGOALS)))) - NETWORK_USEFUL = true - ifneq (,$(or $(findstring microvax1,$(MAKECMDGOALS)),$(findstring microvax2,$(MAKECMDGOALS)))) - VIDEO_USEFUL = true - endif - ifneq (,$(findstring all,$(MAKECMDGOALS))$(word 2,$(MAKECMDGOALS))) - BUILD_MULTIPLE = s - VIDEO_USEFUL = true - endif -else - ifeq ($(MAKECMDGOALS),) - # default target is all - NETWORK_USEFUL = true - VIDEO_USEFUL = true - BUILD_MULTIPLE = s - BUILD_SINGLE := all $(BUILD_SINGLE) - endif -endif -ifeq ($(WIN32),) #*nix Environments (&& cygwin) - ifeq ($(GCC),) - GCC = gcc - endif - OSTYPE = $(shell uname) - # OSNAME is used in messages to indicate the source of libpcap components - OSNAME = $(OSTYPE) - ifeq (SunOS,$(OSTYPE)) - TEST = /bin/test - else - TEST = test - endif - ifeq (CYGWIN,$(findstring CYGWIN,$(OSTYPE))) # uname returns CYGWIN_NT-n.n-ver - OSTYPE = cygwin - OSNAME = windows-build - endif - ifeq (,$(shell $(GCC) -v /dev/null 2>&1 | grep 'clang')) - GCC_VERSION = $(shell $(GCC) -v /dev/null 2>&1 | grep 'gcc version' | awk '{ print $$3 }') - COMPILER_NAME = GCC Version: $(GCC_VERSION) - ifeq (,$(GCC_VERSION)) - ifeq (SunOS,$(OSTYPE)) - ifneq (,$(shell $(GCC) -V 2>&1 | grep 'Sun C')) - SUNC_VERSION = $(shell $(GCC) -V 2>&1 | grep 'Sun C') - COMPILER_NAME = $(wordlist 2,10,$(SUNC_VERSION)) - endif - endif - ifeq (HP-UX,$(OSTYPE)) - ifneq (,$(shell what `which $(firstword $(GCC)) 2>&1`| grep -i compiler)) - COMPILER_NAME = $(strip $(shell what `which $(firstword $(GCC)) 2>&1` | grep -i compiler)) - endif - endif - endif - else - ifeq (Apple,$(shell $(GCC) -v /dev/null 2>&1 | grep 'Apple' | awk '{ print $$1 }')) - COMPILER_NAME = $(shell $(GCC) -v /dev/null 2>&1 | grep 'Apple' | awk '{ print $$1 " " $$2 " " $$3 " " $$4 }') - CLANG_VERSION = $(word 4,$(COMPILER_NAME)) - else - COMPILER_NAME = $(shell $(GCC) -v /dev/null 2>&1 | grep 'clang version' | awk '{ print $$1 " " $$2 " " $$3 }') - CLANG_VERSION = $(word 3,$(COMPILER_NAME)) - ifeq (,$(findstring .,$(CLANG_VERSION))) - COMPILER_NAME = $(shell $(GCC) -v /dev/null 2>&1 | grep 'clang version' | awk '{ print $$1 " " $$2 " " $$3 " " $$4 }') - CLANG_VERSION = $(word 4,$(COMPILER_NAME)) - endif - endif - endif - ifeq (git-repo,$(shell if $(TEST) -d ./.git; then echo git-repo; fi)) - ifeq (need-hooks,$(shell if $(TEST) ! -e ./.git/hooks/post-checkout; then echo need-hooks; fi)) - $(info *** Installing git hooks in local repository ***) - GIT_HOOKS += $(shell /bin/cp './Visual Studio Projects/git-hooks/post-commit' ./.git/hooks/) - GIT_HOOKS += $(shell /bin/cp './Visual Studio Projects/git-hooks/post-checkout' ./.git/hooks/) - GIT_HOOKS += $(shell /bin/cp './Visual Studio Projects/git-hooks/post-merge' ./.git/hooks/) - GIT_HOOKS += $(shell ./.git/hooks/post-checkout) - ifneq (,$(strip $(GIT_HOOKS))) - $(info *** Warning - Error installing git hooks *** $(GIT_HOOKS)) - endif - endif - endif - LTO_EXCLUDE_VERSIONS = - PCAPLIB = pcap - ifeq (agcc,$(findstring agcc,$(GCC))) # Android target build? - OS_CCDEFS = -D_GNU_SOURCE - ifeq (,$(NOASYNCH)) - OS_CCDEFS += -DSIM_ASYNCH_IO - endif - OS_LDFLAGS = -lm - else # Non-Android Builds - INCPATH:=/usr/include - LIBPATH:=/usr/lib - OS_CCDEFS = -D_GNU_SOURCE - GCC_OPTIMIZERS_CMD = $(GCC) -v --help 2>&1 - GCC_WARNINGS_CMD = $(GCC) -v --help 2>&1 - LD_ELF = $(shell echo | $(GCC) -E -dM - | grep __ELF__) - ifeq (Darwin,$(OSTYPE)) - OSNAME = OSX - LIBEXT = dylib - INCPATH:=$(shell $(GCC) -x c -v -E /dev/null 2>&1 | grep -A 10 '> search starts here' | grep '^ ' | grep -v 'framework directory' | tr -d '\n') - ifeq (incopt,$(shell if $(TEST) -d /opt/local/include; then echo incopt; fi)) - INCPATH += /opt/local/include - OS_CCDEFS += -I/opt/local/include - endif - ifeq (libopt,$(shell if $(TEST) -d /opt/local/lib; then echo libopt; fi)) - LIBPATH += /opt/local/lib - OS_LDFLAGS += -L/opt/local/lib - endif - ifeq (libXt,$(shell if $(TEST) -d /usr/X11/lib; then echo libXt; fi)) - LIBPATH += /usr/X11/lib - OS_LDFLAGS += -L/usr/X11/lib - endif - else - ifeq (Linux,$(OSTYPE)) - LIBPATH := $(sort $(foreach lib,$(shell /sbin/ldconfig -p | grep ' => /' | sed 's/^.* => //'),$(dir $(lib)))) - LIBEXT = so - else - ifeq (SunOS,$(OSTYPE)) - OSNAME = Solaris - LIBPATH := $(shell crle | grep 'Default Library Path' | awk '{ print $$5 }' | sed 's/:/ /g') - LIBEXT = so - OS_LDFLAGS += -lsocket -lnsl - ifeq (incsfw,$(shell if $(TEST) -d /opt/sfw/include; then echo incsfw; fi)) - INCPATH += /opt/sfw/include - OS_CCDEFS += -I/opt/sfw/include - endif - ifeq (libsfw,$(shell if $(TEST) -d /opt/sfw/lib; then echo libsfw; fi)) - LIBPATH += /opt/sfw/lib - OS_LDFLAGS += -L/opt/sfw/lib -R/opt/sfw/lib - endif - OS_CCDEFS += -D_LARGEFILE_SOURCE - else - ifeq (cygwin,$(OSTYPE)) - # use 0readme_ethernet.txt documented Windows pcap build components - INCPATH += ../windows-build/winpcap/WpdPack/include - LIBPATH += ../windows-build/winpcap/WpdPack/lib - PCAPLIB = wpcap - LIBEXT = a - else - ifneq (,$(findstring AIX,$(OSTYPE))) - OS_LDFLAGS += -lm -lrt - ifeq (incopt,$(shell if $(TEST) -d /opt/freeware/include; then echo incopt; fi)) - INCPATH += /opt/freeware/include - OS_CCDEFS += -I/opt/freeware/include - endif - ifeq (libopt,$(shell if $(TEST) -d /opt/freeware/lib; then echo libopt; fi)) - LIBPATH += /opt/freeware/lib - OS_LDFLAGS += -L/opt/freeware/lib - endif - else - ifeq (,$(findstring NetBSD,$(OSTYPE))) - ifneq (no ldconfig,$(findstring no ldconfig,$(shell which ldconfig 2>&1))) - LDSEARCH :=$(shell ldconfig -r | grep 'search directories' | awk '{print $$3}' | sed 's/:/ /g') - endif - ifneq (,$(LDSEARCH)) - LIBPATH := $(LDSEARCH) - else - ifeq (,$(strip $(LPATH))) - $(info *** Warning ***) - $(info *** Warning *** The library search path on your $(OSTYPE) platform can't be) - $(info *** Warning *** determined. This should be resolved before you can expect) - $(info *** Warning *** to have fully working simulators.) - $(info *** Warning ***) - $(info *** Warning *** You can specify your library paths via the LPATH environment) - $(info *** Warning *** variable.) - $(info *** Warning ***) - else - LIBPATH = $(subst :, ,$(LPATH)) - OS_LDFLAGS += $(patsubst %,-L%,$(LIBPATH)) - endif - endif - endif - endif - ifeq (usrpkglib,$(shell if $(TEST) -d /usr/pkg/lib; then echo usrpkglib; fi)) - LIBPATH += /usr/pkg/lib - INCPATH += /usr/pkg/include - OS_LDFLAGS += -L/usr/pkg/lib -R/usr/pkg/lib - endif - ifeq (/usr/local/lib,$(findstring /usr/local/lib,$(LIBPATH))) - INCPATH += /usr/local/include - OS_CCDEFS += -I/usr/local/include - endif - ifneq (,$(findstring NetBSD,$(OSTYPE))$(findstring FreeBSD,$(OSTYPE))$(findstring AIX,$(OSTYPE))) - LIBEXT = so - else - ifeq (HP-UX,$(OSTYPE)) - ifeq (ia64,$(shell uname -m)) - LIBEXT = so - else - LIBEXT = sl - endif - OS_CCDEFS += -D_HPUX_SOURCE -D_LARGEFILE64_SOURCE - OS_LDFLAGS += -Wl,+b: - NO_LTO = 1 - else - LIBEXT = a - endif - endif - endif - endif - endif - endif - # Some gcc versions don't support LTO, so only use LTO when the compiler is known to support it - ifeq (,$(NO_LTO)) - ifneq (,$(GCC_VERSION)) - ifeq (,$(shell $(GCC) -v /dev/null 2>&1 | grep '\-\-enable-lto')) - LTO_EXCLUDE_VERSIONS += $(GCC_VERSION) - endif - endif - endif - endif - $(info lib paths are: $(LIBPATH)) - $(info include paths are: $(INCPATH)) - find_lib = $(strip $(firstword $(foreach dir,$(strip $(LIBPATH)),$(wildcard $(dir)/lib$(1).$(LIBEXT))))) - find_include = $(strip $(firstword $(foreach dir,$(strip $(INCPATH)),$(wildcard $(dir)/$(1).h)))) - ifneq (,$(call find_lib,m)) - OS_LDFLAGS += -lm - $(info using libm: $(call find_lib,m)) - endif - ifneq (,$(call find_lib,rt)) - OS_LDFLAGS += -lrt - $(info using librt: $(call find_lib,rt)) - endif - ifneq (,$(call find_include,pthread)) - ifneq (,$(call find_lib,pthread)) - OS_CCDEFS += -DUSE_READER_THREAD - ifeq (,$(NOASYNCH)) - OS_CCDEFS += -DSIM_ASYNCH_IO - endif - OS_LDFLAGS += -lpthread - $(info using libpthread: $(call find_lib,pthread) $(call find_include,pthread)) - else - LIBEXTSAVE := $(LIBEXT) - LIBEXT = a - ifneq (,$(call find_lib,pthread)) - OS_CCDEFS += -DUSE_READER_THREAD - ifeq (,$(NOASYNCH)) - OS_CCDEFS += -DSIM_ASYNCH_IO - endif - OS_LDFLAGS += -lpthread - $(info using libpthread: $(call find_lib,pthread) $(call find_include,pthread)) - endif - LIBEXT = $(LIBEXTSAVE) - endif - endif - ifneq (,$(call find_include,dlfcn)) - ifneq (,$(call find_lib,dl)) - OS_CCDEFS += -DHAVE_DLOPEN=$(LIBEXT) - OS_LDFLAGS += -ldl - $(info using libdl: $(call find_lib,dl) $(call find_include,dlfcn)) - else - ifneq (,$(findstring BSD,$(OSTYPE))$(findstring AIX,$(OSTYPE))) - OS_CCDEFS += -DHAVE_DLOPEN=so - $(info using libdl: $(call find_include,dlfcn)) - else - ifneq (,$(call find_lib,dld)) - OS_CCDEFS += -DHAVE_DLOPEN=$(LIBEXT) - OS_LDFLAGS += -ldld - $(info using libdld: $(call find_lib,dld) $(call find_include,dlfcn)) - endif - endif - endif - endif - ifneq (,$(call find_include,glob)) - OS_CCDEFS += -DHAVE_GLOB - else - ifneq (,$(call find_include,fnmatch)) - OS_CCDEFS += -DHAVE_FNMATCH - endif - endif - ifneq (,$(VIDEO_USEFUL)) - ifneq (,$(call find_include,SDL2/SDL)) - ifneq (,$(call find_lib,SDL2)) - OS_CCDEFS += -DHAVE_LIBSDL -I$(dir $(call find_include,SDL2/SDL)) - OS_LDFLAGS += -lSDL2 - VIDEO_FEATURES = - video capabilities provided by libSDL2 (Simple Directmedia Layer) - $(info using libSDL2: $(call find_lib,SDL2) $(call find_include,SDL2/SDL)) - ifeq (Darwin,$(OSTYPE)) - OS_LDFLAGS += -lobjc -framework cocoa - endif - endif - else - ifneq (,$(call find_include,SDL/SDL)) - ifneq (,$(call find_lib,SDL)) - OS_CCDEFS += -DHAVE_LIBSDL -I$(dir $(call find_include,SDL/SDL)) - OS_LDFLAGS += -lSDL - VIDEO_FEATURES = - video capabilities provided by libSDL (Simple Directmedia Layer) - $(info using libSDL: $(call find_lib,SDL) $(call find_include,SDL/SDL)) - ifeq (Darwin,$(OSTYPE)) - OS_LDFLAGS += -lobjc -framework cocoa - endif - endif - endif - endif - ifeq (,$(findstring HAVE_LIBSDL,$(OS_CCDEFS))) - $(info *** Warning ***) - $(info *** Warning *** The simulator$(BUILD_MULTIPLE) you are building could provide more) - $(info *** Warning *** functionality if video support were available on your system.) - $(info *** Warning *** Install the development components of libSDL packaged by your) - $(info *** Warning *** operating system distribution and rebuild your simulator to) - $(info *** Warning *** enable this extra functionality.) - $(info *** Warning ***) - endif - endif - ifneq (,$(NETWORK_USEFUL)) - ifneq (,$(call find_include,pcap)) - ifneq (,$(shell grep 'pcap/pcap.h' $(call find_include,pcap) | grep include)) - PCAP_H_PATH = $(dir $(call find_include,pcap))pcap/pcap.h - else - PCAP_H_PATH = $(call find_include,pcap) - endif - ifneq (,$(shell grep pcap_compile $(PCAP_H_PATH) | grep const)) - BPF_CONST_STRING = -DBPF_CONST_STRING - endif - NETWORK_CCDEFS += -DHAVE_PCAP_NETWORK -I$(dir $(call find_include,pcap)) $(BPF_CONST_STRING) - NETWORK_LAN_FEATURES += PCAP - ifneq (,$(call find_lib,$(PCAPLIB))) - ifneq ($(USE_NETWORK),) # Network support specified on the GNU make command line - NETWORK_CCDEFS += -DUSE_NETWORK - $(info *** Warning ***) - $(info *** Warning *** Statically linking against libpcap is provides no measurable) - $(info *** Warning *** benefits over dynamically linking libpcap.) - $(info *** Warning ***) - $(info *** Warning *** Support for linking this way is currently deprecated and may be removed) - $(info *** Warning *** in the future.) - $(info *** Warning ***) - ifeq (cygwin,$(OSTYPE)) - # cygwin has no ldconfig so explicitly specify pcap object library - NETWORK_LDFLAGS = -L$(dir $(call find_lib,$(PCAPLIB))) -Wl,-R,$(dir $(call find_lib,$(PCAPLIB))) -l$(PCAPLIB) - else - NETWORK_LDFLAGS = -l$(PCAPLIB) - endif - $(info using libpcap: $(call find_lib,$(PCAPLIB)) $(call find_include,pcap)) - NETWORK_FEATURES = - static networking support using $(OSNAME) provided libpcap components - else # default build uses dynamic libpcap - NETWORK_CCDEFS += -DUSE_SHARED - $(info using libpcap: $(call find_include,pcap)) - NETWORK_FEATURES = - dynamic networking support using $(OSNAME) provided libpcap components - endif - else - LIBEXTSAVE := $(LIBEXT) - LIBEXT = a - ifneq (,$(call find_lib,$(PCAPLIB))) - NETWORK_CCDEFS += -DUSE_NETWORK - NETWORK_LDFLAGS := -L$(dir $(call find_lib,$(PCAPLIB))) -l$(PCAPLIB) - NETWORK_FEATURES = - static networking support using $(OSNAME) provided libpcap components - $(info using libpcap: $(call find_lib,$(PCAPLIB)) $(call find_include,pcap)) - endif - LIBEXT = $(LIBEXTSAVE) - endif - else - # On non-Linux platforms, we'll still try to provide deprecated support for libpcap in /usr/local - INCPATHSAVE := $(INCPATH) - ifeq (,$(findstring Linux,$(OSTYPE))) - # Look for package built from tcpdump.org sources with default install target (or cygwin winpcap) - INCPATH += /usr/local/include - PCAP_H_FOUND = $(call find_include,pcap) - endif - ifneq (,$(strip $(PCAP_H_FOUND))) - ifneq (,$(shell grep 'pcap/pcap.h' $(call find_include,pcap) | grep include)) - PCAP_H_PATH = $(dir $(call find_include,pcap))pcap/pcap.h - else - PCAP_H_PATH = $(call find_include,pcap) - endif - ifneq (,$(shell grep pcap_compile $(PCAP_H_PATH) | grep const)) - BPF_CONST_STRING = -DBPF_CONST_STRING - endif - LIBEXTSAVE := $(LIBEXT) - # first check if binary - shared objects are available/installed in the linker known search paths - ifneq (,$(call find_lib,$(PCAPLIB))) - NETWORK_CCDEFS = -DUSE_SHARED -I$(dir $(call find_include,pcap)) $(BPF_CONST_STRING) - NETWORK_FEATURES = - dynamic networking support using libpcap components from www.tcpdump.org and locally installed libpcap.$(LIBEXT) - $(info using libpcap: $(call find_include,pcap)) - else - LIBPATH += /usr/local/lib - LIBEXT = a - ifneq (,$(call find_lib,$(PCAPLIB))) - $(info using libpcap: $(call find_lib,$(PCAPLIB)) $(call find_include,pcap)) - ifeq (cygwin,$(OSTYPE)) - NETWORK_CCDEFS = -DUSE_NETWORK -DHAVE_PCAP_NETWORK -I$(dir $(call find_include,pcap)) $(BPF_CONST_STRING) - NETWORK_LDFLAGS = -L$(dir $(call find_lib,$(PCAPLIB))) -Wl,-R,$(dir $(call find_lib,$(PCAPLIB))) -l$(PCAPLIB) - NETWORK_FEATURES = - static networking support using libpcap components located in the cygwin directories - else - NETWORK_CCDEFS := -DUSE_NETWORK -DHAVE_PCAP_NETWORK -isystem -I$(dir $(call find_include,pcap)) $(BPF_CONST_STRING) $(call find_lib,$(PCAPLIB)) - NETWORK_FEATURES = - networking support using libpcap components from www.tcpdump.org - $(info *** Warning ***) - $(info *** Warning *** $(BUILD_SINGLE)Simulator$(BUILD_MULTIPLE) being built with networking support using) - $(info *** Warning *** libpcap components from www.tcpdump.org.) - $(info *** Warning *** Some users have had problems using the www.tcpdump.org libpcap) - $(info *** Warning *** components for simh networking. For best results, with) - $(info *** Warning *** simh networking, it is recommended that you install the) - $(info *** Warning *** libpcap-dev (or libpcap-devel) package from your $(OSNAME) distribution) - $(info *** Warning ***) - $(info *** Warning *** Building with the components manually installed from www.tcpdump.org) - $(info *** Warning *** is officially deprecated. Attempting to do so is unsupported.) - $(info *** Warning ***) - endif - else - $(error using libpcap: $(call find_include,pcap) missing $(PCAPLIB).$(LIBEXT)) - endif - NETWORK_LAN_FEATURES += PCAP - endif - LIBEXT = $(LIBEXTSAVE) - else - INCPATH = $(INCPATHSAVE) - $(info *** Warning ***) - $(info *** Warning *** $(BUILD_SINGLE)Simulator$(BUILD_MULTIPLE) are being built WITHOUT) - $(info *** Warning *** libpcap networking support) - $(info *** Warning ***) - $(info *** Warning *** To build simulator(s) with libpcap networking support you) - $(info *** Warning *** should read 0readme_ethernet.txt and follow the instructions) - $(info *** Warning *** regarding the needed libpcap development components for your) - $(info *** Warning *** $(OSTYPE) platform) - $(info *** Warning ***) - endif - endif - # Consider other network connections - ifneq (,$(call find_lib,vdeplug)) - # libvdeplug requires the use of the OS provided libpcap - ifeq (,$(findstring usr/local,$(NETWORK_CCDEFS))) - ifneq (,$(call find_include,libvdeplug)) - # Provide support for vde networking - NETWORK_CCDEFS += -DHAVE_VDE_NETWORK - NETWORK_LAN_FEATURES += VDE - ifeq (,$(findstring USE_NETWORK,$(NETWORK_CCDEFS))$(findstring USE_SHARED,$(NETWORK_CCDEFS))) - NETWORK_CCDEFS += -DUSE_NETWORK - endif - ifeq (Darwin,$(OSTYPE)) - NETWORK_LDFLAGS += -lvdeplug -L$(dir $(call find_lib,vdeplug)) - else - NETWORK_LDFLAGS += -lvdeplug -Wl,-R,$(dir $(call find_lib,vdeplug)) -L$(dir $(call find_lib,vdeplug)) - endif - $(info using libvdeplug: $(call find_lib,vdeplug) $(call find_include,libvdeplug)) - endif - endif - endif - ifeq (,$(findstring HAVE_VDE_NETWORK,$(NETWORK_CCDEFS))) - # Support is available on Linux for libvdeplug. Advise on its usage - ifneq (,$(findstring Linux,$(OSTYPE))) - ifneq (,$(findstring USE_NETWORK,$(NETWORK_CCDEFS))$(findstring USE_SHARED,$(NETWORK_CCDEFS))) - $(info *** Warning ***) - $(info *** Warning *** $(BUILD_SINGLE)Simulator$(BUILD_MULTIPLE) are being built with) - $(info *** Warning *** minimal libpcap networking support) - $(info *** Warning ***) - endif - $(info *** Warning *** Simulators on your $(OSNAME) platform can also be built with) - $(info *** Warning *** extended LAN Ethernet networking support by using VDE Ethernet.) - $(info *** Warning ***) - $(info *** Warning *** To build simulator(s) with extended networking support you) - $(info *** Warning *** should read 0readme_ethernet.txt and follow the instructions) - $(info *** Warning *** regarding the needed libvdeplug components for your $(OSNAME)) - $(info *** Warning *** platform) - $(info *** Warning ***) - endif - endif - ifneq (,$(call find_include,linux/if_tun)) - # Provide support for Tap networking on Linux - NETWORK_CCDEFS += -DHAVE_TAP_NETWORK - NETWORK_LAN_FEATURES += TAP - ifeq (,$(findstring USE_NETWORK,$(NETWORK_CCDEFS))$(findstring USE_SHARED,$(NETWORK_CCDEFS))) - NETWORK_CCDEFS += -DUSE_NETWORK - endif - endif - ifeq (bsdtuntap,$(shell if $(TEST) -e /usr/include/net/if_tun.h -o -e /Library/Extensions/tap.kext; then echo bsdtuntap; fi)) - # Provide support for Tap networking on BSD platforms (including OS X) - NETWORK_CCDEFS += -DHAVE_TAP_NETWORK -DHAVE_BSDTUNTAP - NETWORK_LAN_FEATURES += TAP - ifeq (,$(findstring USE_NETWORK,$(NETWORK_CCDEFS))$(findstring USE_SHARED,$(NETWORK_CCDEFS))) - NETWORK_CCDEFS += -DUSE_NETWORK - endif - endif - ifeq (,$(findstring USE_NETWORK,$(NETWORK_CCDEFS))$(findstring USE_SHARED,$(NETWORK_CCDEFS))$(findstring HAVE_VDE_NETWORK,$(NETWORK_CCDEFS))) - NETWORK_CCDEFS += -DUSE_NETWORK - NETWORK_FEATURES = - WITHOUT Local LAN networking support - $(info *** Warning ***) - $(info *** Warning *** $(BUILD_SINGLE)Simulator$(BUILD_MULTIPLE) are being built WITHOUT LAN networking support) - $(info *** Warning ***) - $(info *** Warning *** To build simulator(s) with networking support you should read) - $(info *** Warning *** 0readme_ethernet.txt and follow the instructions regarding the) - $(info *** Warning *** needed libpcap components for your $(OSTYPE) platform) - $(info *** Warning ***) - endif - NETWORK_OPT = $(NETWORK_CCDEFS) - endif - ifneq (binexists,$(shell if $(TEST) -e BIN; then echo binexists; fi)) - MKDIRBIN = mkdir -p BIN - endif - ifeq (commit-id-exists,$(shell if $(TEST) -e .git-commit-id; then echo commit-id-exists; fi)) - GIT_COMMIT_ID=$(shell cat .git-commit-id) - else - ifeq (,$(shell grep 'define SIM_GIT_COMMIT_ID' sim_rev.h | grep 'Format:')) - GIT_COMMIT_ID=$(shell grep 'define SIM_GIT_COMMIT_ID' sim_rev.h | awk '{ print $$3 }') - endif - endif -else - #Win32 Environments (via MinGW32) - GCC = gcc - ifeq (XP,$(findstring XP,$(shell ver))) - GCC_Path := C:\MinGW\bin\ - else - GCC_Path := $(dir $(shell where gcc.exe)) - endif - ifeq (rename-build-support,$(shell if exist ..\windows-build-windows-build echo rename-build-support)) - FIXED_BUILD := $(shell move ..\windows-build-windows-build ..\windows-build >NUL) - endif - GCC_VERSION = $(word 3,$(shell $(GCC) --version)) - COMPILER_NAME = GCC Version: $(GCC_VERSION) - LTO_EXCLUDE_VERSIONS = 4.5.2 - ifeq (pthreads,$(shell if exist ..\windows-build\pthreads\Pre-built.2\include\pthread.h echo pthreads)) - PTHREADS_CCDEFS = -DUSE_READER_THREAD -DPTW32_STATIC_LIB -I../windows-build/pthreads/Pre-built.2/include - ifeq (,$(NOASYNCH)) - PTHREADS_CCDEFS += -DSIM_ASYNCH_IO - endif - PTHREADS_LDFLAGS = -lpthreadGC2 -L..\windows-build\pthreads\Pre-built.2\lib - else - ifeq (pthreads,$(shell if exist $(dir $(GCC_Path))..\include\pthread.h echo pthreads)) - PTHREADS_CCDEFS = -DUSE_READER_THREAD - ifeq (,$(NOASYNCH)) - PTHREADS_CCDEFS += -DSIM_ASYNCH_IO - endif - PTHREADS_LDFLAGS = -lpthread - endif - endif - ifeq (pcap,$(shell if exist ..\windows-build\winpcap\Wpdpack\include\pcap.h echo pcap)) - NETWORK_LDFLAGS = - NETWORK_OPT = -DUSE_SHARED -I../windows-build/winpcap/Wpdpack/include -I$(GCC_Path)..\include\ddk - NETWORK_FEATURES = - dynamic networking support using windows-build provided libpcap components - else - ifeq (pcap,$(shell if exist $(dir $(GCC_Path))..\include\pcap.h echo pcap)) - NETWORK_LDFLAGS = - NETWORK_OPT = -DUSE_SHARED -I$(GCC_Path)..\include\ddk - NETWORK_FEATURES = - dynamic networking support using libpcap components found in the MinGW directories - endif - endif - ifneq (,$(VIDEO_USEFUL)) - ifeq (libSDL,$(shell if exist ..\windows-build\libSDL\SDL2-2.0.0\include\SDL.h echo libSDL)) - OS_CCDEFS += -DHAVE_LIBSDL -I..\windows-build\libSDL\SDL2-2.0.0\include - OS_LDFLAGS += -lSDL2 -L..\windows-build\libSDL\SDL2-2.0.0\lib - VIDEO_FEATURES = - video capabilities provided by libSDL2 (Simple Directmedia Layer) - else - $(info ***********************************************************************) - $(info ***********************************************************************) - $(info ** This build could produce simulators with video capabilities. **) - $(info ** However, the required files to achieve this can't be found on **) - $(info ** this system. Download the file: **) - $(info ** https://github.com/simh/windows-build/archive/windows-build.zip **) - $(info ** Refer to the file: **) - $(info ** "Visual Studio Projects\0ReadMe_Projects.txt" for where to place **) - $(info ** the 'windows-build' folder extracted from that zip file. **) - $(info ***********************************************************************) - $(info ***********************************************************************) - $(info .) - endif - endif - OS_CCDEFS += -fms-extensions $(PTHREADS_CCDEFS) - OS_LDFLAGS += -lm -lwsock32 -lwinmm $(PTHREADS_LDFLAGS) - EXE = .exe - ifneq (binexists,$(shell if exist BIN echo binexists)) - MKDIRBIN = if not exist BIN mkdir BIN - endif - ifneq ($(USE_NETWORK),) - NETWORK_OPT += -DUSE_SHARED - endif - ifneq (,$(shell if exist .git-commit-id type .git-commit-id)) - GIT_COMMIT_ID=$(shell if exist .git-commit-id type .git-commit-id) - else - ifeq (,$(shell findstr /C:"define SIM_GIT_COMMIT_ID" sim_rev.h | findstr Format)) - GIT_COMMIT_ID=$(shell for /F "tokens=3" %%i in ("$(shell findstr /C:"define SIM_GIT_COMMIT_ID" sim_rev.h)") do echo %%i) - endif - endif -endif -ifneq (,$(GIT_COMMIT_ID)) - CFLAGS_GIT = -DSIM_GIT_COMMIT_ID=$(GIT_COMMIT_ID) -endif -ifneq ($(DEBUG),) - CFLAGS_G = -g -ggdb -g3 - CFLAGS_O = -O0 - BUILD_FEATURES = - debugging support -else - ifneq (clang,$(findstring clang,$(COMPILER_NAME))) - CFLAGS_O = -O2 - else - ifeq (Darwin,$(OSTYPE)) - CFLAGS_O += -O4 -fno-strict-overflow -flto -fwhole-program - else - CFLAGS_O := -O2 -fno-strict-overflow - endif - endif - LDFLAGS_O = - GCC_MAJOR_VERSION = $(firstword $(subst ., ,$(GCC_VERSION))) - ifneq (3,$(GCC_MAJOR_VERSION)) - ifeq (,$(GCC_OPTIMIZERS_CMD)) - GCC_OPTIMIZERS_CMD = $(GCC) --help=optimizers - endif - GCC_OPTIMIZERS = $(shell $(GCC_OPTIMIZERS_CMD)) - endif - ifneq (,$(findstring $(GCC_VERSION),$(LTO_EXCLUDE_VERSIONS))) - NO_LTO = 1 - endif - ifneq (,$(findstring -finline-functions,$(GCC_OPTIMIZERS))) - CFLAGS_O += -finline-functions - endif - ifneq (,$(findstring -fgcse-after-reload,$(GCC_OPTIMIZERS))) - CFLAGS_O += -fgcse-after-reload - endif - ifneq (,$(findstring -fpredictive-commoning,$(GCC_OPTIMIZERS))) - CFLAGS_O += -fpredictive-commoning - endif - ifneq (,$(findstring -fipa-cp-clone,$(GCC_OPTIMIZERS))) - CFLAGS_O += -fipa-cp-clone - endif - ifneq (,$(findstring -funsafe-loop-optimizations,$(GCC_OPTIMIZERS))) - CFLAGS_O += -fno-unsafe-loop-optimizations - endif - ifneq (,$(findstring -fstrict-overflow,$(GCC_OPTIMIZERS))) - CFLAGS_O += -fno-strict-overflow - endif - ifeq (,$(NO_LTO)) - ifneq (,$(findstring -flto,$(GCC_OPTIMIZERS))) - CFLAGS_O += -flto -fwhole-program - LDFLAGS_O += -flto -fwhole-program - endif - endif - BUILD_FEATURES = - compiler optimizations and no debugging support -endif -ifneq (3,$(GCC_MAJOR_VERSION)) - ifeq (,$(GCC_WARNINGS_CMD)) - GCC_WARNINGS_CMD = $(GCC) --help=warnings - endif - ifneq (,$(findstring -Wunused-result,$(shell $(GCC_WARNINGS_CMD)))) - CFLAGS_O += -Wno-unused-result - endif -endif -ifneq (clean,$(MAKECMDGOALS)) - BUILD_FEATURES := $(BUILD_FEATURES). $(COMPILER_NAME) - $(info ***) - $(info *** $(BUILD_SINGLE)Simulator$(BUILD_MULTIPLE) being built with:) - $(info *** $(BUILD_FEATURES).) - ifneq (,$(NETWORK_FEATURES)) - $(info *** $(NETWORK_FEATURES).) - endif - ifneq (,$(NETWORK_LAN_FEATURES)) - $(info *** - Local LAN packet transports: $(NETWORK_LAN_FEATURES)) - endif - ifneq (,$(VIDEO_FEATURES)) - $(info *** $(VIDEO_FEATURES).) - endif - ifneq (,$(GIT_COMMIT_ID)) - $(info ***) - $(info *** git commit id is $(GIT_COMMIT_ID).) - endif - $(info ***) -endif -ifneq ($(DONT_USE_ROMS),) - ROMS_OPT = -DDONT_USE_INTERNAL_ROM -else - BUILD_ROMS = ${BIN}BuildROMs${EXE} -endif -ifneq ($(DONT_USE_READER_THREAD),) - NETWORK_OPT += -DDONT_USE_READER_THREAD -endif - -ifeq (HP-UX,$(OSTYPE)) - CC_STD = -std=gnu99 -else - ifeq (,$(SUNC_VERSION)) - CC_STD = -std=c99 - endif -endif -CC_OUTSPEC = -o $@ -CC := $(GCC) $(CC_STD) -U__STRICT_ANSI__ $(CFLAGS_G) $(CFLAGS_O) $(CFLAGS_GIT) -DSIM_COMPILER="$(COMPILER_NAME)" -I . $(OS_CCDEFS) $(ROMS_OPT) -LDFLAGS := $(OS_LDFLAGS) $(NETWORK_LDFLAGS) $(LDFLAGS_O) - -# -# Common Libraries -# -BIN = BIN/ -SIM = scp.c sim_console.c sim_fio.c sim_timer.c sim_sock.c \ - sim_tmxr.c sim_ether.c sim_tape.c sim_disk.c sim_serial.c \ - sim_video.c - -DISPLAYD = display -ifeq ($(WIN32),) - ifeq (x11,$(shell if $(TEST) -e /usr/include/X11/Intrinsic.h ; then echo x11; fi)) - DISPLAYL = ${DISPLAYD}/display.c $(DISPLAYD)/x11.c - DISPLAYVT = ${DISPLAYD}/vt11.c - DISPLAY_OPT = -DUSE_DISPLAY -I/usr/X11/include -lXt -lX11 -lm - else - DISPLAYL = - DISPLAYVT = - DISPLAY_OPT = - endif -else - DISPLAYL = ${DISPLAYD}/display.c $(DISPLAYD)/win32.c - DISPLAYVT = ${DISPLAYD}/vt11.c - DISPLAY_OPT = -DUSE_DISPLAY -lgdi32 -endif - -# -# Emulator source files and compile time options -# -PDP1D = PDP1 -PDP1 = ${PDP1D}/pdp1_lp.c ${PDP1D}/pdp1_cpu.c ${PDP1D}/pdp1_stddev.c \ - ${PDP1D}/pdp1_sys.c ${PDP1D}/pdp1_dt.c ${PDP1D}/pdp1_drm.c \ - ${PDP1D}/pdp1_clk.c ${PDP1D}/pdp1_dcs.c ${PDP1D}/pdp1_dpy.c ${DISPLAYL} -PDP1_OPT = -I ${PDP1D} $(DISPLAY_OPT) - - -NOVAD = NOVA -NOVA = ${NOVAD}/nova_sys.c ${NOVAD}/nova_cpu.c ${NOVAD}/nova_dkp.c \ - ${NOVAD}/nova_dsk.c ${NOVAD}/nova_lp.c ${NOVAD}/nova_mta.c \ - ${NOVAD}/nova_plt.c ${NOVAD}/nova_pt.c ${NOVAD}/nova_clk.c \ - ${NOVAD}/nova_tt.c ${NOVAD}/nova_tt1.c ${NOVAD}/nova_qty.c -NOVA_OPT = -I ${NOVAD} - - -ECLIPSE = ${NOVAD}/eclipse_cpu.c ${NOVAD}/eclipse_tt.c ${NOVAD}/nova_sys.c \ - ${NOVAD}/nova_dkp.c ${NOVAD}/nova_dsk.c ${NOVAD}/nova_lp.c \ - ${NOVAD}/nova_mta.c ${NOVAD}/nova_plt.c ${NOVAD}/nova_pt.c \ - ${NOVAD}/nova_clk.c ${NOVAD}/nova_tt1.c ${NOVAD}/nova_qty.c -ECLIPSE_OPT = -I ${NOVAD} -DECLIPSE - - -PDP18BD = PDP18B -PDP18B = ${PDP18BD}/pdp18b_dt.c ${PDP18BD}/pdp18b_drm.c ${PDP18BD}/pdp18b_cpu.c \ - ${PDP18BD}/pdp18b_lp.c ${PDP18BD}/pdp18b_mt.c ${PDP18BD}/pdp18b_rf.c \ - ${PDP18BD}/pdp18b_rp.c ${PDP18BD}/pdp18b_stddev.c ${PDP18BD}/pdp18b_sys.c \ - ${PDP18BD}/pdp18b_rb.c ${PDP18BD}/pdp18b_tt1.c ${PDP18BD}/pdp18b_fpp.c -PDP4_OPT = -DPDP4 -I ${PDP18BD} -PDP7_OPT = -DPDP7 -I ${PDP18BD} -PDP9_OPT = -DPDP9 -I ${PDP18BD} -PDP15_OPT = -DPDP15 -I ${PDP18BD} - - -PDP11D = PDP11 -PDP11 = ${PDP11D}/pdp11_fp.c ${PDP11D}/pdp11_cpu.c ${PDP11D}/pdp11_dz.c \ - ${PDP11D}/pdp11_cis.c ${PDP11D}/pdp11_lp.c ${PDP11D}/pdp11_rk.c \ - ${PDP11D}/pdp11_rl.c ${PDP11D}/pdp11_rp.c ${PDP11D}/pdp11_rx.c \ - ${PDP11D}/pdp11_stddev.c ${PDP11D}/pdp11_sys.c ${PDP11D}/pdp11_tc.c \ - ${PDP11D}/pdp11_tm.c ${PDP11D}/pdp11_ts.c ${PDP11D}/pdp11_io.c \ - ${PDP11D}/pdp11_rq.c ${PDP11D}/pdp11_tq.c ${PDP11D}/pdp11_pclk.c \ - ${PDP11D}/pdp11_ry.c ${PDP11D}/pdp11_pt.c ${PDP11D}/pdp11_hk.c \ - ${PDP11D}/pdp11_xq.c ${PDP11D}/pdp11_xu.c ${PDP11D}/pdp11_vh.c \ - ${PDP11D}/pdp11_rh.c ${PDP11D}/pdp11_tu.c ${PDP11D}/pdp11_cpumod.c \ - ${PDP11D}/pdp11_cr.c ${PDP11D}/pdp11_rf.c ${PDP11D}/pdp11_dl.c \ - ${PDP11D}/pdp11_ta.c ${PDP11D}/pdp11_rc.c ${PDP11D}/pdp11_kg.c \ - ${PDP11D}/pdp11_ke.c ${PDP11D}/pdp11_dc.c ${PDP11D}/pdp11_dmc.c \ - ${PDP11D}/pdp11_kmc.c ${PDP11D}/pdp11_dup.c ${PDP11D}/pdp11_rs.c \ - ${PDP11D}/pdp11_vt.c ${PDP11D}/pdp11_io_lib.c $(DISPLAYL) $(DISPLAYVT) -PDP11_OPT = -DVM_PDP11 -I ${PDP11D} ${NETWORK_OPT} $(DISPLAY_OPT) - - -VAXD = VAX -VAX = ${VAXD}/vax_cpu.c ${VAXD}/vax_cpu1.c ${VAXD}/vax_fpa.c ${VAXD}/vax_io.c \ - ${VAXD}/vax_cis.c ${VAXD}/vax_octa.c ${VAXD}/vax_cmode.c \ - ${VAXD}/vax_mmu.c ${VAXD}/vax_stddev.c ${VAXD}/vax_sysdev.c \ - ${VAXD}/vax_sys.c ${VAXD}/vax_syscm.c ${VAXD}/vax_syslist.c \ - ${PDP11D}/pdp11_rl.c ${PDP11D}/pdp11_rq.c ${PDP11D}/pdp11_ts.c \ - ${PDP11D}/pdp11_dz.c ${PDP11D}/pdp11_lp.c ${PDP11D}/pdp11_tq.c \ - ${PDP11D}/pdp11_xq.c ${PDP11D}/pdp11_vh.c ${PDP11D}/pdp11_cr.c \ - ${PDP11D}/pdp11_io_lib.c -VAX_OPT = -DVM_VAX -DUSE_INT64 -DUSE_ADDR64 -I ${VAXD} -I ${PDP11D} ${NETWORK_OPT} - - -VAX610 = ${VAXD}/vax_cpu.c ${VAXD}/vax_cpu1.c ${VAXD}/vax_fpa.c \ - ${VAXD}/vax_cis.c ${VAXD}/vax_octa.c ${VAXD}/vax_cmode.c \ - ${VAXD}/vax_mmu.c ${VAXD}/vax_sys.c ${VAXD}/vax_syscm.c \ - ${VAXD}/vax610_stddev.c ${VAXD}/vax610_sysdev.c ${VAXD}/vax610_io.c \ - ${VAXD}/vax610_syslist.c ${VAXD}/vax610_mem.c ${VAXD}/vax_vc.c \ - ${VAXD}/vax_lk.c ${VAXD}/vax_vs.c ${VAXD}/vax_2681.c \ - ${PDP11D}/pdp11_rl.c ${PDP11D}/pdp11_rq.c ${PDP11D}/pdp11_ts.c \ - ${PDP11D}/pdp11_dz.c ${PDP11D}/pdp11_lp.c ${PDP11D}/pdp11_tq.c \ - ${PDP11D}/pdp11_xq.c ${PDP11D}/pdp11_vh.c ${PDP11D}/pdp11_cr.c \ - ${PDP11D}/pdp11_io_lib.c -VAX610_OPT = -DVM_VAX -DVAX_610 -DUSE_INT64 -DUSE_ADDR64 -DUSE_SIM_VIDEO -I ${VAXD} -I ${PDP11D} ${NETWORK_OPT} - -VAX630 = ${VAXD}/vax_cpu.c ${VAXD}/vax_cpu1.c ${VAXD}/vax_fpa.c \ - ${VAXD}/vax_cis.c ${VAXD}/vax_octa.c ${VAXD}/vax_cmode.c \ - ${VAXD}/vax_mmu.c ${VAXD}/vax_sys.c ${VAXD}/vax_syscm.c \ - ${VAXD}/vax_watch.c ${VAXD}/vax630_stddev.c ${VAXD}/vax630_sysdev.c \ - ${VAXD}/vax630_io.c ${VAXD}/vax630_syslist.c ${VAXD}/vax_vc.c \ - ${VAXD}/vax_lk.c ${VAXD}/vax_vs.c ${VAXD}/vax_2681.c \ - ${PDP11D}/pdp11_rl.c ${PDP11D}/pdp11_rq.c ${PDP11D}/pdp11_ts.c \ - ${PDP11D}/pdp11_dz.c ${PDP11D}/pdp11_lp.c ${PDP11D}/pdp11_tq.c \ - ${PDP11D}/pdp11_xq.c ${PDP11D}/pdp11_vh.c ${PDP11D}/pdp11_cr.c \ - ${PDP11D}/pdp11_io_lib.c -VAX620_OPT = -DVM_VAX -DVAX_620 -DUSE_INT64 -DUSE_ADDR64 -I ${VAXD} -I ${PDP11D} ${NETWORK_OPT} -VAX630_OPT = -DVM_VAX -DVAX_630 -DUSE_INT64 -DUSE_ADDR64 -DUSE_SIM_VIDEO -I ${VAXD} -I ${PDP11D} ${NETWORK_OPT} - - -VAX730 = ${VAXD}/vax_cpu.c ${VAXD}/vax_cpu1.c ${VAXD}/vax_fpa.c \ - ${VAXD}/vax_cis.c ${VAXD}/vax_octa.c ${VAXD}/vax_cmode.c \ - ${VAXD}/vax_mmu.c ${VAXD}/vax_sys.c ${VAXD}/vax_syscm.c \ - ${VAXD}/vax730_stddev.c ${VAXD}/vax730_sys.c \ - ${VAXD}/vax730_mem.c ${VAXD}/vax730_uba.c ${VAXD}/vax730_rb.c \ - ${VAXD}/vax730_syslist.c \ - ${PDP11D}/pdp11_rl.c ${PDP11D}/pdp11_rq.c ${PDP11D}/pdp11_ts.c \ - ${PDP11D}/pdp11_dz.c ${PDP11D}/pdp11_lp.c ${PDP11D}/pdp11_tq.c \ - ${PDP11D}/pdp11_xu.c ${PDP11D}/pdp11_ry.c ${PDP11D}/pdp11_cr.c \ - ${PDP11D}/pdp11_hk.c ${PDP11D}/pdp11_vh.c ${PDP11D}/pdp11_dmc.c \ - ${PDP11D}/pdp11_dup.c ${PDP11D}/pdp11_io_lib.c -VAX730_OPT = -DVM_VAX -DVAX_730 -DUSE_INT64 -DUSE_ADDR64 -I VAX -I ${PDP11D} ${NETWORK_OPT} - - -VAX750 = ${VAXD}/vax_cpu.c ${VAXD}/vax_cpu1.c ${VAXD}/vax_fpa.c \ - ${VAXD}/vax_cis.c ${VAXD}/vax_octa.c ${VAXD}/vax_cmode.c \ - ${VAXD}/vax_mmu.c ${VAXD}/vax_sys.c ${VAXD}/vax_syscm.c \ - ${VAXD}/vax750_stddev.c ${VAXD}/vax750_cmi.c \ - ${VAXD}/vax750_mem.c ${VAXD}/vax750_uba.c ${VAXD}/vax7x0_mba.c \ - ${VAXD}/vax750_syslist.c \ - ${PDP11D}/pdp11_rl.c ${PDP11D}/pdp11_rq.c ${PDP11D}/pdp11_ts.c \ - ${PDP11D}/pdp11_dz.c ${PDP11D}/pdp11_lp.c ${PDP11D}/pdp11_tq.c \ - ${PDP11D}/pdp11_xu.c ${PDP11D}/pdp11_ry.c ${PDP11D}/pdp11_cr.c \ - ${PDP11D}/pdp11_hk.c ${PDP11D}/pdp11_rp.c ${PDP11D}/pdp11_tu.c \ - ${PDP11D}/pdp11_vh.c ${PDP11D}/pdp11_dmc.c ${PDP11D}/pdp11_dup.c \ - ${PDP11D}/pdp11_io_lib.c -VAX750_OPT = -DVM_VAX -DVAX_750 -DUSE_INT64 -DUSE_ADDR64 -I VAX -I ${PDP11D} ${NETWORK_OPT} - - -VAX780 = ${VAXD}/vax_cpu.c ${VAXD}/vax_cpu1.c ${VAXD}/vax_fpa.c \ - ${VAXD}/vax_cis.c ${VAXD}/vax_octa.c ${VAXD}/vax_cmode.c \ - ${VAXD}/vax_mmu.c ${VAXD}/vax_sys.c ${VAXD}/vax_syscm.c \ - ${VAXD}/vax780_stddev.c ${VAXD}/vax780_sbi.c \ - ${VAXD}/vax780_mem.c ${VAXD}/vax780_uba.c ${VAXD}/vax7x0_mba.c \ - ${VAXD}/vax780_fload.c ${VAXD}/vax780_syslist.c \ - ${PDP11D}/pdp11_rl.c ${PDP11D}/pdp11_rq.c ${PDP11D}/pdp11_ts.c \ - ${PDP11D}/pdp11_dz.c ${PDP11D}/pdp11_lp.c ${PDP11D}/pdp11_tq.c \ - ${PDP11D}/pdp11_xu.c ${PDP11D}/pdp11_ry.c ${PDP11D}/pdp11_cr.c \ - ${PDP11D}/pdp11_rp.c ${PDP11D}/pdp11_tu.c ${PDP11D}/pdp11_hk.c \ - ${PDP11D}/pdp11_vh.c ${PDP11D}/pdp11_dmc.c ${PDP11D}/pdp11_dup.c \ - ${PDP11D}/pdp11_io_lib.c -VAX780_OPT = -DVM_VAX -DVAX_780 -DUSE_INT64 -DUSE_ADDR64 -I VAX -I ${PDP11D} ${NETWORK_OPT} - - -VAX8600 = ${VAXD}/vax_cpu.c ${VAXD}/vax_cpu1.c ${VAXD}/vax_fpa.c \ - ${VAXD}/vax_cis.c ${VAXD}/vax_octa.c ${VAXD}/vax_cmode.c \ - ${VAXD}/vax_mmu.c ${VAXD}/vax_sys.c ${VAXD}/vax_syscm.c \ - ${VAXD}/vax860_stddev.c ${VAXD}/vax860_sbia.c \ - ${VAXD}/vax860_abus.c ${VAXD}/vax780_uba.c ${VAXD}/vax7x0_mba.c \ - ${VAXD}/vax860_syslist.c \ - ${PDP11D}/pdp11_rl.c ${PDP11D}/pdp11_rq.c ${PDP11D}/pdp11_ts.c \ - ${PDP11D}/pdp11_dz.c ${PDP11D}/pdp11_lp.c ${PDP11D}/pdp11_tq.c \ - ${PDP11D}/pdp11_xu.c ${PDP11D}/pdp11_ry.c ${PDP11D}/pdp11_cr.c \ - ${PDP11D}/pdp11_rp.c ${PDP11D}/pdp11_tu.c ${PDP11D}/pdp11_hk.c \ - ${PDP11D}/pdp11_vh.c ${PDP11D}/pdp11_dmc.c ${PDP11D}/pdp11_dup.c \ - ${PDP11D}/pdp11_io_lib.c -VAX8600_OPT = -DVM_VAX -DVAX_860 -DUSE_INT64 -DUSE_ADDR64 -I VAX -I ${PDP11D} ${NETWORK_OPT} - - -PDP10D = PDP10 -PDP10 = ${PDP10D}/pdp10_fe.c ${PDP11D}/pdp11_dz.c ${PDP10D}/pdp10_cpu.c \ - ${PDP10D}/pdp10_ksio.c ${PDP10D}/pdp10_lp20.c ${PDP10D}/pdp10_mdfp.c \ - ${PDP10D}/pdp10_pag.c ${PDP10D}/pdp10_rp.c ${PDP10D}/pdp10_sys.c \ - ${PDP10D}/pdp10_tim.c ${PDP10D}/pdp10_tu.c ${PDP10D}/pdp10_xtnd.c \ - ${PDP11D}/pdp11_pt.c ${PDP11D}/pdp11_ry.c ${PDP11D}/pdp11_cr.c \ - ${PDP11D}/pdp11_dup.c ${PDP11D}/pdp11_dmc.c ${PDP11D}/pdp11_kmc.c -PDP10_OPT = -DVM_PDP10 -DUSE_INT64 -I ${PDP10D} -I ${PDP11D} - - -PDP8D = PDP8 -PDP8 = ${PDP8D}/pdp8_cpu.c ${PDP8D}/pdp8_clk.c ${PDP8D}/pdp8_df.c \ - ${PDP8D}/pdp8_dt.c ${PDP8D}/pdp8_lp.c ${PDP8D}/pdp8_mt.c \ - ${PDP8D}/pdp8_pt.c ${PDP8D}/pdp8_rf.c ${PDP8D}/pdp8_rk.c \ - ${PDP8D}/pdp8_rx.c ${PDP8D}/pdp8_sys.c ${PDP8D}/pdp8_tt.c \ - ${PDP8D}/pdp8_ttx.c ${PDP8D}/pdp8_rl.c ${PDP8D}/pdp8_tsc.c \ - ${PDP8D}/pdp8_td.c ${PDP8D}/pdp8_ct.c ${PDP8D}/pdp8_fpp.c -PDP8_OPT = -I ${PDP8D} - - -H316D = H316 -H316 = ${H316D}/h316_stddev.c ${H316D}/h316_lp.c ${H316D}/h316_cpu.c \ - ${H316D}/h316_sys.c ${H316D}/h316_mt.c ${H316D}/h316_fhd.c \ - ${H316D}/h316_dp.c ${H316D}/h316_rtc.c ${H316D}/h316_imp.c \ - ${H316D}/h316_hi.c ${H316D}/h316_mi.c ${H316D}/h316_udp.c -H316_OPT = -I ${H316D} -D VM_IMPTIP - - -HP2100D = HP2100 -HP2100 = ${HP2100D}/hp2100_stddev.c ${HP2100D}/hp2100_dp.c ${HP2100D}/hp2100_dq.c \ - ${HP2100D}/hp2100_dr.c ${HP2100D}/hp2100_lps.c ${HP2100D}/hp2100_ms.c \ - ${HP2100D}/hp2100_mt.c ${HP2100D}/hp2100_mux.c ${HP2100D}/hp2100_cpu.c \ - ${HP2100D}/hp2100_fp.c ${HP2100D}/hp2100_sys.c ${HP2100D}/hp2100_lpt.c \ - ${HP2100D}/hp2100_ipl.c ${HP2100D}/hp2100_ds.c ${HP2100D}/hp2100_cpu0.c \ - ${HP2100D}/hp2100_cpu1.c ${HP2100D}/hp2100_cpu2.c ${HP2100D}/hp2100_cpu3.c \ - ${HP2100D}/hp2100_cpu4.c ${HP2100D}/hp2100_cpu5.c ${HP2100D}/hp2100_cpu6.c \ - ${HP2100D}/hp2100_cpu7.c ${HP2100D}/hp2100_fp1.c ${HP2100D}/hp2100_baci.c \ - ${HP2100D}/hp2100_mpx.c ${HP2100D}/hp2100_pif.c ${HP2100D}/hp2100_di.c \ - ${HP2100D}/hp2100_di_da.c ${HP2100D}/hp_disclib.c -HP2100_OPT = -DHAVE_INT64 -I ${HP2100D} - - -I1401D = I1401 -I1401 = ${I1401D}/i1401_lp.c ${I1401D}/i1401_cpu.c ${I1401D}/i1401_iq.c \ - ${I1401D}/i1401_cd.c ${I1401D}/i1401_mt.c ${I1401D}/i1401_dp.c \ - ${I1401D}/i1401_sys.c -I1401_OPT = -I ${I1401D} - - -I1620D = I1620 -I1620 = ${I1620D}/i1620_cd.c ${I1620D}/i1620_dp.c ${I1620D}/i1620_pt.c \ - ${I1620D}/i1620_tty.c ${I1620D}/i1620_cpu.c ${I1620D}/i1620_lp.c \ - ${I1620D}/i1620_fp.c ${I1620D}/i1620_sys.c -I1620_OPT = -I ${I1620D} - - -I7094D = I7094 -I7094 = ${I7094D}/i7094_cpu.c ${I7094D}/i7094_cpu1.c ${I7094D}/i7094_io.c \ - ${I7094D}/i7094_cd.c ${I7094D}/i7094_clk.c ${I7094D}/i7094_com.c \ - ${I7094D}/i7094_drm.c ${I7094D}/i7094_dsk.c ${I7094D}/i7094_sys.c \ - ${I7094D}/i7094_lp.c ${I7094D}/i7094_mt.c ${I7094D}/i7094_binloader.c -I7094_OPT = -DUSE_INT64 -I ${I7094D} - - -IBM1130D = Ibm1130 -IBM1130 = ${IBM1130D}/ibm1130_cpu.c ${IBM1130D}/ibm1130_cr.c \ - ${IBM1130D}/ibm1130_disk.c ${IBM1130D}/ibm1130_stddev.c \ - ${IBM1130D}/ibm1130_sys.c ${IBM1130D}/ibm1130_gdu.c \ - ${IBM1130D}/ibm1130_gui.c ${IBM1130D}/ibm1130_prt.c \ - ${IBM1130D}/ibm1130_fmt.c ${IBM1130D}/ibm1130_ptrp.c \ - ${IBM1130D}/ibm1130_plot.c ${IBM1130D}/ibm1130_sca.c \ - ${IBM1130D}/ibm1130_t2741.c -IBM1130_OPT = -I ${IBM1130D} -ifneq ($(WIN32),) -IBM1130_OPT += -DGUI_SUPPORT -lgdi32 -endif - - -ID16D = Interdata -ID16 = ${ID16D}/id16_cpu.c ${ID16D}/id16_sys.c ${ID16D}/id_dp.c \ - ${ID16D}/id_fd.c ${ID16D}/id_fp.c ${ID16D}/id_idc.c ${ID16D}/id_io.c \ - ${ID16D}/id_lp.c ${ID16D}/id_mt.c ${ID16D}/id_pas.c ${ID16D}/id_pt.c \ - ${ID16D}/id_tt.c ${ID16D}/id_uvc.c ${ID16D}/id16_dboot.c ${ID16D}/id_ttp.c -ID16_OPT = -I ${ID16D} - - -ID32D = Interdata -ID32 = ${ID32D}/id32_cpu.c ${ID32D}/id32_sys.c ${ID32D}/id_dp.c \ - ${ID32D}/id_fd.c ${ID32D}/id_fp.c ${ID32D}/id_idc.c ${ID32D}/id_io.c \ - ${ID32D}/id_lp.c ${ID32D}/id_mt.c ${ID32D}/id_pas.c ${ID32D}/id_pt.c \ - ${ID32D}/id_tt.c ${ID32D}/id_uvc.c ${ID32D}/id32_dboot.c ${ID32D}/id_ttp.c -ID32_OPT = -I ${ID32D} - - -S3D = S3 -S3 = ${S3D}/s3_cd.c ${S3D}/s3_cpu.c ${S3D}/s3_disk.c ${S3D}/s3_lp.c \ - ${S3D}/s3_pkb.c ${S3D}/s3_sys.c -S3_OPT = -I ${S3D} - - -ALTAIRD = ALTAIR -ALTAIR = ${ALTAIRD}/altair_sio.c ${ALTAIRD}/altair_cpu.c ${ALTAIRD}/altair_dsk.c \ - ${ALTAIRD}/altair_sys.c -ALTAIR_OPT = -I ${ALTAIRD} - - -ALTAIRZ80D = AltairZ80 -ALTAIRZ80 = ${ALTAIRZ80D}/altairz80_cpu.c ${ALTAIRZ80D}/altairz80_cpu_nommu.c \ - ${ALTAIRZ80D}/altairz80_dsk.c ${ALTAIRZ80D}/disasm.c \ - ${ALTAIRZ80D}/altairz80_sio.c ${ALTAIRZ80D}/altairz80_sys.c \ - ${ALTAIRZ80D}/altairz80_hdsk.c ${ALTAIRZ80D}/altairz80_net.c \ - ${ALTAIRZ80D}/flashwriter2.c ${ALTAIRZ80D}/i86_decode.c \ - ${ALTAIRZ80D}/i86_ops.c ${ALTAIRZ80D}/i86_prim_ops.c \ - ${ALTAIRZ80D}/i8272.c ${ALTAIRZ80D}/insnsd.c ${ALTAIRZ80D}/altairz80_mhdsk.c \ - ${ALTAIRZ80D}/mfdc.c ${ALTAIRZ80D}/n8vem.c ${ALTAIRZ80D}/vfdhd.c \ - ${ALTAIRZ80D}/s100_disk1a.c ${ALTAIRZ80D}/s100_disk2.c ${ALTAIRZ80D}/s100_disk3.c \ - ${ALTAIRZ80D}/s100_fif.c ${ALTAIRZ80D}/s100_mdriveh.c \ - ${ALTAIRZ80D}/s100_mdsad.c ${ALTAIRZ80D}/s100_selchan.c \ - ${ALTAIRZ80D}/s100_ss1.c ${ALTAIRZ80D}/s100_64fdc.c \ - ${ALTAIRZ80D}/s100_scp300f.c ${ALTAIRZ80D}/sim_imd.c \ - ${ALTAIRZ80D}/wd179x.c ${ALTAIRZ80D}/s100_hdc1001.c \ - ${ALTAIRZ80D}/s100_if3.c ${ALTAIRZ80D}/s100_adcs6.c \ - ${ALTAIRZ80D}/m68kcpu.c ${ALTAIRZ80D}/m68kdasm.c \ - ${ALTAIRZ80D}/m68kopac.c ${ALTAIRZ80D}/m68kopdm.c \ - ${ALTAIRZ80D}/m68kopnz.c ${ALTAIRZ80D}/m68kops.c ${ALTAIRZ80D}/m68ksim.c -ALTAIRZ80_OPT = -I ${ALTAIRZ80D} - - -GRID = GRI -GRI = ${GRID}/gri_cpu.c ${GRID}/gri_stddev.c ${GRID}/gri_sys.c -GRI_OPT = -I ${GRID} - - -LGPD = LGP -LGP = ${LGPD}/lgp_cpu.c ${LGPD}/lgp_stddev.c ${LGPD}/lgp_sys.c -LGP_OPT = -I ${LGPD} - - -SDSD = SDS -SDS = ${SDSD}/sds_cpu.c ${SDSD}/sds_drm.c ${SDSD}/sds_dsk.c ${SDSD}/sds_io.c \ - ${SDSD}/sds_lp.c ${SDSD}/sds_mt.c ${SDSD}/sds_mux.c ${SDSD}/sds_rad.c \ - ${SDSD}/sds_stddev.c ${SDSD}/sds_sys.c -SDS_OPT = -I ${SDSD} - -SWTP6800D = swtp6800/swtp6800 -SWTP6800C = swtp6800/common -SWTP6800MP-A = ${SWTP6800C}/mp-a.c ${SWTP6800C}/m6800.c ${SWTP6800C}/m6810.c \ - ${SWTP6800C}/bootrom.c ${SWTP6800C}/dc-4.c ${SWTP6800C}/mp-s.c ${SWTP6800D}/mp-a_sys.c \ - ${SWTP6800C}/mp-b2.c ${SWTP6800C}/mp-8m.c -SWTP6800MP-A2 = ${SWTP6800C}/mp-a2.c ${SWTP6800C}/m6800.c ${SWTP6800C}/m6810.c \ - ${SWTP6800C}/bootrom.c ${SWTP6800C}/dc-4.c ${SWTP6800C}/mp-s.c ${SWTP6800D}/mp-a2_sys.c \ - ${SWTP6800C}/mp-b2.c ${SWTP6800C}/mp-8m.c ${SWTP6800C}/i2716.c -SWTP6800_OPT = -I ${SWTP6800D} - -TX0D = TX-0 -TX0 = ${TX0D}/tx0_cpu.c ${TX0D}/tx0_dpy.c ${TX0D}/tx0_stddev.c \ - ${TX0D}/tx0_sys.c ${TX0D}/tx0_sys_orig.c ${DISPLAYL} -TX0_OPT = -I ${TX0D} $(DISPLAY_OPT) - - -SSEMD = SSEM -SSEM = ${SSEMD}/ssem_cpu.c ${SSEMD}/ssem_sys.c -SSEM_OPT = -I ${SSEMD} - -System_80-10D = Intel/System_80-10 -iCOMMOND = Intel/common -System_80-10 = ${iCOMMOND}/i8251.c ${iCOMMOND}/i8255.c ${iCOMMOND}/i8080.c \ - ${iCOMMOND}/multibus.c ${iCOMMOND}/iSBC80-10.c \ - ${System_80-10D}/system_80_10_sys.c ${iCOMMOND}/isbc208.c \ - ${iCOMMOND}/isbc064.c ${iCOMMOND}/ieprom.c ${iCOMMOND}/iram8.c -System_80-10_OPT = -I ${System_80-10D} - - -System_80-20D = Intel/System_80-20 -iCOMMOND = Intel/common -System_80-20 = ${iCOMMOND}/i8251.c ${iCOMMOND}/i8255.c ${iCOMMOND}/i8080.c \ - ${iCOMMOND}/multibus.c ${iCOMMOND}/iSBC80-20.c \ - ${System_80-20D}/system_80_20_sys.c ${iCOMMOND}/isbc208.c \ - ${iCOMMOND}/isbc064.c ${iCOMMOND}/ieprom.c ${iCOMMOND}/iram8.c \ - ${iCOMMOND}/i8259.c -System_80-20_OPT = -I ${System_80-20D} - - -System_80-30D = Intel/System_80-30 -iCOMMOND = Intel/common -System_80-30 = ${iCOMMOND}/i8251.c ${iCOMMOND}/i8255.c ${iCOMMOND}/i8080.c \ - ${iCOMMOND}/multibus.c ${iCOMMOND}/iSBC80-20.c \ - ${System_80-30D}/system_80_30_sys.c ${iCOMMOND}/isbc208.c \ - ${iCOMMOND}/isbc064.c ${iCOMMOND}/ieprom.c ${iCOMMOND}/iram8.c \ - ${iCOMMOND}/i8259.c -System_80-30_OPT = -I ${System_80-30D} - - -# -# Build everything -# -#ALL = pdp1 pdp4 pdp7 pdp8 pdp9 pdp15 pdp11 pdp10 -# vax microvax3900 microvax1 rtvax1000 microvax2 vax730 vax750 vax780 vax8600 -# nova eclipse hp2100 i1401 i1620 s3 altair altairz80 gri -## swtp6800mp-a swtp6800mp-a2 tx-0 ssem -ALL = System_80-10 - -all : ${ALL} - -clean : -ifeq ($(WIN32),) - ${RM} -r ${BIN} -else - if exist BIN\*.exe del /q BIN\*.exe - if exist BIN rmdir BIN -endif - -${BIN}BuildROMs${EXE} : - ${MKDIRBIN} -ifeq (agcc,$(findstring agcc,$(firstword $(CC)))) - gcc $(wordlist 2,1000,${CC}) sim_BuildROMs.c $(CC_OUTSPEC) -else - ${CC} sim_BuildROMs.c $(CC_OUTSPEC) -endif -ifeq ($(WIN32),) - $@ - ${RM} $@ - ifeq (Darwin,$(OSTYPE)) # remove Xcode's debugging symbols folder too - ${RM} -rf $@.dSYM - endif -else - $(@D)\$(@F) - del $(@D)\$(@F) -endif - -# -# Individual builds -# -System_80-10 : ${BIN}System_80-10${EXE} - -${BIN}System_80-10${EXE} : ${System_80-10} ${SIM} - ${MKDIRBIN} - ${CC} ${System_80-10} ${SIM} ${System_80-10_OPT} -o $@ ${LDFLAGS} - -System_80-20 : ${BIN}System_80-20${EXE} - -${BIN}System_80-20${EXE} : ${System_80-20} ${SIM} - ${MKDIRBIN} - ${CC} ${System_80-20} ${SIM} ${System_80-20_OPT} -o $@ ${LDFLAGS} - -System_80-30 : ${BIN}System_80-30${EXE} - -${BIN}System_80-30${EXE} : ${System_80-30} ${SIM} - ${MKDIRBIN} - ${CC} ${System_80-30} ${SIM} ${System_80-30_OPT} -o $@ ${LDFLAGS} - -pdp1 : ${BIN}pdp1${EXE} - -${BIN}pdp1${EXE} : ${PDP1} ${SIM} - ${MKDIRBIN} - ${CC} ${PDP1} ${SIM} ${PDP1_OPT} $(CC_OUTSPEC) ${LDFLAGS} - -pdp4 : ${BIN}pdp4${EXE} - -${BIN}pdp4${EXE} : ${PDP18B} ${SIM} - ${MKDIRBIN} - ${CC} ${PDP18B} ${SIM} ${PDP4_OPT} $(CC_OUTSPEC) ${LDFLAGS} - -pdp7 : ${BIN}pdp7${EXE} - -${BIN}pdp7${EXE} : ${PDP18B} ${SIM} - ${MKDIRBIN} - ${CC} ${PDP18B} ${SIM} ${PDP7_OPT} $(CC_OUTSPEC) ${LDFLAGS} - -pdp8 : ${BIN}pdp8${EXE} - -${BIN}pdp8${EXE} : ${PDP8} ${SIM} - ${MKDIRBIN} - ${CC} ${PDP8} ${SIM} ${PDP8_OPT} $(CC_OUTSPEC) ${LDFLAGS} - -pdp9 : ${BIN}pdp9${EXE} - -${BIN}pdp9${EXE} : ${PDP18B} ${SIM} - ${MKDIRBIN} - ${CC} ${PDP18B} ${SIM} ${PDP9_OPT} $(CC_OUTSPEC) ${LDFLAGS} - -pdp15 : ${BIN}pdp15${EXE} - -${BIN}pdp15${EXE} : ${PDP18B} ${SIM} - ${MKDIRBIN} - ${CC} ${PDP18B} ${SIM} ${PDP15_OPT} $(CC_OUTSPEC) ${LDFLAGS} - -pdp10 : ${BIN}pdp10${EXE} - -${BIN}pdp10${EXE} : ${PDP10} ${SIM} - ${MKDIRBIN} - ${CC} ${PDP10} ${SIM} ${PDP10_OPT} $(CC_OUTSPEC) ${LDFLAGS} - -pdp11 : ${BIN}pdp11${EXE} - -${BIN}pdp11${EXE} : ${PDP11} ${SIM} - ${MKDIRBIN} - ${CC} ${PDP11} ${SIM} ${PDP11_OPT} $(CC_OUTSPEC) ${LDFLAGS} - -vax : microvax3900 - -microvax3900 : ${BIN}microvax3900${EXE} - -${BIN}microvax3900${EXE} : ${VAX} ${SIM} ${BUILD_ROMS} - ${MKDIRBIN} - ${CC} ${VAX} ${SIM} ${VAX_OPT} $(CC_OUTSPEC) ${LDFLAGS} -ifeq ($(WIN32),) - cp ${BIN}microvax3900${EXE} ${BIN}vax${EXE} -else - copy $(@D)\microvax3900${EXE} $(@D)\vax${EXE} -endif - -microvax1 : ${BIN}microvax1${EXE} - -${BIN}microvax1${EXE} : ${VAX610} ${SIM} ${BUILD_ROMS} - ${MKDIRBIN} - ${CC} ${VAX610} ${SIM} ${VAX610_OPT} -o $@ ${LDFLAGS} - -rtvax1000 : ${BIN}rtvax1000${EXE} - -${BIN}rtvax1000${EXE} : ${VAX630} ${SIM} ${BUILD_ROMS} - ${MKDIRBIN} - ${CC} ${VAX630} ${SIM} ${VAX620_OPT} -o $@ ${LDFLAGS} - -microvax2 : ${BIN}microvax2${EXE} - -${BIN}microvax2${EXE} : ${VAX630} ${SIM} ${BUILD_ROMS} - ${MKDIRBIN} - ${CC} ${VAX630} ${SIM} ${VAX630_OPT} -o $@ ${LDFLAGS} - -vax730 : ${BIN}vax730${EXE} - -${BIN}vax730${EXE} : ${VAX730} ${SIM} ${BUILD_ROMS} - ${MKDIRBIN} - ${CC} ${VAX730} ${SIM} ${VAX730_OPT} -o $@ ${LDFLAGS} - -vax750 : ${BIN}vax750${EXE} - -${BIN}vax750${EXE} : ${VAX750} ${SIM} ${BUILD_ROMS} - ${MKDIRBIN} - ${CC} ${VAX750} ${SIM} ${VAX750_OPT} -o $@ ${LDFLAGS} - -vax780 : ${BIN}vax780${EXE} - -${BIN}vax780${EXE} : ${VAX780} ${SIM} ${BUILD_ROMS} - ${MKDIRBIN} - ${CC} ${VAX780} ${SIM} ${VAX780_OPT} $(CC_OUTSPEC) ${LDFLAGS} - -vax8600 : ${BIN}vax8600${EXE} - -${BIN}vax8600${EXE} : ${VAX8600} ${SIM} ${BUILD_ROMS} - ${MKDIRBIN} - ${CC} ${VAX8600} ${SIM} ${VAX8600_OPT} $(CC_OUTSPEC) ${LDFLAGS} - -nova : ${BIN}nova${EXE} - -${BIN}nova${EXE} : ${NOVA} ${SIM} - ${MKDIRBIN} - ${CC} ${NOVA} ${SIM} ${NOVA_OPT} $(CC_OUTSPEC) ${LDFLAGS} - -eclipse : ${BIN}eclipse${EXE} - -${BIN}eclipse${EXE} : ${ECLIPSE} ${SIM} - ${MKDIRBIN} - ${CC} ${ECLIPSE} ${SIM} ${ECLIPSE_OPT} $(CC_OUTSPEC) ${LDFLAGS} - -h316 : ${BIN}h316${EXE} - -${BIN}h316${EXE} : ${H316} ${SIM} - ${MKDIRBIN} - ${CC} ${H316} ${SIM} ${H316_OPT} $(CC_OUTSPEC) ${LDFLAGS} - -hp2100 : ${BIN}hp2100${EXE} - -${BIN}hp2100${EXE} : ${HP2100} ${SIM} - ${MKDIRBIN} - ${CC} ${HP2100} ${SIM} ${HP2100_OPT} $(CC_OUTSPEC) ${LDFLAGS} - -i1401 : ${BIN}i1401${EXE} - -${BIN}i1401${EXE} : ${I1401} ${SIM} - ${MKDIRBIN} - ${CC} ${I1401} ${SIM} ${I1401_OPT} $(CC_OUTSPEC) ${LDFLAGS} - -i1620 : ${BIN}i1620${EXE} - -${BIN}i1620${EXE} : ${I1620} ${SIM} - ${MKDIRBIN} - ${CC} ${I1620} ${SIM} ${I1620_OPT} $(CC_OUTSPEC) ${LDFLAGS} - -i7094 : ${BIN}i7094${EXE} - -${BIN}i7094${EXE} : ${I7094} ${SIM} - ${MKDIRBIN} - ${CC} ${I7094} ${SIM} ${I7094_OPT} $(CC_OUTSPEC) ${LDFLAGS} - -ibm1130 : ${BIN}ibm1130${EXE} - -${BIN}ibm1130${EXE} : ${IBM1130} - ${MKDIRBIN} -ifneq ($(WIN32),) - windres ${IBM1130D}/ibm1130.rc $(BIN)ibm1130.o - ${CC} ${IBM1130} ${SIM} ${IBM1130_OPT} $(BIN)ibm1130.o $(CC_OUTSPEC) ${LDFLAGS} - del BIN\ibm1130.o -else - ${CC} ${IBM1130} ${SIM} ${IBM1130_OPT} $(CC_OUTSPEC) ${LDFLAGS} -endif - -s3 : ${BIN}s3${EXE} - -${BIN}s3${EXE} : ${S3} ${SIM} - ${MKDIRBIN} - ${CC} ${S3} ${SIM} ${S3_OPT} $(CC_OUTSPEC) ${LDFLAGS} - -altair : ${BIN}altair${EXE} - -${BIN}altair${EXE} : ${ALTAIR} ${SIM} - ${MKDIRBIN} - ${CC} ${ALTAIR} ${SIM} ${ALTAIR_OPT} $(CC_OUTSPEC) ${LDFLAGS} - -altairz80 : ${BIN}altairz80${EXE} - -${BIN}altairz80${EXE} : ${ALTAIRZ80} ${SIM} - ${MKDIRBIN} - ${CC} ${ALTAIRZ80} ${SIM} ${ALTAIRZ80_OPT} $(CC_OUTSPEC) ${LDFLAGS} - -gri : ${BIN}gri${EXE} - -${BIN}gri${EXE} : ${GRI} ${SIM} - ${MKDIRBIN} - ${CC} ${GRI} ${SIM} ${GRI_OPT} $(CC_OUTSPEC) ${LDFLAGS} - -lgp : ${BIN}lgp${EXE} - -${BIN}lgp${EXE} : ${LGP} ${SIM} - ${MKDIRBIN} - ${CC} ${LGP} ${SIM} ${LGP_OPT} $(CC_OUTSPEC) ${LDFLAGS} - -id16 : ${BIN}id16${EXE} - -${BIN}id16${EXE} : ${ID16} ${SIM} - ${MKDIRBIN} - ${CC} ${ID16} ${SIM} ${ID16_OPT} $(CC_OUTSPEC) ${LDFLAGS} - -id32 : ${BIN}id32${EXE} - -${BIN}id32${EXE} : ${ID32} ${SIM} - ${MKDIRBIN} - ${CC} ${ID32} ${SIM} ${ID32_OPT} $(CC_OUTSPEC) ${LDFLAGS} - -sds : ${BIN}sds${EXE} - -${BIN}sds${EXE} : ${SDS} ${SIM} - ${MKDIRBIN} - ${CC} ${SDS} ${SIM} ${SDS_OPT} $(CC_OUTSPEC) ${LDFLAGS} - -swtp6800mp-a : ${BIN}swtp6800mp-a${EXE} - -${BIN}swtp6800mp-a${EXE} : ${SWTP6800MP-A} ${SIM} ${BUILD_ROMS} - ${MKDIRBIN} - ${CC} ${SWTP6800MP-A} ${SIM} ${SWTP6800_OPT} $(CC_OUTSPEC) ${LDFLAGS} - -swtp6800mp-a2 : ${BIN}swtp6800mp-a2${EXE} - -${BIN}swtp6800mp-a2${EXE} : ${SWTP6800MP-A2} ${SIM} ${BUILD_ROMS} - ${MKDIRBIN} - ${CC} ${SWTP6800MP-A2} ${SIM} ${SWTP6800_OPT} $(CC_OUTSPEC) ${LDFLAGS} - -tx-0 : ${BIN}tx-0${EXE} - -${BIN}tx-0${EXE} : ${TX0} ${SIM} - ${MKDIRBIN} - ${CC} ${TX0} ${SIM} ${TX0_OPT} $(CC_OUTSPEC) ${LDFLAGS} - -ssem : ${BIN}ssem${EXE} - -${BIN}ssem${EXE} : ${SSEM} ${SIM} - ${MKDIRBIN} - ${CC} ${SSEM} ${SIM} ${SSEM_OPT} $(CC_OUTSPEC) ${LDFLAGS} - diff --git a/build_billi.bat b/build_billi.bat new file mode 100644 index 00000000..52932314 --- /dev/null +++ b/build_billi.bat @@ -0,0 +1,5 @@ +@echo off +rem Build Intel Systems +call build_mingw.bat isys8010 +pause + diff --git a/build_billm.bat b/build_billm.bat new file mode 100644 index 00000000..cd26e8ce --- /dev/null +++ b/build_billm.bat @@ -0,0 +1,5 @@ +@echo off +rem Build swtp6800 systems +call build_mingw.bat swtp6800mp-a swtp6800mp-a2 +pause + diff --git a/MDS-800/common/i8008.c b/isys8010/common/i8008.c similarity index 100% rename from MDS-800/common/i8008.c rename to isys8010/common/i8008.c diff --git a/MDS-800/common/i8080.c b/isys8010/common/i8080.c similarity index 74% rename from MDS-800/common/i8080.c rename to isys8010/common/i8080.c index 890fbc6a..5386b897 100644 --- a/MDS-800/common/i8080.c +++ b/isys8010/common/i8080.c @@ -661,250 +661,250 @@ int32 sim_instr (void) switch (IR) { /* 8085 instructions only */ - case 0x20: /* RIM */ - if (i8080_unit.flags & UNIT_8085) { /* 8085 */ - A = IM; - } else { /* 8080 */ - reason = STOP_OPCODE; - PC--; - } - break; - - case 0x30: /* SIM */ - if (i8080_unit.flags & UNIT_8085) { /* 8085 */ - if (A & MSE) { - IM &= 0xF8; - IM |= A & 0x07; - } - if (A & I75) { /* reset RST 7.5 FF */ - } - } else { /* 8080 */ - reason = STOP_OPCODE; - PC--; - } - break; - - /* Logical instructions */ - - case 0xFE: /* CPI */ - DAR = A; - DAR -= fetch_byte(1); -// DAR &= BYTE_R; - setarith(DAR); - break; - - case 0xE6: /* ANI */ - A &= fetch_byte(1); - setlogical(A); - break; - - case 0xEE: /* XRI */ - A ^= fetch_byte(1); -// DAR &= BYTE_R; - setlogical(A); - break; - - case 0xF6: /* ORI */ - A |= fetch_byte(1); - setlogical(A); - break; - - /* Jump instructions */ - - case 0xC3: /* JMP */ - PC = fetch_word(); - break; - - case 0xE9: /* PCHL */ - PC = HL; - break; - - case 0xCD: /* CALL */ - adr = fetch_word(); - push_word(PC); - PC = adr; - break; - - case 0xC9: /* RET */ - PC = pop_word(); - break; - - /* Data Transfer Group */ - - case 0x32: /* STA */ - DAR = fetch_word(); - DAR &= WORD_R; - put_mbyte(DAR, A); - break; - - case 0x3A: /* LDA */ - DAR = fetch_word(); - DAR &= WORD_R; - A = get_mbyte(DAR); - break; - - case 0x22: /* SHLD */ - DAR = fetch_word(); - DAR &= WORD_R; - put_mword(DAR, HL); - break; - - case 0x2A: /* LHLD */ - DAR = fetch_word(); - DAR &= WORD_R; - HL = get_mword(DAR); - break; - - case 0xEB: /* XCHG */ - DAR = HL; - HL = DE; - HL &= WORD_R; - DE = DAR; - DE &= WORD_R; - break; - - /* Arithmetic Group */ - - case 0xC6: /* ADI */ - A += fetch_byte(1); - setarith(A); - A &= BYTE_R; - break; - - case 0xCE: /* ACI */ - A += fetch_byte(1); - if (GET_FLAG(CF)) - A++; - setarith(A); - A &= BYTE_R; - break; - - case 0xD6: /* SUI */ - A -= fetch_byte(1); - setarith(A); - A &= BYTE_R; - break; - - case 0xDE: /* SBI */ - A -= fetch_byte(1); - if (GET_FLAG(CF)) - A--; - setarith(A); - A &= BYTE_R; - break; - - case 0x27: /* DAA */ - DAR = A & 0x0F; - if (DAR > 9 || GET_FLAG(AF)) { - DAR += 6; - A &= 0xF0; - A |= DAR & 0x0F; - COND_SET_FLAG(DAR & 0x10, AF); - } - DAR = (A >> 4) & 0x0F; - if (DAR > 9 || GET_FLAG(AF)) { - DAR += 6; - if (GET_FLAG(AF)) DAR++; - A &= 0x0F; - A |= (DAR << 4); - } - COND_SET_FLAG(DAR & 0x10, CF); - COND_SET_FLAG(A & 0x80, SF); - COND_SET_FLAG((A & 0xFF) == 0, ZF); - parity(A); - break; - - case 0x07: /* RLC */ - COND_SET_FLAG(A & 0x80, CF); - A = (A << 1) & 0xFF; - if (GET_FLAG(CF)) - A |= 0x01; - A &= BYTE_R; - break; - - case 0x0F: /* RRC */ - COND_SET_FLAG(A & 0x01, CF); - A = (A >> 1) & 0xFF; - if (GET_FLAG(CF)) - A |= 0x80; - A &= BYTE_R; - break; - - case 0x17: /* RAL */ - DAR = GET_FLAG(CF); - COND_SET_FLAG(A & 0x80, CF); - A = (A << 1) & 0xFF; - if (DAR) - A |= 0x01; - A &= BYTE_R; - break; - - case 0x1F: /* RAR */ - DAR = GET_FLAG(CF); - COND_SET_FLAG(A & 0x01, CF); - A = (A >> 1) & 0xFF; - if (DAR) - A |= 0x80; - A &= BYTE_R; - break; - - case 0x2F: /* CMA */ - A = ~A; - A &= BYTE_R; - break; - - case 0x3F: /* CMC */ - TOGGLE_FLAG(CF); - break; - - case 0x37: /* STC */ - SET_FLAG(CF); - break; - - /* Stack, I/O & Machine Control Group */ - - case 0x00: /* NOP */ - break; - - case 0xE3: /* XTHL */ - DAR = pop_word(); - push_word(HL); - HL = DAR; - HL &= WORD_R; - break; - - case 0xF9: /* SPHL */ - SP = HL; - break; - - case 0xFB: /* EI */ - IM |= IE; -// printf("\nEI: pc=%04X", PC - 1); - break; - - case 0xF3: /* DI */ - IM &= ~IE; -// printf("\nDI: pc=%04X", PC - 1); - break; - - case 0xDB: /* IN */ - DAR = fetch_byte(1); - A = dev_table[DAR].routine(0, 0); - A &= BYTE_R; - break; - - case 0xD3: /* OUT */ - DAR = fetch_byte(1); - dev_table[DAR].routine(1, A); - break; - - default: /* undefined opcode */ - if (i8080_unit.flags & UNIT_OPSTOP) { - reason = STOP_OPCODE; - PC--; - } - break; + case 0x20: /* RIM */ + if (i8080_unit.flags & UNIT_8085) { /* 8085 */ + A = IM; + } else { /* 8080 */ + reason = STOP_OPCODE; + PC--; } + break; + + case 0x30: /* SIM */ + if (i8080_unit.flags & UNIT_8085) { /* 8085 */ + if (A & MSE) { + IM &= 0xF8; + IM |= A & 0x07; + } + if (A & I75) { /* reset RST 7.5 FF */ + } + } else { /* 8080 */ + reason = STOP_OPCODE; + PC--; + } + break; + + /* Logical instructions */ + + case 0xFE: /* CPI */ + DAR = A; + DAR -= fetch_byte(1); +// DAR &= BYTE_R; + setarith(DAR); + break; + + case 0xE6: /* ANI */ + A &= fetch_byte(1); + setlogical(A); + break; + + case 0xEE: /* XRI */ + A ^= fetch_byte(1); +// DAR &= BYTE_R; + setlogical(A); + break; + + case 0xF6: /* ORI */ + A |= fetch_byte(1); + setlogical(A); + break; + + /* Jump instructions */ + + case 0xC3: /* JMP */ + PC = fetch_word(); + break; + + case 0xE9: /* PCHL */ + PC = HL; + break; + + case 0xCD: /* CALL */ + adr = fetch_word(); + push_word(PC); + PC = adr; + break; + + case 0xC9: /* RET */ + PC = pop_word(); + break; + + /* Data Transfer Group */ + + case 0x32: /* STA */ + DAR = fetch_word(); + DAR &= WORD_R; + put_mbyte(DAR, A); + break; + + case 0x3A: /* LDA */ + DAR = fetch_word(); + DAR &= WORD_R; + A = get_mbyte(DAR); + break; + + case 0x22: /* SHLD */ + DAR = fetch_word(); + DAR &= WORD_R; + put_mword(DAR, HL); + break; + + case 0x2A: /* LHLD */ + DAR = fetch_word(); + DAR &= WORD_R; + HL = get_mword(DAR); + break; + + case 0xEB: /* XCHG */ + DAR = HL; + HL = DE; + HL &= WORD_R; + DE = DAR; + DE &= WORD_R; + break; + + /* Arithmetic Group */ + + case 0xC6: /* ADI */ + A += fetch_byte(1); + setarith(A); + A &= BYTE_R; + break; + + case 0xCE: /* ACI */ + A += fetch_byte(1); + if (GET_FLAG(CF)) + A++; + setarith(A); + A &= BYTE_R; + break; + + case 0xD6: /* SUI */ + A -= fetch_byte(1); + setarith(A); + A &= BYTE_R; + break; + + case 0xDE: /* SBI */ + A -= fetch_byte(1); + if (GET_FLAG(CF)) + A--; + setarith(A); + A &= BYTE_R; + break; + + case 0x27: /* DAA */ + DAR = A & 0x0F; + if (DAR > 9 || GET_FLAG(AF)) { + DAR += 6; + A &= 0xF0; + A |= DAR & 0x0F; + COND_SET_FLAG(DAR & 0x10, AF); + } + DAR = (A >> 4) & 0x0F; + if (DAR > 9 || GET_FLAG(AF)) { + DAR += 6; + if (GET_FLAG(AF)) DAR++; + A &= 0x0F; + A |= (DAR << 4); + } + COND_SET_FLAG(DAR & 0x10, CF); + COND_SET_FLAG(A & 0x80, SF); + COND_SET_FLAG((A & 0xFF) == 0, ZF); + parity(A); + break; + + case 0x07: /* RLC */ + COND_SET_FLAG(A & 0x80, CF); + A = (A << 1) & 0xFF; + if (GET_FLAG(CF)) + A |= 0x01; + A &= BYTE_R; + break; + + case 0x0F: /* RRC */ + COND_SET_FLAG(A & 0x01, CF); + A = (A >> 1) & 0xFF; + if (GET_FLAG(CF)) + A |= 0x80; + A &= BYTE_R; + break; + + case 0x17: /* RAL */ + DAR = GET_FLAG(CF); + COND_SET_FLAG(A & 0x80, CF); + A = (A << 1) & 0xFF; + if (DAR) + A |= 0x01; + A &= BYTE_R; + break; + + case 0x1F: /* RAR */ + DAR = GET_FLAG(CF); + COND_SET_FLAG(A & 0x01, CF); + A = (A >> 1) & 0xFF; + if (DAR) + A |= 0x80; + A &= BYTE_R; + break; + + case 0x2F: /* CMA */ + A = ~A; + A &= BYTE_R; + break; + + case 0x3F: /* CMC */ + TOGGLE_FLAG(CF); + break; + + case 0x37: /* STC */ + SET_FLAG(CF); + break; + + /* Stack, I/O & Machine Control Group */ + + case 0x00: /* NOP */ + break; + + case 0xE3: /* XTHL */ + DAR = pop_word(); + push_word(HL); + HL = DAR; + HL &= WORD_R; + break; + + case 0xF9: /* SPHL */ + SP = HL; + break; + + case 0xFB: /* EI */ + IM |= IE; +// printf("\nEI: pc=%04X", PC - 1); + break; + + case 0xF3: /* DI */ + IM &= ~IE; +// printf("\nDI: pc=%04X", PC - 1); + break; + + case 0xDB: /* IN */ + DAR = fetch_byte(1); + A = dev_table[DAR].routine(0, 0); + A &= BYTE_R; + break; + + case 0xD3: /* OUT */ + DAR = fetch_byte(1); + dev_table[DAR].routine(1, A); + break; + + default: /* undefined opcode */ + if (i8080_unit.flags & UNIT_OPSTOP) { + reason = STOP_OPCODE; + PC--; + } + break; + } loop_end: if (GET_XACK(1) == 0) { /* no XACK for instruction fetch */ reason = STOP_XACK; @@ -941,12 +941,12 @@ int32 fetch_byte(int32 flag) val = get_mbyte(PC) & 0xFF; /* fetch byte */ if (i8080_dev.dctrl & DEBUG_asm || uptr->flags & UNIT_TRACE) { /* display source code */ switch (flag) { - case 0: /* opcode fetch */ - printf("OP=%02X %04X %s", val, PC, opcode[val]); - break; - case 1: /* byte operand fetch */ - printf("0%02XH", val); - break; + case 0: /* opcode fetch */ + printf("OP=%02X %04X %s", val, PC, opcode[val]); + break; + case 1: /* byte operand fetch */ + printf("0%02XH", val); + break; } } PC = (PC + 1) & ADDRMASK; /* increment PC */ @@ -993,32 +993,32 @@ uint16 pop_word(void) int32 cond(int32 con) { switch (con) { - case 0: /* NZ */ - if (GET_FLAG(ZF) == 0) return 1; - break; - case 1: /* Z */ - if (GET_FLAG(ZF)) return 1; - break; - case 2: /* NC */ - if (GET_FLAG(CF) == 0) return 1; - break; - case 3: /* C */ - if (GET_FLAG(CF)) return 1; - break; - case 4: /* PO */ - if (GET_FLAG(PF) == 0) return 1; - break; - case 5: /* PE */ - if (GET_FLAG(PF)) return 1; - break; - case 6: /* P */ - if (GET_FLAG(SF) == 0) return 1; - break; - case 7: /* M */ - if (GET_FLAG(SF)) return 1; - break; - default: - break; + case 0: /* NZ */ + if (GET_FLAG(ZF) == 0) return 1; + break; + case 1: /* Z */ + if (GET_FLAG(ZF)) return 1; + break; + case 2: /* NC */ + if (GET_FLAG(CF) == 0) return 1; + break; + case 3: /* C */ + if (GET_FLAG(CF)) return 1; + break; + case 4: /* PO */ + if (GET_FLAG(PF) == 0) return 1; + break; + case 5: /* PE */ + if (GET_FLAG(PF)) return 1; + break; + case 6: /* P */ + if (GET_FLAG(SF) == 0) return 1; + break; + case 7: /* M */ + if (GET_FLAG(SF)) return 1; + break; + default: + break; } return 0; } @@ -1086,26 +1086,26 @@ void setinc(int32 reg) int32 getreg(int32 reg) { switch (reg) { - case 0: /* reg B */ - // printf("reg=%04X BC=%04X ret=%04X\n", - // reg, BC, (BC >>8) & 0xff); - return ((BC >>8) & BYTE_R); - case 1: /* reg C */ - return (BC & BYTE_R); - case 2: /* reg D */ - return ((DE >>8) & BYTE_R); - case 3: /* reg E */ - return (DE & BYTE_R); - case 4: /* reg H */ - return ((HL >>8) & BYTE_R); - case 5: /* reg L */ - return (HL & BYTE_R); - case 6: /* reg M */ - return (get_mbyte(HL)); - case 7: /* reg A */ - return (A); - default: - break; + case 0: /* reg B */ +// printf("reg=%04X BC=%04X ret=%04X\n", +// reg, BC, (BC >>8) & 0xff); + return ((BC >>8) & BYTE_R); + case 1: /* reg C */ + return (BC & BYTE_R); + case 2: /* reg D */ + return ((DE >>8) & BYTE_R); + case 3: /* reg E */ + return (DE & BYTE_R); + case 4: /* reg H */ + return ((HL >>8) & BYTE_R); + case 5: /* reg L */ + return (HL & BYTE_R); + case 6: /* reg M */ + return (get_mbyte(HL)); + case 7: /* reg A */ + return (A); + default: + break; } return 0; } @@ -1114,39 +1114,39 @@ int32 getreg(int32 reg) void putreg(int32 reg, int32 val) { switch (reg) { - case 0: /* reg B */ + case 0: /* reg B */ // printf("reg=%04X val=%04X\n", reg, val); - BC = BC & BYTE_R; + BC = BC & BYTE_R; // printf("BC&0x00ff=%04X val<<8=%04X\n", BC, val<<8); - BC = BC | (val <<8); - break; - case 1: /* reg C */ - BC = BC & 0xFF00; - BC = BC | val; - break; - case 2: /* reg D */ - DE = DE & BYTE_R; - DE = DE | (val <<8); - break; - case 3: /* reg E */ - DE = DE & 0xFF00; - DE = DE | val; - break; - case 4: /* reg H */ - HL = HL & BYTE_R; - HL = HL | (val <<8); - break; - case 5: /* reg L */ - HL = HL & 0xFF00; - HL = HL | val; - break; - case 6: /* reg M */ - put_mbyte(HL, val); - break; - case 7: /* reg A */ - A = val & BYTE_R; - default: - break; + BC = BC | (val <<8); + break; + case 1: /* reg C */ + BC = BC & 0xFF00; + BC = BC | val; + break; + case 2: /* reg D */ + DE = DE & BYTE_R; + DE = DE | (val <<8); + break; + case 3: /* reg E */ + DE = DE & 0xFF00; + DE = DE | val; + break; + case 4: /* reg H */ + HL = HL & BYTE_R; + HL = HL | (val <<8); + break; + case 5: /* reg L */ + HL = HL & 0xFF00; + HL = HL | val; + break; + case 6: /* reg M */ + put_mbyte(HL, val); + break; + case 7: /* reg A */ + A = val & BYTE_R; + default: + break; } } @@ -1154,16 +1154,16 @@ void putreg(int32 reg, int32 val) int32 getpair(int32 reg) { switch (reg) { - case 0: /* reg BC */ - return (BC); - case 1: /* reg DE */ - return (DE); - case 2: /* reg HL */ - return (HL); - case 3: /* reg SP */ - return (SP); - default: - break; + case 0: /* reg BC */ + return (BC); + case 1: /* reg DE */ + return (DE); + case 2: /* reg HL */ + return (HL); + case 3: /* reg SP */ + return (SP); + default: + break; } return 0; } @@ -1175,17 +1175,17 @@ int32 getpush(int32 reg) int32 stat; switch (reg) { - case 0: /* reg BC */ - return (BC); - case 1: /* reg DE */ - return (DE); - case 2: /* reg HL */ - return (HL); - case 3: /* reg (A << 8) | PSW */ - stat = A << 8 | PSW; - return (stat); - default: - break; + case 0: /* reg BC */ + return (BC); + case 1: /* reg DE */ + return (DE); + case 2: /* reg HL */ + return (HL); + case 3: /* reg (A << 8) | PSW */ + stat = A << 8 | PSW; + return (stat); + default: + break; } return 0; } @@ -1196,21 +1196,21 @@ int32 getpush(int32 reg) void putpush(int32 reg, int32 data) { switch (reg) { - case 0: /* reg BC */ - BC = data; - break; - case 1: /* reg DE */ - DE = data; - break; - case 2: /* reg HL */ - HL = data; - break; - case 3: /* reg (A << 8) | PSW */ - A = (data >> 8) & BYTE_R; - PSW = data & BYTE_R; - break; - default: - break; + case 0: /* reg BC */ + BC = data; + break; + case 1: /* reg DE */ + DE = data; + break; + case 2: /* reg HL */ + HL = data; + break; + case 3: /* reg (A << 8) | PSW */ + A = (data >> 8) & BYTE_R; + PSW = data & BYTE_R; + break; + default: + break; } } @@ -1219,20 +1219,20 @@ void putpush(int32 reg, int32 data) void putpair(int32 reg, int32 val) { switch (reg) { - case 0: /* reg BC */ - BC = val; - break; - case 1: /* reg DE */ - DE = val; - break; - case 2: /* reg HL */ - HL = val; - break; - case 3: /* reg SP */ - SP = val; - break; - default: - break; + case 0: /* reg BC */ + BC = val; + break; + case 1: /* reg DE */ + DE = val; + break; + case 2: /* reg HL */ + HL = val; + break; + case 3: /* reg SP */ + SP = val; + break; + default: + break; } } diff --git a/MDS-800/common/i8088.c b/isys8010/common/i8088.c similarity index 100% rename from MDS-800/common/i8088.c rename to isys8010/common/i8088.c diff --git a/isys8010/common/i8251.c b/isys8010/common/i8251.c new file mode 100644 index 00000000..5298fd77 --- /dev/null +++ b/isys8010/common/i8251.c @@ -0,0 +1,257 @@ +/* i8251.c: Intel i8251 UART adapter + + Copyright (c) 2010, William A. Beech + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + WILLIAM A. BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name of William A. Beech shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from William A. Beech. + + MODIFICATIONS: + + ?? ??? 10 - Original file. + 16 Dec 12 - Modified to use isbc_80_10.cfg file to set base and size. + 24 Apr 15 -- Modified to use simh_debug + + NOTES: + + These functions support a simulated i8251 interface device on an iSBC. + The device had one physical I/O port which could be connected + to any serial I/O device that would connect to a current loop, + RS232, or TTY interface. Available baud rates were jumper + selectable for each port from 110 to 9600. + + All I/O is via programmed I/O. The i8251 has a status port + and a data port. + + The simulated device does not support synchronous mode. The simulated device + supports a select from I/O space and one address line. The data port is at the + lower address and the status/command port is at the higher. + + A write to the status port can select some options for the device: + + Asynchronous Mode Instruction + 7 6 5 4 3 2 1 0 + +---+---+---+---+---+---+---+---+ + | S2 S1 EP PEN L2 L1 B2 B1| + +---+---+---+---+---+---+---+---+ + + Baud Rate Factor + B2 0 1 0 1 + B1 0 0 1 1 + sync 1X 16X 64X + mode + + Character Length + L2 0 1 0 1 + L1 0 0 1 1 + 5 6 7 8 + bits bits bits bits + + EP - A 1 in this bit position selects even parity. + PEN - A 1 in this bit position enables parity. + + Number of Stop Bits + S2 0 1 0 1 + S1 0 0 1 1 + invalid 1 1.5 2 + bit bits bits + + Command Instruction Format + 7 6 5 4 3 2 1 0 + +---+---+---+---+---+---+---+---+ + | EH IR RTS ER SBRK RxE DTR TxE| + +---+---+---+---+---+---+---+---+ + + TxE - A 1 in this bit position enables transmit. + DTR - A 1 in this bit position forces *DTR to zero. + RxE - A 1 in this bit position enables receive. + SBRK - A 1 in this bit position forces TxD to zero. + ER - A 1 in this bit position resets the error bits + RTS - A 1 in this bit position forces *RTS to zero. + IR - A 1 in this bit position returns the 8251 to Mode Instruction Format. + EH - A 1 in this bit position enables search for sync characters. + + A read of the status port gets the port status: + + Status Read Format + 7 6 5 4 3 2 1 0 + +---+---+---+---+---+---+---+---+ + |DSR SD FE OE PE TxE RxR TxR| + +---+---+---+---+---+---+---+---+ + + TxR - A 1 in this bit position signals transmit ready to receive a character. + RxR - A 1 in this bit position signals receiver has a character. + TxE - A 1 in this bit position signals transmitter has no more characters to transmit. + PE - A 1 in this bit signals a parity error. + OE - A 1 in this bit signals an transmit overrun error. + FE - A 1 in this bit signals a framing error. + SD - A 1 in this bit position returns the 8251 to Mode Instruction Format. + DSR - A 1 in this bit position signals *DSR is at zero. + + A read from the data port gets the typed character, a write + to the data port writes the character to the device. +*/ + +#include "system_defs.h" + +#define UNIT_V_ANSI (UNIT_V_UF + 0) /* ANSI mode */ +#define UNIT_ANSI (1 << UNIT_V_ANSI) + +#define TXR 0x01 +#define RXR 0x02 +#define TXE 0x04 +#define SD 0x40 + +extern int32 reg_dev(int32 (*routine)(), int32 port); + +/* function prototypes */ + +t_stat i8251_svc (UNIT *uptr); +t_stat i8251_reset (DEVICE *dptr, int32 base); +int32 i8251s(int32 io, int32 data); +int32 i8251d(int32 io, int32 data); +void i8251_reset1(void); +/* i8251 Standard I/O Data Structures */ + +UNIT i8251_unit = { + UDATA (&i8251_svc, 0, 0), KBD_POLL_WAIT +}; + +REG i8251_reg[] = { + { HRDATA (DATA, i8251_unit.buf, 8) }, + { HRDATA (STAT, i8251_unit.u3, 8) }, + { HRDATA (MODE, i8251_unit.u4, 8) }, + { HRDATA (CMD, i8251_unit.u5, 8) }, + { NULL } +}; + +MTAB i8251_mod[] = { + { UNIT_ANSI, 0, "TTY", "TTY", NULL }, + { UNIT_ANSI, UNIT_ANSI, "ANSI", "ANSI", NULL }, + { 0 } +}; + +DEVICE i8251_dev = { + "8251", //name + &i8251_unit, //units + i8251_reg, //registers + i8251_mod, //modifiers + 1, //numunits + 10, //aradix + 31, //awidth + 1, //aincr + 16, //dradix + 8, //dwidth + NULL, //examine + NULL, //deposit +// &i8251_reset, //reset + NULL, //reset + NULL, //boot + NULL, //attach + NULL, //detach + NULL, //ctxt + 0, //flags + 0, //dctrl + NULL, //debflags + NULL, //msize + NULL //lname +}; + +/* Service routines to handle simulator functions */ + +/* i8251_svc - actually gets char & places in buffer */ + +t_stat i8251_svc (UNIT *uptr) +{ + int32 temp; + + sim_activate (&i8251_unit, i8251_unit.wait); /* continue poll */ + if ((temp = sim_poll_kbd ()) < SCPE_KFLAG) + return temp; /* no char or error? */ + i8251_unit.buf = temp & 0xFF; /* Save char */ + i8251_unit.u3 |= RXR; /* Set status */ + + /* Do any special character handling here */ + + i8251_unit.pos++; + return SCPE_OK; +} + +/* Reset routine */ + +t_stat i8251_reset (DEVICE *dptr, int32 base) +{ + reg_dev(i8251d, base); + reg_dev(i8251s, base + 1); + reg_dev(i8251d, base + 2); + reg_dev(i8251s, base + 3); + i8251_reset1(); + printf(" 8251: Registered at %02X\n", base); + sim_activate (&i8251_unit, i8251_unit.wait); /* activate unit */ + return SCPE_OK; +} + +/* I/O instruction handlers, called from the CPU module when an + IN or OUT instruction is issued. +*/ + +int32 i8251s(int32 io, int32 data) +{ +// printf("\nio=%d data=%04X\n", io, data); + if (io == 0) { /* read status port */ + return i8251_unit.u3; + } else { /* write status port */ + if (i8251_unit.u6) { /* if mode, set cmd */ + i8251_unit.u5 = data; + printf("8251: Command Instruction=%02X\n", data); + if (data & SD) /* reset port! */ + i8251_reset1(); + } else { /* set mode */ + i8251_unit.u4 = data; + printf("8251: Mode Instruction=%02X\n", data); + i8251_unit.u6 = 1; /* set cmd received */ + } + return (0); + } +} + +int32 i8251d(int32 io, int32 data) +{ + if (io == 0) { /* read data port */ + i8251_unit.u3 &= ~RXR; + return (i8251_unit.buf); + } else { /* write data port */ + sim_putchar(data); + } + return 0; +} + +void i8251_reset1(void) +{ + i8251_unit.u3 = TXR + TXE; /* status */ + i8251_unit.u4 = 0; /* mode instruction */ + i8251_unit.u5 = 0; /* command instruction */ + i8251_unit.u6 = 0; + i8251_unit.buf = 0; + i8251_unit.pos = 0; + printf(" 8251: Reset\n"); +} + +/* end of i8251.c */ diff --git a/MDS-800/common/i8255.c b/isys8010/common/i8255.c similarity index 67% rename from MDS-800/common/i8255.c rename to isys8010/common/i8255.c index b0b3e79b..32090368 100644 --- a/MDS-800/common/i8255.c +++ b/isys8010/common/i8255.c @@ -2,75 +2,81 @@ Copyright (c) 2010, William A. Beech - Permission is hereby granted, free of charge, to any person obtaining a - copy of this software and associated documentation files (the "Software"), - to deal in the Software without restriction, including without limitation - the rights to use, copy, modify, merge, publish, distribute, sublicense, - and/or sell copies of the Software, and to permit persons to whom the - Software is furnished to do so, subject to the following conditions: + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: - The above copyright notice and this permission notice shall be included in - all copies or substantial portions of the Software. + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - WILLIAM A. BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + WILLIAM A. BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - Except as contained in this notice, the name of William A. Beech shall not be - used in advertising or otherwise to promote the sale, use or other dealings - in this Software without prior written authorization from William A. Beech. + Except as contained in this notice, the name of William A. Beech shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from William A. Beech. - These functions support a simulated i8255 interface device on an iSBC. - The device has threee physical 8-bit I/O ports which could be connected - to any parallel I/O device. + MODIFICATIONS: - All I/O is via programmed I/O. The i8255 has a control port (PIOS) - and three data ports (PIOA, PIOB, and PIOC). + ?? ??? 10 - Original file. + 16 Dec 12 - Modified to use isbc_80_10.cfg file to set base and size. + 24 Apr 15 -- Modified to use simh_debug - The simulated device supports a select from I/O space and two address lines. - The data ports are at the lower addresses and the control port is at - the highest. - - A write to the control port can configure the device: + NOTES: - Control Word - +---+---+---+---+---+---+---+---+ - | D7 D6 D5 D4 D3 D2 D1 D0| - +---+---+---+---+---+---+---+---+ + These functions support a simulated i8255 interface device on an iSBC. + The device has threee physical 8-bit I/O ports which could be connected + to any parallel I/O device. - Group B - D0 Port C (lower) 1-Input, 0-Output - D1 Port B 1-Input, 0-Output - D2 Mode Selection 0-Mode 0, 1-Mode 1 - - Group A - D3 Port C (upper) 1-Input, 0-Output - D4 Port A 1-Input, 0-Output - D5-6 Mode Selection 00-Mode 0, 01-Mode 1, 1X-Mode 2 + All I/O is via programmed I/O. The i8255 has a control port (PIOS) + and three data ports (PIOA, PIOB, and PIOC). - D7 Mode Set Flag 1=Active, 0=Bit Set + The simulated device supports a select from I/O space and two address lines. + The data ports are at the lower addresses and the control port is at + the highest. + + A write to the control port can configure the device: - Mode 0 - Basic Input/Output - Mode 1 - Strobed Input/Output - Mode 2 - Bidirectional Bus + Control Word + +---+---+---+---+---+---+---+---+ + | D7 D6 D5 D4 D3 D2 D1 D0| + +---+---+---+---+---+---+---+---+ - Bit Set - D7=0, D3:1 select port C bit, D0 1=set, 0=reset + Group B + D0 Port C (lower) 1-Input, 0-Output + D1 Port B 1-Input, 0-Output + D2 Mode Selection 0-Mode 0, 1-Mode 1 + + Group A + D3 Port C (upper) 1-Input, 0-Output + D4 Port A 1-Input, 0-Output + D5-6 Mode Selection 00-Mode 0, 01-Mode 1, 1X-Mode 2 - A read to the data ports gets the current port value, a write - to the data ports writes the character to the device. + D7 Mode Set Flag 1=Active, 0=Bit Set - *** Need to modify so that multiple devices can be registered and - used. - - ?? ??? 10 - Original file. - 16 Dec 12 - Modified to use isbc_80_10.cfg file to set base and size. + Mode 0 - Basic Input/Output + Mode 1 - Strobed Input/Output + Mode 2 - Bidirectional Bus + + Bit Set - D7=0, D3:1 select port C bit, D0 1=set, 0=reset + + A read to the data ports gets the current port value, a write + to the data ports writes the character to the device. + + *** Need to modify so that multiple devices can be registered and + used. + */ -#include "system_defs.h" /* system header in system dir */ -#define i8255_DEV 4 /* number of devices */ +#include "system_defs.h" /* system header in system dir */ +#define i8255_DEV 4 /* number of devices */ /* function prototypes */ @@ -403,56 +409,56 @@ int32 i8255c3(int32 io, int32 data) t_stat i8255_reset (DEVICE *dptr, int32 base) { - switch (i8255_cnt) { - case 0: - reg_dev(i8255a0, base); - reg_dev(i8255b0, base + 1); - reg_dev(i8255c0, base + 2); - reg_dev(i8255s0, base + 3); - i8255_unit[0].u3 = 0x9B; /* control */ - i8255_unit[0].u4 = 0xFF; /* Port A */ - i8255_unit[0].u5 = 0xFF; /* Port B */ - i8255_unit[0].u6 = 0xFF; /* Port C */ - printf(" 8255-0: Reset\n"); - break; - case 1: - reg_dev(i8255a1, base); - reg_dev(i8255b1, base + 1); - reg_dev(i8255c1, base + 2); - reg_dev(i8255s1, base + 3); - i8255_unit[1].u3 = 0x9B; /* control */ - i8255_unit[1].u4 = 0xFF; /* Port A */ - i8255_unit[1].u5 = 0xFF; /* Port B */ - i8255_unit[1].u6 = 0xFF; /* Port C */ - printf(" 8255-1: Reset\n"); - break; - case 2: - reg_dev(i8255a2, base); - reg_dev(i8255b2, base + 1); - reg_dev(i8255c2, base + 2); - reg_dev(i8255s2, base + 3); - i8255_unit[2].u3 = 0x9B; /* control */ - i8255_unit[2].u4 = 0xFF; /* Port A */ - i8255_unit[2].u5 = 0xFF; /* Port B */ - i8255_unit[2].u6 = 0xFF; /* Port C */ - printf(" 8255-2: Reset\n"); - break; - case 3: - reg_dev(i8255a3, base); - reg_dev(i8255b3, base + 1); - reg_dev(i8255c3, base + 2); - reg_dev(i8255s3, base + 3); - i8255_unit[3].u3 = 0x9B; /* control */ - i8255_unit[3].u4 = 0xFF; /* Port A */ - i8255_unit[3].u5 = 0xFF; /* Port B */ - i8255_unit[3].u6 = 0xFF; /* Port C */ - printf(" 8255-3: Reset\n"); - break; - default: - printf(" 8255: Bad device\n"); - } + switch (i8255_cnt) { + case 0: + reg_dev(i8255a0, base); + reg_dev(i8255b0, base + 1); + reg_dev(i8255c0, base + 2); + reg_dev(i8255s0, base + 3); + i8255_unit[0].u3 = 0x9B; /* control */ + i8255_unit[0].u4 = 0xFF; /* Port A */ + i8255_unit[0].u5 = 0xFF; /* Port B */ + i8255_unit[0].u6 = 0xFF; /* Port C */ + printf(" 8255-0: Reset\n"); + break; + case 1: + reg_dev(i8255a1, base); + reg_dev(i8255b1, base + 1); + reg_dev(i8255c1, base + 2); + reg_dev(i8255s1, base + 3); + i8255_unit[1].u3 = 0x9B; /* control */ + i8255_unit[1].u4 = 0xFF; /* Port A */ + i8255_unit[1].u5 = 0xFF; /* Port B */ + i8255_unit[1].u6 = 0xFF; /* Port C */ + printf(" 8255-1: Reset\n"); + break; + case 2: + reg_dev(i8255a2, base); + reg_dev(i8255b2, base + 1); + reg_dev(i8255c2, base + 2); + reg_dev(i8255s2, base + 3); + i8255_unit[2].u3 = 0x9B; /* control */ + i8255_unit[2].u4 = 0xFF; /* Port A */ + i8255_unit[2].u5 = 0xFF; /* Port B */ + i8255_unit[2].u6 = 0xFF; /* Port C */ + printf(" 8255-2: Reset\n"); + break; + case 3: + reg_dev(i8255a3, base); + reg_dev(i8255b3, base + 1); + reg_dev(i8255c3, base + 2); + reg_dev(i8255s3, base + 3); + i8255_unit[3].u3 = 0x9B; /* control */ + i8255_unit[3].u4 = 0xFF; /* Port A */ + i8255_unit[3].u5 = 0xFF; /* Port B */ + i8255_unit[3].u6 = 0xFF; /* Port C */ + printf(" 8255-3: Reset\n"); + break; + default: + printf(" 8255: Bad device\n"); + } printf(" 8255-%d: Registered at %02X\n", i8255_cnt, base); - i8255_cnt++; + i8255_cnt++; return SCPE_OK; } diff --git a/MDS-800/common/i8259.c b/isys8010/common/i8259.c similarity index 100% rename from MDS-800/common/i8259.c rename to isys8010/common/i8259.c diff --git a/MDS-800/common/i8273.c b/isys8010/common/i8273.c similarity index 100% rename from MDS-800/common/i8273.c rename to isys8010/common/i8273.c diff --git a/MDS-800/common/i8274.c b/isys8010/common/i8274.c similarity index 100% rename from MDS-800/common/i8274.c rename to isys8010/common/i8274.c diff --git a/isys8010/common/iSBC80-10.c b/isys8010/common/iSBC80-10.c new file mode 100644 index 00000000..3bba9161 --- /dev/null +++ b/isys8010/common/iSBC80-10.c @@ -0,0 +1,148 @@ +/* iSBC80-10.c: Intel iSBC 80/10 Processor simulator + + Copyright (c) 2010, William A. Beech + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + WILLIAM A. BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name of William A. Beech shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from William A. Beech. + + MODIFICATIONS: + + ?? ??? 10 - Original file. + 24 Apr 15 -- Modified to use simh_debug + + NOTES: + + This software was written by Bill Beech, Dec 2010, to allow emulation of Multibus + Computer Systems. +*/ + +#include "system_defs.h" + +/* set the base I/O address for the first 8255 */ +#define I8255_BASE_0 0xE4 + +/* set the base I/O address for the second 8255 */ +#define I8255_BASE_1 0xE8 + +/* set the base I/O address for the 8251 */ +#define I8251_BASE 0xEC + +/* set the base and size for the EPROM on the iSBC 80/10 */ +#define ROM_SIZE 0x1000 + +/* set the base and size for the RAM on the iSBC 80/10 */ +#define RAM_BASE 0x3C00 +#define RAM_SIZE 0x0400 + +/* set INTR for CPU */ +#define INTR INT_1 + +/* function prototypes */ + +int32 get_mbyte(int32 addr); +int32 get_mword(int32 addr); +void put_mbyte(int32 addr, int32 val); +void put_mword(int32 addr, int32 val); +t_stat SBC_reset (DEVICE *dptr); + +/* external function prototypes */ + +extern t_stat i8080_reset (DEVICE *dptr); /* reset the 8080 emulator */ +extern int32 multibus_get_mbyte(int32 addr); +extern void multibus_put_mbyte(int32 addr, int32 val); +extern int32 EPROM_get_mbyte(int32 addr); +extern int32 RAM_get_mbyte(int32 addr); +extern void RAM_put_mbyte(int32 addr, int32 val); +extern UNIT i8255_unit; +extern UNIT EPROM_unit; +extern UNIT RAM_unit; +extern t_stat i8255_reset (DEVICE *dptr, int32 base); +extern t_stat i8251_reset (DEVICE *dptr, int32 base); +extern t_stat pata_reset (DEVICE *dptr, int32 base); +extern t_stat EPROM_reset (DEVICE *dptr, int32 size); +extern t_stat RAM_reset (DEVICE *dptr, int32 base, int32 size); + +/* SBC reset routine */ + +t_stat SBC_reset (DEVICE *dptr) +{ + printf("Initializing iSBC-80/10:\n"); + i8080_reset (NULL); + i8255_reset (NULL, I8255_BASE_0); + i8255_reset (NULL, I8255_BASE_1); + i8251_reset (NULL, I8251_BASE); + EPROM_reset (NULL, ROM_SIZE); + RAM_reset (NULL, RAM_BASE, RAM_SIZE); + return SCPE_OK; +} + +/* get a byte from memory - handle RAM, ROM, I/O, and Multibus memory */ + +int32 get_mbyte(int32 addr) +{ + int32 val, org, len; + + /* if local EPROM handle it */ + if ((i8255_unit.u5 & 0x01) && (addr >= EPROM_unit.u3) && (addr < (EPROM_unit.u3 + EPROM_unit.capac))) { + return EPROM_get_mbyte(addr); + } /* if local RAM handle it */ + if ((i8255_unit.u5 & 0x02) && (addr >= RAM_unit.u3) && (addr < (RAM_unit.u3 + RAM_unit.capac))) { + return RAM_get_mbyte(addr); + } /* otherwise, try the multibus */ + return multibus_get_mbyte(addr); +} + +/* get a word from memory */ + +int32 get_mword(int32 addr) +{ + int32 val; + + val = get_mbyte(addr); + val |= (get_mbyte(addr+1) << 8); + return val; +} + +/* put a byte to memory - handle RAM, ROM, I/O, and Multibus memory */ + +void put_mbyte(int32 addr, int32 val) +{ + /* if local EPROM handle it */ + if ((i8255_unit.u5 & 0x01) && (addr >= EPROM_unit.u3) && (addr <= (EPROM_unit.u3 + EPROM_unit.capac))) { + printf("Write to R/O memory address %04X - ignored\n", addr); + return; + } /* if local RAM handle it */ + if ((i8255_unit.u5 & 0x02) && (addr >= RAM_unit.u3) && (addr <= (RAM_unit.u3 + RAM_unit.capac))) { + RAM_put_mbyte(addr, val); + return; + } /* otherwise, try the multibus */ + multibus_put_mbyte(addr, val); +} + +/* put a word to memory */ + +void put_mword(int32 addr, int32 val) +{ + put_mbyte(addr, val); + put_mbyte(addr+1, val >> 8); +} + +/* end of iSBC80-10.c */ diff --git a/MDS-800/common/iSBC80-20.c b/isys8010/common/iSBC80-20.c similarity index 100% rename from MDS-800/common/iSBC80-20.c rename to isys8010/common/iSBC80-20.c diff --git a/MDS-800/common/iSBC80-30.c b/isys8010/common/iSBC80-30.c similarity index 100% rename from MDS-800/common/iSBC80-30.c rename to isys8010/common/iSBC80-30.c diff --git a/MDS-800/common/ieprom.c b/isys8010/common/ieprom.c similarity index 53% rename from MDS-800/common/ieprom.c rename to isys8010/common/ieprom.c index 6555f24f..62eb1734 100644 --- a/MDS-800/common/ieprom.c +++ b/isys8010/common/ieprom.c @@ -2,35 +2,40 @@ Copyright (c) 2010, William A. Beech - Permission is hereby granted, free of charge, to any person obtaining a - copy of this software and associated documentation files (the "Software"), - to deal in the Software without restriction, including without limitation - the rights to use, copy, modify, merge, publish, distribute, sublicense, - and/or sell copies of the Software, and to permit persons to whom the - Software is furnished to do so, subject to the following conditions: + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: - The above copyright notice and this permission notice shall be included in - all copies or substantial portions of the Software. + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - WILLIAM A. BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + WILLIAM A. BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - Except as contained in this notice, the name of William A. Beech shall not be - used in advertising or otherwise to promote the sale, use or other dealings - in this Software without prior written authorization from William A. Beech. + Except as contained in this notice, the name of William A. Beech shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from William A. Beech. - These functions support a simulated i2732 EPROM device on an iSBC. This - allows the attachment of the device to a binary file containing the EPROM - code. + MODIFICATIONS: - Unit will support a single 2708, 2716, 2732 and 2764 EPROM type. + ?? ??? 10 - Original file. + 16 Dec 12 - Modified to use isbc_80_10.cfg file to set base and size. + 24 Apr 15 -- Modified to use simh_debug - ?? ??? 10 - Original file. - 16 Dec 12 - Modified to use isbc_80_10.cfg file to set base and size. + NOTES: + + These functions support a simulated i2732 EPROM device on an Intel iSBC 80/XX. + This allows the attachment of the device to a binary file containing the EPROM + code image. + + Unit will support a single 2708, 2716, 2732 and 2764 type EPROMs. */ #include "system_defs.h" @@ -101,33 +106,27 @@ t_stat EPROM_attach (UNIT *uptr, char *cptr) FILE *fp; t_stat r; - if (EPROM_dev.dctrl & DEBUG_flow) - printf("EPROM_attach: cptr=%s\n", cptr); + sim_debug (DEBUG_flow, &EPROM_dev, "EPROM_attach: cptr=%s\n", cptr); if ((r = attach_unit (uptr, cptr)) != SCPE_OK) { - if (EPROM_dev.dctrl & DEBUG_flow) - printf("EPROM_attach: Error\n"); + sim_debug (DEBUG_flow, &EPROM_dev, "EPROM_attach: Error\n"); return r; } - if (EPROM_dev.dctrl & DEBUG_read) - printf("\tAllocate buffer\n"); + sim_debug (DEBUG_read, &EPROM_dev, "\tAllocate buffer\n"); if (EPROM_unit.filebuf == NULL) { /* no buffer allocated */ EPROM_unit.filebuf = malloc(EPROM_unit.capac); /* allocate EPROM buffer */ if (EPROM_unit.filebuf == NULL) { - if (EPROM_dev.dctrl & DEBUG_flow) - printf("EPROM_attach: Malloc error\n"); + sim_debug (DEBUG_flow, &EPROM_dev, "EPROM_attach: Malloc error\n"); return SCPE_MEM; } } - if (EPROM_dev.dctrl & DEBUG_read) - printf("\tOpen file %s\n", EPROM_unit.filename); + sim_debug (DEBUG_read, &EPROM_dev, "\tOpen file %s\n", EPROM_unit.filename); fp = fopen(EPROM_unit.filename, "rb"); /* open EPROM file */ if (fp == NULL) { printf("EPROM: Unable to open ROM file %s\n", EPROM_unit.filename); printf("\tNo ROM image loaded!!!\n"); return SCPE_OK; } - if (EPROM_dev.dctrl & DEBUG_read) - printf("\tRead file\n"); + sim_debug (DEBUG_read, &EPROM_dev, "\tRead file\n"); j = 0; /* load EPROM file */ c = fgetc(fp); while (c != EOF) { @@ -138,12 +137,10 @@ t_stat EPROM_attach (UNIT *uptr, char *cptr) break; } } - if (EPROM_dev.dctrl & DEBUG_read) - printf("\tClose file\n"); + sim_debug (DEBUG_read, &EPROM_dev, "\tClose file\n"); fclose(fp); printf("EPROM: %d bytes of ROM image %s loaded\n", j, EPROM_unit.filename); - if (EPROM_dev.dctrl & DEBUG_flow) - printf("EPROM_attach: Done\n"); + sim_debug (DEBUG_flow, &EPROM_dev, "EPROM_attach: Done\n"); return SCPE_OK; } @@ -153,12 +150,10 @@ t_stat EPROM_reset (DEVICE *dptr, int32 size) { t_stat r; -// if (EPROM_dev.dctrl & DEBUG_flow) /* entry message */ - printf(" EPROM_reset: base=0000 size=%04X\n", size); +// sim_debug (DEBUG_flow, &EPROM_dev, " EPROM_reset: base=0000 size=%04X\n", size); if ((EPROM_unit.flags & UNIT_ATT) == 0) { /* if unattached */ EPROM_unit.capac = size; /* set EPROM size to 0 */ - if (EPROM_dev.dctrl & DEBUG_flow) /* exit message */ - printf("Done1\n"); + sim_debug (DEBUG_flow, &EPROM_dev, "Done1\n"); // printf(" EPROM: Available [%04X-%04XH]\n", // 0, EPROM_unit.capac - 1); return SCPE_OK; @@ -166,8 +161,7 @@ t_stat EPROM_reset (DEVICE *dptr, int32 size) if ((EPROM_unit.flags & UNIT_ATT) == 0) { printf("EPROM: No file attached\n"); } - if (EPROM_dev.dctrl & DEBUG_flow) /* exit message */ - printf("Done2\n"); + sim_debug (DEBUG_flow, &EPROM_dev, "Done2\n"); return SCPE_OK; } @@ -177,24 +171,19 @@ int32 EPROM_get_mbyte(int32 addr) { int32 val; - if (i8255_unit.u6 & 0x01) { /* EPROM enabled */ - if (EPROM_dev.dctrl & DEBUG_read) - printf("EPROM_get_mbyte: addr=%04X\n", addr); + if (i8255_unit.u5 & 0x01) { /* EPROM enabled */ + sim_debug (DEBUG_read, &EPROM_dev, "EPROM_get_mbyte: addr=%04X\n", addr); if ((addr >= 0) && (addr < EPROM_unit.capac)) { SET_XACK(1); /* good memory address */ - if (EPROM_dev.dctrl & DEBUG_xack) - printf("EPROM_get_mbyte: Set XACK for %04X\n", addr); + sim_debug (DEBUG_xack, &EPROM_dev, "EPROM_get_mbyte: Set XACK for %04X\n", addr); val = *(uint8 *)(EPROM_unit.filebuf + addr); - if (EPROM_dev.dctrl & DEBUG_read) - printf(" val=%04X\n", val); + sim_debug (DEBUG_read, &EPROM_dev, " val=%04X\n", val); return (val & 0xFF); } - if (EPROM_dev.dctrl & DEBUG_read) - printf(" EPROM Disabled\n"); + sim_debug (DEBUG_read, &EPROM_dev, " EPROM Disabled\n"); return 0xFF; } - if (EPROM_dev.dctrl & DEBUG_read) - printf(" Out of range\n"); + sim_debug (DEBUG_read, &EPROM_dev, " Out of range\n"); return 0xFF; } diff --git a/MDS-800/common/ijedec.c b/isys8010/common/ijedec.c similarity index 100% rename from MDS-800/common/ijedec.c rename to isys8010/common/ijedec.c diff --git a/MDS-800/common/iram16.c b/isys8010/common/iram16.c similarity index 100% rename from MDS-800/common/iram16.c rename to isys8010/common/iram16.c diff --git a/MDS-800/common/iram8.c b/isys8010/common/iram8.c similarity index 52% rename from MDS-800/common/iram8.c rename to isys8010/common/iram8.c index 46d2a4b4..f6c51401 100644 --- a/MDS-800/common/iram8.c +++ b/isys8010/common/iram8.c @@ -2,31 +2,36 @@ Copyright (c) 2011, William A. Beech - Permission is hereby granted, free of charge, to any person obtaining a - copy of this software and associated documentation files (the "Software"), - to deal in the Software without restriction, including without limitation - the rights to use, copy, modify, merge, publish, distribute, sublicense, - and/or sell copies of the Software, and to permit persons to whom the - Software is furnished to do so, subject to the following conditions: + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: - The above copyright notice and this permission notice shall be included in - all copies or substantial portions of the Software. + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - WILLIAM A. BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + WILLIAM A. BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - Except as contained in this notice, the name of William A. Beech shall not be - used in advertising or otherwise to promote the sale, use or other dealings - in this Software without prior written authorization from William A. Beech. + Except as contained in this notice, the name of William A. Beech shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from William A. Beech. - These functions support a simulated i8111 or 8102 RAM device on an iSBC. + MODIFICATIONS: - ?? ??? 11 - Original file. - 16 Dec 12 - Modified to use isbc_80_10.cfg file to set base and size. + ?? ??? 11 - Original file. + 16 Dec 12 - Modified to use isbc_80_10.cfg file to set base and size. + 24 Apr 15 -- Modified to use simh_debug + + NOTES: + + These functions support a simulated i8111 or i8102 RAM devices on an iSBC-80/XX. */ #include "system_defs.h" @@ -92,8 +97,7 @@ DEVICE RAM_dev = { t_stat RAM_reset (DEVICE *dptr, int32 base, int32 size) { -// if (RAM_dev.dctrl & DEBUG_flow) - printf(" RAM_reset: base=%04X size=%04X\n", base, size-1); + sim_debug (DEBUG_flow, &RAM_dev, " RAM_reset: base=%04X size=%04X\n", base, size-1); if (RAM_unit.capac == 0) { /* if undefined */ RAM_unit.capac = size; RAM_unit.u3 = base; @@ -101,16 +105,14 @@ t_stat RAM_reset (DEVICE *dptr, int32 base, int32 size) if (RAM_unit.filebuf == NULL) { /* no buffer allocated */ RAM_unit.filebuf = malloc(RAM_unit.capac); if (RAM_unit.filebuf == NULL) { - if (RAM_dev.dctrl & DEBUG_flow) - printf("RAM_set_size: Malloc error\n"); + sim_debug (DEBUG_flow, &RAM_dev, "RAM_set_size: Malloc error\n"); return SCPE_MEM; } } // printf(" RAM: Available [%04X-%04XH]\n", // RAM_unit.u3, // RAM_unit.u3 + RAM_unit.capac - 1); - if (RAM_dev.dctrl & DEBUG_flow) - printf("RAM_reset: Done\n"); + sim_debug (DEBUG_flow, &RAM_dev, "RAM_reset: Done\n"); return SCPE_OK; } @@ -121,23 +123,18 @@ int32 RAM_get_mbyte(int32 addr) int32 val; if (i8255_unit.u6 & 0x02) { /* enable RAM */ - if (RAM_dev.dctrl & DEBUG_read) - printf("RAM_get_mbyte: addr=%04X\n", addr); + sim_debug (DEBUG_read, &RAM_dev, "RAM_get_mbyte: addr=%04X\n", addr); if ((addr >= RAM_unit.u3) && (addr < (RAM_unit.u3 + RAM_unit.capac))) { SET_XACK(1); /* good memory address */ - if (RAM_dev.dctrl & DEBUG_xack) - printf("RAM_get_mbyte: Set XACK for %04X\n", addr); + sim_debug (DEBUG_xack, &RAM_dev, "RAM_get_mbyte: Set XACK for %04X\n", addr); val = *(uint8 *)(RAM_unit.filebuf + (addr - RAM_unit.u3)); - if (RAM_dev.dctrl & DEBUG_read) - printf(" val=%04X\n", val); + sim_debug (DEBUG_read, &RAM_dev, " val=%04X\n", val); return (val & 0xFF); } - if (RAM_dev.dctrl & DEBUG_read) - printf(" RAM disabled\n"); + sim_debug (DEBUG_read, &RAM_dev, " RAM disabled\n"); return 0xFF; } - if (RAM_dev.dctrl & DEBUG_read) - printf(" Out of range\n"); + sim_debug (DEBUG_read, &RAM_dev, " Out of range\n"); return 0xFF; } @@ -145,24 +142,19 @@ int32 RAM_get_mbyte(int32 addr) void RAM_put_mbyte(int32 addr, int32 val) { - if (i8255_unit.u6 & 0x02) { /* enable RAM */ - if (RAM_dev.dctrl & DEBUG_write) - printf("RAM_put_mbyte: addr=%04X, val=%02X\n", addr, val); + if (i8255_unit.u5 & 0x02) { /* enable RAM */ + sim_debug (DEBUG_write, &RAM_dev, "RAM_put_mbyte: addr=%04X, val=%02X\n", addr, val); if ((addr >= RAM_unit.u3) && (addr < RAM_unit.u3 + RAM_unit.capac)) { SET_XACK(1); /* good memory address */ - if (RAM_dev.dctrl & DEBUG_xack) - printf("RAM_put_mbyte: Set XACK for %04X\n", addr); + sim_debug (DEBUG_xack, &RAM_dev, "RAM_put_mbyte: Set XACK for %04X\n", addr); *(uint8 *)(RAM_unit.filebuf + (addr - RAM_unit.u3)) = val & 0xFF; - if (RAM_dev.dctrl & DEBUG_write) - printf("\n"); + sim_debug (DEBUG_write, &RAM_dev, "\n"); return; } - if (RAM_dev.dctrl & DEBUG_write) - printf(" RAM disabled\n"); + sim_debug (DEBUG_write, &RAM_dev, " RAM disabled\n"); return; } - if (RAM_dev.dctrl & DEBUG_write) - printf(" Out of range\n"); + sim_debug (DEBUG_write, &RAM_dev, " Out of range\n"); } /* end of iRAM8.c */ diff --git a/MDS-800/common/isbc064.c b/isys8010/common/isbc064.c similarity index 54% rename from MDS-800/common/isbc064.c rename to isys8010/common/isbc064.c index 4e7c18ca..b6204ec8 100644 --- a/MDS-800/common/isbc064.c +++ b/isys8010/common/isbc064.c @@ -2,33 +2,37 @@ Copyright (c) 2011, William A. Beech - Permission is hereby granted, free of charge, to any person obtaining a - copy of this software and associated documentation files (the "Software"), - to deal in the Software without restriction, including without limitation - the rights to use, copy, modify, merge, publish, distribute, sublicense, - and/or sell copies of the Software, and to permit persons to whom the - Software is furnished to do so, subject to the following conditions: + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: - The above copyright notice and this permission notice shall be included in - all copies or substantial portions of the Software. + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - WILLIAM A. BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + WILLIAM A. BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - Except as contained in this notice, the name of William A. Beech shall not be - used in advertising or otherwise to promote the sale, use or other dealings - in this Software without prior written authorization from William A. Beech. + Except as contained in this notice, the name of William A. Beech shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from William A. Beech. - These functions support a simulated isbc016, isbc032, isbc048 and isbc064 - memory card on an Intel multibus system. - - ?? ??? 11 - Original file. - 16 Dec 12 - Modified to use system_80_10.cfg file to set base and size. - + MODIFICATIONS: + + ?? ??? 11 - Original file. + 16 Dec 12 - Modified to use isbc_80_10.cfg file to set base and size. + 24 Apr 15 -- Modified to use simh_debug + + NOTES: + + These functions support a simulated isbc016, isbc032, isbc048 and isbc064 + memory card on an Intel multibus system. */ #include "system_defs.h" @@ -93,8 +97,7 @@ DEVICE isbc064_dev = { t_stat isbc064_reset (DEVICE *dptr) { - if (isbc064_dev.dctrl & DEBUG_flow) - printf("isbc064_reset: "); + sim_debug (DEBUG_flow, &isbc064_dev, "isbc064_reset: "); if ((isbc064_dev.flags & DEV_DIS) == 0) { isbc064_unit.capac = SBC064_SIZE; isbc064_unit.u3 = SBC064_BASE; @@ -105,13 +108,11 @@ t_stat isbc064_reset (DEVICE *dptr) if (isbc064_unit.filebuf == NULL) { isbc064_unit.filebuf = malloc(isbc064_unit.capac); if (isbc064_unit.filebuf == NULL) { - if (isbc064_dev.dctrl & DEBUG_flow) - printf("isbc064_reset: Malloc error\n"); + sim_debug (DEBUG_flow, &isbc064_dev, "isbc064_reset: Malloc error\n"); return SCPE_MEM; } } - if (isbc064_dev.dctrl & DEBUG_flow) - printf("isbc064_reset: Done\n"); + sim_debug (DEBUG_flow, &isbc064_dev, "isbc064_reset: Done\n"); return SCPE_OK; } @@ -125,26 +126,20 @@ int32 isbc064_get_mbyte(int32 addr) if ((isbc064_dev.flags & DEV_DIS) == 0) { org = isbc064_unit.u3; len = isbc064_unit.capac; - if (isbc064_dev.dctrl & DEBUG_read) - printf("isbc064_get_mbyte: addr=%04X", addr); - if (isbc064_dev.dctrl & DEBUG_read) - printf("isbc064_put_mbyte: org=%04X, len=%04X\n", org, len); + sim_debug (DEBUG_read, &isbc064_dev, "isbc064_get_mbyte: addr=%04X", addr); + sim_debug (DEBUG_read, &isbc064_dev, "isbc064_get_mbyte: org=%04X, len=%04X\n", org, len); if ((addr >= org) && (addr < (org + len))) { SET_XACK(1); /* good memory address */ - if (isbc064_dev.dctrl & DEBUG_xack) - printf("isbc064_get_mbyte: Set XACK for %04X\n", addr); + sim_debug (DEBUG_xack, &isbc064_dev, "isbc064_get_mbyte: Set XACK for %04X\n", addr); val = *(uint8 *)(isbc064_unit.filebuf + (addr - org)); - if (isbc064_dev.dctrl & DEBUG_read) - printf(" val=%04X\n", val); + sim_debug (DEBUG_read, &isbc064_dev, " val=%04X\n", val); return (val & 0xFF); } else { - if (isbc064_dev.dctrl & DEBUG_read) - printf(" Out of range\n"); + sim_debug (DEBUG_read, &isbc064_dev, " Out of range\n"); return 0xFF; /* multibus has active high pullups */ } } - if (isbc064_dev.dctrl & DEBUG_read) - printf(" Disabled\n"); + sim_debug (DEBUG_read, &isbc064_dev, " Disabled\n"); return 0xFF; /* multibus has active high pullups */ } @@ -169,26 +164,20 @@ void isbc064_put_mbyte(int32 addr, int32 val) if ((isbc064_dev.flags & DEV_DIS) == 0) { org = isbc064_unit.u3; len = isbc064_unit.capac; - if (isbc064_dev.dctrl & DEBUG_write) - printf("isbc064_put_mbyte: addr=%04X, val=%02X\n", addr, val); - if (isbc064_dev.dctrl & DEBUG_write) - printf("isbc064_put_mbyte: org=%04X, len=%04X\n", org, len); + sim_debug (DEBUG_write, &isbc064_dev, "isbc064_put_mbyte: addr=%04X, val=%02X\n", addr, val); + sim_debug (DEBUG_write, &isbc064_dev, "isbc064_put_mbyte: org=%04X, len=%04X\n", org, len); if ((addr >= org) && (addr < (org + len))) { SET_XACK(1); /* good memory address */ - if (isbc064_dev.dctrl & DEBUG_xack) - printf("isbc064_put_mbyte: Set XACK for %04X\n", addr); + sim_debug (DEBUG_write, &isbc064_dev, "isbc064_put_mbyte: Set XACK for %04X\n", addr); *(uint8 *)(isbc064_unit.filebuf + (addr - org)) = val & 0xFF; - if (isbc064_dev.dctrl & DEBUG_xack) - printf("isbc064_put_mbyte: Return\n"); + sim_debug (DEBUG_write, &isbc064_dev, "isbc064_put_mbyte: Return\n"); return; } else { - if (isbc064_dev.dctrl & DEBUG_write) - printf(" Out of range\n"); + sim_debug (DEBUG_write, &isbc064_dev, " Out of range\n"); return; } } - if (isbc064_dev.dctrl & DEBUG_write) - printf("isbc064_put_mbyte: Disabled\n"); + sim_debug (DEBUG_write, &isbc064_dev, "isbc064_put_mbyte: Disabled\n"); } /* put a word into memory */ diff --git a/MDS-800/common/isbc064b.c b/isys8010/common/isbc064b.c similarity index 100% rename from MDS-800/common/isbc064b.c rename to isys8010/common/isbc064b.c diff --git a/MDS-800/common/isbc064x.c b/isys8010/common/isbc064x.c similarity index 100% rename from MDS-800/common/isbc064x.c rename to isys8010/common/isbc064x.c diff --git a/isys8010/common/isbc208.c b/isys8010/common/isbc208.c new file mode 100644 index 00000000..26a3ba4b --- /dev/null +++ b/isys8010/common/isbc208.c @@ -0,0 +1,1616 @@ +/* isbc208.c: Intel iSBC208 Floppy Disk adapter + + Copyright (c) 2011, William A. Beech + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + WILLIAM A. BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name of William A. Beech shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from William A. Beech. + + MODIFICATIONS: + + ?? ??? 11 - Original file. + 16 Dec 12 - Modified to use isbc_80_10.cfg file to set base and size. + 24 Apr 15 -- Modified to use simh_debug + + NOTES: + + These functions support a simulated iSBC208 interface to 4 each 8-, 5 1/4-, or + 3 1/2-inch floppy disk drives. Commands are setup with programmed I/O to the + simulated ports of an i8237 DMA controller and an i8272 FDC. Data transfer + to/from the simulated disks is performed directly with the multibus memory. + + The iSBC-208 can be configured for 8- or 16-bit addresses. It defaults to 8-bit + addresses for the 8080/8085 processors. It can be configured for I/O port + addresses with 3-bits (8-bit address) or 11-bits (16-bit address). Default is + 3-bits set to 0. This defines the port offset to be used to determine the actual + port address. Bus priority can be configured for parallel or serial mode. Default is + serial. The multibus interface interrupt can be configured for interrupt 0-7. + Default is none. Since all channel registers in the i8237 are 16-bit, transfers + are done as two 8-bit operations, low- then high-byte. + + Port addressing is as follows (Port offset = 0): + + Port Mode Command Function + + 00 Write Load DMAC Channel 0 Base and Current Address Regsiters + Read Read DMAC Channel 0 Current Address Register + 01 Write Load DMAC Channel 0 Base and Current Word Count Registers + Read Read DMAC Channel 0 Current Word Count Register + 04 Write Load DMAC Channel 2 Base and Current Address Regsiters + Read Read DMAC Channel 2 Current Address Register + 05 Write Load DMAC Channel 2 Base and Current Word Count Registers + Read Read DMAC Channel 2 Current Word Count Register + 06 Write Load DMAC Channel 3 Base and Current Address Regsiters + Read Read DMAC Channel 3 Current Address Register + 07 Write Load DMAC Channel 3 Base and Current Word Count Registers + Read Read DMAC Channel 3 Current Word Count Register + 08 Write Load DMAC Command Register + Read Read DMAC Status Register + 09 Write Load DMAC Request Register + OA Write Set/Reset DMAC Mask Register + OB Write Load DMAC Mode Register + OC Write Clear DMAC First/Last Flip-Flop + 0D Write DMAC Master Clear + OF Write Load DMAC Mask Register + 10 Read Read FDC Status Register + 11 Write Load FDC Data Register + Read Read FDC Data Register + 12 Write Load Controller Auxiliary Port + Read Poll Interrupt Status + 13 Write Controller Reset + 14 Write Load Controller Low-Byte Segment Address Register + 15 Write Load Controller High-Byte Segment Address Register + 20-2F Read/Write Reserved for iSBX Multimodule Board + + Register usage is defined in the following paragraphs. + + Read/Write DMAC Address Registers + + Used to simultaneously load a channel's current-address register and base-address + register with the memory address of the first byte to be transferred. (The Channel + 0 current/base address register must be loaded prior to initiating a diskette read + or write operation.) Since each channel's address registers are 16 bits in length + (64K address range), two "write address register" commands must be executed in + order to load the complete current/base address registers for any channel. + + Read/Write DMAC Word Count Registers + + The Write DMAC Word Count Register command is used to simultaneously load a + channel's current and base word-count registers with the number of bytes + to be transferred during a subsequent DMA operation. Since the word-count + registers are 16-bits in length, two commands must be executed to load both + halves of the registers. + + Write DMAC Command Register + + The Write DMAC Command Register command loads an 8-bit byte into the + DMAC's command register to define the operating characteristics of the + DMAC. The functions of the individual bits in the command register are + defined in the following diagram. Note that only two bits within the + register are applicable to the controller; the remaining bits select + functions that are not supported and, accordingly, must always be set + to zero. + + 7 6 5 4 3 2 1 0 + +---+---+---+---+---+---+---+---+ + | 0 0 0 0 0 0 | + +---+---+---+---+---+---+---+---+ + | | + | +---------- 0 CONTROLLER ENABLE + | 1 CONTROLLER DISABLE + | + +------------------ 0 FIXED PRIORITY + 1 ROTATING PRIORITY + + Read DMAC Status Register Command + + The Read DMAC Status Register command accesses an 8-bit status byte that + identifies the DMA channels that have reached terminal count or that + have a pending DMA request. + + 7 6 5 4 3 2 1 0 + +---+---+---+---+---+---+---+---+ + | 0 0 | + +---+---+---+---+---+---+---+---+ + | | | | | | + | | | | | +-- CHANNEL 0 TC + | | | | +---------- CHANNEL 2 TC + | | | +-------------- CHANNEL 3 TC + | | +------------------ CHANNEL 0 DMA REQUEST + | +-------------------------- CHANNEL 2 DMA REQUEST + +------------------------------ CHANNEL 3 DMA REQUEST + + Write DMAC Request Register + + The data byte associated with the Write DMAC Request Register command + sets or resets a channel's associated request bit within the DMAC's + internal 4-bit request register. + + 7 6 5 4 3 2 1 0 + +---+---+---+---+---+---+---+---+ + | X X X X X | + +---+---+---+---+---+---+---+---+ + | | | + | +---+-- 00 SELECT CHANNEL 0 + | 01 SELECT CHANNEL 1 + | 10 SELECT CHANNEL 2 + | 11 SELECT CHANNEL 3 + | + +---------- 0 RESET REQUEST BIT + 1 SET REQUEST BIT + + Set/Reset DMAC Mask Register + + Prior to a DREQ-initiated DMA transfer, the channel's mask bit must + be reset to enable recognition of the DREQ input. When the transfer + is complete (terminal count reached or external EOP applied) and + the channel is not programmed to autoinitialize, the channel's + mask bit is automatically set (disabling DREQ) and must be reset + prior to a subsequent DMA transfer. All four bits of the mask + register are set (disabling the DREQ inputs) by a DMAC master + clear or controller reset. Additionally, all four bits can be + set/reset by a single Write DMAC Mask Register command. + + + 7 6 5 4 3 2 1 0 + +---+---+---+---+---+---+---+---+ + | X X X X X | + +---+---+---+---+---+---+---+---+ + | | | + | +---+-- 00 SELECT CHANNEL 0 + | 01 SELECT CHANNEL 1 + | 10 SELECT CHANNEL 2 + | 11 SELECT CHANNEL 3 + | + +---------- 0 RESET REQUEST BIT + 1 SET REQUEST BIT + + Write DMAC Mode Register + + The Write DMAC Mode Register command is used to define the + operating mode characteristics for each DMA channel. Each + channel has an internal 6-bit mode register; the high-order + six bits of the associated data byte are written into the + mode register addressed by the two low-order bits. + + + 7 6 5 4 3 2 1 0 + +---+---+---+---+---+---+---+---+ + | | + +---+---+---+---+---+---+---+---+ + | | | | | | | | + | | | | | | +---+-- 00 SELECT CHANNEL 0 + | | | | | | 01 SELECT CHANNEL 1 + | | | | | | 10 SELECT CHANNEL 2 + | | | | | | 11 SELECT CHANNEL 3 + | | | | | | + | | | | +---+---------- 00 VERIFY TRANSFER + | | | | 01 WRITE TRANSFER + | | | | 10 READ TRANSFER + | | | | + | | | +------------------ 0 AUTOINITIALIZE DISABLE + | | | 1 AUTOINITIALIZE ENABLE + | | | + | | +---------------------- 0 ADDRESS INCREMENT + | | 1 ADDRESS DECREMENT + | | + +---+-------------------------- 00 DEMAND MODE + 01 SINGLE MODE + 10 BLOCK MODE + + Clear DMAC First/Last Flip-Flop + + The Clear DMAC First/Last Flip-Flop command initializes + the DMAC's internal first/last flip-flop so that the + next byte written to or re~d from the 16-bit address + or word-count registers is the low-order byte. The + flip-flop is toggled with each register access so that + a second register read or write command accesses the + high-order byte. + + DMAC Master Clear + + The DMAC Master Clear command clears the DMAC's command, status, + request, and temporary registers to zero, initializes the + first/last flip-flop, and sets the four channel mask bits in + the mask register to disable all DMA requests (i.e., the DMAC + is placed in an idle state). + + Write DMAC Mask Register + + The Write DMAC Mask Register command allows all four bits of the + DMAC's mask register to be written with a single command. + + 7 6 5 4 3 2 1 0 + +---+---+---+---+---+---+---+---+ + | X X X X X | + +---+---+---+---+---+---+---+---+ + | | | + | | +-- 0 CLEAR CHANNEL 0 MASK BIT + | | 1 SET CHANNEL 0 MASK BIT + | | + | +---------- 0 CLEAR CHANNEL 2 MASK BIT + | 1 SET CHANNEL 2 MASK BIT + | + +-------------- 0 CLEAR CHANNEL 3 MASK BIT + 1 SET CHANNEL 3 MASK BIT + + Read FDC Status Register + + The Read FDC Status Register command accesses the FDC's main + status register. The individual status register bits are as + follows: + + 7 6 5 4 3 2 1 0 + +---+---+---+---+---+---+---+---+ + | | + +---+---+---+---+---+---+---+---+ + | | | | | | | | + | | | | | | | +-- FDD 0 BUSY + | | | | | | +------ FDD 1 BUSY + | | | | | +---------- FDD 2 BUSY + | | | | +-------------- FDD 3 BUSY + | | | +------------------ FDC BUSY + | | +---------------------- NON-DMA MODE + | +-------------------------- DATA INPUT/OUTPUT + +------------------------------ REQUEST FOR MASTER + + Read/Write FDC Data Register + + The Read and Write FDC Data Register commands are used to write + command and parameter bytes to the FDC in order to specify the + operation to be performed (referred to as the "command phase") + and to read status bytes from the FDC following the operation + (referred to as the "result phase"). During the command and + result phases, the 8-bit data register is actually a series of + 8-bit registers in a stack. Each register is accessed in + sequence; the number of registers accessed and the individual + register contents are defined by the specific disk command. + + Write Controller Auxiliary Port + + The Write Controller Auxiliary Port command is used to set or + clear individual bits within the controller's auxiliary port. + The four low-order port bits are dedicated to auxiliary drive + control functions (jumper links are required to connect the + desired port bit to an available pin on the drive interface + connectors). The most common application for these bits is + the "Motor-On" control function for mini-sized drives. + + 7 6 5 4 3 2 1 0 + +---+---+---+---+---+---+---+---+ + | | + +---+---+---+---+---+---+---+---+ + | | | | | | | | + | | | | +---+---+---+-- DRIVE CONTROL + | | | +------------------ ADDR 20 + | | +---------------------- ADDR 21 + | +-------------------------- ADDR 22 + +------------------------------ ADDR 23 + + Poll Interrupt Status + + The Poll Interrupt Status command presents the interrupt + status of the controller and the two interrupt status + lines dedicated to the iSBX Multimodule board. + 7 6 5 4 3 2 1 0 + +---+---+---+---+---+---+---+---+ + | X X X X X | + +---+---+---+---+---+---+---+---+ + | | | + | | +-- CONTROLLER INTERRUPT + | +------ MULTIMODULE BOARD INTERRUPT 0 + +---------- MULTIMODULE BOARD INTERRUPT 1 + + Controller Reset + + The Controller Reset command is the software reset for the + controller. This command clears the controller's auxiliary + port and segment address register, provides a reset signal + to the iSBX Multimodule board and initializes the bus + controller (releases the bus), the DMAC (clears the internal + registers and masks the DREQ inputs), and the FDC (places + the FDC in an idle state and disables the output control + lines to the diskette drive). + + Write Controller Low- And High-Byte Segment Address Registers + + The Write Controller Low- and High-Byte Address Registers + commands are required when the controller uses 20-bit + addressing (memory address range from 0 to OFFFFFH). These + commands are issued prior to initiating a diskette read or + write operation to specify the 16-bit segment address. + + FDC Commands + + The 8272/D765 is capable of performing 15 different + commands. Each command is initiated by a multibyte transfer + from the processor, and the result after execution of the + command may also be a multibyte transfer back to the processor. + Because of this multibyte interchange of information between + the FDC and the processor, it is convenient to consider each + command as consisting of three phases: + + Command Phase: The FDC receives all information required to + perform a particular operation from the processor. + + Execution Phase: The FDC performs the operation it was + instructed to do. + + Result Phase: After completion of the operation, status + and other housekeeping information are made available + to the processor. + + Not all the FDC commands are supported by this emulation. Only the subset + of commands required to build an operable CP/M BIOS are supported. They are: + + Read - Read specified data from the selected FDD. + + Write - Write specified data to the selected FDD. + + Seek - Move the R/W head to the specified cylinder on the specified FDD. + + Specify - Set the characteristics for all the FDDs. + + Sense Interrupt - Sense change in FDD Ready line or and of Seek/Recalibrate + command. + + Sense Drive - Returns status of all the FDDs. + + Recalibrate - Move the R/W head to cylinder 0 on the specified FDD. + + Format Track - Format the current track on the specified FDD. + + Read ID - Reads the first address mark it finds. + + Simulated Floppy Disk Drives + + The units in this device simulate an 8- or 5 1/4- or 3 1/2 inch drives. The + drives can emulate SSSD, SSDD, and DSDD. Drives can be attached to files up + to 1.44MB in size. Drive configuration is selected when a disk is logged onto + the system. An identity sector or identity byte contains information to + configure the OS drivers for the type of drive to emulate. + + uptr->u3 - + uptr->u4 - + uptr->u5 - + uptr->u6 - unit number (0-FDD_NUM) +*/ + +#include "system_defs.h" + +#define UNIT_V_WPMODE (UNIT_V_UF) /* Write protect */ +#define UNIT_WPMODE (1 << UNIT_V_WPMODE) + +/* master status register definitions */ +#define RQM 0x80 /* Request for master */ +#define DIO 0x40 /* Data I/O Direction 0=W, 1=R */ +#define NDM 0x20 /* Non-DMA mode */ +#define CB 0x10 /* FDC busy */ +#define D3B 0x08 /* FDD 3 busy */` +#define D2B 0x04 /* FDD 2 busy */` +#define D1B 0x02 /* FDD 1 busy */` +#define D0B 0x01 /* FDD 0 busy */` + +/* status register 0 definitions */ +#define IC 0xC0 /* Interrupt code */ +#define IC_NORM 0x00 /* normal completion */ +#define IC_ABNORM 0x40 /* abnormal completion */ +#define IC_INVC 0x80 /* invalid command */ +#define IC_RC 0xC0 /* drive not ready */ +#define SE 0x20 /* Seek end */ +#define EC 0x10 /* Equipment check */ +#define NR 0x08 /* Not ready */ +#define HD 0x04 /* Head selected */ +#define US 0x03 /* Unit selected */ +#define US_0 0x00 /* Unit 0 */ +#define US_1 0x01 /* Unit 1 */ +#define US_2 0x02 /* Unit 2 */ +#define US_3 0x03 /* Unit 3 */ + +/* status register 1 definitions */ +#define EN 0x80 /* End of cylinder */ +#define DE 0x20 /* Data error */ +#define OR 0x10 /* Overrun */ +#define ND 0x04 /* No data */ +#define NW 0x02 /* Not writable */ +#define MA 0x01 /* Missing address mark */ + +/* status register 2 definitions */ +#define CM 0x40 /* Control mark */ +#define DD 0x20 /* Data error in data field */ +#define WC 0x10 /* Wrong cylinder */ +#define BC 0x02 /* Bad cylinder */ +#define MD 0x01 /* Missing address mark in data field */ + +/* status register 3/fddst definitions */ +#define FT 0x80 /* Fault */ +#define WP 0x40 /* Write protect */ +#define RDY 0x20 /* Ready */ +#define T0 0x10 /* Track 0 */ +#define TS 0x08 /* Two sided */ +//#define HD 0x04 /* Head selected */ +//#define US 0x03 /* Unit selected */ + +/* FDC command definitions */ +#define READTRK 0x02 +#define SPEC 0x03 +#define SENDRV 0x04 +#define WRITE 0x05 +#define READ 0x06 +#define HOME 0x07 +#define SENINT 0x08 +#define WRITEDEL 0x09 +#define READID 0x0A +#define READDEL 0x0C +#define FMTTRK 0x0D +#define SEEK 0x0F +#define SCANEQ 0x11 +#define SCANLOEQ 0x19 +#define SCANHIEQ 0x1D + +#define FDD_NUM 4 + +/* internal function prototypes */ + +t_stat isbc208_svc (UNIT *uptr); +t_stat isbc208_reset (DEVICE *dptr); +void isbc208_reset1 (void); +t_stat isbc208_attach (UNIT *uptr, char *cptr); +t_stat isbc208_set_mode (UNIT *uptr, int32 val, char *cptr, void *desc); +int32 isbc208_r0(int32 io, int32 data); +int32 isbc208_r1(int32 io, int32 data); +int32 isbc208_r2(int32 io, int32 data); +int32 isbc208_r3(int32 io, int32 data); +int32 isbc208_r4(int32 io, int32 data); +int32 isbc208_r5(int32 io, int32 data); +int32 isbc208_r6(int32 io, int32 data); +int32 isbc208_r7(int32 io, int32 data); +int32 isbc208_r8(int32 io, int32 data); +int32 isbc208_r9(int32 io, int32 data); +int32 isbc208_rA(int32 io, int32 data); +int32 isbc208_rB(int32 io, int32 data); +int32 isbc208_rC(int32 io, int32 data); +int32 isbc208_rD(int32 io, int32 data); +int32 isbc208_rE(int32 io, int32 data); +int32 isbc208_rF(int32 io, int32 data); +int32 isbc208_r10(int32 io, int32 data); +int32 isbc208_r11(int32 io, int32 data); +int32 isbc208_r12(int32 io, int32 data); +int32 isbc208_r13(int32 io, int32 data); +int32 isbc208_r14(int32 io, int32 data); +int32 isbc208_r15(int32 io, int32 data); + +/* external function prototypes */ + +extern void set_irq(int32 int_num); +extern void clr_irq(int32 int_num); +extern int32 reg_dev(int32 (*routine)(), int32 port); +extern void multibus_put_mbyte(int32 addr, int32 val); +extern int32 multibus_get_mbyte(int32 addr); + +/* 8237 physical register definitions */ +uint16 i8237_r0; // 8237 ch 0 address register +uint16 i8237_r1; // 8237 ch 0 count register +uint16 i8237_r2; // 8237 ch 1 address register +uint16 i8237_r3; // 8237 ch 1 count register +uint16 i8237_r4; // 8237 ch 2 address register +uint16 i8237_r5; // 8237 ch 2 count register +uint16 i8237_r6; // 8237 ch 3 address register +uint16 i8237_r7; // 8237 ch 3 count register +uint8 i8237_r8; // 8237 status register +uint8 i8237_r9; // 8237 command register +uint8 i8237_rA; // 8237 mode register +uint8 i8237_rB; // 8237 mask register +uint8 i8237_rC; // 8237 request register +uint8 i8237_rD; // 8237 first/last ff + +/* 8272 physical register definitions */ +/* 8272 command register stack*/ +uint8 i8272_w0; // MT+MFM+SK+command +uint8 i8272_w1; // HDS [HDS=H << 2] + DS1 + DS0 +uint8 i8272_w2; // cylinder # (0-XX) +uint8 i8272_w3; // head # (0 or 1) +uint8 i8272_w4; // sector # (1-XX) +uint8 i8272_w5; // number of bytes (128 << N) +uint8 i8272_w6; // End of track (last sector # on cylinder) +uint8 i8272_w7; // Gap length +uint8 i8272_w8; // Data length (when N=0, size to read or write) + +/* 8272 status register stack */ +uint8 i8272_msr; // main status +uint8 i8272_r0; // ST 0 +uint8 i8272_r1; // ST 1 +uint8 i8272_r2; // ST 2 +uint8 i8272_r3; // ST 3 + +/* iSBC-208 physical register definitions */ +uint16 isbc208_sr; // isbc-208 segment register +uint8 isbc208_i; // iSBC-208 interrupt register +uint8 isbc208_a; // iSBC-208 auxillary port register + +/* data obtained from analyzing command registers/attached file length */ +int32 wsp = 0, rsp = 0; // indexes to write and read stacks (8272 data) +int32 cyl; // current cylinder +int32 hed; // current head [ h << 2] +int32 h; // current head +int32 sec; // current sector +int32 drv; // current drive +uint8 cmd, pcmd; // current command +int32 secn; // N 0-128, 1-256, etc +int32 spt; // sectors per track +int32 ssize; // sector size (128 << N) + +uint8 *isbc208_buf[FDD_NUM] = { /* FDD buffer pointers */ + NULL, + NULL, + NULL, + NULL +}; + +int32 fddst[FDD_NUM] = { // in ST3 format + 0, // status of FDD 0 + 0, // status of FDD 1 + 0, // status of FDD 2 + 0 // status of FDD 3 +}; + +int8 maxcyl[FDD_NUM] = { + 0, // last cylinder + 1 of FDD 0 + 0, // last cylinder + 1 of FDD 1 + 0, // last cylinder + 1 of FDD 2 + 0 // last cylinder + 1 of FDD 3 +}; + +/* isbc208 Standard SIMH Device Data Structures - 4 units */ +UNIT isbc208_unit[] = { + { UDATA (&isbc208_svc, UNIT_ATTABLE+UNIT_DISABLE, 0), 20 }, + { UDATA (&isbc208_svc, UNIT_ATTABLE+UNIT_DISABLE, 0), 20 }, + { UDATA (&isbc208_svc, UNIT_ATTABLE+UNIT_DISABLE, 0), 20 }, + { UDATA (&isbc208_svc, UNIT_ATTABLE+UNIT_DISABLE, 0), 20 } +}; + +REG isbc208_reg[] = { + { HRDATA (CH0ADR, i8237_r0, 16) }, + { HRDATA (CH0CNT, i8237_r1, 16) }, + { HRDATA (CH1ADR, i8237_r2, 16) }, + { HRDATA (CH1CNT, i8237_r3, 16) }, + { HRDATA (CH2ADR, i8237_r4, 16) }, + { HRDATA (CH2CNT, i8237_r5, 16) }, + { HRDATA (CH3ADR, i8237_r6, 16) }, + { HRDATA (CH3CNT, i8237_r7, 16) }, + { HRDATA (STAT37, i8237_r8, 8) }, + { HRDATA (CMD37, i8237_r9, 8) }, + { HRDATA (MODE, i8237_rA, 8) }, + { HRDATA (MASK, i8237_rB, 8) }, + { HRDATA (REQ, i8237_rC, 8) }, + { HRDATA (FF, i8237_rD, 8) }, + { HRDATA (STAT72, i8272_msr, 8) }, + { HRDATA (STAT720, i8272_r0, 8) }, + { HRDATA (STAT721, i8272_r1, 8) }, + { HRDATA (STAT722, i8272_r2, 8) }, + { HRDATA (STAT723, i8272_r3, 8) }, + { HRDATA (CMD720, i8272_w0, 8) }, + { HRDATA (CMD721, i8272_w1, 8) }, + { HRDATA (CMD722, i8272_w2, 8) }, + { HRDATA (CMD723, i8272_w3, 8) }, + { HRDATA (CMD724, i8272_w4, 8) }, + { HRDATA (CMD725, i8272_w5, 8) }, + { HRDATA (CMD726, i8272_w6, 8) }, + { HRDATA (CMD727, i8272_w7, 8) }, + { HRDATA (CMD728, i8272_w8, 8) }, + { HRDATA (FDD0, fddst[0], 8) }, + { HRDATA (FDD1, fddst[1], 8) }, + { HRDATA (FDD2, fddst[2], 8) }, + { HRDATA (FDD3, fddst[3], 8) }, + { HRDATA (SEGREG, isbc208_sr, 8) }, + { HRDATA (AUX, isbc208_a, 8) }, + { HRDATA (INT, isbc208_i, 8) }, + { NULL } +}; + +MTAB isbc208_mod[] = { + { UNIT_WPMODE, 0, "RW", "RW", &isbc208_set_mode }, + { UNIT_WPMODE, UNIT_WPMODE, "WP", "WP", &isbc208_set_mode }, + { 0 } +}; + +DEBTAB isbc208_debug[] = { + { "ALL", DEBUG_all }, + { "FLOW", DEBUG_flow }, + { "READ", DEBUG_read }, + { "WRITE", DEBUG_write }, + { "LEV1", DEBUG_level1 }, + { "LEV2", DEBUG_level2 }, + { "REG", DEBUG_reg }, + { NULL } +}; + +DEVICE isbc208_dev = { + "SBC208", //name + isbc208_unit, //units + isbc208_reg, //registers + isbc208_mod, //modifiers + FDD_NUM, //numunits + 16, //aradix + 32, //awidth + 1, //aincr + 16, //dradix + 8, //dwidth + NULL, //examine + NULL, //deposit + &isbc208_reset, //deposit + NULL, //boot + &isbc208_attach, //attach + NULL, //detach + NULL, //ctxt + DEV_DEBUG+DEV_DISABLE+DEV_DIS, //flags + 0, //dctrl +// DEBUG_flow + DEBUG_read + DEBUG_write, //dctrl + isbc208_debug, //debflags + NULL, //msize + NULL //lname +}; + +/* Service routines to handle simulator functions */ + +/* service routine - actually does the simulated disk I/O */ + +t_stat isbc208_svc (UNIT *uptr) +{ + int32 i, imgadr, data; + int c; + int32 bpt, bpc; + FILE *fp; + + if ((i8272_msr & CB) && cmd && (uptr->u6 == drv)) { /* execution phase */ + sim_debug (DEBUG_flow, &isbc208_dev, "isbc208_svc: Entered execution phase\n"); + switch (cmd) { + case READ: /* 0x06 */ +// printf("READ-e: fddst=%02X", fddst[uptr->u6]); + h = i8272_w3; // h = 0 or 1 + hed = i8272_w3 << 2; // hed = 0 or 4 [h << 2] + sec = i8272_w4; // sector number (1-XX) + secn = i8272_w5; // N (0-5) + spt = i8272_w6; // sectors/track + ssize = 128 << secn; // size of sector (bytes) + bpt = ssize * spt; // bytes/track + bpc = bpt * 2; // bytes/cylinder +// printf(" d=%d h=%d c=%d s=%d\n", drv, h, cyl, sec); + sim_debug (DEBUG_flow, &isbc208_dev, + "isbc208_svc: FDC read: h=%d, hed=%d, sec=%d, secn=%d, spt=%d, ssize=%04X, bpt=%04X, bpc=%04X\n", + h, hed, sec, secn, spt, ssize, bpt, bpc); + sim_debug (DEBUG_flow, &isbc208_dev, + "isbc208_svc: FDC read: d=%d h=%d c=%d s=%d N=%d spt=%d fddst=%02X\n", + drv, h, cyl, sec, secn, spt, fddst[uptr->u6]); + sim_debug (DEBUG_flow, &isbc208_dev, "\nFDC read of d=%d h=%d c=%d s=%d", + drv, h, cyl, sec); + if ((fddst[uptr->u6] & RDY) == 0) { // drive not ready + i8272_r0 = IC_ABNORM + NR + hed + drv; /* command done - Not ready error*/ + i8272_r3 = fddst[uptr->u6]; + i8272_msr |= (RQM + DIO + CB); /* enter result phase */ + sim_debug (DEBUG_flow, &isbc208_dev, "isbc208_svc: FDC read: Not Ready\n"); + } else { // get image addr for this d, h, c, s + imgadr = (cyl * bpc) + (h * bpt) + ((sec - 1) * ssize); + sim_debug (DEBUG_flow, &isbc208_dev, + "isbc208_svc: FDC read: DMA addr=%04X cnt=%04X imgadr=%04X\n", + i8237_r0, i8237_r1, imgadr); + for (i=0; i<=i8237_r1; i++) { /* copy selected sector to memory */ + data = *(isbc208_buf[uptr->u6] + (imgadr + i)); + multibus_put_mbyte(i8237_r0 + i, data); + } +//*** need to step return results IAW table 3-11 in 143078-001 + i8272_w4 = ++sec; /* next sector */ + i8272_r0 = hed + drv; /* command done - no error */ + i8272_r3 = fddst[uptr->u6]; + } + i8272_r1 = 0; + i8272_r2 = 0; + i8272_w2 = cyl; /* generate a current address mark */ + i8272_w3 = h; + if (i8272_w4 > i8272_w6) { // beyond last sector of track? + i8272_w4 = 1; // yes, set to sector 1; + if (h) { // on head one? + i8272_w2++; // yes, step cylinder + h = 0; // back to head 0 + } + } + i8272_w5 = secn; + i8272_msr |= (RQM + DIO + CB); /* enter result phase */ + rsp = wsp = 0; /* reset indexes */ + set_irq(SBC208_INT); /* set interrupt */ +// printf("READ-x: fddst=%02X\n", fddst[uptr->u6]); + break; + case WRITE: /* 0x05 */ +// printf("WRITE-e: fddst=%02X\n", fddst[uptr->u6]); + h = i8272_w3; // h = 0 or 1 + hed = i8272_w3 << 2; // hed = 0 or 4 [h << 2] + sec = i8272_w4; // sector number (1-XX) + secn = i8272_w5; // N (0-5) + spt = i8272_w6; // sectors/track + ssize = 128 << secn; // size of sector (bytes) + bpt = ssize * spt; // bytes/track + bpc = bpt * 2; // bytes/cylinder + sim_debug (DEBUG_flow, &isbc208_dev, + "isbc208_svc: FDC write: hed=%d, sec=%d, secn=%d, spt=%d, ssize=%04X, bpt=%04X, bpc=%04X\n", + hed, sec, secn, spt, ssize, bpt, bpc); + sim_debug (DEBUG_flow, &isbc208_dev, + "isbc208_svc: FDC write: d=%d h=%d c=%d s=%d N=%d spt=%d fddst=%02X\n", + drv, h, cyl, sec, secn, spt, fddst[uptr->u6]); + i8272_r1 = 0; // clear ST1 + i8272_r2 = 0; // clear ST2 + if ((fddst[uptr->u6] & RDY) == 0) { + i8272_r0 = IC_ABNORM + NR + hed + drv; /* Not ready error*/ + i8272_r3 = fddst[uptr->u6]; + i8272_msr |= (RQM + DIO + CB); /* enter result phase */ + sim_debug (DEBUG_flow, &isbc208_dev, "isbc208_svc: FDC write: Not Ready\n"); +// } else if (fddst[uptr->u6] & WP) { +// i8272_r0 = IC_ABNORM + hed + drv; /* write protect error*/ +// i8272_r1 = NW; // set not writable in ST1 +// i8272_r3 = fddst[uptr->u6] + WP; +// i8272_msr |= (RQM + DIO + CB); /* enter result phase */ +// printf("\nWrite Protected fddst[%d]=%02X\n", uptr->u6, fddst[uptr->u6]); +// if (isbc208_dev.dctrl & DEBUG_flow) +// printf("isbc208_svc: FDC write: Write Protected\n"); + } else { // get image addr for this d, h, c, s + imgadr = (cyl * bpc) + (h * bpt) + ((sec - 1) * ssize); + sim_debug (DEBUG_flow, &isbc208_dev, + "isbc208_svc: FDC write: DMA adr=%04X cnt=%04X imgadr=%04X\n", + i8237_r0, i8237_r1, imgadr); + for (i=0; i<=i8237_r1; i++) { /* copy selected memory to image */ + data = multibus_get_mbyte(i8237_r0 + i); + *(isbc208_buf[uptr->u6] + (imgadr + i)) = data; + } + //*** quick fix. Needs more thought! + fp = fopen(uptr->filename, "wb"); // write out modified image + for (i=0; icapac; i++) { + c = *(isbc208_buf[uptr->u6] + i) & 0xFF; + fputc(c, fp); + } + fclose(fp); +//*** need to step return results IAW table 3-11 in 143078-001 + i8272_w2 = cyl; /* generate a current address mark */ + i8272_w3 = hed >> 2; + i8272_w4 = ++sec; /* next sector */ + i8272_w5 = secn; + i8272_r0 = hed + drv; /* command done - no error */ + i8272_r3 = fddst[uptr->u6]; + i8272_msr |= (RQM + DIO + CB); /* enter result phase */ + } + rsp = wsp = 0; /* reset indexes */ + set_irq(SBC208_INT); /* set interrupt */ +// printf("WRITE-x: fddst=%02X\n", fddst[uptr->u6]); + break; + case FMTTRK: /* 0x0D */ + if ((fddst[uptr->u6] & RDY) == 0) { + i8272_r0 = IC_ABNORM + NR + hed + drv; /* Not ready error*/ + i8272_msr |= (RQM + DIO + CB); /* enter result phase */ + sim_debug (DEBUG_flow, &isbc208_dev, "isbc208_svc: Not Ready\n"); + } else if (fddst[uptr->u6] & WP) { + i8272_r0 = IC_ABNORM + hed + drv; /* write protect error*/ + i8272_r3 = fddst[uptr->u6] + WP; + i8272_msr |= (RQM + DIO + CB); /* enter result phase */ + sim_debug (DEBUG_flow, &isbc208_dev, "isbc208_svc: Write Protected\n"); + } else { + ; /* do nothing for now */ + i8272_msr |= (RQM + DIO + CB); /* enter result phase */ + } + rsp = wsp = 0; /* reset indexes */ + set_irq(SBC208_INT); /* set interrupt */ + break; + case SENINT: /* 0x08 */ + i8272_msr |= (RQM + DIO + CB); /* enter result phase */ + i8272_r0 = hed + drv; /* command done - no error */ + i8272_r1 = 0; + i8272_r2 = 0; + rsp = wsp = 0; /* reset indexes */ + clr_irq(SBC208_INT); /* clear interrupt */ + break; + case SENDRV: /* 0x04 */ + sim_debug (DEBUG_flow, &isbc208_dev, "isbc208_svc: FDC sense drive of disk=%d fddst=%02X\n", + drv, fddst[uptr->u6]); + i8272_msr |= (RQM + DIO + CB); /* enter result phase */ + i8272_r0 = hed + drv; /* command done - no error */ + i8272_r1 = 0; + i8272_r2 = 0; + i8272_r3 = fddst[drv]; /* drv status */ + rsp = wsp = 0; /* reset indexes */ + break; + case HOME: /* 0x07 */ +// printf("HOME-e: fddst=%02X\n", fddst[uptr->u6]); + sim_debug (DEBUG_flow, &isbc208_dev, "isbc208_svc: FDC home: disk=%d fddst=%02X\n", + drv, fddst[uptr->u6]); + if ((fddst[uptr->u6] & RDY) == 0) { + i8272_r0 = IC_ABNORM + NR + hed + drv; /* Not ready error*/ + i8272_r3 = fddst[uptr->u6]; + sim_debug (DEBUG_flow, &isbc208_dev, "isbc208_svc: Not Ready\n"); + } else { + cyl = 0; /* now on cylinder 0 */ + fddst[drv] |= T0; /* set status flag */ + i8272_r0 = SE + hed + drv; /* seek end - no error */ + } + i8272_r1 = 0; + i8272_r2 = 0; + i8272_msr &= ~(RQM + DIO + CB + hed + drv); /* execution phase done*/ + i8272_msr |= RQM; /* enter COMMAND phase */ + rsp = wsp = 0; /* reset indexes */ + set_irq(SBC208_INT); /* set interrupt */ +// printf("HOME-x: fddst=%02X\n", fddst[uptr->u6]); + break; + case SPEC: /* 0x03 */ + fddst[0] |= TS; //*** bad, bad, bad! + fddst[1] |= TS; + fddst[2] |= TS; + fddst[3] |= TS; +// printf("SPEC-e: fddst[%d]=%02X\n", uptr->u6, fddst[uptr->u6]); + sim_debug (DEBUG_flow, &isbc208_dev, + "isbc208_svc: FDC specify SRT=%d ms HUT=%d ms HLT=%d ms \n", + 16 - (drv >> 4), 16 * (drv & 0x0f), i8272_w2 & 0xfe); + i8272_r0 = hed + drv; /* command done - no error */ + i8272_r1 = 0; + i8272_r2 = 0; + i8272_msr &= ~(RQM + DIO + CB); /* execution phase done*/ + i8272_msr = 0; // force 0 for now, where does 0x07 come from? + i8272_msr |= RQM; /* enter command phase */ + rsp = wsp = 0; /* reset indexes */ +// printf("SPEC-x: fddst[%d]=%02X\n", uptr->u6, fddst[uptr->u6]); + break; + case READID: /* 0x0A */ + if ((fddst[uptr->u6] & RDY) == 0) { + i8272_r0 = IC_RC + NR + hed + drv; /* Not ready error*/ + i8272_r3 = fddst[uptr->u6]; + sim_debug (DEBUG_flow, &isbc208_dev, "isbc208_svc: Not Ready\n"); + } else { + i8272_w2 = cyl; /* generate a valid address mark */ + i8272_w3 = hed >> 2; + i8272_w4 = 1; /* always sector 1 */ + i8272_w5 = secn; + i8272_r0 = hed + drv; /* command done - no error */ + i8272_msr &= ~(RQM + DIO + CB); /* execution phase done*/ + i8272_msr |= RQM; /* enter command phase */ + } + i8272_r1 = 0; + i8272_r2 = 0; + rsp = wsp = 0; /* reset indexes */ + break; + case SEEK: /* 0x0F */ +// printf("SEEK-e: fddst=%02X\n", fddst[uptr->u6]); + sim_debug (DEBUG_flow, &isbc208_dev, "isbc208_svc: FDC seek: disk=%d cyl=%d fddst=%02X\n", + drv, i8272_w2, fddst[uptr->u6]); + if ((fddst[uptr->u6] & RDY) == 0) { /* Not ready? */ + i8272_r0 = IC_ABNORM + NR + hed + drv; /* error*/ + i8272_r3 = fddst[uptr->u6]; + sim_debug (DEBUG_flow, &isbc208_dev, "isbc208_svc: FDC seek: Not Ready\n"); + } else if (i8272_w2 >= maxcyl[uptr->u6]) { + i8272_r0 = IC_ABNORM + RDY + hed + drv; /* seek error*/ + sim_debug (DEBUG_flow, &isbc208_dev, "isbc208_svc: FDC seek: Invalid Cylinder %d\n", i8272_w2); + } else { + i8272_r0 |= SE + hed + drv; /* command done - no error */ + cyl = i8272_w2; /* new cylinder number */ + if (cyl == 0) { /* if cyl 0, set flag */ + fddst[drv] |= T0; /* set T0 status flag */ + i8272_r3 |= T0; + } else { + fddst[drv] &= ~T0; /* clear T0 status flag */ + i8272_r3 &= ~T0; + } + } + i8272_r1 = 0; + i8272_r2 = 0; + i8272_msr &= ~(RQM + DIO + CB + hed + drv); /* execution phase done*/ + i8272_msr |= RQM; /* enter command phase */ + rsp = wsp = 0; /* reset indexes */ +// set_irq(SBC208_INT); /* set interrupt */ +// printf("SEEK-x: fddst=%02X\n", fddst[uptr->u6]); + break; + default: + i8272_msr &= ~(RQM + DIO + CB); /* execution phase done*/ + i8272_msr |= RQM; /* enter command phase */ + i8272_r0 = IC_INVC + hed + drv; /* set bad command error */ + i8272_r1 = 0; + i8272_r2 = 0; + rsp = wsp = 0; /* reset indexes */ + break; + } + pcmd = cmd; /* save for result phase */ + cmd = 0; /* reset command */ + sim_debug (DEBUG_flow, &isbc208_dev, + "isbc208_svc: Exit: RSLT0 msr=%02X ST0=%02X ST1=%02X ST2=%02X ST3=%02X\n", + i8272_msr, i8272_r0, i8272_r1, i8272_r2, i8272_r3); + } + sim_activate (&isbc208_unit[uptr->u6], isbc208_unit[uptr->u6].wait); + return SCPE_OK; +} + +// read/write FDC data register +int32 isbc208_r11(int32 io, int32 data) +{ + if (io == 0) { /* read FDC data register */ + wsp = 0; /* clear write stack index */ + switch (rsp) { /* read from next stack register */ + case 0: + sim_debug (DEBUG_reg, &isbc208_dev, "i8272_r1 read as %02X\n", i8272_r1); + sim_debug (DEBUG_reg, &isbc208_dev, "i8272_r3 read as %02X\n", i8272_r3); + rsp++; /* step read stack index */ + clr_irq(SBC208_INT); /* clear interrupt */ + if (pcmd == SENDRV) { + i8272_msr = RQM; /* result phase SENDRV done */ + return i8272_r1; // SENDRV return ST1 + } + return i8272_r0; /* ST0 */ + case 1: + sim_debug (DEBUG_reg, &isbc208_dev, "i8272_r2 read as %02X\n", i8272_r2); + rsp++; /* step read stack index */ + if (pcmd == SENINT) { + i8272_msr = RQM; /* result phase SENINT done */ + return cyl; // SENINT return current cylinder + } + return i8272_r1; /* ST1 */ + case 2: + sim_debug (DEBUG_reg, &isbc208_dev, "i8272_r3 read as %02X\n", i8272_r3); + rsp++; /* step read stack index */ + return i8272_r2; /* ST2 */ + case 3: + sim_debug (DEBUG_reg, &isbc208_dev, "i8272_w2 read as %02X\n", i8272_w2); + rsp++; /* step read stack index */ + return i8272_w2; /* C - cylinder */ + case 4: + sim_debug (DEBUG_reg, &isbc208_dev, "i8272_w3 read as %02X\n", i8272_w3); + rsp++; /* step read stack index */ + return i8272_w3; /* H - head */ + case 5: + sim_debug (DEBUG_reg, &isbc208_dev, "i8272_w4 read as %02X\n", i8272_w4); + rsp++; /* step read stack index */ + return i8272_w4; /* R - sector */ + case 6: + sim_debug (DEBUG_reg, &isbc208_dev, "i8272_w5 read as %02X\n", i8272_w5); + i8272_msr = RQM; /* result phase ALL OTHERS done */ + return i8272_w5; /* N - sector size*/ + } + } else { /* write FDC data register */ + rsp = 0; /* clear read stack index */ + switch (wsp) { /* write to next stack register */ + case 0: + i8272_w0 = data; /* rws = MT + MFM + SK + cmd */ + cmd = data & 0x1F; /* save the current command */ + sim_debug (DEBUG_reg, &isbc208_dev, "i8272_w0 set to %02X\n", data); + if (cmd == SENINT) { + i8272_msr = CB; /* command phase SENINT done */ + return 0; + } + wsp++; /* step write stack index */ + break; + case 1: + i8272_w1 = data; /* rws = hed + drv */ + if (cmd != SPEC) + drv = data & 0x03; + sim_debug (DEBUG_reg, &isbc208_dev, "i8272_w1 set to %02X\n", data); + if (cmd == HOME || cmd == SENDRV || cmd == READID) { + i8272_msr = CB + hed + drv; /* command phase HOME, READID and SENDRV done */ + return 0; + } + wsp++; /* step write stack index */ + break; + case 2: + i8272_w2 = data; /* rws = C */ + sim_debug (DEBUG_reg, &isbc208_dev, "i8272_w2 set to %02X\n", data); + if (cmd == SPEC || cmd == SEEK) { + i8272_msr = CB + hed + drv; /* command phase SPECIFY and SEEK done */ + return 0; + } + wsp++; /* step write stack index */ + break; + case 3: + i8272_w3 = data; /* rw = H */ + hed = data; + wsp++; /* step write stack index */ + sim_debug (DEBUG_reg, &isbc208_dev, "i8272_w3 set to %02X\n", data); + break; + case 4: + i8272_w4 = data; /* rw = R */ + sec = data; + wsp++; /* step write stack index */ + sim_debug (DEBUG_reg, &isbc208_dev, "i8272_w4 set to %02X\n", data); + break; + case 5: + i8272_w5 = data; /* rw = N */ + sim_debug (DEBUG_reg, &isbc208_dev, "i8272_w5 set to %02X\n", data); + if (cmd == FMTTRK) { + i8272_msr = CB + hed + drv; /* command phase FMTTRK done */ + return 0; + } + wsp++; /* step write stack index */ + break; + case 6: + i8272_w6 = data; /* rw = last sector number */ + wsp++; /* step write stack index */ + sim_debug (DEBUG_reg, &isbc208_dev, "i8272_w6 set to %02X\n", data); + break; + case 7: + i8272_w7 = data; /* rw = gap length */ + wsp++; /* step write stack index */ + sim_debug (DEBUG_reg, &isbc208_dev, "i8272_w7 set to %02X\n", data); + break; + case 8: + i8272_w8 = data; /* rw = bytes to transfer */ + sim_debug (DEBUG_reg, &isbc208_dev, "i8272_w8 set to %02X\n", data); + if (cmd == READ || cmd == WRITE) + i8272_msr = CB + hed + drv; /* command phase all others done */ + break; + } + return 0; + } +} + +/* Reset routine */ + +t_stat isbc208_reset (DEVICE *dptr) +{ + reg_dev(isbc208_r0, SBC208_BASE + 0); + reg_dev(isbc208_r1, SBC208_BASE + 1); + reg_dev(isbc208_r2, SBC208_BASE + 2); + reg_dev(isbc208_r3, SBC208_BASE + 3); + reg_dev(isbc208_r4, SBC208_BASE + 4); + reg_dev(isbc208_r5, SBC208_BASE + 5); + reg_dev(isbc208_r6, SBC208_BASE + 6); + reg_dev(isbc208_r7, SBC208_BASE + 7); + reg_dev(isbc208_r8, SBC208_BASE + 8); + reg_dev(isbc208_r9, SBC208_BASE + 9); + reg_dev(isbc208_rA, SBC208_BASE + 10); + reg_dev(isbc208_rB, SBC208_BASE + 11); + reg_dev(isbc208_rC, SBC208_BASE + 12); + reg_dev(isbc208_rD, SBC208_BASE + 13); + reg_dev(isbc208_rE, SBC208_BASE + 14); + reg_dev(isbc208_rF, SBC208_BASE + 15); + reg_dev(isbc208_r10, SBC208_BASE + 16); + reg_dev(isbc208_r11, SBC208_BASE + 17); + reg_dev(isbc208_r12, SBC208_BASE + 18); + reg_dev(isbc208_r13, SBC208_BASE + 19); + reg_dev(isbc208_r14, SBC208_BASE + 20); + reg_dev(isbc208_r15, SBC208_BASE + 21); + if ((isbc208_dev.flags & DEV_DIS) == 0) + isbc208_reset1(); + return SCPE_OK; +} + +void isbc208_reset1 (void) +{ + int32 i; + UNIT *uptr; + static int flag = 1; + + if (flag) printf("iSBC 208: Initializing\n"); + for (i = 0; i < FDD_NUM; i++) { /* handle all units */ + uptr = isbc208_dev.units + i; + if (uptr->capac == 0) { /* if not configured */ +// printf(" SBC208%d: Not configured\n", i); +// if (flag) { +// printf(" ALL: \"set isbc208 en\"\n"); +// printf(" EPROM: \"att isbc2080 \"\n"); +// flag = 0; +// } + uptr->capac = 0; /* initialize unit */ + uptr->u3 = 0; + uptr->u4 = 0; + uptr->u5 = 0; + uptr->u6 = i; /* unit number - only set here! */ + fddst[i] = WP + T0 + i; /* initial drive status */ + uptr->flags |= UNIT_WPMODE; /* set WP in unit flags */ + sim_activate (&isbc208_unit[uptr->u6], isbc208_unit[uptr->u6].wait); + } else { + fddst[i] = RDY + WP + T0 + i; /* initial attach drive status */ +// printf(" SBC208%d: Configured, Attached to %s\n", i, uptr->filename); + } + } + i8237_r8 = 0; /* status */ + i8237_r9 = 0; /* command */ + i8237_rB = 0x0F; /* mask */ + i8237_rC = 0; /* request */ + i8237_rD = 0; /* first/last FF */ + i8272_msr = RQM; /* 8272 ready for start of command */ + rsp = wsp = 0; /* reset indexes */ + cmd = 0; /* clear command */ + if (flag) { + printf(" 8237 Reset\n"); + printf(" 8272 Reset\n"); + } + flag = 0; +} + +/* isbc208 attach - attach an .IMG file to a FDD */ + +t_stat isbc208_attach (UNIT *uptr, char *cptr) +{ + t_stat r; + FILE *fp; + int32 i, c = 0; + long flen; + + sim_debug (DEBUG_flow, &isbc208_dev, " isbc208_attach: Entered with cptr=%s\n", cptr); + if ((r = attach_unit (uptr, cptr)) != SCPE_OK) { + printf(" isbc208_attach: Attach error\n"); + return r; + } + fp = fopen(uptr->filename, "rb"); + if (fp == NULL) { + printf(" Unable to open disk img file %s\n", uptr->filename); + printf(" No disk image loaded!!!\n"); + } else { + printf("iSBC 208: Attach\n"); + fseek(fp, 0, SEEK_END); /* size disk image */ + flen = ftell(fp); + fseek(fp, 0, SEEK_SET); + if (isbc208_buf[uptr->u6] == NULL) { /* no buffer allocated */ + isbc208_buf[uptr->u6] = malloc(flen); + if (isbc208_buf[uptr->u6] == NULL) { + printf(" iSBC208_attach: Malloc error\n"); + return SCPE_MEM; + } + } + uptr->capac = flen; + i = 0; + c = fgetc(fp); // copy disk image into buffer + while (c != EOF) { + *(isbc208_buf[uptr->u6] + i++) = c & 0xFF; + c = fgetc(fp); + } + fclose(fp); + fddst[uptr->u6] |= RDY; /* set unit ready */ + if (flen == 368640) { /* 5" 360K DSDD */ + maxcyl[uptr->u6] = 40; + fddst[uptr->u6] |= TS; // two sided + } + else if (flen == 737280) { /* 5" 720K DSQD / 3.5" 720K DSDD */ + maxcyl[uptr->u6] = 80; + fddst[uptr->u6] |= TS; // two sided + } + else if (flen == 1228800) { /* 5" 1.2M DSHD */ + maxcyl[uptr->u6] = 80; + fddst[uptr->u6] |= TS; // two sided + } + else if (flen == 1474560) { /* 3.5" 1.44M DSHD */ + maxcyl[uptr->u6] = 80; + fddst[uptr->u6] |= TS; // two sided + } + printf(" Drive-%d: %d bytes of disk image %s loaded, fddst=%02X\n", + uptr->u6, i, uptr->filename, fddst[uptr->u6]); + } + sim_debug (DEBUG_flow, &isbc208_dev, " iSBC208_attach: Done\n"); + return SCPE_OK; +} + +/* isbc208 set mode = 8- or 16-bit data bus */ + +t_stat isbc208_set_mode (UNIT *uptr, int32 val, char *cptr, void *desc) +{ + UNIT *uptr1; + + sim_debug (DEBUG_flow, &isbc208_dev, " isbc208_set_mode: Entered with val=%08XH uptr->flags=%08X\n", + val, uptr->flags); + if (val & UNIT_WPMODE) { /* write protect */ + fddst[uptr->u6] |= WP; + uptr->flags |= val; + } else { /* read write */ + fddst[uptr->u6] &= ~WP; + uptr->flags &= ~val; + } +// printf("fddst[%d]=%02XH uptr->flags=%08X\n", uptr->u6, fddst[uptr->u6], uptr->flags); + sim_debug (DEBUG_flow, &isbc208_dev, " isbc208_set_mode: Done\n"); + return SCPE_OK; +} + +/* I/O instruction handlers, called from the CPU module when an + IN or OUT instruction is issued. + + Each function is passed an 'io' flag, where 0 means a read from + the port, and 1 means a write to the port. On input, the actual + input is passed as the return value, on output, 'data' is written + to the device. +*/ + +int32 isbc208_r0(int32 io, int32 data) +{ + if (io == 0) { /* read current address CH 0 */ + if (i8237_rD) { /* high byte */ + i8237_rD = 0; + sim_debug (DEBUG_reg, &isbc208_dev, "i8237_r0(H) read as %04X\n", i8237_r0); + return (i8237_r0 >> 8); + } else { /* low byte */ + i8237_rD++; + sim_debug (DEBUG_reg, &isbc208_dev, "i8237_r0(L) read as %04X\n", i8237_r0); + return (i8237_r0 & 0xFF); + } + } else { /* write base & current address CH 0 */ + if (i8237_rD) { /* high byte */ + i8237_rD = 0; + i8237_r0 |= (data << 8); + sim_debug (DEBUG_reg, &isbc208_dev, "i8237_r0(H) set to %04X\n", i8237_r0); + } else { /* low byte */ + i8237_rD++; + i8237_r0 = data & 0xFF; + sim_debug (DEBUG_reg, &isbc208_dev, "i8237_r0(L) set to %04X\n", i8237_r0); + } + return 0; + } +} + +int32 isbc208_r1(int32 io, int32 data) +{ + if (io == 0) { /* read current word count CH 0 */ + if (i8237_rD) { /* high byte */ + i8237_rD = 0; + sim_debug (DEBUG_reg, &isbc208_dev, "i8237_r1(H) read as %04X\n", i8237_r1); + return (i8237_r1 >> 8); + } else { /* low byte */ + i8237_rD++; + sim_debug (DEBUG_reg, &isbc208_dev, "i8237_r1(L) read as %04X\n", i8237_r1); + return (i8237_r1 & 0xFF); + } + } else { /* write base & current address CH 0 */ + if (i8237_rD) { /* high byte */ + i8237_rD = 0; + i8237_r1 |= (data << 8); + sim_debug (DEBUG_reg, &isbc208_dev, "i8237_r1(H) set to %04X\n", i8237_r1); + } else { /* low byte */ + i8237_rD++; + i8237_r1 = data & 0xFF; + sim_debug (DEBUG_reg, &isbc208_dev, "i8237_r1(L) set to %04X\n", i8237_r1); + } + return 0; + } +} + +int32 isbc208_r2(int32 io, int32 data) +{ + if (io == 0) { /* read current address CH 1 */ + if (i8237_rD) { /* high byte */ + i8237_rD = 0; + sim_debug (DEBUG_reg, &isbc208_dev, "i8237_r2(H) read as %04X\n", i8237_r2); + return (i8237_r2 >> 8); + } else { /* low byte */ + i8237_rD++; + sim_debug (DEBUG_reg, &isbc208_dev, "i8237_r2(L) read as %04X\n", i8237_r2); + return (i8237_r2 & 0xFF); + } + } else { /* write base & current address CH 1 */ + if (i8237_rD) { /* high byte */ + i8237_rD = 0; + i8237_r2 |= (data << 8); + sim_debug (DEBUG_reg, &isbc208_dev, "i8237_r2(H) set to %04X\n", i8237_r2); + } else { /* low byte */ + i8237_rD++; + i8237_r2 = data & 0xFF; + sim_debug (DEBUG_reg, &isbc208_dev, "i8237_r2(L) set to %04X\n", i8237_r2); + } + return 0; + } +} + +int32 isbc208_r3(int32 io, int32 data) +{ + if (io == 0) { /* read current word count CH 1 */ + if (i8237_rD) { /* high byte */ + i8237_rD = 0; + sim_debug (DEBUG_reg, &isbc208_dev, "i8237_r3(H) read as %04X\n", i8237_r3); + return (i8237_r3 >> 8); + } else { /* low byte */ + i8237_rD++; + sim_debug (DEBUG_reg, &isbc208_dev, "i8237_r3(L) read as %04X\n", i8237_r3); + return (i8237_r3 & 0xFF); + } + } else { /* write base & current address CH 1 */ + if (i8237_rD) { /* high byte */ + i8237_rD = 0; + i8237_r3 |= (data << 8); + sim_debug (DEBUG_reg, &isbc208_dev, "i8237_r3(H) set to %04X\n", i8237_r3); + } else { /* low byte */ + i8237_rD++; + i8237_r3 = data & 0xFF; + sim_debug (DEBUG_reg, &isbc208_dev, "i8237_r3(L) set to %04X\n", i8237_r3); + } + return 0; + } +} + +int32 isbc208_r4(int32 io, int32 data) +{ + if (io == 0) { /* read current address CH 2 */ + if (i8237_rD) { /* high byte */ + i8237_rD = 0; + sim_debug (DEBUG_reg, &isbc208_dev, "i8237_r4(H) read as %04X\n", i8237_r4); + return (i8237_r4 >> 8); + } else { /* low byte */ + i8237_rD++; + sim_debug (DEBUG_reg, &isbc208_dev, "i8237_r4(L) read as %04X\n", i8237_r4); + return (i8237_r4 & 0xFF); + } + } else { /* write base & current address CH 2 */ + if (i8237_rD) { /* high byte */ + i8237_rD = 0; + i8237_r4 |= (data << 8); + sim_debug (DEBUG_reg, &isbc208_dev, "i8237_r4(H) set to %04X\n", i8237_r4); + } else { /* low byte */ + i8237_rD++; + i8237_r4 = data & 0xFF; + sim_debug (DEBUG_reg, &isbc208_dev, "i8237_r4(L) set to %04X\n", i8237_r4); + } + return 0; + } +} + +int32 isbc208_r5(int32 io, int32 data) +{ + if (io == 0) { /* read current word count CH 2 */ + if (i8237_rD) { /* high byte */ + i8237_rD = 0; + sim_debug (DEBUG_reg, &isbc208_dev, "i8237_r5(H) read as %04X\n", i8237_r5); + return (i8237_r5 >> 8); + } else { /* low byte */ + i8237_rD++; + sim_debug (DEBUG_reg, &isbc208_dev, "i8237_r5(L) read as %04X\n", i8237_r5); + return (i8237_r5 & 0xFF); + } + } else { /* write base & current address CH 2 */ + if (i8237_rD) { /* high byte */ + i8237_rD = 0; + i8237_r5 |= (data << 8); + sim_debug (DEBUG_reg, &isbc208_dev, "i8237_r5(H) set to %04X\n", i8237_r5); + } else { /* low byte */ + i8237_rD++; + i8237_r5 = data & 0xFF; + sim_debug (DEBUG_reg, &isbc208_dev, "i8237_r5(L) set to %04X\n", i8237_r5); + } + return 0; + } +} + +int32 isbc208_r6(int32 io, int32 data) +{ + if (io == 0) { /* read current address CH 3 */ + if (i8237_rD) { /* high byte */ + i8237_rD = 0; + sim_debug (DEBUG_reg, &isbc208_dev, "i8237_r6(H) read as %04X\n", i8237_r6); + return (i8237_r6 >> 8); + } else { /* low byte */ + i8237_rD++; + sim_debug (DEBUG_reg, &isbc208_dev, "i8237_r6(L) read as %04X\n", i8237_r6); + return (i8237_r6 & 0xFF); + } + } else { /* write base & current address CH 3 */ + if (i8237_rD) { /* high byte */ + i8237_rD = 0; + i8237_r6 |= (data << 8); + sim_debug (DEBUG_reg, &isbc208_dev, "i8237_r6(H) set to %04X\n", i8237_r6); + } else { /* low byte */ + i8237_rD++; + i8237_r6 = data & 0xFF; + sim_debug (DEBUG_reg, &isbc208_dev, "i8237_r6(L) set to %04X\n", i8237_r6); + } + return 0; + } +} + +int32 isbc208_r7(int32 io, int32 data) +{ + if (io == 0) { /* read current word count CH 3 */ + if (i8237_rD) { /* high byte */ + i8237_rD = 0; + sim_debug (DEBUG_reg, &isbc208_dev, "i8237_r7(H) read as %04X\n", i8237_r7); + return (i8237_r7 >> 8); + } else { /* low byte */ + i8237_rD++; + sim_debug (DEBUG_reg, &isbc208_dev, "i8237_r7(L) read as %04X\n", i8237_r7); + return (i8237_r7 & 0xFF); + } + } else { /* write base & current address CH 3 */ + if (i8237_rD) { /* high byte */ + i8237_rD = 0; + i8237_r7 |= (data << 8); + sim_debug (DEBUG_reg, &isbc208_dev, "i8237_r7(H) set to %04X\n", i8237_r7); + } else { /* low byte */ + i8237_rD++; + i8237_r7 = data & 0xFF; + sim_debug (DEBUG_reg, &isbc208_dev, "i8237_r7(L) set to %04X\n", i8237_r7); + } + return 0; + } +} + +int32 isbc208_r8(int32 io, int32 data) +{ + if (io == 0) { /* read status register */ + sim_debug (DEBUG_reg, &isbc208_dev, "i8237_r8 (status) read as %02X\n", i8237_r8); + return (i8237_r8); + } else { /* write command register */ + i8237_r9 = data & 0xFF; + sim_debug (DEBUG_reg, &isbc208_dev, "i8237_r9 (command) set to %02X\n", i8237_r9); + return 0; + } +} + +int32 isbc208_r9(int32 io, int32 data) +{ + if (io == 0) { + sim_debug (DEBUG_reg, &isbc208_dev, "Illegal read of isbc208_r9\n"); + return 0; + } else { /* write request register */ + i8237_rC = data & 0xFF; + sim_debug (DEBUG_reg, &isbc208_dev, "i8237_rC (request) set to %02X\n", i8237_rC); + return 0; + } +} + +int32 isbc208_rA(int32 io, int32 data) +{ + if (io == 0) { + sim_debug (DEBUG_reg, &isbc208_dev, "Illegal read of isbc208_rA\n"); + return 0; + } else { /* write single mask register */ + switch(data & 0x03) { + case 0: + if (data & 0x04) + i8237_rB |= 1; + else + i8237_rB &= ~1; + break; + case 1: + if (data & 0x04) + i8237_rB |= 2; + else + i8237_rB &= ~2; + break; + case 2: + if (data & 0x04) + i8237_rB |= 4; + else + i8237_rB &= ~4; + break; + case 3: + if (data & 0x04) + i8237_rB |= 8; + else + i8237_rB &= ~8; + break; + } + sim_debug (DEBUG_reg, &isbc208_dev, "i8237_rB (mask) set to %02X\n", i8237_rB); + return 0; + } +} + +int32 isbc208_rB(int32 io, int32 data) +{ + if (io == 0) { + sim_debug (DEBUG_reg, &isbc208_dev, "Illegal read of isbc208_rB\n"); + return 0; + } else { /* write mode register */ + i8237_rA = data & 0xFF; + sim_debug (DEBUG_reg, &isbc208_dev, "i8237_rA (mode) set to %02X\n", i8237_rA); + return 0; + } +} + +int32 isbc208_rC(int32 io, int32 data) +{ + if (io == 0) { + sim_debug (DEBUG_reg, &isbc208_dev, "Illegal read of isbc208_rC\n"); + return 0; + } else { /* clear byte pointer FF */ + i8237_rD = 0; + sim_debug (DEBUG_reg, &isbc208_dev, "i8237_rD (FF) cleared\n"); + return 0; + } +} + +int32 isbc208_rD(int32 io, int32 data) +{ + if (io == 0) { /* read temporary register */ + sim_debug (DEBUG_reg, &isbc208_dev, "Illegal read of isbc208_rD\n"); + return 0; + } else { /* master clear */ + isbc208_reset1(); + sim_debug (DEBUG_reg, &isbc208_dev, "i8237 master clear\n"); + return 0; + } +} + +int32 isbc208_rE(int32 io, int32 data) +{ + if (io == 0) { + sim_debug (DEBUG_reg, &isbc208_dev, "Illegal read of isbc208_rE\n"); + return 0; + } else { /* clear mask register */ + i8237_rB = 0; + sim_debug (DEBUG_reg, &isbc208_dev, "i8237_rB (mask) cleared\n"); + return 0; + } +} + +int32 isbc208_rF(int32 io, int32 data) +{ + if (io == 0) { + sim_debug (DEBUG_reg, &isbc208_dev, "Illegal read of isbc208_rF\n"); + return 0; + } else { /* write all mask register bits */ + i8237_rB = data & 0x0F; + sim_debug (DEBUG_reg, &isbc208_dev, "i8237_rB (mask) set to %02X\n", i8237_rB); + return 0; + } +} + +int32 isbc208_r10(int32 io, int32 data) +{ + if (io == 0) { /* read FDC status register */ + sim_debug (DEBUG_reg, &isbc208_dev, "i8272_msr read as %02X\n", i8272_msr); + return i8272_msr; + } else { + sim_debug (DEBUG_reg, &isbc208_dev, "Illegal write to isbc208_r10\n"); + return 0; + } +} + +int32 isbc208_r12(int32 io, int32 data) +{ + if (io == 0) { /* read interrupt status */ + sim_debug (DEBUG_reg, &isbc208_dev, "isbc208_r12 read as %02X\n", isbc208_i); + return (isbc208_i); + } else { /* write controller auxillary port */ + isbc208_a = data & 0xFF; + sim_debug (DEBUG_reg, &isbc208_dev, "isbc208_r12 set to %02X\n", isbc208_a); + return 0; + } +} + +int32 isbc208_r13(int32 io, int32 data) +{ + if (io == 0) { + sim_debug (DEBUG_reg, &isbc208_dev, "Illegal read of isbc208_r13\n"); + return 0; + } else { /* reset controller */ + isbc208_reset1(); + sim_debug (DEBUG_reg, &isbc208_dev, "isbc208_r13 controller reset\n"); + return 0; + } +} + +int32 isbc208_r14(int32 io, int32 data) +{ + if (io == 0) { + sim_debug (DEBUG_reg, &isbc208_dev, "Illegal read of isbc208_r14\n"); + return 0; + } else { /* Low-Byte Segment Address Register */ + isbc208_sr = data & 0xFF; + sim_debug (DEBUG_reg, &isbc208_dev, "isbc208_sr(L) set to %02X\n", data & 0xFF); + return 0; + } +} + +int32 isbc208_r15(int32 io, int32 data) +{ + if (io == 0) { + sim_debug (DEBUG_reg, &isbc208_dev, "Illegal read of isbc208_r15\n"); + return 0; + } else { /* High-Byte Segment Address Register */ + isbc208_sr |= data << 8; + sim_debug (DEBUG_reg, &isbc208_dev, "isbc208_sr(H) set to %02X\n", data); + return 0; + } +} + +/* end of isbc208.c */ diff --git a/MDS-800/common/iSBC80-10.c b/isys8010/common/mds-800.c similarity index 100% rename from MDS-800/common/iSBC80-10.c rename to isys8010/common/mds-800.c diff --git a/MDS-800/common/multibus.c b/isys8010/common/multibus.c similarity index 84% rename from MDS-800/common/multibus.c rename to isys8010/common/multibus.c index 6821103a..28428564 100644 --- a/MDS-800/common/multibus.c +++ b/isys8010/common/multibus.c @@ -2,32 +2,38 @@ Copyright (c) 2010, William A. Beech - Permission is hereby granted, free of charge, to any person obtaining a - copy of this software and associated documentation files (the "Software"), - to deal in the Software without restriction, including without limitation - the rights to use, copy, modify, merge, publish, distribute, sublicense, - and/or sell copies of the Software, and to permit persons to whom the - Software is furnished to do so, subject to the following conditions: + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: - The above copyright notice and this permission notice shall be included in - all copies or substantial portions of the Software. + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - WILLIAM A. BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + WILLIAM A. BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - Except as contained in this notice, the name of William A. Beech shall not be - used in advertising or otherwise to promote the sale, use or other dealings - in this Software without prior written authorization from William A. Beech. + Except as contained in this notice, the name of William A. Beech shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from William A. Beech. - This software was written by Bill Beech, Dec 2010, to allow emulation of Multibus - Computer Systems. + MODIFICATIONS: + + ?? ??? 10 - Original file. + 16 Dec 12 - Modified to use isbc_80_10.cfg file to set base and size. + 24 Apr 15 -- Modified to use simh_debug + + NOTES: + + This software was written by Bill Beech, Dec 2010, to allow emulation of Multibus + Computer Systems. - ?? ??? 10 - Original file. - 16 Dec 12 - Modified to use isbc_80_10.cfg file to set base and size. */ #include "system_defs.h" @@ -285,4 +291,5 @@ void multibus_put_mword(int32 addr, int32 val) multibus_put_mbyte(addr+1, val << 8); } +/* end of multibus.c */ diff --git a/MDS-800/common/pata.c b/isys8010/common/pata.c similarity index 100% rename from MDS-800/common/pata.c rename to isys8010/common/pata.c diff --git a/MDS-800/System_80-10/System_80-10.vsd b/isys8010/isys8010/System_80-10.vsd similarity index 100% rename from MDS-800/System_80-10/System_80-10.vsd rename to isys8010/isys8010/System_80-10.vsd diff --git a/MDS-800/MDS-800/functional description.vsd b/isys8010/isys8010/functional description.vsd similarity index 100% rename from MDS-800/MDS-800/functional description.vsd rename to isys8010/isys8010/functional description.vsd diff --git a/MDS-800/System_80-10/system_80_10.cfg b/isys8010/isys8010/isys8010.cfg similarity index 100% rename from MDS-800/System_80-10/system_80_10.cfg rename to isys8010/isys8010/isys8010.cfg diff --git a/MDS-800/MDS-800/Mds-800.txt b/isys8010/isys8010/isys8010.txt similarity index 100% rename from MDS-800/MDS-800/Mds-800.txt rename to isys8010/isys8010/isys8010.txt diff --git a/MDS-800/System_80-10/system_80_10_sys.c b/isys8010/isys8010/isys8010_sys.c similarity index 98% rename from MDS-800/System_80-10/system_80_10_sys.c rename to isys8010/isys8010/isys8010_sys.c index 21128265..69d7e8b7 100644 --- a/MDS-800/System_80-10/system_80_10_sys.c +++ b/isys8010/isys8010/isys8010_sys.c @@ -1,4 +1,4 @@ -/* system_80_10_sys.c: multibus system interface +/* sys-8010_sys.c: multibus system interface Copyright (c) 2010, William A. Beech diff --git a/MDS-800/System_80-10/system_defs.h b/isys8010/isys8010/system_defs.h similarity index 51% rename from MDS-800/System_80-10/system_defs.h rename to isys8010/isys8010/system_defs.h index 9ee659da..82b46ab3 100644 --- a/MDS-800/System_80-10/system_defs.h +++ b/isys8010/isys8010/system_defs.h @@ -2,26 +2,26 @@ Copyright (c) 2010, William A. Beech - Permission is hereby granted, free of charge, to any person obtaining a - copy of this software and associated documentation files (the "Software"), - to deal in the Software without restriction, including without limitation - the rights to use, copy, modify, merge, publish, distribute, sublicense, - and/or sell copies of the Software, and to permit persons to whom the - Software is furnished to do so, subject to the following conditions: + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: - The above copyright notice and this permission notice shall be included in - all copies or substantial portions of the Software. + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - William A. Beech BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + William A. Beech BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - Except as contained in this notice, the name of William A. Beech shall not be - used in advertising or otherwise to promote the sale, use or other dealings - in this Software without prior written authorization from William A. Beech. + Except as contained in this notice, the name of William A. Beech shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from William A. Beech. ?? ??? 10 - Original file. 16 Dec 12 - Modified to use isbc_80_10.cfg file to set base and size. @@ -29,8 +29,8 @@ #include #include -#include "system_80_10.cfg" /* Intel System 80/10 configuration */ -#include "sim_defs.h" /* simulator defns */ +#include "isys8010.cfg" /* Intel System 80/10 configuration */ +#include "sim_defs.h" /* simulator defns */ /* multibus interrupt definitions */ diff --git a/makefile b/makefile index d6826150..59c44de6 100644 --- a/makefile +++ b/makefile @@ -1194,6 +1194,7 @@ SDS = ${SDSD}/sds_cpu.c ${SDSD}/sds_drm.c ${SDSD}/sds_dsk.c ${SDSD}/sds_io.c \ ${SDSD}/sds_stddev.c ${SDSD}/sds_sys.c SDS_OPT = -I ${SDSD} + SWTP6800D = swtp6800/swtp6800 SWTP6800C = swtp6800/common SWTP6800MP-A = ${SWTP6800C}/mp-a.c ${SWTP6800C}/m6800.c ${SWTP6800C}/m6810.c \ @@ -1204,11 +1205,23 @@ SWTP6800MP-A2 = ${SWTP6800C}/mp-a2.c ${SWTP6800C}/m6800.c ${SWTP6800C}/m6810.c \ ${SWTP6800C}/mp-b2.c ${SWTP6800C}/mp-8m.c ${SWTP6800C}/i2716.c SWTP6800_OPT = -I ${SWTP6800D} + +ISYS8010D = isys8010/isys8010 +ISYS8010C = isys8010/common +ISYS8010 = ${ISYS8010C}/i8080.c ${ISYS8010D}/isys8010_sys.c \ + ${ISYS8010C}/i8251.c ${ISYS8010C}/i8255.c \ + ${ISYS8010C}/ieprom.c ${ISYS8010C}/iram8.c \ + ${ISYS8010C}/multibus.c ${ISYS8010C}/isbc80-10.c \ + ${ISYS8010C}/isbc064.c ${ISYS8010C}/isbc208.c +ISYS8010_OPT = -I ${ISYS8010D} + + TX0D = TX-0 TX0 = ${TX0D}/tx0_cpu.c ${TX0D}/tx0_dpy.c ${TX0D}/tx0_stddev.c \ ${TX0D}/tx0_sys.c ${TX0D}/tx0_sys_orig.c ${DISPLAYL} TX0_OPT = -I ${TX0D} $(DISPLAY_OPT) + SSEMD = SSEM SSEM = ${SSEMD}/ssem_cpu.c ${SSEMD}/ssem_sys.c SSEM_OPT = -I ${SSEMD} @@ -1301,7 +1314,7 @@ ALL = pdp1 pdp4 pdp7 pdp8 pdp9 pdp15 pdp11 pdp10 \ vax microvax3900 microvax1 rtvax1000 microvax2 vax730 vax750 vax780 vax8600 \ nova eclipse hp2100 i1401 i1620 s3 altair altairz80 gri \ i7094 ibm1130 id16 id32 sds lgp h316 \ - swtp6800mp-a swtp6800mp-a2 tx-0 ssem + swtp6800mp-a swtp6800mp-a2 tx-0 ssem isys8010 all : ${ALL} @@ -1551,6 +1564,13 @@ ${BIN}swtp6800mp-a2${EXE} : ${SWTP6800MP-A2} ${SIM} ${BUILD_ROMS} ${MKDIRBIN} ${CC} ${SWTP6800MP-A2} ${SIM} ${SWTP6800_OPT} $(CC_OUTSPEC) ${LDFLAGS} + +isys8010: ${BIN}isys8010${EXE} + +${BIN}isys8010${EXE} : ${ISYS8010} ${SIM} ${BUILD_ROMS} + ${MKDIRBIN} + ${CC} ${ISYS8010} ${SIM} ${ISYS8010_OPT} $(CC_OUTSPEC) ${LDFLAGS} + tx-0 : ${BIN}tx-0${EXE} ${BIN}tx-0${EXE} : ${TX0} ${SIM} diff --git a/swtp6800/common/bootrom.c b/swtp6800/common/bootrom.c index 0340a412..8bde4039 100644 --- a/swtp6800/common/bootrom.c +++ b/swtp6800/common/bootrom.c @@ -2,41 +2,48 @@ Copyright (c) 2010-2012, William A. Beech - Permission is hereby granted, free of charge, to any person obtaining a - copy of this software and associated documentation files (the "Software"), - to deal in the Software without restriction, including without limitation - the rights to use, copy, modify, merge, publish, distribute, sublicense, - and/or sell copies of the Software, and to permit persons to whom the - Software is furnished to do so, subject to the following conditions: + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: - The above copyright notice and this permission notice shall be included in - all copies or substantial portions of the Software. + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - WILLIAM A. BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + WILLIAM A. BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - Except as contained in this notice, the name of William A. Beech shall not be - used in advertising or otherwise to promote the sale, use or other dealings - in this Software without prior written authorization from William A. Beech. + Except as contained in this notice, the name of William A. Beech shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from William A. Beech. - These functions support a single simulated 2704 to 2764 EPROM device on - an 8-bit computer system.. This device allows the buffer to be loaded from - a binary file containing the emulated EPROM code. + MODIFICATIONS: - These functions support a simulated 2704, 2708, 2716, 2732 or 2764 EPROM - device on a CPU board. The byte get and put routines use an offset into - the boot EPROM image to locate the proper byte. This allows another device - to set the base address for the boot EPROM. The device type is stored as - a binary number in the first three unit flag bits. + 23 Apr 15 -- Modified to use simh_debug + + NOTES: + + These functions support a single simulated 2704 to 2764 EPROM device on + an 8-bit computer system.. This device allows the buffer to be loaded from + a binary file containing the emulated EPROM code. + + These functions support a simulated 2704, 2708, 2716, 2732 or 2764 EPROM + device on a CPU board. The byte get and put routines use an offset into + the boot EPROM image to locate the proper byte. This allows another device + to set the base address for the boot EPROM. The device type is stored as + a binary number in the first three unit flag bits. + + This device uses a dynamically allocated buffer to hold the EPROM image. + A call to BOOTROM_config will free the current buffer. A call to + BOOTROM_reset will allocate a new buffer of BOOTROM_unit.capac bytes. A + call to BOOTROM_attach will load the buffer with the EPROM image. - This device uses a dynamically allocated buffer to hold the EPROM image. - A call to BOOTROM_config will free the current buffer. A call to - BOOTROM_reset will allocate a new buffer of BOOTROM_unit.capac bytes. A - call to BOOTROM_attach will load the buffer with the EPROM image. */ #include @@ -129,11 +136,9 @@ t_stat BOOTROM_attach (UNIT *uptr, char *cptr) t_addr image_size, capac; int i; - if (BOOTROM_dev.dctrl & DEBUG_flow) - printf("BOOTROM_attach: cptr=%s\n", cptr); + sim_debug (DEBUG_flow, &BOOTROM_dev, "BOOTROM_attach: cptr=%s\n", cptr); if ((r = attach_unit (uptr, cptr)) != SCPE_OK) { - if (BOOTROM_dev.dctrl & DEBUG_flow) - printf("BOOTROM_attach: Error\n"); + sim_debug (DEBUG_flow, &BOOTROM_dev, "BOOTROM_attach: Error\n"); return r; } image_size = (t_addr)sim_fsize_ex (BOOTROM_unit.fileref); @@ -141,11 +146,10 @@ t_stat BOOTROM_attach (UNIT *uptr, char *cptr) if (i > (UNIT_2764>>UNIT_V_MSIZE)) { detach_unit (uptr); return SCPE_ARG; - } + } uptr->flags &= ~UNIT_MSIZE; uptr->flags |= (i << UNIT_V_MSIZE); - if (BOOTROM_dev.dctrl & DEBUG_flow) - printf("BOOTROM_attach: Done\n"); + sim_debug (DEBUG_flow, &BOOTROM_dev, "BOOTROM_attach: Done\n"); return (BOOTROM_reset (NULL)); } @@ -153,11 +157,9 @@ t_stat BOOTROM_attach (UNIT *uptr, char *cptr) t_stat BOOTROM_config (UNIT *uptr, int32 val, char *cptr, void *desc) { - if (BOOTROM_dev.dctrl & DEBUG_flow) /* entry message */ - printf("BOOTROM_config: val=%d\n", val); + sim_debug (DEBUG_flow, &BOOTROM_dev, "BOOTROM_config: val=%d\n", val); if ((val < UNIT_NONE) || (val > UNIT_2764)) { /* valid param? */ - if (BOOTROM_dev.dctrl & DEBUG_flow) /* No */ - printf("BOOTROM_config: Parameter error\n"); + sim_debug (DEBUG_flow, &BOOTROM_dev, "BOOTROM_config: Parameter error\n"); return SCPE_ARG; } if (val == UNIT_NONE) @@ -168,11 +170,9 @@ t_stat BOOTROM_config (UNIT *uptr, int32 val, char *cptr, void *desc) free (BOOTROM_unit.filebuf); BOOTROM_unit.filebuf = NULL; } - if (BOOTROM_dev.dctrl & DEBUG_flow) /* status message */ - printf("BOOTROM_config: BOOTROM_unit.capac=%d\n", + sim_debug (DEBUG_flow, &BOOTROM_dev, "BOOTROM_config: BOOTROM_unit.capac=%d\n", BOOTROM_unit.capac); - if (BOOTROM_dev.dctrl & DEBUG_flow) /* exit message */ - printf("BOOTROM_config: Done\n"); + sim_debug (DEBUG_flow, &BOOTROM_dev, "BOOTROM_config: Done\n"); return SCPE_OK; } @@ -184,15 +184,13 @@ t_stat BOOTROM_reset (DEVICE *dptr) int c; FILE *fp; - if (BOOTROM_dev.dctrl & DEBUG_flow) - printf("BOOTROM_reset: \n"); + sim_debug (DEBUG_flow, &BOOTROM_dev, "BOOTROM_reset: \n"); if ((BOOTROM_unit.flags & UNIT_MSIZE) == 0) { /* if none selected */ // printf(" EPROM: Defaulted to None\n"); // printf(" \"set eprom NONE | 2704 | 2708 | 2716 | 2732 | 2764\"\n"); // printf(" \"att eprom \"\n"); BOOTROM_unit.capac = 0; /* set EPROM size to 0 */ - if (BOOTROM_dev.dctrl & DEBUG_flow) - printf("BOOTROM_reset: Done1\n"); + sim_debug (DEBUG_flow, &BOOTROM_dev, "BOOTROM_reset: Done1\n"); return SCPE_OK; } /* if attached */ // printf(" EPROM: Initializing [%04X-%04XH]\n", @@ -200,8 +198,7 @@ t_stat BOOTROM_reset (DEVICE *dptr) if (BOOTROM_unit.filebuf == NULL) { /* no buffer allocated */ BOOTROM_unit.filebuf = calloc(1, BOOTROM_unit.capac); /* allocate EPROM buffer */ if (BOOTROM_unit.filebuf == NULL) { - if (BOOTROM_dev.dctrl & DEBUG_flow) - printf("BOOTROM_reset: Malloc error\n"); + sim_debug (DEBUG_flow, &BOOTROM_dev, "BOOTROM_reset: Malloc error\n"); return SCPE_MEM; } } @@ -231,8 +228,7 @@ t_stat BOOTROM_reset (DEVICE *dptr) } fclose(fp); // printf("\t%d bytes of ROM image %s loaded\n", j, BOOTROM_unit.filename); - if (BOOTROM_dev.dctrl & DEBUG_flow) - printf("BOOTROM_reset: Done2\n"); + sim_debug (DEBUG_flow, &BOOTROM_dev, "BOOTROM_reset: Done2\n"); return SCPE_OK; } @@ -243,20 +239,16 @@ int32 BOOTROM_get_mbyte(int32 offset) int32 val; if (BOOTROM_unit.filebuf == NULL) { - if (BOOTROM_dev.dctrl & DEBUG_read) - printf("BOOTROM_get_mbyte: EPROM not configured\n"); + sim_debug (DEBUG_read, &BOOTROM_dev, "BOOTROM_get_mbyte: EPROM not configured\n"); return 0xFF; } - if (BOOTROM_dev.dctrl & DEBUG_read) - printf("BOOTROM_get_mbyte: offset=%04X\n", offset); + sim_debug (DEBUG_read, &BOOTROM_dev, "BOOTROM_get_mbyte: offset=%04X\n", offset); if ((t_addr)offset > BOOTROM_unit.capac) { - if (BOOTROM_dev.dctrl & DEBUG_read) - printf("BOOTROM_get_mbyte: EPROM reference beyond ROM size\n"); + sim_debug (DEBUG_read, &BOOTROM_dev, "BOOTROM_get_mbyte: EPROM reference beyond ROM size\n"); return 0xFF; } val = *((uint8 *)(BOOTROM_unit.filebuf) + offset) & 0xFF; - if (BOOTROM_dev.dctrl & DEBUG_read) - printf("BOOTROM_get_mbyte: Normal val=%02X\n", val); + sim_debug (DEBUG_read, &BOOTROM_dev, "BOOTROM_get_mbyte: Normal val=%02X\n", val); return val; } diff --git a/swtp6800/common/dc-4.c b/swtp6800/common/dc-4.c index 0c2f0b96..0da08b43 100644 --- a/swtp6800/common/dc-4.c +++ b/swtp6800/common/dc-4.c @@ -2,216 +2,222 @@ Copyright (c) 2005-2012, William A. Beech - Permission is hereby granted, free of charge, to any person obtaining a - copy of this software and associated documentation files (the "Software"), - to deal in the Software without restriction, including without limitation - the rights to use, copy, modify, merge, publish, distribute, sublicense, - and/or sell copies of the Software, and to permit persons to whom the - Software is furnished to do so, subject to the following conditions: + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: - The above copyright notice and this permission notice shall be included in - all copies or substantial portions of the Software. + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - WILLIAM A BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + WILLIAM A BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - Except as contained in this notice, the name of William A. Beech shall not - be used in advertising or otherwise to promote the sale, use or other dealings - in this Software without prior written authorization from William A. Beech. + Except as contained in this notice, the name of William A. Beech shall not + be used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from William A. Beech. - The DC-4 is a 5-inch floppy controller which can control up - to 4 daisy-chained 5-inch floppy drives. The controller is based on - the Western Digital 1797 Floppy Disk Controller (FDC) chip. This - file only emulates the minimum DC-4 functionality to interface with - the virtual disk file. + MODIFICATIONS: - The floppy controller is interfaced to the CPU by use of 5 memory - addreses. These are SS-30 slot numbers 5 and 6 (0x8014-0x801B). + 23 Apr 15 -- Modified to use simh_debug - Address Mode Function - ------- ---- -------- + NOTES: - 0x8014 Read Returns FDC interrupt status - 0x8014 Write Selects the drive/head/motor control - 0x8018 Read Returns status of FDC - 0x8018 Write FDC command register - 0x8019 Read Returns FDC track register - 0x8019 Write Set FDC track register - 0x801A Read Returns FDC sector register - 0x801A Write Set FDC sector register - 0x801B Read Read data - 0x801B Write Write data + The DC-4 is a 5-inch floppy controller which can control up + to 4 daisy-chained 5-inch floppy drives. The controller is based on + the Western Digital 1797 Floppy Disk Controller (FDC) chip. This + file only emulates the minimum DC-4 functionality to interface with + the virtual disk file. - Drive Select Read (0x8014): + The floppy controller is interfaced to the CPU by use of 5 memory + addreses. These are SS-30 slot numbers 5 and 6 (0x8014-0x801B). - +---+---+---+---+---+---+---+---+ - | I | D | X | X | X | X | X | X | - +---+---+---+---+---+---+---+---+ + Address Mode Function + ------- ---- -------- - I = Set indicates an interrupt request from the FDC pending. - D = DRQ pending - same as bit 1 of FDC status register. + 0x8014 Read Returns FDC interrupt status + 0x8014 Write Selects the drive/head/motor control + 0x8018 Read Returns status of FDC + 0x8018 Write FDC command register + 0x8019 Read Returns FDC track register + 0x8019 Write Set FDC track register + 0x801A Read Returns FDC sector register + 0x801A Write Set FDC sector register + 0x801B Read Read data + 0x801B Write Write data - Drive Select Write (0x8014): + Drive Select Read (0x8014): - +---+---+---+---+---+---+---+---+ - | M | S | X | X | X | X | Device| - +---+---+---+---+---+---+---+---+ + +---+---+---+---+---+---+---+---+ + | I | D | X | X | X | X | X | X | + +---+---+---+---+---+---+---+---+ - M = If this bit is 1, the one-shot is triggered/retriggered to - start/keep the motors on. - S = Side select. If set, side one is selected otherwise side zero - is selected. - X = not used - Device = value 0 thru 3, selects drive 0-3 to be controlled. + I = Set indicates an interrupt request from the FDC pending. + D = DRQ pending - same as bit 1 of FDC status register. - Drive Status Read (0x8018): + Drive Select Write (0x8014): - +---+---+---+---+---+---+---+---+ - | R | P | H | S | C | L | D | B | - +---+---+---+---+---+---+---+---+ + +---+---+---+---+---+---+---+---+ + | M | S | X | X | X | X | Device| + +---+---+---+---+---+---+---+---+ - B - When 1, the controller is busy. - D - When 1, index mark detected (type I) or data request - read data - ready/write data empty (type II or III). - H - When 1, track 0 (type I) or lost data (type II or III). - C - When 1, crc error detected. - S - When 1, seek (type I) or RNF (type II or III) error. - H - When 1, head is currently loaded (type I) or record type/ - write fault (type II or III). - P - When 1, indicates that diskette is write-protected. - R - When 1, drive is not ready. + M = If this bit is 1, the one-shot is triggered/retriggered to + start/keep the motors on. + S = Side select. If set, side one is selected otherwise side zero + is selected. + X = not used + Device = value 0 thru 3, selects drive 0-3 to be controlled. - Drive Control Write (0x8018) for type I commands: + Drive Status Read (0x8018): - +---+---+---+---+---+---+---+---+ - | 0 | S2| S1| S0| H | V | R1| R0| - +---+---+---+---+---+---+---+---+ + +---+---+---+---+---+---+---+---+ + | R | P | H | S | C | L | D | B | + +---+---+---+---+---+---+---+---+ - R0/R1 - Selects the step rate. - V - When 1, verify on destination track. - H - When 1, loads head to drive surface. - S0/S1/S2 = 000 - home. - 001 - seek track in data register. - 010 - step without updating track register. - 011 - step and update track register. - 100 - step in without updating track register. - 101 - step in and update track register. - 110 - step out without updating track register. - 111 - step out and update track register. + B - When 1, the controller is busy. + D - When 1, index mark detected (type I) or data request - read data + ready/write data empty (type II or III). + H - When 1, track 0 (type I) or lost data (type II or III). + C - When 1, crc error detected. + S - When 1, seek (type I) or RNF (type II or III) error. + H - When 1, head is currently loaded (type I) or record type/ + write fault (type II or III). + P - When 1, indicates that diskette is write-protected. + R - When 1, drive is not ready. - Drive Control Write (0x8018) for type II commands: + Drive Control Write (0x8018) for type I commands: - +---+---+---+---+---+---+---+---+ - | 1 | 0 | T | M | S | E | B | A | - +---+---+---+---+---+---+---+---+ + +---+---+---+---+---+---+---+---+ + | 0 | S2| S1| S0| H | V | R1| R0| + +---+---+---+---+---+---+---+---+ - A - Zero for read, 1 on write deleted data mark else data mark. - B - When 1, shifts sector length field definitions one place. - E - When, delay operation 15 ms, 0 no delay. - S - When 1, select side 1, 0 select side 0. - M - When 1, multiple records, 0 for single record. - T - When 1, write command, 0 for read. + R0/R1 - Selects the step rate. + V - When 1, verify on destination track. + H - When 1, loads head to drive surface. + S0/S1/S2 = 000 - home. + 001 - seek track in data register. + 010 - step without updating track register. + 011 - step and update track register. + 100 - step in without updating track register. + 101 - step in and update track register. + 110 - step out without updating track register. + 111 - step out and update track register. - Drive Control Write (0x8018) for type III commands: + Drive Control Write (0x8018) for type II commands: - +---+---+---+---+---+---+---+---+ - | 1 | 1 | T0| T1| 0 | E | 0 | 0 | - +---+---+---+---+---+---+---+---+ + +---+---+---+---+---+---+---+---+ + | 1 | 0 | T | M | S | E | B | A | + +---+---+---+---+---+---+---+---+ - E - When, delay operation 15 ms, 0 no delay. - T0/T1 - 00 - read address command. - 10 - read track command. - 11 - write track command. + A - Zero for read, 1 on write deleted data mark else data mark. + B - When 1, shifts sector length field definitions one place. + E - When, delay operation 15 ms, 0 no delay. + S - When 1, select side 1, 0 select side 0. + M - When 1, multiple records, 0 for single record. + T - When 1, write command, 0 for read. - Tracks are numbered from 0 up to one minus the last track in the 1797! + Drive Control Write (0x8018) for type III commands: - Track Register Read (0x8019): + +---+---+---+---+---+---+---+---+ + | 1 | 1 | T0| T1| 0 | E | 0 | 0 | + +---+---+---+---+---+---+---+---+ - +---+---+---+---+---+---+---+---+ - | Track Number | - +---+---+---+---+---+---+---+---+ + E - When, delay operation 15 ms, 0 no delay. + T0/T1 - 00 - read address command. + 10 - read track command. + 11 - write track command. - Reads the current 8-bit value from the track position. + Tracks are numbered from 0 up to one minus the last track in the 1797! - Track Register Write (0x8019): + Track Register Read (0x8019): - +---+---+---+---+---+---+---+---+ - | Track Number | - +---+---+---+---+---+---+---+---+ + +---+---+---+---+---+---+---+---+ + | Track Number | + +---+---+---+---+---+---+---+---+ - Writes the 8-bit value to the track register. + Reads the current 8-bit value from the track position. - Sectors are numbers from 1 up to the last sector in the 1797! + Track Register Write (0x8019): - Sector Register Read (0x801A): + +---+---+---+---+---+---+---+---+ + | Track Number | + +---+---+---+---+---+---+---+---+ - +---+---+---+---+---+---+---+---+ - | Sector Number | - +---+---+---+---+---+---+---+---+ + Writes the 8-bit value to the track register. - Reads the current 8-bit value from the sector position. + Sectors are numbers from 1 up to the last sector in the 1797! - Sector Register Write (0x801A): + Sector Register Read (0x801A): - +---+---+---+---+---+---+---+---+ - | Sector Number | - +---+---+---+---+---+---+---+---+ + +---+---+---+---+---+---+---+---+ + | Sector Number | + +---+---+---+---+---+---+---+---+ - Writes the 8-bit value to the sector register. + Reads the current 8-bit value from the sector position. - Data Register Read (0x801B): + Sector Register Write (0x801A): - +---+---+---+---+---+---+---+---+ - | Data | - +---+---+---+---+---+---+---+---+ + +---+---+---+---+---+---+---+---+ + | Sector Number | + +---+---+---+---+---+---+---+---+ - Reads the current 8-bit value from the data register. + Writes the 8-bit value to the sector register. - Data Register Write (0x801B): + Data Register Read (0x801B): - +---+---+---+---+---+---+---+---+ - | Data | - +---+---+---+---+---+---+---+---+ + +---+---+---+---+---+---+---+---+ + | Data | + +---+---+---+---+---+---+---+---+ - Writes the 8-bit value to the data register. + Reads the current 8-bit value from the data register. - A FLEX disk is defined as follows: + Data Register Write (0x801B): - Track Sector Use - 0 1 Boot sector - 0 2 Boot sector (cont) - 0 3 Unused - 0 4 System Identity Record (explained below) - 0 5 Unused - 0 6-last Directory - 10 entries/sector (explained below) - 1 1 First available data sector - last-1 last Last available data sector + +---+---+---+---+---+---+---+---+ + | Data | + +---+---+---+---+---+---+---+---+ - System Identity Record + Writes the 8-bit value to the data register. - Byte Use - 0x00 Two bytes of zeroes (Clears forward link) - 0x10 Volume name in ASCII(11 bytes) - 0x1B Volume number in binary (2 bytes) - 0x1D Address of first free data sector (Track-Sector) (2 bytes) - 0x1F Address of last free data sector (Track-Sector) (2 bytes) - 0x21 Total number of data sectors in binary (2 bytes) - 0x23 Current date (Month-Day-Year) in binary - 0x26 Highest track number on disk in binary (byte) - 0x27 Highest sector number on a track in binary (byte) + A FLEX disk is defined as follows: - The following unit registers are used by this controller emulation: + Track Sector Use + 0 1 Boot sector + 0 2 Boot sector (cont) + 0 3 Unused + 0 4 System Identity Record (explained below) + 0 5 Unused + 0 6-last Directory - 10 entries/sector (explained below) + 1 1 First available data sector + last-1 last Last available data sector - dsk_unit[cur_drv].u3 unit current flags - dsk_unit[cur_drv].u4 unit current track - dsk_unit[cur_drv].u5 unit current sector - dsk_unit[cur_drv].pos unit current sector byte index into buffer - dsk_unit[cur_drv].filebuf unit current sector buffer - dsk_unit[cur_drv].fileref unit current attached file reference + System Identity Record + + Byte Use + 0x00 Two bytes of zeroes (Clears forward link) + 0x10 Volume name in ASCII(11 bytes) + 0x1B Volume number in binary (2 bytes) + 0x1D Address of first free data sector (Track-Sector) (2 bytes) + 0x1F Address of last free data sector (Track-Sector) (2 bytes) + 0x21 Total number of data sectors in binary (2 bytes) + 0x23 Current date (Month-Day-Year) in binary + 0x26 Highest track number on disk in binary (byte) + 0x27 Highest sector number on a track in binary (byte) + + The following unit registers are used by this controller emulation: + + dsk_unit[cur_drv].u3 unit current flags + dsk_unit[cur_drv].u4 unit current track + dsk_unit[cur_drv].u5 unit current sector + dsk_unit[cur_drv].pos unit current sector byte index into buffer + dsk_unit[cur_drv].filebuf unit current sector buffer + dsk_unit[cur_drv].fileref unit current attached file reference */ #include @@ -370,25 +376,22 @@ int32 fdcdrv(int32 io, int32 data) static long pos; if (io) { /* write to DC-4 drive register */ - if (dsk_dev.dctrl & DEBUG_write) - printf("\nfdcdrv: Drive selected %d cur_dsk=%d", data & 0x03, cur_dsk); + sim_debug (DEBUG_write, &dsk_dev, "\nfdcdrv: Drive selected %d cur_dsk=%d", + data & 0x03, cur_dsk); if (cur_dsk == (data & 0x03)) return 0; /* already selected */ cur_dsk = data & 0x03; /* only 2 drive select bits */ - if (dsk_dev.dctrl & DEBUG_write) - printf("\nfdcdrv: Drive set to %d", cur_dsk); + sim_debug (DEBUG_write, &dsk_dev, "\nfdcdrv: Drive set to %d", cur_dsk); if ((dsk_unit[cur_dsk].flags & UNIT_ENABLE) == 0) { dsk_unit[cur_dsk].u3 |= WRPROT; /* set 1797 WPROT */ - if (dsk_dev.dctrl & DEBUG_write) - printf("\nfdcdrv: Drive write protected"); + sim_debug (DEBUG_write, &dsk_dev, "\nfdcdrv: Drive write protected"); } else { dsk_unit[cur_dsk].u3 &= ~WRPROT; /* set 1797 not WPROT */ - if (dsk_dev.dctrl & DEBUG_write) - printf("\nfdcdrv: Drive NOT write protected"); + sim_debug (DEBUG_write, &dsk_dev, "\nfdcdrv: Drive NOT write protected"); } pos = 0x200; /* Read in SIR */ - if (dsk_dev.dctrl & DEBUG_read) - printf("\nfdcdrv: Read pos = %ld ($%04X)", pos, (unsigned int) pos); + sim_debug (DEBUG_read, &dsk_dev, "\nfdcdrv: Read pos = %ld ($%04X)", + pos, (unsigned int) pos); sim_fseek(dsk_unit[cur_dsk].fileref, pos, SEEK_SET); /* seek to offset */ sim_fread(dsk_unit[cur_dsk].filebuf, SECSIZ, 1, dsk_unit[cur_dsk].fileref); /* read in buffer */ dsk_unit[cur_dsk].u3 |= BUSY | DRQ; /* set DRQ & BUSY */ @@ -398,13 +401,11 @@ int32 fdcdrv(int32 io, int32 data) cpd = *((uint8 *)(dsk_unit[cur_dsk].filebuf) + MAXCYL) & 0xFF; trksiz = spt * SECSIZ; dsksiz = trksiz * cpd; - if (dsk_dev.dctrl & DEBUG_read) - printf("\nfdcdrv: spt=%d heds=%d cpd=%d trksiz=%d dsksiz=%d flags=%08X u3=%08X", + sim_debug (DEBUG_read, &dsk_dev, "\nfdcdrv: spt=%d heds=%d cpd=%d trksiz=%d dsksiz=%d flags=%08X u3=%08X", spt, heds, cpd, trksiz, dsksiz, dsk_unit[cur_dsk].flags, dsk_unit[cur_dsk].u3); return 0; } else { /* read from DC-4 drive register */ - if (dsk_dev.dctrl & DEBUG_read) - printf("\nfdcdrv: Drive read as %02X", intrq); + sim_debug (DEBUG_read, &dsk_dev, "\nfdcdrv: Drive read as %02X", intrq); return intrq; } } @@ -418,8 +419,7 @@ int32 fdccmd(int32 io, int32 data) if ((dsk_unit[cur_dsk].flags & UNIT_ATT) == 0) { /* not attached */ dsk_unit[cur_dsk].u3 |= NOTRDY; /* set not ready flag */ - if (dsk_dev.dctrl & DEBUG_flow) - printf("\nfdccmd: Drive %d is not attached", cur_dsk); + sim_debug (DEBUG_flow, &dsk_dev, "\nfdccmd: Drive %d is not attached", cur_dsk); return 0; } else { dsk_unit[cur_dsk].u3 &= ~NOTRDY; /* clear not ready flag */ @@ -428,29 +428,27 @@ int32 fdccmd(int32 io, int32 data) switch(data) { case 0x8C: /* read command */ case 0x9C: - if (dsk_dev.dctrl & DEBUG_read) - printf("\nfdccmd: Read of disk %d, track %d, sector %d", + sim_debug (DEBUG_read, &dsk_dev, "\nfdccmd: Read of disk %d, track %d, sector %d", cur_dsk, dsk_unit[cur_dsk].u4, dsk_unit[cur_dsk].u5); pos = trksiz * dsk_unit[cur_dsk].u4; /* calculate file offset */ pos += SECSIZ * (dsk_unit[cur_dsk].u5 - 1); - if (dsk_dev.dctrl & DEBUG_read) - printf("\nfdccmd: Read pos = %ld ($%08X)", pos, (unsigned int) pos); + sim_debug (DEBUG_read, &dsk_dev, "\nfdccmd: Read pos = %ld ($%08X)", + pos, (unsigned int) pos); sim_fseek(dsk_unit[cur_dsk].fileref, pos, SEEK_SET); /* seek to offset */ sim_fread(dsk_unit[cur_dsk].filebuf, SECSIZ, 1, dsk_unit[cur_dsk].fileref); /* read in buffer */ dsk_unit[cur_dsk].u3 |= BUSY | DRQ; /* set DRQ & BUSY */ dsk_unit[cur_dsk].pos = 0; /* clear counter */ break; case 0xAC: /* write command */ - if (dsk_dev.dctrl & DEBUG_write) - printf("\nfdccmd: Write of disk %d, track %d, sector %d", + sim_debug (DEBUG_write, &dsk_dev, "\nfdccmd: Write of disk %d, track %d, sector %d", cur_dsk, dsk_unit[cur_dsk].u4, dsk_unit[cur_dsk].u5); if (dsk_unit[cur_dsk].u3 & WRPROT) { printf("\nfdccmd: Drive %d is write-protected", cur_dsk); } else { pos = trksiz * dsk_unit[cur_dsk].u4; /* calculate file offset */ pos += SECSIZ * (dsk_unit[cur_dsk].u5 - 1); - if (dsk_dev.dctrl & DEBUG_write) - printf("\nfdccmd: Write pos = %ld ($%08X)", pos, (unsigned int) pos); + sim_debug (DEBUG_write, &dsk_dev, "\nfdccmd: Write pos = %ld ($%08X)", + pos, (unsigned int) pos); sim_fseek(dsk_unit[cur_dsk].fileref, pos, SEEK_SET); /* seek to offset */ wrt_flag = 1; /* set write flag */ dsk_unit[cur_dsk].u3 |= BUSY | DRQ;/* set DRQ & BUSY */ @@ -461,18 +459,17 @@ int32 fdccmd(int32 io, int32 data) case 0x1B: dsk_unit[cur_dsk].u4 = fdcbyte; /* set track */ dsk_unit[cur_dsk].u3 &= ~(BUSY | DRQ); /* clear flags */ - if (dsk_dev.dctrl & DEBUG_flow) - printf("\nfdccmd: Seek of disk %d, track %d", cur_dsk, fdcbyte); + sim_debug (DEBUG_flow, &dsk_dev, "\nfdccmd: Seek of disk %d, track %d", + cur_dsk, fdcbyte); break; case 0x0B: /* restore command */ dsk_unit[cur_dsk].u4 = 0; /* home the drive */ dsk_unit[cur_dsk].u3 &= ~(BUSY | DRQ); /* clear flags */ - if (dsk_dev.dctrl & DEBUG_flow) - printf("\nfdccmd: Drive %d homed", cur_dsk); + sim_debug (DEBUG_flow, &dsk_dev, "\nfdccmd: Drive %d homed", cur_dsk); break; case 0xF0: /* write track command */ - if (dsk_dev.dctrl & DEBUG_write) - printf("\nfdccmd: Write track command for drive %d", cur_dsk); + sim_debug (DEBUG_write, &dsk_dev, "\nfdccmd: Write track command for drive %d", + cur_dsk); break; default: printf("Unknown FDC command %02XH\n\r", data); @@ -481,15 +478,15 @@ int32 fdccmd(int32 io, int32 data) val = dsk_unit[cur_dsk].u3; /* set return value */ /* either print below will force the val to 0x43 forever. timing problem in the 6800 disk driver software? */ -// if (dsk_dev.dctrl & DEBUG_flow) -// printf("\nfdccmd: Exit Drive %d status=%02X", cur_dsk, val); -// printf("\n%02X", val); //even this short fails it! +// sim_debug (DEBUG_flow, &dsk_dev, "\nfdccmd: Exit Drive %d status=%02X", +// cur_dsk, val); +// sim_debug (DEBUG_flow, &dsk_dev, "\n%02X", val); //even this short fails it! if (val1 == 0 && ((val & (BUSY + DRQ)) == (BUSY + DRQ))) /* delay BUSY going high */ val &= ~BUSY; if (val != val1) /* now allow BUSY after one read */ val1 = val; - if (dsk_dev.dctrl & DEBUG_flow) - printf("\nfdccmd: Exit Drive %d status=%02X", cur_dsk, val); + sim_debug (DEBUG_flow, &dsk_dev, "\nfdccmd: Exit Drive %d status=%02X", + cur_dsk, val); } return val; } @@ -500,11 +497,11 @@ int32 fdctrk(int32 io, int32 data) { if (io) { dsk_unit[cur_dsk].u4 = data & 0xFF; - if (dsk_dev.dctrl & DEBUG_read) - printf("\nfdctrk: Drive %d track set to %d", cur_dsk, dsk_unit[cur_dsk].u4); + sim_debug (DEBUG_read, &dsk_dev, "\nfdctrk: Drive %d track set to %d", + cur_dsk, dsk_unit[cur_dsk].u4); } - if (dsk_dev.dctrl & DEBUG_write) - printf("\nfdctrk: Drive %d track read as %d", cur_dsk, dsk_unit[cur_dsk].u4); + sim_debug (DEBUG_write, &dsk_dev, "\nfdctrk: Drive %d track read as %d", + cur_dsk, dsk_unit[cur_dsk].u4); return dsk_unit[cur_dsk].u4; } @@ -516,11 +513,11 @@ int32 fdcsec(int32 io, int32 data) dsk_unit[cur_dsk].u5 = data & 0xFF; if (dsk_unit[cur_dsk].u5 == 0) /* fix for swtp boot! */ dsk_unit[cur_dsk].u5 = 1; - if (dsk_dev.dctrl & DEBUG_write) - printf("\nfdcsec: Drive %d sector set to %d", cur_dsk, dsk_unit[cur_dsk].u5); + sim_debug (DEBUG_write, &dsk_dev, "\nfdcsec: Drive %d sector set to %d", + cur_dsk, dsk_unit[cur_dsk].u5); } - if (dsk_dev.dctrl & DEBUG_read) - printf("\nfdcsec: Drive %d sector read as %d", cur_dsk, dsk_unit[cur_dsk].u5); + sim_debug (DEBUG_read, &dsk_dev, "\nfdcsec: Drive %d sector read as %d", + cur_dsk, dsk_unit[cur_dsk].u5); return dsk_unit[cur_dsk].u5; } @@ -533,8 +530,8 @@ int32 fdcdata(int32 io, int32 data) if (io) { /* write byte to fdc */ fdcbyte = data; /* save for seek */ if (dsk_unit[cur_dsk].pos < SECSIZ) { /* copy bytes to buffer */ - if (dsk_dev.dctrl & DEBUG_write) - printf("\nfdcdata: Writing byte %d of %02X", dsk_unit[cur_dsk].pos, data); + sim_debug (DEBUG_write, &dsk_dev, "\nfdcdata: Writing byte %d of %02X", + dsk_unit[cur_dsk].pos, data); *((uint8 *)(dsk_unit[cur_dsk].filebuf) + dsk_unit[cur_dsk].pos) = data; /* byte into buffer */ dsk_unit[cur_dsk].pos++; /* step counter */ if (dsk_unit[cur_dsk].pos == SECSIZ) { @@ -543,21 +540,19 @@ int32 fdcdata(int32 io, int32 data) sim_fwrite(dsk_unit[cur_dsk].filebuf, SECSIZ, 1, dsk_unit[cur_dsk].fileref); /* write it */ wrt_flag = 0; /* clear write flag */ } - if (dsk_dev.dctrl & DEBUG_write) - printf("\nfdcdata: Sector write complete"); + sim_debug (DEBUG_write, &dsk_dev, "\nfdcdata: Sector write complete"); } } return 0; } else { /* read byte from fdc */ if (dsk_unit[cur_dsk].pos < SECSIZ) { /* copy bytes from buffer */ - if (dsk_dev.dctrl & DEBUG_read) - printf("\nfdcdata: Reading byte %d u3=%02X", dsk_unit[cur_dsk].pos, dsk_unit[cur_dsk].u3); + sim_debug (DEBUG_read, &dsk_dev, "\nfdcdata: Reading byte %d u3=%02X", + dsk_unit[cur_dsk].pos, dsk_unit[cur_dsk].u3); val = *((uint8 *)(dsk_unit[cur_dsk].filebuf) + dsk_unit[cur_dsk].pos) & 0xFF; dsk_unit[cur_dsk].pos++; /* step counter */ if (dsk_unit[cur_dsk].pos == SECSIZ) { /* done? */ dsk_unit[cur_dsk].u3 &= ~(BUSY | DRQ); /* clear flags */ - if (dsk_dev.dctrl & DEBUG_write) - printf("\nfdcdata: Sector read complete"); + sim_debug (DEBUG_read, &dsk_dev, "\nfdcdata: Sector read complete"); } return val; } else diff --git a/swtp6800/common/i2716.c b/swtp6800/common/i2716.c index d041568d..8db16414 100644 --- a/swtp6800/common/i2716.c +++ b/swtp6800/common/i2716.c @@ -2,40 +2,46 @@ Copyright (c) 2011-2012, William A. Beech - Permission is hereby granted, free of charge, to any person obtaining a - copy of this software and associated documentation files (the "Software"), - to deal in the Software without restriction, including without limitation - the rights to use, copy, modify, merge, publish, distribute, sublicense, - and/or sell copies of the Software, and to permit persons to whom the - Software is furnished to do so, subject to the following conditions: + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: - The above copyright notice and this permission notice shall be included in - all copies or substantial portions of the Software. + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - WILLIAM A. BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + WILLIAM A. BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - Except as contained in this notice, the name of William A. Beech shall not be - used in advertising or otherwise to promote the sale, use or other dealings - in this Software without prior written authorization from William A. Beech. + Except as contained in this notice, the name of William A. Beech shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from William A. Beech. - These functions support a simulated 2704 to 2764 EPROMs device on an 8-bit - computer system. This device allows the attachment of the device to a binary file - containing the EPROM code. + MODIFICATIONS: - These functions support emulation of 0 to 4 2716 EPROM devices on a CPU board. - The byte get and put routines use an offset into the boot EPROM image to locate - the proper byte. This allows another device to set the base address for each - EPROM. + 24 Apr 15 -- Modified to use simh_debug - This device uses a dynamically allocated buffer to hold each EPROM image. - A call to BOOTROM_config will free the current buffer. A call to - i2716_reset will allocate a new buffer of 2048 bytes. A - call to BOOTROM_attach will load the buffer with the EPROM image. + NOTES: + + These functions support a simulated 2704 to 2764 EPROMs device on an 8-bit + computer system. This device allows the attachment of the device to a binary file + containing the EPROM code. + + These functions support emulation of 0 to 4 2716 EPROM devices on a CPU board. + The byte get and put routines use an offset into the boot EPROM image to locate + the proper byte. This allows another device to set the base address for each + EPROM. + + This device uses a dynamically allocated buffer to hold each EPROM image. + A call to BOOTROM_config will free the current buffer. A call to + i2716_reset will allocate a new buffer of 2048 bytes. A + call to BOOTROM_attach will load the buffer with the EPROM image. */ #include @@ -110,23 +116,19 @@ t_stat i2716_attach (UNIT *uptr, char *cptr) t_stat r; FILE *fp; - if (i2716_dev.dctrl & DEBUG_flow) - printf("i2716_attach: cptr=%s\n", cptr); + sim_debug (DEBUG_flow, &i2716_dev, "i2716_attach: cptr=%s\n", cptr); if ((r = attach_unit (uptr, cptr)) != SCPE_OK) { - if (i2716_dev.dctrl & DEBUG_flow) - printf("i2716_attach: Error\n"); + sim_debug (DEBUG_flow, &i2716_dev, "i2716_attach: Error\n"); return r; } - if (i2716_dev.dctrl & DEBUG_read) - printf("\tOpen file\n"); + sim_debug (DEBUG_read, &i2716_dev, "\tOpen file\n"); fp = fopen(uptr->filename, "rb"); /* open EPROM file */ if (fp == NULL) { printf("i2716%d: Unable to open ROM file %s\n", (int)(uptr - i2716_dev.units), uptr->filename); printf("\tNo ROM image loaded!!!\n"); return SCPE_OK; } - if (i2716_dev.dctrl & DEBUG_read) - printf("\tRead file\n"); + sim_debug (DEBUG_read, &i2716_dev, "\tRead file\n"); j = 0; /* load EPROM file */ c = fgetc(fp); while (c != EOF) { @@ -137,12 +139,10 @@ t_stat i2716_attach (UNIT *uptr, char *cptr) break; } } - if (i2716_dev.dctrl & DEBUG_read) - printf("\tClose file\n"); + sim_debug (DEBUG_read, &i2716_dev, "\tClose file\n"); fclose(fp); // printf("i2716%d: %d bytes of ROM image %s loaded\n",uptr - i2716_dev.units, j, uptr->filename); - if (i2716_dev.dctrl & DEBUG_flow) - printf("i2716_attach: Done\n"); + sim_debug (DEBUG_flow, &i2716_dev, "i2716_attach: Done\n"); return SCPE_OK; } @@ -153,20 +153,18 @@ t_stat i2716_reset (DEVICE *dptr) int32 i, base; UNIT *uptr; - if (i2716_dev.dctrl & DEBUG_flow) - printf("i2716_reset: \n"); + sim_debug (DEBUG_flow, &i2716_dev, "i2716_reset: \n"); for (i = 0; i < I2716_NUM; i++) { /* init all units */ uptr = i2716_dev.units + i; - if (i2716_dev.dctrl & DEBUG_flow) - printf("i2716 %d unit.flags=%08X\n", i, uptr->flags); + sim_debug (DEBUG_flow, &i2716_dev, "i2716 %d unit.flags=%08X\n", + i, uptr->flags); uptr->capac = 2048; uptr->u3 = 2048 * i; base = get_base(); if (uptr->filebuf == NULL) { /* no buffer allocated */ uptr->filebuf = malloc(2048); /* allocate EPROM buffer */ if (uptr->filebuf == NULL) { - if (i2716_dev.dctrl & DEBUG_flow) - printf("i2716_reset: Malloc error\n"); + sim_debug (DEBUG_flow, &i2716_dev, "i2716_reset: Malloc error\n"); return SCPE_MEM; } } @@ -180,8 +178,7 @@ t_stat i2716_reset (DEVICE *dptr) // printf("i2716%d: No file attached\n", i); // } } - if (i2716_dev.dctrl & DEBUG_flow) - printf("i2716_reset: Done\n"); + sim_debug (DEBUG_flow, &i2716_dev, "i2716_reset: Done\n"); return SCPE_OK; } @@ -202,19 +199,16 @@ int32 i2716_get_mbyte(int32 offset) len = uptr->capac - 1; if ((offset >= org) && (offset < (org + len))) { if (uptr->filebuf == NULL) { - if (i2716_dev.dctrl & DEBUG_read) - printf("i2716_get_mbyte: EPROM not configured\n"); + sim_debug (DEBUG_read, &i2716_dev, "i2716_get_mbyte: EPROM not configured\n"); return 0xFF; } else { val = *((uint8 *)(uptr->filebuf) + (offset - org)); - if (i2716_dev.dctrl & DEBUG_read) - printf(" val=%04X\n", val); + sim_debug (DEBUG_read, &i2716_dev, " val=%04X\n", val); return (val & 0xFF); } } } - if (i2716_dev.dctrl & DEBUG_read) - printf("i2716_get_mbyte: Out of range\n"); + sim_debug (DEBUG_read, &i2716_dev, "i2716_get_mbyte: Out of range\n"); return 0xFF; } diff --git a/swtp6800/common/m6800.c b/swtp6800/common/m6800.c index 6390e0dd..8018c62c 100644 --- a/swtp6800/common/m6800.c +++ b/swtp6800/common/m6800.c @@ -2,70 +2,75 @@ Copyright (c) 2005-2012, William Beech - Permission is hereby granted, free of charge, to any person obtaining a - copy of this software and associated documentation files (the "Software"), - to deal in the Software without restriction, including without limitation - the rights to use, copy, modify, merge, publish, distribute, sublicense, - and/or sell copies of the Software, and to permit persons to whom the - Software is furnished to do so, subject to the following conditions: + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: - The above copyright notice and this permission notice shall be included in - all copies or substantial portions of the Software. + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - WILLIAM A. BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + WILLIAM A. BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - Except as contained in this notice, the name of William A. Beech shall not - be used in advertising or otherwise to promote the sale, use or other dealings - in this Software without prior written authorization from William A. Beech. + Except as contained in this notice, the name of William A. Beech shall not + be used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from William A. Beech. - cpu Motorola M6800 CPU + MODIFICATIONS: - The register state for the M6800 CPU is: + 23 Apr 15 -- Modified to use simh_debug - A<0:7> Accumulator A - B<0:7> Accumulator B - IX<0:15> Index Register - CCR<0:7> Condition Code Register - HF half-carry flag - IF interrupt flag - NF negative flag - ZF zero flag - VF overflow flag - CF carry flag - PC<0:15> program counter - SP<0:15> Stack Pointer + NOTES: + cpu Motorola M6800 CPU - The M6800 is an 8-bit CPU, which uses 16-bit registers to address - up to 64KB of memory. + The register state for the M6800 CPU is: - The 72 basic instructions come in 1, 2, and 3-byte flavors. + A<0:7> Accumulator A + B<0:7> Accumulator B + IX<0:15> Index Register + CCR<0:7> Condition Code Register + HF half-carry flag + IF interrupt flag + NF negative flag + ZF zero flag + VF overflow flag + CF carry flag + PC<0:15> program counter + SP<0:15> Stack Pointer - This routine is the instruction decode routine for the M6800. - It is called from the CPU board simulator to execute - instructions in simulated memory, starting at the simulated PC. - It runs until 'reason' is set non-zero. + The M6800 is an 8-bit CPU, which uses 16-bit registers to address + up to 64KB of memory. - General notes: + The 72 basic instructions come in 1, 2, and 3-byte flavors. - 1. Reasons to stop. The simulator can be stopped by: + This routine is the instruction decode routine for the M6800. + It is called from the CPU board simulator to execute + instructions in simulated memory, starting at the simulated PC. + It runs until 'reason' is set non-zero. - WAI instruction - I/O error in I/O simulator - Invalid OP code (if ITRAP is set on CPU) - Invalid mamory address (if MTRAP is set on CPU) + General notes: - 2. Interrupts. - There are 4 types of interrupt, and in effect they do a - hardware CALL instruction to one of 4 possible high memory addresses. + 1. Reasons to stop. The simulator can be stopped by: - 3. Non-existent memory. - On the SWTP 6800, reads to non-existent memory - return 0FFH, and writes are ignored. + WAI instruction + I/O error in I/O simulator + Invalid OP code (if ITRAP is set on CPU) + Invalid mamory address (if MTRAP is set on CPU) + + 2. Interrupts. + There are 4 types of interrupt, and in effect they do a + hardware CALL instruction to one of 4 possible high memory addresses. + + 3. Non-existent memory. + On the SWTP 6800, reads to non-existent memory + return 0FFH, and writes are ignored. */ #include @@ -1734,15 +1739,13 @@ int32 fetch_byte(int32 flag) uint8 val; val = CPU_BD_get_mbyte(PC) & 0xFF; /* fetch byte */ - if (m6800_dev.dctrl & DEBUG_asm) { /* display source code */ - switch (flag) { - case 0: /* opcode fetch */ - printf("\n%04X %s", PC, opcode[val]); - break; - case 1: /* byte operand fetch */ - printf("0%02XH", val); - break; - } + switch (flag) { + case 0: /* opcode fetch */ + sim_debug (DEBUG_asm, &m6800_dev, "%04X %s\n", PC, opcode[val]); + break; + case 1: /* byte operand fetch */ + sim_debug (DEBUG_asm, &m6800_dev, "0%02XH\n", val); + break; } PC = (PC + 1) & ADDRMASK; /* increment PC */ return val; @@ -1755,8 +1758,7 @@ int32 fetch_word(void) val = CPU_BD_get_mbyte(PC) << 8; /* fetch high byte */ val |= CPU_BD_get_mbyte(PC + 1) & 0xFF; /* fetch low byte */ - if (m6800_dev.dctrl & DEBUG_asm) - printf("0%04XH", val); + sim_debug (DEBUG_asm, &m6800_dev, "0%04XH", val); PC = (PC + 2) & ADDRMASK; /* increment PC */ return val; } diff --git a/swtp6800/common/m6810.c b/swtp6800/common/m6810.c index a752fb2b..c73617e5 100644 --- a/swtp6800/common/m6810.c +++ b/swtp6800/common/m6810.c @@ -2,31 +2,37 @@ Copyright (c) 2011-2012, William A. Beech - Permission is hereby granted, free of charge, to any person obtaining a - copy of this software and associated documentation files (the "Software"), - to deal in the Software without restriction, including without limitation - the rights to use, copy, modify, merge, publish, distribute, sublicense, - and/or sell copies of the Software, and to permit persons to whom the - Software is furnished to do so, subject to the following conditions: + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: - The above copyright notice and this permission notice shall be included in - all copies or substantial portions of the Software. + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - WILLIAM A. BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + WILLIAM A. BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - Except as contained in this notice, the name of William A. Beech shall not be - used in advertising or otherwise to promote the sale, use or other dealings - in this Software without prior written authorization from William A. Beech. + Except as contained in this notice, the name of William A. Beech shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from William A. Beech. - These functions support a simulated m6810 RAM device on a CPU board. The - byte get and put routines use an offset into the RAM image to locate the - proper byte. This allows another device to set the base address for the - M6810. + MODIFICATIONS: + + 24 Apr 15 -- Modified to use simh_debug + + NOTES: + + These functions support a simulated m6810 RAM device on a CPU board. The + byte get and put routines use an offset into the RAM image to locate the + proper byte. This allows another device to set the base address for the + M6810. */ #include @@ -88,8 +94,7 @@ DEVICE m6810_dev = { t_stat m6810_reset (DEVICE *dptr) { - if (m6810_dev.dctrl & DEBUG_flow) - printf("m6810_reset: \n"); + sim_debug (DEBUG_flow, &m6810_dev, "m6810_reset: \n"); if (m6810_unit.filebuf == NULL) { m6810_unit.filebuf = malloc(128); if (m6810_unit.filebuf == NULL) { @@ -98,8 +103,7 @@ t_stat m6810_reset (DEVICE *dptr) } m6810_unit.capac = 128; } - if (m6810_dev.dctrl & DEBUG_flow) - printf("m6810_reset: Done\n"); + sim_debug (DEBUG_flow, &m6810_dev, "m6810_reset: Done\n"); return SCPE_OK; } @@ -113,16 +117,13 @@ int32 m6810_get_mbyte(int32 offset) { int32 val; - if (m6810_dev.dctrl & DEBUG_read) - printf("m6810_get_mbyte: offset=%04X\n", offset); + sim_debug (DEBUG_read, &m6810_dev, "m6810_get_mbyte: offset=%04X\n", offset); if (((t_addr)offset) < m6810_unit.capac) { val = *((uint8 *)(m6810_unit.filebuf) + offset) & 0xFF; - if (m6810_dev.dctrl & DEBUG_read) - printf("val=%04X\n", val); + sim_debug (DEBUG_read, &m6810_dev, "val=%04X\n", val); return val; } else { - if (m6810_dev.dctrl & DEBUG_read) - printf("m6810_get_mbyte: out of range\n"); + sim_debug (DEBUG_read, &m6810_dev, "m6810_get_mbyte: out of range\n"); return 0xFF; } } @@ -131,14 +132,13 @@ int32 m6810_get_mbyte(int32 offset) void m6810_put_mbyte(int32 offset, int32 val) { - if (m6810_dev.dctrl & DEBUG_write) - printf("m6810_put_mbyte: offset=%04X, val=%02X\n", offset, val); + sim_debug (DEBUG_write, &m6810_dev, "m6810_put_mbyte: offset=%04X, val=%02X\n", + offset, val); if ((t_addr)offset < m6810_unit.capac) { *((uint8 *)(m6810_unit.filebuf) + offset) = val & 0xFF; return; } else { - if (m6810_dev.dctrl & DEBUG_write) - printf("m6810_put_mbyte: out of range\n"); + sim_debug (DEBUG_write, &m6810_dev, "m6810_put_mbyte: out of range\n"); return; } } diff --git a/swtp6800/common/mp-8m.c b/swtp6800/common/mp-8m.c index 69f5bb9d..0cee9993 100644 --- a/swtp6800/common/mp-8m.c +++ b/swtp6800/common/mp-8m.c @@ -2,33 +2,39 @@ Copyright (c) 2011-2012, William A. Beech - Permission is hereby granted, free of charge, to any person obtaining a - copy of this software and associated documentation files (the "Software"), - to deal in the Software without restriction, including without limitation - the rights to use, copy, modify, merge, publish, distribute, sublicense, - and/or sell copies of the Software, and to permit persons to whom the - Software is furnished to do so, subject to the following conditions: + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: - The above copyright notice and this permission notice shall be included in - all copies or substantial portions of the Software. + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - WILLIAM A. BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + WILLIAM A. BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - Except as contained in this notice, the name of William A. Beech shall not be - used in advertising or otherwise to promote the sale, use or other dealings - in this Software without prior written authorization from William A. Beech. + Except as contained in this notice, the name of William A. Beech shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from William A. Beech. - These functions support 6 simulated MP-8M memory cards on an SS-50 system. + MODIFICATIONS: - Each unit uses a dynamically allocated 8192 byte buffer to hold the data. - Each unit contains the base address in mp_8m_unit.u3. The unit capacity is - held in mp_8m_unit.capac. Each unit can be enabled or disabled to reconfigure - the RAM for the system. + 24 Apr 15 -- Modified to use simh_debug + + NOTES: + + These functions support 6 simulated MP-8M memory cards on an SS-50 system. + + Each unit uses a dynamically allocated 8192 byte buffer to hold the data. + Each unit contains the base address in mp_8m_unit.u3. The unit capacity is + held in mp_8m_unit.capac. Each unit can be enabled or disabled to reconfigure + the RAM for the system. */ #include @@ -101,12 +107,11 @@ t_stat mp_8m_reset (DEVICE *dptr) int32 i, j, val; UNIT *uptr; - if (mp_8m_dev.dctrl & DEBUG_flow) - printf("mp_8m_reset: \n"); + sim_debug (DEBUG_flow, &mp_8m_dev, "mp_8m_reset: \n"); for (i = 0; i < MP_8M_NUM; i++) { /* init all units */ uptr = mp_8m_dev.units + i; - if (mp_8m_dev.dctrl & DEBUG_flow) - printf("MP-8M %d unit.flags=%08X\n", i, uptr->flags); + sim_debug (DEBUG_flow, &mp_8m_dev, "MP-8M %d unit.flags=%08X\n", + i, uptr->flags); uptr->capac = 0x2000; if (i < 4) uptr->u3 = 0x2000 * i; @@ -123,12 +128,10 @@ t_stat mp_8m_reset (DEVICE *dptr) *((uint8 *)(uptr->filebuf) + j) = val & 0xFF; } } - if (mp_8m_dev.dctrl & DEBUG_flow) - printf("MP-8M %d initialized at [%04X-%04XH]\n", i, uptr->u3, - uptr->u3 + uptr->capac - 1); + sim_debug (DEBUG_flow, &mp_8m_dev, "MP-8M %d initialized at [%04X-%04XH]\n", + i, uptr->u3, uptr->u3 + uptr->capac - 1); } - if (mp_8m_dev.dctrl & DEBUG_flow) - printf("mp_8m_reset: Done\n"); + sim_debug (DEBUG_flow, &mp_8m_dev, "mp_8m_reset: Done\n"); return SCPE_OK; } @@ -144,21 +147,18 @@ int32 mp_8m_get_mbyte(int32 addr) int32 i; UNIT *uptr; - if (mp_8m_dev.dctrl & DEBUG_read) - printf("mp_8m_get_mbyte: addr=%04X", addr); + sim_debug (DEBUG_read, &mp_8m_dev, "mp_8m_get_mbyte: addr=%04X", addr); for (i = 0; i < MP_8M_NUM; i++) { /* find addressed unit */ uptr = mp_8m_dev.units + i; org = uptr->u3; len = uptr->capac - 1; if ((addr >= org) && (addr <= org + len)) { val = *((uint8 *)(uptr->filebuf) + (addr - org)); - if (mp_8m_dev.dctrl & DEBUG_read) - printf(" val=%04X\n", val); + sim_debug (DEBUG_read, &mp_8m_dev, " val=%04X\n", val); return (val & 0xFF); } } - if (mp_8m_dev.dctrl & DEBUG_read) - printf("mp_8m_get_mbyte: Out of range\n"); + sim_debug (DEBUG_read, &mp_8m_dev, "mp_8m_get_mbyte: Out of range\n"); return 0xFF; /* multibus has active high pullups */ } @@ -181,21 +181,19 @@ void mp_8m_put_mbyte(int32 addr, int32 val) int32 i; UNIT *uptr; - if (mp_8m_dev.dctrl & DEBUG_write) - printf("mp_8m_put_mbyte: addr=%04X, val=%02X", addr, val); + sim_debug (DEBUG_write, &mp_8m_dev, "mp_8m_put_mbyte: addr=%04X, val=%02X", + addr, val); for (i = 0; i < MP_8M_NUM; i++) { /* find addressed unit */ uptr = mp_8m_dev.units + i; org = uptr->u3; len = uptr->capac - 1; if ((addr >= org) && (addr < org + len)) { *((uint8 *)(uptr->filebuf) + (addr - org)) = val & 0xFF; - if (mp_8m_dev.dctrl & DEBUG_write) - printf("\n"); + sim_debug (DEBUG_write, &mp_8m_dev, "\n"); return; } } - if (mp_8m_dev.dctrl & DEBUG_write) - printf("mp_8m_put_mbyte: Out of range\n"); + sim_debug (DEBUG_write, &mp_8m_dev, "mp_8m_put_mbyte: Out of range\n"); } /* put a word into memory */ diff --git a/swtp6800/common/mp-a.c b/swtp6800/common/mp-a.c index b6517bac..a8118c3c 100644 --- a/swtp6800/common/mp-a.c +++ b/swtp6800/common/mp-a.c @@ -2,35 +2,41 @@ Copyright (c) 2011-2012, William Beech - Permission is hereby granted, free of charge, to any person obtaining a - copy of this software and associated documentation files (the "Software"), - to deal in the Software without restriction, including without limitation - the rights to use, copy, modify, merge, publish, distribute, sublicense, - and/or sell copies of the Software, and to permit persons to whom the - Software is furnished to do so, subject to the following conditions: + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: - The above copyright notice and this permission notice shall be included in - all copies or substantial portions of the Software. + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - WILLIAM A. BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + WILLIAM A. BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - Except as contained in this notice, the name of William A. Beech shall not - be used in advertising or otherwise to promote the sale, use or other dealings - in this Software without prior written authorization from William A. Beech. + Except as contained in this notice, the name of William A. Beech shall not + be used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from William A. Beech. - The MP-A CPU Board contains the following devices [mp-a.c]: - M6800 processor [m6800.c]. - M6810 128 byte RAM at 0xA000 [m6810.c]. - M6830, SWTBUG, or custom boot ROM at 0xE000 [bootrom.c]. - Interface to the SS-50 bus and the MP-B2 Mother Board for I/O - and memory boards [mp-b2.c]. - Note: The file names of the emulator source programs for each device are - contained in "[]". + MODIFICATIONS: + + 24 Apr 15 -- Modified to use simh_debug + + NOTES: + + The MP-A CPU Board contains the following devices [mp-a.c]: + M6800 processor [m6800.c]. + M6810 128 byte RAM at 0xA000 [m6810.c]. + M6830, SWTBUG, or custom boot ROM at 0xE000 [bootrom.c]. + Interface to the SS-50 bus and the MP-B2 Mother Board for I/O + and memory boards [mp-b2.c]. + Note: The file names of the emulator source programs for each device are + contained in "[]". */ #include @@ -128,35 +134,29 @@ int32 CPU_BD_get_mbyte(int32 addr) { int32 val; - if (CPU_BD_dev.dctrl & DEBUG_read) - printf("CPU_BD_get_mbyte: addr=%04X\n", addr); + sim_debug (DEBUG_read, &CPU_BD_dev, "CPU_BD_get_mbyte: addr=%04X\n", addr); switch(addr & 0xF000) { case 0xA000: if (CPU_BD_unit.flags & UNIT_RAM) { val = m6810_get_mbyte(addr - 0xA000) & 0xFF; - if (CPU_BD_dev.dctrl & DEBUG_read) - printf("CPU_BD_get_mbyte: m6810 val=%02X\n", val); + sim_debug (DEBUG_read, &CPU_BD_dev, "CPU_BD_get_mbyte: m6810 val=%02X\n", val); return val; } else { val = MB_get_mbyte(addr) & 0xFF; - if (CPU_BD_dev.dctrl & DEBUG_read) - printf("CPU_BD_get_mbyte: m6810 val=%02X\n", val); + sim_debug (DEBUG_read, &CPU_BD_dev, "CPU_BD_get_mbyte: m6810 val=%02X\n", val); return val; } case 0xE000: val = BOOTROM_get_mbyte(addr - 0xE000) & 0xFF; - if (CPU_BD_dev.dctrl & DEBUG_read) - printf("CPU_BD_get_mbyte: EPROM=%02X\n", val); + sim_debug (DEBUG_read, &CPU_BD_dev, "CPU_BD_get_mbyte: EPROM=%02X\n", val); return val; case 0xF000: val = BOOTROM_get_mbyte(addr - (0x10000 - BOOTROM_unit.capac)) & 0xFF; - if (CPU_BD_dev.dctrl & DEBUG_read) - printf("CPU_BD_get_mbyte: EPROM=%02X\n", val); + sim_debug (DEBUG_read, &CPU_BD_dev, "CPU_BD_get_mbyte: EPROM=%02X\n", val); return val; default: val = MB_get_mbyte(addr) & 0xFF; - if (CPU_BD_dev.dctrl & DEBUG_read) - printf("CPU_BD_get_mbyte: mp_b2 val=%02X\n", val); + sim_debug (DEBUG_read, &CPU_BD_dev, "CPU_BD_get_mbyte: mp_b2 val=%02X\n", val); return val; } } @@ -167,13 +167,11 @@ int32 CPU_BD_get_mword(int32 addr) { int32 val; - if (CPU_BD_dev.dctrl & DEBUG_read) - printf("CPU_BD_get_mword: addr=%04X\n", addr); + sim_debug (DEBUG_read, &CPU_BD_dev, "CPU_BD_get_mword: addr=%04X\n", addr); val = (CPU_BD_get_mbyte(addr) << 8); val |= CPU_BD_get_mbyte(addr+1); val &= 0xFFFF; - if (CPU_BD_dev.dctrl & DEBUG_read) - printf("CPU_BD_get_mword: val=%04X\n", val); + sim_debug (DEBUG_read, &CPU_BD_dev, "CPU_BD_get_mword: val=%04X\n", val); return val; } @@ -181,8 +179,8 @@ int32 CPU_BD_get_mword(int32 addr) void CPU_BD_put_mbyte(int32 addr, int32 val) { - if (CPU_BD_dev.dctrl & DEBUG_write) - printf("CPU_BD_put_mbyte: addr=%04X, val=%02X\n", addr, val); + sim_debug (DEBUG_write, &CPU_BD_dev, "CPU_BD_put_mbyte: addr=%04X, val=%02X\n", + addr, val); switch(addr & 0xF000) { case 0xA000: if (CPU_BD_unit.flags & UNIT_RAM) { @@ -202,8 +200,8 @@ void CPU_BD_put_mbyte(int32 addr, int32 val) void CPU_BD_put_mword(int32 addr, int32 val) { - if (CPU_BD_dev.dctrl & DEBUG_write) - printf("CPU_BD_put_mword: addr=%04X, val=%04X\n", addr, val); + sim_debug (DEBUG_write, &CPU_BD_dev, "CPU_BD_put_mword: addr=%04X, val=%04X\n", + addr, val); CPU_BD_put_mbyte(addr, val >> 8); CPU_BD_put_mbyte(addr+1, val); } diff --git a/swtp6800/common/mp-a2.c b/swtp6800/common/mp-a2.c index e333a7f4..f592c1f3 100644 --- a/swtp6800/common/mp-a2.c +++ b/swtp6800/common/mp-a2.c @@ -2,37 +2,43 @@ Copyright (c) 2011-2012, William Beech - Permission is hereby granted, free of charge, to any person obtaining a - copy of this software and associated documentation files (the "Software"), - to deal in the Software without restriction, including without limitation - the rights to use, copy, modify, merge, publish, distribute, sublicense, - and/or sell copies of the Software, and to permit persons to whom the - Software is furnished to do so, subject to the following conditions: + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: - The above copyright notice and this permission notice shall be included in - all copies or substantial portions of the Software. + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - WILLIAM A. BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + WILLIAM A. BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - Except as contained in this notice, the name of William A. Beech shall not - be used in advertising or otherwise to promote the sale, use or other dealings - in this Software without prior written authorization from William A. Beech. + Except as contained in this notice, the name of William A. Beech shall not + be used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from William A. Beech. - The MP-A2 CPU Board contains the following devices [mp-a2.c]: - M6800 processor [m6800.c]. - M6810 128 byte RAM at 0xA000 [m6810.c]. - M6830, SWTBUG, or custom boot ROM at 0xE000 [bootrom.c]. - 4 ea 2716 EPROMs at either 0xC000, 0xC800, 0xD000 and 0xD800 (LO_PROM)or - 0xE000, 0xE800, 0xF000 and 0xF800 (HI_PROM) [eprom.c]. - Interface to the SS-50 bus and the MP-B2 Mother Board for I/O - and memory boards [mp-b2.c]. - Note: The file names of the emulator source programs for each device are - contained in "[]". + MODIFICATIONS: + + 24 Apr 15 -- Modified to use simh_debug + + NOTES: + + The MP-A2 CPU Board contains the following devices [mp-a2.c]: + M6800 processor [m6800.c]. + M6810 128 byte RAM at 0xA000 [m6810.c]. + M6830, SWTBUG, or custom boot ROM at 0xE000 [bootrom.c]. + 4 ea 2716 EPROMs at either 0xC000, 0xC800, 0xD000 and 0xD800 (LO_PROM)or + 0xE000, 0xE800, 0xF000 and 0xF800 (HI_PROM) [eprom.c]. + Interface to the SS-50 bus and the MP-B2 Mother Board for I/O + and memory boards [mp-b2.c]. + Note: The file names of the emulator source programs for each device are + contained in "[]". */ #include @@ -169,46 +175,39 @@ int32 CPU_BD_get_mbyte(int32 addr) { int32 val; - if (CPU_BD_dev.dctrl & DEBUG_read) - printf("CPU_BD_get_mbyte: addr=%04X\n", addr); + sim_debug (DEBUG_read, &CPU_BD_dev, "CPU_BD_get_mbyte: addr=%04X\n", addr); switch(addr & 0xF000) { case 0xA000: if (CPU_BD_unit.flags & UNIT_RAM) { val = m6810_get_mbyte(addr - 0xA000) & 0xFF; - if (CPU_BD_dev.dctrl & DEBUG_read) - printf("CPU_BD_get_mbyte: m6810 val=%02X\n", val); + sim_debug (DEBUG_read, &CPU_BD_dev, "CPU_BD_get_mbyte: m6810 val=%02X\n", val); return val; } else { val = MB_get_mbyte(addr) & 0xFF; - if (CPU_BD_dev.dctrl & DEBUG_read) - printf("CPU_BD_get_mbyte: m6810 val=%02X\n", val); + sim_debug (DEBUG_read, &CPU_BD_dev, "CPU_BD_get_mbyte: m6810 val=%02X\n", val); return val; } case 0xC000: if (CPU_BD_unit.flags & UNIT_LO_PROM) { val = i2716_get_mbyte(addr - 0xC000) & 0xFF; - if (CPU_BD_dev.dctrl & DEBUG_read) - printf("CPU_BD_get_mbyte: 2716=%02X\n", val); + sim_debug (DEBUG_read, &CPU_BD_dev, "CPU_BD_get_mbyte: 2716=%02X\n", val); return val; } else return 0xFF; break; case 0xE000: val = BOOTROM_get_mbyte(addr - 0xE000) & 0xFF; - if (CPU_BD_dev.dctrl & DEBUG_read) - printf("CPU_BD_get_mbyte: EPROM=%02X\n", val); + sim_debug (DEBUG_read, &CPU_BD_dev, "CPU_BD_get_mbyte: EPROM=%02X\n", val); return val; case 0xF000: if (CPU_BD_unit.flags & UNIT_MON) { val = BOOTROM_get_mbyte(addr - (0x10000 - BOOTROM_unit.capac)) & 0xFF; - if (CPU_BD_dev.dctrl & DEBUG_read) - printf("CPU_BD_get_mbyte: EPROM=%02X\n", val); + sim_debug (DEBUG_read, &CPU_BD_dev, "CPU_BD_get_mbyte: EPROM=%02X\n", val); return val; } default: val = MB_get_mbyte(addr) & 0xFF; - if (CPU_BD_dev.dctrl & DEBUG_read) - printf("CPU_BD_get_mbyte: mp_b2 val=%02X\n", val); + sim_debug (DEBUG_read, &CPU_BD_dev, "CPU_BD_get_mbyte: mp_b2 val=%02X\n", val); return val; } } @@ -219,13 +218,11 @@ int32 CPU_BD_get_mword(int32 addr) { int32 val; - if (CPU_BD_dev.dctrl & DEBUG_read) - printf("CPU_BD_get_mword: addr=%04X\n", addr); + sim_debug (DEBUG_read, &CPU_BD_dev, "CPU_BD_get_mword: addr=%04X\n", addr); val = (CPU_BD_get_mbyte(addr) << 8); val |= CPU_BD_get_mbyte(addr+1); val &= 0xFFFF; - if (CPU_BD_dev.dctrl & DEBUG_read) - printf("CPU_BD_get_mword: val=%04X\n", val); + sim_debug (DEBUG_read, &CPU_BD_dev, "CPU_BD_get_mword: val=%04X\n", val); return val; } @@ -233,8 +230,8 @@ int32 CPU_BD_get_mword(int32 addr) void CPU_BD_put_mbyte(int32 addr, int32 val) { - if (CPU_BD_dev.dctrl & DEBUG_write) - printf("CPU_BD_put_mbyte: addr=%04X, val=%02X\n", addr, val); + sim_debug (DEBUG_write, &CPU_BD_dev, "CPU_BD_put_mbyte: addr=%04X, val=%02X\n", + addr, val); switch(addr & 0xF000) { case 0xA000: if (CPU_BD_unit.flags & UNIT_RAM) { @@ -254,8 +251,8 @@ void CPU_BD_put_mbyte(int32 addr, int32 val) void CPU_BD_put_mword(int32 addr, int32 val) { - if (CPU_BD_dev.dctrl & DEBUG_write) - printf("CPU_BD_put_mword: addr=%04X, val=%04X\n", addr, val); + sim_debug (DEBUG_write, &CPU_BD_dev, "CPU_BD_put_mword: addr=%04X, val=%04X\n", + addr, val); CPU_BD_put_mbyte(addr, val >> 8); CPU_BD_put_mbyte(addr+1, val); } diff --git a/swtp6800/common/mp-b2.c b/swtp6800/common/mp-b2.c index 0f334c39..f4fc0790 100644 --- a/swtp6800/common/mp-b2.c +++ b/swtp6800/common/mp-b2.c @@ -2,26 +2,33 @@ Copyright (c) 2011-2012, William A. Beech - Permission is hereby granted, free of charge, to any person obtaining a - copy of this software and associated documentation files (the "Software"), - to deal in the Software without restriction, including without limitation - the rights to use, copy, modify, merge, publish, distribute, sublicense, - and/or sell copies of the Software, and to permit persons to whom the - Software is furnished to do so, subject to the following conditions: + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: - The above copyright notice and this permission notice shall be included in - all copies or substantial portions of the Software. + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - WILLIAM A. BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + WILLIAM A. BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name of William A. Beech shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from William A. Beech. + + MODIFICATIONS: + + 24 Apr 15 -- Modified to use simh_debug + + NOTES: - Except as contained in this notice, the name of William A. Beech shall not be - used in advertising or otherwise to promote the sale, use or other dealings - in this Software without prior written authorization from William A. Beech. */ #include @@ -174,13 +181,13 @@ int32 MB_get_mbyte(int32 addr) { int32 val; - if (MB_dev.dctrl & DEBUG_read) - printf("MB_get_mbyte: addr=%04X\n", addr); + sim_debug (DEBUG_read, &MB_dev, "MB_get_mbyte: addr=%04X\n", addr); switch(addr & 0xF000) { case 0x0000: case 0x1000: if (MB_unit.flags & UNIT_RAM_0000) { val = mp_8m_get_mbyte(addr) & 0xFF; + sim_debug (DEBUG_read, &MB_dev, "MB_get_mbyte: addr=%04X\n", addr); if (MB_dev.dctrl & DEBUG_read) printf("MB_get_mbyte: mp_8m val=%02X\n", val); return val; @@ -190,8 +197,7 @@ int32 MB_get_mbyte(int32 addr) case 0x3000: if (MB_unit.flags & UNIT_RAM_2000) { val = mp_8m_get_mbyte(addr) & 0xFF; - if (MB_dev.dctrl & DEBUG_read) - printf("MB_get_mbyte: mp_8m val=%02X\n", val); + sim_debug (DEBUG_read, &MB_dev, "MB_get_mbyte: mp_8m val=%02X\n", val); return val; } else return 0xFF; @@ -199,6 +205,7 @@ int32 MB_get_mbyte(int32 addr) case 0x5000: if (MB_unit.flags & UNIT_RAM_4000) { val = mp_8m_get_mbyte(addr) & 0xFF; + sim_debug (DEBUG_read, &MB_dev, "MB_get_mbyte: addr=%04X\n", addr); if (MB_dev.dctrl & DEBUG_read) printf("MB_get_mbyte: mp_8m val=%02X\n", val); return val; @@ -208,8 +215,7 @@ int32 MB_get_mbyte(int32 addr) case 0x7000: if (MB_unit.flags & UNIT_RAM_6000) { val = mp_8m_get_mbyte(addr) & 0xFF; - if (MB_dev.dctrl & DEBUG_read) - printf("MB_get_mbyte: mp_8m val=%02X\n", val); + sim_debug (DEBUG_read, &MB_dev, "MB_get_mbyte: mp_8m val=%02X\n", val); return val; } else return 0xFF; @@ -218,15 +224,14 @@ int32 MB_get_mbyte(int32 addr) val = (dev_table[addr - 0x8000].routine(0, 0)) & 0xFF; else val = 0xFF; - if (MB_dev.dctrl & DEBUG_read) - printf("MB_get_mbyte: I/O addr=%04X val=%02X\n", addr, val); + sim_debug (DEBUG_read, &MB_dev, "MB_get_mbyte: I/O addr=%04X val=%02X\n", + addr, val); return val; case 0xA000: case 0xB000: if (MB_unit.flags & UNIT_RAM_A000) { val = mp_8m_get_mbyte(addr) & 0xFF; - if (MB_dev.dctrl & DEBUG_read) - printf("MB_get_mbyte: mp_8m val=%02X\n", val); + sim_debug (DEBUG_read, &MB_dev, "MB_get_mbyte: mp_8m val=%02X\n", val); return val; } else return 0xFF; @@ -234,8 +239,7 @@ int32 MB_get_mbyte(int32 addr) case 0xD000: if (MB_unit.flags & UNIT_RAM_C000) { val = mp_8m_get_mbyte(addr) & 0xFF; - if (MB_dev.dctrl & DEBUG_read) - printf("MB_get_mbyte: mp_8m val=%02X\n", val); + sim_debug (DEBUG_read, &MB_dev, "MB_get_mbyte: mp_8m val=%02X\n", val); return val; } else return 0xFF; @@ -250,14 +254,11 @@ int32 MB_get_mword(int32 addr) { int32 val; - - if (MB_dev.dctrl & DEBUG_read) - printf("MB_get_mword: addr=%04X\n", addr); + sim_debug (DEBUG_read, &MB_dev, "MB_get_mword: addr=%04X\n", addr); val = (MB_get_mbyte(addr) << 8); val |= MB_get_mbyte(addr+1); val &= 0xFFFF; - if (MB_dev.dctrl & DEBUG_read) - printf("MB_get_mword: val=%04X\n", val); + sim_debug (DEBUG_read, &MB_dev, "MB_get_mword: val=%04X\n", val); return val; } @@ -265,8 +266,8 @@ int32 MB_get_mword(int32 addr) void MB_put_mbyte(int32 addr, int32 val) { - if (MB_dev.dctrl & DEBUG_write) - printf("MB_put_mbyte: addr=%04X, val=%02X\n", addr, val); + sim_debug (DEBUG_write, &MB_dev, "MB_put_mbyte: addr=%04X, val=%02X\n", + addr, val); switch(addr & 0xF000) { case 0x0000: case 0x1000: @@ -317,8 +318,7 @@ void MB_put_mbyte(int32 addr, int32 val) void MB_put_mword(int32 addr, int32 val) { - if (MB_dev.dctrl & DEBUG_write) - printf("MB_ptt_mword: addr=%04X, val=%04X\n", addr, val); + sim_debug (DEBUG_write, &MB_dev, "MB_ptt_mword: addr=%04X, val=%04X\n", addr, val); MB_put_mbyte(addr, val >> 8); MB_put_mbyte(addr+1, val); } diff --git a/swtp6800/common/mp-s.c b/swtp6800/common/mp-s.c index f4bae1f3..c7ebe913 100644 --- a/swtp6800/common/mp-s.c +++ b/swtp6800/common/mp-s.c @@ -2,53 +2,59 @@ Copyright (c) 2005-2012, William Beech - Permission is hereby granted, free of charge, to any person obtaining a - copy of this software and associated documentation files (the "Software"), - to deal in the Software without restriction, including without limitation - the rights to use, copy, modify, merge, publish, distribute, sublicense, - and/or sell copies of the Software, and to permit persons to whom the - Software is furnished to do so, subject to the following conditions: + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: - The above copyright notice and this permission notice shall be included in - all copies or substantial portions of the Software. + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - Willaim Beech BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + Willaim Beech BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - Except as contained in this notice, the name of William A. Beech shall not - be used in advertising or otherwise to promote the sale, use or other dealings - in this Software without prior written authorization from William A. Beech. - - These functions support a simulated SWTP MP-S interface card. - The card contains one M6850 ACIA. The ACIA implements one complete - serial port. It provides 7 or 8-bit ASCII RS-232 interface to Terminals - or 20 mA current loop interface to a model 33 or 37 Teletype. It is not - compatible with baudot Teletypes. Baud rates from 110 to 1200 are - switch selectable from S! on the MP-S. The ACIA ports appear at all - 4 addresses. This fact is used by SWTBUG to determine the presence of the - MP-S vice MP-C serial card. The ACIA interrupt request line can be connected - to the IRQ or NMI interrupt lines by a jumper on the MP-S. + Except as contained in this notice, the name of William A. Beech shall not + be used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from William A. Beech. - All I/O is via either programmed I/O or interrupt controlled I/O. - It has a status port and a data port. A write to the status port - can select some options for the device (0x03 will reset the port). - A read of the status port gets the port status: + MODIFICATIONS: - +---+---+---+---+---+---+---+---+ - | I | P | O | F |CTS|DCD|TXE|RXF| - +---+---+---+---+---+---+---+---+ + 24 Apr 15 -- Modified to use simh_debug - RXF - A 1 in this bit position means a character has been received - on the data port and is ready to be read. - TXE - A 1 in this bit means the port is ready to receive a character - on the data port and transmit it out over the serial line. - - A read to the data port gets the buffered character, a write - to the data port writes the character to the device. + NOTES: + + These functions support a simulated SWTP MP-S interface card. + The card contains one M6850 ACIA. The ACIA implements one complete + serial port. It provides 7 or 8-bit ASCII RS-232 interface to Terminals + or 20 mA current loop interface to a model 33 or 37 Teletype. It is not + compatible with baudot Teletypes. Baud rates from 110 to 1200 are + switch selectable from S! on the MP-S. The ACIA ports appear at all + 4 addresses. This fact is used by SWTBUG to determine the presence of the + MP-S vice MP-C serial card. The ACIA interrupt request line can be connected + to the IRQ or NMI interrupt lines by a jumper on the MP-S. + + All I/O is via either programmed I/O or interrupt controlled I/O. + It has a status port and a data port. A write to the status port + can select some options for the device (0x03 will reset the port). + A read of the status port gets the port status: + + +---+---+---+---+---+---+---+---+ + | I | P | O | F |CTS|DCD|TXE|RXF| + +---+---+---+---+---+---+---+---+ + + RXF - A 1 in this bit position means a character has been received + on the data port and is ready to be read. + TXE - A 1 in this bit means the port is ready to receive a character + on the data port and transmit it out over the serial line. + + A read to the data port gets the buffered character, a write + to the data port writes the character to the device. */ #include