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alpha, HP2100, ID16, ID32, PDP11 and VAX: Normalize array REG definitions

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Array REGister definitions have been made consistent by passing the
address of the whole array object.  This allows proper sizing assessment
to occur in the register validation logic.
This commit is contained in:
Mark Pizzolato 2020-03-01 12:11:13 -08:00
parent 7b75c89aaf
commit 90eddfc733
7 changed files with 13 additions and 13 deletions
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2
HP2100/hp2100_di_da.c
View file

@ -562,7 +562,7 @@ static REG da_reg [] = {
{ BRDATA (ISTATE, if_state, 10, sizeof (IF_STATE) * CHAR_BIT, DA_UNITS), PV_LEFT },
{ BRDATA (ICMD, if_command, 10, sizeof (IF_COMMAND) * CHAR_BIT, DA_UNITS), PV_LEFT },
{ BRDATA (CNVARS, icd_cntlr, 10, CHAR_BIT, sizeof (CNTLR_VARS) * DA_UNITS), REG_HRO },
{ BRDATA (CNVARS, &icd_cntlr, 10, CHAR_BIT, sizeof (CNTLR_VARS) * DA_UNITS), REG_HRO },
{ NULL }
};

4
HP2100/hp2100_mpx.c
View file

@ -1032,8 +1032,8 @@ static REG mpx_reg [] = {
{ BRDATA (ACKWAIT, mpx_ack_wait, 10, 10, MPX_PORTS) },
{ BRDATA (PFLAGS, mpx_flags, 2, 12, MPX_PORTS) },
{ BRDATA (RBUF, mpx_rbuf, 8, 8, MPX_PORTS * RD_BUF_SIZE), REG_A },
{ BRDATA (WBUF, mpx_wbuf, 8, 8, MPX_PORTS * WR_BUF_SIZE), REG_A },
{ BRDATA (RBUF, &mpx_rbuf, 8, 8, MPX_PORTS * RD_BUF_SIZE), REG_A },
{ BRDATA (WBUF, &mpx_wbuf, 8, 8, MPX_PORTS * WR_BUF_SIZE), REG_A },
{ BRDATA (GET, mpx_get, 10, 10, MPX_PORTS * 2) },
{ BRDATA (SEP, mpx_sep, 10, 10, MPX_PORTS * 2) },

2
Interdata/id_fd.c
View file

@ -168,7 +168,7 @@ REG fd_reg[] = {
{ HRDATA (STA, fd_sta, 8) },
{ HRDATA (BUF, fd_db, 8) },
{ HRDATA (LRN, fd_lrn, 16) },
{ BRDATA (ESTA, fd_es, 16, 8, ES_SIZE * FD_NUMDR) },
{ BRDATA (ESTA, &fd_es, 16, 8, ES_SIZE * FD_NUMDR) },
{ BRDATA (DBUF, fdxb, 16, 8, FD_NUMBY) },
{ HRDATA (DBPTR, fd_bptr, 8) },
{ FLDATA (WDV, fd_wdv, 0) },

4
PDP11/pdp11_dmc.c
View file

@ -1197,8 +1197,8 @@ REG dmc_reg[] = {
{ BRDATAD (SPEED, dmc_speed, DEV_RDX, 32, DMC_NUMDEVICE, "line speed") },
{ BRDATAD (CORRUPT, dmc_corruption, DEV_RDX, 32, DMC_NUMDEVICE, "data corruption factor (0.1%)") },
{ BRDATAD (DIAG, dmc_microdiag, DEV_RDX, 1, DMC_NUMDEVICE, "Microdiagnostic Enabled") },
{ BRDATAD (PEER, dmc_peer, DEV_RDX, 8, DMC_NUMDEVICE*PEERSIZE, "peer address:port") },
{ BRDATAD (PORT, dmc_port, DEV_RDX, 8, DMC_NUMDEVICE*PEERSIZE, "listen port") },
{ BRDATAD (PEER, &dmc_peer, DEV_RDX, 8, DMC_NUMDEVICE*PEERSIZE, "peer address:port") },
{ BRDATAD (PORT, &dmc_port, DEV_RDX, 8, DMC_NUMDEVICE*PEERSIZE, "listen port") },
{ BRDATAD (BASEADDR, dmc_baseaddr, DEV_RDX, 32, DMC_NUMDEVICE, "program set base address") },
{ BRDATAD (BASESIZE, dmc_basesize, DEV_RDX, 16, DMC_NUMDEVICE, "program set base size") },
{ BRDATAD (MODEM, dmc_modem, DEV_RDX, 8, DMC_NUMDEVICE, "modem control bits") },

8
PDP11/pdp11_rq.c
View file

@ -988,7 +988,7 @@ REG rq_reg[] = {
{ DRDATAD (I4TIME, rq_itime4, 24, "init stage 4 delay"), PV_LEFT + REG_NZ },
{ DRDATAD (QTIME, rq_qtime, 24, "response time for 'immediate' packets"), PV_LEFT + REG_NZ },
{ DRDATAD (XTIME, rq_xtime, 24, "response time for data transfers"), PV_LEFT + REG_NZ },
{ BRDATAD (PKTS, rq_ctx.pak, DEV_RDX, 16, sizeof(rq_ctx.pak)/2, "packet buffers, 33W each, 32 entries") },
{ BRDATAD (PKTS, &rq_ctx.pak, DEV_RDX, 16, sizeof(rq_ctx.pak)/2, "packet buffers, 33W each, 32 entries") },
{ URDATAD (CPKT, rq_unit[0].cpkt, 10, 5, 0, RQ_NUMDR, 0, "current packet, units 0 to 3") },
{ URDATAD (UCNUM, rq_unit[0].cnum, 10, 5, 0, RQ_NUMDR, 0, "ctrl number, units 0 to 3") },
{ URDATAD (PKTQ, rq_unit[0].pktq, 10, 5, 0, RQ_NUMDR, 0, "packet queue, units 0 to 3") },
@ -1167,7 +1167,7 @@ REG rqb_reg[] = {
{ FLDATA (PRGI, rqb_ctx.prgi, 0), REG_HIDDEN },
{ FLDATA (PIP, rqb_ctx.pip, 0), REG_HIDDEN },
{ BINRDATA(CTYPE, rqb_ctx.ctype, 32), REG_HIDDEN },
{ BRDATAD (PKTS, rqb_ctx.pak, DEV_RDX, 16, sizeof(rq_ctx.pak)/2, "packet buffers, 33W each, 32 entries") },
{ BRDATAD (PKTS, &rqb_ctx.pak, DEV_RDX, 16, sizeof(rq_ctx.pak)/2, "packet buffers, 33W each, 32 entries") },
{ URDATAD (CPKT, rqb_unit[0].cpkt, 10, 5, 0, RQ_NUMDR, 0, "current packet, units 0 to 3") },
{ URDATAD (UCNUM, rqb_unit[0].cnum, 10, 5, 0, RQ_NUMDR, 0, "ctrl number, units 0 to 3") },
{ URDATAD (PKTQ, rqb_unit[0].pktq, 10, 5, 0, RQ_NUMDR, 0, "packet queue, units 0 to 3") },
@ -1240,7 +1240,7 @@ REG rqc_reg[] = {
{ FLDATA (PRGI, rqc_ctx.prgi, 0), REG_HIDDEN },
{ FLDATA (PIP, rqc_ctx.pip, 0), REG_HIDDEN },
{ BINRDATA(CTYPE, rqc_ctx.ctype, 32), REG_HIDDEN },
{ BRDATAD (PKTS, rqc_ctx.pak, DEV_RDX, 16, sizeof(rq_ctx.pak)/2, "packet buffers, 33W each, 32 entries") },
{ BRDATAD (PKTS, &rqc_ctx.pak, DEV_RDX, 16, sizeof(rq_ctx.pak)/2, "packet buffers, 33W each, 32 entries") },
{ URDATAD (CPKT, rqc_unit[0].cpkt, 10, 5, 0, RQ_NUMDR, 0, "current packet, units 0 to 3") },
{ URDATAD (UCNUM, rqc_unit[0].cnum, 10, 5, 0, RQ_NUMDR, 0, "ctrl number, units 0 to 3") },
{ URDATAD (PKTQ, rqc_unit[0].pktq, 10, 5, 0, RQ_NUMDR, 0, "packet queue, units 0 to 3") },
@ -1313,7 +1313,7 @@ REG rqd_reg[] = {
{ FLDATA (PRGI, rqd_ctx.prgi, 0), REG_HIDDEN },
{ FLDATA (PIP, rqd_ctx.pip, 0), REG_HIDDEN },
{ BINRDATA(CTYPE, rqd_ctx.ctype, 32), REG_HIDDEN },
{ BRDATAD (PKTS, rqd_ctx.pak, DEV_RDX, 16, sizeof(rq_ctx.pak)/2, "packet buffers, 33W each, 32 entries") },
{ BRDATAD (PKTS, &rqd_ctx.pak, DEV_RDX, 16, sizeof(rq_ctx.pak)/2, "packet buffers, 33W each, 32 entries") },
{ URDATAD (CPKT, rqd_unit[0].cpkt, 10, 5, 0, RQ_NUMDR, 0, "current packet, units 0 to 3") },
{ URDATAD (UCNUM, rqd_unit[0].cnum, 10, 5, 0, RQ_NUMDR, 0, "ctrl number, units 0 to 3") },
{ URDATAD (PKTQ, rqd_unit[0].pktq, 10, 5, 0, RQ_NUMDR, 0, "packet queue, units 0 to 3") },

2
PDP11/pdp11_tq.c
View file

@ -464,7 +464,7 @@ REG tq_reg[] = {
{ DRDATAD (QTIME, tq_qtime, 24, "response time for 'immediate' packets"), PV_LEFT + REG_NZ },
{ DRDATAD (XTIME, tq_xtime, 24, "response time for data transfers"), PV_LEFT + REG_NZ },
{ DRDATAD (RWTIME, tq_rwtime, 32, "rewind time 2 sec (adjusted later)"), PV_LEFT + REG_NZ },
{ BRDATAD (PKTS, tq_pkt, DEV_RDX, 16, TQ_NPKTS * (TQ_PKT_SIZE_W + 1), "packet buffers, 33W each, 32 entries") },
{ BRDATAD (PKTS, &tq_pkt, DEV_RDX, 16, TQ_NPKTS * (TQ_PKT_SIZE_W + 1), "packet buffers, 33W each, 32 entries") },
{ URDATAD (PLUG, tq_unit[0].unit_plug, 10, 32, 0, TQ_NUMDR, PV_LEFT | REG_RO, "unit plug value, units 0 to 3") },
{ DRDATA (DEVTYPE, tq_typ, 2), REG_HRO },
{ DRDATA (DEVCAP, drv_tab[TQU_TYPE].cap, T_ADDR_W), PV_LEFT | REG_HRO },

4
alpha/alpha_ev5_tlb.c
View file

@ -99,13 +99,13 @@ REG tlb_reg[] = {
{ HRDATA (IASN, itlb_asn, ITB_ASN_WIDTH) },
{ HRDATA (INLU, itlb_nlu, ITLB_WIDTH) },
{ BRDATA (IMINI, &i_mini_tlb, 16, 32, TLB_ESIZE) },
{ BRDATA (ITLB, itlb, 16, 32, ITLB_SIZE*TLB_ESIZE) },
{ BRDATA (ITLB, &itlb, 16, 32, ITLB_SIZE*TLB_ESIZE) },
{ HRDATA (DCM, dtlb_cm, 2) },
{ HRDATA (DSPAGE, dtlb_spage, 2), REG_HRO },
{ HRDATA (DASN, dtlb_asn, DTB_ASN_WIDTH) },
{ HRDATA (DNLU, dtlb_nlu, DTLB_WIDTH) },
{ BRDATA (DMINI, &d_mini_tlb, 16, 32, TLB_ESIZE) },
{ BRDATA (DTLB, dtlb, 16, 32, DTLB_SIZE*TLB_ESIZE) },
{ BRDATA (DTLB, &dtlb, 16, 32, DTLB_SIZE*TLB_ESIZE) },
{ NULL }
};