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Fixed interrupts to treat all Qbus devices as BR4. Changed RQ and TQ to BR4 to reflect real hardware (for the Unibus case).

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Mark Pizzolato 2011-12-17 10:04:53 -08:00
parent de9facf9cc
commit 93f09d3253
6 changed files with 129 additions and 96 deletions
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98
PDP11/pdp11_defs.h
View file

@ -1,6 +1,6 @@
/* pdp11_defs.h: PDP-11 simulator definitions /* pdp11_defs.h: PDP-11 simulator definitions
Copyright (c) 1993-2010, Robert M Supnik Copyright (c) 1993-2011, Robert M Supnik
Permission is hereby granted, free of charge, to any person obtaining a Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"), copy of this software and associated documentation files (the "Software"),
@ -26,6 +26,7 @@
The author gratefully acknowledges the help of Max Burnet, Megan Gentry, The author gratefully acknowledges the help of Max Burnet, Megan Gentry,
and John Wilson in resolving questions about the PDP-11 and John Wilson in resolving questions about the PDP-11
11-Dec-11 RMS Fixed priority of PIRQ vs IO; added INT_INTERNALn
22-May-10 RMS Added check for 64b definitions 22-May-10 RMS Added check for 64b definitions
19-Nov-08 RMS Moved I/O support routines to I/O library 19-Nov-08 RMS Moved I/O support routines to I/O library
16-May-08 RMS Added KE11A, DC11 support 16-May-08 RMS Added KE11A, DC11 support
@ -628,61 +629,65 @@ typedef struct pdp_dib DIB;
#define IOBA_PSW (IOPAGEBASE + 017776) /* PSW */ #define IOBA_PSW (IOPAGEBASE + 017776) /* PSW */
#define IOLN_PSW 002 #define IOLN_PSW 002
/* Interrupt assignments; within each level, priority is right to left */ /* Interrupt assignments; within each level, priority is right to left
PIRQn has the highest priority with a level and is always bit <0>
On level 6, the clock is second highest priority */
#define IPL_HLVL 8 /* # int levels */ #define IPL_HLVL 8 /* # int levels */
#define IPL_HMIN 4 /* lowest IO int level */
#define INT_V_PIR7 0 /* BR7 */ #define INT_V_PIR7 0 /* BR7 */
#define INT_V_CLK 0 /* BR6 */ #define INT_V_PIR6 0 /* BR6 */
#define INT_V_PCLK 1 #define INT_V_CLK 1
#define INT_V_DTA 2 #define INT_V_PCLK 2
#define INT_V_TA 3 #define INT_V_DTA 3
#define INT_V_PIR6 4 #define INT_V_TA 4
#define INT_V_RK 0 /* BR5 */ #define INT_V_PIR5 0 /* BR5 */
#define INT_V_RL 1 #define INT_V_RK 1
#define INT_V_RX 2 #define INT_V_RL 2
#define INT_V_TM 3 #define INT_V_RX 3
#define INT_V_RP 4 #define INT_V_TM 4
#define INT_V_TS 5 #define INT_V_RP 5
#define INT_V_HK 6 #define INT_V_TS 6
#define INT_V_RQ 7 #define INT_V_HK 7
#define INT_V_DZRX 8 #define INT_V_RQ 8
#define INT_V_DZTX 9 #define INT_V_DZRX 9
#define INT_V_TQ 10 #define INT_V_DZTX 10
#define INT_V_RY 11 #define INT_V_TQ 11
#define INT_V_XQ 12 #define INT_V_RY 12
#define INT_V_XU 13 #define INT_V_XQ 13
#define INT_V_TU 14 #define INT_V_XU 14
#define INT_V_RF 15 #define INT_V_TU 15
#define INT_V_RC 16 #define INT_V_RF 16
#define INT_V_PIR5 17 #define INT_V_RC 17
#define INT_V_TTI 0 /* BR4 */ #define INT_V_PIR4 0 /* BR4 */
#define INT_V_TTO 1 #define INT_V_TTI 1
#define INT_V_PTR 2 #define INT_V_TTO 2
#define INT_V_PTP 3 #define INT_V_PTR 3
#define INT_V_LPT 4 #define INT_V_PTP 4
#define INT_V_VHRX 5 #define INT_V_LPT 5
#define INT_V_VHTX 6 #define INT_V_VHRX 6
#define INT_V_CR 7 #define INT_V_VHTX 7
#define INT_V_DLI 8 #define INT_V_CR 8
#define INT_V_DLO 9 #define INT_V_DLI 9
#define INT_V_DCI 10 #define INT_V_DLO 10
#define INT_V_DCO 11 #define INT_V_DCI 11
#define INT_V_PIR4 12 #define INT_V_DCO 12
#define INT_V_PIR3 0 /* BR3 */ #define INT_V_PIR3 0 /* BR3 */
#define INT_V_PIR2 0 /* BR2 */ #define INT_V_PIR2 0 /* BR2 */
#define INT_V_PIR1 0 /* BR1 */ #define INT_V_PIR1 0 /* BR1 */
#define INT_PIR7 (1u << INT_V_PIR7) #define INT_PIR7 (1u << INT_V_PIR7)
#define INT_PIR6 (1u << INT_V_PIR6)
#define INT_CLK (1u << INT_V_CLK) #define INT_CLK (1u << INT_V_CLK)
#define INT_PCLK (1u << INT_V_PCLK) #define INT_PCLK (1u << INT_V_PCLK)
#define INT_DTA (1u << INT_V_DTA) #define INT_DTA (1u << INT_V_DTA)
#define INT_TA (1u << INT_V_TA) #define INT_TA (1u << INT_V_TA)
#define INT_PIR6 (1u << INT_V_PIR6) #define INT_PIR5 (1u << INT_V_PIR5)
#define INT_RK (1u << INT_V_RK) #define INT_RK (1u << INT_V_RK)
#define INT_RL (1u << INT_V_RL) #define INT_RL (1u << INT_V_RL)
#define INT_RX (1u << INT_V_RX) #define INT_RX (1u << INT_V_RX)
@ -700,11 +705,11 @@ typedef struct pdp_dib DIB;
#define INT_TU (1u << INT_V_TU) #define INT_TU (1u << INT_V_TU)
#define INT_RF (1u << INT_V_RF) #define INT_RF (1u << INT_V_RF)
#define INT_RC (1u << INT_V_RC) #define INT_RC (1u << INT_V_RC)
#define INT_PIR5 (1u << INT_V_PIR5) #define INT_PIR4 (1u << INT_V_PIR4)
#define INT_PTR (1u << INT_V_PTR)
#define INT_PTP (1u << INT_V_PTP)
#define INT_TTI (1u << INT_V_TTI) #define INT_TTI (1u << INT_V_TTI)
#define INT_TTO (1u << INT_V_TTO) #define INT_TTO (1u << INT_V_TTO)
#define INT_PTR (1u << INT_V_PTR)
#define INT_PTP (1u << INT_V_PTP)
#define INT_LPT (1u << INT_V_LPT) #define INT_LPT (1u << INT_V_LPT)
#define INT_VHRX (1u << INT_V_VHRX) #define INT_VHRX (1u << INT_V_VHRX)
#define INT_VHTX (1u << INT_V_VHTX) #define INT_VHTX (1u << INT_V_VHTX)
@ -713,11 +718,18 @@ typedef struct pdp_dib DIB;
#define INT_DLO (1u << INT_V_DLO) #define INT_DLO (1u << INT_V_DLO)
#define INT_DCI (1u << INT_V_DCI) #define INT_DCI (1u << INT_V_DCI)
#define INT_DCO (1u << INT_V_DCO) #define INT_DCO (1u << INT_V_DCO)
#define INT_PIR4 (1u << INT_V_PIR4)
#define INT_PIR3 (1u << INT_V_PIR3) #define INT_PIR3 (1u << INT_V_PIR3)
#define INT_PIR2 (1u << INT_V_PIR2) #define INT_PIR2 (1u << INT_V_PIR2)
#define INT_PIR1 (1u << INT_V_PIR1) #define INT_PIR1 (1u << INT_V_PIR1)
#define INT_INTERNAL7 (INT_PIR7)
#define INT_INTERNAL6 (INT_PIR6 | INT_CLK)
#define INT_INTERNAL5 (INT_PIR5)
#define INT_INTERNAL4 (INT_PIR4)
#define INT_INTERNAL3 (INT_PIR3)
#define INT_INTERNAL2 (INT_PIR2)
#define INT_INTERNAL1 (INT_PIR1)
#define IPL_CLK 6 /* int pri levels */ #define IPL_CLK 6 /* int pri levels */
#define IPL_PCLK 6 #define IPL_PCLK 6
#define IPL_DTA 6 #define IPL_DTA 6

23
PDP11/pdp11_io.c
View file

@ -1,6 +1,6 @@
/* pdp11_io.c: PDP-11 I/O simulator /* pdp11_io.c: PDP-11 I/O simulator
Copyright (c) 1993-2008, Robert M Supnik Copyright (c) 1993-2011, Robert M Supnik
Permission is hereby granted, free of charge, to any person obtaining a Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"), copy of this software and associated documentation files (the "Software"),
@ -23,6 +23,7 @@
used in advertising or otherwise to promote the sale, use or other dealings used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Robert M Supnik. in this Software without prior written authorization from Robert M Supnik.
12-Dec-11 RMS Fixed interrupts to treat all Qbus devices as BR4
19-Nov-08 RMS Moved I/O support routines to I/O library 19-Nov-08 RMS Moved I/O support routines to I/O library
16-May-08 RMS Added multiple DC11 support 16-May-08 RMS Added multiple DC11 support
Renamed DL11 in autoconfigure Renamed DL11 in autoconfigure
@ -79,6 +80,11 @@ static const int32 pirq_bit[7] = {
INT_V_PIR5, INT_V_PIR6, INT_V_PIR7 INT_V_PIR5, INT_V_PIR6, INT_V_PIR7
}; };
static const int32 int_internal[IPL_HLVL] = {
INT_INTERNAL7, INT_INTERNAL6, INT_INTERNAL5, INT_INTERNAL4,
INT_INTERNAL3, INT_INTERNAL2, INT_INTERNAL1, 0
};
/* I/O page lookup and linkage routines /* I/O page lookup and linkage routines
Inputs: Inputs:
@ -118,27 +124,32 @@ if (iodispW[idx]) {
return SCPE_NXM; return SCPE_NXM;
} }
/* Calculate interrupt outstanding */ /* Calculate interrupt outstanding
In a Qbus system, all device interrupts are treated as BR4 */
int32 calc_ints (int32 nipl, int32 trq) int32 calc_ints (int32 nipl, int32 trq)
{ {
int32 i; int32 i, t;
t_bool all_int = (UNIBUS || (nipl < IPL_HMIN));
for (i = IPL_HLVL - 1; i > nipl; i--) { for (i = IPL_HLVL - 1; i > nipl; i--) {
if (int_req[i]) t = all_int? int_req[i]: (int_req[i] & int_internal[i]);
if (t)
return (trq | TRAP_INT); return (trq | TRAP_INT);
} }
return (trq & ~TRAP_INT); return (trq & ~TRAP_INT);
} }
/* Find vector for highest priority interrupt */ /* Find vector for highest priority interrupt
In a Qbus system, all device interrupts are treated as BR4 */
int32 get_vector (int32 nipl) int32 get_vector (int32 nipl)
{ {
int32 i, j, t, vec; int32 i, j, t, vec;
t_bool all_int = (UNIBUS || (nipl < IPL_HMIN));
for (i = IPL_HLVL - 1; i > nipl; i--) { /* loop thru lvls */ for (i = IPL_HLVL - 1; i > nipl; i--) { /* loop thru lvls */
t = int_req[i]; /* get level */ t = all_int? int_req[i]: (int_req[i] & int_internal[i]);
for (j = 0; t && (j < 32); j++) { /* srch level */ for (j = 0; t && (j < 32); j++) { /* srch level */
if ((t >> j) & 1) { /* irq found? */ if ((t >> j) & 1) { /* irq found? */
int_req[i] = int_req[i] & ~(1u << j); /* clr irq */ int_req[i] = int_req[i] & ~(1u << j); /* clr irq */

19
VAX/vax780_defs.h
View file

@ -1,6 +1,6 @@
/* vax780_defs.h: VAX 780 model-specific definitions file /* vax780_defs.h: VAX 780 model-specific definitions file
Copyright (c) 2004-2008, Robert M Supnik Copyright (c) 2004-2011, Robert M Supnik
Permission is hereby granted, free of charge, to any person obtaining a Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"), copy of this software and associated documentation files (the "Software"),
@ -23,6 +23,8 @@
used in advertising or otherwise to promote the sale, use or other dealings used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Robert M Supnik. in this Software without prior written authorization from Robert M Supnik.
26-Nov-11 MP Changed RQ amd TQ BR levels to BR4 to reflect real hardware
25-Nov-11 RMS Added VEC_QBUS definition
19-Nov-08 RMS Moved I/O support routines to I/O library 19-Nov-08 RMS Moved I/O support routines to I/O library
29-Apr-07 RMS Modified model-specific reserved operand check macros 29-Apr-07 RMS Modified model-specific reserved operand check macros
to reflect 780 microcode patches (found by Naoki Hamada) to reflect 780 microcode patches (found by Naoki Hamada)
@ -317,16 +319,16 @@ typedef struct {
#define INT_V_DZTX 1 #define INT_V_DZTX 1
#define INT_V_HK 2 #define INT_V_HK 2
#define INT_V_RL 3 #define INT_V_RL 3
#define INT_V_RQ 4 #define INT_V_TS 4
#define INT_V_TQ 5 #define INT_V_RY 5
#define INT_V_TS 6 #define INT_V_XU 6
#define INT_V_RY 7
#define INT_V_XU 8
#define INT_V_LPT 0 /* BR4 */ #define INT_V_LPT 0 /* BR4 */
#define INT_V_PTR 1 #define INT_V_PTR 1
#define INT_V_PTP 2 #define INT_V_PTP 2
#define INT_V_CR 3 #define INT_V_CR 3
#define INT_V_RQ 4
#define INT_V_TQ 5
#define INT_DZRX (1u << INT_V_DZRX) #define INT_DZRX (1u << INT_V_DZRX)
#define INT_DZTX (1u << INT_V_DZTX) #define INT_DZTX (1u << INT_V_DZTX)
@ -346,8 +348,8 @@ typedef struct {
#define IPL_DZTX (0x15 - IPL_HMIN) #define IPL_DZTX (0x15 - IPL_HMIN)
#define IPL_HK (0x15 - IPL_HMIN) #define IPL_HK (0x15 - IPL_HMIN)
#define IPL_RL (0x15 - IPL_HMIN) #define IPL_RL (0x15 - IPL_HMIN)
#define IPL_RQ (0x15 - IPL_HMIN) #define IPL_RQ (0x14 - IPL_HMIN)
#define IPL_TQ (0x15 - IPL_HMIN) #define IPL_TQ (0x14 - IPL_HMIN)
#define IPL_TS (0x15 - IPL_HMIN) #define IPL_TS (0x15 - IPL_HMIN)
#define IPL_RY (0x15 - IPL_HMIN) #define IPL_RY (0x15 - IPL_HMIN)
#define IPL_XU (0x15 - IPL_HMIN) #define IPL_XU (0x15 - IPL_HMIN)
@ -358,6 +360,7 @@ typedef struct {
/* Device vectors */ /* Device vectors */
#define VEC_QBUS 0
#define VEC_Q 0000 #define VEC_Q 0000
#define VEC_PTR 0070 #define VEC_PTR 0070
#define VEC_PTP 0074 #define VEC_PTP 0074

16
VAX/vax_cpu1.c
View file

@ -23,6 +23,7 @@
used in advertising or otherwise to promote the sale, use or other dealings used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Robert M Supnik. in this Software without prior written authorization from Robert M Supnik.
25-Nov-11 RMS Added VEC_QBUS test in interrupt handler
23-Mar-11 RMS Revised idle design (from Mark Pizzolato) 23-Mar-11 RMS Revised idle design (from Mark Pizzolato)
28-May-08 RMS Inlined physical memory routines 28-May-08 RMS Inlined physical memory routines
29-Apr-07 RMS Separated base register access checks for 11/780 29-Apr-07 RMS Separated base register access checks for 11/780
@ -1099,7 +1100,7 @@ return (R[0]? 0: CC_Z);
/* Interrupt or exception /* Interrupt or exception
vec = SCB vector vec = SCB vector (bit<0> = interrupt in Qbus mode)
cc = condition codes cc = condition codes
ipl = new IPL if interrupt ipl = new IPL if interrupt
ei = -1: severe exception ei = -1: severe exception
@ -1118,8 +1119,8 @@ int32 acc;
in_ie = 1; /* flag int/exc */ in_ie = 1; /* flag int/exc */
CLR_TRAPS; /* clear traps */ CLR_TRAPS; /* clear traps */
newpc = ReadLP ((SCBB + vec) & PAMASK); /* read new PC */ newpc = ReadLP ((SCBB + vec) & (PAMASK & ~3)); /* read new PC */
if (ei < 0) /* severe? on istk */ if (ei == IE_SVE) /* severe? on istk */
newpc = newpc | 1; newpc = newpc | 1;
if (newpc & 2) /* bad flags? */ if (newpc & 2) /* bad flags? */
ABORT (STOP_ILLVEC); ABORT (STOP_ILLVEC);
@ -1136,8 +1137,13 @@ else {
SP = KSP; /* new stack */ SP = KSP; /* new stack */
} }
} }
if (ei > 0) /* if int, new IPL */ if (ei == IE_INT) { /* if int, new IPL */
PSL = newpsl | (ipl << PSL_V_IPL); int32 newipl;
if (VEC_QBUS && ((vec & VEC_Q) != 0)) /* Qbus and Qbus vector? */
newipl = PSL_IPL17; /* force IPL 17 */
else newipl = ipl << PSL_V_IPL; /* otherwise, int IPL */
PSL = newpsl | newipl;
}
else PSL = newpsl | /* exc, old IPL/1F */ else PSL = newpsl | /* exc, old IPL/1F */
((newpc & 1)? PSL_IPL1F: (oldpsl & PSL_IPL)) | (oldcur << PSL_V_PRV); ((newpc & 1)? PSL_IPL1F: (oldpsl & PSL_IPL)) | (oldcur << PSL_V_PRV);
if (DEBUG_PRI (cpu_dev, LOG_CPU_I)) if (DEBUG_PRI (cpu_dev, LOG_CPU_I))

1
VAX/vax_defs.h
View file

@ -188,6 +188,7 @@
#define PSL_M_IPL 0x1F #define PSL_M_IPL 0x1F
#define PSL_IPL (PSL_M_IPL << PSL_V_IPL) #define PSL_IPL (PSL_M_IPL << PSL_V_IPL)
#define PSL_IPL1 (0x01 << PSL_V_IPL) #define PSL_IPL1 (0x01 << PSL_V_IPL)
#define PSL_IPL17 (0x17 << PSL_V_IPL)
#define PSL_IPL1F (0x1F << PSL_V_IPL) #define PSL_IPL1F (0x1F << PSL_V_IPL)
#define PSL_MBZ (0x30200000 | PSW_MBZ) /* must be zero */ #define PSL_MBZ (0x30200000 | PSW_MBZ) /* must be zero */
#define PSW_MBZ 0xFF00 /* must be zero */ #define PSW_MBZ 0xFF00 /* must be zero */

66
VAX/vaxmod_defs.h
View file

@ -1,6 +1,6 @@
/* vaxmod_defs.h: VAX model-specific definitions file /* vaxmod_defs.h: VAX model-specific definitions file
Copyright (c) 1998-2007, Robert M Supnik Copyright (c) 1998-2011, Robert M Supnik
Permission is hereby granted, free of charge, to any person obtaining a Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"), copy of this software and associated documentation files (the "Software"),
@ -23,6 +23,8 @@
used in advertising or otherwise to promote the sale, use or other dealings used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Robert M Supnik. in this Software without prior written authorization from Robert M Supnik.
11-Dec-11 RMS Moved all Qbus devices to BR4; deleted RP definitions
25-Nov-11 RMS Added VEC_QBUS definition
29-Apr-07 RMS Separated checks for PxBR and SBR 29-Apr-07 RMS Separated checks for PxBR and SBR
17-May-06 RMS Added CR11/CD11 support 17-May-06 RMS Added CR11/CD11 support
10-May-06 RMS Added NOP'd reserved operand checking macros 10-May-06 RMS Added NOP'd reserved operand checking macros
@ -317,7 +319,8 @@ typedef struct {
#define IOBA_PTP (IOPAGEBASE + 017554) /* PC11 punch */ #define IOBA_PTP (IOPAGEBASE + 017554) /* PC11 punch */
#define IOLN_PTP 004 #define IOLN_PTP 004
/* The KA65x maintains 4 separate hardware IPL levels, IPL 17 to IPL 14 /* The KA65x maintains 4 separate hardware IPL levels, IPL 17 to IPL 14;
however, DEC Qbus controllers all interrupt on IPL 14
Within each IPL, priority is right to left Within each IPL, priority is right to left
*/ */
@ -329,38 +332,36 @@ typedef struct {
/* IPL 15 */ /* IPL 15 */
/* IPL 14 - devices through RY are IPL 15 on Unibus systems */
#define INT_V_RQ 0 /* RQDX3 */ #define INT_V_RQ 0 /* RQDX3 */
#define INT_V_RL 1 /* RLV12/RL02 */ #define INT_V_RL 1 /* RLV12/RL02 */
#define INT_V_DZRX 2 /* DZ11 */ #define INT_V_DZRX 2 /* DZ11 */
#define INT_V_DZTX 3 #define INT_V_DZTX 3
#define INT_V_RP 4 /* RP,RM drives */ #define INT_V_TS 4 /* TS11/TSV05 */
#define INT_V_TS 5 /* TS11/TSV05 */ #define INT_V_TQ 5 /* TMSCP */
#define INT_V_TQ 6 /* TMSCP */ #define INT_V_XQ 6 /* DEQNA/DELQA */
#define INT_V_XQ 7 /* DEQNA/DELQA */ #define INT_V_RY 7 /* RXV21 */
#define INT_V_RY 8 /* RXV21 */
/* IPL 14 */ #define INT_V_TTI 8 /* console */
#define INT_V_TTO 9
#define INT_V_TTI 0 /* console */ #define INT_V_PTR 10 /* PC11 */
#define INT_V_TTO 1 #define INT_V_PTP 11
#define INT_V_PTR 2 /* PC11 */ #define INT_V_LPT 12 /* LP11 */
#define INT_V_PTP 3 #define INT_V_CSI 13 /* SSC cons UART */
#define INT_V_LPT 4 /* LP11 */ #define INT_V_CSO 14
#define INT_V_CSI 5 /* SSC cons UART */ #define INT_V_TMR0 15 /* SSC timers */
#define INT_V_CSO 6 #define INT_V_TMR1 16
#define INT_V_TMR0 7 /* SSC timers */ #define INT_V_VHRX 17 /* DHQ11 */
#define INT_V_TMR1 8 #define INT_V_VHTX 18
#define INT_V_VHRX 9 /* DHQ11 */ #define INT_V_QDSS 19 /* QDSS */
#define INT_V_VHTX 10 #define INT_V_CR 20
#define INT_V_QDSS 11 /* QDSS */
#define INT_V_CR 12
#define INT_CLK (1u << INT_V_CLK) #define INT_CLK (1u << INT_V_CLK)
#define INT_RQ (1u << INT_V_RQ) #define INT_RQ (1u << INT_V_RQ)
#define INT_RL (1u << INT_V_RL) #define INT_RL (1u << INT_V_RL)
#define INT_DZRX (1u << INT_V_DZRX) #define INT_DZRX (1u << INT_V_DZRX)
#define INT_DZTX (1u << INT_V_DZTX) #define INT_DZTX (1u << INT_V_DZTX)
#define INT_RP (1u << INT_V_RP)
#define INT_TS (1u << INT_V_TS) #define INT_TS (1u << INT_V_TS)
#define INT_TQ (1u << INT_V_TQ) #define INT_TQ (1u << INT_V_TQ)
#define INT_XQ (1u << INT_V_XQ) #define INT_XQ (1u << INT_V_XQ)
@ -380,15 +381,14 @@ typedef struct {
#define INT_CR (1u << INT_V_CR) #define INT_CR (1u << INT_V_CR)
#define IPL_CLK (0x16 - IPL_HMIN) /* relative IPL */ #define IPL_CLK (0x16 - IPL_HMIN) /* relative IPL */
#define IPL_RQ (0x15 - IPL_HMIN) #define IPL_RQ (0x14 - IPL_HMIN)
#define IPL_RL (0x15 - IPL_HMIN) #define IPL_RL (0x14 - IPL_HMIN)
#define IPL_DZRX (0x15 - IPL_HMIN) #define IPL_DZRX (0x14 - IPL_HMIN)
#define IPL_DZTX (0x15 - IPL_HMIN) #define IPL_DZTX (0x14 - IPL_HMIN)
#define IPL_RP (0x15 - IPL_HMIN) #define IPL_TS (0x14 - IPL_HMIN)
#define IPL_TS (0x15 - IPL_HMIN) #define IPL_TQ (0x14 - IPL_HMIN)
#define IPL_TQ (0x15 - IPL_HMIN) #define IPL_XQ (0x14 - IPL_HMIN)
#define IPL_XQ (0x15 - IPL_HMIN) #define IPL_RY (0x14 - IPL_HMIN)
#define IPL_RY (0x15 - IPL_HMIN)
#define IPL_TTI (0x14 - IPL_HMIN) #define IPL_TTI (0x14 - IPL_HMIN)
#define IPL_TTO (0x14 - IPL_HMIN) #define IPL_TTO (0x14 - IPL_HMIN)
#define IPL_PTR (0x14 - IPL_HMIN) #define IPL_PTR (0x14 - IPL_HMIN)
@ -410,6 +410,7 @@ typedef struct {
/* Device vectors */ /* Device vectors */
#define VEC_QBUS 1 /* Qbus system */
#define VEC_Q 0x200 /* Qbus vector offset */ #define VEC_Q 0x200 /* Qbus vector offset */
#define VEC_PTR (VEC_Q + 0070) #define VEC_PTR (VEC_Q + 0070)
#define VEC_PTP (VEC_Q + 0074) #define VEC_PTP (VEC_Q + 0074)
@ -420,7 +421,6 @@ typedef struct {
#define VEC_LPT (VEC_Q + 0200) #define VEC_LPT (VEC_Q + 0200)
#define VEC_TS (VEC_Q + 0224) #define VEC_TS (VEC_Q + 0224)
#define VEC_CR (VEC_Q + 0230) #define VEC_CR (VEC_Q + 0230)
#define VEC_RP (VEC_Q + 0254)
#define VEC_TQ (VEC_Q + 0260) #define VEC_TQ (VEC_Q + 0260)
#define VEC_RX (VEC_Q + 0264) #define VEC_RX (VEC_Q + 0264)
#define VEC_RY (VEC_Q + 0264) #define VEC_RY (VEC_Q + 0264)