Added generic ability to have up to 32 DZ Multiplexers enabled in a system. The default is 4 which provides 16 lines on a Qbus system and 32 lines on a UNIBUS system.
This commit is contained in:
Mark Pizzolato
parent
417102c5c4
commit
954cb3405f
1 changed files with 38 additions and 30 deletions
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@ -84,6 +84,11 @@ extern int32 int_req[IPL_HLVL];
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#if !defined (DZ_LINES)
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#define DZ_LINES 8
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#endif
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#define MAX_DZ_MUXES 32
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#if DZ_MUXES > MAX_DZ_MUXES
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#error "Too many DZ multiplexers"
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#endif
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#define DZ_MNOMASK (DZ_MUXES - 1) /* mask for mux no */
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#define DZ_LNOMASK (DZ_LINES - 1) /* mask for lineno */
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@ -146,19 +151,19 @@ extern int32 sim_switches;
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extern FILE *sim_log;
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extern int32 tmxr_poll; /* calibrated delay */
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uint16 dz_csr[DZ_MUXES] = { 0 }; /* csr */
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uint16 dz_rbuf[DZ_MUXES] = { 0 }; /* rcv buffer */
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uint16 dz_lpr[DZ_MUXES] = { 0 }; /* line param */
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uint16 dz_tcr[DZ_MUXES] = { 0 }; /* xmit control */
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uint16 dz_msr[DZ_MUXES] = { 0 }; /* modem status */
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uint16 dz_tdr[DZ_MUXES] = { 0 }; /* xmit data */
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uint8 dz_sae[DZ_MUXES] = { 0 }; /* silo alarm enabled */
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uint16 dz_csr[MAX_DZ_MUXES] = { 0 }; /* csr */
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uint16 dz_rbuf[MAX_DZ_MUXES] = { 0 }; /* rcv buffer */
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uint16 dz_lpr[MAX_DZ_MUXES] = { 0 }; /* line param */
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uint16 dz_tcr[MAX_DZ_MUXES] = { 0 }; /* xmit control */
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uint16 dz_msr[MAX_DZ_MUXES] = { 0 }; /* modem status */
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uint16 dz_tdr[MAX_DZ_MUXES] = { 0 }; /* xmit data */
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uint8 dz_sae[MAX_DZ_MUXES] = { 0 }; /* silo alarm enabled */
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uint32 dz_rxi = 0; /* rcv interrupts */
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uint32 dz_txi = 0; /* xmt interrupts */
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int32 dz_mctl = 0; /* modem ctrl enabled */
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int32 dz_auto = 0; /* autodiscon enabled */
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TMLN dz_ldsc[DZ_MUXES * DZ_LINES] = { {0} }; /* line descriptors */
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TMXR dz_desc = { DZ_MUXES * DZ_LINES, 0, 0, dz_ldsc }; /* mux descriptor */
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TMLN *dz_ldsc = NULL; /* line descriptors */
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TMXR dz_desc = { DZ_MUXES * DZ_LINES, 0, 0, NULL }; /* mux descriptor */
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/* debugging bitmaps */
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#define DBG_REG 0x0001 /* trace read/write registers */
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@ -211,15 +216,15 @@ DIB dz_dib = {
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UNIT dz_unit = { UDATA (&dz_svc, UNIT_IDLE|UNIT_ATTABLE|DZ_8B_DFLT, 0) };
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REG dz_reg[] = {
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{ BRDATA (CSR, dz_csr, DEV_RDX, 16, DZ_MUXES) },
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{ BRDATA (RBUF, dz_rbuf, DEV_RDX, 16, DZ_MUXES) },
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{ BRDATA (LPR, dz_lpr, DEV_RDX, 16, DZ_MUXES) },
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{ BRDATA (TCR, dz_tcr, DEV_RDX, 16, DZ_MUXES) },
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{ BRDATA (MSR, dz_msr, DEV_RDX, 16, DZ_MUXES) },
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{ BRDATA (TDR, dz_tdr, DEV_RDX, 16, DZ_MUXES) },
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{ BRDATA (SAENB, dz_sae, DEV_RDX, 1, DZ_MUXES) },
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{ GRDATA (RXINT, dz_rxi, DEV_RDX, DZ_MUXES, 0) },
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{ GRDATA (TXINT, dz_txi, DEV_RDX, DZ_MUXES, 0) },
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{ BRDATA (CSR, dz_csr, DEV_RDX, 16, MAX_DZ_MUXES) },
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{ BRDATA (RBUF, dz_rbuf, DEV_RDX, 16, MAX_DZ_MUXES) },
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{ BRDATA (LPR, dz_lpr, DEV_RDX, 16, MAX_DZ_MUXES) },
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{ BRDATA (TCR, dz_tcr, DEV_RDX, 16, MAX_DZ_MUXES) },
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{ BRDATA (MSR, dz_msr, DEV_RDX, 16, MAX_DZ_MUXES) },
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{ BRDATA (TDR, dz_tdr, DEV_RDX, 16, MAX_DZ_MUXES) },
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{ BRDATA (SAENB, dz_sae, DEV_RDX, 1, MAX_DZ_MUXES) },
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{ GRDATA (RXINT, dz_rxi, DEV_RDX, MAX_DZ_MUXES, 0) },
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{ GRDATA (TXINT, dz_txi, DEV_RDX, MAX_DZ_MUXES, 0) },
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{ FLDATA (MDMCTL, dz_mctl, 0) },
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{ FLDATA (AUTODS, dz_auto, 0) },
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{ GRDATA (DEVADDR, dz_dib.ba, DEV_RDX, 32, 0), REG_HRO },
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@ -421,7 +426,7 @@ t_stat dz_svc (UNIT *uptr)
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{
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int32 dz, t, newln;
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for (dz = t = 0; dz < DZ_MUXES; dz++) /* check enabled */
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for (dz = t = 0; dz < dz_desc.lines/DZ_LINES; dz++) /* check enabled */
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t = t | (dz_csr[dz] & CSR_MSE);
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if (t) { /* any enabled? */
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newln = tmxr_poll_conn (&dz_desc); /* poll connect */
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@ -461,10 +466,10 @@ return c;
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void dz_update_rcvi (void)
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{
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int32 i, dz, line, scnt[DZ_MUXES];
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int32 i, dz, line, scnt[MAX_DZ_MUXES];
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TMLN *lp;
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for (dz = 0; dz < DZ_MUXES; dz++) { /* loop thru muxes */
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for (dz = 0; dz < dz_desc.lines/DZ_LINES; dz++) { /* loop thru muxes */
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scnt[dz] = 0; /* clr input count */
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for (i = 0; i < DZ_LINES; i++) { /* poll lines */
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line = (dz * DZ_LINES) + i; /* get line num */
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@ -474,7 +479,7 @@ for (dz = 0; dz < DZ_MUXES; dz++) { /* loop thru muxes */
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dz_msr[dz] &= ~(1 << (i + MSR_V_CD)); /* reset car det */
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}
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}
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for (dz = 0; dz < DZ_MUXES; dz++) { /* loop thru muxes */
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for (dz = 0; dz < dz_desc.lines/DZ_LINES; dz++) { /* loop thru muxes */
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if (scnt[dz] && (dz_csr[dz] & CSR_MSE)) { /* input & enabled? */
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dz_csr[dz] |= CSR_RDONE; /* set done */
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if (dz_sae[dz] && (scnt[dz] >= DZ_SILO_ALM)) { /* alm enb & cnt hi? */
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@ -498,7 +503,7 @@ void dz_update_xmti (void)
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{
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int32 dz, linemask, i, j, line;
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for (dz = 0; dz < DZ_MUXES; dz++) { /* loop thru muxes */
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for (dz = 0; dz < dz_desc.lines/DZ_LINES; dz++) { /* loop thru muxes */
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linemask = dz_tcr[dz] & DZ_LMASK; /* enabled lines */
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dz_csr[dz] &= ~CSR_TRDY; /* assume not rdy */
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j = CSR_GETTL (dz_csr[dz]); /* start at current */
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@ -540,7 +545,7 @@ int32 dz_rxinta (void)
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{
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int32 dz;
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for (dz = 0; dz < DZ_MUXES; dz++) { /* find 1st mux */
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for (dz = 0; dz < dz_desc.lines/DZ_LINES; dz++) { /* find 1st mux */
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if (dz_rxi & (1 << dz)) {
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sim_debug(DBG_INT, &dz_dev, "dz_rzinta(dz=%d)\n", dz);
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dz_clr_rxint (dz); /* clear intr */
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@ -570,7 +575,7 @@ int32 dz_txinta (void)
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{
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int32 dz;
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for (dz = 0; dz < DZ_MUXES; dz++) { /* find 1st mux */
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for (dz = 0; dz < dz_desc.lines/DZ_LINES; dz++) { /* find 1st mux */
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if (dz_txi & (1 << dz)) {
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sim_debug(DBG_INT, &dz_dev, "dz_txinta(dz=%d)\n", dz);
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dz_clr_txint (dz); /* clear intr */
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@ -609,7 +614,9 @@ t_stat dz_reset (DEVICE *dptr)
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{
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int32 i, ndev;
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for (i = 0; i < DZ_MUXES; i++) /* init muxes */
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if (dz_ldsc == NULL)
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dz_desc.ldsc = dz_ldsc = calloc (dz_desc.lines, sizeof(*dz_ldsc));
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for (i = 0; i < dz_desc.lines/DZ_LINES; i++) /* init muxes */
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dz_clear (i, TRUE);
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dz_rxi = dz_txi = 0; /* clr master int */
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CLR_INT (DZRX);
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@ -661,7 +668,7 @@ t_stat r;
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if (cptr == NULL)
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return SCPE_ARG;
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newln = (int32) get_uint (cptr, 10, (DZ_MUXES * DZ_LINES), &r);
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newln = (int32) get_uint (cptr, 10, (MAX_DZ_MUXES * DZ_LINES), &r);
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if ((r != SCPE_OK) || (newln == dz_desc.lines))
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return r;
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if ((newln == 0) || (newln % DZ_LINES))
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@ -682,8 +689,9 @@ if (newln < dz_desc.lines) {
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}
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dz_dib.lnt = (newln / DZ_LINES) * IOLN_DZ; /* set length */
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dz_desc.lines = newln;
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dz_desc.ldsc = dz_ldsc = realloc(dz_ldsc, dz_desc.lines*sizeof(*dz_ldsc));
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ndev = ((dz_dev.flags & DEV_DIS)? 0: (dz_desc.lines / DZ_LINES));
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return auto_config (dz_dev.name, ndev); /* auto config */
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return dz_reset (&dz_dev); /* setup lines and auto config */
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}
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/* SET LOG processor */
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@ -700,7 +708,7 @@ tptr = strchr (cptr, '=');
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if ((tptr == NULL) || (*tptr == 0))
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return SCPE_ARG;
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*tptr++ = 0;
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ln = (int32) get_uint (cptr, 10, (DZ_MUXES * DZ_LINES), &r);
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ln = (int32) get_uint (cptr, 10, dz_desc.lines, &r);
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if ((r != SCPE_OK) || (ln >= dz_desc.lines))
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return SCPE_ARG;
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return tmxr_set_log (NULL, ln, tptr, desc);
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@ -715,7 +723,7 @@ int32 ln;
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if (cptr == NULL)
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return SCPE_ARG;
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ln = (int32) get_uint (cptr, 10, (DZ_MUXES * DZ_LINES), &r);
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ln = (int32) get_uint (cptr, 10, dz_desc.lines, &r);
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if ((r != SCPE_OK) || (ln >= dz_desc.lines))
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return SCPE_ARG;
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return tmxr_set_nolog (NULL, ln, NULL, desc);
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