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MicroVAX I: Make SID register reflect D-FLOAT or G-FLOAT instruction set

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- Limit choices to explicitly either G-FLOAT or D-FLOAT for SET CPU INST=
- Compile in all instruction implementations and dynamically use the
  enabled ones.
This commit is contained in:
Mark Pizzolato 2019-04-30 17:39:56 -07:00
parent 621e97e170
commit 95c24b4f81
6 changed files with 47 additions and 43 deletions
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7
VAX/vax610_defs.h
View file

@ -54,7 +54,7 @@
/* Microcode constructs */
#define VAX610_SID (7 << 24) /* system ID */
#define VAX610_FLOAT (1 << 16) /* floating point type */
#define VAX610_FLOAT (1 << 16) /* floating point type D=1, G=0 */
#define VAX610_MREV (5 << 8) /* microcode revision */
#define VAX610_HWREV 1 /* hardware revision */
#define CON_HLTPIN 0x0200 /* external CPU halt */
@ -98,10 +98,11 @@
{ MTAB_XTD|MTAB_VDV, 0, "MODEL", "MODEL={MicroVAX|VAXStation}", \
&cpu_set_model, &cpu_show_model, NULL, "Set/Show the simulator CPU Model" },
#define CPU_INSTRUCTION_SET (VAX_BASE | VAX_GFLOAT)
#define CPU_INST_MODIFIERS { MTAB_XTD|MTAB_VDV|MTAB_VALR|MTAB_NMO, 0, "INSTRUCTIONS", "INSTRUCTIONS={G-FLOAT|NOG-FLOAT|D-FLOAT|NOD-FLOAT}", \
&cpu_set_instruction_set, NULL, NULL, "Set the CPU Instruction Set" }, \
#define CPU_INST_MODIFIERS { MTAB_XTD|MTAB_VDV|MTAB_VALR|MTAB_NMO, 0, "INSTRUCTIONS", "INSTRUCTIONS={G-FLOAT|D-FLOAT}", \
&vax610_set_instruction_set, NULL, NULL, "Set the CPU Instruction Set" }, \
{ MTAB_XTD|MTAB_VDV, 0, "INSTRUCTIONS", NULL, \
NULL, &cpu_show_instruction_set, NULL, "Show the CPU Instruction Set (SHOW -V)" },
t_stat vax610_set_instruction_set (UNIT *uptr, int32 val, CONST char *cptr, void *desc);
/* QVSS memory space */

17
VAX/vax610_sysdev.c
View file

@ -156,7 +156,7 @@ switch (rg) {
break;
case MT_SID: /* SID */
val = (VAX610_SID | VAX610_FLOAT | VAX610_MREV | VAX610_HWREV);
val = (VAX610_SID | ((cpu_instruction_set & VAX_DFLOAT) ? VAX610_FLOAT: 0) | VAX610_MREV | VAX610_HWREV);
break;
case MT_NICR: /* NICR */
@ -514,6 +514,21 @@ AP = 1;
return SCPE_OK;
}
t_stat vax610_set_instruction_set (UNIT *uptr, int32 val, CONST char *cptr, void *desc)
{
char gbuf[CBUFSIZE];
if (!cptr || !*cptr)
return SCPE_ARG;
get_glyph (cptr, gbuf, 0);
if (MATCH_CMD(gbuf, "G-FLOAT") == 0)
return cpu_set_instruction_set (uptr, val, "G-FLOAT;NOD-FLOAT", NULL);
if (MATCH_CMD(gbuf, "D-FLOAT") == 0)
return cpu_set_instruction_set (uptr, val, "D-FLOAT;NOG-FLOAT", NULL);
return sim_messagef (SCPE_ARG, "Unknown/Unsupported instruction set: %s\n", gbuf);
}
/* SYSD reset */
t_stat sysd_reset (DEVICE *dptr)

33
VAX/vax_cis.c
View file

@ -53,8 +53,6 @@
#include "vax_defs.h"
#if defined (FULL_VAX)
/* Decimal string structure */
#define DSTRLNT 4
@ -109,6 +107,18 @@ t_stat r;
DSTR accum, src1, src2, dst;
DSTR mptable[10];
if (!(((IG_PACKD == DR_GETIGRP(drom[opc][0])) &&
(cpu_instruction_set & VAX_PACKED)) ||
((IG_EMONL == DR_GETIGRP(drom[opc][0])) &&
(cpu_instruction_set & VAX_EMONL)))) { /* Emulated? */
/* CIS and emulate only instructions - invoke emulator interface
opnd[0:5] = six operands to be pushed (if PSL<fpd> = 0)
cc = condition codes
opc = opcode
*/
return cpu_emulate_exception (op, cc, opc, acc);
}
switch (opc) { /* case on opcode */
/* MOVTC
@ -1643,22 +1653,3 @@ sign = Read ((R[3] + 1) & LMASK, L_BYTE, RA); /* read */
R[2] = ED_PUTSIGN (R[2], sign); /* now fault safe */
return sign;
}
#else
extern int32 cpu_emulate_exception (int32 *opnd, int32 cc, int32 opc, int32 acc);
/* CIS instructions - invoke emulator interface
opnd[0:5] = six operands to be pushed (if PSL<fpd> = 0)
cc = condition codes
opc = opcode
*/
int32 op_cis (int32 *opnd, int32 cc, int32 opc, int32 acc)
{
return cpu_emulate_exception (opnd, cc, opc, acc);
}
#endif

12
VAX/vax_cpu.c
View file

@ -736,12 +736,12 @@ for ( ;; ) {
#endif
#if defined(VAX_610)
/*
* This case is formally UNPREDICTABLE, but how the MicroVAX I CPU
* worked. Instructions without the DR_F in their drom table entry
* are specifically uninterruptible instructions, so this would not
* ever happen during normal execution, but the MicroVAX I HCORE
* diagnostic contrives this as a test and expects thost cases to
* be ignored.
* This case is formally UNPREDICTABLE, but it is how the MicroVAX I
* CPU worked. Instructions without the DR_F in their drom table
* entry are specifically uninterruptible instructions, so this
* would not ever happen during normal execution, but the MicroVAX I
* HCORE diagnostic contrives this as a test and expects thost cases
* to be ignored.
*/
if ((PSL & PSL_FPD) && (numspec & DR_F)) {
#else

4
VAX/vax_defs.h
View file

@ -842,6 +842,7 @@ extern int32 extra_bytes; /* bytes referenced by current string instru
extern BITFIELD cpu_psl_bits[];
extern char const * const opcode[];
extern const uint16 drom[NUM_INST][MAX_SPEC + 1];
extern int32 cpu_emulate_exception (int32 *opnd, int32 cc, int32 opc, int32 acc);
void cpu_idle (void);
/* Instruction History */
@ -970,6 +971,7 @@ extern int32 con_halt (int32 code, int32 cc);
extern t_stat cpu_boot (int32 unitno, DEVICE *dptr);
extern t_stat build_dib_tab (void);
extern void rom_wr_B (int32 pa, int32 val);
extern int32 cpu_instruction_set;
#if defined (VAX_780)
#include "vax780_defs.h"
@ -1027,6 +1029,8 @@ extern t_stat cpu_load_bootcode (const char *filename, const unsigned char *buil
extern t_stat cpu_print_model (FILE *st);
extern t_stat cpu_show_model (FILE *st, UNIT *uptr, int32 val, CONST void *desc);
extern t_stat cpu_set_model (UNIT *uptr, int32 val, CONST char *cptr, void *desc);
extern t_stat cpu_show_instruction_set (FILE *st, UNIT *uptr, int32 val, CONST void *desc);
extern t_stat cpu_set_instruction_set (UNIT *uptr, int32 val, CONST char *cptr, void *desc);
extern t_stat cpu_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr);
extern t_stat cpu_model_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr);
extern const uint32 byte_mask[33];

17
VAX/vax_octa.c
View file

@ -46,8 +46,6 @@
#include "vax_defs.h"
#if defined (FULL_VAX)
#define WORDSWAP(x) ((((x) & WMASK) << 16) | (((x) >> 16) & WMASK))
typedef struct {
@ -117,6 +115,11 @@ int32 op_octa (int32 *opnd, int32 cc, int32 opc, int32 acc, int32 spec, int32 va
int32 r, rh, temp, flg;
int32 r_octa[4];
if ((cpu_instruction_set & VAX_EXTAC) == 0) { /* Implemented? */
RSVD_INST_FAULT(opc);
return cc;
}
switch (opc) {
/* PUSHAO
@ -1256,13 +1259,3 @@ else {
}
return;
}
#else
int32 op_octa (int32 *opnd, int32 cc, int32 opc, int32 acc, int32 spec, int32 va, InstHistory *hst)
{
RSVD_INST_FAULT(opc);
return cc;
}
#endif