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Intel-Systems: Reorganize for clean builds with Release targets.

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This commit is contained in:
Bill Beech 2020-08-02 14:19:52 -07:00
parent 6fdc447410
commit 964cb721ed
69 changed files with 2805 additions and 425 deletions
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4
Intel-Systems/common/i3214.c
View file

@ -40,6 +40,8 @@
#include "system_defs.h" #include "system_defs.h"
#if defined (I3214_NUM) && (I3214_NUM > 0)
// 3214 status bits // 3214 status bits
/* external globals */ /* external globals */
@ -207,4 +209,6 @@ uint8 i3214_monitor_do_boot(t_bool io, uint8 data, uint8 devnum)
return 0; return 0;
} }
#endif /* I3214_NUM > 0 */
/* end of i3214.c */ /* end of i3214.c */

2
Intel-Systems/common/i8080.c
View file

@ -406,7 +406,7 @@ int32 sim_instr(void)
sim_printf(" CPU = 8085\n"); sim_printf(" CPU = 8085\n");
else else
sim_printf(" CPU = 8080\n"); sim_printf(" CPU = 8080\n");
sim_printf(" i8080:\n"); // sim_printf(" i8080:\n");
} }
/* Main instruction fetch/decode loop */ /* Main instruction fetch/decode loop */

4
Intel-Systems/common/i8237.c
View file

@ -235,6 +235,8 @@
#include "system_defs.h" #include "system_defs.h"
#if defined (I8237_NUM) && (I8237_NUM > 0)
/* external globals */ /* external globals */
/* internal function prototypes */ /* internal function prototypes */
@ -841,4 +843,6 @@ uint8 i8237_rFx(t_bool io, uint8 data, uint8 devnum)
return 0; return 0;
} }
#endif /* I8237_NUM > 0 */
/* end of i8237.c */ /* end of i8237.c */

16
Intel-Systems/common/i8251.c
View file

@ -111,6 +111,8 @@
#include "system_defs.h" #include "system_defs.h"
#if defined (I8251_NUM) && (I8251_NUM > 0)
#define UNIT_V_ANSI (UNIT_V_UF + 0) /* ANSI mode */ #define UNIT_V_ANSI (UNIT_V_UF + 0) /* ANSI mode */
#define UNIT_ANSI (1 << UNIT_V_ANSI) #define UNIT_ANSI (1 << UNIT_V_ANSI)
@ -180,8 +182,8 @@ DEBTAB i8251_debug[] = {
}; };
MTAB i8251_mod[] = { MTAB i8251_mod[] = {
{ UNIT_ANSI, 0, "TTY", "TTY", NULL }, { UNIT_ANSI, 0, "ANSI", "ANSI", NULL },
{ UNIT_ANSI, UNIT_ANSI, "ANSI", "ANSI", NULL }, { UNIT_ANSI, UNIT_ANSI, "TTY", "TTY", NULL },
{ 0 } { 0 }
}; };
@ -234,12 +236,10 @@ t_stat i8251_svc (UNIT *uptr)
sim_activate (uptr, uptr->wait); /* continue poll */ sim_activate (uptr, uptr->wait); /* continue poll */
if ((temp = sim_poll_kbd ()) < SCPE_KFLAG) if ((temp = sim_poll_kbd ()) < SCPE_KFLAG)
return temp; /* no char or error? */ return temp; /* no char or error? */
uptr->buf = temp & 0xFF; /* Save char */ uptr->buf = temp & 0x7F; /* Save char */
if (uptr->flags & UNIT_ANSI)
uptr->buf = toupper(uptr->buf);
uptr->u3 |= RXR; /* Set status */ uptr->u3 |= RXR; /* Set status */
/* Do any special character handling here */
uptr->pos++;
return SCPE_OK; return SCPE_OK;
} }
@ -298,4 +298,6 @@ uint8 i8251d(t_bool io, uint8 data, uint8 devnum)
return 0; return 0;
} }
#endif /* I8251_NUM > 0 */
/* end of i8251.c */ /* end of i8251.c */

4
Intel-Systems/common/i8253.c
View file

@ -35,6 +35,8 @@
#include "system_defs.h" #include "system_defs.h"
#if defined (I8253_NUM) && (I8253_NUM > 0)
/* external globals */ /* external globals */
/* external function prototypes */ /* external function prototypes */
@ -206,4 +208,6 @@ uint8 i8253c(t_bool io, uint8 data, uint8 devnum)
return 0; return 0;
} }
#endif /* I8253_NUM > 0 */
/* end of i8253.c */ /* end of i8253.c */

4
Intel-Systems/common/i8255.c
View file

@ -77,6 +77,8 @@
#include "system_defs.h" /* system header in system dir */ #include "system_defs.h" /* system header in system dir */
#if defined (I8255_NUM) && (I8255_NUM > 0)
/* internal function prototypes */ /* internal function prototypes */
t_stat i8255_cfg(uint8 base, uint8 devnum); t_stat i8255_cfg(uint8 base, uint8 devnum);
@ -268,4 +270,6 @@ uint8 i8255c(t_bool io, uint8 data, uint8 devnum)
return 0; return 0;
} }
#endif /* I8255_NUM > 0 */
/* end of i8255.c */ /* end of i8255.c */

4
Intel-Systems/common/i8259.c
View file

@ -35,6 +35,8 @@
#include "system_defs.h" /* system header in system dir */ #include "system_defs.h" /* system header in system dir */
#if defined (I8259_NUM) && (I8259_NUM > 0)
/* function prototypes */ /* function prototypes */
t_stat i8259_cfg(uint8 base, uint8 devnum); t_stat i8259_cfg(uint8 base, uint8 devnum);
@ -244,4 +246,6 @@ void i8259_dump(uint8 devnum)
sim_printf(" OCW3=%02X\n", i8259_ocw3[devnum]); sim_printf(" OCW3=%02X\n", i8259_ocw3[devnum]);
} }
#endif /* I8259_NUM > 0 */
/* end of i8259.c */ /* end of i8259.c */

4
Intel-Systems/common/i8272.c
View file

@ -36,6 +36,8 @@
#include "system_defs.h" #include "system_defs.h"
#if defined (I8272_NUM) && (I8272_NUM > 0)
#define UNIT_V_WPMODE (UNIT_V_UF) /* Write protect */ #define UNIT_V_WPMODE (UNIT_V_UF) /* Write protect */
#define UNIT_WPMODE (1 << UNIT_V_WPMODE) #define UNIT_WPMODE (1 << UNIT_V_WPMODE)
@ -891,4 +893,6 @@ uint8 i8272_r01(t_bool io, uint8 data)
return 0; return 0;
} }
#endif /* I8272_NUM > 0 */
/* end of i8272.c */ /* end of i8272.c */

41
Intel-Systems/common/ieprom.c
View file

@ -40,10 +40,10 @@
/* function prototypes */ /* function prototypes */
t_stat EPROM_cfg(uint16 base, uint16 size); t_stat EPROM_cfg (uint16 base, uint16 size, uint8 devnum);
t_stat EPROM_attach (UNIT *uptr, CONST char *cptr); t_stat EPROM_attach (UNIT *uptr, CONST char *cptr);
t_stat EPROM_reset (DEVICE *dptr); t_stat EPROM_reset (DEVICE *dptr);
uint8 EPROM_get_mbyte(uint16 addr); uint8 EPROM_get_mbyte (uint16 addr, uint8 devnum);
/* external function prototypes */ /* external function prototypes */
@ -53,8 +53,9 @@ uint8 EPROM_get_mbyte(uint16 addr);
/* SIMH EPROM Standard I/O Data Structures */ /* SIMH EPROM Standard I/O Data Structures */
UNIT EPROM_unit = { UNIT EPROM_unit[] = {
UDATA (NULL, UNIT_ATTABLE+UNIT_BINK+UNIT_ROABLE+UNIT_RO+UNIT_BUFABLE+UNIT_MUSTBUF, 0), 0 {UDATA (NULL, UNIT_ATTABLE+UNIT_BINK+UNIT_ROABLE+UNIT_RO+UNIT_BUFABLE+UNIT_MUSTBUF, 0), 0},
{UDATA (NULL, UNIT_ATTABLE+UNIT_BINK+UNIT_ROABLE+UNIT_RO+UNIT_BUFABLE+UNIT_MUSTBUF, 0), 0}
}; };
DEBTAB EPROM_debug[] = { DEBTAB EPROM_debug[] = {
@ -70,10 +71,10 @@ DEBTAB EPROM_debug[] = {
DEVICE EPROM_dev = { DEVICE EPROM_dev = {
"EPROM", //name "EPROM", //name
&EPROM_unit, //units EPROM_unit, //units
NULL, //registers NULL, //registers
NULL, //modifiers NULL, //modifiers
1, //numunits EPROM_NUM, //numunits
16, //aradix 16, //aradix
16, //awidth 16, //awidth
1, //aincr 1, //aincr
@ -81,7 +82,7 @@ DEVICE EPROM_dev = {
8, //dwidth 8, //dwidth
NULL, //examine NULL, //examine
NULL, //deposit NULL, //deposit
EPROM_reset, //reset &EPROM_reset, //reset
NULL, //boot NULL, //boot
&EPROM_attach, //attach &EPROM_attach, //attach
NULL, //detach NULL, //detach
@ -97,12 +98,17 @@ DEVICE EPROM_dev = {
// EPROM configuration // EPROM configuration
t_stat EPROM_cfg(uint16 base, uint16 size) t_stat EPROM_cfg(uint16 base, uint16 size, uint8 devnum)
{ {
EPROM_unit.capac = size; /* set EPROM size */ EPROM_unit[devnum].capac = size; /* set EPROM size */
EPROM_unit.u3 = base & 0xFFFF; /* set EPROM base */ EPROM_unit[devnum].u3 = base & 0xFFFF; /* set EPROM base */
sim_printf(" EPROM: 0%04XH bytes at base 0%04XH\n", EPROM_unit[devnum].filebuf = (uint8 *)calloc(size, sizeof(uint8));
EPROM_unit.capac, EPROM_unit.u3); if (EPROM_unit[devnum].filebuf == NULL) {
sim_printf (" EPROM[%d]: Calloc error\n", devnum);
return SCPE_MEM;
}
sim_printf(" EPROM[%d]: 0%04XH bytes at base 0%04XH\n",
devnum, EPROM_unit[devnum].capac, EPROM_unit[devnum].u3);
return SCPE_OK; return SCPE_OK;
} }
@ -110,6 +116,10 @@ t_stat EPROM_cfg(uint16 base, uint16 size)
t_stat EPROM_reset (DEVICE *dptr) t_stat EPROM_reset (DEVICE *dptr)
{ {
// uint8 devnum;
// for (devnum = 0; devnum <= EPROM_NUM; devnum++) {
// }
return SCPE_OK; return SCPE_OK;
} }
@ -128,13 +138,12 @@ t_stat EPROM_attach (UNIT *uptr, CONST char *cptr)
/* get a byte from memory */ /* get a byte from memory */
uint8 EPROM_get_mbyte(uint16 addr) uint8 EPROM_get_mbyte(uint16 addr, uint8 devnum)
{ {
uint8 val; uint8 val;
val = *((uint8 *)EPROM_unit.filebuf + (addr - EPROM_unit.u3)); val = *((uint8 *)EPROM_unit[devnum].filebuf + (addr - EPROM_unit[devnum].u3));
val &= 0xFF; return (val &= 0xFF);
return val;
} }
/* end of iEPROM.c */ /* end of iEPROM.c */

144
Intel-Systems/common/ieprom1.c
View file

@ -1,144 +0,0 @@
/* iEPROM1.c: Intel EPROM simulator for 8-bit SBCs
Copyright (c) 2010, William A. Beech
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
WILLIAM A. BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
Except as contained in this notice, the name of William A. Beech shall not be
used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from William A. Beech.
MODIFICATIONS:
?? ??? 10 - Original file.
NOTES:
These functions support a simulated ROM devices on an iSBC-80/XX SBCs.
This allows the attachment of the device to a binary file containing the EPROM
code image. Unit will support a single 2708, 2716, 2732, or 2764 type EPROM.
These functions also support bit 1 of 8255 number 1, port B, to enable/
disable the onboard ROM.
*/
#include "system_defs.h"
/* function prototypes */
t_stat EPROM1_cfg(uint16 base, uint16 size);
t_stat EPROM1_attach (UNIT *uptr, CONST char *cptr);
t_stat EPROM1_reset (DEVICE *dptr);
uint8 EPROM1_get_mbyte(uint16 addr);
/* external function prototypes */
extern void multibus_put_mbyte(uint16 addr, uint8 val);
/* external globals */
extern uint8 xack; /* XACK signal */
/* globals */
/* SIMH EPROM Standard I/O Data Structures */
UNIT EPROM1_unit[] = {
UDATA (NULL, UNIT_ATTABLE+UNIT_BINK+UNIT_ROABLE+UNIT_RO+UNIT_BUFABLE+UNIT_MUSTBUF, 0), 0
};
DEBTAB EPROM1_debug[] = {
{ "ALL", DEBUG_all },
{ "FLOW", DEBUG_flow },
{ "READ", DEBUG_read },
{ "WRITE", DEBUG_write },
{ "XACK", DEBUG_xack },
{ "LEV1", DEBUG_level1 },
{ "LEV2", DEBUG_level2 },
{ NULL }
};
DEVICE EPROM1_dev = {
"EPROM1", //name
EPROM1_unit, //units
NULL, //registers
NULL, //modifiers
1, //numunits
16, //aradix
16, //awidth
1, //aincr
16, //dradix
8, //dwidth
NULL, //examine
NULL, //deposit
NULL, //reset
NULL, //boot
&EPROM1_attach, //attach
NULL, //detach
NULL, //ctxt
DEV_DEBUG, //flags
0, //dctrl
EPROM1_debug, //debflags
NULL, //msize
NULL //lname
};
/* EPROM functions */
// EPROM configuration
t_stat EPROM1_cfg(uint16 base, uint16 size)
{
EPROM1_unit->capac = size; /* set EPROM size */
EPROM1_unit->u3 = base & 0xFFFF; /* set EPROM base */
sim_printf(" EPROM1: 0%04XH bytes at base 0%04XH\n",
EPROM1_unit->capac, EPROM1_unit->u3);
return SCPE_OK;
}
/* EPROM reset */
t_stat EPROM1_reset (DEVICE *dptr)
{
return SCPE_OK;
}
/* EPROM attach */
t_stat EPROM1_attach (UNIT *uptr, CONST char *cptr)
{
t_stat r;
if ((r = attach_unit (uptr, cptr)) != SCPE_OK) {
sim_printf("EPROM1_attach: Error %d\n", r);
return r;
}
return SCPE_OK;
}
/* get a byte from memory */
uint8 EPROM1_get_mbyte(uint16 addr)
{
uint8 val;
val = *((uint8 *)EPROM1_unit->filebuf + (addr - EPROM1_unit->u3));
val &= 0xFF;
return val;
}
/* end of iEPROM1.c */

408
Intel-Systems/common/io.c Normal file
View file

@ -0,0 +1,408 @@
/* i0.c: Intel intellec imm8-60
Copyright (c) 2020, William A. Beech
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
WILLIAM A. BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
Except as contained in this notice, the name of William A. Beech shall not be
used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from William A. Beech.
MODIFICATIONS:
18 July 20 - Original file.
NOTES:
These functions support a simulated imm8-60 interface board attached to a
Teletype Model 33 ASR.
*/
#include "system_defs.h"
#if defined (IO_NUM) && (IO_NUM > 0)
// imm8-60 status bits
// I/O COMMAND CONSTANTS
#define RBIT 1 //TTY READER GO/NO GO
#define PCMD 2 //PTP GO/NO GO
#define RCMD 4 //PTR GO/NO GO
#define DSB 8 //PROM ENABLE/DISABLE. DSB=1
#define XXX 0x10 //DATA IN T/C
#define XXY 0x20 //DATA OUT T/C
#define PBIT 0x40 //1702 PROM PROG. GO/NO GO
#define PBITA 0x80 //1702A PROM PROG. GO/NO GO
// TTY I/O CONSTANTS
#define TTI 0 //TTY INPUT DATA PORT
#define TTO 0 //TTY OUTPUT DATA PORT
#define TTS 1 //TTY INPUT STATUS PORT
#define TTC 1 //TTY OUTPUT COMMAND PORT
#define TTYGO RBIT OR DSB //START TTY READER
#define TTYNO DSB //STOP TTY READER
#define TTYDA 1 //DATA AVAILABLE
#define TTYBE 4 //TRANSMIT BUFFER EMPTY
// CRT I/O CONSTANTS
#define CRTI 4 //CRT INPUT DATA PORT
#define CRTS 5 //CRT INPUT STATUS PORT
#define CRTO 4 //CRT OUTPUT DATA PORT
#define CRTDA 1 //DATA AVAILABLE
#define CRTBE 4 //TRANSMIT BUFFER EMPTY
// PTR I/O CONSTANTS
#define PTRI 3 //PTR INPUT DATA PORT (NOT INVERTED)
#define PTRS TTS //PTR INPUT STATUS PORT
#define PTRC TTC //PTR OUTPUT COMMAND PORT
#define PTRGO RCMD OR DSB //START PTR
#define PTRNO TTYNO //STOP PTR
#define PTRDA 0x20 //PTR DATA AVAILABLE
// PTP I/O CONSTANTS
#define PTPO 3 //PTP OUTPUT DATA PORT
#define PTPS TTS //PTP INPUT STATUS PORT
#define PTPC TTC //PTP OUTPUT COMMAND PORT
#define PRDY 0x40 //PUNCH READY STATUS
#define PTPGO PCMD OR DSB //PTP START PUNCH
#define PTPNO TTYNO //STOP PUNCH
// PROM PROGRAMMER I/O CONSTANTS
#define PAD 2 //PROM ADDRES OUTPUT PORT
#define PDO PTPO //PROM DATA OUTPUT PORT
#define PDI 2 //PROM DATA INPUT PORT
#define PROMC TTC //PROGRAMMING PULSE OUTPUT PORT
#define PROGO PBITA //START PROGRAMMING
#define PRONO 0 //STOP PROGRAMMING
#define ENB 0 //ENABLE PROGRAMMER
/* external globals */
/* external function prototypes */
extern uint8 reg_dev(uint8 (*routine)(t_bool, uint8, uint8), uint8, uint8);
/* globals */
uint8 status = 0;
uint8 command = 0;
/* function prototypes */
t_stat IO_cfg(uint8 base, uint8 devnum);
t_stat IO_svc (UNIT *uptr);
t_stat IO_reset (DEVICE *dptr);
t_stat IO_attach (UNIT *uptr, CONST char *cptr);
t_stat PTR_reset(DEVICE *dptr);
t_stat PTR_attach (UNIT *uptr, CONST char *cptr);
uint8 IO_is(t_bool io, uint8 data, uint8 devnum);
uint8 IO_id(t_bool io, uint8 data, uint8 devnum);
uint8 IO_oc(t_bool io, uint8 data, uint8 devnum);
uint8 IO_od(t_bool io, uint8 data, uint8 devnum);
void IO_reset_dev(uint8 devnum);
/* imm-60 Standard I/O Data Structures */
UNIT IO_unit[4] = {
{ UDATA (&IO_svc, 0, 0), 10 }, //TTY input/output
{ UDATA (&IO_svc, 0, 0), 10 }, //TTY status/command
{ UDATA (&IO_svc, 0, 0), KBD_POLL_WAIT }, //PROM data input/output
{ UDATA (0, UNIT_ATTABLE+UNIT_DISABLE+UNIT_BUFABLE+UNIT_MUSTBUF, 0x1000) } //TTY reader/punch
};
REG IO_reg[] = {
{ HRDATA (DATA0, IO_unit[0].buf, 8) },
{ HRDATA (STAT0, status, 8) },
{ HRDATA (MODE0, IO_unit[0].u4, 8) },
{ HRDATA (CMD0, IO_unit[0].u5, 8) },
{ HRDATA (DATA1, IO_unit[1].buf, 8) },
{ HRDATA (STAT1, status, 8) },
{ HRDATA (MODE1, IO_unit[1].u4, 8) },
{ HRDATA (CMD1, IO_unit[1].u5, 8) },
{ HRDATA (DATA2, IO_unit[2].buf, 8) },
{ HRDATA (STAT2, status, 8) },
{ HRDATA (MODE2, IO_unit[2].u4, 8) },
{ HRDATA (CMD2, IO_unit[2].u5, 8) },
{ HRDATA (DATA3, IO_unit[3].buf, 8) },
{ HRDATA (STAT3, status, 8) },
{ HRDATA (MODE3, IO_unit[3].u4, 8) },
{ HRDATA (CMD3, IO_unit[3].u5, 8) },
{ NULL }
};
DEBTAB IO_debug[] = {
{ "ALL", DEBUG_all },
{ "FLOW", DEBUG_flow },
{ "READ", DEBUG_read },
{ "WRITE", DEBUG_write },
{ "XACK", DEBUG_xack },
{ "LEV1", DEBUG_level1 },
{ "LEV2", DEBUG_level2 },
{ NULL }
};
MTAB IO_mod[] = {
{ 0 }
};
/* address width is set to 16 bits to use devices in 8086/8088 implementations */
DEVICE IO_dev = {
"IO", //name
IO_unit, //units
IO_reg, //registers
IO_mod, //modifiers
IO_NUM, //numunits
16, //aradix
16, //awidth
1, //aincr
16, //dradix
8, //dwidth
NULL, //examine
NULL, //deposit
&IO_reset, //reset
NULL, //boot
&IO_attach, //attach
NULL, //detach
NULL, //ctxt
0, //flags
0, //dctrl
IO_debug, //debflags
NULL, //msize
NULL //lname
};
UNIT PTR_unit[1] = {
{ UDATA (0, UNIT_ATTABLE+UNIT_DISABLE+UNIT_BUFABLE+UNIT_MUSTBUF, 0x1000) } //TTY reader/punch
};
REG PTR_reg[] = {
{ HRDATA (DATA0, IO_unit[0].buf, 8) },
{ HRDATA (STAT0, status, 8) },
{ HRDATA (MODE0, IO_unit[0].u4, 8) },
{ HRDATA (CMD0, IO_unit[0].u5, 8) },
{ NULL }
};
DEBTAB PTR_debug[] = {
{ "ALL", DEBUG_all },
{ "FLOW", DEBUG_flow },
{ "READ", DEBUG_read },
{ "WRITE", DEBUG_write },
{ "XACK", DEBUG_xack },
{ "LEV1", DEBUG_level1 },
{ "LEV2", DEBUG_level2 },
{ NULL }
};
MTAB PTR_mod[] = {
{ 0 }
};
/* address width is set to 16 bits to use devices in 8086/8088 implementations */
DEVICE PTR_dev = {
"PTR", //name
PTR_unit, //units
PTR_reg, //registers
PTR_mod, //modifiers
PTR_NUM, //numunits
16, //aradix
16, //awidth
1, //aincr
16, //dradix
8, //dwidth
NULL, //examine
NULL, //deposit
&PTR_reset, //reset
NULL, //boot
&PTR_attach, //attach
NULL, //detach
NULL, //ctxt
0, //flags
0, //dctrl
PTR_debug, //debflags
NULL, //msize
NULL //lname
};
// imm-60 configuration
t_stat IO_cfg(uint8 base, uint8 devnum)
{
sim_printf(" io[%d]: at base port 0%02XH\n",
devnum, base & 0xFF);
reg_dev(IO_id, base, devnum);
reg_dev(IO_is, base + 1, devnum);
reg_dev(IO_oc, base + 2, devnum);
reg_dev(IO_od, base + 3, devnum);
return SCPE_OK;
}
/* Service routines to handle simulator functions */
/* IO_svc - actually gets char & places in buffer */
t_stat IO_svc (UNIT *uptr)
{
int32 temp;
sim_activate (uptr, uptr->wait); /* continue poll */
if ((temp = sim_poll_kbd ()) < SCPE_KFLAG) {
status |= TTYDA; //clear data avail
return temp; /* no char or error? */
}
// if (command & RBIT) { //read from tty rdr
// printf("%c", (int)(uptr+3)->filebuf);
// }
uptr->buf = toupper(temp & 0x7F); /* Save char */
status &= ~TTYDA; /* Set data available status */
return SCPE_OK;
}
/* Reset routine */
t_stat IO_reset (DEVICE *dptr)
{
uint8 devnum;
for (devnum=0; devnum < IO_NUM; devnum++) {
IO_reset_dev(devnum);
sim_activate (&IO_unit[devnum], IO_unit[devnum].wait); /* activate unit */
}
return SCPE_OK;
}
void IO_reset_dev(uint8 devnum)
{
status = TTYDA | PTRDA | DSB; /* set data not avail status */
IO_unit[devnum].u4 = 0;
IO_unit[devnum].u5 = 0;
IO_unit[devnum].u6 = 0;
IO_unit[devnum].buf = 0;
IO_unit[devnum].pos = 0;
}
t_stat IO_attach (UNIT *uptr, CONST char *cptr)
{
t_stat r;
if ((r = attach_unit (uptr, cptr)) != SCPE_OK) {
sim_printf(" IO_attach: Attach error %d\n", r);
return r;
}
return SCPE_OK;
}
t_stat PTR_reset(DEVICE *dptr)
{
return SCPE_OK;
}
t_stat PTR_attach (UNIT *uptr, CONST char *cptr)
{
t_stat r;
if ((r = attach_unit (uptr, cptr)) != SCPE_OK) {
sim_printf(" PTR_attach: Attach error %d\n", r);
return r;
}
return SCPE_OK;
}
/* I/O instruction handlers, called from the CPU module when an
IN or OUT instruction is issued.
*/
// status/command
uint8 IO_is(t_bool io, uint8 data, uint8 devnum)
{
if (io == 0) { /* read status port - works*/
return status;
} else { /* write command port */
command = data;
if (command & RBIT) {
status &= ~TTYDA; /* Set data available status */
data = data;
}
}
return 0;
}
// TTY in/out
uint8 IO_id(t_bool io, uint8 data, uint8 devnum)
{
char val;
if (io == 0) { /* read data port */
if (command & RBIT) { //read from tty rdr
status |= TTYDA; //set TTYDA off
return 'Z';
} else {
status |= TTYDA; //set TTYDA off
val = IO_unit[devnum].buf;
val = (~val) & 0x7f;
return (val);
}
} else { /* write data port - works*/
// IO_unit[devnum].u3 |= TTYBE; //set TTYBE off
val = ~data;
sim_putchar(val & 0x7f);
}
return 0;
}
uint8 IO_oc(t_bool io, uint8 data, uint8 devnum)
{
if (io == 0) { /* read status port */
data = data;
} else { /* write status port */
data = data;
}
return 0;
}
// TTY RDR in/PCH out
uint8 IO_od(t_bool io, uint8 data, uint8 devnum)
{
char val;
if (io == 0) { /* read data port */
status |= PTRDA; //set PTRDA off
val = IO_unit[devnum].buf;
val = (~val) & 0x7f;
return (val);
} else { /* write data port - works*/
data = data;
// IO_unit[devnum].u3 |= TTYBE; //set TTYBE off
// val = ~data;
// sim_putchar(val & 0x7f);
}
return 0;
}
#endif /* IO_NUM > 0 */
/* end of imm8-60.c */

2
Intel-Systems/common/ioc-cont.c
View file

@ -142,7 +142,7 @@ DEVICE ioc_cont_dev = {
t_stat ioc_cont_cfg(uint8 base, uint8 devnum) t_stat ioc_cont_cfg(uint8 base, uint8 devnum)
{ {
sim_printf(" ioc-cont[%d]: at base 0%02XH\n", sim_printf(" ioc-cont[%d]: at base port 0%02XH\n",
devnum, base & 0xFF); devnum, base & 0xFF);
reg_dev(ioc_cont0, base, devnum); reg_dev(ioc_cont0, base, devnum);
reg_dev(ioc_cont1, base + 1, devnum); reg_dev(ioc_cont1, base + 1, devnum);

12
Intel-Systems/common/ipb.c
View file

@ -42,7 +42,7 @@ void put_mword(uint16 addr, uint16 val);
extern t_stat i8080_reset (DEVICE *dptr); /* reset the 8080 emulator */ extern t_stat i8080_reset (DEVICE *dptr); /* reset the 8080 emulator */
extern uint8 multibus_get_mbyte(uint16 addr); extern uint8 multibus_get_mbyte(uint16 addr);
extern void multibus_put_mbyte(uint16 addr, uint8 val); extern void multibus_put_mbyte(uint16 addr, uint8 val);
extern uint8 EPROM_get_mbyte(uint16 addr); extern uint8 EPROM_get_mbyte(uint16 addr, uint8 devnum);
extern uint8 RAM_get_mbyte(uint16 addr); extern uint8 RAM_get_mbyte(uint16 addr);
extern void RAM_put_mbyte(uint16 addr, uint8 val); extern void RAM_put_mbyte(uint16 addr, uint8 val);
extern t_stat i8251_cfg(uint8 base, uint8 devnum); extern t_stat i8251_cfg(uint8 base, uint8 devnum);
@ -60,7 +60,7 @@ extern t_stat ipc_cont_cfg(uint8 base, uint8 devnum);
extern t_stat ioc_cont_reset(DEVICE *dptr); extern t_stat ioc_cont_reset(DEVICE *dptr);
extern t_stat ioc_cont_cfg(uint8 base, uint8 devnum); extern t_stat ioc_cont_cfg(uint8 base, uint8 devnum);
extern uint8 reg_dev(uint8 (*routine)(t_bool, uint8, uint8), uint8, uint8); extern uint8 reg_dev(uint8 (*routine)(t_bool, uint8, uint8), uint8, uint8);
extern t_stat EPROM_cfg(uint16 base, uint16 size); extern t_stat EPROM_cfg(uint16 base, uint16 size, uint8 devnum);
extern t_stat RAM_cfg(uint16 base, uint16 size); extern t_stat RAM_cfg(uint16 base, uint16 size);
extern t_stat multibus_cfg(); extern t_stat multibus_cfg();
@ -97,7 +97,7 @@ t_stat SBC_config(void)
i8259_cfg(I8259_BASE_1, 1); i8259_cfg(I8259_BASE_1, 1);
ipc_cont_cfg(ICONT_BASE, 0); ipc_cont_cfg(ICONT_BASE, 0);
ioc_cont_cfg(DBB_BASE, 0); ioc_cont_cfg(DBB_BASE, 0);
EPROM_cfg(ROM_BASE, ROM_SIZE); EPROM_cfg(ROM_BASE, ROM_SIZE, 0);
RAM_cfg(RAM_BASE, RAM_SIZE); RAM_cfg(RAM_BASE, RAM_SIZE);
return SCPE_OK; return SCPE_OK;
} }
@ -128,13 +128,13 @@ uint8 get_mbyte(uint16 addr)
{ {
SET_XACK(1); /* set no XACK */ SET_XACK(1); /* set no XACK */
if (addr >= 0xF800) { //monitor ROM - always there if (addr >= 0xF800) { //monitor ROM - always there
return EPROM_get_mbyte(addr - 0xF000); //top half of EPROM return EPROM_get_mbyte(addr - 0xF000, 0); //top half of EPROM
} }
if ((addr < 0x1000) && ((ipc_cont_unit.u3 & 0x04) == 0)) { //startup if ((addr < 0x1000) && ((ipc_cont_unit.u3 & 0x04) == 0)) { //startup
return EPROM_get_mbyte(addr); //top half of EPROM for boot return EPROM_get_mbyte(addr, 0); //top half of EPROM for boot
} }
if ((addr >= 0xE800) && (addr < 0xF000) && ((ipc_cont_unit.u3 & 0x10) == 0)) { //diagnostic ROM if ((addr >= 0xE800) && (addr < 0xF000) && ((ipc_cont_unit.u3 & 0x10) == 0)) { //diagnostic ROM
return EPROM_get_mbyte(addr - 0xE800); //bottom half of EPROM return EPROM_get_mbyte(addr - 0xE800, 0); //bottom half of EPROM
} }
if (addr < 0x8000) { //IPB RAM if (addr < 0x8000) { //IPB RAM
return RAM_get_mbyte(addr); return RAM_get_mbyte(addr);

2
Intel-Systems/common/ipc-cont.c
View file

@ -96,7 +96,7 @@ DEVICE ipc_cont_dev = {
t_stat ipc_cont_cfg(uint8 base, uint8 devnum) t_stat ipc_cont_cfg(uint8 base, uint8 devnum)
{ {
sim_printf(" ipc-cont[%d]: at base 0%02XH\n", sim_printf(" ipc-cont[%d]: at port 0%02XH\n",
devnum, base & 0xFF); devnum, base & 0xFF);
reg_dev(ipc_cont, base, devnum); reg_dev(ipc_cont, base, devnum);
return SCPE_OK; return SCPE_OK;

12
Intel-Systems/common/ipc.c
View file

@ -45,7 +45,7 @@ void put_mword(uint16 addr, uint16 val);
extern t_stat i8080_reset (DEVICE *dptr); /* reset the 8080 emulator */ extern t_stat i8080_reset (DEVICE *dptr); /* reset the 8080 emulator */
extern uint8 multibus_get_mbyte(uint16 addr); extern uint8 multibus_get_mbyte(uint16 addr);
extern void multibus_put_mbyte(uint16 addr, uint8 val); extern void multibus_put_mbyte(uint16 addr, uint8 val);
extern uint8 EPROM_get_mbyte(uint16 addr); extern uint8 EPROM_get_mbyte(uint16 addr, uint8 devnum);
extern uint8 RAM_get_mbyte(uint16 addr); extern uint8 RAM_get_mbyte(uint16 addr);
extern void RAM_put_mbyte(uint16 addr, uint8 val); extern void RAM_put_mbyte(uint16 addr, uint8 val);
extern t_stat i8251_cfg(uint8 base, uint8 devnum); extern t_stat i8251_cfg(uint8 base, uint8 devnum);
@ -63,7 +63,7 @@ extern t_stat ipc_cont_cfg(uint8 base, uint8 devnum);
extern t_stat ioc_cont_reset(DEVICE *dptr); extern t_stat ioc_cont_reset(DEVICE *dptr);
extern t_stat ioc_cont_cfg(uint8 base, uint8 devnum); extern t_stat ioc_cont_cfg(uint8 base, uint8 devnum);
extern uint8 reg_dev(uint8 (*routine)(t_bool, uint8, uint8), uint8, uint8); extern uint8 reg_dev(uint8 (*routine)(t_bool, uint8, uint8), uint8, uint8);
extern t_stat EPROM_cfg(uint16 base, uint16 size); extern t_stat EPROM_cfg(uint16 base, uint16 size, uint8 devnum);
extern t_stat RAM_cfg(uint16 base, uint16 size); extern t_stat RAM_cfg(uint16 base, uint16 size);
extern t_stat multibus_cfg(); extern t_stat multibus_cfg();
@ -100,7 +100,7 @@ t_stat SBC_config(void)
i8259_cfg(I8259_BASE_1, 1); i8259_cfg(I8259_BASE_1, 1);
ipc_cont_cfg(ICONT_BASE, 0); ipc_cont_cfg(ICONT_BASE, 0);
ioc_cont_cfg(DBB_BASE, 0); ioc_cont_cfg(DBB_BASE, 0);
EPROM_cfg(ROM_BASE, ROM_SIZE); EPROM_cfg(ROM_BASE, ROM_SIZE, 0);
RAM_cfg(RAM_BASE, RAM_SIZE); RAM_cfg(RAM_BASE, RAM_SIZE);
return SCPE_OK; return SCPE_OK;
} }
@ -131,13 +131,13 @@ uint8 get_mbyte(uint16 addr)
{ {
SET_XACK(1); /* set no XACK */ SET_XACK(1); /* set no XACK */
if (addr >= 0xF800) { //monitor ROM - always there if (addr >= 0xF800) { //monitor ROM - always there
return EPROM_get_mbyte(addr - 0xF000); //top half of EPROM return EPROM_get_mbyte(addr - 0xF000, 0); //top half of EPROM
} }
if ((addr < 0x1000) && ((ipc_cont_unit.u3 & 0x04) == 0)) { //startup if ((addr < 0x1000) && ((ipc_cont_unit.u3 & 0x04) == 0)) { //startup
return EPROM_get_mbyte(addr); //top half of EPROM for boot return EPROM_get_mbyte(addr, 0); //top half of EPROM for boot
} }
if ((addr >= 0xE800) && (addr < 0xF000) && ((ipc_cont_unit.u3 & 0x10) == 0)) { //diagnostic ROM if ((addr >= 0xE800) && (addr < 0xF000) && ((ipc_cont_unit.u3 & 0x10) == 0)) { //diagnostic ROM
return EPROM_get_mbyte(addr - 0xE800); //bottom half of EPROM return EPROM_get_mbyte(addr - 0xE800, 0); //bottom half of EPROM
} }
if (addr < 0x8000) { //IPC RAM if (addr < 0x8000) { //IPC RAM
return RAM_get_mbyte(addr); return RAM_get_mbyte(addr);

4
Intel-Systems/common/isbc064.c
View file

@ -37,6 +37,8 @@
#include "system_defs.h" #include "system_defs.h"
#if defined (SBC064_NUM) && (SBC064_NUM > 0)
#define UNIT_V_MSIZE (UNIT_V_UF+2) /* Memory Size */ #define UNIT_V_MSIZE (UNIT_V_UF+2) /* Memory Size */
#define UNIT_MSIZE (1 << UNIT_V_MSIZE) #define UNIT_MSIZE (1 << UNIT_V_MSIZE)
@ -161,4 +163,6 @@ void isbc064_put_mbyte(uint16 addr, uint8 val)
return; return;
} }
#endif /* SBC064_NUM > 0 */
/* end of isbc064.c */ /* end of isbc064.c */

4
Intel-Systems/common/isbc201.c
View file

@ -160,6 +160,8 @@
#include "system_defs.h" /* system header in system dir */ #include "system_defs.h" /* system header in system dir */
#if defined (SBC201_NUM) && (SBC201_NUM > 0)
#define UNIT_V_WPMODE (UNIT_V_UF) /* Write protect */ #define UNIT_V_WPMODE (UNIT_V_UF) /* Write protect */
#define UNIT_WPMODE (1 << UNIT_V_WPMODE) #define UNIT_WPMODE (1 << UNIT_V_WPMODE)
@ -628,4 +630,6 @@ void isbc201_diskio(void)
} }
} }
#endif /* SBC201_NUM > 0 */
/* end of isbc201.c */ /* end of isbc201.c */

4
Intel-Systems/common/isbc202.c
View file

@ -133,6 +133,8 @@
#include "system_defs.h" /* system header in system dir */ #include "system_defs.h" /* system header in system dir */
#if defined (SBC202_NUM) && (SBC202_NUM > 0)
#define UNIT_V_WPMODE (UNIT_V_UF) /* Write protect */ #define UNIT_V_WPMODE (UNIT_V_UF) /* Write protect */
#define UNIT_WPMODE (1 << UNIT_V_WPMODE) #define UNIT_WPMODE (1 << UNIT_V_WPMODE)
@ -641,4 +643,6 @@ void isbc202_diskio(void)
} }
} }
#endif /* SBC202_NUM > 0 */
/* end of isbc202.c */ /* end of isbc202.c */

4
Intel-Systems/common/isbc206.c
View file

@ -128,6 +128,8 @@
#include "system_defs.h" /* system header in system dir */ #include "system_defs.h" /* system header in system dir */
#if defined (SBC206_NUM) && (SBC206_NUM > 0)
#define UNIT_V_WPMODE (UNIT_V_UF) /* Write protect */ #define UNIT_V_WPMODE (UNIT_V_UF) /* Write protect */
#define UNIT_WPMODE (1 << UNIT_V_WPMODE) #define UNIT_WPMODE (1 << UNIT_V_WPMODE)
@ -597,4 +599,6 @@ void isbc206_diskio(void)
} }
} }
#endif /* SBC206_NUM > 0 */
/* end of isbc206.c */ /* end of isbc206.c */

4
Intel-Systems/common/isbc208.c
View file

@ -397,6 +397,8 @@
#include "system_defs.h" #include "system_defs.h"
#if defined (SBC208_NUM) && (SBC208_NUM > 0)
#define UNIT_V_WPMODE (UNIT_V_UF) /* Write protect */ #define UNIT_V_WPMODE (UNIT_V_UF) /* Write protect */
#define UNIT_WPMODE (1 << UNIT_V_WPMODE) #define UNIT_WPMODE (1 << UNIT_V_WPMODE)
@ -1486,4 +1488,6 @@ uint8 isbc208_r15(t_bool io, uint8 data, uint8 devnum)
} }
} }
#endif /* SBC208_NUM > 0 */
/* end of isbc208.c */ /* end of isbc208.c */

13
Intel-Systems/common/isbc464.c
View file

@ -33,9 +33,11 @@
#include "system_defs.h" #include "system_defs.h"
#if defined (SBC464_NUM) && (SBC464_NUM > 0)
/* prototypes */ /* prototypes */
t_stat isbc064_cfg(uint16 base, uint16 size); t_stat isbc464_cfg(uint16 base, uint16 size);
t_stat isbc464_reset (DEVICE *dptr); t_stat isbc464_reset (DEVICE *dptr);
t_stat isbc464_attach (UNIT *uptr, CONST char *cptr); t_stat isbc464_attach (UNIT *uptr, CONST char *cptr);
uint8 isbc464_get_mbyte(uint16 addr); uint8 isbc464_get_mbyte(uint16 addr);
@ -100,6 +102,13 @@ t_stat isbc464_cfg(uint16 base, uint16 size)
size, base); size, base);
isbc464_unit.capac = size; //set size isbc464_unit.capac = size; //set size
isbc464_unit.u3 = base; //and base isbc464_unit.u3 = base; //and base
isbc464_unit.filebuf = (uint8 *)calloc(size, sizeof(uint8));
if (isbc464_unit.filebuf == NULL) {
sim_printf (" sbc464: Calloc error\n");
return SCPE_MEM;
}
// sim_printf(" sbc464: 0%04XH bytes at base 0%04XH\n",
// isbc464_unit.capac, isbc464_unit.u3);
return SCPE_OK; return SCPE_OK;
} }
@ -138,4 +147,6 @@ uint8 isbc464_get_mbyte(uint16 addr)
return (val & 0xFF); return (val & 0xFF);
} }
#endif /* SBC464_NUM > 0 */
/* end of isbc464.c */ /* end of isbc464.c */

64
Intel-Systems/common/multibus.c
View file

@ -142,13 +142,27 @@ DEVICE multibus_dev = {
t_stat multibus_cfg(void) t_stat multibus_cfg(void)
{ {
sim_printf("Configuring Multibus Devices\n"); sim_printf("Configuring Multibus Devices\n");
if (SBC064_NUM) isbc064_cfg(SBC064_BASE, SBC064_SIZE); #if defined (SBC064_NUM) && (SBC064_NUM > 0)
if (SBC464_NUM) isbc464_cfg(SBC464_BASE, SBC464_SIZE); isbc064_cfg(SBC064_BASE, SBC064_SIZE);
if (SBC201_NUM) isbc201_cfg(SBC201_BASE); #endif
if (SBC202_NUM) isbc202_cfg(SBC202_BASE); #if defined (SBC464_NUM) && (SBC464_NUM > 0)
if (SBC206_NUM) isbc206_cfg(SBC206_BASE); isbc464_cfg(SBC464_BASE, SBC464_SIZE);
if (SBC208_NUM) isbc208_cfg(SBC208_BASE); #endif
if (ZX200A_NUM) zx200a_cfg(ZX200A_BASE); #if defined (SBC201_NUM) && (SBC201_NUM > 0)
isbc201_cfg(SBC201_BASE);
#endif
#if defined (SBC202_NUM) && (SBC202_NUM > 0)
isbc202_cfg(SBC202_BASE);
#endif
#if defined (SBC206_NUM) && (SBC206_NUM > 0)
isbc206_cfg(SBC206_BASE);
#endif
#if defined (SBC208_NUM) && (SBC208_NUM > 0)
isbc208_cfg(SBC208_BASE);
#endif
#if defined (ZX200A_NUM) && (ZX200A_NUM > 0)
zx200a_cfg(ZX200A_BASE);
#endif
return SCPE_OK; return SCPE_OK;
} }
@ -158,34 +172,34 @@ t_stat multibus_reset(DEVICE *dptr)
{ {
if (SBC_reset(NULL) == 0) { if (SBC_reset(NULL) == 0) {
sim_printf(" Multibus: Reset\n"); sim_printf(" Multibus: Reset\n");
if (SBC064_NUM) { //device installed #if defined (SBC064_NUM) && (SBC064_NUM > 0)
isbc064_reset(&isbc064_dev); isbc064_reset(&isbc064_dev);
sim_printf(" Multibus: SBC064 reset\n"); sim_printf(" Multibus: SBC064 reset\n");
} #endif
if (SBC464_NUM) { //unit enabled #if defined (SBC464_NUM) && (SBC464_NUM > 0)
isbc464_reset(&isbc464_dev); isbc464_reset(&isbc464_dev);
sim_printf(" Multibus: SBC464 reset\n"); sim_printf(" Multibus: SBC464 reset\n");
} #endif
if (SBC201_NUM) { //unit enabled #if defined (SBC201_NUM) && (SBC201_NUM > 0)
isbc201_reset(&isbc201_dev); isbc201_reset(&isbc201_dev);
sim_printf(" Multibus: SBC201 reset\n"); sim_printf(" Multibus: SBC201 reset\n");
} #endif
if (SBC202_NUM) { //unit enabled #if defined (SBC202_NUM) && (SBC202_NUM > 0)
isbc202_reset(&isbc202_dev); isbc202_reset(&isbc202_dev);
sim_printf(" Multibus: SBC202 reset\n"); sim_printf(" Multibus: SBC202 reset\n");
} #endif
if (SBC206_NUM) { //unit enabled #if defined (SBC208_NUM) && (SBC208_NUM > 0)
isbc206_reset(&isbc206_dev); isbc206_reset(&isbc206_dev);
sim_printf(" Multibus: SBC206 reset\n"); sim_printf(" Multibus: SBC206 reset\n");
} #endif
if (SBC208_NUM) { //unit enabled #if defined (SBC208_NUM) && (SBC208_NUM > 0)
isbc208_reset(&isbc208_dev); isbc208_reset(&isbc208_dev);
sim_printf(" Multibus: SBC208 reset\n"); sim_printf(" Multibus: SBC208 reset\n");
} #endif
if (ZX200A_NUM) { //unit enabled #if defined (ZX200A_NUM) && (ZX200A_NUM > 0)
zx200a_reset(&zx200a_dev); zx200a_reset(&zx200a_dev);
sim_printf(" Multibus: ZX200A reset\n"); sim_printf(" Multibus: ZX200A reset\n");
} #endif
sim_activate (&multibus_unit, multibus_unit.wait); /* activate unit */ sim_activate (&multibus_unit, multibus_unit.wait); /* activate unit */
return SCPE_OK; return SCPE_OK;
} else { } else {
@ -319,26 +333,30 @@ uint8 reg_dev(uint8 (*routine)(t_bool io, uint8 data, uint8 devnum), uint8 port,
uint8 multibus_get_mbyte(uint16 addr) uint8 multibus_get_mbyte(uint16 addr)
{ {
SET_XACK(0); /* set no XACK */ SET_XACK(0); /* set no XACK */
#if defined (SBC464_NUM) && (SBC464_NUM > 0)
if ((isbc464_dev.flags & DEV_DIS) == 0) { //ROM is enabled if ((isbc464_dev.flags & DEV_DIS) == 0) { //ROM is enabled
if (addr >= isbc464_unit.u3 && addr < (isbc464_unit.u3 + isbc464_unit.capac)) if (addr >= isbc464_unit.u3 && addr < (isbc464_unit.u3 + isbc464_unit.capac))
return(isbc464_get_mbyte(addr)); return(isbc464_get_mbyte(addr));
} }
#endif
#if defined (SBC064_NUM) && (SBC064_NUM > 0)
if ((isbc064_dev.flags & DEV_DIS) == 0) { //RAM is enabled if ((isbc064_dev.flags & DEV_DIS) == 0) { //RAM is enabled
if (addr >= isbc064_unit.u3 && addr < (isbc064_unit.u3 + isbc064_unit.capac)) if (addr >= isbc064_unit.u3 && addr < (isbc064_unit.u3 + isbc064_unit.capac))
return (isbc064_get_mbyte(addr)); return (isbc064_get_mbyte(addr));
} }
#endif
return 0; return 0;
} }
void multibus_put_mbyte(uint16 addr, uint8 val) void multibus_put_mbyte(uint16 addr, uint8 val)
{ {
SET_XACK(0); /* set no XACK */ SET_XACK(0); /* set no XACK */
#if defined (SBC064_NUM) && (SBC064_NUM > 0)
if ((isbc064_dev.flags & DEV_DIS) == 0) { //device is enabled if ((isbc064_dev.flags & DEV_DIS) == 0) { //device is enabled
if ((addr >= SBC064_BASE) && (addr <= (SBC064_BASE + SBC064_SIZE - 1))) if ((addr >= SBC064_BASE) && (addr <= (SBC064_BASE + SBC064_SIZE - 1)))
isbc064_put_mbyte(addr, val); isbc064_put_mbyte(addr, val);
} else {
return;
} }
#endif
} }
/* end of multibus.c */ /* end of multibus.c */

3
Intel-Systems/common/zx200a.c
View file

@ -139,6 +139,7 @@
#include "system_defs.h" /* system header in system dir */ #include "system_defs.h" /* system header in system dir */
#if defined (ZX200A_NUM) && (ZX200A_NUM > 0)
#define UNIT_V_WPMODE (UNIT_V_UF) /* Write protect */ #define UNIT_V_WPMODE (UNIT_V_UF) /* Write protect */
#define UNIT_WPMODE (1 << UNIT_V_WPMODE) #define UNIT_WPMODE (1 << UNIT_V_WPMODE)
@ -789,4 +790,6 @@ void zx200a_diskio(void)
} }
} }
#endif /* ZX200A_NUM > 0 */
/* end of zx-200a.c */ /* end of zx-200a.c */

142
Intel-Systems/ids88/cpu.c Normal file
View file

@ -0,0 +1,142 @@
/* cpu.c: Intel Intellec 8/80 CPU Module simulator
Copyright (c) 2010, William A. Beech
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
WILLIAM A. BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
Except as contained in this notice, the name of William A. Beech shall not be
used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from William A. Beech.
This software was written by Bill Beech, Dec 2010, to allow emulation of Multibus
Computer Systems.
15 July 2020 - Original file.
*/
#include "system_defs.h"
/* function prototypes */
t_stat SBC_config(void);
t_stat SBC_reset (DEVICE *dptr);
uint8 get_mbyte(uint16 addr);
uint16 get_mword(uint16 addr);
void put_mbyte(uint16 addr, uint8 val);
void put_mword(uint16 addr, uint16 val);
// globals
int onetime = 0;
/* external function prototypes */
extern t_stat monitor_reset (void);
extern t_stat monitor_cfg(void);
extern t_stat fp_reset (void);
extern t_stat fp_cfg(void);
extern t_stat i8080_reset (DEVICE *dptr); /* reset the 8080 emulator */
extern uint8 EPROM_get_mbyte(uint16 addr, uint8 devnum);
extern t_stat multibus_cfg(void);
extern uint8 multibus_get_mbyte(uint16 addr);
extern void multibus_put_mbyte(uint16 addr, uint8 val);
extern uint8 reg_dev(uint8 (*routine)(t_bool, uint8, uint8), uint8, uint8);
extern t_stat i3214_cfg(uint8 base, uint8 devnum);
// external globals
extern uint8 monitor_boot;
extern DEVICE i8080_dev;
extern uint8 i3214_mask;
extern uint8 EPROM_enable;
extern uint8 i3214_cnt;
extern uint8 i3214_ram[16];
extern uint8 BUS_OVERRIDE;
t_stat SBC_config(void)
{
sim_printf("Configuring Intellec 8/MOD 80 CPU Card\n Onboard Devices:\n");
i3214_cfg(I3214_BASE, 0);
fp_cfg();
monitor_cfg();
return SCPE_OK;
}
/* SBC reset routine
put here to cause a reset of the entire MDS-800 system */
t_stat SBC_reset (DEVICE *dptr)
{
if (onetime == 0) {
SBC_config();
multibus_cfg();
onetime++;
}
i8080_reset(&i8080_dev);
EPROM_enable = 1;
BUS_OVERRIDE = 0;
fp_reset();
monitor_reset();
return SCPE_OK;
}
// memory operations
/* get a byte from memory - handle RAM, ROM and Multibus memory */
uint8 get_mbyte(uint16 addr)
{
uint8 val;
if (((monitor_boot & 0x04) == 0) && (addr >= ROM_BASE_0) && (addr <= (ROM_BASE_0 + ROM_SIZE_0)))
val = EPROM_get_mbyte(addr, 0);
else if ((addr >= ROM_BASE_1) && (addr <= (ROM_BASE_1 + ROM_SIZE_1)))
val = EPROM_get_mbyte(addr, 1);
else
val = multibus_get_mbyte(addr);
val &= 0xFF;
return val;
}
/* get a word from memory */
uint16 get_mword(uint16 addr)
{
uint16 val;
val = get_mbyte(addr);
val |= (get_mbyte(addr+1) << 8);
return val;
}
/* put a byte to memory - handle RAM, ROM and Multibus memory */
void put_mbyte(uint16 addr, uint8 val)
{
multibus_put_mbyte(addr, val);
}
/* put a word to memory */
void put_mword(uint16 addr, uint16 val)
{
put_mbyte(addr, val & 0xff);
put_mbyte(addr+1, val >> 8);
}
/* end of cpu.c */

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/* front_panel.c: Intel MDS-800 Front Panel Module simulator
Copyright (c) 2010, William A. Beech
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
WILLIAM A. BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
Except as contained in this notice, the name of William A. Beech shall not be
used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from William A. Beech.
This software was written by Bill Beech, Dec 2010, to allow emulation of Multibus
Computer Systems.
5 October 2017 - Original file.
*/
#include "system_defs.h"
/* function prototypes */
t_stat fp_reset (void);
t_stat fp_cfg (void);
/* external function prototypes */
extern t_stat EPROM_reset(DEVICE *dptr, uint8 devnum);
extern t_stat EPROM_cfg(uint16 base, uint16 size, uint8 devnum);
/* external globals */
extern DEVICE EPROM_dev;
t_stat fp_cfg(void)
{
sim_printf("Configuring MDS-800 Front Panel Card\n Onboard Devices:\n");
EPROM_cfg(ROM_BASE_0, ROM_SIZE_0, 0);
return SCPE_OK;
}
/* CPU reset routine
put here to cause a reset of the entire IPC system */
t_stat fp_reset (void)
{
EPROM_reset(&EPROM_dev, 0);
return SCPE_OK;
}
/* end of front_panel.c */

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/* ids-88_sys.c: multibus system interface
Copyright (c) 2010, William A. Beech
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
William A. Beech BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
Except as contained in this notice, the name of William A. Beech shall not be
used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from William A. Beech.
5 October 2017 - Original file.
*/
#include "system_defs.h"
extern DEVICE i8080_dev;
extern REG i8080_reg[];
extern DEVICE EPROM_dev;
extern DEVICE RAM_dev;
/* SCP data structures
sim_name simulator name string
sim_PC pointer to saved PC register descriptor
sim_emax number of words needed for examine
sim_devices array of pointers to simulated devices
sim_stop_messages array of pointers to stop messages
*/
char sim_name[] = "Intel Intellec 8/mod 80";
REG *sim_PC = &i8080_reg[0];
int32 sim_emax = 4;
DEVICE *sim_devices[] = {
&i8080_dev,
&EPROM_dev,
NULL
};
const char *sim_stop_messages[] = {
"Unknown error",
"Unknown I/O Instruction",
"HALT instruction",
"Breakpoint",
"Invalid Opcode",
"Invalid Memory",
"XACK Error"
};
/* end of ids-88_sys.c */

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/* monitor.c: Intel MDS-800 Monitor Module simulator
Copyright (c) 2010, William A. Beech
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
WILLIAM A. BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
Except as contained in this notice, the name of William A. Beech shall not be
used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from William A. Beech.
This software was written by Bill Beech, Dec 2010, to allow emulation of Multibus
Computer Systems.
5 October 2017 - Original file.
*/
#include "system_defs.h"
/* function prototypes */
t_stat monitor_cfg(void);
t_stat monitor_reset (void);
/* external function prototypes */
extern t_stat i8251_reset(DEVICE *dptr);
extern t_stat i8251_cfg(uint8 base, uint8 devnum);
extern t_stat EPROM_reset(DEVICE *dptr);
extern t_stat EPROM_cfg(uint16 base, uint16 size, uint8 devnum);
extern uint8 reg_dev(uint8 (*routine)(t_bool, uint8, uint8), uint8, uint8);
extern uint8 i3214_monitor_do_boot(t_bool io, uint8 data, uint8 devnum);
// external globals
extern uint32 PCX; /* program counter */
extern DEVICE i8251_dev;
extern DEVICE EPROM_dev;
extern uint8 monitor_boot;
// globals
t_stat monitor_cfg(void)
{
sim_printf("Configuring MDS-800 Monitor Card\n Onboard Devices:\n");
EPROM_cfg(ROM_BASE_1, ROM_SIZE_1, 1);
i8251_cfg(I8251_BASE_0, 0);
i8251_cfg(I8251_BASE_1, 1);
return SCPE_OK;
}
/* Monitor reset routine
put here to cause a reset of the entire IPC system */
t_stat monitor_reset (void)
{
monitor_boot = 0x00;
i8251_reset(&i8251_dev);
EPROM_reset(&EPROM_dev);
return SCPE_OK;
}
/* end of monitor.c */

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/* system_defs.h: Intel iSBC simulator definitions
Copyright (c) 2010, William A. Beech
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
William A. Beech BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
Except as contained in this notice, the name of William A. Beech shall not be
used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from William A. Beech.
5 October 2017 - Original file.
*/
#include <stdio.h>
#include <ctype.h>
#include "sim_defs.h" /* simulator defns */
#define SET_XACK(VAL) (xack = VAL)
/* set the base I/O address for the 8251 */
#define I8251_BASE_0 0xF4 //TTY
#define I8251_BASE_1 0xF6 //CRT
#define I8251_NUM 0
// set the base I/O address for the 3214
#define I3214_BASE 0xFC
#define I3214_NUM 0
/* set the base and size for the EPROM0 on the Monitor Module */
#define ROM_BASE 0x3800
#define ROM_SIZE 0x3fFF
#define ROM_DISABLE 1
/* set the base and size for the EPROM1 on the Front Panel Module */
#define ROM_BASE_1 0xF800
#define ROM_SIZE_1 0x07FF
#define ROM_DISABLE_1 0
#define EPROM_NUM 1
/* set the base and size for the RAM on the MDS 210 */
#define RAM_BASE 0x0000
#define RAM_SIZE 0x37FF
//board definitions for the multibus
/* set the base I/O address for the iSBC 201 */
#define SBC201_BASE 0x88
#define SBC201_INT INT_3
#define SBC201_NUM 0
/* set the base I/O address for the iSBC 202 */
#define SBC202_BASE 0x78
#define SBC202_INT INT_3
#define SBC202_NUM 0
/* set the base I/O address for the iSBC 206 */
#define SBC206_BASE 0x68
#define SBC206_INT INT_1
#define SBC206_NUM 0
/* set the base I/O address for the iSBC 208 */
#define SBC208_BASE 0x40
#define SBC208_INT INT_1
#define SBC208_NUM 0
/* set the base for the ZX-200a disk controller */
#define ZX200A_BASE 0x78
#define ZX200A_INT INT_2
#define ZX200A_NUM 0
/* set the base and size for the iSBC 064 */
#define SBC064_BASE 0x0000
#define SBC064_SIZE 0xF7FF
#define SBC064_NUM 0
/* set the base and size for the iSBC 464 ROM */
#define SBC464_BASE 0xA800
#define SBC464_SIZE 0x47FF
#define SBC464_NUM 0
/* set INTR for CPU */
#define INTR INT_2
/* multibus interrupt definitions */
#define INT_0 0x01
#define INT_1 0x02
#define INT_2 0x04
#define INT_3 0x08
#define INT_4 0x10
#define INT_5 0x20
#define INT_6 0x40
#define INT_7 0x80
/* CPU interrupt definitions */
#define INT_R 0x200
#define I75 0x40
#define I65 0x20
#define I55 0x10
/* Memory */
#define MAXMEMSIZE 0xFFFF /* 8080 max memory size */
#define MEMSIZE (i8080_unit.capac) /* 8080 actual memory size */
#define ADDRMASK (MAXMEMSIZE) /* 8080 address mask */
#define MEM_ADDR_OK(x) (((uint16) (x)) <= MEMSIZE)
/* debug definitions */
#define DEBUG_flow 0x0001
#define DEBUG_read 0x0002
#define DEBUG_write 0x0004
#define DEBUG_level1 0x0008
#define DEBUG_level2 0x0010
#define DEBUG_reg 0x0020
#define DEBUG_asm 0x0040
#define DEBUG_xack 0x0080
#define DEBUG_all 0xFFFF
/* Simulator stop codes */
#define STOP_RSRV 1 /* must be 1 */
#define STOP_HALT 2 /* HALT */
#define STOP_IBKPT 3 /* breakpoint */
#define STOP_OPCODE 4 /* Invalid Opcode */
#define STOP_IO 5 /* I/O error */
#define STOP_MEM 6 /* Memory error */
#define STOP_XACK 7 /* XACK error */
/* end of system_defs.h */

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/* cpu.c: Intel MDS-800 CPU Module simulator
Copyright (c) 2010, William A. Beech
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
WILLIAM A. BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
Except as contained in this notice, the name of William A. Beech shall not be
used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from William A. Beech.
This software was written by Bill Beech, Dec 2010, to allow emulation of Multibus
Computer Systems.
5 October 2017 - Original file.
*/
#include "system_defs.h"
/* function prototypes */
t_stat SBC_config(void);
t_stat SBC_reset (DEVICE *dptr);
uint8 get_mbyte(uint16 addr);
uint16 get_mword(uint16 addr);
void put_mbyte(uint16 addr, uint8 val);
void put_mword(uint16 addr, uint16 val);
// globals
int onetime = 0;
/* external function prototypes */
extern t_stat monitor_reset (void);
extern t_stat monitor_cfg(void);
extern t_stat fp_reset (void);
extern t_stat fp_cfg(void);
extern t_stat i8080_reset (DEVICE *dptr); /* reset the 8080 emulator */
extern uint8 EPROM_get_mbyte(uint16 addr, uint8 devnum);
extern t_stat multibus_cfg(void);
extern uint8 multibus_get_mbyte(uint16 addr);
extern void multibus_put_mbyte(uint16 addr, uint8 val);
extern uint8 reg_dev(uint8 (*routine)(t_bool, uint8, uint8), uint8, uint8);
extern t_stat i3214_cfg(uint8 base, uint8 devnum);
// external globals
extern uint8 monitor_boot;
extern DEVICE i8080_dev;
extern uint8 i3214_mask;
extern uint8 EPROM_enable;
extern uint8 i3214_cnt;
extern uint8 i3214_ram[16];
extern uint8 BUS_OVERRIDE;
t_stat SBC_config(void)
{
sim_printf("Configuring MDS-800 CPU Card\n Onboard Devices:\n");
i3214_cfg(I3214_BASE, 0);
fp_cfg();
monitor_cfg();
return SCPE_OK;
}
/* SBC reset routine
put here to cause a reset of the entire MDS-800 system */
t_stat SBC_reset (DEVICE *dptr)
{
if (onetime == 0) {
SBC_config();
multibus_cfg();
onetime++;
}
i8080_reset(&i8080_dev);
EPROM_enable = 1;
BUS_OVERRIDE = 0;
fp_reset();
monitor_reset();
return SCPE_OK;
}
// memory operations
/* get a byte from memory - handle RAM, ROM and Multibus memory */
uint8 get_mbyte(uint16 addr)
{
uint8 val;
if (((monitor_boot & 0x04) == 0) && (addr >= ROM_BASE_0) && (addr <= (ROM_BASE_0 + ROM_SIZE_0)))
val = EPROM_get_mbyte(addr, 0);
else if ((addr >= ROM_BASE_1) && (addr <= (ROM_BASE_1 + ROM_SIZE_1)))
val = EPROM_get_mbyte(addr, 1);
else
val = multibus_get_mbyte(addr);
val &= 0xFF;
return val;
}
/* get a word from memory */
uint16 get_mword(uint16 addr)
{
uint16 val;
val = get_mbyte(addr);
val |= (get_mbyte(addr+1) << 8);
return val;
}
/* put a byte to memory - handle RAM, ROM and Multibus memory */
void put_mbyte(uint16 addr, uint8 val)
{
multibus_put_mbyte(addr, val);
}
/* put a word to memory */
void put_mword(uint16 addr, uint16 val)
{
put_mbyte(addr, val & 0xff);
put_mbyte(addr+1, val >> 8);
}
/* end of cpu.c */

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/* front_panel.c: Intel MDS-800 Front Panel Module simulator
Copyright (c) 2010, William A. Beech
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
WILLIAM A. BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
Except as contained in this notice, the name of William A. Beech shall not be
used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from William A. Beech.
This software was written by Bill Beech, Dec 2010, to allow emulation of Multibus
Computer Systems.
5 October 2017 - Original file.
*/
#include "system_defs.h"
/* function prototypes */
t_stat fp_reset (void);
t_stat fp_cfg (void);
/* external function prototypes */
extern t_stat EPROM_reset(DEVICE *dptr, uint8 devnum);
extern t_stat EPROM_cfg(uint16 base, uint16 size, uint8 devnum);
/* external globals */
extern DEVICE EPROM_dev;
t_stat fp_cfg(void)
{
sim_printf("Configuring MDS-800 Front Panel Card\n Onboard Devices:\n");
EPROM_cfg(ROM_BASE_0, ROM_SIZE_0, 0);
return SCPE_OK;
}
/* CPU reset routine
put here to cause a reset of the entire IPC system */
t_stat fp_reset (void)
{
EPROM_reset(&EPROM_dev, 0);
return SCPE_OK;
}
/* end of front_panel.c */

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/* cpu.c: Intel MDS-800 CPU Module simulator
Copyright (c) 2010, William A. Beech
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
WILLIAM A. BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
Except as contained in this notice, the name of William A. Beech shall not be
used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from William A. Beech.
This software was written by Bill Beech, Dec 2010, to allow emulation of Multibus
Computer Systems.
5 October 2017 - Original file.
*/
#include "system_defs.h"
/* function prototypes */
t_stat SBC_config(void);
t_stat SBC_reset (DEVICE *dptr);
uint8 get_mbyte(uint16 addr);
uint16 get_mword(uint16 addr);
void put_mbyte(uint16 addr, uint8 val);
void put_mword(uint16 addr, uint16 val);
// globals
int onetime = 0;
/* external function prototypes */
extern t_stat i8080_reset (DEVICE *dptr); /* reset the 8080 emulator */
extern uint8 EPROM_get_mbyte(uint16 addr, uint8 devnum);
extern uint8 RAM_get_mbyte (uint16 addr);
extern void RAM_put_mbyte (uint16 addr, uint8 val);
extern t_stat multibus_cfg(void);
extern uint8 reg_dev(uint8 (*routine)(t_bool, uint8, uint8), uint8, uint8);
extern t_stat EPROM_cfg (uint16 base, uint16 size, uint8 devnum);
extern t_stat RAM_cfg(uint16 base, uint16 size);
extern t_stat IO_cfg(uint8 base, uint8 devnum);
// external globals
extern DEVICE i8080_dev;
t_stat SBC_config(void)
{
sim_printf("Configuring IDS-8/MOD 80 CPU Card\n Onboard Devices:\n");
EPROM_cfg(ROM_BASE, ROM_SIZE, 0);
RAM_cfg(RAM_BASE, RAM_SIZE);
IO_cfg(IO_BASE_0, 0);
// IO_cfg(IO_BASE_1, 1);
put_mbyte(0, 0xc3);
put_mbyte(1, 0x00);
put_mbyte(2, 0x38);
return SCPE_OK;
}
/* SBC reset routine
put here to cause a reset of the entire MDS-800 system */
t_stat SBC_reset (DEVICE *dptr)
{
if (onetime == 0) {
SBC_config();
onetime++;
}
i8080_reset(&i8080_dev);
return SCPE_OK;
}
// memory operations
/* get a byte from memory - handle RAM, ROM and Multibus memory */
uint8 get_mbyte(uint16 addr)
{
uint8 val;
if ((addr >= ROM_BASE) && (addr <= (ROM_BASE + ROM_SIZE)))
val = EPROM_get_mbyte(addr, 0);
else if ((addr >= RAM_BASE) && (addr <= (RAM_BASE + RAM_SIZE)))
val = RAM_get_mbyte(addr);
else
val = 0xff;
val &= 0xFF;
return val;
}
/* get a word from memory */
uint16 get_mword(uint16 addr)
{
uint16 val;
val = get_mbyte(addr);
val |= (get_mbyte(addr+1) << 8);
return val;
}
/* put a byte to memory - handle RAM, ROM and Multibus memory */
void put_mbyte(uint16 addr, uint8 val)
{
if ((addr >= RAM_BASE) && (addr <= (RAM_BASE + RAM_SIZE)))
RAM_put_mbyte(addr, val);
}
/* put a word to memory */
void put_mword(uint16 addr, uint16 val)
{
put_mbyte(addr, val & 0xff);
put_mbyte(addr+1, val >> 8);
}
/* end of cpu.c */

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/* mds-800_sys.c: multibus system interface
Copyright (c) 2010, William A. Beech
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
William A. Beech BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
Except as contained in this notice, the name of William A. Beech shall not be
used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from William A. Beech.
5 October 2017 - Original file.
*/
#include "system_defs.h"
extern DEVICE i8080_dev;
extern REG i8080_reg[];
extern DEVICE EPROM_dev;
extern DEVICE RAM_dev;
extern DEVICE IO_dev;
extern DEVICE PTR_dev;
extern DEVICE multibus_dev;
/* SCP data structures
sim_name simulator name string
sim_PC pointer to saved PC register descriptor
sim_emax number of words needed for examine
sim_devices array of pointers to simulated devices
sim_stop_messages array of pointers to stop messages
*/
char sim_name[] = "Intel Intellec 8/MOD 80";
REG *sim_PC = &i8080_reg[0];
int32 sim_emax = 4;
DEVICE *sim_devices[] = {
&i8080_dev,
&EPROM_dev,
&RAM_dev,
&IO_dev,
&PTR_dev,
&multibus_dev,
NULL
};
const char *sim_stop_messages[] = {
"Unknown error",
"Unknown I/O Instruction",
"HALT instruction",
"Breakpoint",
"Invalid Opcode",
"Invalid Memory",
"XACK Error"
};
/* end of mds-800_sys.c */

254
Intel-Systems/ids880/sdkmultibus.c Normal file
View file

@ -0,0 +1,254 @@
/* sdkmultibus.c: Multibus I simulator
Copyright (c) 2010, William A. Beech
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
WILLIAM A. BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
Except as contained in this notice, the name of William A. Beech shall not be
used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from William A. Beech.
MODIFICATIONS:
?? ??? 10 - Original file.
24 Apr 15 -- Modified to use simh_debug
NOTES:
*/
#include "system_defs.h"
/* function prototypes */
t_stat multibus_cfg(void);
t_stat multibus_svc(UNIT *uptr);
t_stat multibus_reset(DEVICE *dptr);
void set_irq(int32 int_num);
void clr_irq(int32 int_num);
uint8 nulldev(t_bool io, uint8 port, uint8 devnum);
uint8 reg_dev(uint8 (*routine)(t_bool, uint8, uint8), uint8, uint8);
t_stat multibus_reset (DEVICE *dptr);
/* external function prototypes */
extern t_stat SBC_reset(DEVICE *dptr); /* reset the iSBC80/10 emulator */
extern void set_cpuint(int32 int_num);
/* local globals */
int32 mbirq = 0; /* set no multibus interrupts */
/* external globals */
extern uint8 xack; /* XACK signal */
extern int32 int_req; /* i8080 INT signal */
extern uint16 PCX;
/* multibus Standard SIMH Device Data Structures */
UNIT multibus_unit = {
UDATA (&multibus_svc, 0, 0), 20
};
REG multibus_reg[] = {
{ HRDATA (MBIRQ, mbirq, 32) },
{ HRDATA (XACK, xack, 8) },
{ NULL }
};
DEBTAB multibus_debug[] = {
{ "ALL", DEBUG_all },
{ "FLOW", DEBUG_flow },
{ "READ", DEBUG_read },
{ "WRITE", DEBUG_write },
{ "LEV1", DEBUG_level1 },
{ "LEV2", DEBUG_level2 },
{ NULL }
};
DEVICE multibus_dev = {
"MBIRQ", //name
&multibus_unit, //units
multibus_reg, //registers
NULL, //modifiers
1, //numunits
16, //aradix
16, //awidth
1, //aincr
16, //dradix
8, //dwidth
NULL, //examine
NULL, //deposit
&multibus_reset, //reset
NULL, //boot
NULL, //attach
NULL, //detach
NULL, //ctxt
DEV_DEBUG, //flags
0, //dctrl
multibus_debug, //debflags
NULL, //msize
NULL //lname
};
/* Service routines to handle simulator functions */
// multibus_cfg
t_stat multibus_cfg(void)
{
sim_printf("Configuring Multibus Devices\n");
return SCPE_OK;
}
/* Reset routine */
t_stat multibus_reset(DEVICE *dptr)
{
if (SBC_reset(NULL) == 0) {
sim_printf(" Multibus: Reset\n");
sim_activate (&multibus_unit, multibus_unit.wait); /* activate unit */
return SCPE_OK;
} else {
sim_printf(" Multibus: SBC not selected\n");
return SCPE_OK;
}
}
/* service routine - actually does the simulated interrupts */
t_stat multibus_svc(UNIT *uptr)
{
switch (mbirq) {
case INT_2:
set_cpuint(INT_R);
break;
default:
break;
}
sim_activate (&multibus_unit, multibus_unit.wait); /* continue poll */
return SCPE_OK;
}
void set_irq(int32 int_num)
{
mbirq |= int_num;
}
void clr_irq(int32 int_num)
{
mbirq &= ~int_num;
}
/* This is the I/O configuration table. There are 256 possible
device addresses, if a device is plugged to a port it's routine
address is here, 'nulldev' means no device has been registered.
*/
struct idev {
uint8 (*routine)(t_bool io, uint8 data, uint8 devnum);
uint8 port;
uint8 devnum;
};
struct idev dev_table[256] = {
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 000H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 004H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 008H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 00CH */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 010H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 014H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 018H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 01CH */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 020H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 024H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 028H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 02CH */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 030H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 034H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 038H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 03CH */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 040H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 044H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 048H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 04CH */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 050H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 054H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 058H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 05CH */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 060H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 064H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 068H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 06CH */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 070H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 074H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 078H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 07CH */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 080H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 084H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 088H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 08CH */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 090H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 094H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 098H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 09CH */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0A0H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0A4H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0A8H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0A0H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0B0H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0B4H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0B8H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0B0H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0C0H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0C4H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0C8H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0CCH */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0D0H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0D4H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0D8H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0DCH */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0E0H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0E4H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0E8H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0ECH */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0F0H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0F4H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0F8H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev} /* 0FCH */
};
uint8 nulldev(t_bool io, uint8 data, uint8 devnum)
{
SET_XACK(0); /* set no XACK */
return 0xff; /* multibus has active high pullups and inversion */
}
uint8 reg_dev(uint8 (*routine)(t_bool io, uint8 data, uint8 devnum), uint8 port, uint8 devnum)
{
if (dev_table[port].routine != &nulldev) { /* port already assigned */
if (dev_table[port].routine != routine)
sim_printf(" I/O Port %02X is already assigned\n", port);
} else {
dev_table[port].routine = routine;
dev_table[port].devnum = devnum;
}
return 0;
}
/* end of multibus.c */

141
Intel-Systems/ids880/system_defs.h Normal file
View file

@ -0,0 +1,141 @@
/* system_defs.h: Intel iSBC simulator definitions
Copyright (c) 2010, William A. Beech
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
William A. Beech BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
Except as contained in this notice, the name of William A. Beech shall not be
used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from William A. Beech.
5 October 2017 - Original file.
*/
#include <stdio.h>
#include <ctype.h>
#include "sim_defs.h" /* simulator defns */
#define SET_XACK(VAL) (xack = VAL)
/* set the base I/O address for the imm8-60 */
#define IO_BASE_0 0x00 //TTY
#define IO_NUM 1
#define PTR_NUM 1
// set the base I/O address for the 3214
#define I3214_BASE 0xFC
#define I3214_NUM 0
/* set the base and size for the EPROM0 on the Monitor Module */
#define ROM_BASE 0x3800
#define ROM_SIZE 0x07ff
#define ROM_DISABLE 0
#define EPROM_NUM 1
/* set the base and size for the RAM on the MDS 225 */
#define RAM_BASE 0x0000
#define RAM_SIZE 0x37ff
#define RAM_DISABLE 0
//board definitions for the multibus
/* set the base I/O address for the iSBC 201 */
#define SBC201_BASE 0x88
#define SBC201_INT INT_3
#define SBC201_NUM 0
/* set the base I/O address for the iSBC 202 */
#define SBC202_BASE 0x78
#define SBC202_INT INT_3
#define SBC202_NUM 0
/* set the base I/O address for the iSBC 206 */
#define SBC206_BASE 0x68
#define SBC206_INT INT_1
#define SBC206_NUM 0
/* set the base I/O address for the iSBC 208 */
#define SBC208_BASE 0x40
#define SBC208_INT INT_1
#define SBC208_NUM 0
/* set the base for the ZX-200a disk controller */
#define ZX200A_BASE 0x78
#define ZX200A_INT INT_2
#define ZX200A_NUM 0
/* set the base and size for the iSBC 064 */
#define SBC064_BASE 0x0000
#define SBC064_SIZE 0xF7FF
#define SBC064_NUM 0
/* set the base and size for the iSBC 464 ROM */
#define SBC464_BASE 0xA800
#define SBC464_SIZE 0x47FF
#define SBC464_NUM 0
/* set INTR for CPU */
#define INTR INT_2
/* multibus interrupt definitions */
#define INT_0 0x01
#define INT_1 0x02
#define INT_2 0x04
#define INT_3 0x08
#define INT_4 0x10
#define INT_5 0x20
#define INT_6 0x40
#define INT_7 0x80
/* CPU interrupt definitions */
#define INT_R 0x200
#define I75 0x40
#define I65 0x20
#define I55 0x10
/* Memory */
#define MAXMEMSIZE 0xFFFF /* 8080 max memory size */
#define MEMSIZE (i8080_unit.capac) /* 8080 actual memory size */
#define ADDRMASK (MAXMEMSIZE) /* 8080 address mask */
#define MEM_ADDR_OK(x) (((uint16) (x)) <= MEMSIZE)
/* debug definitions */
#define DEBUG_flow 0x0001
#define DEBUG_read 0x0002
#define DEBUG_write 0x0004
#define DEBUG_level1 0x0008
#define DEBUG_level2 0x0010
#define DEBUG_reg 0x0020
#define DEBUG_asm 0x0040
#define DEBUG_xack 0x0080
#define DEBUG_all 0xFFFF
/* Simulator stop codes */
#define STOP_RSRV 1 /* must be 1 */
#define STOP_HALT 2 /* HALT */
#define STOP_IBKPT 3 /* breakpoint */
#define STOP_OPCODE 4 /* Invalid Opcode */
#define STOP_IO 5 /* I/O error */
#define STOP_MEM 6 /* Memory error */
#define STOP_XACK 7 /* XACK error */
/* end of system_defs.h */

2
Intel-Systems/imds-210/system_defs.h
View file

@ -33,6 +33,8 @@
#define IPC 0 #define IPC 0
#define SET_XACK(VAL) (xack = VAL) #define SET_XACK(VAL) (xack = VAL)
#define I3214_NUM 0
/* set the base for the DBB ports */ /* set the base for the DBB ports */
#define DBB_BASE 0xC0 #define DBB_BASE 0xC0

6
Intel-Systems/imds-220/imds-220_sys.c
View file

@ -67,9 +67,15 @@ DEVICE *sim_devices[] = {
&i8259_dev, &i8259_dev,
&ipc_cont_dev, &ipc_cont_dev,
&multibus_dev, &multibus_dev,
#if defined (SBC201_NUM) && (SBC201_NUM > 0)
&isbc201_dev, &isbc201_dev,
#endif
#if defined (SBC202_NUM) && (SBC202_NUM > 0)
&isbc202_dev, &isbc202_dev,
#endif
#if defined (ZX200A_NUM) && (ZX200A_NUM > 0)
&zx200a_dev, &zx200a_dev,
#endif
NULL NULL
}; };

4
Intel-Systems/imds-220/system_defs.h
View file

@ -32,6 +32,8 @@
#define SET_XACK(VAL) (xack = VAL) #define SET_XACK(VAL) (xack = VAL)
#define I3214_NUM 0
/* set the base for the DBB ports */ /* set the base for the DBB ports */
#define DBB_BASE 0xC0 #define DBB_BASE 0xC0
@ -76,7 +78,7 @@
/* set the base I/O address for the iSBC 202 */ /* set the base I/O address for the iSBC 202 */
#define SBC202_BASE 0x78 #define SBC202_BASE 0x78
#define SBC202_INT INT_2 #define SBC202_INT INT_2
#define SBC202_NUM 0 #define SBC202_NUM 1
/* set the base I/O address for the iSBC 206 */ /* set the base I/O address for the iSBC 206 */
#define SBC206_BASE 0x68 #define SBC206_BASE 0x68

8
Intel-Systems/imds-225/imds-225_sys.c
View file

@ -68,10 +68,18 @@ DEVICE *sim_devices[] = {
&i8259_dev, &i8259_dev,
&ipc_cont_dev, &ipc_cont_dev,
&multibus_dev, &multibus_dev,
#if defined (SBC201_NUM) && (SBC20_NUM > 0)
&isbc201_dev, &isbc201_dev,
#endif
#if defined (SBC202_NUM) && (SBC202_NUM > 0)
&isbc202_dev, &isbc202_dev,
#endif
#if defined (SBC206_NUM) && (SBC206_NUM > 0)
&isbc206_dev, &isbc206_dev,
#endif
#if defined (ZX200A_NUM) && (ZX200A_NUM > 0)
&zx200a_dev, &zx200a_dev,
#endif
NULL NULL
}; };

2
Intel-Systems/imds-225/system_defs.h
View file

@ -32,6 +32,8 @@
#define SET_XACK(VAL) (xack = VAL) #define SET_XACK(VAL) (xack = VAL)
#define I3214_NUM 0
/* set the base for the DBB ports */ /* set the base for the DBB ports */
#define DBB_BASE 0xC0 #define DBB_BASE 0xC0

8
Intel-Systems/imds-230/imds-230_sys.c
View file

@ -68,10 +68,18 @@ DEVICE *sim_devices[] = {
&i8259_dev, &i8259_dev,
&ipc_cont_dev, &ipc_cont_dev,
&multibus_dev, &multibus_dev,
#if defined (SBC201_NUM) && (SBC201_NUM > 0)
&isbc201_dev, &isbc201_dev,
#endif
#if defined (SBC202_NUM) && (SBC202_NUM > 0)
&isbc202_dev, &isbc202_dev,
#endif
#if defined (ZX200A_NUM) && (ZX200A_NUM > 0)
&zx200a_dev, &zx200a_dev,
#endif
#if defined (SBC064_NUM) && (SBC064_NUM > 0)
&isbc064_dev, &isbc064_dev,
#endif
NULL NULL
}; };

2
Intel-Systems/imds-230/system_defs.h
View file

@ -32,6 +32,8 @@
#define SET_XACK(VAL) (xack = VAL) #define SET_XACK(VAL) (xack = VAL)
#define I3214_NUM 0
/* set the base for the DBB ports */ /* set the base for the DBB ports */
#define DBB_BASE 0xC0 #define DBB_BASE 0xC0

14
Intel-Systems/imds-800/cpu.c
View file

@ -51,8 +51,7 @@ extern t_stat monitor_cfg(void);
extern t_stat fp_reset (void); extern t_stat fp_reset (void);
extern t_stat fp_cfg(void); extern t_stat fp_cfg(void);
extern t_stat i8080_reset (DEVICE *dptr); /* reset the 8080 emulator */ extern t_stat i8080_reset (DEVICE *dptr); /* reset the 8080 emulator */
extern uint8 EPROM_get_mbyte(uint16 addr); extern uint8 EPROM_get_mbyte(uint16 addr, uint8 devnum);
extern uint8 EPROM1_get_mbyte(uint16 addr);
extern t_stat multibus_cfg(void); extern t_stat multibus_cfg(void);
extern uint8 multibus_get_mbyte(uint16 addr); extern uint8 multibus_get_mbyte(uint16 addr);
extern void multibus_put_mbyte(uint16 addr, uint8 val); extern void multibus_put_mbyte(uint16 addr, uint8 val);
@ -104,11 +103,12 @@ uint8 get_mbyte(uint16 addr)
{ {
uint8 val; uint8 val;
if (((monitor_boot & 0x04) == 0) && (addr >= ROM0_BASE) && (addr <= (ROM0_BASE + ROM0_SIZE))) if (((monitor_boot & 0x04) == 0) && (addr >= ROM_BASE_0) && (addr <= (ROM_BASE_0 + ROM_SIZE_0)))
val = EPROM_get_mbyte(addr); val = EPROM_get_mbyte(addr, 0);
else if (ROM1_SIZE && (addr >= ROM1_BASE) && (addr <= (ROM1_BASE + ROM1_SIZE))) else if ((addr >= ROM_BASE_1) && (addr <= (ROM_BASE_1 + ROM_SIZE_1)))
val = EPROM1_get_mbyte(addr); val = EPROM_get_mbyte(addr, 1);
else val = multibus_get_mbyte(addr); else
val = multibus_get_mbyte(addr);
val &= 0xFF; val &= 0xFF;
return val; return val;
} }

8
Intel-Systems/imds-800/front_panel.c
View file

@ -39,16 +39,16 @@ t_stat fp_cfg(void);
/* external function prototypes */ /* external function prototypes */
extern t_stat EPROM_reset(DEVICE *dptr); extern t_stat EPROM_reset(DEVICE *dptr);
extern t_stat EPROM_cfg(uint16 base, uint16 size); extern t_stat EPROM_cfg(uint16 base, uint16 size, uint8 devnum);
/* external globals */ /* external globals */
extern DEVICE EPROM_dev; extern DEVICE EPROM_dev[];
t_stat fp_cfg(void) t_stat fp_cfg(void)
{ {
sim_printf("Configuring MDS-800 Front Panel Card\n Onboard Devices:\n"); sim_printf("Configuring MDS-800 Front Panel Card\n Onboard Devices:\n");
EPROM_cfg(ROM0_BASE, ROM0_SIZE); EPROM_cfg(ROM_BASE_0, ROM_SIZE_0, 0);
return SCPE_OK; return SCPE_OK;
} }
@ -57,7 +57,7 @@ t_stat fp_cfg(void)
t_stat fp_reset (void) t_stat fp_reset (void)
{ {
EPROM_reset(&EPROM_dev); EPROM_reset(EPROM_dev);
return SCPE_OK; return SCPE_OK;
} }

10
Intel-Systems/imds-800/imds-800_sys.c
View file

@ -33,7 +33,6 @@ extern REG i8080_reg[];
extern DEVICE i8251_dev; extern DEVICE i8251_dev;
extern DEVICE i3214_dev; extern DEVICE i3214_dev;
extern DEVICE EPROM_dev; extern DEVICE EPROM_dev;
extern DEVICE EPROM1_dev;
extern DEVICE RAM_dev; extern DEVICE RAM_dev;
extern DEVICE multibus_dev; extern DEVICE multibus_dev;
extern DEVICE isbc201_dev; extern DEVICE isbc201_dev;
@ -59,14 +58,21 @@ int32 sim_emax = 4;
DEVICE *sim_devices[] = { DEVICE *sim_devices[] = {
&i8080_dev, &i8080_dev,
&EPROM_dev, &EPROM_dev,
&EPROM1_dev,
&i8251_dev, &i8251_dev,
&i3214_dev, &i3214_dev,
&multibus_dev, &multibus_dev,
#if defined (SBC064_NUM) && (SBC064_NUM > 0)
&isbc064_dev, &isbc064_dev,
#endif
#if defined (SBC201_NUM) && (SBC201_NUM > 0)
&isbc201_dev, &isbc201_dev,
#endif
#if defined (SBC202_NUM) && (SBC202_NUM > 0)
&isbc202_dev, &isbc202_dev,
#endif
#if defined (ZX200A_NUM) && (ZX200A_NUM > 0)
&zx200a_dev, &zx200a_dev,
#endif
NULL NULL
}; };

10
Intel-Systems/imds-800/monitor.c
View file

@ -40,8 +40,8 @@ t_stat monitor_reset (void);
extern t_stat i8251_reset(DEVICE *dptr); extern t_stat i8251_reset(DEVICE *dptr);
extern t_stat i8251_cfg(uint8 base, uint8 devnum); extern t_stat i8251_cfg(uint8 base, uint8 devnum);
extern t_stat EPROM1_reset(DEVICE *dptr); extern t_stat EPROM_reset(DEVICE *dptr);
extern t_stat EPROM1_cfg(uint16 base, uint16 size); extern t_stat EPROM_cfg(uint16 base, uint16 size, uint8 devnum);
extern uint8 reg_dev(uint8 (*routine)(t_bool, uint8, uint8), uint8, uint8); extern uint8 reg_dev(uint8 (*routine)(t_bool, uint8, uint8), uint8, uint8);
extern uint8 i3214_monitor_do_boot(t_bool io, uint8 data, uint8 devnum); extern uint8 i3214_monitor_do_boot(t_bool io, uint8 data, uint8 devnum);
@ -49,7 +49,7 @@ extern uint8 i3214_monitor_do_boot(t_bool io, uint8 data, uint8 devnum);
extern uint32 PCX; /* program counter */ extern uint32 PCX; /* program counter */
extern DEVICE i8251_dev; extern DEVICE i8251_dev;
extern DEVICE EPROM1_dev; extern DEVICE EPROM_dev;
extern uint8 monitor_boot; extern uint8 monitor_boot;
// globals // globals
@ -57,7 +57,7 @@ extern uint8 monitor_boot;
t_stat monitor_cfg(void) t_stat monitor_cfg(void)
{ {
sim_printf("Configuring MDS-800 Monitor Card\n Onboard Devices:\n"); sim_printf("Configuring MDS-800 Monitor Card\n Onboard Devices:\n");
EPROM1_cfg(ROM1_BASE, ROM1_SIZE); EPROM_cfg(ROM_BASE_1, ROM_SIZE_1, 1);
i8251_cfg(I8251_BASE_0, 0); i8251_cfg(I8251_BASE_0, 0);
i8251_cfg(I8251_BASE_1, 1); i8251_cfg(I8251_BASE_1, 1);
return SCPE_OK; return SCPE_OK;
@ -70,7 +70,7 @@ t_stat monitor_reset (void)
{ {
monitor_boot = 0x00; monitor_boot = 0x00;
i8251_reset(&i8251_dev); i8251_reset(&i8251_dev);
EPROM1_reset(&EPROM1_dev); EPROM_reset(&EPROM_dev);
return SCPE_OK; return SCPE_OK;
} }

15
Intel-Systems/imds-800/system_defs.h
View file

@ -42,20 +42,21 @@
#define I3214_NUM 1 #define I3214_NUM 1
/* set the base and size for the EPROM0 on the Monitor Module */ /* set the base and size for the EPROM0 on the Monitor Module */
#define ROM0_BASE 0x0000 #define ROM_BASE_0 0x0000
#define ROM0_SIZE 0x00FF #define ROM_SIZE_0 0x00FF
#define ROM0_DISABLE 1 #define ROM_DISABLE_0 1
/* set the base and size for the EPROM1 on the Front Panel Module */ /* set the base and size for the EPROM1 on the Front Panel Module */
#define ROM1_BASE 0xF800 #define ROM_BASE_1 0xF800
#define ROM1_SIZE 0x07FF #define ROM_SIZE_1 0x07FF
#define ROM1_DISABLE 0 #define ROM_DISABLE_1 0
#define EPROM_NUM 2
//board definitions for the multibus //board definitions for the multibus
/* set the base I/O address for the iSBC 201 */ /* set the base I/O address for the iSBC 201 */
#define SBC201_BASE 0x88 #define SBC201_BASE 0x88
#define SBC201_INT INT_3 #define SBC201_INT INT_3
#define SBC201_NUM 1 #define SBC201_NUM 0
/* set the base I/O address for the iSBC 202 */ /* set the base I/O address for the iSBC 202 */
#define SBC202_BASE 0x78 #define SBC202_BASE 0x78

11
Intel-Systems/imds-810/cpu.c
View file

@ -50,8 +50,7 @@ extern t_stat monitor_reset (void);
extern t_stat fp_reset (void); extern t_stat fp_reset (void);
extern t_stat i3214_reset (DEVICE *dptr); extern t_stat i3214_reset (DEVICE *dptr);
extern t_stat i8080_reset (DEVICE *dptr); /* reset the 8080 emulator */ extern t_stat i8080_reset (DEVICE *dptr); /* reset the 8080 emulator */
extern uint8 EPROM_get_mbyte(uint16 addr); extern uint8 EPROM_get_mbyte(uint16 addr, uint8 devnum);
extern uint8 EPROM1_get_mbyte(uint16 addr);
extern uint8 multibus_get_mbyte(uint16 addr); extern uint8 multibus_get_mbyte(uint16 addr);
extern void multibus_put_mbyte(uint16 addr, uint8 val); extern void multibus_put_mbyte(uint16 addr, uint8 val);
extern uint8 reg_dev(uint8 (*routine)(t_bool, uint8, uint8), uint8, uint8); extern uint8 reg_dev(uint8 (*routine)(t_bool, uint8, uint8), uint8, uint8);
@ -104,10 +103,10 @@ uint8 get_mbyte(uint16 addr)
{ {
uint8 val; uint8 val;
if (EPROM_enable && (addr >= ROM0_BASE && addr <= ROM0_BASE + ROM0_SIZE)) if (EPROM_enable && (addr >= ROM_BASE_0 && addr <= ROM_BASE_0 + ROM_SIZE_0))
val = EPROM_get_mbyte(addr); val = EPROM_get_mbyte(addr, 0);
else if (ROM1_SIZE && addr >= ROM1_BASE && addr <= ROM1_BASE + ROM1_SIZE) else if (ROM_SIZE_1 && addr >= ROM_BASE_1 && addr <= ROM_BASE_1 + ROM_SIZE_1)
val = EPROM1_get_mbyte(addr); val = EPROM_get_mbyte(addr, 1);
else val = multibus_get_mbyte(addr); else val = multibus_get_mbyte(addr);
val &= 0xFF; val &= 0xFF;
return(val); return(val);

4
Intel-Systems/imds-810/front_panel.c
View file

@ -40,7 +40,7 @@ t_stat fp_cfg(void);
extern uint8 EPROM_get_mbyte(uint16 addr); extern uint8 EPROM_get_mbyte(uint16 addr);
extern t_stat EPROM_reset(DEVICE *dptr); extern t_stat EPROM_reset(DEVICE *dptr);
extern t_stat EPROM_cfg(uint16 base, uint16 size); extern t_stat EPROM_cfg(uint16 base, uint16 size, uint8 devnum);
// external globals // external globals
@ -52,7 +52,7 @@ extern uint16 PCX; /* program counter */
t_stat fp_cfg(void) t_stat fp_cfg(void)
{ {
sim_printf("Configuring MDS-800 Front Panel Module\n Onboard Devices:\n"); sim_printf("Configuring MDS-800 Front Panel Module\n Onboard Devices:\n");
EPROM_cfg(ROM0_BASE, ROM0_SIZE); EPROM_cfg(ROM_BASE_0, ROM_SIZE_0, 0);
return SCPE_OK; return SCPE_OK;
} }

14
Intel-Systems/imds-810/imds-810_sys.c
View file

@ -33,13 +33,13 @@ extern REG i8080_reg[];
extern DEVICE i8251_dev; extern DEVICE i8251_dev;
extern DEVICE EPROM_dev; extern DEVICE EPROM_dev;
extern DEVICE i3214_dev; extern DEVICE i3214_dev;
extern DEVICE EPROM1_dev;
extern DEVICE RAM_dev; extern DEVICE RAM_dev;
extern DEVICE multibus_dev; extern DEVICE multibus_dev;
extern DEVICE isbc201_dev; extern DEVICE isbc201_dev;
extern DEVICE isbc202_dev; extern DEVICE isbc202_dev;
extern DEVICE zx200a_dev; extern DEVICE zx200a_dev;
extern DEVICE isbc064_dev; extern DEVICE isbc064_dev;
extern DEVICE isbc464_dev;
/* SCP data structures /* SCP data structures
@ -59,14 +59,24 @@ int32 sim_emax = 4;
DEVICE *sim_devices[] = { DEVICE *sim_devices[] = {
&i8080_dev, &i8080_dev,
&EPROM_dev, &EPROM_dev,
&EPROM1_dev,
&i8251_dev, &i8251_dev,
&i3214_dev, &i3214_dev,
&multibus_dev, &multibus_dev,
#if defined (SBC064_NUM) && (SBC064_NUM > 0)
&isbc064_dev, &isbc064_dev,
#endif
#if defined (SBC201_NUM) && (SBC201_NUM > 0)
&isbc201_dev, &isbc201_dev,
#endif
#if defined (SBC202_NUM) && (SBC202_NUM > 0)
&isbc202_dev, &isbc202_dev,
#endif
#if defined (ZX200A_NUM) && (ZX200A_NUM > 0)
&zx200a_dev, &zx200a_dev,
#endif
#if defined (SBC464_NUM) && (SBC464_NUM > 0)
&isbc464_dev,
#endif
NULL NULL
}; };

20
Intel-Systems/imds-810/monitor.c
View file

@ -38,21 +38,19 @@ t_stat monitor_reset (void);
/* external function prototypes */ /* external function prototypes */
extern uint8 monitor_do_boot(t_bool io, uint8 data);
extern uint8 EPROM1_get_mbyte(uint16 addr);
extern t_stat i3214_reset(DEVICE *dptr);
extern t_stat EPROM1_reset(DEVICE *dptr);
extern uint8 reg_dev(uint8 (*routine)(t_bool, uint8, uint8), uint8, uint8);
extern t_stat EPROM1_cfg(uint16 base, uint16 size);
extern t_stat i8251_reset(DEVICE *dptr); extern t_stat i8251_reset(DEVICE *dptr);
extern t_stat i8251_cfg(uint8 base, uint8 size); extern t_stat i8251_cfg(uint8 base, uint8 devnum);
extern t_stat EPROM_reset(DEVICE *dptr);
extern t_stat EPROM_cfg(uint16 base, uint16 size, uint8 devnum);
extern uint8 reg_dev(uint8 (*routine)(t_bool, uint8, uint8), uint8, uint8);
extern uint8 i3214_monitor_do_boot(t_bool io, uint8 data, uint8 devnum);
// external globals // external globals
extern uint16 PCX; /* program counter */ extern uint16 PCX; /* program counter */
extern UNIT EPROM1_unit; //8316 PROM extern UNIT EPROM_unit[]; //8316 PROM
extern DEVICE i8251_dev; extern DEVICE i8251_dev;
extern DEVICE EPROM1_dev; extern DEVICE EPROM_dev;
// globals // globals
@ -63,7 +61,7 @@ extern uint8 monitor_boot;
t_stat monitor_cfg(void) t_stat monitor_cfg(void)
{ {
sim_printf("Initializing MDS-800 Monitor Module\n Onboard Devices:\n"); sim_printf("Initializing MDS-800 Monitor Module\n Onboard Devices:\n");
EPROM1_cfg(ROM1_BASE, ROM1_SIZE); EPROM_cfg(ROM_BASE_1, ROM_SIZE_1, 1);
i8251_cfg(I8251_BASE_0, 0); i8251_cfg(I8251_BASE_0, 0);
i8251_cfg(I8251_BASE_1, 1); i8251_cfg(I8251_BASE_1, 1);
return SCPE_OK; return SCPE_OK;
@ -76,7 +74,7 @@ t_stat monitor_reset (void)
{ {
monitor_boot = 0x00; monitor_boot = 0x00;
i8251_reset(&i8251_dev); i8251_reset(&i8251_dev);
EPROM1_reset(&EPROM1_dev); EPROM_reset(&EPROM_dev);
return SCPE_OK; return SCPE_OK;
} }

17
Intel-Systems/imds-810/system_defs.h
View file

@ -42,14 +42,15 @@
#define I3214_NUM 1 #define I3214_NUM 1
/* set the base and size for the EPROM0 on the Monitor Module */ /* set the base and size for the EPROM0 on the Monitor Module */
#define ROM0_BASE 0x0000 #define ROM_BASE_0 0x0000
#define ROM0_SIZE 0x00FF #define ROM_SIZE_0 0x00FF
#define ROM0_DISABLE 1 #define ROM_DISABLE_0 1
#define EPROM_NUM 2
/* set the base and size for the EPROM1 on the Front Panel Module */ /* set the base and size for the EPROM1 on the Front Panel Module */
#define ROM1_BASE 0xF800 #define ROM_BASE_1 0xF800
#define ROM1_SIZE 0x07FF #define ROM_SIZE_1 0x07FF
#define ROM1_DISABLE 1 #define ROM_DISABLE_1 1
//board definitions for the multibus //board definitions for the multibus
/* set the base I/O address for the iSBC 201 */ /* set the base I/O address for the iSBC 201 */
@ -79,8 +80,8 @@
/* set the base and size for the iSBC 064 */ /* set the base and size for the iSBC 064 */
#define SBC064_BASE 0x0000 #define SBC064_BASE 0x0000
#define SBC064_SIZE 0xFFFF #define SBC064_SIZE 0x7FFF
#define SBC064_NUM 0 #define SBC064_NUM 1
/* set the base and size for the iSBC 464 ROM */ /* set the base and size for the iSBC 464 ROM */
#define SBC464_BASE 0xA800 #define SBC464_BASE 0xA800

149
Intel-Systems/isdk80/isdk80.c Normal file
View file

@ -0,0 +1,149 @@
/* iSDK80.c: Intel iSDK 80 Processor simulator
Copyright (c) 2020, William A. Beech
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
WILLIAM A. BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
Except as contained in this notice, the name of William A. Beech shall not be
used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from William A. Beech.
MODIFICATIONS:
08 Jun 20 - Original file.
*/
#include "system_defs.h"
/* function prototypes */
t_stat SBC_config(void);
t_stat SBC_reset (DEVICE *dptr);
uint8 get_mbyte(uint16 addr);
uint16 get_mword(uint16 addr);
void put_mbyte(uint16 addr, uint8 val);
void put_mword(uint16 addr, uint16 val);
/* external globals */
extern uint8 i8255_C[4]; //port C byte I/O
extern uint16 PCX; /* External view of PC */
extern DEVICE i8080_dev;
extern DEVICE i8251_dev;
extern DEVICE i8255_dev;
extern DEVICE EPROM_dev;
extern UNIT EPROM_unit[];
extern DEVICE RAM_dev;
extern UNIT RAM_unit;
/* external function prototypes */
extern uint8 EPROM_get_mbyte(uint16 addr, uint8 devnum);
extern uint8 RAM_get_mbyte(uint16 addr);
extern void RAM_put_mbyte(uint16 addr, uint8 val);
extern t_stat i8080_reset (DEVICE *dptr); /* reset the 8080 emulator */
extern t_stat i8251_reset (DEVICE *dptr);
extern t_stat i8255_reset (DEVICE *dptr);
extern t_stat EPROM_reset (DEVICE *dptr);
extern t_stat RAM_reset (DEVICE *dptr);
extern uint8 reg_dev(uint8 (*routine)(t_bool, uint8, uint8), uint8, uint8);
extern t_stat i8251_cfg(uint8 base, uint8 devnum);
extern t_stat i8255_cfg(uint8 base, uint8 devnum);
extern t_stat RAM_cfg(uint16 base, uint16 size);
extern t_stat EPROM_cfg(uint16 base, uint16 size, uint8 devnum);
extern t_stat multibus_cfg();
/* globals */
int onetime = 0;
t_stat SBC_config(void)
{
sim_printf("Configuring iSDK-80 SBC\n Onboard Devices:\n");
i8251_cfg(I8251_BASE, 0);
i8255_cfg(I8255_BASE_0, 0);
i8255_cfg(I8255_BASE_1, 1);
EPROM_cfg(ROM_BASE, ROM_SIZE, 0);
RAM_cfg(RAM_BASE, RAM_SIZE);
return SCPE_OK;
}
/* SBC reset routine */
t_stat SBC_reset (DEVICE *dptr)
{
if (onetime == 0) {
SBC_config();
multibus_cfg();
onetime++;
}
i8080_reset(&i8080_dev);
i8251_reset(&i8251_dev);
i8255_reset(&i8255_dev);
return SCPE_OK;
}
/* get a byte from memory - handle RAM, ROM, I/O, and Multibus memory */
uint8 get_mbyte(uint16 addr)
{
/* if local EPROM handle it */
if ((addr >= EPROM_unit->u3) && ((uint16)addr <= (EPROM_unit->u3 + EPROM_unit->capac))) {
return EPROM_get_mbyte(addr, 0);
} /* if local RAM handle it */
if ((addr >= RAM_unit.u3) && ((uint16)addr <= (RAM_unit.u3 + RAM_unit.capac))) {
return RAM_get_mbyte(addr);
}
return 0xff;
}
/* get a word from memory */
uint16 get_mword(uint16 addr)
{
uint16 val;
val = get_mbyte(addr);
val |= (get_mbyte(addr+1) << 8);
return val;
}
/* put a byte to memory - handle RAM, ROM, I/O, and Multibus memory */
void put_mbyte(uint16 addr, uint8 val)
{
/* if local EPROM handle it */
if ((addr >= EPROM_unit->u3) && ((uint16)addr <= (EPROM_unit->u3 + EPROM_unit->capac))) {
sim_printf("Write to R/O memory address %04X from PC=%04X - ignored\n", addr, PCX);
return;
} /* if local RAM handle it */
if ((addr >= RAM_unit.u3) && ((uint16)addr <= (RAM_unit.u3 + RAM_unit.capac))) {
RAM_put_mbyte(addr, val);
return;
}
}
/* put a word to memory */
void put_mword(uint16 addr, uint16 val)
{
put_mbyte(addr, val & 0xff);
put_mbyte(addr+1, val >> 8);
}
/* end of iSDK80.c */

73
Intel-Systems/isdk80/isdk80_sys.c Normal file
View file

@ -0,0 +1,73 @@
/* isdk80_sys.c: SDK 80 system interface
Copyright (c) 2020, William A. Beech
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
William A. Beech BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
Except as contained in this notice, the name of William A. Beech shall not be
used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from William A. Beech.
08 Jun 20 - Original file.
*/
#include "system_defs.h"
extern DEVICE i8080_dev;
extern REG i8080_reg[];
extern DEVICE i8251_dev;
extern DEVICE i8255_dev;
extern DEVICE EPROM_dev;
extern DEVICE RAM_dev;
extern DEVICE multibus_dev;
/* SCP data structures
sim_name simulator name string
sim_PC pointer to saved PC register descriptor
sim_emax number of words needed for examine
sim_devices array of pointers to simulated devices
sim_stop_messages array of pointers to stop messages
*/
char sim_name[] = "Intel SDK-80";
REG *sim_PC = &i8080_reg[0];
int32 sim_emax = 4;
DEVICE *sim_devices[] = {
&i8080_dev,
&EPROM_dev,
&RAM_dev,
&i8251_dev,
&i8255_dev,
&multibus_dev,
NULL
};
const char *sim_stop_messages[] = {
"Unknown error",
"Unknown I/O Instruction",
"HALT instruction",
"Breakpoint",
"Invalid Opcode",
"Invalid Memory",
"XACK Error"
};

295
Intel-Systems/isdk80/sdkmultibus.c Normal file
View file

@ -0,0 +1,295 @@
/* sdkmultibus.c: Multibus I simulator
Copyright (c) 2010, William A. Beech
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
WILLIAM A. BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
Except as contained in this notice, the name of William A. Beech shall not be
used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from William A. Beech.
MODIFICATIONS:
?? ??? 10 - Original file.
24 Apr 15 -- Modified to use simh_debug
NOTES:
*/
#include "system_defs.h"
/* function prototypes */
t_stat multibus_cfg(void);
t_stat multibus_svc(UNIT *uptr);
t_stat multibus_reset(DEVICE *dptr);
void set_irq(int32 int_num);
void clr_irq(int32 int_num);
uint8 nulldev(t_bool io, uint8 port, uint8 devnum);
uint8 reg_dev(uint8 (*routine)(t_bool, uint8, uint8), uint8, uint8);
t_stat multibus_reset (DEVICE *dptr);
uint8 multibus_get_mbyte(uint16 addr);
void multibus_put_mbyte(uint16 addr, uint8 val);
/* external function prototypes */
extern t_stat SBC_reset(DEVICE *dptr); /* reset the iSBC80/10 emulator */
extern uint8 isbc064_get_mbyte(uint16 addr);
extern void isbc064_put_mbyte(uint16 addr, uint8 val);
extern uint8 isbc464_get_mbyte(uint16 addr);
extern void set_cpuint(int32 int_num);
extern t_stat isbc064_reset (DEVICE *);
extern t_stat isbc464_reset (DEVICE *);
extern t_stat isbc201_reset (DEVICE *);
extern t_stat isbc202_reset (DEVICE *);
extern t_stat isbc206_reset (DEVICE *);
extern t_stat isbc208_reset (DEVICE *);
extern t_stat zx200a_reset(DEVICE *);
extern t_stat isbc064_cfg(uint16 base, uint16 size);
extern t_stat isbc464_cfg(uint16 base, uint16 size);
extern t_stat isbc201_cfg(uint8 base);
extern t_stat isbc202_cfg(uint8 base);
extern t_stat isbc206_cfg(uint8 base);
extern t_stat isbc208_cfg(uint8 base);
extern t_stat zx200a_cfg(uint8 base);
/* local globals */
int32 mbirq = 0; /* set no multibus interrupts */
/* external globals */
extern uint8 xack; /* XACK signal */
extern int32 int_req; /* i8080 INT signal */
extern uint16 PCX;
extern DEVICE isbc064_dev;
extern DEVICE isbc464_dev;
extern DEVICE isbc201_dev;
extern DEVICE isbc202_dev;
extern DEVICE isbc206_dev;
extern DEVICE isbc208_dev;
extern DEVICE zx200a_dev;
extern UNIT isbc064_unit;
extern UNIT isbc464_unit;
/* multibus Standard SIMH Device Data Structures */
UNIT multibus_unit = {
UDATA (&multibus_svc, 0, 0), 20
};
REG multibus_reg[] = {
{ HRDATA (MBIRQ, mbirq, 32) },
{ HRDATA (XACK, xack, 8) },
{ NULL }
};
DEBTAB multibus_debug[] = {
{ "ALL", DEBUG_all },
{ "FLOW", DEBUG_flow },
{ "READ", DEBUG_read },
{ "WRITE", DEBUG_write },
{ "LEV1", DEBUG_level1 },
{ "LEV2", DEBUG_level2 },
{ NULL }
};
DEVICE multibus_dev = {
"MBIRQ", //name
&multibus_unit, //units
multibus_reg, //registers
NULL, //modifiers
1, //numunits
16, //aradix
16, //awidth
1, //aincr
16, //dradix
8, //dwidth
NULL, //examine
NULL, //deposit
&multibus_reset, //reset
NULL, //boot
NULL, //attach
NULL, //detach
NULL, //ctxt
DEV_DEBUG, //flags
0, //dctrl
multibus_debug, //debflags
NULL, //msize
NULL //lname
};
/* Service routines to handle simulator functions */
// multibus_cfg
t_stat multibus_cfg(void)
{
sim_printf("Configuring Multibus Devices\n");
return SCPE_OK;
}
/* Reset routine */
t_stat multibus_reset(DEVICE *dptr)
{
if (SBC_reset(NULL) == 0) {
sim_printf(" Multibus: Reset\n");
sim_activate (&multibus_unit, multibus_unit.wait); /* activate unit */
return SCPE_OK;
} else {
sim_printf(" Multibus: SBC not selected\n");
return SCPE_OK;
}
}
/* service routine - actually does the simulated interrupts */
t_stat multibus_svc(UNIT *uptr)
{
switch (mbirq) {
case INT_2:
set_cpuint(INT_R);
break;
default:
break;
}
sim_activate (&multibus_unit, multibus_unit.wait); /* continue poll */
return SCPE_OK;
}
void set_irq(int32 int_num)
{
mbirq |= int_num;
}
void clr_irq(int32 int_num)
{
mbirq &= ~int_num;
}
/* This is the I/O configuration table. There are 256 possible
device addresses, if a device is plugged to a port it's routine
address is here, 'nulldev' means no device has been registered.
*/
struct idev {
uint8 (*routine)(t_bool io, uint8 data, uint8 devnum);
uint8 port;
uint8 devnum;
};
struct idev dev_table[256] = {
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 000H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 004H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 008H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 00CH */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 010H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 014H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 018H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 01CH */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 020H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 024H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 028H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 02CH */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 030H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 034H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 038H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 03CH */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 040H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 044H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 048H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 04CH */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 050H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 054H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 058H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 05CH */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 060H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 064H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 068H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 06CH */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 070H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 074H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 078H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 07CH */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 080H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 084H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 088H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 08CH */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 090H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 094H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 098H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 09CH */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0A0H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0A4H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0A8H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0A0H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0B0H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0B4H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0B8H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0B0H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0C0H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0C4H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0C8H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0CCH */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0D0H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0D4H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0D8H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0DCH */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0E0H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0E4H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0E8H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0ECH */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0F0H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0F4H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0F8H */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev} /* 0FCH */
};
uint8 nulldev(t_bool io, uint8 data, uint8 devnum)
{
SET_XACK(0); /* set no XACK */
return 0xff; /* multibus has active high pullups and inversion */
}
uint8 reg_dev(uint8 (*routine)(t_bool io, uint8 data, uint8 devnum), uint8 port, uint8 devnum)
{
if (dev_table[port].routine != &nulldev) { /* port already assigned */
if (dev_table[port].routine != routine)
sim_printf(" I/O Port %02X is already assigned\n", port);
} else {
dev_table[port].routine = routine;
dev_table[port].devnum = devnum;
}
return 0;
}
/* get a byte from memory */
uint8 multibus_get_mbyte(uint16 addr)
{
SET_XACK(0); /* set no XACK */
return 0xff;
}
void multibus_put_mbyte(uint16 addr, uint8 val)
{
SET_XACK(0); /* set no XACK */
}
/* end of multibus.c */

139
Intel-Systems/isdk80/system_defs.h Normal file
View file

@ -0,0 +1,139 @@
/* system_defs.h: Intel iSBC simulator definitions
Copyright (c) 2020, William A. Beech
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
William A. Beech BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
Except as contained in this notice, the name of William A. Beech shall not be
used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from William A. Beech.
?? ??? 10 - Original file.
*/
#include <stdio.h>
#include <ctype.h>
#include "sim_defs.h" /* simulator defns */
#define SET_XACK(VAL) (xack = VAL)
/* set the base I/O address for the 8255 */
#define I8255_BASE_0 0xF4
#define I8255_BASE_1 0xEC
#define I8255_NUM 2
/* set the base I/O address for the 8251 */
#define I8251_BASE 0xFA
#define I8251_NUM 1
/* set the base and size for the EPROM on the MDS 220 */
#define ROM_BASE 0x0000
#define ROM_SIZE 0x0FFF
#define ROM_DISABLE 0
#define EPROM_NUM 1
/* set the base and size for the RAM on the MDS 220 */
#define RAM_BASE 0x1000
#define RAM_SIZE 0x13FF
//board definitions for the multibus
/* set the base I/O address for the iSBC 201 */
#define SBC201_BASE 0x88
#define SBC201_INT INT_3
#define SBC201_NUM 0
/* set the base I/O address for the iSBC 202 */
#define SBC202_BASE 0x78
#define SBC202_INT INT_3
#define SBC202_NUM 0
/* set the base I/O address for the iSBC 206 */
#define SBC206_BASE 0x68
#define SBC206_INT INT_1
#define SBC206_NUM 0
/* set the base I/O address for the iSBC 208 */
#define SBC208_BASE 0x40
#define SBC208_INT INT_2
#define SBC208_NUM 0
/* set the base for the ZX-200a disk controller */
#define ZX200A_BASE 0x78
#define ZX200A_INT INT_2
#define ZX200A_NUM 0
/* set the base and size for the iSBC 064 */
#define SBC064_BASE 0x0000
#define SBC064_SIZE 0xFFFF
#define SBC064_NUM 0
/* set the base and size for the iSBC 464 ROM */
#define SBC464_BASE 0xA800
#define SBC464_SIZE 0x47FF
#define SBC464_NUM 0
/* set INTR for CPU */
#define INTR INT_2
/* multibus interrupt definitions */
#define INT_0 0x01
#define INT_1 0x02
#define INT_2 0x04
#define INT_3 0x08
#define INT_4 0x10
#define INT_5 0x20
#define INT_6 0x40
#define INT_7 0x80
/* CPU interrupts definitions */
#define INT_R 0x200
#define I75 0x40
#define I65 0x20
#define I55 0x10
/* Memory */
#define MAXMEMSIZE 0x0FFFF /* 8080 max memory size */
#define MEMSIZE (i8080_unit.capac) /* 8080 actual memory size */
#define ADDRMASK (MAXMEMSIZE) /* 8080 address mask */
#define MEM_ADDR_OK(x) (((uint16) (x)) <= MEMSIZE)
/* debug definitions */
#define DEBUG_flow 0x0001
#define DEBUG_read 0x0002
#define DEBUG_write 0x0004
#define DEBUG_level1 0x0008
#define DEBUG_level2 0x0010
#define DEBUG_reg 0x0020
#define DEBUG_asm 0x0040
#define DEBUG_xack 0x0080
#define DEBUG_all 0xFFFF
/* Simulator stop codes */
#define STOP_RSRV 1 /* must be 1 */
#define STOP_HALT 2 /* HALT */
#define STOP_IBKPT 3 /* breakpoint */
#define STOP_OPCODE 4 /* Invalid Opcode */
#define STOP_IO 5 /* I/O error */
#define STOP_MEM 6 /* Memory error */
#define STOP_XACK 7 /* XACK error */

14
Intel-Systems/isys8010/isbc8010.c
View file

@ -53,7 +53,7 @@ extern DEVICE i8080_dev;
extern DEVICE i8251_dev; extern DEVICE i8251_dev;
extern DEVICE i8255_dev; extern DEVICE i8255_dev;
extern DEVICE EPROM_dev; extern DEVICE EPROM_dev;
extern UNIT EPROM_unit; extern UNIT EPROM_unit[];
extern DEVICE RAM_dev; extern DEVICE RAM_dev;
extern UNIT RAM_unit; extern UNIT RAM_unit;
@ -61,7 +61,7 @@ extern UNIT RAM_unit;
extern uint8 multibus_get_mbyte(uint16 addr); extern uint8 multibus_get_mbyte(uint16 addr);
extern void multibus_put_mbyte(uint16 addr, uint8 val); extern void multibus_put_mbyte(uint16 addr, uint8 val);
extern uint8 EPROM_get_mbyte(uint16 addr); extern uint8 EPROM_get_mbyte(uint16 addr, uint8 devnum);
extern uint8 RAM_get_mbyte(uint16 addr); extern uint8 RAM_get_mbyte(uint16 addr);
extern void RAM_put_mbyte(uint16 addr, uint8 val); extern void RAM_put_mbyte(uint16 addr, uint8 val);
extern t_stat i8080_reset (DEVICE *dptr); /* reset the 8080 emulator */ extern t_stat i8080_reset (DEVICE *dptr); /* reset the 8080 emulator */
@ -73,7 +73,7 @@ extern uint8 reg_dev(uint8 (*routine)(t_bool, uint8, uint8), uint8, uint8);
extern t_stat i8251_cfg(uint8 base, uint8 devnum); extern t_stat i8251_cfg(uint8 base, uint8 devnum);
extern t_stat i8255_cfg(uint8 base, uint8 devnum); extern t_stat i8255_cfg(uint8 base, uint8 devnum);
extern t_stat RAM_cfg(uint16 base, uint16 size); extern t_stat RAM_cfg(uint16 base, uint16 size);
extern t_stat EPROM_cfg(uint16 base, uint16 size); extern t_stat EPROM_cfg(uint16 base, uint16 size, uint8 devnum);
extern t_stat multibus_cfg(); extern t_stat multibus_cfg();
/* globals */ /* globals */
@ -86,7 +86,7 @@ t_stat SBC_config(void)
i8251_cfg(I8251_BASE, 0); i8251_cfg(I8251_BASE, 0);
i8255_cfg(I8255_BASE_0, 0); i8255_cfg(I8255_BASE_0, 0);
i8255_cfg(I8255_BASE_1, 1); i8255_cfg(I8255_BASE_1, 1);
EPROM_cfg(ROM_BASE, ROM_SIZE); EPROM_cfg(ROM_BASE, ROM_SIZE, 0);
RAM_cfg(RAM_BASE, RAM_SIZE); RAM_cfg(RAM_BASE, RAM_SIZE);
return SCPE_OK; return SCPE_OK;
} }
@ -112,8 +112,8 @@ uint8 get_mbyte(uint16 addr)
{ {
/* if local EPROM handle it */ /* if local EPROM handle it */
if ((ROM_DISABLE && (i8255_C[0] & 0x80)) || (ROM_DISABLE == 0)) { /* EPROM enabled */ if ((ROM_DISABLE && (i8255_C[0] & 0x80)) || (ROM_DISABLE == 0)) { /* EPROM enabled */
if ((addr >= EPROM_unit.u3) && ((uint16)addr <= (EPROM_unit.u3 + EPROM_unit.capac))) { if ((addr >= EPROM_unit->u3) && ((uint16)addr <= (EPROM_unit->u3 + EPROM_unit->capac))) {
return EPROM_get_mbyte(addr); return EPROM_get_mbyte(addr, 0);
} }
} /* if local RAM handle it */ } /* if local RAM handle it */
if ((RAM_DISABLE && (i8255_C[0] & 0x20)) || (RAM_DISABLE == 0)) { /* RAM enabled */ if ((RAM_DISABLE && (i8255_C[0] & 0x20)) || (RAM_DISABLE == 0)) { /* RAM enabled */
@ -141,7 +141,7 @@ void put_mbyte(uint16 addr, uint8 val)
{ {
/* if local EPROM handle it */ /* if local EPROM handle it */
if ((ROM_DISABLE && (i8255_C[0] & 0x80)) || (ROM_DISABLE == 0)) { /* EPROM enabled */ if ((ROM_DISABLE && (i8255_C[0] & 0x80)) || (ROM_DISABLE == 0)) { /* EPROM enabled */
if ((addr >= EPROM_unit.u3) && ((uint16)addr <= (EPROM_unit.u3 + EPROM_unit.capac))) { if ((addr >= EPROM_unit->u3) && ((uint16)addr <= (EPROM_unit->u3 + EPROM_unit->capac))) {
sim_printf("Write to R/O memory address %04X from PC=%04X - ignored\n", addr, PCX); sim_printf("Write to R/O memory address %04X from PC=%04X - ignored\n", addr, PCX);
return; return;
} }

14
Intel-Systems/isys8010/isys8010_sys.c
View file

@ -66,13 +66,27 @@ DEVICE *sim_devices[] = {
&i8251_dev, &i8251_dev,
&i8255_dev, &i8255_dev,
&multibus_dev, &multibus_dev,
#if defined (SBC064_NUM) && (SBC064_NUM > 0)
&isbc064_dev, &isbc064_dev,
#endif
#if defined (SBC464_NUM) && (SBC464_NUM > 0)
&isbc464_dev, &isbc464_dev,
#endif
#if defined (SBC201_NUM) && (SBC201_NUM > 0)
&isbc201_dev, &isbc201_dev,
#endif
#if defined (SBC202_NUM) && (SBC202_NUM > 0)
&isbc202_dev, &isbc202_dev,
#endif
#if defined (SBC206_NUM) && (SBC206_NUM > 0)
&isbc206_dev, &isbc206_dev,
#endif
#if defined (SBC208_NUM) && (SBC208_NUM > 0)
&isbc208_dev, &isbc208_dev,
#endif
#if defined (ZX200A_NUM) && (ZX200A_NUM > 0)
&zx200a_dev, &zx200a_dev,
#endif
NULL NULL
}; };

14
Intel-Systems/isys8020/isbc8020.c
View file

@ -71,8 +71,8 @@ extern t_stat i8259_reset (DEVICE *dptr);
extern uint8 i8259a(t_bool io, uint8 data, uint8 devnum); extern uint8 i8259a(t_bool io, uint8 data, uint8 devnum);
extern uint8 i8259b(t_bool io, uint8 data, uint8 devnum); extern uint8 i8259b(t_bool io, uint8 data, uint8 devnum);
extern DEVICE i8259_dev; extern DEVICE i8259_dev;
extern uint8 EPROM_get_mbyte(uint16 addr); extern uint8 EPROM_get_mbyte(uint16 addr, uint8 devnum);
extern UNIT EPROM_unit; extern UNIT EPROM_unit[];
extern t_stat EPROM_reset (DEVICE *dptr); extern t_stat EPROM_reset (DEVICE *dptr);
extern uint8 RAM_get_mbyte(uint16 addr); extern uint8 RAM_get_mbyte(uint16 addr);
extern void RAM_put_mbyte(uint16 addr, uint8 val); extern void RAM_put_mbyte(uint16 addr, uint8 val);
@ -83,7 +83,7 @@ extern t_stat i8253_cfg(uint8 base, uint8 devnum);
extern t_stat i8255_cfg(uint8 base, uint8 devnum); extern t_stat i8255_cfg(uint8 base, uint8 devnum);
extern t_stat i8259_cfg(uint8 base, uint8 devnum); extern t_stat i8259_cfg(uint8 base, uint8 devnum);
extern t_stat RAM_cfg(uint16 base, uint16 size); extern t_stat RAM_cfg(uint16 base, uint16 size);
extern t_stat EPROM_cfg(uint16 base, uint16 size); extern t_stat EPROM_cfg(uint16 base, uint16 size, uint8 devnum);
extern t_stat multibus_cfg(); extern t_stat multibus_cfg();
extern uint8 reg_dev(uint8 (*routine)(t_bool, uint8, uint8), uint8, uint8); extern uint8 reg_dev(uint8 (*routine)(t_bool, uint8, uint8), uint8, uint8);
@ -99,7 +99,7 @@ t_stat SBC_config(void)
i8255_cfg(I8255_BASE_0, 0); i8255_cfg(I8255_BASE_0, 0);
i8255_cfg(I8255_BASE_1, 1); i8255_cfg(I8255_BASE_1, 1);
i8259_cfg(I8259_BASE, 0); i8259_cfg(I8259_BASE, 0);
EPROM_cfg(ROM_BASE, ROM_SIZE); EPROM_cfg(ROM_BASE, ROM_SIZE, 0);
RAM_cfg(RAM_BASE, RAM_SIZE); RAM_cfg(RAM_BASE, RAM_SIZE);
return SCPE_OK; return SCPE_OK;
} }
@ -129,8 +129,8 @@ uint8 get_mbyte(uint16 addr)
{ {
/* if local EPROM handle it */ /* if local EPROM handle it */
if ((ROM_DISABLE && (i8255_C[0] & 0x20)) || (ROM_DISABLE == 0)) { /* EPROM enabled */ if ((ROM_DISABLE && (i8255_C[0] & 0x20)) || (ROM_DISABLE == 0)) { /* EPROM enabled */
if ((addr >= EPROM_unit.u3) && ((uint16)addr <= (EPROM_unit.u3 + EPROM_unit.capac))) if ((addr >= EPROM_unit->u3) && ((uint16)addr <= (EPROM_unit->u3 + EPROM_unit->capac)))
return EPROM_get_mbyte(addr); return EPROM_get_mbyte(addr, 0);
} /* if local RAM handle it */ } /* if local RAM handle it */
if ((RAM_DISABLE && (i8255_C[0] & 0x20)) || (RAM_DISABLE == 0)) { /* RAM enabled */ if ((RAM_DISABLE && (i8255_C[0] & 0x20)) || (RAM_DISABLE == 0)) { /* RAM enabled */
if ((addr >= RAM_unit.u3) && ((uint16)addr <= (RAM_unit.u3 + RAM_unit.capac))) if ((addr >= RAM_unit.u3) && ((uint16)addr <= (RAM_unit.u3 + RAM_unit.capac)))
@ -156,7 +156,7 @@ void put_mbyte(uint16 addr, uint8 val)
{ {
/* if local EPROM handle it */ /* if local EPROM handle it */
if ((ROM_DISABLE && (i8255_C[0] & 0x20)) || (ROM_DISABLE == 0)) { /* EPROM enabled */ if ((ROM_DISABLE && (i8255_C[0] & 0x20)) || (ROM_DISABLE == 0)) { /* EPROM enabled */
if ((addr >= EPROM_unit.u3) && ((uint16)addr <= (EPROM_unit.u3 + EPROM_unit.capac))) { if ((addr >= EPROM_unit->u3) && ((uint16)addr <= (EPROM_unit->u3 + EPROM_unit->capac))) {
sim_printf("Write to R/O memory address %04X from PC=%04X - ignored\n", addr, PCX); sim_printf("Write to R/O memory address %04X from PC=%04X - ignored\n", addr, PCX);
return; return;
} }

8
Intel-Systems/isys8020/isys8020_sys.c
View file

@ -67,10 +67,18 @@ DEVICE *sim_devices[] = {
&i8253_dev, &i8253_dev,
&i8255_dev, &i8255_dev,
&multibus_dev, &multibus_dev,
#if defined (SBC064_NUM) && (SBC064_NUM > 0)
&isbc064_dev, &isbc064_dev,
#endif
#if defined (SBC201_NUM) && (SBC201_NUM > 0)
&isbc201_dev, &isbc201_dev,
#endif
#if defined (SBC202_NUM) && (SBC202_NUM > 0)
&isbc202_dev, &isbc202_dev,
#endif
#if defined (SBC208_NUM) && (SBC208_NUM > 0)
&isbc208_dev, &isbc208_dev,
#endif
NULL NULL
}; };

14
Intel-Systems/isys8024/isbc8024.c
View file

@ -75,8 +75,8 @@ extern t_stat i8259_reset (DEVICE *dptr);
extern uint8 i8259a(t_bool io, uint8 data, uint8 devnum); extern uint8 i8259a(t_bool io, uint8 data, uint8 devnum);
extern uint8 i8259b(t_bool io, uint8 data, uint8 devnum); extern uint8 i8259b(t_bool io, uint8 data, uint8 devnum);
extern DEVICE i8259_dev; extern DEVICE i8259_dev;
extern uint8 EPROM_get_mbyte(uint16 addr); extern uint8 EPROM_get_mbyte(uint16 addr, uint8 devnum);
extern UNIT EPROM_unit; extern UNIT EPROM_unit[];
extern t_stat EPROM_reset (DEVICE *dptr, uint16 base, uint16 size); extern t_stat EPROM_reset (DEVICE *dptr, uint16 base, uint16 size);
extern uint8 RAM_get_mbyte(uint16 addr); extern uint8 RAM_get_mbyte(uint16 addr);
extern void RAM_put_mbyte(uint16 addr, uint8 val); extern void RAM_put_mbyte(uint16 addr, uint8 val);
@ -87,7 +87,7 @@ extern t_stat i8253_cfg(uint8 base, uint8 devnum);
extern t_stat i8255_cfg(uint8 base, uint8 devnum); extern t_stat i8255_cfg(uint8 base, uint8 devnum);
extern t_stat i8259_cfg(uint8 base, uint8 devnum); extern t_stat i8259_cfg(uint8 base, uint8 devnum);
extern t_stat RAM_cfg(uint16 base, uint16 size); extern t_stat RAM_cfg(uint16 base, uint16 size);
extern t_stat EPROM_cfg(uint16 base, uint16 size); extern t_stat EPROM_cfg(uint16 base, uint16 size, uint8 devnum);
extern t_stat multibus_cfg(); extern t_stat multibus_cfg();
// globals // globals
@ -102,7 +102,7 @@ t_stat SBC_config(void)
i8255_cfg(I8255_BASE_0, 0); i8255_cfg(I8255_BASE_0, 0);
i8255_cfg(I8255_BASE_1, 1); i8255_cfg(I8255_BASE_1, 1);
i8259_cfg(I8259_BASE, 0); i8259_cfg(I8259_BASE, 0);
EPROM_cfg(ROM_BASE, ROM_SIZE); EPROM_cfg(ROM_BASE, ROM_SIZE, 0);
RAM_cfg(RAM_BASE, RAM_SIZE); RAM_cfg(RAM_BASE, RAM_SIZE);
return SCPE_OK; return SCPE_OK;
} }
@ -131,8 +131,8 @@ uint8 get_mbyte(uint16 addr)
{ {
/* if local EPROM handle it */ /* if local EPROM handle it */
if ((ROM_DISABLE && (i8255_C[0] & 0x20)) || (ROM_DISABLE == 0)) { /* EPROM enabled */ if ((ROM_DISABLE && (i8255_C[0] & 0x20)) || (ROM_DISABLE == 0)) { /* EPROM enabled */
if ((addr >= EPROM_unit.u3) && ((uint16)addr <= (EPROM_unit.u3 + EPROM_unit.capac))) { if ((addr >= EPROM_unit->u3) && ((uint16)addr <= (EPROM_unit->u3 + EPROM_unit->capac))) {
return EPROM_get_mbyte(addr); return EPROM_get_mbyte(addr, 0);
} }
} /* if local RAM handle it */ } /* if local RAM handle it */
if ((RAM_DISABLE && (i8255_C[0] & 0x10)) || (RAM_DISABLE == 0)) { /* RAM enabled */ if ((RAM_DISABLE && (i8255_C[0] & 0x10)) || (RAM_DISABLE == 0)) { /* RAM enabled */
@ -160,7 +160,7 @@ void put_mbyte(uint16 addr, uint8 val)
{ {
/* if local EPROM handle it */ /* if local EPROM handle it */
if ((ROM_DISABLE && (i8255_C[0] & 0x20)) || (ROM_DISABLE == 0)) { /* EPROM enabled */ if ((ROM_DISABLE && (i8255_C[0] & 0x20)) || (ROM_DISABLE == 0)) { /* EPROM enabled */
if ((addr >= EPROM_unit.u3) && ((uint16)addr <= (EPROM_unit.u3 + EPROM_unit.capac))) { if ((addr >= EPROM_unit->u3) && ((uint16)addr <= (EPROM_unit->u3 + EPROM_unit->capac))) {
sim_printf("Write to R/O memory address %04X from PC=%04X - ignored\n", addr, PCX); sim_printf("Write to R/O memory address %04X from PC=%04X - ignored\n", addr, PCX);
return; return;
} }

6
Intel-Systems/isys8024/isys8024_sys.c
View file

@ -66,9 +66,15 @@ DEVICE *sim_devices[] = {
&EPROM_dev, &EPROM_dev,
&RAM_dev, &RAM_dev,
&multibus_dev, &multibus_dev,
#if defined (SBC064_NUM) && (SBC064_NUM > 0)
&isbc064_dev, &isbc064_dev,
#endif
#if defined (SBC201_NUM) && (SBC201_NUM > 0)
&isbc201_dev, &isbc201_dev,
#endif
#if defined (SBC202_NUM) && (SBC202_NUM > 0)
&isbc202_dev, &isbc202_dev,
#endif
NULL NULL
}; };

14
Intel-Systems/isys8030/isbc8030.c
View file

@ -63,8 +63,8 @@ extern t_stat i8255_reset (DEVICE *dptr);
extern DEVICE i8255_dev; extern DEVICE i8255_dev;
extern t_stat i8259_reset (DEVICE *dptr); extern t_stat i8259_reset (DEVICE *dptr);
extern DEVICE i8259_dev; extern DEVICE i8259_dev;
extern uint8 EPROM_get_mbyte(uint16 addr); extern uint8 EPROM_get_mbyte(uint16 addr, uint8 devnum);
extern UNIT EPROM_unit; extern UNIT EPROM_unit[];
extern t_stat EPROM_reset (DEVICE *dptr, uint16 base, uint16 size); extern t_stat EPROM_reset (DEVICE *dptr, uint16 base, uint16 size);
extern uint8 RAM_get_mbyte(uint16 addr); extern uint8 RAM_get_mbyte(uint16 addr);
extern void RAM_put_mbyte(uint16 addr, uint8 val); extern void RAM_put_mbyte(uint16 addr, uint8 val);
@ -75,7 +75,7 @@ extern t_stat i8253_cfg(uint8 base, uint8 devnum);
extern t_stat i8255_cfg(uint8 base, uint8 devnum); extern t_stat i8255_cfg(uint8 base, uint8 devnum);
extern t_stat i8259_cfg(uint8 base, uint8 devnum); extern t_stat i8259_cfg(uint8 base, uint8 devnum);
extern t_stat RAM_cfg(uint16 base, uint16 size); extern t_stat RAM_cfg(uint16 base, uint16 size);
extern t_stat EPROM_cfg(uint16 base, uint16 size); extern t_stat EPROM_cfg(uint16 base, uint16 size, uint8 devnum);
extern t_stat multibus_cfg(); extern t_stat multibus_cfg();
// globals // globals
@ -89,7 +89,7 @@ t_stat SBC_config(void)
i8253_cfg(I8253_BASE, 0); i8253_cfg(I8253_BASE, 0);
i8255_cfg(I8255_BASE, 0); i8255_cfg(I8255_BASE, 0);
i8259_cfg(I8259_BASE, 0); i8259_cfg(I8259_BASE, 0);
EPROM_cfg(ROM_BASE, ROM_SIZE); EPROM_cfg(ROM_BASE, ROM_SIZE, 0);
RAM_cfg(RAM_BASE, RAM_SIZE); RAM_cfg(RAM_BASE, RAM_SIZE);
return SCPE_OK; return SCPE_OK;
} }
@ -117,8 +117,8 @@ uint8 get_mbyte(uint16 addr)
{ {
/* if local EPROM handle it */ /* if local EPROM handle it */
if ((ROM_DISABLE && (i8255_C[0] & 0x80)) || (ROM_DISABLE == 0)) { /* EPROM enabled */ if ((ROM_DISABLE && (i8255_C[0] & 0x80)) || (ROM_DISABLE == 0)) { /* EPROM enabled */
if ((addr >= EPROM_unit.u3) && ((uint16)addr <= (EPROM_unit.u3 + EPROM_unit.capac))) { if ((addr >= EPROM_unit->u3) && ((uint16)addr <= (EPROM_unit->u3 + EPROM_unit->capac))) {
return EPROM_get_mbyte(addr); return EPROM_get_mbyte(addr, 0);
} }
} /* if local RAM handle it */ } /* if local RAM handle it */
if ((RAM_DISABLE && (i8255_C[0] & 0x20)) || (RAM_DISABLE == 0)) { /* RAM enabled */ if ((RAM_DISABLE && (i8255_C[0] & 0x20)) || (RAM_DISABLE == 0)) { /* RAM enabled */
@ -146,7 +146,7 @@ void put_mbyte(uint16 addr, uint8 val)
{ {
/* if local EPROM handle it */ /* if local EPROM handle it */
if ((ROM_DISABLE && (i8255_C[0] & 0x80)) || (ROM_DISABLE == 0)) { /* EPROM enabled */ if ((ROM_DISABLE && (i8255_C[0] & 0x80)) || (ROM_DISABLE == 0)) { /* EPROM enabled */
if ((addr >= EPROM_unit.u3) && ((uint16)addr <= (EPROM_unit.u3 + EPROM_unit.capac))) { if ((addr >= EPROM_unit->u3) && ((uint16)addr <= (EPROM_unit->u3 + EPROM_unit->capac))) {
sim_printf("Write to R/O memory address %04X from %04X - ignored\n", addr, PCX); sim_printf("Write to R/O memory address %04X from %04X - ignored\n", addr, PCX);
return; return;
} }

10
Intel-Systems/isys8030/isys8030_sys.c
View file

@ -51,7 +51,7 @@ extern DEVICE isbc064_dev;
sim_stop_messages array of pointers to stop messages sim_stop_messages array of pointers to stop messages
*/ */
char sim_name[] = "Intel System 80/10"; char sim_name[] = "Intel System 80/30";
REG *sim_PC = &i8080_reg[0]; REG *sim_PC = &i8080_reg[0];
@ -66,10 +66,18 @@ DEVICE *sim_devices[] = {
&EPROM_dev, &EPROM_dev,
&RAM_dev, &RAM_dev,
&multibus_dev, &multibus_dev,
#if defined (SBC064_NUM) && (SBC064_NUM > 0)
&isbc064_dev, &isbc064_dev,
#endif
#if defined (SBC201_NUM) && (SBC201_NUM > 0)
&isbc201_dev, &isbc201_dev,
#endif
#if defined (SBC202_NUM) && (SBC202_NUM > 0)
&isbc202_dev, &isbc202_dev,
#endif
#if defined (ZX200A_NUM) && (ZX200A_NUM > 0)
&zx200a_dev, &zx200a_dev,
#endif
NULL NULL
}; };

2
Intel-Systems/isys8030/system_defs.h
View file

@ -33,7 +33,7 @@
#define SET_XACK(VAL) (xack = VAL) #define SET_XACK(VAL) (xack = VAL)
//chip definitions for the iSBC-80/30 //chip definitions for the iSBC-80/30
/* set the base I/O address for the 8253/8254 */ /* set the base I/O address for the 8041/8741 */
#define I8041_BASE 0xDC #define I8041_BASE 0xDC
#define I8041_NUM 1 #define I8041_NUM 1

8
Visual Studio Projects/imds-225.vcproj
View file

@ -231,10 +231,6 @@
RelativePath="..\Intel-Systems\common\ipc.c" RelativePath="..\Intel-Systems\common\ipc.c"
> >
</File> </File>
<File
RelativePath="..\Intel-Systems\common\multibus.c"
>
</File>
<File <File
RelativePath="..\Intel-Systems\common\iram8.c" RelativePath="..\Intel-Systems\common\iram8.c"
> >
@ -256,11 +252,11 @@
> >
</File> </File>
<File <File
RelativePath="..\Intel-Systems\common\isbc208.c" RelativePath="..\Intel-Systems\common\isbc464.c"
> >
</File> </File>
<File <File
RelativePath="..\Intel-Systems\common\isbc464.c" RelativePath="..\Intel-Systems\common\multibus.c"
> >
</File> </File>
<File <File

28
Visual Studio Projects/imds-800.vcproj
View file

@ -208,16 +208,36 @@
RelativePath="..\Intel-Systems\common\i8251.c" RelativePath="..\Intel-Systems\common\i8251.c"
> >
</File> </File>
<File
RelativePath="..\Intel-Systems\common\i8253.c"
>
</File>
<File
RelativePath="..\Intel-Systems\common\i8255.c"
>
</File>
<File
RelativePath="..\Intel-Systems\common\i8259.c"
>
</File>
<File <File
RelativePath="..\Intel-Systems\common\ieprom.c" RelativePath="..\Intel-Systems\common\ieprom.c"
> >
</File> </File>
<File <File
RelativePath="..\Intel-Systems\common\ieprom1.c" RelativePath="..\Intel-Systems\imds-800\imds-800_sys.c"
> >
</File> </File>
<File <File
RelativePath="..\Intel-Systems\imds-800\imds-800_sys.c" RelativePath="..\Intel-Systems\common\ioc-cont.c"
>
</File>
<File
RelativePath="..\Intel-Systems\common\ipc-cont.c"
>
</File>
<File
RelativePath="..\Intel-Systems\common\iram8.c"
> >
</File> </File>
<File <File
@ -245,11 +265,11 @@
> >
</File> </File>
<File <File
RelativePath="..\Intel-Systems\common\multibus.c" RelativePath="..\Intel-Systems\imds-800\monitor.c"
> >
</File> </File>
<File <File
RelativePath="..\Intel-Systems\imds-800\monitor.c" RelativePath="..\Intel-Systems\common\multibus.c"
> >
</File> </File>
<File <File

8
Visual Studio Projects/imds-810.vcproj
View file

@ -212,10 +212,6 @@
RelativePath="..\Intel-Systems\common\ieprom.c" RelativePath="..\Intel-Systems\common\ieprom.c"
> >
</File> </File>
<File
RelativePath="..\Intel-Systems\common\ieprom1.c"
>
</File>
<File <File
RelativePath="..\Intel-Systems\imds-810\imds-810_sys.c" RelativePath="..\Intel-Systems\imds-810\imds-810_sys.c"
> >
@ -245,11 +241,11 @@
> >
</File> </File>
<File <File
RelativePath="..\Intel-Systems\common\multibus.c" RelativePath="..\Intel-Systems\imds-810\monitor.c"
> >
</File> </File>
<File <File
RelativePath="..\Intel-Systems\imds-810\monitor.c" RelativePath="..\Intel-Systems\common\multibus.c"
> >
</File> </File>
<File <File

172
makefile
View file

@ -1718,144 +1718,100 @@ SWTP6800MP-A2 = ${SWTP6800C}/mp-a2.c ${SWTP6800C}/m6800.c ${SWTP6800C}/m6810.c \
SWTP6800_OPT = -I ${SWTP6800D} SWTP6800_OPT = -I ${SWTP6800D}
INTELSYSD = ${SIMHD}/Intel-Systems INTELSYSD = ${SIMHD}/Intel-Systems
INTELSYSC = ${SIMHD}/Intel-Systems/common
INTEL_PARTS = \
${INTELSYSC}/i3214.c \
${INTELSYSC}/i8251.c \
${INTELSYSC}/i8253.c \
${INTELSYSC}/i8255.c \
${INTELSYSC}/i8259.c \
${INTELSYSC}/ieprom.c \
${INTELSYSC}/ioc-cont.c \
${INTELSYSC}/ipc-cont.c \
${INTELSYSC}/iram8.c \
${INTELSYSC}/io.c \
${INTELSYSC}/isbc064.c \
${INTELSYSC}/isbc202.c \
${INTELSYSC}/isbc201.c \
${INTELSYSC}/isbc206.c \
${INTELSYSC}/isbc464.c \
${INTELSYSC}/isbc208.c \
${INTELSYSC}/multibus.c \
${INTELSYSC}/zx200a.c
ISDK80D = ${INTELSYSD}/isdk80
ISDK80 = ${INTELSYSC}/i8080.c ${ISDK80D}/isdk80_sys.c \
${ISDK80D}/isdk80.c ${INTEL_PARTS}
ISDK80_OPT = -I ${ISDK80D}
IDS880D = ${INTELSYSD}/ids880
IDS880 = ${INTELSYSC}/i8080.c ${IDS880D}/ids880_sys.c \
${IDS880D}/ids880.c ${INTEL_PARTS}
IDS880_OPT = -I ${IDS880D}
ISYS8010D = ${INTELSYSD}/isys8010 ISYS8010D = ${INTELSYSD}/isys8010
ISYS8010C = ${INTELSYSD}/common ISYS8010 = ${INTELSYSC}/i8080.c ${ISYS8010D}/isys8010_sys.c \
ISYS8010 = ${ISYS8010C}/i8080.c ${ISYS8010D}/isys8010_sys.c \ ${ISYS8010D}/isbc8010.c ${INTEL_PARTS}
${ISYS8010C}/i8251.c ${ISYS8010C}/i8255.c \
${ISYS8010C}/ieprom.c ${ISYS8010C}/iram8.c \
${ISYS8010C}/multibus.c ${ISYS8010D}/isbc8010.c \
${ISYS8010C}/isbc064.c ${ISYS8010C}/isbc202.c \
${ISYS8010C}/isbc201.c ${ISYS8010C}/zx200a.c \
${ISYS8010C}/isbc206.c ${ISYS8010C}/isbc464.c \
${ISYS8010C}/isbc208.c
ISYS8010_OPT = -I ${ISYS8010D} ISYS8010_OPT = -I ${ISYS8010D}
ISYS8020D = ${INTELSYSD}/isys8020 ISYS8020D = ${INTELSYSD}/isys8020
ISYS8020C = ${INTELSYSD}/common ISYS8020 = ${INTELSYSC}/i8080.c ${ISYS8020D}/isys8020_sys.c \
ISYS8020 = ${ISYS8020C}/i8080.c ${ISYS8020D}/isys8020_sys.c \ ${ISYS8020D}/isbc8020.c ${INTEL_PARTS}
${ISYS8020C}/i8251.c ${ISYS8020C}/i8255.c \
${ISYS8020C}/ieprom.c ${ISYS8020C}/iram8.c \
${ISYS8020C}/multibus.c ${ISYS8020D}/isbc8020.c \
${ISYS8020C}/isbc064.c ${ISYS8020C}/i8259.c \
${ISYS8020C}/isbc202.c ${ISYS8020C}/isbc201.c \
${ISYS8020C}/isbc206.c ${ISYS8020C}/isbc464.c \
${ISYS8020C}/zx200a.c ${ISYS8020C}/i8253.c \
${ISYS8020C}/isbc208.c
ISYS8020_OPT = -I ${ISYS8020D} ISYS8020_OPT = -I ${ISYS8020D}
ISYS8024D = ${INTELSYSD}/isys8024 ISYS8024D = ${INTELSYSD}/isys8024
ISYS8024C = ${INTELSYSD}/common ISYS8024 = ${INTELSYSC}/i8080.c ${ISYS8024D}/isys8024_sys.c \
ISYS8024 = ${ISYS8024C}/i8080.c ${ISYS8024D}/isys8024_sys.c \ ${ISYS8024D}/isbc8024.c ${INTEL_PARTS}
${ISYS8024C}/i8251.c ${ISYS8024C}/i8253.c \
${ISYS8024C}/i8255.c ${ISYS8024C}/i8259.c \
${ISYS8024C}/ieprom.c ${ISYS8024C}/iram8.c \
${ISYS8024C}/multibus.c ${ISYS8024D}/isbc8024.c \
${ISYS8024C}/isbc064.c ${ISYS8024C}/isbc208.c \
${ISYS8024C}/isbc202.c ${ISYS8024C}/isbc201.c \
${ISYS8024C}/isbc206.c ${ISYS8024C}/isbc464.c \
${ISYS8024C}/zx200a.c
ISYS8024_OPT = -I ${ISYS8024D} ISYS8024_OPT = -I ${ISYS8024D}
ISYS8030D = ${INTELSYSD}/isys8030 ISYS8030D = ${INTELSYSD}/isys8030
ISYS8030C = ${INTELSYSD}/common ISYS8030 = ${INTELSYSC}/i8080.c ${ISYS8030D}/isys8030_sys.c \
ISYS8030 = ${ISYS8030C}/i8080.c ${ISYS8030D}/isys8030_sys.c \ ${ISYS8030D}/isbc8030.c ${INTEL_PARTS}
${ISYS8030C}/i8251.c ${ISYS8030C}/i8255.c \
${ISYS8030C}/i8259.c ${ISYS8030C}/i8253.c \
${ISYS8030C}/ieprom.c ${ISYS8030C}/iram8.c \
${ISYS8030C}/multibus.c ${ISYS8030D}/isbc8030.c \
${ISYS8030C}/isbc202.c ${ISYS8030C}/isbc201.c \
${ISYS8030C}/isbc206.c ${ISYS8030C}/isbc464.c \
${ISYS8030C}/isbc064.c ${ISYS8030C}/zx200a.c \
${ISYS8010C}/isbc208.c
ISYS8030_OPT = -I ${ISYS8030D} ISYS8030_OPT = -I ${ISYS8030D}
IMDS210D = ${INTELSYSD}/imds-210 IMDS210D = ${INTELSYSD}/imds-210
IMDS210C = ${INTELSYSD}/common IMDS210 = ${INTELSYSC}/i8080.c ${IMDS210D}/imds-210_sys.c \
IMDS210 = ${IMDS210C}/i8080.c ${IMDS210D}/imds-210_sys.c \ ${INTELSYSC}/ipb.c ${INTEL_PARTS}
${IMDS210C}/i8251.c ${IMDS210C}/i8255.c \
${IMDS210C}/i8259.c ${IMDS210C}/i8253.c \
${IMDS210C}/ieprom.c ${IMDS210C}/iram8.c \
${IMDS210C}/multibus.c ${IMDS210C}/ipb.c \
${IMDS210C}/ipc-cont.c ${IMDS210C}/ioc-cont.c \
${IMDS210C}/isbc202.c ${IMDS210C}/isbc201.c \
${IMDS210C}/isbc206.c ${IMDS210C}/isbc208.c \
${IMDS210C}/isbc464.c ${IMDS210C}/zx200a.c \
${IMDS210C}/isbc064.c
IMDS210_OPT = -I ${IMDS210D} IMDS210_OPT = -I ${IMDS210D}
IMDS220D = ${INTELSYSD}/imds-220 IMDS220D = ${INTELSYSD}/imds-220
IMDS220C = ${INTELSYSD}/common IMDS220 = ${INTELSYSC}/i8080.c ${IMDS220D}/imds-220_sys.c \
IMDS220 = ${IMDS220C}/i8080.c ${IMDS220D}/imds-220_sys.c \ ${INTELSYSC}/ipb.c ${INTEL_PARTS}
${IMDS220C}/i8251.c ${IMDS220C}/i8255.c \
${IMDS220C}/i8259.c ${IMDS220C}/i8253.c \
${IMDS220C}/ieprom.c ${IMDS220C}/iram8.c \
${IMDS220C}/multibus.c ${IMDS220C}/ipb.c \
${IMDS220C}/ipc-cont.c ${IMDS220C}/ioc-cont.c \
${IMDS220C}/isbc202.c ${IMDS220C}/isbc201.c \
${IMDS220C}/isbc206.c ${IMDS210C}/isbc208.c \
${IMDS220C}/isbc464.c ${IMDS220C}/zx200a.c \
${IMDS220C}/isbc064.c
IMDS220_OPT = -I ${IMDS220D} IMDS220_OPT = -I ${IMDS220D}
IMDS225D = ${INTELSYSD}/imds-225 IMDS225D = ${INTELSYSD}/imds-225
IMDS225C = ${INTELSYSD}/common IMDS225 = ${INTELSYSC}/i8080.c ${IMDS225D}/imds-225_sys.c \
IMDS225 = ${IMDS225C}/i8080.c ${IMDS225D}/imds-225_sys.c \ ${INTELSYSC}/ipc.c ${INTEL_PARTS}
${IMDS225C}/i8251.c ${IMDS225C}/i8255.c \
${IMDS225C}/i8259.c ${IMDS225C}/i8253.c \
${IMDS225C}/ieprom.c ${IMDS225C}/iram8.c \
${IMDS225C}/multibus.c ${IMDS225C}/ipc.c \
${IMDS225C}/ipc-cont.c ${IMDS225C}/ioc-cont.c \
${IMDS225C}/isbc202.c ${IMDS225C}/isbc201.c \
${IMDS225C}/zx200a.c ${IMDS225C}/isbc464.c \
${IMDS225C}/isbc206.c ${IMDS225C}/isbc208.c \
${IMDS220C}/isbc064.c
IMDS225_OPT = -I ${IMDS225D} IMDS225_OPT = -I ${IMDS225D}
IMDS230D = ${INTELSYSD}/imds-230 IMDS230D = ${INTELSYSD}/imds-230
IMDS230C = ${INTELSYSD}/common IMDS230 = ${INTELSYSC}/i8080.c ${IMDS230D}/imds-230_sys.c \
IMDS230 = ${IMDS230C}/i8080.c ${IMDS230D}/imds-230_sys.c \ ${INTELSYSC}/ipb.c ${INTEL_PARTS}
${IMDS230C}/i8251.c ${IMDS230C}/i8255.c \
${IMDS230C}/i8259.c ${IMDS230C}/i8253.c \
${IMDS230C}/ieprom.c ${IMDS230C}/iram8.c \
${IMDS230C}/multibus.c ${IMDS230C}/ipb.c \
${IMDS230C}/ipc-cont.c ${IMDS230C}/ioc-cont.c \
${IMDS230C}/isbc202.c ${IMDS230C}/isbc201.c \
${IMDS230C}/isbc206.c ${IMDS230C}/isbc208.c \
${IMDS230C}/isbc464.c ${IMDS230C}/zx200a.c \
${IMDS230C}/isbc064.c
IMDS230_OPT = -I ${IMDS230D} IMDS230_OPT = -I ${IMDS230D}
IMDS800D = ${INTELSYSD}/imds-800 IMDS800D = ${INTELSYSD}/imds-800
IMDS800C = ${INTELSYSD}/common IMDS800 = ${INTELSYSC}/i8080.c ${IMDS800D}/imds-800_sys.c \
IMDS800 = ${IMDS800C}/i8080.c ${IMDS800D}/imds-800_sys.c \
${IMDS800D}/cpu.c ${IMDS800D}/front_panel.c \ ${IMDS800D}/cpu.c ${IMDS800D}/front_panel.c \
${IMDS800D}/monitor.c ${IMDS800C}/ieprom1.c \ ${IMDS800D}/monitor.c ${INTEL_PARTS}
${IMDS800C}/i8251.c ${IMDS800C}/ieprom.c \
${IMDS800C}/multibus.c ${IMDS800C}/isbc064.c \
${IMDS800C}/isbc202.c ${IMDS800C}/isbc201.c \
${IMDS800C}/zx200a.c ${IMDS800C}/isbc464.c \
${IMDS800C}/isbc206.c ${IMDS800C}/i3214.c
IMDS800_OPT = -I ${IMDS800D} IMDS800_OPT = -I ${IMDS800D}
IMDS810D = ${INTELSYSD}/imds-810 IMDS810D = ${INTELSYSD}/imds-810
IMDS810C = ${INTELSYSD}/common IMDS810 = ${INTELSYSC}/i8080.c ${IMDS810D}/imds-810_sys.c \
IMDS810 = ${IMDS800C}/i8080.c ${IMDS810D}/imds-810_sys.c \
${IMDS810D}/cpu.c ${IMDS810D}/front_panel.c \ ${IMDS810D}/cpu.c ${IMDS810D}/front_panel.c \
${IMDS810D}/monitor.c ${IMDS810C}/ieprom1.c \ ${IMDS810D}/monitor.c ${INTEL_PARTS}
${IMDS810C}/i8251.c ${IMDS810C}/ieprom.c \
${IMDS810C}/multibus.c ${IMDS810C}/isbc064.c \
${IMDS810C}/isbc202.c ${IMDS810C}/isbc201.c \
${IMDS810C}/zx200a.c ${IMDS810C}/isbc464.c \
${IMDS810C}/isbc206.c ${IMDS800C}/i3214.c
IMDS810_OPT = -I ${IMDS810D} IMDS810_OPT = -I ${IMDS810D}
@ -2629,6 +2585,24 @@ ifneq (,$(call find_test,${SWTP6800D},swtp6800mp-a2))
$@ $(call find_test,${SWTP6800D},swtp6800mp-a2) ${TEST_ARG} $@ $(call find_test,${SWTP6800D},swtp6800mp-a2) ${TEST_ARG}
endif endif
isdk80: ${BIN}isdk80${EXE}
${BIN}isdk80${EXE} : ${ISDK80} ${SIM} ${BUILD_ROMS}
${MKDIRBIN}
${CC} ${ISDK80} ${SIM} ${ISDK80_OPT} ${CC_OUTSPEC} ${LDFLAGS}
ifneq (,$(call find_test,${ISDK80D},isdk80))
$@ $(call find_test,${ISDK80D},isdk80) ${TEST_ARG}
endif
ids880: ${BIN}ids880${EXE}
${BIN}ids880${EXE} : ${IDS880} ${SIM} ${BUILD_ROMS}
${MKDIRBIN}
${CC} ${IDS880} ${SIM} ${IDS880_OPT} ${CC_OUTSPEC} ${LDFLAGS}
ifneq (,$(call find_test,${IDS880D},ids880))
$@ $(call find_test,${IDS880D},ids880) ${TEST_ARG}
endif
isys8010: ${BIN}isys8010${EXE} isys8010: ${BIN}isys8010${EXE}
${BIN}isys8010${EXE} : ${ISYS8010} ${SIM} ${BUILD_ROMS} ${BIN}isys8010${EXE} : ${ISYS8010} ${SIM} ${BUILD_ROMS}