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Added SHOW CPU MEMORY support for all VAX simulators to display the memory controller and board configuration

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This commit is contained in:
Mark Pizzolato 2013-04-08 12:18:09 -07:00
parent 52838eab05
commit 96dbeae08f
12 changed files with 261 additions and 57 deletions
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2
VAX/vax610_mem.c
View file

@ -139,7 +139,7 @@ int32 i;
while (memsize) { while (memsize) {
for (i=0; boards[i].capacity > memsize; ++i) for (i=0; boards[i].capacity > memsize; ++i)
; ;
fprintf(st, "Memory (0x%08x): %3d %sbytes (%s) - CSR: 0x%08x.\n", baseaddr, boards[i].capacity/((boards[i].capacity >= 1024) ? 1024 : 1), (boards[i].capacity >= 1024) ? "M" : "K", boards[i].option, csraddr); fprintf(st, "Memory (@0x%08x): %3d %sbytes (%s) - CSR: 0x%08x.\n", baseaddr, boards[i].capacity/((boards[i].capacity >= 1024) ? 1024 : 1), (boards[i].capacity >= 1024) ? "M" : "K", boards[i].option, csraddr);
memsize -= boards[i].capacity; memsize -= boards[i].capacity;
baseaddr += boards[i].capacity*1024; baseaddr += boards[i].capacity*1024;
csraddr += (boards[i].capacity/256)*2; csraddr += (boards[i].capacity/256)*2;

15
VAX/vax630_defs.h
View file

@ -98,12 +98,15 @@
#define INITMEMSIZE (1 << 24) /* initial memory size */ #define INITMEMSIZE (1 << 24) /* initial memory size */
#define MEMSIZE (cpu_unit.capac) #define MEMSIZE (cpu_unit.capac)
#define ADDR_IS_MEM(x) (((uint32) (x)) < MEMSIZE) #define ADDR_IS_MEM(x) (((uint32) (x)) < MEMSIZE)
#define MEM_MODIFIERS { UNIT_MSIZE, (1u << 20), NULL, "1M", &cpu_set_size, NULL, NULL, "Set Memory to 1M bytes" }, \ #define MEM_MODIFIERS { UNIT_MSIZE, (1u << 20), NULL, "1M", &cpu_set_size, NULL, NULL, "Set Memory to 1M bytes" }, \
{ UNIT_MSIZE, (1u << 21), NULL, "2M", &cpu_set_size, NULL, NULL, "Set Memory to 2M bytes" }, \ { UNIT_MSIZE, (1u << 21), NULL, "2M", &cpu_set_size, NULL, NULL, "Set Memory to 2M bytes" }, \
{ UNIT_MSIZE, (1u << 22), NULL, "4M", &cpu_set_size, NULL, NULL, "Set Memory to 4M bytes" }, \ { UNIT_MSIZE, (1u << 21) + (1u << 20), NULL, "3M", &cpu_set_size, NULL, NULL, "Set Memory to 3M bytes" }, \
{ UNIT_MSIZE, (1u << 23), NULL, "8M", &cpu_set_size, NULL, NULL, "Set Memory to 8M bytes" }, \ { UNIT_MSIZE, (1u << 22) + (1u << 20), NULL, "5M", &cpu_set_size, NULL, NULL, "Set Memory to 5M bytes" }, \
{ UNIT_MSIZE, (1u << 23) + (1u << 22), NULL, "12M", &cpu_set_size, NULL, NULL, "Set Memory to 12M bytes" }, \ { UNIT_MSIZE, (1u << 23) + (1u << 20), NULL, "9M", &cpu_set_size, NULL, NULL, "Set Memory to 9M bytes" }, \
{ UNIT_MSIZE, (1u << 24), NULL, "16M", &cpu_set_size, NULL, NULL, "Set Memory to 16M bytes" } { UNIT_MSIZE, (1u << 23) + (1u << 22) + (1u << 20), NULL, "13M", &cpu_set_size, NULL, NULL, "Set Memory to 13M bytes" }, \
{ UNIT_MSIZE, (1u << 24), NULL, "16M", &cpu_set_size, NULL, NULL, "Set Memory to 16M bytes" }, \
{ MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, "MEMORY", NULL, NULL, &cpu_show_memory, NULL, "Display memory configuration" }
extern t_stat cpu_show_memory (FILE* st, UNIT* uptr, int32 val, void* desc);
#define CPU_MODEL_MODIFIERS { MTAB_XTD|MTAB_VDV, 0, "MODEL", NULL, \ #define CPU_MODEL_MODIFIERS { MTAB_XTD|MTAB_VDV, 0, "MODEL", NULL, \
NULL, &cpu_show_model, NULL, "Display the simulator CPU Model" }, \ NULL, &cpu_show_model, NULL, "Display the simulator CPU Model" }, \
{ MTAB_XTD|MTAB_VDV, 0, "DIAG", "DIAG={FULL|MIN}", \ { MTAB_XTD|MTAB_VDV, 0, "DIAG", "DIAG={FULL|MIN}", \

29
VAX/vax630_sysdev.c
View file

@ -979,3 +979,32 @@ fprintf (st, "The simulator is booted with the BOOT command:\n\n");
fprintf (st, " sim> BOOT\n\n"); fprintf (st, " sim> BOOT\n\n");
return SCPE_OK; return SCPE_OK;
} }
t_stat cpu_show_memory (FILE* st, UNIT* uptr, int32 val, void* desc)
{
uint32 memsize = (uint32)(MEMSIZE>>20);
uint32 baseaddr = 0;
struct {
uint32 capacity;
char *option;
} boards[] = {
{ 16, "MS630-CA"},
{ 4, "MS630-BB"},
{ 2, "MS630-BA"},
{ 1, "MS630-AA"},
{ 0, NULL}};
int32 i;
while (memsize > 1) {
for (i=0; boards[i].capacity > memsize; ++i)
;
if (memsize == 2)
i = 3;
fprintf(st, "Memory (@0x%08x): %3d Mbytes (%s)\n", baseaddr, boards[i].capacity, boards[i].option);
memsize -= boards[i].capacity;
baseaddr += boards[i].capacity<<20;
}
if (memsize)
fprintf(st, "Memory (0x%08x): 1 Mbytes (On-Board)\n", baseaddr);
return SCPE_OK;
}

4
VAX/vax730_defs.h
View file

@ -129,7 +129,9 @@
{ UNIT_MSIZE, (2u << 20), NULL, "2M", &cpu_set_size, NULL, NULL, "Set Memory to 2M bytes" }, \ { UNIT_MSIZE, (2u << 20), NULL, "2M", &cpu_set_size, NULL, NULL, "Set Memory to 2M bytes" }, \
{ UNIT_MSIZE, (3u << 20), NULL, "2M", &cpu_set_size, NULL, NULL, "Set Memory to 3M bytes" }, \ { UNIT_MSIZE, (3u << 20), NULL, "2M", &cpu_set_size, NULL, NULL, "Set Memory to 3M bytes" }, \
{ UNIT_MSIZE, (4u << 20), NULL, "4M", &cpu_set_size, NULL, NULL, "Set Memory to 4M bytes" }, \ { UNIT_MSIZE, (4u << 20), NULL, "4M", &cpu_set_size, NULL, NULL, "Set Memory to 4M bytes" }, \
{ UNIT_MSIZE, (5u << 20), NULL, "5M", &cpu_set_size, NULL, NULL, "Set Memory to 5M bytes" } { UNIT_MSIZE, (5u << 20), NULL, "5M", &cpu_set_size, NULL, NULL, "Set Memory to 5M bytes" }, \
{ MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, "MEMORY", NULL, NULL, &cpu_show_memory, NULL, "Display memory configuration" }
extern t_stat cpu_show_memory (FILE* st, UNIT* uptr, int32 val, void* desc);
#define CPU_MODEL_MODIFIERS \ #define CPU_MODEL_MODIFIERS \
{ MTAB_XTD|MTAB_VDV, 0, "MODEL", NULL, \ { MTAB_XTD|MTAB_VDV, 0, "MODEL", NULL, \
NULL, &cpu_show_model, NULL, "Display the simulator CPU Model" } NULL, &cpu_show_model, NULL, "Display the simulator CPU Model" }

29
VAX/vax730_mem.c
View file

@ -188,11 +188,7 @@ t_stat mctl_reset (DEVICE *dptr)
{ {
mcsr0 = 0; mcsr0 = 0;
mcsr1 = 0; mcsr1 = 0;
mcsr2 = 0; mcsr2 = MEM_BOARD_MASK(MEMSIZE, MEM_SIZE_64K) | MCSR2_CS; /* Use 64k chips */
if (MEMSIZE > MAXMEMSIZE) /* More than 2MB? */
mcsr2 = mcsr2 | MEM_BOARD_MASK(MEMSIZE, MEM_SIZE_64K) | MCSR2_CS; /* Use 64k chips */
else
mcsr2 = mcsr2 | MEM_BOARD_MASK(MEMSIZE, MEM_SIZE_16K); /* Use 16k chips */
return SCPE_OK; return SCPE_OK;
} }
@ -200,3 +196,26 @@ char *mctl_description (DEVICE *dptr)
{ {
return "memory controller"; return "memory controller";
} }
t_stat cpu_show_memory (FILE* st, UNIT* uptr, int32 val, void* desc)
{
uint32 memsize = (uint32)(MEMSIZE>>20);
uint32 baseaddr = 0;
uint32 slot = 6;
struct {
uint32 capacity;
char *option;
} boards[] = {
{ 1, "MS730-CA M8750"},
{ 0, NULL}};
int32 bd;
while (memsize) {
bd = 0;
fprintf(st, "Memory slot %d (@0x%08x): %3d Mbytes (%s)\n", slot, baseaddr, boards[bd].capacity, boards[bd].option);
memsize -= boards[bd].capacity;
baseaddr += boards[bd].capacity<<20;
++slot;
}
return SCPE_OK;
}

19
VAX/vax750_defs.h
View file

@ -141,15 +141,22 @@
#define MAXMEMWIDTH 21 /* max mem, 16k chips */ #define MAXMEMWIDTH 21 /* max mem, 16k chips */
#define MAXMEMSIZE (1 << MAXMEMWIDTH) #define MAXMEMSIZE (1 << MAXMEMWIDTH)
#define MAXMEMWIDTH_X 23 /* max mem, 64k chips */ #define MAXMEMWIDTH_Y 23 /* max mem, 64k chips */
#define MAXMEMSIZE_X (1 << MAXMEMWIDTH_X) #define MAXMEMSIZE_Y (1 << MAXMEMWIDTH_Y)
#define MAXMEMWIDTH_X 24 /* max mem, 256k chips */
#define MAXMEMSIZE_X ((1 << MAXMEMWIDTH_X) - (1 << 20)) /* 15M Max before interfering with Register Space */
#define INITMEMSIZE (1 << MAXMEMWIDTH) /* initial memory size */ #define INITMEMSIZE (1 << MAXMEMWIDTH) /* initial memory size */
#define MEMSIZE (cpu_unit.capac) #define MEMSIZE (cpu_unit.capac)
#define ADDR_IS_MEM(x) (((uint32) (x)) < MEMSIZE) #define ADDR_IS_MEM(x) (((uint32) (x)) < MEMSIZE)
#define MEM_MODIFIERS { UNIT_MSIZE, (1u << 20), NULL, "1M", &cpu_set_size, NULL, NULL, "Set Memory to 1M bytes" }, \ #define MEM_MODIFIERS { UNIT_MSIZE, (1u << 20), NULL, "1M", &cpu_set_size, NULL, NULL, "Set Memory to 1M bytes" }, \
{ UNIT_MSIZE, (1u << 21), NULL, "2M", &cpu_set_size, NULL, NULL, "Set Memory to 2M bytes" }, \ { UNIT_MSIZE, (1u << 21), NULL, "2M", &cpu_set_size, NULL, NULL, "Set Memory to 2M bytes" }, \
{ UNIT_MSIZE, (1u << 22), NULL, "4M", &cpu_set_size, NULL, NULL, "Set Memory to 4M bytes" }, \ { UNIT_MSIZE, (1u << 22), NULL, "4M", &cpu_set_size, NULL, NULL, "Set Memory to 4M bytes" }, \
{ UNIT_MSIZE, (1u << 23), NULL, "8M", &cpu_set_size, NULL, NULL, "Set Memory to 8M bytes" } { UNIT_MSIZE, (1u << 23), NULL, "8M", &cpu_set_size, NULL, NULL, "Set Memory to 8M bytes" }, \
{ UNIT_MSIZE, (1u << 23) + (1u << 22), NULL, "12M", &cpu_set_size, NULL, NULL, "Set Memory to 12M bytes" }, \
{ UNIT_MSIZE, (1u << 23) + (6u << 20), NULL, "14M", &cpu_set_size, NULL, NULL, "Set Memory to 14M bytes" }, \
{ UNIT_MSIZE, (1u << 23) + (7u << 20), NULL, "15M", &cpu_set_size, NULL, NULL, "Set Memory to 15M bytes" }, \
{ MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, "MEMORY", NULL, NULL, &cpu_show_memory, NULL, "Display memory configuration" }
extern t_stat cpu_show_memory (FILE* st, UNIT* uptr, int32 val, void* desc);
#define CPU_MODEL_MODIFIERS \ #define CPU_MODEL_MODIFIERS \
{ MTAB_XTD|MTAB_VDV, 0, "MODEL", NULL, \ { MTAB_XTD|MTAB_VDV, 0, "MODEL", NULL, \
NULL, &cpu_show_model, NULL, "Display the simulator CPU Model" } NULL, &cpu_show_model, NULL, "Display the simulator CPU Model" }

90
VAX/vax750_mem.c
View file

@ -63,19 +63,24 @@
#define MCSR2_INIT 0x00010000 /* Cold/warm restart flag */ #define MCSR2_INIT 0x00010000 /* Cold/warm restart flag */
#define MCSR2_V_SA 17 #define MCSR2_V_SA 17
#define MCSR2_M_SA 0x7F /* Start address */ #define MCSR2_M_SA 0x7F /* Start address */
#define MCSR2_V_CS 24 #define MCSR2_V_CS64 24
#define MCSR2_CS (1u << MCSR2_V_CS) /* Chip size */ #define MCSR2_CS64 (1u << MCSR2_V_CS64) /* Chip size */
#define MCSR2_MBZ 0xFF000000 #define MCSR2_V_CS256 25
#define MCSR2_CS256 (1u << MCSR2_V_CS256) /* Chip size */
#define MCSR2_MBZ 0xFC000000
/* Debug switches */ /* Debug switches */
#define MCTL_DEB_RRD 0x01 /* reg reads */ #define MCTL_DEB_RRD 0x01 /* reg reads */
#define MCTL_DEB_RWR 0x02 /* reg writes */ #define MCTL_DEB_RWR 0x02 /* reg writes */
#define MEM_SIZE_16K (1u << 17) /* Board size (16k chips) */ #define MEM_SIZE_16K (1u << 18) /* Board size (16k chips) */
#define MEM_SIZE_64K (1u << 19) /* Board size (64k chips) */ #define MEM_SIZE_64K (1u << 20) /* Board size (64k chips) */
#define MEM_BOARD_MASK(x,y) ((1u << (uint32)(x/y)) - 1) #define MEM_SIZE_256K (1u << 22) /* Board size (256k chips) */
#define MEM_64K_MASK 0x5555 #define MEM_64K_MASK 0x5555
#define MEM_BOARD_MASK_64K(x) ((((1u << (uint32)(x/MEM_SIZE_64K)) - 1) & MEM_64K_MASK) | MCSR2_CS64)
#define MEM_256K_MASK 0x5555
#define MEM_BOARD_MASK_256K(x) ((((1u << (uint32)(x/MEM_SIZE_256K)) - 1) & MEM_256K_MASK) | MCSR2_CS256)
extern UNIT cpu_unit; extern UNIT cpu_unit;
@ -100,6 +105,9 @@ DIB mctl_dib = { TR_MCTL, 0, &mctl_rdreg, &mctl_wrreg, 0 };
UNIT mctl_unit = { UDATA (NULL, 0, 0) }; UNIT mctl_unit = { UDATA (NULL, 0, 0) };
REG mctl_reg[] = { REG mctl_reg[] = {
{ HRDATAD (CSR0, mcsr0, 32, "ECC syndrome bits") },
{ HRDATAD (CSR1, mcsr1, 32, "CPU error control/check bits") },
{ HRDATAD (CSR2, mcsr2, 32, "Memory Configuration") },
{ NULL } { NULL }
}; };
@ -198,12 +206,24 @@ return;
t_stat mctl_reset (DEVICE *dptr) t_stat mctl_reset (DEVICE *dptr)
{ {
uint32 large_slot_size = MEM_SIZE_16K, large_slots;
uint32 small_slot_size, small_slots;
uint32 boards, board_mask;
mcsr0 = 0; mcsr0 = 0;
mcsr1 = 0; mcsr1 = 0;
if (MEMSIZE > MAXMEMSIZE) /* More than 2MB? */ if (MEMSIZE > MAXMEMSIZE_Y) /* More than 8MB? */
mcsr2 = MCSR2_INIT | (MEM_BOARD_MASK(MEMSIZE, MEM_SIZE_64K) & MEM_64K_MASK) | MCSR2_CS; /* Use 64k chips */ large_slot_size = MEM_SIZE_256K; /* Use 256k chips */
else else {
mcsr2 = MCSR2_INIT | MEM_BOARD_MASK(MEMSIZE, MEM_SIZE_16K); /* Use 16k chips */ if (MEMSIZE > MAXMEMSIZE)
large_slot_size = MEM_SIZE_64K;
}
small_slot_size = large_slot_size >> 2;
large_slots = (uint32)(MEMSIZE/large_slot_size);
small_slots = (MEMSIZE & (large_slot_size -1))/small_slot_size;
boards = ((1u << ((large_slots + small_slots) << 1)) - 1);
board_mask = (((large_slot_size == MEM_SIZE_16K)? 0xFFFF : 0x5555) & (((1u << (large_slots << 1)) - 1))) | (((large_slot_size == MEM_SIZE_256K) ? 0xAAAA : 0xFFFF) << (large_slots << 1));
mcsr2 = MCSR2_INIT | (boards & board_mask) | ((large_slot_size == MEM_SIZE_256K) ? MCSR2_CS256 : 0); /* Use 256k chips */
return SCPE_OK; return SCPE_OK;
} }
@ -211,3 +231,53 @@ char *mctl_description (DEVICE *dptr)
{ {
return "Memory controller"; return "Memory controller";
} }
t_stat cpu_show_memory (FILE* st, UNIT* uptr, int32 val, void* desc)
{
uint32 memsize = (uint32)(MEMSIZE>>10);
uint32 baseaddr = 0;
struct {
uint32 capacity;
char *option;
} boards[] = {
{ 4096, "MS750-JD M7199"},
{ 1024, "MS750-CA M8750"},
{ 256, "MS750-AA M8728"},
{ 0, NULL}};
int32 i, bd;
for (i=0; i<8; i++) {
if (mcsr2&MCSR2_CS256) {
switch ((mcsr2&(3<<(i*2)))>>(i*2)) {
case 0:
case 3:
bd = 3; /* Not Present */
break;
case 2:
bd = 1; /* 64Kb chips */
break;
case 1:
bd = 0; /* 256Kb chips */
break;
}
}
else {
switch ((mcsr2&(3<<(i*2)))>>(i*2)) {
case 0:
bd = 3; /* Not Present */
break;
case 3:
bd = 2; /* 16Kb chips */
break;
case 1:
case 2:
bd = 1; /* 64Kb chips */
break;
}
}
if (boards[bd].capacity)
fprintf(st, "Memory slot %d (@0x%08x): %3d %sbytes (%s)\n", 11+i, baseaddr, boards[bd].capacity/((boards[bd].capacity>=1024) ? 1024 : 1), (boards[bd].capacity>=1024) ? "M" : "K", boards[bd].option);
baseaddr += boards[bd].capacity<<10;
}
return SCPE_OK;
}

9
VAX/vax780_defs.h
View file

@ -157,12 +157,17 @@
#define INITMEMSIZE (1 << MAXMEMWIDTH) /* initial memory size */ #define INITMEMSIZE (1 << MAXMEMWIDTH) /* initial memory size */
#define MEMSIZE (cpu_unit.capac) #define MEMSIZE (cpu_unit.capac)
#define ADDR_IS_MEM(x) (((uint32) (x)) < MEMSIZE) #define ADDR_IS_MEM(x) (((uint32) (x)) < MEMSIZE)
#define MEM_MODIFIERS { UNIT_MSIZE, (1u << 23), NULL, "8M", &cpu_set_size, NULL, NULL, "Set Memory to 8M bytes" }, \ #define MEM_MODIFIERS { UNIT_MSIZE, (1u << 20), NULL, "1M", &cpu_set_size, NULL, NULL, "Set Memory to 1M bytes" }, \
{ UNIT_MSIZE, (1u << 21), NULL, "2M", &cpu_set_size, NULL, NULL, "Set Memory to 2M bytes" }, \
{ UNIT_MSIZE, (1u << 22), NULL, "4M", &cpu_set_size, NULL, NULL, "Set Memory to 4M bytes" }, \
{ UNIT_MSIZE, (1u << 23), NULL, "8M", &cpu_set_size, NULL, NULL, "Set Memory to 8M bytes" }, \
{ UNIT_MSIZE, (1u << 24), NULL, "16M", &cpu_set_size, NULL, NULL, "Set Memory to 16M bytes" }, \ { UNIT_MSIZE, (1u << 24), NULL, "16M", &cpu_set_size, NULL, NULL, "Set Memory to 16M bytes" }, \
{ UNIT_MSIZE, (1u << 25), NULL, "32M", &cpu_set_size, NULL, NULL, "Set Memory to 32M bytes" }, \ { UNIT_MSIZE, (1u << 25), NULL, "32M", &cpu_set_size, NULL, NULL, "Set Memory to 32M bytes" }, \
{ UNIT_MSIZE, (1u << 25) + (1u << 24), NULL, "48M", &cpu_set_size, NULL, NULL, "Set Memory to 48M bytes" }, \ { UNIT_MSIZE, (1u << 25) + (1u << 24), NULL, "48M", &cpu_set_size, NULL, NULL, "Set Memory to 48M bytes" }, \
{ UNIT_MSIZE, (1u << 26), NULL, "64M", &cpu_set_size, NULL, NULL, "Set Memory to 64M bytes" }, \ { UNIT_MSIZE, (1u << 26), NULL, "64M", &cpu_set_size, NULL, NULL, "Set Memory to 64M bytes" }, \
{ UNIT_MSIZE, (1u << 27), NULL, "128M", &cpu_set_size, NULL, NULL, "Set Memory to 128M bytes" } { UNIT_MSIZE, (1u << 27), NULL, "128M", &cpu_set_size, NULL, NULL, "Set Memory to 128M bytes" }, \
{ MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, "MEMORY", NULL, NULL, &cpu_show_memory, NULL, "Display memory configuration" }
extern t_stat cpu_show_memory (FILE* st, UNIT* uptr, int32 val, void* desc);
#define CPU_MODEL_MODIFIERS \ #define CPU_MODEL_MODIFIERS \
{ MTAB_XTD|MTAB_VDV, 0, "MODEL", NULL, \ { MTAB_XTD|MTAB_VDV, 0, "MODEL", NULL, \
NULL, &cpu_show_model, NULL, "Display the simulator CPU Model" } NULL, &cpu_show_model, NULL, "Display the simulator CPU Model" }

85
VAX/vax780_mem.c
View file

@ -32,17 +32,20 @@
/* Memory controller register A */ /* Memory controller register A */
#define MCRA_OF 0x0 #define MCRA_OF 0x0
#define MCRA_SUMM 0x00100000 /* err summ (MS780E) */ #define MCRA_SUMM 0x00100000 /* err summ (MS780E) */
#define MCRA_C_SIZE 0x00007E00 /* array size - fixed */ #define MCRA_M_SIZE 0x00007E00 /* array size - field */
#define MCRA_V_SIZE 9 #define MCRA_V_SIZE 9
#define MCRA_ILVE 0x00000100 /* interleave wr enab */ #define MCRA_ILVE 0x00000100 /* interleave wr enab */
#define MCRA_TYPE 0x000000F8 /* type */ #define MCRA_M_TYPE 0x000000F8 /* type */
#define MCRA_C_TYPE 0x00000010 /* 16k uninterleaved */ #define MCRA_C_TYPE_16K 0x00000010 /* 16k uninterleaved (256kb arrays) */
#define MCRA_E_TYPE 0x0000006A /* 256k upper + lower */ #define MCRA_C_TYPE_4K 0x00000008 /* 4k uninterleaved (64kb arrays) */
#define MCRA_ILV 0x00000007 /* interleave */ #define MCRA_E_TYPE_256K 0x00000070 /* 256k uninterleaved (4096kb arrays) */
#define MCRA_RD (0x00107FFF|SBI_FAULTS) #define MCRA_E_TYPE_64K 0x00000068 /* 64k uninterleaved (1024kb arrays) */
#define MCRA_WR 0x00000100 #define MCRA_E_TYPE 0x0000006A /* 256k upper + lower */
#define MCRA_ILV 0x00000007 /* interleave */
#define MCRA_RD (0x00107FFF|SBI_FAULTS)
#define MCRA_WR 0x00000100
/* Memory controller register B */ /* Memory controller register B */
@ -263,19 +266,17 @@ return;
t_stat mctl_reset (DEVICE *dptr) t_stat mctl_reset (DEVICE *dptr)
{ {
int32 i, amb; int32 i, amb, akb;
t_bool extmem = MEMSIZE > MAXMEMSIZE; t_bool extmem = MEMSIZE > MAXMEMSIZE;
amb = (int32) (MEMSIZE / 2) >> 20; /* array size MB */ amb = (int32) (MEMSIZE / MCTL_NUM) >> 20; /* array size MB */
for (i = 0; i < MCTL_NUM; i++) { /* init for MS780C */ akb = (int32) (MEMSIZE / MCTL_NUM) >> 10; /* array size KB */
if (extmem) { /* extended memory? */ for (i = 0; i < MCTL_NUM; i++) {
mcr_a[i] = ((amb - 1) << MCRA_V_SIZE) | MCRA_E_TYPE; if (extmem) /* Need MS780E? */
mcr_b[i] = MCRB_INIT | ((i * amb) << (MCRB_V_SA + 4)); mcr_a[i] = ((amb - 1) << MCRA_V_SIZE) | ((amb <= 16) ? MCRA_E_TYPE_64K : MCRA_E_TYPE_256K);
} else /* Use MS780C */
else { mcr_a[i] = (((akb >> 6) - 1) << MCRA_V_SIZE) | ((akb <= 1024) ? MCRA_C_TYPE_4K : MCRA_C_TYPE_16K);
mcr_a[i] = MCRA_C_SIZE | MCRA_C_TYPE; mcr_b[i] = MCRB_INIT | ((i * akb) << (MCRB_V_SA - 6));
mcr_b[i] = MCRB_INIT | (i << 21);
}
mcr_c[i] = 0; mcr_c[i] = 0;
mcr_d[i] = 0; mcr_d[i] = 0;
} }
@ -289,3 +290,43 @@ static char buf[64];
sprintf (buf, "Memory controller %d", (int)(dptr-mctl_dev)); sprintf (buf, "Memory controller %d", (int)(dptr-mctl_dev));
return buf; return buf;
} }
t_stat cpu_show_memory (FILE* st, UNIT* uptr, int32 val, void* desc)
{
struct {
uint32 capacity;
char *option;
} boards[] = {
{ 4096, "MS780-JD M8374 array"},
{ 1024, "MS780-FD M8373 array"},
{ 256, "MS780-C M8210 array"},
{ 64, "MS780-C M8211 array"},
{ 0, NULL}};
uint32 i, slot, bd;
for (i = 0; i < MCTL_NUM; i++) {
uint32 baseaddr = ((mcr_b[i] & MCRB_SA) << 1);
fprintf (st, "Memory Controller %d - MS780-%s\n", i, ((mcr_a[i]&MCRA_M_TYPE) >> 5) ? "E" : "C");
switch (mcr_a[i]&MCRA_M_TYPE) {
case MCRA_C_TYPE_4K:
bd = 3; /* 4kbit chips, 64Kbyte arrays */
break;
case MCRA_C_TYPE_16K:
bd = 2; /* 16kbit chips, 256Kbyte arrays */
break;
case MCRA_E_TYPE_64K:
bd = 1; /* 64kbit chips, 1Mbyte arrays */
break;
case MCRA_E_TYPE_256K:
bd = 0; /* 256kbit chips, 4Mbyte arrays */
break;
}
for (slot=0; slot<=((mcr_a[i]&MCRA_M_SIZE)>>MCRA_V_SIZE); slot += ((mcr_a[i]&MCRA_C_TYPE_4K)? 1 : 4)) {
if (boards[bd].capacity)
fprintf(st, "Memory slot %d (@0x%08x): %3d %sbytes (%s)\n", slot, baseaddr, boards[bd].capacity/((boards[bd].capacity>=1024) ? 1024 : 1), (boards[bd].capacity>=1024) ? "M" : "K", boards[bd].option);
baseaddr += boards[bd].capacity<<10;
}
}
return SCPE_OK;
}

2
VAX/vax860_abus.c
View file

@ -258,7 +258,7 @@ struct {
{ 4, "MS86-B"}, { 4, "MS86-B"},
{ 16, "MS86-C"}, { 16, "MS86-C"},
{ 64, "MS86-D"}, { 64, "MS86-D"},
{256, "MS86-E"}, /* Fake 256MB board which never existed */ {256, "MS86-E (board never existed)"}, /* Fake 256MB board */
{ 0, NULL}}; { 0, NULL}};
int32 i, j; int32 i, j;

27
VAX/vax_sysdev.c
View file

@ -30,6 +30,7 @@
nvr non-volatile ROM (no registers) nvr non-volatile ROM (no registers)
csi console storage input csi console storage input
cso console storage output cso console storage output
cmctl memory controller
sysd system devices (SSC miscellany) sysd system devices (SSC miscellany)
23-Dec-10 RMS Added power clear call to boot routine (Mark Pizzolato) 23-Dec-10 RMS Added power clear call to boot routine (Mark Pizzolato)
@ -1143,6 +1144,32 @@ switch (rg) {
return; return;
} }
t_stat cpu_show_memory (FILE* st, UNIT* uptr, int32 val, void* desc)
{
uint32 memsize = (uint32)(MEMSIZE>>20);
uint32 baseaddr = 0;
struct {
uint32 capacity;
char *option;
} boards[] = {
{ 16, "MS650-BA"},
{ 0, NULL}};
int32 i;
while (memsize > 1) {
if (baseaddr >= (64<<20)) {
fprintf(st, "Memory (@0x%08x): %3d Mbytes (Simulated Extended Memory)\n", baseaddr, memsize);
break;
}
for (i=0; boards[i].capacity > memsize; ++i)
;
fprintf(st, "Memory (@0x%08x): %3d Mbytes (%s)\n", baseaddr, boards[i].capacity, boards[i].option);
memsize -= boards[i].capacity;
baseaddr += boards[i].capacity<<20;
}
return SCPE_OK;
}
/* KA655 registers */ /* KA655 registers */
int32 ka_rd (int32 pa) int32 ka_rd (int32 pa)

7
VAX/vaxmod_defs.h
View file

@ -118,14 +118,15 @@
#define INITMEMSIZE (1 << 24) /* initial memory size */ #define INITMEMSIZE (1 << 24) /* initial memory size */
#define MEMSIZE (cpu_unit.capac) #define MEMSIZE (cpu_unit.capac)
#define ADDR_IS_MEM(x) (((uint32) (x)) < MEMSIZE) #define ADDR_IS_MEM(x) (((uint32) (x)) < MEMSIZE)
#define MEM_MODIFIERS { UNIT_MSIZE, (1u << 23), NULL, "8M", &cpu_set_size, NULL, NULL, "Set Memory to 8M bytes" }, \ #define MEM_MODIFIERS { UNIT_MSIZE, (1u << 24), NULL, "16M", &cpu_set_size, NULL, NULL, "Set Memory to 16M bytes" }, \
{ UNIT_MSIZE, (1u << 24), NULL, "16M", &cpu_set_size, NULL, NULL, "Set Memory to 16M bytes" }, \
{ UNIT_MSIZE, (1u << 25), NULL, "32M", &cpu_set_size, NULL, NULL, "Set Memory to 32M bytes" }, \ { UNIT_MSIZE, (1u << 25), NULL, "32M", &cpu_set_size, NULL, NULL, "Set Memory to 32M bytes" }, \
{ UNIT_MSIZE, (1u << 25) + (1u << 24), NULL, "48M", &cpu_set_size, NULL, NULL, "Set Memory to 48M bytes" }, \ { UNIT_MSIZE, (1u << 25) + (1u << 24), NULL, "48M", &cpu_set_size, NULL, NULL, "Set Memory to 48M bytes" }, \
{ UNIT_MSIZE, (1u << 26), NULL, "64M", &cpu_set_size, NULL, NULL, "Set Memory to 64M bytes" }, \ { UNIT_MSIZE, (1u << 26), NULL, "64M", &cpu_set_size, NULL, NULL, "Set Memory to 64M bytes" }, \
{ UNIT_MSIZE, (1u << 27), NULL, "128M", &cpu_set_size, NULL, NULL, "Set Memory to 128M bytes" }, \ { UNIT_MSIZE, (1u << 27), NULL, "128M", &cpu_set_size, NULL, NULL, "Set Memory to 128M bytes" }, \
{ UNIT_MSIZE, (1u << 28), NULL, "256M", &cpu_set_size, NULL, NULL, "Set Memory to 256M bytes" }, \ { UNIT_MSIZE, (1u << 28), NULL, "256M", &cpu_set_size, NULL, NULL, "Set Memory to 256M bytes" }, \
{ UNIT_MSIZE, (1u << 29), NULL, "512M", &cpu_set_size, NULL, NULL, "Set Memory to 512M bytes" } { UNIT_MSIZE, (1u << 29), NULL, "512M", &cpu_set_size, NULL, NULL, "Set Memory to 512M bytes" }, \
{ MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, "MEMORY", NULL, NULL, &cpu_show_memory, NULL, "Display memory configuration" }
extern t_stat cpu_show_memory (FILE* st, UNIT* uptr, int32 val, void* desc);
#define CPU_MODEL_MODIFIERS { MTAB_XTD|MTAB_VDV, 0, "MODEL", "MODEL={VAXServer|MicroVAX}", \ #define CPU_MODEL_MODIFIERS { MTAB_XTD|MTAB_VDV, 0, "MODEL", "MODEL={VAXServer|MicroVAX}", \
&cpu_set_model, &cpu_show_model, NULL, "Set/Display processor model" }, \ &cpu_set_model, &cpu_show_model, NULL, "Set/Display processor model" }, \
{ MTAB_XTD|MTAB_VDV, 0, "AUTOBOOT", "AUTOBOOT", \ { MTAB_XTD|MTAB_VDV, 0, "AUTOBOOT", "AUTOBOOT", \